diff --git a/transpile_python/service.go b/transpile_python/service.go index 74e19ca..c930418 100644 --- a/transpile_python/service.go +++ b/transpile_python/service.go @@ -253,8 +253,6 @@ func handleFuncDecl(decl ast.Decl) string { } code += "def " name := "" - code += handleFuncDeclType(fd.Type) - code += "" name = handleFuncDeclName(fd.Name) if name == "NewController" { return "" @@ -314,7 +312,7 @@ func handleFuncDeclParams(t *ast.FuncType) string { ftype = handleIdent(ft) } for _, names := range field.Names { - values = append(values, ftype+""+names.Name) + values = append(values, names.Name) } } code += strings.Join(values, ",") diff --git a/transpile_python/service_test.go b/transpile_python/service_test.go index e75ede5..50c544a 100644 --- a/transpile_python/service_test.go +++ b/transpile_python/service_test.go @@ -376,6 +376,48 @@ def vdiv(inp,outp,param): def main(): v = vdiv(inp,outp,"500") main() +` + Compare(source, expected) + }) + + It("Interfaces", func() { + source := `package test + //@subcircuit + func mem_module(intfc any) { + ram := Part("Memory_RAM", "AS6C1616") + ram["A[0:19]"] += intfc.addr + ram["DQ[0:15]"] += intfc.data + ram["WE#"] += intfc.wr + ram["OE#"] += intfc["rd"] + } + + func main() { + rd := Net("MEM_RD#") + wr := Net("MEM_WR#") + addr := Bus("MEM_ADDR", 20) + data := Bus("MEM_DATA", 16) + mem_intfc = Interface(rd, wr, addr, data) + mem_module(mem_intfc) + uc_module(clk, mem_intfc, io_intfc) + } + ` + expected := `from skidl import * +@subcircuit +def mem_module(intfc): + ram = Part("Memory_RAM","AS6C1616") + ram["A[0:19]"] += intfc.addr + ram["DQ[0:15]"] += intfc.data + ram["WE#"] += intfc.wr + ram["OE#"] += intfc["rd"] +def main(): + rd = Net("MEM_RD#") + wr = Net("MEM_WR#") + addr = Bus("MEM_ADDR",20) + data = Bus("MEM_DATA",16) + mem_intfc = Interface(rd,wr,addr,data) + mem_module(mem_intfc) + uc_module(clk,mem_intfc,io_intfc) +main() ` Compare(source, expected) })