add support for esp32c3 to receive UART data
Этот коммит содержится в:
Dmitriy
Ron Evans
родитель
1dcdd5f2d2
коммит
0dd521e1d1
1 изменённых файлов: 257 добавлений и 4 удалений
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@ -5,6 +5,8 @@ package machine
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import (
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"device/esp"
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"device/riscv"
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"errors"
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"runtime/interrupt"
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"runtime/volatile"
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"sync"
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@ -214,18 +216,269 @@ func setupPinInterrupt() error {
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}).Enable()
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}
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var DefaultUART = UART0
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var (
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DefaultUART = UART0
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UART0 = &_UART0
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_UART0 = UART{Bus: esp.UART0, Buffer: NewRingBuffer()}
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UART1 = &_UART1
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_UART1 = UART{Bus: esp.UART1, Buffer: NewRingBuffer()}
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onceUart = sync.Once{}
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errSamePins = errors.New("UART: invalid pin combination")
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errWrongUART = errors.New("UART: unsupported UARTn")
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errWrongBitSize = errors.New("UART: invalid data size")
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errWrongStopBitSize = errors.New("UART: invalid bit size")
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)
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type UART struct {
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Bus *esp.UART_Type
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Buffer *RingBuffer
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Bus *esp.UART_Type
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Buffer *RingBuffer
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ParityErrorDetected bool // set when parity error detected
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DataErrorDetected bool // set when data corruption detected
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DataOverflowDetected bool // set when data overflow detected in UART FIFO buffer or RingBuffer
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}
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type UARTStopBits int
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const (
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UARTStopBits_Default UARTStopBits = iota
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UARTStopBits_1
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UARTStopBits_1_5
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UARTStopBits_2
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)
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const (
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defaultDataBits = 8
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defaultStopBit = 1
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defaultParity = ParityNone
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uartInterrupts = esp.UART_INT_ENA_RXFIFO_FULL_INT_ENA |
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esp.UART_INT_ENA_PARITY_ERR_INT_ENA |
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esp.UART_INT_ENA_FRM_ERR_INT_ENA |
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esp.UART_INT_ENA_RXFIFO_OVF_INT_ENA |
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esp.UART_INT_ENA_GLITCH_DET_INT_ENA
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pplClockFreq = 80e6
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)
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type registerSet struct {
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interruptMapReg *volatile.Register32
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uartClockBitMask uint32
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gpioMatrixSignal uint32
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}
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func (uart *UART) Configure(config UARTConfig) error {
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if config.BaudRate == 0 {
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config.BaudRate = 115200
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}
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if config.TX == config.RX {
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return errSamePins
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}
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switch {
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case uart.Bus == esp.UART0:
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return uart.configure(config, registerSet{
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interruptMapReg: &esp.INTERRUPT_CORE0.UART_INTR_MAP,
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uartClockBitMask: esp.SYSTEM_PERIP_CLK_EN0_UART_CLK_EN,
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gpioMatrixSignal: 6,
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})
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case uart.Bus == esp.UART1:
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return uart.configure(config, registerSet{
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interruptMapReg: &esp.INTERRUPT_CORE0.UART1_INTR_MAP,
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uartClockBitMask: esp.SYSTEM_PERIP_CLK_EN0_UART1_CLK_EN,
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gpioMatrixSignal: 9,
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})
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}
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return errWrongUART
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}
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func (uart *UART) configure(config UARTConfig, regs registerSet) error {
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initUARTClock(uart.Bus, regs)
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// - disbale TX/RX clock to make sure the UART transmitter or receiver is not at work during configuration
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uart.Bus.SetCLK_CONF_TX_SCLK_EN(0)
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uart.Bus.SetCLK_CONF_RX_SCLK_EN(0)
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// Configure static registers (Ref: Configuring URATn Communication)
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// - default clock source: 1=APB_CLK, 2=FOSC_CLK, 3=XTAL_CLK
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uart.Bus.SetCLK_CONF_SCLK_SEL(1)
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// reset divisor of the divider via UART_SCLK_DIV_NUM, UART_SCLK_DIV_A, and UART_SCLK_DIV_B
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uart.Bus.SetCLK_CONF_SCLK_DIV_NUM(0)
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uart.Bus.SetCLK_CONF_SCLK_DIV_A(0)
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uart.Bus.SetCLK_CONF_SCLK_DIV_B(0)
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// - the baud rate
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uart.SetBaudRate(config.BaudRate)
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// - the data format
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uart.SetFormat(defaultDataBits, defaultStopBit, defaultParity)
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// - set UART mode
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uart.Bus.SetRS485_CONF_RS485_EN(0)
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uart.Bus.SetRS485_CONF_RS485TX_RX_EN(0)
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uart.Bus.SetRS485_CONF_RS485RXBY_TX_EN(0)
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uart.Bus.SetCONF0_IRDA_EN(0)
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// - disable hw-flow control
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uart.Bus.SetCONF0_TX_FLOW_EN(0)
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uart.Bus.SetCONF1_RX_FLOW_EN(0)
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// synchronize values into Core Clock
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uart.Bus.SetID_REG_UPDATE(1)
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uart.setupPins(config, regs)
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uart.configureInterrupt(regs.interruptMapReg)
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uart.enableTransmitter()
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uart.enableReceiver()
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// Start TX/RX
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uart.Bus.SetCLK_CONF_TX_SCLK_EN(1)
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uart.Bus.SetCLK_CONF_RX_SCLK_EN(1)
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return nil
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}
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func (uart *UART) SetFormat(dataBits, stopBits int, parity UARTParity) error {
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if dataBits < 5 {
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return errWrongBitSize
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}
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if stopBits > 1 {
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return errWrongStopBitSize
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}
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// - data length
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uart.Bus.SetCONF0_BIT_NUM(uint32(dataBits - 5))
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// - stop bit
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uart.Bus.SetCONF0_STOP_BIT_NUM(uint32(stopBits))
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// - parity check
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switch parity {
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case ParityNone:
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uart.Bus.SetCONF0_PARITY_EN(0)
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case ParityEven:
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uart.Bus.SetCONF0_PARITY_EN(1)
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uart.Bus.SetCONF0_PARITY(0)
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case ParityOdd:
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uart.Bus.SetCONF0_PARITY_EN(1)
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uart.Bus.SetCONF0_PARITY(1)
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}
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return nil
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}
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func initUARTClock(bus *esp.UART_Type, regs registerSet) {
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uartClock := &esp.SYSTEM.PERIP_CLK_EN0
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uartClockReset := &esp.SYSTEM.PERIP_RST_EN0
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// Initialize/reset URATn (Ref: Initializing URATn)
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// - enable the clock for UART RAM
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uartClock.SetBits(esp.SYSTEM_PERIP_CLK_EN0_UART_MEM_CLK_EN)
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// - enable APB_CLK for UARTn
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uartClock.SetBits(regs.uartClockBitMask)
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// - reset sequence
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uartClockReset.ClearBits(regs.uartClockBitMask)
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bus.SetCLK_CONF_RST_CORE(1)
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uartClockReset.SetBits(regs.uartClockBitMask)
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uartClockReset.ClearBits(regs.uartClockBitMask)
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bus.SetCLK_CONF_RST_CORE(0)
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// synchronize core register
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bus.SetID_REG_UPDATE(0)
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// enable RTC clock
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esp.RTC_CNTL.SetRTC_CLK_CONF_DIG_CLK8M_EN(1)
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// wait for Core Clock to ready for configuration
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for bus.GetID_REG_UPDATE() > 0 {
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riscv.Asm("nop")
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}
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}
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func (uart *UART) SetBaudRate(baudRate uint32) {
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// based on esp-idf
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max_div := uint32((1 << 12) - 1)
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sclk_div := (pplClockFreq + (max_div * baudRate) - 1) / (max_div * baudRate)
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clk_div := (pplClockFreq << 4) / (baudRate * sclk_div)
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uart.Bus.SetCLKDIV(clk_div >> 4)
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uart.Bus.SetCLKDIV_FRAG(clk_div & 0xf)
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uart.Bus.SetCLK_CONF_SCLK_DIV_NUM(sclk_div - 1)
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}
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func (uart *UART) setupPins(config UARTConfig, regs registerSet) {
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config.RX.Configure(PinConfig{Mode: PinInputPullup})
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config.TX.Configure(PinConfig{Mode: PinInputPullup})
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// link TX with GPIO signal X (technical reference manual 5.10) (this is not interrupt signal!)
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config.TX.outFunc().Set(regs.gpioMatrixSignal)
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// link RX with GPIO signal X and route signals via GPIO matrix (GPIO_SIGn_IN_SEL 0x40)
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inFunc(regs.gpioMatrixSignal).Set(esp.GPIO_FUNC_IN_SEL_CFG_SIG_IN_SEL | uint32(config.RX))
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}
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func (uart *UART) configureInterrupt(intrMapReg *volatile.Register32) { // Disable all UART interrupts
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// Disable all UART interrupts
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uart.Bus.INT_ENA.ClearBits(0x0ffff)
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intrMapReg.Set(7)
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onceUart.Do(func() {
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_ = interrupt.New(7, func(i interrupt.Interrupt) {
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UART0.serveInterrupt(0)
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UART1.serveInterrupt(1)
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}).Enable()
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})
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}
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func (uart *UART) serveInterrupt(num int) {
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// get interrupt status
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interrutFlag := uart.Bus.INT_ST.Get()
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if (interrutFlag & uartInterrupts) == 0 {
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return
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}
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// block UART interrupts while processing
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uart.Bus.INT_ENA.ClearBits(uartInterrupts)
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if interrutFlag&esp.UART_INT_ENA_RXFIFO_FULL_INT_ENA > 0 {
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for uart.Bus.GetSTATUS_RXFIFO_CNT() > 0 {
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b := uart.Bus.GetFIFO_RXFIFO_RD_BYTE()
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if !uart.Buffer.Put(byte(b & 0xff)) {
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uart.DataOverflowDetected = true
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}
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}
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}
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if interrutFlag&esp.UART_INT_ENA_PARITY_ERR_INT_ENA > 0 {
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uart.ParityErrorDetected = true
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}
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if 0 != interrutFlag&esp.UART_INT_ENA_FRM_ERR_INT_ENA {
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uart.DataErrorDetected = true
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}
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if 0 != interrutFlag&esp.UART_INT_ENA_RXFIFO_OVF_INT_ENA {
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uart.DataOverflowDetected = true
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}
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if 0 != interrutFlag&esp.UART_INT_ENA_GLITCH_DET_INT_ENA {
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uart.DataErrorDetected = true
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}
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// Clear the UART interrupt status
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uart.Bus.INT_CLR.SetBits(interrutFlag)
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uart.Bus.INT_CLR.ClearBits(interrutFlag)
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// Enable interrupts
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uart.Bus.INT_ENA.Set(uartInterrupts)
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}
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const uart_empty_thresh_default = 10
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func (uart *UART) enableTransmitter() {
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uart.Bus.SetCONF0_TXFIFO_RST(1)
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uart.Bus.SetCONF0_TXFIFO_RST(0)
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// TXINFO empty threshold is when txfifo_empty_int interrupt produced after the amount of data in Tx-FIFO is less than this register value.
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uart.Bus.SetCONF1_TXFIFO_EMPTY_THRHD(uart_empty_thresh_default)
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// we are not using interrut on TX since write we are waiting for FIFO to have space.
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// uart.Bus.INT_ENA.SetBits(esp.UART_INT_ENA_TXFIFO_EMPTY_INT_ENA)
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}
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func (uart *UART) enableReceiver() {
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uart.Bus.SetCONF0_RXFIFO_RST(1)
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uart.Bus.SetCONF0_RXFIFO_RST(0)
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// using value 1 so that we can start populate ring buffer with data as we get it
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uart.Bus.SetCONF1_RXFIFO_FULL_THRHD(1)
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// enable interrupts for:
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uart.Bus.SetINT_ENA_RXFIFO_FULL_INT_ENA(1)
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uart.Bus.SetINT_ENA_FRM_ERR_INT_ENA(1)
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uart.Bus.SetINT_ENA_PARITY_ERR_INT_ENA(1)
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uart.Bus.SetINT_ENA_GLITCH_DET_INT_ENA(1)
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uart.Bus.SetINT_ENA_RXFIFO_OVF_INT_ENA(1)
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}
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func (uart *UART) WriteByte(b byte) error {
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