teensy40: enable hardware UART reconfiguration, fix receive watermark interrupt
Этот коммит содержится в:
ardnew
Ron Evans
родитель
3eb9dca695
коммит
1e92e5f6c6
4 изменённых файлов: 82 добавлений и 93 удалений
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@ -2,6 +2,7 @@
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// Type definitions, fields, and constants associated with the MPU peripheral
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// of the NXP MIMXRT1062.
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//go:build nxp && mimxrt1062
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// +build nxp,mimxrt1062
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package nxp
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@ -216,6 +217,12 @@ func enableIcache(enable bool) {
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}
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}
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var (
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dcacheCcsidr volatile.Register32
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dcacheSets volatile.Register32
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dcacheWays volatile.Register32
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)
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func enableDcache(enable bool) {
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if enable != SystemControl.CCR.HasBits(SCB_CCR_DC_Msk) {
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if enable {
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@ -244,11 +251,6 @@ func enableDcache(enable bool) {
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isb 0xF
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`, nil)
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} else {
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var (
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ccsidr volatile.Register32
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sets volatile.Register32
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ways volatile.Register32
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)
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SystemControl.CSSELR.Set(0)
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arm.AsmFull(`
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dsb 0xF
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@ -257,17 +259,17 @@ func enableDcache(enable bool) {
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arm.AsmFull(`
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dsb 0xF
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`, nil)
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ccsidr.Set(SystemControl.CCSIDR.Get())
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sets.Set((ccsidr.Get() & SCB_CCSIDR_NUMSETS_Msk) >> SCB_CCSIDR_NUMSETS_Pos)
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for sets.Get() != 0 {
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ways.Set((ccsidr.Get() & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
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for ways.Get() != 0 {
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dcacheCcsidr.Set(SystemControl.CCSIDR.Get())
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dcacheSets.Set((dcacheCcsidr.Get() & SCB_CCSIDR_NUMSETS_Msk) >> SCB_CCSIDR_NUMSETS_Pos)
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for dcacheSets.Get() != 0 {
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dcacheWays.Set((dcacheCcsidr.Get() & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
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for dcacheWays.Get() != 0 {
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SystemControl.DCCISW.Set(
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((sets.Get() << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
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((ways.Get() << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk))
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ways.Set(ways.Get() - 1)
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((dcacheSets.Get() << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
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((dcacheWays.Get() << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk))
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dcacheWays.Set(dcacheWays.Get() - 1)
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}
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sets.Set(sets.Get() - 1)
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dcacheSets.Set(dcacheSets.Get() - 1)
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}
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arm.AsmFull(`
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dsb 0xF
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@ -88,15 +88,20 @@ const (
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I2C_SCL_PIN = I2C1_SCL_PIN // D19/A5
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)
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// Default peripherals
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var (
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DefaultUART = UART1
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)
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func init() {
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// register any interrupt handlers for this board's peripherals
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UART1.Interrupt = interrupt.New(nxp.IRQ_LPUART6, _UART1.handleInterrupt)
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UART2.Interrupt = interrupt.New(nxp.IRQ_LPUART4, _UART2.handleInterrupt)
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UART3.Interrupt = interrupt.New(nxp.IRQ_LPUART2, _UART3.handleInterrupt)
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UART4.Interrupt = interrupt.New(nxp.IRQ_LPUART3, _UART4.handleInterrupt)
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UART5.Interrupt = interrupt.New(nxp.IRQ_LPUART8, _UART5.handleInterrupt)
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UART6.Interrupt = interrupt.New(nxp.IRQ_LPUART1, _UART6.handleInterrupt)
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UART7.Interrupt = interrupt.New(nxp.IRQ_LPUART7, _UART7.handleInterrupt)
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_UART1.Interrupt = interrupt.New(nxp.IRQ_LPUART6, _UART1.handleInterrupt)
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_UART2.Interrupt = interrupt.New(nxp.IRQ_LPUART4, _UART2.handleInterrupt)
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_UART3.Interrupt = interrupt.New(nxp.IRQ_LPUART2, _UART3.handleInterrupt)
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_UART4.Interrupt = interrupt.New(nxp.IRQ_LPUART3, _UART4.handleInterrupt)
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_UART5.Interrupt = interrupt.New(nxp.IRQ_LPUART8, _UART5.handleInterrupt)
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_UART6.Interrupt = interrupt.New(nxp.IRQ_LPUART1, _UART6.handleInterrupt)
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_UART7.Interrupt = interrupt.New(nxp.IRQ_LPUART7, _UART7.handleInterrupt)
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}
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// #=====================================================#
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@ -136,7 +141,6 @@ const (
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)
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var (
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DefaultUART = UART1
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UART1 = &_UART1
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_UART1 = UART{
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Bus: nxp.LPUART6,
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@ -33,7 +33,6 @@ type UART struct {
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// auxiliary state data used internally
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configured bool
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msbFirst bool
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transmitting volatile.Register32
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}
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@ -46,6 +45,11 @@ func (uart *UART) resetTransmitting() {
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uart.Bus.GLOBAL.ClearBits(nxp.LPUART_GLOBAL_RST)
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}
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func (uart *UART) usesConfig(c UARTConfig) bool {
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return uart.configured && uart.baud == c.BaudRate &&
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uart.rx == c.RX && uart.tx == c.TX
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}
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// Configure initializes a UART with the given UARTConfig and other default
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// settings.
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func (uart *UART) Configure(config UARTConfig) {
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@ -56,13 +60,19 @@ func (uart *UART) Configure(config UARTConfig) {
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if config.BaudRate == 0 {
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config.BaudRate = defaultUartFreq
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}
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uart.baud = config.BaudRate
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// use default UART pins if not specified
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if config.RX == 0 && config.TX == 0 {
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config.RX = UART_RX_PIN
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config.TX = UART_TX_PIN
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}
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// Do not reconfigure pins and device buffers if duplicate config provided.
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if uart.usesConfig(config) {
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return
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}
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uart.baud = config.BaudRate
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uart.rx = config.RX
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uart.tx = config.TX
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@ -77,9 +87,38 @@ func (uart *UART) Configure(config UARTConfig) {
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// reset all internal logic and registers
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uart.resetTransmitting()
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// disable until we have finished configuring registers
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uart.Bus.CTRL.Set(0)
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// determine the baud rate and over-sample divisors
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sbr, osr := uart.getBaudRateDivisor(uart.baud)
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// set the baud rate, over-sample configuration, stop bits
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baudBits := (((osr - 1) << nxp.LPUART_BAUD_OSR_Pos) & nxp.LPUART_BAUD_OSR_Msk) |
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((sbr << nxp.LPUART_BAUD_SBR_Pos) & nxp.LPUART_BAUD_SBR_Msk)
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if osr <= 8 {
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// if OSR less than or equal to 8, we must enable sampling on both edges
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baudBits |= nxp.LPUART_BAUD_BOTHEDGE
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}
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uart.Bus.BAUD.Set(baudBits)
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uart.Bus.PINCFG.Set(0) // disable triggers
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// configure watermarks, flush and enable TX/RX FIFOs
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rxSize, txSize := uart.getFIFOSize()
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rxWater := rxSize >> 1
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if rxWater > uint32(nxp.LPUART_FIFO_RXFIFOSIZE_Msk>>nxp.LPUART_FIFO_RXFIFOSIZE_Pos) {
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rxWater = uint32(nxp.LPUART_FIFO_RXFIFOSIZE_Msk >> nxp.LPUART_FIFO_RXFIFOSIZE_Pos)
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}
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txWater := txSize >> 1
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if txWater > uint32(nxp.LPUART_FIFO_TXFIFOSIZE_Msk>>nxp.LPUART_FIFO_TXFIFOSIZE_Pos) {
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txWater = uint32(nxp.LPUART_FIFO_TXFIFOSIZE_Msk >> nxp.LPUART_FIFO_TXFIFOSIZE_Pos)
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}
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uart.Bus.WATER.Set(
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((rxWater << nxp.LPUART_WATER_RXWATER_Pos) & nxp.LPUART_WATER_RXWATER_Msk) |
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((txWater << nxp.LPUART_WATER_TXWATER_Pos) & nxp.LPUART_WATER_TXWATER_Msk))
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uart.Bus.FIFO.SetBits(nxp.LPUART_FIFO_RXFE | nxp.LPUART_FIFO_TXFE |
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nxp.LPUART_FIFO_RXFLUSH | nxp.LPUART_FIFO_TXFLUSH)
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// for now we assume some configuration. in particular:
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// Data bits -> 8-bit
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// Parity bit -> None (parity bit generation disabled)
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@ -90,71 +129,16 @@ func (uart *UART) Configure(config UARTConfig) {
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// RX RTS enabled -> false
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// TX CTS enabled -> false
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// set the baud rate, over-sample configuration, stop bits
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baudBits := (((osr - 1) << nxp.LPUART_BAUD_OSR_Pos) & nxp.LPUART_BAUD_OSR_Msk) |
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((sbr << nxp.LPUART_BAUD_SBR_Pos) & nxp.LPUART_BAUD_SBR_Msk) |
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((nxp.LPUART_BAUD_SBNS_SBNS_0 << nxp.LPUART_BAUD_SBNS_Pos) & nxp.LPUART_BAUD_SBNS_Msk)
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if osr <= 8 {
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// if OSR less than or equal to 8, we must enable sampling on both edges
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baudBits |= nxp.LPUART_BAUD_BOTHEDGE
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}
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uart.Bus.BAUD.Set(baudBits)
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uart.Bus.PINCFG.Set(0) // disable triggers
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// use 8 data bits, disable parity, use 1 idle char, and idle count starts
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// after start bit
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ctrlBits := uint32(((nxp.LPUART_CTRL_M_M_0 << nxp.LPUART_CTRL_M_Pos) & nxp.LPUART_CTRL_M_Msk) |
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((nxp.LPUART_CTRL_PE_PE_0 << nxp.LPUART_CTRL_PE_Pos) & nxp.LPUART_CTRL_PE_Msk) |
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((nxp.LPUART_CTRL_ILT_ILT_0 << nxp.LPUART_CTRL_ILT_Pos) & nxp.LPUART_CTRL_ILT_Msk) |
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((nxp.LPUART_CTRL_IDLECFG_IDLECFG_0 << nxp.LPUART_CTRL_IDLECFG_Pos) & nxp.LPUART_CTRL_IDLECFG_Msk))
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uart.Bus.CTRL.Set(ctrlBits)
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rxSize, txSize := uart.getFIFOSize()
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rxWater := rxSize >> 1
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if rxWater > uint32(nxp.LPUART_FIFO_RXFIFOSIZE_Msk>>nxp.LPUART_FIFO_RXFIFOSIZE_Pos) {
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rxWater = uint32(nxp.LPUART_FIFO_RXFIFOSIZE_Msk >> nxp.LPUART_FIFO_RXFIFOSIZE_Pos)
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}
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txWater := txSize >> 1
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if txWater > uint32(nxp.LPUART_FIFO_TXFIFOSIZE_Msk>>nxp.LPUART_FIFO_TXFIFOSIZE_Pos) {
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txWater = uint32(nxp.LPUART_FIFO_TXFIFOSIZE_Msk >> nxp.LPUART_FIFO_TXFIFOSIZE_Pos)
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}
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uart.Bus.WATER.Set(
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((rxWater << nxp.LPUART_WATER_RXWATER_Pos) & nxp.LPUART_WATER_RXWATER_Msk) |
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((txWater << nxp.LPUART_WATER_TXWATER_Pos) & nxp.LPUART_WATER_TXWATER_Msk))
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// enable TX/RX FIFOs
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uart.Bus.FIFO.SetBits(nxp.LPUART_FIFO_RXFE | nxp.LPUART_FIFO_TXFE)
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// flush TX/RX FIFOs
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uart.Bus.FIFO.SetBits(nxp.LPUART_FIFO_RXFLUSH | nxp.LPUART_FIFO_TXFLUSH)
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uart.Bus.MODIR.SetBits( // set the CTS configuration/TX CTS source
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((nxp.LPUART_MODIR_TXCTSC_TXCTSC_0 << nxp.LPUART_MODIR_TXCTSC_Pos) & nxp.LPUART_MODIR_TXCTSC_Msk) |
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((nxp.LPUART_MODIR_TXCTSSRC_TXCTSSRC_0 << nxp.LPUART_MODIR_TXCTSSRC_Pos) & nxp.LPUART_MODIR_TXCTSSRC_Msk))
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// enable transmitter, receiver functions
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uart.Bus.CTRL.Set(nxp.LPUART_CTRL_TE | nxp.LPUART_CTRL_RE |
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// enable receiver, idle line interrupts
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nxp.LPUART_CTRL_RIE | nxp.LPUART_CTRL_ILIE)
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// clear all status flags
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stat := uint32(nxp.LPUART_STAT_RXEDGIF_Msk | nxp.LPUART_STAT_IDLE_Msk | nxp.LPUART_STAT_OR_Msk |
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nxp.LPUART_STAT_NF_Msk | nxp.LPUART_STAT_FE_Msk | nxp.LPUART_STAT_PF_Msk |
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nxp.LPUART_STAT_LBKDIF_Msk | nxp.LPUART_STAT_MA1F_Msk | nxp.LPUART_STAT_MA2F_Msk)
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uart.Bus.STAT.Set(uart.Bus.STAT.Get())
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// set data bits order
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if uart.msbFirst {
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stat |= nxp.LPUART_STAT_MSBF
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} else {
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stat &^= nxp.LPUART_STAT_MSBF
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}
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uart.Bus.STAT.SetBits(stat)
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// enable RX/TX functions
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uart.Bus.CTRL.SetBits(nxp.LPUART_CTRL_TE | nxp.LPUART_CTRL_RE)
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// enable RX IRQ
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uart.Interrupt.SetPriority(0xc0)
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// enable RX interrupt
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uart.Interrupt.SetPriority(0xC0)
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uart.Interrupt.Enable()
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uart.configured = true
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@ -211,13 +195,13 @@ func (uart *UART) WriteByte(c byte) error {
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// corresponding baud rate divisor (1..8191) that best partition a given baud
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// rate into equal intervals.
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//
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// This is an integral (i.e. non-floating point) port of the logic at the
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// This is an integral (non-floating point) translation of the logic at the
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// beginning of:
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// void HardwareSerial::begin(uint32_t baud, uint16_t format)
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// (from Teensyduino: `cores/teensy4/HardwareSerial.cpp`)
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//
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// We don't want to risk using floating point here in the machine package in
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// case it gets called before the FPU or interrupts are ready (e.g., init()).
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// We don't want to use floating point here in case it gets called from an ISR
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// or very early during system init.
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func (uart *UART) getBaudRateDivisor(baudRate uint32) (sbr uint32, osr uint32) {
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const clock = 24000000 // UART is muxed to 24 MHz OSC
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err := uint32(0xFFFFFFFF)
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@ -8,8 +8,7 @@ MEMORY
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ENTRY(Reset_Handler);
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_stack_size = 128K;
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_heap_size = 512K;
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_stack_size = 4K;
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SECTIONS
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{
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