stm32l5: add pwm
Этот коммит содержится в:
Kenneth Bell
Ron Evans
родитель
ee167f15de
коммит
2c4b507d34
5 изменённых файлов: 259 добавлений и 16 удалений
11
src/examples/pwm/nucleo-l552ze.go
Обычный файл
11
src/examples/pwm/nucleo-l552ze.go
Обычный файл
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@ -0,0 +1,11 @@
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// +build stm32l5
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package main
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import "machine"
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var (
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pwm = &machine.TIM1
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pinA = machine.PA8
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pinB = machine.PA9
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)
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@ -1,4 +1,4 @@
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// +build stm32f4
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// +build stm32f4 stm32l5
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package machine
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@ -8,6 +8,8 @@ import (
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"runtime/volatile"
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)
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const PWM_MODE1 = 0x6
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type TimerCallback func()
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type ChannelCallback func(channel uint8)
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@ -94,7 +96,7 @@ func (t *TIM) SetMatchInterrupt(channel uint8, callback ChannelCallback) error {
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t.OCInterrupt = t.registerOCInterrupt()
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// Clear the interrupt flag
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t.Device.SR.ClearBits(stm32.TIM_SR_CC1IF_Match << channel)
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t.Device.SR.ClearBits(stm32.TIM_SR_CC1IF << channel)
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// Enable the interrupt
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t.OCInterrupt.SetPriority(0xc1)
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@ -6,9 +6,30 @@ package machine
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import (
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"device/stm32"
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"runtime/interrupt"
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"runtime/volatile"
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"unsafe"
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)
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const (
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AF0_SYSTEM = 0
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AF1_TIM1_2_5_8_LPTIM1 = 1
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AF2_TIM1_2_3_4_5_LPTIM3 = 2
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AF3_SPI2_SAI1_I2C4_USART2_TIM1_8_OCTOSPI1 = 3
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AF4_I2C1_2_3_4 = 4
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AF5_SPI1_2_3_I2C4_DFSDM1_OCTOSPI1 = 5
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AF6_SPI3_I2C3_DFSDM1_COMP1 = 6
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AF7_USART1_2_3 = 7
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AF8_UART4_5_LPUART1_SDMMC1 = 8
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AF9_FDCAN1_TSC = 9
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AF10_USB_OCTOSPI1 = 10
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AF11_UCPD1 = 11
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AF12_SDMMC1_COMP1_2_TIM1_8_FMC = 12
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AF13_SAI1_2_TIM8 = 13
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AF14_TIM2_8_15_16_17_LPTIM2 = 14
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AF15_EVENTOUT = 15
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)
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const (
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PA0 = portA + 0
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PA1 = portA + 1
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@ -249,3 +270,220 @@ func enableAltFuncClock(bus unsafe.Pointer) {
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM1EN)
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}
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}
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//---------- Timer related code
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var (
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TIM1 = TIM{
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EnableRegister: &stm32.RCC.APB2ENR,
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EnableFlag: stm32.RCC_APB2ENR_TIM1EN,
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Device: stm32.TIM1,
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Channels: [4]TimerChannel{
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TimerChannel{Pins: []PinFunction{{PA8, AF1_TIM1_2_5_8_LPTIM1}, {PE9, AF1_TIM1_2_5_8_LPTIM1}}},
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TimerChannel{Pins: []PinFunction{{PA9, AF1_TIM1_2_5_8_LPTIM1}, {PE11, AF1_TIM1_2_5_8_LPTIM1}}},
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TimerChannel{Pins: []PinFunction{{PA10, AF1_TIM1_2_5_8_LPTIM1}, {PE13, AF1_TIM1_2_5_8_LPTIM1}}},
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TimerChannel{Pins: []PinFunction{{PA11, AF1_TIM1_2_5_8_LPTIM1}, {PE14, AF1_TIM1_2_5_8_LPTIM1}}},
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},
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busFreq: APB2_TIM_FREQ,
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}
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TIM2 = TIM{
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EnableRegister: &stm32.RCC.APB1ENR1,
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EnableFlag: stm32.RCC_APB1ENR1_TIM2EN,
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Device: stm32.TIM2,
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Channels: [4]TimerChannel{
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TimerChannel{Pins: []PinFunction{{PA0, AF1_TIM1_2_5_8_LPTIM1}, {PA5, AF1_TIM1_2_5_8_LPTIM1}, {PA15, AF1_TIM1_2_5_8_LPTIM1}}},
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TimerChannel{Pins: []PinFunction{{PA1, AF1_TIM1_2_5_8_LPTIM1}, {PB3, AF1_TIM1_2_5_8_LPTIM1}}},
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TimerChannel{Pins: []PinFunction{{PA2, AF1_TIM1_2_5_8_LPTIM1}, {PB10, AF1_TIM1_2_5_8_LPTIM1}}},
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TimerChannel{Pins: []PinFunction{{PA3, AF1_TIM1_2_5_8_LPTIM1}, {PB11, AF1_TIM1_2_5_8_LPTIM1}}},
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},
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busFreq: APB1_TIM_FREQ,
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}
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TIM3 = TIM{
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EnableRegister: &stm32.RCC.APB1ENR1,
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EnableFlag: stm32.RCC_APB1ENR1_TIM3EN,
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Device: stm32.TIM3,
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Channels: [4]TimerChannel{
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TimerChannel{Pins: []PinFunction{{PA6, AF2_TIM1_2_3_4_5_LPTIM3}, {PB4, AF2_TIM1_2_3_4_5_LPTIM3}, {PC6, AF2_TIM1_2_3_4_5_LPTIM3}, {PE3, AF2_TIM1_2_3_4_5_LPTIM3}}},
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TimerChannel{Pins: []PinFunction{{PA7, AF2_TIM1_2_3_4_5_LPTIM3}, {PB5, AF2_TIM1_2_3_4_5_LPTIM3}, {PC7, AF2_TIM1_2_3_4_5_LPTIM3}, {PE4, AF2_TIM1_2_3_4_5_LPTIM3}}},
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TimerChannel{Pins: []PinFunction{{PB0, AF2_TIM1_2_3_4_5_LPTIM3}, {PC8, AF2_TIM1_2_3_4_5_LPTIM3}, {PE5, AF2_TIM1_2_3_4_5_LPTIM3}}},
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TimerChannel{Pins: []PinFunction{{PB1, AF2_TIM1_2_3_4_5_LPTIM3}, {PC9, AF2_TIM1_2_3_4_5_LPTIM3}, {PE6, AF2_TIM1_2_3_4_5_LPTIM3}}},
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},
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busFreq: APB1_TIM_FREQ,
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}
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TIM4 = TIM{
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EnableRegister: &stm32.RCC.APB1ENR1,
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EnableFlag: stm32.RCC_APB1ENR1_TIM4EN,
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Device: stm32.TIM4,
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Channels: [4]TimerChannel{
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TimerChannel{Pins: []PinFunction{{PB6, AF2_TIM1_2_3_4_5_LPTIM3}, {PD12, AF2_TIM1_2_3_4_5_LPTIM3}}},
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TimerChannel{Pins: []PinFunction{{PB7, AF2_TIM1_2_3_4_5_LPTIM3}, {PD13, AF2_TIM1_2_3_4_5_LPTIM3}}},
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TimerChannel{Pins: []PinFunction{{PB8, AF2_TIM1_2_3_4_5_LPTIM3}, {PD14, AF2_TIM1_2_3_4_5_LPTIM3}}},
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TimerChannel{Pins: []PinFunction{{PB9, AF2_TIM1_2_3_4_5_LPTIM3}, {PD15, AF2_TIM1_2_3_4_5_LPTIM3}}},
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},
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busFreq: APB1_TIM_FREQ,
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}
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TIM5 = TIM{
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EnableRegister: &stm32.RCC.APB1ENR1,
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EnableFlag: stm32.RCC_APB1ENR1_TIM5EN,
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Device: stm32.TIM5,
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Channels: [4]TimerChannel{
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TimerChannel{Pins: []PinFunction{{PA0, AF2_TIM1_2_3_4_5_LPTIM3}, {PF6, AF2_TIM1_2_3_4_5_LPTIM3}}},
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TimerChannel{Pins: []PinFunction{{PA1, AF2_TIM1_2_3_4_5_LPTIM3}, {PF7, AF2_TIM1_2_3_4_5_LPTIM3}}},
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TimerChannel{Pins: []PinFunction{{PA2, AF2_TIM1_2_3_4_5_LPTIM3}, {PF8, AF2_TIM1_2_3_4_5_LPTIM3}}},
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TimerChannel{Pins: []PinFunction{{PA3, AF2_TIM1_2_3_4_5_LPTIM3}, {PF9, AF2_TIM1_2_3_4_5_LPTIM3}}},
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},
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busFreq: APB1_TIM_FREQ,
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}
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TIM6 = TIM{
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EnableRegister: &stm32.RCC.APB1ENR1,
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EnableFlag: stm32.RCC_APB1ENR1_TIM6EN,
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Device: stm32.TIM6,
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Channels: [4]TimerChannel{
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TimerChannel{Pins: []PinFunction{}},
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TimerChannel{Pins: []PinFunction{}},
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TimerChannel{Pins: []PinFunction{}},
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TimerChannel{Pins: []PinFunction{}},
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},
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busFreq: APB1_TIM_FREQ,
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}
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TIM7 = TIM{
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EnableRegister: &stm32.RCC.APB1ENR1,
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EnableFlag: stm32.RCC_APB1ENR1_TIM7EN,
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Device: stm32.TIM7,
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Channels: [4]TimerChannel{
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TimerChannel{Pins: []PinFunction{}},
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TimerChannel{Pins: []PinFunction{}},
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TimerChannel{Pins: []PinFunction{}},
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TimerChannel{Pins: []PinFunction{}},
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},
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busFreq: APB1_TIM_FREQ,
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}
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TIM8 = TIM{
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EnableRegister: &stm32.RCC.APB2ENR,
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EnableFlag: stm32.RCC_APB2ENR_TIM8EN,
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Device: stm32.TIM8,
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Channels: [4]TimerChannel{
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TimerChannel{Pins: []PinFunction{{PC6, AF3_SPI2_SAI1_I2C4_USART2_TIM1_8_OCTOSPI1}}},
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TimerChannel{Pins: []PinFunction{{PC7, AF3_SPI2_SAI1_I2C4_USART2_TIM1_8_OCTOSPI1}}},
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TimerChannel{Pins: []PinFunction{{PC8, AF3_SPI2_SAI1_I2C4_USART2_TIM1_8_OCTOSPI1}}},
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TimerChannel{Pins: []PinFunction{{PC9, AF3_SPI2_SAI1_I2C4_USART2_TIM1_8_OCTOSPI1}}},
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},
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busFreq: APB2_TIM_FREQ,
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}
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TIM15 = TIM{
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EnableRegister: &stm32.RCC.APB2ENR,
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EnableFlag: stm32.RCC_APB2ENR_TIM15EN,
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Device: stm32.TIM15,
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Channels: [4]TimerChannel{
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TimerChannel{Pins: []PinFunction{{PA1, AF14_TIM2_8_15_16_17_LPTIM2}, {PB14, AF14_TIM2_8_15_16_17_LPTIM2}, {PF9, AF14_TIM2_8_15_16_17_LPTIM2}, {PG10, AF14_TIM2_8_15_16_17_LPTIM2}}},
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TimerChannel{Pins: []PinFunction{{PA2, AF14_TIM2_8_15_16_17_LPTIM2}, {PB15, AF14_TIM2_8_15_16_17_LPTIM2}, {PF10, AF14_TIM2_8_15_16_17_LPTIM2}, {PG11, AF14_TIM2_8_15_16_17_LPTIM2}}},
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TimerChannel{Pins: []PinFunction{}},
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TimerChannel{Pins: []PinFunction{}},
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},
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busFreq: APB2_TIM_FREQ,
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}
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TIM16 = TIM{
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EnableRegister: &stm32.RCC.APB2ENR,
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EnableFlag: stm32.RCC_APB2ENR_TIM16EN,
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Device: stm32.TIM16,
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Channels: [4]TimerChannel{
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TimerChannel{Pins: []PinFunction{{PA6, AF14_TIM2_8_15_16_17_LPTIM2}, {PB8, AF14_TIM2_8_15_16_17_LPTIM2}, {PE0, AF14_TIM2_8_15_16_17_LPTIM2}}},
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TimerChannel{Pins: []PinFunction{}},
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TimerChannel{Pins: []PinFunction{}},
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TimerChannel{Pins: []PinFunction{}},
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},
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busFreq: APB2_TIM_FREQ,
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}
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TIM17 = TIM{
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EnableRegister: &stm32.RCC.APB2ENR,
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EnableFlag: stm32.RCC_APB2ENR_TIM17EN,
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Device: stm32.TIM17,
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Channels: [4]TimerChannel{
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TimerChannel{Pins: []PinFunction{{PA7, AF14_TIM2_8_15_16_17_LPTIM2}, {PB9, AF14_TIM2_8_15_16_17_LPTIM2}, {PE1, AF14_TIM2_8_15_16_17_LPTIM2}}},
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TimerChannel{Pins: []PinFunction{}},
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TimerChannel{Pins: []PinFunction{}},
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TimerChannel{Pins: []PinFunction{}},
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},
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busFreq: APB2_TIM_FREQ,
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}
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)
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func (t *TIM) registerUPInterrupt() interrupt.Interrupt {
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switch t {
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case &TIM1:
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return interrupt.New(stm32.IRQ_TIM1_UP, TIM1.handleUPInterrupt)
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case &TIM2:
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return interrupt.New(stm32.IRQ_TIM2, TIM2.handleUPInterrupt)
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case &TIM3:
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return interrupt.New(stm32.IRQ_TIM3, TIM3.handleUPInterrupt)
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case &TIM4:
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return interrupt.New(stm32.IRQ_TIM4, TIM4.handleUPInterrupt)
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case &TIM5:
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return interrupt.New(stm32.IRQ_TIM5, TIM5.handleUPInterrupt)
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case &TIM6:
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return interrupt.New(stm32.IRQ_TIM6, TIM6.handleUPInterrupt)
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case &TIM7:
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return interrupt.New(stm32.IRQ_TIM7, TIM7.handleUPInterrupt)
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case &TIM8:
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return interrupt.New(stm32.IRQ_TIM8_UP, TIM8.handleUPInterrupt)
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case &TIM15:
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return interrupt.New(stm32.IRQ_TIM15, TIM15.handleUPInterrupt)
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case &TIM16:
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return interrupt.New(stm32.IRQ_TIM16, TIM16.handleUPInterrupt)
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case &TIM17:
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return interrupt.New(stm32.IRQ_TIM17, TIM17.handleUPInterrupt)
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}
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return interrupt.Interrupt{}
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}
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func (t *TIM) registerOCInterrupt() interrupt.Interrupt {
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switch t {
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case &TIM1:
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return interrupt.New(stm32.IRQ_TIM1_CC, TIM1.handleOCInterrupt)
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case &TIM2:
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return interrupt.New(stm32.IRQ_TIM2, TIM2.handleOCInterrupt)
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case &TIM3:
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return interrupt.New(stm32.IRQ_TIM3, TIM3.handleOCInterrupt)
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case &TIM4:
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return interrupt.New(stm32.IRQ_TIM4, TIM4.handleOCInterrupt)
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case &TIM5:
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return interrupt.New(stm32.IRQ_TIM5, TIM5.handleOCInterrupt)
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case &TIM6:
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return interrupt.New(stm32.IRQ_TIM6, TIM6.handleOCInterrupt)
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case &TIM7:
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return interrupt.New(stm32.IRQ_TIM7, TIM7.handleOCInterrupt)
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case &TIM8:
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return interrupt.New(stm32.IRQ_TIM8_CC, TIM8.handleOCInterrupt)
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case &TIM15:
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return interrupt.New(stm32.IRQ_TIM15, TIM15.handleOCInterrupt)
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case &TIM16:
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return interrupt.New(stm32.IRQ_TIM16, TIM16.handleOCInterrupt)
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case &TIM17:
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return interrupt.New(stm32.IRQ_TIM17, TIM17.handleOCInterrupt)
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}
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return interrupt.Interrupt{}
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}
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func (t *TIM) enableMainOutput() {
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t.Device.BDTR.SetBits(stm32.TIM_BDTR_MOE)
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}
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type arrtype = uint32
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type arrRegType = volatile.Register32
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const (
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ARR_MAX = 0x10000
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PSC_MAX = 0x10000
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)
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|
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@ -12,6 +12,12 @@ func CPUFrequency() uint32 {
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return 110000000
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}
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// Internal use: configured speed of the APB1 and APB2 timers, this should be kept
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// in sync with any changes to runtime package which configures the oscillators
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// and clock frequencies
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const APB1_TIM_FREQ = 110e6 // 110MHz
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const APB2_TIM_FREQ = 110e6 // 110MHz
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//---------- UART related code
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// Configure the UART.
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|
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@ -26,20 +26,6 @@ const (
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PLL_R = 2 // RCC_PLLR_DIV2
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)
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/*
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timer settings used for tick and sleep.
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note: TICK_TIMER_FREQ and SLEEP_TIMER_FREQ are controlled by PLL / clock
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settings above, so must be kept in sync if the clock settings are changed.
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*/
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const (
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TICK_RATE = 1000 // 1 KHz
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SLEEP_TIMER_IRQ = stm32.IRQ_TIM15
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||||
SLEEP_TIMER_FREQ = 110000000 // 110 MHz
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TICK_TIMER_IRQ = stm32.IRQ_TIM16
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TICK_TIMER_FREQ = 110000000 // 110 MHz
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)
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type arrtype = uint32
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func init() {
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