machine/hifive1b: add support for SPI1
Signed-off-by: Ron Evans <ron@hybridgroup.com>
Этот коммит содержится в:
Ron Evans
Ayke
родитель
373fa6d69b
коммит
46d468b79d
4 изменённых файлов: 136 добавлений и 14 удалений
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@ -2,6 +2,8 @@
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package machine
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import "device/sifive"
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const (
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P00 Pin = 0
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P01 Pin = 1
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@ -36,3 +38,10 @@ const (
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P30 Pin = 30
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P31 Pin = 31
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)
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// SPI on the HiFive1.
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var (
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SPI1 = SPI{
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Bus: sifive.QSPI1,
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}
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)
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@ -6,23 +6,23 @@ const (
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D0 = P16
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D1 = P17
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D2 = P18
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D3 = P19 // Green LED/PWM
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D4 = P20 // PWM
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D5 = P21 // Blue LED/PWM
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D6 = P22 // Red LED/PWM
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D3 = P19 // Green LED/PWM (PWM1_PWM1)
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D4 = P20 // PWM (PWM1_PWM0)
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D5 = P21 // Blue LED/PWM (PWM1_PWM2)
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D6 = P22 // Red LED/PWM (PWM1_PWM3)
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D7 = P16
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D8 = NoPin // PWM?
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D9 = P01
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D10 = P02
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D11 = P03
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D12 = P04
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D13 = P05
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D10 = P02 // SPI1_CS0
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D11 = P03 // SPI1_DQ0
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D12 = P04 // SPI1_DQ1
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D13 = P05 // SPI1_SCK
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D14 = NoPin // not connected
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D15 = P09 // does not seem to work?
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D16 = P10 // PWM
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D17 = P11 // PWM
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D18 = P12 // SDA/PWM
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D19 = P13 // SDL/PWM
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D16 = P10 // PWM (PWM2_PWM0)
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D17 = P11 // PWM (PWM2_PWM1)
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D18 = P12 // SDA (I2C0_SDA)/PWM (PWM2_PWM2)
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D19 = P13 // SDL (I2C0_SCL)/PWM (PWM2_PWM3)
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)
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const (
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@ -40,3 +40,14 @@ const (
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UART_TX_PIN = NoPin
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UART_RX_PIN = NoPin
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)
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// SPI pins
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const (
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SPI0_SCK_PIN = NoPin
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SPI0_MOSI_PIN = NoPin
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SPI0_MISO_PIN = NoPin
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SPI1_SCK_PIN = D13
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SPI1_MOSI_PIN = D11
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SPI1_MISO_PIN = D12
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)
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@ -6,18 +6,30 @@ import (
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"device/sifive"
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)
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const CPU_FREQUENCY = 16000000
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type PinMode uint8
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const (
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PinInput PinMode = iota
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PinOutput
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PinPWM
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PinSPI
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PinI2C = PinSPI
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)
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// Configure this pin with the given configuration.
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func (p Pin) Configure(config PinConfig) {
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sifive.GPIO0.INPUT_EN.SetBits(1 << uint8(p))
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if config.Mode == PinOutput {
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switch config.Mode {
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case PinOutput:
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sifive.GPIO0.OUTPUT_EN.SetBits(1 << uint8(p))
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case PinPWM:
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sifive.GPIO0.IOF_EN.SetBits(1 << uint8(p))
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sifive.GPIO0.IOF_SEL.SetBits(1 << uint8(p))
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case PinSPI:
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sifive.GPIO0.IOF_EN.SetBits(1 << uint8(p))
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sifive.GPIO0.IOF_SEL.ClearBits(1 << uint8(p))
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}
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}
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@ -59,3 +71,93 @@ func (uart UART) WriteByte(c byte) {
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sifive.UART0.TXDATA.Set(uint32(c))
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}
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// SPI on the FE310. The normal SPI0 is actually a quad-SPI meant for flash, so it is best
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// to use SPI1 or SPI2 port for most applications.
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type SPI struct {
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Bus *sifive.QSPI_Type
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}
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// SPIConfig is used to store config info for SPI.
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type SPIConfig struct {
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Frequency uint32
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SCK Pin
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MOSI Pin
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MISO Pin
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LSBFirst bool
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Mode uint8
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}
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// Configure is intended to setup the SPI interface.
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func (spi SPI) Configure(config SPIConfig) error {
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// Use default pins if not set.
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if config.SCK == 0 && config.MOSI == 0 && config.MISO == 0 {
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config.SCK = SPI0_SCK_PIN
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config.MOSI = SPI0_MOSI_PIN
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config.MISO = SPI0_MISO_PIN
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}
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// enable pins for SPI
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config.SCK.Configure(PinConfig{Mode: PinSPI})
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config.MOSI.Configure(PinConfig{Mode: PinSPI})
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config.MISO.Configure(PinConfig{Mode: PinSPI})
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// set default frequency
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if config.Frequency == 0 {
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config.Frequency = 4000000
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}
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// div = (SPI_CFG(dev)->f_sys / (2 * frequency)) - 1;
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div := CPU_FREQUENCY/(2*config.Frequency) - 1
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spi.Bus.DIV.Set(div)
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// set mode
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switch config.Mode {
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case 0:
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spi.Bus.MODE.ClearBits(sifive.QSPI_MODE_PHASE)
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spi.Bus.MODE.ClearBits(sifive.QSPI_MODE_POLARITY)
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case 1:
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spi.Bus.MODE.SetBits(sifive.QSPI_MODE_PHASE)
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spi.Bus.MODE.ClearBits(sifive.QSPI_MODE_POLARITY)
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case 2:
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spi.Bus.MODE.ClearBits(sifive.QSPI_MODE_PHASE)
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spi.Bus.MODE.SetBits(sifive.QSPI_MODE_POLARITY)
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case 3:
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spi.Bus.MODE.SetBits(sifive.QSPI_MODE_PHASE | sifive.QSPI_MODE_POLARITY)
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default: // to mode 0
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spi.Bus.MODE.ClearBits(sifive.QSPI_MODE_PHASE)
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spi.Bus.MODE.ClearBits(sifive.QSPI_MODE_POLARITY)
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}
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// frame length
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spi.Bus.FMT.SetBits(8 << sifive.QSPI_FMT_LENGTH_Pos)
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// Set single line operation, by clearing all bits
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spi.Bus.FMT.ClearBits(sifive.QSPI_FMT_PROTOCOL_Msk)
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// set bit transfer order
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if config.LSBFirst {
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spi.Bus.FMT.SetBits(sifive.QSPI_FMT_ENDIAN)
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} else {
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spi.Bus.FMT.ClearBits(sifive.QSPI_FMT_ENDIAN)
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}
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return nil
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}
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// Transfer writes/reads a single byte using the SPI interface.
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func (spi SPI) Transfer(w byte) (byte, error) {
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// wait for tx ready
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for spi.Bus.TXDATA.HasBits(sifive.QSPI_TXDATA_FULL) {
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}
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// write data
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spi.Bus.TXDATA.Set(uint32(w))
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// wait until receive has data
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for spi.Bus.RXDATA.HasBits(sifive.QSPI_RXDATA_EMPTY) {
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}
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// return data
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return byte(spi.Bus.RXDATA.Get() & sifive.QSPI_RXDATA_DATA_Msk), nil
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}
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@ -1,4 +1,4 @@
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// +build sam stm32,!stm32f407
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// +build sam stm32,!stm32f407 fe310
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package machine
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