runtime: separate runtime initialization for STM32F4 boards
The STM32F469 can use the same initialization as the existing STM32F407 with a few frequency tweaks. This change splits the generic initialization code into a separate runtime_stm32f4.go file, leaving only the 407 board specific constants in the existing runtime_stm32f407.go file. Note that runtime_stm32f405.go initialization seems semantically similar to the 407, but I don't have enough confidence in merging 405 with 407 in this change.
Этот коммит содержится в:
Elias Naur
kenbell
родитель
11ee0969b6
коммит
55ca5287fe
2 изменённых файлов: 97 добавлений и 89 удалений
88
src/runtime/runtime_stm32f4.go
Обычный файл
88
src/runtime/runtime_stm32f4.go
Обычный файл
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@ -0,0 +1,88 @@
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//go:build stm32f4 && (stm32f407 || stm32f469)
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// +build stm32f4
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// +build stm32f407 stm32f469
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package runtime
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import (
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"device/stm32"
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"machine"
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)
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func init() {
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initCLK()
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machine.Serial.Configure(machine.UARTConfig{})
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initTickTimer(&machine.TIM2)
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}
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func putchar(c byte) {
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machine.Serial.WriteByte(c)
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}
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func initCLK() {
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// Reset clock registers
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// Set HSION
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stm32.RCC.CR.SetBits(stm32.RCC_CR_HSION)
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for !stm32.RCC.CR.HasBits(stm32.RCC_CR_HSIRDY) {
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}
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// Reset CFGR
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stm32.RCC.CFGR.Set(0x00000000)
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// Reset HSEON, CSSON and PLLON
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stm32.RCC.CR.ClearBits(stm32.RCC_CR_HSEON | stm32.RCC_CR_CSSON | stm32.RCC_CR_PLLON)
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// Reset PLLCFGR
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stm32.RCC.PLLCFGR.Set(0x24003010)
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// Reset HSEBYP
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stm32.RCC.CR.ClearBits(stm32.RCC_CR_HSEBYP)
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// Disable all interrupts
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stm32.RCC.CIR.Set(0x00000000)
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// Set up the clock
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var startupCounter uint32 = 0
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// Enable HSE
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stm32.RCC.CR.Set(stm32.RCC_CR_HSEON)
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// Wait till HSE is ready and if timeout is reached exit
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for {
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startupCounter++
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if stm32.RCC.CR.HasBits(stm32.RCC_CR_HSERDY) || (startupCounter == HSE_STARTUP_TIMEOUT) {
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break
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}
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}
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if stm32.RCC.CR.HasBits(stm32.RCC_CR_HSERDY) {
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// Enable high performance mode, configure maximum system frequency.
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_PWREN)
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stm32.PWR.CR.SetBits(0x4000) // PWR_CR_VOS
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// HCLK = SYSCLK / 1
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stm32.RCC.CFGR.SetBits(stm32.RCC_CFGR_HPRE_Div1 << stm32.RCC_CFGR_HPRE_Pos)
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// PCLK2 = HCLK / 2
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stm32.RCC.CFGR.SetBits(stm32.RCC_CFGR_PPRE2_Div2 << stm32.RCC_CFGR_PPRE2_Pos)
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// PCLK1 = HCLK / 4
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stm32.RCC.CFGR.SetBits(stm32.RCC_CFGR_PPRE1_Div4 << stm32.RCC_CFGR_PPRE1_Pos)
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// Configure the main PLL
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stm32.RCC.PLLCFGR.Set(PLL_CFGR)
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// Enable main PLL
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stm32.RCC.CR.SetBits(stm32.RCC_CR_PLLON)
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// Wait till the main PLL is ready
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for (stm32.RCC.CR.Get() & stm32.RCC_CR_PLLRDY) == 0 {
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}
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// Configure Flash prefetch, Instruction cache, Data cache and wait state
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stm32.FLASH.ACR.Set(stm32.FLASH_ACR_ICEN | stm32.FLASH_ACR_DCEN | (5 << stm32.FLASH_ACR_LATENCY_Pos))
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// Select the main PLL as system clock source
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stm32.RCC.CFGR.ClearBits(stm32.RCC_CFGR_SW_Msk)
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stm32.RCC.CFGR.SetBits(stm32.RCC_CFGR_SW_PLL << stm32.RCC_CFGR_SW_Pos)
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for (stm32.RCC.CFGR.Get() & stm32.RCC_CFGR_SWS_Msk) != (stm32.RCC_CFGR_SWS_PLL << stm32.RCC_CFGR_SWS_Pos) {
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}
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} else {
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// If HSE failed to start up, the application will have wrong clock configuration
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for {
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}
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}
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// Enable the CCM RAM clock
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stm32.RCC.AHB1ENR.SetBits(1 << 20)
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}
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@ -1,11 +1,9 @@
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// +build stm32,stm32f407
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//go:build stm32f4 && stm32f407
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// +build stm32f4,stm32f407
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package runtime
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import (
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"device/stm32"
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"machine"
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)
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import "device/stm32"
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/*
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clock settings
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@ -24,84 +22,6 @@ const (
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PLL_N = 336
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PLL_P = 2 // SYSCLK = PLL_VCO / PLL_P
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PLL_Q = 7 // USB OTS FS, SDIO and RNG Clock = PLL_VCO / PLL_Q
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PLL_CFGR = PLL_M | (PLL_N << stm32.RCC_PLLCFGR_PLLN_Pos) | (((PLL_P >> 1) - 1) << stm32.RCC_PLLCFGR_PLLP_Pos) |
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(1 << stm32.RCC_PLLCFGR_PLLSRC_Pos) | (PLL_Q << stm32.RCC_PLLCFGR_PLLQ_Pos)
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)
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func init() {
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initCLK()
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machine.Serial.Configure(machine.UARTConfig{})
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initTickTimer(&machine.TIM2)
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}
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func putchar(c byte) {
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machine.Serial.WriteByte(c)
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}
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func initCLK() {
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// Reset clock registers
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// Set HSION
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stm32.RCC.CR.SetBits(stm32.RCC_CR_HSION)
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for !stm32.RCC.CR.HasBits(stm32.RCC_CR_HSIRDY) {
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}
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// Reset CFGR
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stm32.RCC.CFGR.Set(0x00000000)
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// Reset HSEON, CSSON and PLLON
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stm32.RCC.CR.ClearBits(stm32.RCC_CR_HSEON | stm32.RCC_CR_CSSON | stm32.RCC_CR_PLLON)
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// Reset PLLCFGR
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stm32.RCC.PLLCFGR.Set(0x24003010)
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// Reset HSEBYP
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stm32.RCC.CR.ClearBits(stm32.RCC_CR_HSEBYP)
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// Disable all interrupts
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stm32.RCC.CIR.Set(0x00000000)
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// Set up the clock
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var startupCounter uint32 = 0
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// Enable HSE
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stm32.RCC.CR.Set(stm32.RCC_CR_HSEON)
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// Wait till HSE is ready and if timeout is reached exit
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for {
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startupCounter++
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if stm32.RCC.CR.HasBits(stm32.RCC_CR_HSERDY) || (startupCounter == HSE_STARTUP_TIMEOUT) {
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break
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}
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}
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if stm32.RCC.CR.HasBits(stm32.RCC_CR_HSERDY) {
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// Enable high performance mode, System frequency up to 168MHz
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_PWREN)
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stm32.PWR.CR.SetBits(0x4000) // PWR_CR_VOS
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// HCLK = SYSCLK / 1
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stm32.RCC.CFGR.SetBits(stm32.RCC_CFGR_HPRE_Div1 << stm32.RCC_CFGR_HPRE_Pos)
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// PCLK2 = HCLK / 2
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stm32.RCC.CFGR.SetBits(stm32.RCC_CFGR_PPRE2_Div2 << stm32.RCC_CFGR_PPRE2_Pos)
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// PCLK1 = HCLK / 4
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stm32.RCC.CFGR.SetBits(stm32.RCC_CFGR_PPRE1_Div4 << stm32.RCC_CFGR_PPRE1_Pos)
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// Configure the main PLL
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// PLL Options - See RM0090 Reference Manual pg. 95
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stm32.RCC.PLLCFGR.Set(PLL_M | (PLL_N << 6) | (((PLL_P >> 1) - 1) << 16) |
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(1 << stm32.RCC_PLLCFGR_PLLSRC_Pos) | (PLL_Q << 24))
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// Enable main PLL
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stm32.RCC.CR.SetBits(stm32.RCC_CR_PLLON)
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// Wait till the main PLL is ready
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for (stm32.RCC.CR.Get() & stm32.RCC_CR_PLLRDY) == 0 {
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}
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// Configure Flash prefetch, Instruction cache, Data cache and wait state
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stm32.FLASH.ACR.Set(stm32.FLASH_ACR_ICEN | stm32.FLASH_ACR_DCEN | (5 << stm32.FLASH_ACR_LATENCY_Pos))
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// Select the main PLL as system clock source
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stm32.RCC.CFGR.ClearBits(stm32.RCC_CFGR_SW_Msk)
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stm32.RCC.CFGR.SetBits(stm32.RCC_CFGR_SW_PLL << stm32.RCC_CFGR_SW_Pos)
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for (stm32.RCC.CFGR.Get() & stm32.RCC_CFGR_SWS_Msk) != (stm32.RCC_CFGR_SWS_PLL << stm32.RCC_CFGR_SWS_Pos) {
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}
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} else {
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// If HSE failed to start up, the application will have wrong clock configuration
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for {
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}
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}
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// Enable the CCM RAM clock
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stm32.RCC.AHB1ENR.SetBits(1 << 20)
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}
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