From 5ff76aacabb3cadefde8995a11fb4a12e8acedd0 Mon Sep 17 00:00:00 2001
From: Yannis Huber <yannis.h@hotmail.ch>
Date: Sat, 4 Jul 2020 15:13:44 +0200
Subject: [PATCH] runtime: reuse common code between 32 and 64-bit RISC-V

---
 src/runtime/arch_tinygoriscv.go   | 12 +-----------
 src/runtime/arch_tinygoriscv32.go | 13 +++++++++++++
 src/runtime/arch_tinygoriscv64.go |  6 ------
 3 files changed, 14 insertions(+), 17 deletions(-)
 create mode 100644 src/runtime/arch_tinygoriscv32.go

diff --git a/src/runtime/arch_tinygoriscv.go b/src/runtime/arch_tinygoriscv.go
index 8bd0f076..3dcbcec2 100644
--- a/src/runtime/arch_tinygoriscv.go
+++ b/src/runtime/arch_tinygoriscv.go
@@ -1,19 +1,9 @@
-// +build tinygo.riscv32
+// +build tinygo.riscv
 
 package runtime
 
 import "device/riscv"
 
-const GOARCH = "arm" // riscv pretends to be arm
-
-// The bitness of the CPU (e.g. 8, 32, 64).
-const TargetBits = 32
-
-// Align on word boundary.
-func align(ptr uintptr) uintptr {
-	return (ptr + 3) &^ 3
-}
-
 func getCurrentStackPointer() uintptr {
 	return riscv.AsmFull("mv {}, sp", nil)
 }
diff --git a/src/runtime/arch_tinygoriscv32.go b/src/runtime/arch_tinygoriscv32.go
new file mode 100644
index 00000000..dcae7604
--- /dev/null
+++ b/src/runtime/arch_tinygoriscv32.go
@@ -0,0 +1,13 @@
+// +build tinygo.riscv32
+
+package runtime
+
+const GOARCH = "arm" // riscv pretends to be arm
+
+// The bitness of the CPU (e.g. 8, 32, 64).
+const TargetBits = 32
+
+// Align on word boundary.
+func align(ptr uintptr) uintptr {
+	return (ptr + 3) &^ 3
+}
diff --git a/src/runtime/arch_tinygoriscv64.go b/src/runtime/arch_tinygoriscv64.go
index f17e1dfd..a4a8c14f 100644
--- a/src/runtime/arch_tinygoriscv64.go
+++ b/src/runtime/arch_tinygoriscv64.go
@@ -2,8 +2,6 @@
 
 package runtime
 
-import "device/riscv"
-
 const GOARCH = "arm64" // riscv pretends to be arm
 
 // The bitness of the CPU (e.g. 8, 32, 64).
@@ -13,7 +11,3 @@ const TargetBits = 64
 func align(ptr uintptr) uintptr {
 	return (ptr + 7) &^ 7
 }
-
-func getCurrentStackPointer() uintptr {
-	return riscv.AsmFull("mv {}, sp", nil)
-}