From 75bcbbe6d8d454513fc3524a7a77cceeb0cf37d6 Mon Sep 17 00:00:00 2001
From: Yannis Huber <yannis.h@hotmail.ch>
Date: Tue, 16 Jun 2020 11:28:19 +0200
Subject: [PATCH] riscv: align stack and data sections to 8 bytes

Alignment on 4 bytes can cause load/store address misalignment
exceptions when loading/storing 64bit values on the stack.
---
 targets/riscv.ld | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/targets/riscv.ld b/targets/riscv.ld
index 7f4427a8..6ebee272 100644
--- a/targets/riscv.ld
+++ b/targets/riscv.ld
@@ -18,7 +18,7 @@ SECTIONS
      * See: http://blog.japaric.io/stack-overflow-protection/ */
     .stack (NOLOAD) :
     {
-        . = ALIGN(4);
+        . = ALIGN(8);
         . += _stack_size;
         _stack_top = .;
     } >RAM
@@ -29,25 +29,25 @@ SECTIONS
     /* Globals with initial value */
     .data :
     {
-        . = ALIGN(4);
+        . = ALIGN(8);
         /* see https://gnu-mcu-eclipse.github.io/arch/riscv/programmer/#the-gp-global-pointer-register */
         PROVIDE( __global_pointer$ = . + (4K / 2) );
         _sdata = .;        /* used by startup code */
         *(.sdata)
         *(.data .data.*)
-        . = ALIGN(4);
+        . = ALIGN(8);
         _edata = .;        /* used by startup code */
     } >RAM AT>FLASH_TEXT
 
     /* Zero-initialized globals  */
     .bss :
     {
-        . = ALIGN(4);
+        . = ALIGN(8);
         _sbss = .;         /* used by startup code */
         *(.sbss)
         *(.bss .bss.*)
         *(COMMON)
-        . = ALIGN(4);
+        . = ALIGN(8);
         _ebss = .;         /* used by startup code */
     } >RAM