From 8f9419a35d9e68cc20e88ac19c5a19d39085e7fe Mon Sep 17 00:00:00 2001
From: Ayke van Laethem <aykevanlaethem@gmail.com>
Date: Fri, 29 Nov 2019 22:54:27 +0100
Subject: [PATCH] targets: add hifive1-qemu for testing RISC-V bare metal in
 QEMU

Most tests don't pass yet, so can't add this test to the standard tests,
yet.
---
 src/runtime/runtime_fe310.go           |  8 --------
 src/runtime/runtime_fe310_baremetal.go | 14 ++++++++++++++
 src/runtime/runtime_fe310_qemu.go      | 16 ++++++++++++++++
 targets/hifive1-qemu.json              |  6 ++++++
 targets/hifive1-qemu.ld                | 13 +++++++++++++
 targets/riscv.json                     |  3 ++-
 6 files changed, 51 insertions(+), 9 deletions(-)
 create mode 100644 src/runtime/runtime_fe310_baremetal.go
 create mode 100644 src/runtime/runtime_fe310_qemu.go
 create mode 100644 targets/hifive1-qemu.json
 create mode 100644 targets/hifive1-qemu.ld

diff --git a/src/runtime/runtime_fe310.go b/src/runtime/runtime_fe310.go
index 9f92fd08..cef0efba 100644
--- a/src/runtime/runtime_fe310.go
+++ b/src/runtime/runtime_fe310.go
@@ -9,7 +9,6 @@ import (
 	"machine"
 	"unsafe"
 
-	"device/riscv"
 	"device/sifive"
 )
 
@@ -106,10 +105,3 @@ func sleepTicks(d timeUnit) {
 	for ticks() < target {
 	}
 }
-
-func abort() {
-	// lock up forever
-	for {
-		riscv.Asm("wfi")
-	}
-}
diff --git a/src/runtime/runtime_fe310_baremetal.go b/src/runtime/runtime_fe310_baremetal.go
new file mode 100644
index 00000000..229615da
--- /dev/null
+++ b/src/runtime/runtime_fe310_baremetal.go
@@ -0,0 +1,14 @@
+// +build fe310,!qemu
+
+package runtime
+
+import (
+	"device/riscv"
+)
+
+func abort() {
+	// lock up forever
+	for {
+		riscv.Asm("wfi")
+	}
+}
diff --git a/src/runtime/runtime_fe310_qemu.go b/src/runtime/runtime_fe310_qemu.go
new file mode 100644
index 00000000..bf92ee27
--- /dev/null
+++ b/src/runtime/runtime_fe310_qemu.go
@@ -0,0 +1,16 @@
+// +build fe310,qemu
+
+package runtime
+
+import (
+	"runtime/volatile"
+	"unsafe"
+)
+
+// Special memory-mapped device to exit tests, created by SiFive.
+var testExit = (*volatile.Register32)(unsafe.Pointer(uintptr(0x100000)))
+
+func abort() {
+	// Signal a successful exit.
+	testExit.Set(0x5555)
+}
diff --git a/targets/hifive1-qemu.json b/targets/hifive1-qemu.json
new file mode 100644
index 00000000..9a50cee6
--- /dev/null
+++ b/targets/hifive1-qemu.json
@@ -0,0 +1,6 @@
+{
+	"inherits": ["fe310"],
+	"build-tags": ["hifive1b", "qemu"],
+	"linkerscript": "targets/hifive1-qemu.ld",
+	"emulator": ["qemu-system-riscv32", "-machine", "sifive_e", "-nographic", "-kernel"]
+}
diff --git a/targets/hifive1-qemu.ld b/targets/hifive1-qemu.ld
new file mode 100644
index 00000000..aaafa674
--- /dev/null
+++ b/targets/hifive1-qemu.ld
@@ -0,0 +1,13 @@
+
+/* memory map:
+ * https://github.com/sifive/freedom-e-sdk/blob/v201908-branch/bsp/sifive-hifive1/metal.default.lds
+ */
+MEMORY
+{
+    FLASH_TEXT (rw) : ORIGIN = 0x20400000, LENGTH = 0x1fc00000
+    RAM (xrw)       : ORIGIN = 0x80000000, LENGTH = 0x4000
+}
+
+_stack_size = 2K;
+
+INCLUDE "targets/riscv.ld"
diff --git a/targets/riscv.json b/targets/riscv.json
index 1749d121..e33084ac 100644
--- a/targets/riscv.json
+++ b/targets/riscv.json
@@ -22,5 +22,6 @@
 	],
 	"extra-files": [
 		"src/device/riscv/start.S"
-	]
+	],
+	"gdb": "riscv64-unknown-elf-gdb"
 }