From 90fb0ee4eb321b5c692269ed85843cfb7540ba03 Mon Sep 17 00:00:00 2001 From: Ayke van Laethem Date: Thu, 7 Jun 2018 18:35:54 +0200 Subject: [PATCH] Add AVR support This requires support in LLVM, as AVR support is still experimental. For example, in bindings/go/build.sh, add -DLLVM_EXPERIMENTAL_TARGETS_TO_BUILD=AVR to cmake_flags. --- Makefile | 22 +- avr.S | 62 + avr.ld | 43 + gen-device.py | 125 +- src/device/avr/at90can128.go | 1000 ++++++++++++++++ src/device/avr/at90can128.ld | 6 + src/device/avr/at90can32.go | 1000 ++++++++++++++++ src/device/avr/at90can32.ld | 6 + src/device/avr/at90can64.go | 1000 ++++++++++++++++ src/device/avr/at90can64.ld | 6 + src/device/avr/at90pwm1.go | 841 ++++++++++++++ src/device/avr/at90pwm1.ld | 6 + src/device/avr/at90pwm161.go | 757 ++++++++++++ src/device/avr/at90pwm161.ld | 6 + src/device/avr/at90pwm216.go | 934 +++++++++++++++ src/device/avr/at90pwm216.ld | 6 + src/device/avr/at90pwm2b.go | 970 ++++++++++++++++ src/device/avr/at90pwm2b.ld | 6 + src/device/avr/at90pwm316.go | 1025 +++++++++++++++++ src/device/avr/at90pwm316.ld | 6 + src/device/avr/at90pwm3b.go | 1097 ++++++++++++++++++ src/device/avr/at90pwm3b.ld | 6 + src/device/avr/at90pwm81.go | 832 +++++++++++++ src/device/avr/at90pwm81.ld | 6 + src/device/avr/at90usb1286.go | 952 +++++++++++++++ src/device/avr/at90usb1286.ld | 6 + src/device/avr/at90usb1287.go | 1117 ++++++++++++++++++ src/device/avr/at90usb1287.ld | 6 + src/device/avr/at90usb162.go | 776 +++++++++++++ src/device/avr/at90usb162.ld | 6 + src/device/avr/at90usb646.go | 1117 ++++++++++++++++++ src/device/avr/at90usb646.ld | 6 + src/device/avr/at90usb647.go | 1117 ++++++++++++++++++ src/device/avr/at90usb647.ld | 6 + src/device/avr/at90usb82.go | 776 +++++++++++++ src/device/avr/at90usb82.ld | 6 + src/device/avr/atmega128.go | 676 +++++++++++ src/device/avr/atmega128.ld | 6 + src/device/avr/atmega1280.go | 1090 ++++++++++++++++++ src/device/avr/atmega1280.ld | 6 + src/device/avr/atmega1281.go | 986 ++++++++++++++++ src/device/avr/atmega1281.ld | 6 + src/device/avr/atmega1284.go | 774 +++++++++++++ src/device/avr/atmega1284.ld | 6 + src/device/avr/atmega1284p.go | 870 ++++++++++++++ src/device/avr/atmega1284p.ld | 6 + src/device/avr/atmega1284rfr2.go | 1793 +++++++++++++++++++++++++++++ src/device/avr/atmega1284rfr2.ld | 6 + src/device/avr/atmega128a.go | 666 +++++++++++ src/device/avr/atmega128a.ld | 6 + src/device/avr/atmega128rfa1.go | 1585 +++++++++++++++++++++++++ src/device/avr/atmega128rfa1.ld | 6 + src/device/avr/atmega128rfr2.go | 1768 ++++++++++++++++++++++++++++ src/device/avr/atmega128rfr2.ld | 6 + src/device/avr/atmega16.go | 491 ++++++++ src/device/avr/atmega16.ld | 6 + src/device/avr/atmega162.go | 585 ++++++++++ src/device/avr/atmega162.ld | 6 + src/device/avr/atmega164a.go | 711 ++++++++++++ src/device/avr/atmega164a.ld | 6 + src/device/avr/atmega164p.go | 711 ++++++++++++ src/device/avr/atmega164p.ld | 6 + src/device/avr/atmega164pa.go | 711 ++++++++++++ src/device/avr/atmega164pa.ld | 6 + src/device/avr/atmega165a.go | 605 ++++++++++ src/device/avr/atmega165a.ld | 6 + src/device/avr/atmega165p.go | 605 ++++++++++ src/device/avr/atmega165p.ld | 6 + src/device/avr/atmega165pa.go | 605 ++++++++++ src/device/avr/atmega165pa.ld | 6 + src/device/avr/atmega168.go | 640 ++++++++++ src/device/avr/atmega168.ld | 6 + src/device/avr/atmega168a.go | 641 +++++++++++ src/device/avr/atmega168a.ld | 6 + src/device/avr/atmega168p.go | 642 +++++++++++ src/device/avr/atmega168p.ld | 6 + src/device/avr/atmega168pa.go | 643 +++++++++++ src/device/avr/atmega168pa.ld | 6 + src/device/avr/atmega168pb.go | 685 +++++++++++ src/device/avr/atmega168pb.ld | 6 + src/device/avr/atmega169a.go | 679 +++++++++++ src/device/avr/atmega169a.ld | 6 + src/device/avr/atmega169p.go | 679 +++++++++++ src/device/avr/atmega169p.ld | 6 + src/device/avr/atmega169pa.go | 747 ++++++++++++ src/device/avr/atmega169pa.ld | 6 + src/device/avr/atmega16a.go | 553 +++++++++ src/device/avr/atmega16a.ld | 6 + src/device/avr/atmega16hva.go | 560 +++++++++ src/device/avr/atmega16hva.ld | 6 + src/device/avr/atmega16hvb.go | 796 +++++++++++++ src/device/avr/atmega16hvb.ld | 6 + src/device/avr/atmega16hvbrevb.go | 796 +++++++++++++ src/device/avr/atmega16hvbrevb.ld | 6 + src/device/avr/atmega16m1.go | 1163 +++++++++++++++++++ src/device/avr/atmega16m1.ld | 6 + src/device/avr/atmega16u2.go | 842 ++++++++++++++ src/device/avr/atmega16u2.ld | 6 + src/device/avr/atmega16u4.go | 1137 ++++++++++++++++++ src/device/avr/atmega16u4.ld | 6 + src/device/avr/atmega2560.go | 1090 ++++++++++++++++++ src/device/avr/atmega2560.ld | 6 + src/device/avr/atmega2561.go | 988 ++++++++++++++++ src/device/avr/atmega2561.ld | 6 + src/device/avr/atmega2564rfr2.go | 1768 ++++++++++++++++++++++++++++ src/device/avr/atmega2564rfr2.ld | 6 + src/device/avr/atmega256rfr2.go | 1769 ++++++++++++++++++++++++++++ src/device/avr/atmega256rfr2.ld | 6 + src/device/avr/atmega32.go | 491 ++++++++ src/device/avr/atmega32.ld | 6 + src/device/avr/atmega3208.go | 1291 +++++++++++++++++++++ src/device/avr/atmega3208.ld | 6 + src/device/avr/atmega3209.go | 1305 +++++++++++++++++++++ src/device/avr/atmega3209.ld | 6 + src/device/avr/atmega324a.go | 711 ++++++++++++ src/device/avr/atmega324a.ld | 6 + src/device/avr/atmega324p.go | 711 ++++++++++++ src/device/avr/atmega324p.ld | 6 + src/device/avr/atmega324pa.go | 782 +++++++++++++ src/device/avr/atmega324pa.ld | 6 + src/device/avr/atmega324pb.go | 990 ++++++++++++++++ src/device/avr/atmega324pb.ld | 6 + src/device/avr/atmega325.go | 605 ++++++++++ src/device/avr/atmega325.ld | 6 + src/device/avr/atmega3250.go | 630 ++++++++++ src/device/avr/atmega3250.ld | 6 + src/device/avr/atmega3250a.go | 630 ++++++++++ src/device/avr/atmega3250a.ld | 6 + src/device/avr/atmega3250p.go | 630 ++++++++++ src/device/avr/atmega3250p.ld | 6 + src/device/avr/atmega3250pa.go | 619 ++++++++++ src/device/avr/atmega3250pa.ld | 6 + src/device/avr/atmega325a.go | 606 ++++++++++ src/device/avr/atmega325a.ld | 6 + src/device/avr/atmega325p.go | 606 ++++++++++ src/device/avr/atmega325p.ld | 6 + src/device/avr/atmega325pa.go | 600 ++++++++++ src/device/avr/atmega325pa.ld | 6 + src/device/avr/atmega328.go | 718 ++++++++++++ src/device/avr/atmega328.ld | 6 + src/device/avr/atmega328p.go | 643 +++++++++++ src/device/avr/atmega328p.ld | 6 + src/device/avr/atmega328pb.go | 916 +++++++++++++++ src/device/avr/atmega328pb.ld | 6 + src/device/avr/atmega329.go | 676 +++++++++++ src/device/avr/atmega329.ld | 6 + src/device/avr/atmega3290.go | 708 ++++++++++++ src/device/avr/atmega3290.ld | 6 + src/device/avr/atmega3290a.go | 708 ++++++++++++ src/device/avr/atmega3290a.ld | 6 + src/device/avr/atmega3290p.go | 711 ++++++++++++ src/device/avr/atmega3290p.ld | 6 + src/device/avr/atmega3290pa.go | 699 +++++++++++ src/device/avr/atmega3290pa.ld | 6 + src/device/avr/atmega329a.go | 839 ++++++++++++++ src/device/avr/atmega329a.ld | 6 + src/device/avr/atmega329p.go | 853 ++++++++++++++ src/device/avr/atmega329p.ld | 6 + src/device/avr/atmega329pa.go | 839 ++++++++++++++ src/device/avr/atmega329pa.ld | 6 + src/device/avr/atmega32a.go | 474 ++++++++ src/device/avr/atmega32a.ld | 6 + src/device/avr/atmega32c1.go | 991 ++++++++++++++++ src/device/avr/atmega32c1.ld | 6 + src/device/avr/atmega32hvb.go | 796 +++++++++++++ src/device/avr/atmega32hvb.ld | 6 + src/device/avr/atmega32hvbrevb.go | 683 +++++++++++ src/device/avr/atmega32hvbrevb.ld | 6 + src/device/avr/atmega32m1.go | 1019 ++++++++++++++++ src/device/avr/atmega32m1.ld | 6 + src/device/avr/atmega32u2.go | 789 +++++++++++++ src/device/avr/atmega32u2.ld | 6 + src/device/avr/atmega32u4.go | 1022 ++++++++++++++++ src/device/avr/atmega32u4.ld | 6 + src/device/avr/atmega406.go | 613 ++++++++++ src/device/avr/atmega406.ld | 6 + src/device/avr/atmega48.go | 633 ++++++++++ src/device/avr/atmega48.ld | 6 + src/device/avr/atmega4808.go | 1291 +++++++++++++++++++++ src/device/avr/atmega4808.ld | 6 + src/device/avr/atmega4809.go | 1305 +++++++++++++++++++++ src/device/avr/atmega4809.ld | 6 + src/device/avr/atmega48a.go | 642 +++++++++++ src/device/avr/atmega48a.ld | 6 + src/device/avr/atmega48p.go | 635 ++++++++++ src/device/avr/atmega48p.ld | 6 + src/device/avr/atmega48pa.go | 644 +++++++++++ src/device/avr/atmega48pa.ld | 6 + src/device/avr/atmega48pb.go | 677 +++++++++++ src/device/avr/atmega48pb.ld | 6 + src/device/avr/atmega64.go | 670 +++++++++++ src/device/avr/atmega64.ld | 6 + src/device/avr/atmega640.go | 1079 +++++++++++++++++ src/device/avr/atmega640.ld | 6 + src/device/avr/atmega644.go | 667 +++++++++++ src/device/avr/atmega644.ld | 6 + src/device/avr/atmega644a.go | 710 ++++++++++++ src/device/avr/atmega644a.ld | 6 + src/device/avr/atmega644p.go | 710 ++++++++++++ src/device/avr/atmega644p.ld | 6 + src/device/avr/atmega644pa.go | 710 ++++++++++++ src/device/avr/atmega644pa.ld | 6 + src/device/avr/atmega644rfr2.go | 1760 ++++++++++++++++++++++++++++ src/device/avr/atmega644rfr2.ld | 6 + src/device/avr/atmega645.go | 599 ++++++++++ src/device/avr/atmega645.ld | 6 + src/device/avr/atmega6450.go | 618 ++++++++++ src/device/avr/atmega6450.ld | 6 + src/device/avr/atmega6450a.go | 618 ++++++++++ src/device/avr/atmega6450a.ld | 6 + src/device/avr/atmega6450p.go | 618 ++++++++++ src/device/avr/atmega6450p.ld | 6 + src/device/avr/atmega645a.go | 600 ++++++++++ src/device/avr/atmega645a.ld | 6 + src/device/avr/atmega645p.go | 600 ++++++++++ src/device/avr/atmega645p.ld | 6 + src/device/avr/atmega649.go | 666 +++++++++++ src/device/avr/atmega649.ld | 6 + src/device/avr/atmega6490.go | 692 +++++++++++ src/device/avr/atmega6490.ld | 6 + src/device/avr/atmega6490a.go | 692 +++++++++++ src/device/avr/atmega6490a.ld | 6 + src/device/avr/atmega6490p.go | 692 +++++++++++ src/device/avr/atmega6490p.ld | 6 + src/device/avr/atmega649a.go | 666 +++++++++++ src/device/avr/atmega649a.ld | 6 + src/device/avr/atmega649p.go | 666 +++++++++++ src/device/avr/atmega649p.ld | 6 + src/device/avr/atmega64a.go | 670 +++++++++++ src/device/avr/atmega64a.ld | 6 + src/device/avr/atmega64c1.go | 896 ++++++++++++++ src/device/avr/atmega64c1.ld | 6 + src/device/avr/atmega64hve2.go | 664 +++++++++++ src/device/avr/atmega64hve2.ld | 6 + src/device/avr/atmega64m1.go | 1019 ++++++++++++++++ src/device/avr/atmega64m1.ld | 6 + src/device/avr/atmega64rfr2.go | 1738 ++++++++++++++++++++++++++++ src/device/avr/atmega64rfr2.ld | 6 + src/device/avr/atmega8.go | 463 ++++++++ src/device/avr/atmega8.ld | 6 + src/device/avr/atmega8515.go | 420 +++++++ src/device/avr/atmega8515.ld | 6 + src/device/avr/atmega8535.go | 475 ++++++++ src/device/avr/atmega8535.ld | 6 + src/device/avr/atmega88.go | 640 ++++++++++ src/device/avr/atmega88.ld | 6 + src/device/avr/atmega88a.go | 641 +++++++++++ src/device/avr/atmega88a.ld | 6 + src/device/avr/atmega88p.go | 642 +++++++++++ src/device/avr/atmega88p.ld | 6 + src/device/avr/atmega88pa.go | 643 +++++++++++ src/device/avr/atmega88pa.ld | 6 + src/device/avr/atmega88pb.go | 685 +++++++++++ src/device/avr/atmega88pb.ld | 6 + src/device/avr/atmega8a.go | 463 ++++++++ src/device/avr/atmega8a.ld | 6 + src/device/avr/atmega8hva.go | 560 +++++++++ src/device/avr/atmega8hva.ld | 6 + src/device/avr/atmega8u2.go | 789 +++++++++++++ src/device/avr/atmega8u2.ld | 6 + src/device/avr/avr.go | 9 + src/machine/machine_avr.go | 50 + src/runtime/runtime_avr.go | 109 ++ tgo.go | 3 + 264 files changed, 105721 insertions(+), 3 deletions(-) create mode 100644 avr.S create mode 100644 avr.ld create mode 100644 src/device/avr/at90can128.go create mode 100644 src/device/avr/at90can128.ld create mode 100644 src/device/avr/at90can32.go create mode 100644 src/device/avr/at90can32.ld create mode 100644 src/device/avr/at90can64.go create mode 100644 src/device/avr/at90can64.ld create mode 100644 src/device/avr/at90pwm1.go create mode 100644 src/device/avr/at90pwm1.ld create mode 100644 src/device/avr/at90pwm161.go create mode 100644 src/device/avr/at90pwm161.ld create mode 100644 src/device/avr/at90pwm216.go create mode 100644 src/device/avr/at90pwm216.ld create mode 100644 src/device/avr/at90pwm2b.go create mode 100644 src/device/avr/at90pwm2b.ld create mode 100644 src/device/avr/at90pwm316.go create mode 100644 src/device/avr/at90pwm316.ld create mode 100644 src/device/avr/at90pwm3b.go create mode 100644 src/device/avr/at90pwm3b.ld create mode 100644 src/device/avr/at90pwm81.go create mode 100644 src/device/avr/at90pwm81.ld create mode 100644 src/device/avr/at90usb1286.go create mode 100644 src/device/avr/at90usb1286.ld create mode 100644 src/device/avr/at90usb1287.go create mode 100644 src/device/avr/at90usb1287.ld create mode 100644 src/device/avr/at90usb162.go create mode 100644 src/device/avr/at90usb162.ld create mode 100644 src/device/avr/at90usb646.go create mode 100644 src/device/avr/at90usb646.ld create mode 100644 src/device/avr/at90usb647.go create mode 100644 src/device/avr/at90usb647.ld create mode 100644 src/device/avr/at90usb82.go create mode 100644 src/device/avr/at90usb82.ld create mode 100644 src/device/avr/atmega128.go create mode 100644 src/device/avr/atmega128.ld create mode 100644 src/device/avr/atmega1280.go create mode 100644 src/device/avr/atmega1280.ld create mode 100644 src/device/avr/atmega1281.go create mode 100644 src/device/avr/atmega1281.ld create mode 100644 src/device/avr/atmega1284.go create mode 100644 src/device/avr/atmega1284.ld create mode 100644 src/device/avr/atmega1284p.go create mode 100644 src/device/avr/atmega1284p.ld create mode 100644 src/device/avr/atmega1284rfr2.go create mode 100644 src/device/avr/atmega1284rfr2.ld create mode 100644 src/device/avr/atmega128a.go create mode 100644 src/device/avr/atmega128a.ld create mode 100644 src/device/avr/atmega128rfa1.go create mode 100644 src/device/avr/atmega128rfa1.ld create mode 100644 src/device/avr/atmega128rfr2.go create mode 100644 src/device/avr/atmega128rfr2.ld create mode 100644 src/device/avr/atmega16.go create mode 100644 src/device/avr/atmega16.ld create mode 100644 src/device/avr/atmega162.go create mode 100644 src/device/avr/atmega162.ld create mode 100644 src/device/avr/atmega164a.go create mode 100644 src/device/avr/atmega164a.ld create mode 100644 src/device/avr/atmega164p.go create mode 100644 src/device/avr/atmega164p.ld create mode 100644 src/device/avr/atmega164pa.go create mode 100644 src/device/avr/atmega164pa.ld create mode 100644 src/device/avr/atmega165a.go create mode 100644 src/device/avr/atmega165a.ld create mode 100644 src/device/avr/atmega165p.go create mode 100644 src/device/avr/atmega165p.ld create mode 100644 src/device/avr/atmega165pa.go create mode 100644 src/device/avr/atmega165pa.ld create mode 100644 src/device/avr/atmega168.go create mode 100644 src/device/avr/atmega168.ld create mode 100644 src/device/avr/atmega168a.go create mode 100644 src/device/avr/atmega168a.ld create mode 100644 src/device/avr/atmega168p.go create mode 100644 src/device/avr/atmega168p.ld create mode 100644 src/device/avr/atmega168pa.go create mode 100644 src/device/avr/atmega168pa.ld create mode 100644 src/device/avr/atmega168pb.go create mode 100644 src/device/avr/atmega168pb.ld create mode 100644 src/device/avr/atmega169a.go create mode 100644 src/device/avr/atmega169a.ld create mode 100644 src/device/avr/atmega169p.go create mode 100644 src/device/avr/atmega169p.ld create mode 100644 src/device/avr/atmega169pa.go create mode 100644 src/device/avr/atmega169pa.ld create mode 100644 src/device/avr/atmega16a.go create mode 100644 src/device/avr/atmega16a.ld create mode 100644 src/device/avr/atmega16hva.go create mode 100644 src/device/avr/atmega16hva.ld create mode 100644 src/device/avr/atmega16hvb.go create mode 100644 src/device/avr/atmega16hvb.ld create mode 100644 src/device/avr/atmega16hvbrevb.go create mode 100644 src/device/avr/atmega16hvbrevb.ld create mode 100644 src/device/avr/atmega16m1.go create mode 100644 src/device/avr/atmega16m1.ld create mode 100644 src/device/avr/atmega16u2.go create mode 100644 src/device/avr/atmega16u2.ld create mode 100644 src/device/avr/atmega16u4.go create mode 100644 src/device/avr/atmega16u4.ld create mode 100644 src/device/avr/atmega2560.go create mode 100644 src/device/avr/atmega2560.ld create mode 100644 src/device/avr/atmega2561.go create mode 100644 src/device/avr/atmega2561.ld create mode 100644 src/device/avr/atmega2564rfr2.go create mode 100644 src/device/avr/atmega2564rfr2.ld create mode 100644 src/device/avr/atmega256rfr2.go create mode 100644 src/device/avr/atmega256rfr2.ld create mode 100644 src/device/avr/atmega32.go create mode 100644 src/device/avr/atmega32.ld create mode 100644 src/device/avr/atmega3208.go create mode 100644 src/device/avr/atmega3208.ld create mode 100644 src/device/avr/atmega3209.go create mode 100644 src/device/avr/atmega3209.ld create mode 100644 src/device/avr/atmega324a.go create mode 100644 src/device/avr/atmega324a.ld create mode 100644 src/device/avr/atmega324p.go create mode 100644 src/device/avr/atmega324p.ld create mode 100644 src/device/avr/atmega324pa.go create mode 100644 src/device/avr/atmega324pa.ld create mode 100644 src/device/avr/atmega324pb.go create mode 100644 src/device/avr/atmega324pb.ld create mode 100644 src/device/avr/atmega325.go create mode 100644 src/device/avr/atmega325.ld create mode 100644 src/device/avr/atmega3250.go create mode 100644 src/device/avr/atmega3250.ld create mode 100644 src/device/avr/atmega3250a.go create mode 100644 src/device/avr/atmega3250a.ld create mode 100644 src/device/avr/atmega3250p.go create mode 100644 src/device/avr/atmega3250p.ld create mode 100644 src/device/avr/atmega3250pa.go create mode 100644 src/device/avr/atmega3250pa.ld create mode 100644 src/device/avr/atmega325a.go create mode 100644 src/device/avr/atmega325a.ld create mode 100644 src/device/avr/atmega325p.go create mode 100644 src/device/avr/atmega325p.ld create mode 100644 src/device/avr/atmega325pa.go create mode 100644 src/device/avr/atmega325pa.ld create mode 100644 src/device/avr/atmega328.go create mode 100644 src/device/avr/atmega328.ld create mode 100644 src/device/avr/atmega328p.go create mode 100644 src/device/avr/atmega328p.ld create mode 100644 src/device/avr/atmega328pb.go create mode 100644 src/device/avr/atmega328pb.ld create mode 100644 src/device/avr/atmega329.go create mode 100644 src/device/avr/atmega329.ld create mode 100644 src/device/avr/atmega3290.go create mode 100644 src/device/avr/atmega3290.ld create mode 100644 src/device/avr/atmega3290a.go create mode 100644 src/device/avr/atmega3290a.ld create mode 100644 src/device/avr/atmega3290p.go create mode 100644 src/device/avr/atmega3290p.ld create mode 100644 src/device/avr/atmega3290pa.go create mode 100644 src/device/avr/atmega3290pa.ld create mode 100644 src/device/avr/atmega329a.go create mode 100644 src/device/avr/atmega329a.ld create mode 100644 src/device/avr/atmega329p.go create mode 100644 src/device/avr/atmega329p.ld create mode 100644 src/device/avr/atmega329pa.go create mode 100644 src/device/avr/atmega329pa.ld create mode 100644 src/device/avr/atmega32a.go create mode 100644 src/device/avr/atmega32a.ld create mode 100644 src/device/avr/atmega32c1.go create mode 100644 src/device/avr/atmega32c1.ld create mode 100644 src/device/avr/atmega32hvb.go create mode 100644 src/device/avr/atmega32hvb.ld create mode 100644 src/device/avr/atmega32hvbrevb.go create mode 100644 src/device/avr/atmega32hvbrevb.ld create mode 100644 src/device/avr/atmega32m1.go create mode 100644 src/device/avr/atmega32m1.ld create mode 100644 src/device/avr/atmega32u2.go create mode 100644 src/device/avr/atmega32u2.ld create mode 100644 src/device/avr/atmega32u4.go create mode 100644 src/device/avr/atmega32u4.ld create mode 100644 src/device/avr/atmega406.go create mode 100644 src/device/avr/atmega406.ld create mode 100644 src/device/avr/atmega48.go create mode 100644 src/device/avr/atmega48.ld create mode 100644 src/device/avr/atmega4808.go create mode 100644 src/device/avr/atmega4808.ld create mode 100644 src/device/avr/atmega4809.go create mode 100644 src/device/avr/atmega4809.ld create mode 100644 src/device/avr/atmega48a.go create mode 100644 src/device/avr/atmega48a.ld create mode 100644 src/device/avr/atmega48p.go create mode 100644 src/device/avr/atmega48p.ld create mode 100644 src/device/avr/atmega48pa.go create mode 100644 src/device/avr/atmega48pa.ld create mode 100644 src/device/avr/atmega48pb.go create mode 100644 src/device/avr/atmega48pb.ld create mode 100644 src/device/avr/atmega64.go create mode 100644 src/device/avr/atmega64.ld create mode 100644 src/device/avr/atmega640.go create mode 100644 src/device/avr/atmega640.ld create mode 100644 src/device/avr/atmega644.go create mode 100644 src/device/avr/atmega644.ld create mode 100644 src/device/avr/atmega644a.go create mode 100644 src/device/avr/atmega644a.ld create mode 100644 src/device/avr/atmega644p.go create mode 100644 src/device/avr/atmega644p.ld create mode 100644 src/device/avr/atmega644pa.go create mode 100644 src/device/avr/atmega644pa.ld create mode 100644 src/device/avr/atmega644rfr2.go create mode 100644 src/device/avr/atmega644rfr2.ld create mode 100644 src/device/avr/atmega645.go create mode 100644 src/device/avr/atmega645.ld create mode 100644 src/device/avr/atmega6450.go create mode 100644 src/device/avr/atmega6450.ld create mode 100644 src/device/avr/atmega6450a.go create mode 100644 src/device/avr/atmega6450a.ld create mode 100644 src/device/avr/atmega6450p.go create mode 100644 src/device/avr/atmega6450p.ld create mode 100644 src/device/avr/atmega645a.go create mode 100644 src/device/avr/atmega645a.ld create mode 100644 src/device/avr/atmega645p.go create mode 100644 src/device/avr/atmega645p.ld create mode 100644 src/device/avr/atmega649.go create mode 100644 src/device/avr/atmega649.ld create mode 100644 src/device/avr/atmega6490.go create mode 100644 src/device/avr/atmega6490.ld create mode 100644 src/device/avr/atmega6490a.go create mode 100644 src/device/avr/atmega6490a.ld create mode 100644 src/device/avr/atmega6490p.go create mode 100644 src/device/avr/atmega6490p.ld create mode 100644 src/device/avr/atmega649a.go create mode 100644 src/device/avr/atmega649a.ld create mode 100644 src/device/avr/atmega649p.go create mode 100644 src/device/avr/atmega649p.ld create mode 100644 src/device/avr/atmega64a.go create mode 100644 src/device/avr/atmega64a.ld create mode 100644 src/device/avr/atmega64c1.go create mode 100644 src/device/avr/atmega64c1.ld create mode 100644 src/device/avr/atmega64hve2.go create mode 100644 src/device/avr/atmega64hve2.ld create mode 100644 src/device/avr/atmega64m1.go create mode 100644 src/device/avr/atmega64m1.ld create mode 100644 src/device/avr/atmega64rfr2.go create mode 100644 src/device/avr/atmega64rfr2.ld create mode 100644 src/device/avr/atmega8.go create mode 100644 src/device/avr/atmega8.ld create mode 100644 src/device/avr/atmega8515.go create mode 100644 src/device/avr/atmega8515.ld create mode 100644 src/device/avr/atmega8535.go create mode 100644 src/device/avr/atmega8535.ld create mode 100644 src/device/avr/atmega88.go create mode 100644 src/device/avr/atmega88.ld create mode 100644 src/device/avr/atmega88a.go create mode 100644 src/device/avr/atmega88a.ld create mode 100644 src/device/avr/atmega88p.go create mode 100644 src/device/avr/atmega88p.ld create mode 100644 src/device/avr/atmega88pa.go create mode 100644 src/device/avr/atmega88pa.ld create mode 100644 src/device/avr/atmega88pb.go create mode 100644 src/device/avr/atmega88pb.ld create mode 100644 src/device/avr/atmega8a.go create mode 100644 src/device/avr/atmega8a.ld create mode 100644 src/device/avr/atmega8hva.go create mode 100644 src/device/avr/atmega8hva.ld create mode 100644 src/device/avr/atmega8u2.go create mode 100644 src/device/avr/atmega8u2.ld create mode 100644 src/device/avr/avr.go create mode 100644 src/machine/machine_avr.go create mode 100644 src/runtime/runtime_avr.go diff --git a/Makefile b/Makefile index 97e0f0a1..ced7634b 100644 --- a/Makefile +++ b/Makefile @@ -3,7 +3,7 @@ all: tgo tgo: build/tgo -.PHONY: all tgo run-hello run-blinky flash-blinky clean gen-device gen-device-nrf +.PHONY: all tgo run-hello run-blinky clean gen-device gen-device-nrf # Custom LLVM toolchain. LLVM := $(shell go env GOPATH)/src/github.com/aykevl/llvm/bindings/go/llvm/workdir/llvm_build/bin/ @@ -43,6 +43,16 @@ RUNTIME_PARTS += build/runtime_nrf.bc RUNTIME_PARTS += build/nrfx_system_nrf52.bc OBJ += build/nrfx_startup_nrf51.o # TODO nrf52, see https://bugs.llvm.org/show_bug.cgi?id=31601 +else ifeq ($(TARGET),arduino) +GCC = avr-gcc +AS = avr-as -mmcu=atmega328p +LD = avr-ld -T avr.ld --gc-sections +SIZE = avr-size +OBJCOPY = avr-objcopy +LLFLAGS += -target avr8-- +TGOFLAGS += -target $(TARGET) +OBJ += build/avr.o + else $(error Unknown target) @@ -56,8 +66,13 @@ run-hello: build/hello run-blinky: build/blinky ./build/blinky -flash-blinky: build/blinky.hex +ifeq ($(TARGET),pca10040) +flash-%: build/%.hex nrfjprog -f nrf52 --sectorerase --program $< --reset +else ifeq ($(TARGET),arduino) +flash-%: build/%.hex + avrdude -c arduino -p atmega328p -P /dev/ttyACM0 -U flash:w:$< +endif clean: @rm -rf build @@ -102,6 +117,9 @@ build/nrfx_%.o: lib/nrfx/mdk/gcc_%.S @mkdir -p build clang $(CFLAGS) -D__STARTUP_CLEAR_BSS -c -o $@ $^ +build/%.o: %.S + $(AS) -o $@ $^ + # Merge all runtime LLVM files together in a single bitcode file. build/runtime-$(TARGET)-combined.bc: $(RUNTIME_PARTS) $(LINK) -o $@ $^ diff --git a/avr.S b/avr.S new file mode 100644 index 00000000..96252759 --- /dev/null +++ b/avr.S @@ -0,0 +1,62 @@ +.section .isr +isr: + rjmp reset + +.org 0x18 ; WDT + rjmp wdt + +; Startup code +.section .reset +.org 26 +reset: + clr r1 ; r1 is expected to be 0 by the C calling convention + + ; Zero .bss +clear_bss: + ldi xl, lo8(_sbss) + ldi xh, hi8(_sbss) +clear_bss_loop: + ldi yl, lo8(_ebss) + ldi yh, hi8(_ebss) + cp xl, yl ; if x == y + cpc xh, yh + breq clear_bss_end + st x+, r1 ; zero byte in *x + rjmp clear_bss_loop +clear_bss_end: + + ; Set up the stack pointer. + ldi xl, lo8(_stack_top) + ldi xh, hi8(_stack_top) + out 0x3d, xl; SPL + out 0x3e, xh; SPH + + ; Enable interrupts. + ; TODO: make sure interrupts are started after all initializers have run. + sei + + ; main will be placed right after here by the linker script so there's no + ; need to jump. + + +; The only thing this WDT handler really does is disable itself, to get out of +; sleep mode. +.section .text.wdt +wdt: + push r16 + + clr r16 + wdr ; Reset watchdog + out 0x34, r16 ; Clear reset reason (MCUSR) + + ; part 1: set WDCE and WDE to enable editing WDTCSR + lds r16, 0x60 ; r16 = WDTCSR + ori r16, 0x18 ; r16 |= WDCE | WDE + sts 0x60, r16 ; WDTCSR = r16 + + ; part 2: within 4 clock cycles, set the new value for WDTCSR + clr r16 + sts 0x60, r16 ; WDTCSR = 0 + + pop r16 + reti diff --git a/avr.ld b/avr.ld new file mode 100644 index 00000000..a26e0003 --- /dev/null +++ b/avr.ld @@ -0,0 +1,43 @@ + +MEMORY +{ + FLASH_TEXT (rw) : ORIGIN = 0, LENGTH = 32256 + RAM (xrw) : ORIGIN = 0, LENGTH = 2K +} + +_stack_size = 512; + +SECTIONS +{ + .text : + { + KEEP(*(.isr)) + KEEP(*(.reset)) + KEEP(*(.text.main)) /* main must follow the reset handler */ + *(.text.*) + *(.rodata) + *(.rodata.*) + } + + .stack : + { + . += _stack_size; + _stack_top = .; + } >RAM + + .data : + { + *(.data) + *(.data*) + } >RAM AT>FLASH_TEXT + + .bss : + { + _sbss = .; + *(.bss) + *(.bss*) + *(COMMON) + _ebss = .; + _heap_start = .; + } >RAM +} diff --git a/gen-device.py b/gen-device.py index 1f2e449a..179c400a 100755 --- a/gen-device.py +++ b/gen-device.py @@ -143,6 +143,110 @@ def parseSVDRegister(peripheralName, regEl, baseAddress, namePrefix=''): 'array': array, } +def readATDF(path): + # Read Atmel device descriptor files. + # See: http://packs.download.atmel.com + + device = Device() + + xml = minidom.parse(path) + device = xml.getElementsByTagName('device')[0] + deviceName = device.getAttribute('name') + arch = device.getAttribute('architecture') + family = device.getAttribute('family') + + memorySizes = {} + for el in device.getElementsByTagName('address-space'): + addressSpace = { + 'size': int(el.getAttribute('size'), 0), + 'segments': {}, + } + memorySizes[el.getAttribute('name')] = addressSpace + for segmentEl in el.getElementsByTagName('memory-segment'): + addressSpace['segments'][segmentEl.getAttribute('name')] = int(segmentEl.getAttribute('size'), 0) + + device.interrupts = [] + for el in device.getElementsByTagName('interrupts')[0].getElementsByTagName('interrupt'): + device.interrupts.append({ + 'index': int(el.getAttribute('index')), + 'name': el.getAttribute('name'), + 'description': el.getAttribute('caption'), + }) + + allRegisters = {} + commonRegisters = {} + + device.peripherals = [] + for el in xml.getElementsByTagName('modules')[0].getElementsByTagName('module'): + peripheral = { + 'name': el.getAttribute('name'), + 'description': el.getAttribute('caption'), + 'registers': [], + } + device.peripherals.append(peripheral) + for regElGroup in el.getElementsByTagName('register-group'): + for regEl in regElGroup.getElementsByTagName('register'): + size = int(regEl.getAttribute('size')) + regName = regEl.getAttribute('name') + regOffset = int(regEl.getAttribute('offset'), 0) + reg = { + 'description': regEl.getAttribute('caption'), + 'bitfields': [], + 'array': None, + } + if size == 1: + reg['variants'] = [{ + 'name': regName, + 'address': regOffset, + }] + elif size == 2: + reg['variants'] = [{ + 'name': regName + 'L', + 'address': regOffset, + }, { + 'name': regName + 'H', + 'address': regOffset, + }] + else: + reg['variants'] = [] # TODO + + for bitfieldEl in regEl.getElementsByTagName('bitfield'): + reg['bitfields'].append({ + 'name': regName + '_' + bitfieldEl.getAttribute('name'), + 'description': bitfieldEl.getAttribute('caption'), + 'value': int(bitfieldEl.getAttribute('mask'), 0), + }) + + if regName in allRegisters: + firstReg = allRegisters[regName] + if firstReg['register'] in firstReg['peripheral']['registers']: + firstReg['peripheral']['registers'].remove(firstReg['register']) + if firstReg['address'] != regOffset: + continue # TODO + commonRegisters = allRegisters[regName]['register'] + continue + else: + allRegisters[regName] = {'address': regOffset, 'register': reg, 'peripheral': peripheral} + + peripheral['registers'].append(reg) + + device.metadata = { + 'file': os.path.basename(path), + 'descriptorSource': 'http://packs.download.atmel.com/', + 'name': deviceName, + 'nameLower': deviceName.lower(), + 'description': 'Device information for the {}.'.format(deviceName), + 'licenseBlock': '', + 'regType': 'uint8', + 'arch': arch, + 'family': family, + 'flashSize': memorySizes['prog']['size'], + 'ramSize': memorySizes['data']['segments'].get('IRAM', memorySizes['data']['segments'].get('INTERNAL_SRAM')), + 'numInterrupts': len(device.interrupts), + } + + return device + def writeGo(outdir, device): # The Go module for this device. out = open(outdir + '/' + device.metadata['nameLower'] + '.go', 'w') @@ -224,6 +328,19 @@ const ( out.write('\n') out.write(')\n') +def writeLD(outdir, device): + # Variables for the linker script. + out = open(outdir + '/' + device.metadata['nameLower'] + '.ld', 'w') + out.write('''\ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from {file}, see {descriptorSource} */ + +__flash_size = 0x{flashSize:x}; +__ram_size = 0x{ramSize:x}; +__num_isrs = {numInterrupts}; +'''.format(**device.metadata)) + out.close() + def generate(indir, outdir): for filepath in glob(indir + '/*.svd'): @@ -231,8 +348,14 @@ def generate(indir, outdir): device = readSVD(filepath) writeGo(outdir, device) + for filepath in glob(indir + '/*.atdf'): + print(filepath) + device = readATDF(filepath) + writeGo(outdir, device) + writeLD(outdir, device) + if __name__ == '__main__': - indir = sys.argv[1] # directory with register descriptor files (*.svd) + indir = sys.argv[1] # directory with register descriptor files (*.svd, *.atdf) outdir = sys.argv[2] # output directory generate(indir, outdir) diff --git a/src/device/avr/at90can128.go b/src/device/avr/at90can128.go new file mode 100644 index 00000000..00f02a0f --- /dev/null +++ b/src/device/avr/at90can128.go @@ -0,0 +1,1000 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from AT90CAN128.atdf, see http://packs.download.atmel.com/ + +// +build avr,at90can128 + +// Device information for the AT90CAN128. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "AT90CAN128" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_INT3 = 4 // External Interrupt Request 3 + IRQ_INT4 = 5 // External Interrupt Request 4 + IRQ_INT5 = 6 // External Interrupt Request 5 + IRQ_INT6 = 7 // External Interrupt Request 6 + IRQ_INT7 = 8 // External Interrupt Request 7 + IRQ_TIMER2_COMP = 9 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 10 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 11 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 12 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 13 // Timer/Counter Compare Match B + IRQ_TIMER1_COMPC = 14 // Timer/Counter1 Compare Match C + IRQ_TIMER1_OVF = 15 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 16 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 17 // Timer/Counter0 Overflow + IRQ_CANIT = 18 // CAN Transfer Complete or Error + IRQ_OVRIT = 19 // CAN Timer Overrun + IRQ_SPI_STC = 20 // SPI Serial Transfer Complete + IRQ_USART0_RX = 21 // USART0, Rx Complete + IRQ_USART0_UDRE = 22 // USART0 Data Register Empty + IRQ_USART0_TX = 23 // USART0, Tx Complete + IRQ_ANALOG_COMP = 24 // Analog Comparator + IRQ_ADC = 25 // ADC Conversion Complete + IRQ_EE_READY = 26 // EEPROM Ready + IRQ_TIMER3_CAPT = 27 // Timer/Counter3 Capture Event + IRQ_TIMER3_COMPA = 28 // Timer/Counter3 Compare Match A + IRQ_TIMER3_COMPB = 29 // Timer/Counter3 Compare Match B + IRQ_TIMER3_COMPC = 30 // Timer/Counter3 Compare Match C + IRQ_TIMER3_OVF = 31 // Timer/Counter3 Overflow + IRQ_USART1_RX = 32 // USART1, Rx Complete + IRQ_USART1_UDRE = 33 // USART1, Data Register Empty + IRQ_USART1_TX = 34 // USART1, Tx Complete + IRQ_TWI = 35 // 2-wire Serial Interface + IRQ_SPM_READY = 36 // Store Program Memory Read + IRQ_max = 36 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + PORTG: 0x34, // Data Register, Port G + DDRG: 0x33, // Data Direction Register, Port G + PING: 0x32, // Input Pins, Port G + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // Two Wire Serial Interface + TWI = struct { + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + UDR1 __reg + UCSR1A __reg + UCSR1B __reg + UCSR1C __reg + UBRR1L __reg + UBRR1H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register t Bytes + UBRR0H: 0xc4, // USART Baud Rate Register t Bytes + UDR1: 0xce, // USART I/O Data Register + UCSR1A: 0xc8, // USART Control and Status Register A + UCSR1B: 0xc9, // USART Control and Status Register B + UCSR1C: 0xca, // USART Control and Status Register C + UBRR1L: 0xcc, // USART Baud Rate Register t Bytes + UBRR1H: 0xcc, // USART Baud Rate Register t Bytes + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + XMCRA __reg + XMCRB __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + RAMPZ __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + XMCRA: 0x74, // External Memory Control Register A + XMCRB: 0x75, // External Memory Control Register B + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + SMCR: 0x53, // Sleep Mode Control Register + RAMPZ: 0x5b, // RAM Page Z Select Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EICRB __reg + EIMSK __reg + EIFR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EICRB: 0x6a, // External Interrupt Control Register B + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access Bytes + EEARH: 0x41, // EEPROM Read/Write Access Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0A __reg + TCNT0 __reg + OCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR0A: 0x44, // Timer/Counter0 Control Register + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + OCR1CL __reg + OCR1CH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + TCCR3A __reg + TCCR3B __reg + TCCR3C __reg + TCNT3L __reg + TCNT3H __reg + OCR3AL __reg + OCR3AH __reg + OCR3BL __reg + OCR3BH __reg + OCR3CL __reg + OCR3CH __reg + ICR3L __reg + ICR3H __reg + TIMSK3 __reg + TIFR3 __reg + }{ + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register Bytes + OCR1CL: 0x8c, // Timer/Counter1 Output Compare Register Bytes + OCR1CH: 0x8c, // Timer/Counter1 Output Compare Register Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR3A: 0x90, // Timer/Counter3 Control Register A + TCCR3B: 0x91, // Timer/Counter3 Control Register B + TCCR3C: 0x92, // Timer/Counter 3 Control Register C + TCNT3L: 0x94, // Timer/Counter3 Bytes + TCNT3H: 0x94, // Timer/Counter3 Bytes + OCR3AL: 0x98, // Timer/Counter3 Output Compare Register Bytes + OCR3AH: 0x98, // Timer/Counter3 Output Compare Register Bytes + OCR3BL: 0x9a, // Timer/Counter3 Output Compare Register Bytes + OCR3BH: 0x9a, // Timer/Counter3 Output Compare Register Bytes + OCR3CL: 0x9c, // Timer/Counter3 Output Compare Register Bytes + OCR3CH: 0x9c, // Timer/Counter3 Output Compare Register Bytes + ICR3L: 0x96, // Timer/Counter3 Input Capture Register Bytes + ICR3H: 0x96, // Timer/Counter3 Input Capture Register Bytes + TIMSK3: 0x71, // Timer/Counter Interrupt Mask Register + TIFR3: 0x38, // Timer/Counter Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2A __reg + TCNT2 __reg + OCR2A __reg + TIMSK2 __reg + TIFR2 __reg + ASSR __reg + }{ + TCCR2A: 0xb0, // Timer/Counter2 Control Register + TCNT2: 0xb2, // Timer/Counter2 + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x60, // Watchdog Timer Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 1 + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, + } + + // Controller Area Network + CAN = struct { + CANGCON __reg + CANGSTA __reg + CANGIT __reg + CANGIE __reg + CANEN2 __reg + CANEN1 __reg + CANIE2 __reg + CANIE1 __reg + CANSIT2 __reg + CANSIT1 __reg + CANBT1 __reg + CANBT2 __reg + CANBT3 __reg + CANTCON __reg + CANTIML __reg + CANTIMH __reg + CANTTCL __reg + CANTTCH __reg + CANTEC __reg + CANREC __reg + CANHPMOB __reg + CANPAGE __reg + CANSTMOB __reg + CANCDMOB __reg + CANIDT4 __reg + CANIDT3 __reg + CANIDT2 __reg + CANIDT1 __reg + CANIDM4 __reg + CANIDM3 __reg + CANIDM2 __reg + CANIDM1 __reg + CANSTML __reg + CANSTMH __reg + CANMSG __reg + }{ + CANGCON: 0xd8, // CAN General Control Register + CANGSTA: 0xd9, // CAN General Status Register + CANGIT: 0xda, // CAN General Interrupt Register + CANGIE: 0xdb, // CAN General Interrupt Enable Register + CANEN2: 0xdc, // Enable MOb Register + CANEN1: 0xdd, // Enable MOb Register + CANIE2: 0xde, // Enable Interrupt MOb Register + CANIE1: 0xdf, // Enable Interrupt MOb Register + CANSIT2: 0xe0, // CAN Status Interrupt MOb Register + CANSIT1: 0xe1, // CAN Status Interrupt MOb Register + CANBT1: 0xe2, // Bit Timing Register 1 + CANBT2: 0xe3, // Bit Timing Register 2 + CANBT3: 0xe4, // Bit Timing Register 3 + CANTCON: 0xe5, // Timer Control Register + CANTIML: 0xe6, // Timer Register + CANTIMH: 0xe6, // Timer Register + CANTTCL: 0xe8, // TTC Timer Register + CANTTCH: 0xe8, // TTC Timer Register + CANTEC: 0xea, // Transmit Error Counter Register + CANREC: 0xeb, // Receive Error Counter Register + CANHPMOB: 0xec, // Highest Priority MOb Register + CANPAGE: 0xed, // Page MOb Register + CANSTMOB: 0xee, // MOb Status Register + CANCDMOB: 0xef, // MOb Control and DLC Register + CANIDT4: 0xf0, // Identifier Tag Register 4 + CANIDT3: 0xf1, // Identifier Tag Register 3 + CANIDT2: 0xf2, // Identifier Tag Register 2 + CANIDT1: 0xf3, // Identifier Tag Register 1 + CANIDM4: 0xf4, // Identifier Mask Register 4 + CANIDM3: 0xf5, // Identifier Mask Register 3 + CANIDM2: 0xf6, // Identifier Mask Register 2 + CANIDM1: 0xf7, // Identifier Mask Register 1 + CANSTML: 0xf8, // Time Stamp Register + CANSTMH: 0xf8, // Time Stamp Register + CANMSG: 0xfa, // Message Data Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0xe // Brown-out Detector trigger level + EXTENDED_TA0SEL = 0x1 // Reserved for factory tests + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally; [CKDIV8=0] + LOW_CKOUT = 0x40 // Clock output on PORTC7; [CKOUT=0] + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPDR: SPI Data Register + SPDR_SPD = 0xff // SPI Data Register +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0x40 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity + + // UCSR1A: USART Control and Status Register A + UCSR1A_RXC1 = 0x80 // USART Receive Complete + UCSR1A_TXC1 = 0x40 // USART Transmitt Complete + UCSR1A_UDRE1 = 0x20 // USART Data Register Empty + UCSR1A_FE1 = 0x10 // Framing Error + UCSR1A_DOR1 = 0x8 // Data overRun + UCSR1A_UPE1 = 0x4 // Parity Error + UCSR1A_U2X1 = 0x2 // Double the USART transmission speed + UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode + + // UCSR1B: USART Control and Status Register B + UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable + UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable + UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable + UCSR1B_RXEN1 = 0x10 // Receiver Enable + UCSR1B_TXEN1 = 0x8 // Transmitter Enable + UCSR1B_UCSZ12 = 0x4 // Character Size + UCSR1B_RXB81 = 0x2 // Receive Data Bit 8 + UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8 + + // UCSR1C: USART Control and Status Register C + UCSR1C_UMSEL1 = 0x40 // USART Mode Select + UCSR1C_UPM1 = 0x30 // Parity Mode Bits + UCSR1C_USBS1 = 0x8 // Stop Bit Select + UCSR1C_UCSZ1 = 0x6 // Character Size + UCSR1C_UCPOL1 = 0x1 // Clock Polarity +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // XMCRA: External Memory Control Register A + XMCRA_SRE = 0x80 // External SRAM Enable + XMCRA_SRL = 0x70 // Wait state page limit + XMCRA_SRW1 = 0xc // Wait state select bit upper page + XMCRA_SRW0 = 0x3 // Wait state select bit lower page + + // XMCRB: External Memory Control Register B + XMCRB_XMBK = 0x80 // External Memory Bus Keeper Enable + XMCRB_XMM = 0x7 // External Memory High Mask + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // RAMPZ: RAM Page Z Select Register + RAMPZ_RAMPZ0 = 0x1 // RAM Page Z Select Register Bit 0 + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EICRB: External Interrupt Control Register B + EICRB_ISC7 = 0xc0 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC6 = 0x30 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC5 = 0xc // External Interrupt 7-4 Sense Control Bit + EICRB_ISC4 = 0x3 // External Interrupt 7-4 Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xff // External Interrupt Request 7 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xff // External Interrupt Flags +) + +// Bitfields for EEPROM: EEPROM +const ( + // EEARL: EEPROM Read/Write Access Bytes + + // EEARH: EEPROM Read/Write Access Bytes + EEAR_EEAR = 0xfff // EEPROM Address bits + + // EEDR: EEPROM Data Register + EEDR_EEDR = 0xff // EEPROM Data bits + + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0A: Timer/Counter0 Control Register + TCCR0A_FOC0A = 0x80 // Force Output Compare + TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0A_COM0A = 0x30 // Compare Match Output Modes + TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0A_CS0 = 0x7 // Clock Selects + + // OCR0A: Timer/Counter0 Output Compare Register + OCR0A_OCR0A = 0xff // Output Compare A bits + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0 + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_COM1C = 0xc // Compare Output Mode 1C, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + TCCR1C_FOC1C = 0x20 // Force Output Compare 1C + + // TIMSK1: Timer/Counter Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1C = 0x8 // Timer/Counter1 Output CompareC Match Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output CompareB Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output CompareA Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1C = 0x8 // Output Compare Flag 1C + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR3A: Timer/Counter3 Control Register A + TCCR3A_COM3A = 0xc0 // Compare Output Mode 3A, bits + TCCR3A_COM3B = 0x30 // Compare Output Mode 3B, bits + TCCR3A_COM3C = 0xc // Compare Output Mode 3C, bits + TCCR3A_WGM3 = 0x3 // Waveform Generation Mode + + // TCCR3B: Timer/Counter3 Control Register B + TCCR3B_ICNC3 = 0x80 // Input Capture 3 Noise Canceler + TCCR3B_ICES3 = 0x40 // Input Capture 3 Edge Select + TCCR3B_WGM3 = 0x18 // Waveform Generation Mode + TCCR3B_CS3 = 0x7 // Prescaler source of Timer/Counter 3 + + // TCCR3C: Timer/Counter 3 Control Register C + TCCR3C_FOC3A = 0x80 // Force Output Compare 3A + TCCR3C_FOC3B = 0x40 // Force Output Compare 3B + TCCR3C_FOC3C = 0x20 // Force Output Compare 3C + + // TIMSK3: Timer/Counter Interrupt Mask Register + TIMSK3_ICIE3 = 0x20 // Timer/Counter3 Input Capture Interrupt Enable + TIMSK3_OCIE3C = 0x8 // Timer/Counter3 Output CompareC Match Interrupt Enable + TIMSK3_OCIE3B = 0x4 // Timer/Counter3 Output CompareB Match Interrupt Enable + TIMSK3_OCIE3A = 0x2 // Timer/Counter3 Output CompareA Match Interrupt Enable + TIMSK3_TOIE3 = 0x1 // Timer/Counter3 Overflow Interrupt Enable + + // TIFR3: Timer/Counter Interrupt Flag register + TIFR3_ICF3 = 0x20 // Input Capture Flag 3 + TIFR3_OCF3C = 0x8 // Output Compare Flag 3C + TIFR3_OCF3B = 0x4 // Output Compare Flag 3B + TIFR3_OCF3A = 0x2 // Output Compare Flag 3A + TIFR3_TOV3 = 0x1 // Timer/Counter3 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2A: Timer/Counter2 Control Register + TCCR2A_FOC2A = 0x80 // Force Output Compare + TCCR2A_WGM20 = 0x40 // Waveform Genration Mode + TCCR2A_COM2A = 0x30 // Compare Output Mode bits + TCCR2A_WGM21 = 0x8 // Waveform Generation Mode + TCCR2A_CS2 = 0x7 // Clock Select bits + + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2A = 0x2 // Output Compare Flag 2 + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x10 // Enable External Clock Interrupt + ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register 1 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for CAN: Controller Area Network +const ( + // CANGCON: CAN General Control Register + CANGCON_ABRQ = 0x80 // Abort Request + CANGCON_OVRQ = 0x40 // Overload Frame Request + CANGCON_TTC = 0x20 // Time Trigger Communication + CANGCON_SYNTTC = 0x10 // Synchronization of TTC + CANGCON_LISTEN = 0x8 // Listening Mode + CANGCON_TEST = 0x4 // Test Mode + CANGCON_ENASTB = 0x2 // Enable / Standby + CANGCON_SWRES = 0x1 // Software Reset Request + + // CANGSTA: CAN General Status Register + CANGSTA_OVRG = 0x40 // Overload Frame Flag + CANGSTA_TXBSY = 0x10 // Transmitter Busy + CANGSTA_RXBSY = 0x8 // Receiver Busy + CANGSTA_ENFG = 0x4 // Enable Flag + CANGSTA_BOFF = 0x2 // Bus Off Mode + CANGSTA_ERRP = 0x1 // Error Passive Mode + + // CANGIT: CAN General Interrupt Register + CANGIT_CANIT = 0x80 // General Interrupt Flag + CANGIT_BOFFIT = 0x40 // Bus Off Interrupt Flag + CANGIT_OVRTIM = 0x20 // Overrun CAN Timer + CANGIT_BXOK = 0x10 // Burst Receive Interrupt + CANGIT_SERG = 0x8 // Stuff Error General + CANGIT_CERG = 0x4 // CRC Error General + CANGIT_FERG = 0x2 // Form Error General + CANGIT_AERG = 0x1 // Ackknowledgement Error General + + // CANGIE: CAN General Interrupt Enable Register + CANGIE_ENIT = 0x80 // Enable all Interrupts + CANGIE_ENBOFF = 0x40 // Enable Bus Off INterrupt + CANGIE_ENRX = 0x20 // Enable Receive Interrupt + CANGIE_ENTX = 0x10 // Enable Transmitt Interrupt + CANGIE_ENERR = 0x8 // Enable MOb Error Interrupt + CANGIE_ENBX = 0x4 // Enable Burst Receive Interrupt + CANGIE_ENERG = 0x2 // Enable General Error Interrupt + CANGIE_ENOVRT = 0x1 // Enable CAN Timer Overrun Interrupt + + // CANEN2: Enable MOb Register + CANEN2_ENMOB = 0xff // Enable MOb + + // CANEN1: Enable MOb Register + CANEN1_ENMOB = 0x7f // Enable MOb + + // CANIE2: Enable Interrupt MOb Register + CANIE2_IEMOB = 0xff // Interrupt Enable by MOb + + // CANIE1: Enable Interrupt MOb Register + CANIE1_IEMOB = 0x7f // Interrupt Enable by MOb + + // CANSIT2: CAN Status Interrupt MOb Register + CANSIT2_SIT = 0xff // Status of Interrupt by MOb + + // CANSIT1: CAN Status Interrupt MOb Register + CANSIT1_SIT = 0x7f // Status of Interrupt by MOb + + // CANBT1: Bit Timing Register 1 + CANBT1_BRP = 0x7e // Baud Rate Prescaler bits + + // CANBT2: Bit Timing Register 2 + CANBT2_SJW = 0x60 // Re-Sync Jump Width + CANBT2_PRS = 0xe // Propagation Time Segment + + // CANBT3: Bit Timing Register 3 + CANBT3_PHS2 = 0x70 // Phase Segments + CANBT3_PHS1 = 0xe // Phase Segment 1 + CANBT3_SMP = 0x1 // Sample Type + + // CANTCON: Timer Control Register + CANTCON_TPRSC = 0xff // CAN Timer Prescaler + + // CANTIML: Timer Register + + // CANTIMH: Timer Register + CANTIM_CANTIM = 0xffff // CAN Timer Count + + // CANTTCL: TTC Timer Register + + // CANTTCH: TTC Timer Register + CANTTC_TIMTTC = 0xffff // TTC Timer Count + + // CANTEC: Transmit Error Counter Register + CANTEC_TEC = 0xff // Trasnmit Error Count + + // CANREC: Receive Error Counter Register + CANREC_REC = 0xff // Receive Error Count + + // CANHPMOB: Highest Priority MOb Register + CANHPMOB_HPMOB = 0xf0 // Highest Priority MOb number + CANHPMOB_CGP = 0xf // CAN General purpose bits + + // CANPAGE: Page MOb Register + CANPAGE_MOBNB = 0xf0 // MOb Number Bits + CANPAGE_AINC = 0x8 // MOb Data Buffer Auto Increment + CANPAGE_INDX = 0x7 // Data Buffer Index Bits + + // CANSTMOB: MOb Status Register + CANSTMOB_DLCW = 0x80 // Data Length Code Warning + CANSTMOB_TXOK = 0x40 // Transmit OK + CANSTMOB_RXOK = 0x20 // Receive OK + CANSTMOB_BERR = 0x10 // Bit Error + CANSTMOB_SERR = 0x8 // Stuff Error + CANSTMOB_CERR = 0x4 // CRC Error + CANSTMOB_FERR = 0x2 // Form Error + CANSTMOB_AERR = 0x1 // Ackknowledgement Error + + // CANCDMOB: MOb Control and DLC Register + CANCDMOB_CONMOB = 0xc0 // MOb Config Bits + CANCDMOB_RPLV = 0x20 // Reply Valid + CANCDMOB_IDE = 0x10 // Identifier Extension + CANCDMOB_DLC = 0xf // Data Length Code Bits + + // CANIDT4: Identifier Tag Register 4 + CANIDT4_IDT = 0xf8 // Identifier Tag + CANIDT4_RTRTAG = 0x4 // Remote Trasnmission Request Tag + CANIDT4_RB1TAG = 0x2 // Reserved Bit 1 Tag + CANIDT4_RB0TAG = 0x1 // Reserved Bit 0 Tag + + // CANIDT3: Identifier Tag Register 3 + CANIDT3_IDT = 0xff // Identifier Tag + + // CANIDT2: Identifier Tag Register 2 + CANIDT2_IDT = 0xff // Identifier Tag + + // CANIDT1: Identifier Tag Register 1 + CANIDT1_IDT = 0xff // Identifier Tag + + // CANIDM4: Identifier Mask Register 4 + CANIDM4_IDMSK = 0xf8 // Identifier Mask + CANIDM4_RTRMSK = 0x4 // Remote Transmission Request Mask + CANIDM4_IDEMSK = 0x1 // Identifier Extension Mask + + // CANIDM3: Identifier Mask Register 3 + CANIDM3_IDMSK = 0xff // Identifier Mask + + // CANIDM2: Identifier Mask Register 2 + CANIDM2_IDMSK = 0xff // Identifier Mask + + // CANIDM1: Identifier Mask Register 1 + CANIDM1_IDMSK = 0xff // Identifier Mask + + // CANSTML: Time Stamp Register + + // CANSTMH: Time Stamp Register + CANSTM_TIMSTM = 0xffff // Time Stamp Count + + // CANMSG: Message Data Register + CANMSG_MSG = 0xff // Message Data +) diff --git a/src/device/avr/at90can128.ld b/src/device/avr/at90can128.ld new file mode 100644 index 00000000..7f96296c --- /dev/null +++ b/src/device/avr/at90can128.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from AT90CAN128.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x20000; +__ram_size = 0x1000; +__num_isrs = 37; diff --git a/src/device/avr/at90can32.go b/src/device/avr/at90can32.go new file mode 100644 index 00000000..24f46a90 --- /dev/null +++ b/src/device/avr/at90can32.go @@ -0,0 +1,1000 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from AT90CAN32.atdf, see http://packs.download.atmel.com/ + +// +build avr,at90can32 + +// Device information for the AT90CAN32. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "AT90CAN32" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_INT3 = 4 // External Interrupt Request 3 + IRQ_INT4 = 5 // External Interrupt Request 4 + IRQ_INT5 = 6 // External Interrupt Request 5 + IRQ_INT6 = 7 // External Interrupt Request 6 + IRQ_INT7 = 8 // External Interrupt Request 7 + IRQ_TIMER2_COMP = 9 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 10 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 11 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 12 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 13 // Timer/Counter Compare Match B + IRQ_TIMER1_COMPC = 14 // Timer/Counter1 Compare Match C + IRQ_TIMER1_OVF = 15 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 16 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 17 // Timer/Counter0 Overflow + IRQ_CANIT = 18 // CAN Transfer Complete or Error + IRQ_OVRIT = 19 // CAN Timer Overrun + IRQ_SPI_STC = 20 // SPI Serial Transfer Complete + IRQ_USART0_RX = 21 // USART0, Rx Complete + IRQ_USART0_UDRE = 22 // USART0 Data Register Empty + IRQ_USART0_TX = 23 // USART0, Tx Complete + IRQ_ANALOG_COMP = 24 // Analog Comparator + IRQ_ADC = 25 // ADC Conversion Complete + IRQ_EE_READY = 26 // EEPROM Ready + IRQ_TIMER3_CAPT = 27 // Timer/Counter3 Capture Event + IRQ_TIMER3_COMPA = 28 // Timer/Counter3 Compare Match A + IRQ_TIMER3_COMPB = 29 // Timer/Counter3 Compare Match B + IRQ_TIMER3_COMPC = 30 // Timer/Counter3 Compare Match C + IRQ_TIMER3_OVF = 31 // Timer/Counter3 Overflow + IRQ_USART1_RX = 32 // USART1, Rx Complete + IRQ_USART1_UDRE = 33 // USART1, Data Register Empty + IRQ_USART1_TX = 34 // USART1, Tx Complete + IRQ_TWI = 35 // 2-wire Serial Interface + IRQ_SPM_READY = 36 // Store Program Memory Read + IRQ_max = 36 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + PORTG: 0x34, // Data Register, Port G + DDRG: 0x33, // Data Direction Register, Port G + PING: 0x32, // Input Pins, Port G + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // Two Wire Serial Interface + TWI = struct { + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + UDR1 __reg + UCSR1A __reg + UCSR1B __reg + UCSR1C __reg + UBRR1L __reg + UBRR1H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register t Bytes + UBRR0H: 0xc4, // USART Baud Rate Register t Bytes + UDR1: 0xce, // USART I/O Data Register + UCSR1A: 0xc8, // USART Control and Status Register A + UCSR1B: 0xc9, // USART Control and Status Register B + UCSR1C: 0xca, // USART Control and Status Register C + UBRR1L: 0xcc, // USART Baud Rate Register t Bytes + UBRR1H: 0xcc, // USART Baud Rate Register t Bytes + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + XMCRA __reg + XMCRB __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + RAMPZ __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + XMCRA: 0x74, // External Memory Control Register A + XMCRB: 0x75, // External Memory Control Register B + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + SMCR: 0x53, // Sleep Mode Control Register + RAMPZ: 0x5b, // RAM Page Z Select Register - Not used. + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EICRB __reg + EIMSK __reg + EIFR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EICRB: 0x6a, // External Interrupt Control Register B + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access Bytes + EEARH: 0x41, // EEPROM Read/Write Access Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0A __reg + TCNT0 __reg + OCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR0A: 0x44, // Timer/Counter0 Control Register + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + OCR1CL __reg + OCR1CH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + TCCR3A __reg + TCCR3B __reg + TCCR3C __reg + TCNT3L __reg + TCNT3H __reg + OCR3AL __reg + OCR3AH __reg + OCR3BL __reg + OCR3BH __reg + OCR3CL __reg + OCR3CH __reg + ICR3L __reg + ICR3H __reg + TIMSK3 __reg + TIFR3 __reg + }{ + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register Bytes + OCR1CL: 0x8c, // Timer/Counter1 Output Compare Register Bytes + OCR1CH: 0x8c, // Timer/Counter1 Output Compare Register Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR3A: 0x90, // Timer/Counter3 Control Register A + TCCR3B: 0x91, // Timer/Counter3 Control Register B + TCCR3C: 0x92, // Timer/Counter 3 Control Register C + TCNT3L: 0x94, // Timer/Counter3 Bytes + TCNT3H: 0x94, // Timer/Counter3 Bytes + OCR3AL: 0x98, // Timer/Counter3 Output Compare Register Bytes + OCR3AH: 0x98, // Timer/Counter3 Output Compare Register Bytes + OCR3BL: 0x9a, // Timer/Counter3 Output Compare Register Bytes + OCR3BH: 0x9a, // Timer/Counter3 Output Compare Register Bytes + OCR3CL: 0x9c, // Timer/Counter3 Output Compare Register Bytes + OCR3CH: 0x9c, // Timer/Counter3 Output Compare Register Bytes + ICR3L: 0x96, // Timer/Counter3 Input Capture Register Bytes + ICR3H: 0x96, // Timer/Counter3 Input Capture Register Bytes + TIMSK3: 0x71, // Timer/Counter Interrupt Mask Register + TIFR3: 0x38, // Timer/Counter Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2A __reg + TCNT2 __reg + OCR2A __reg + TIMSK2 __reg + TIFR2 __reg + ASSR __reg + }{ + TCCR2A: 0xb0, // Timer/Counter2 Control Register + TCNT2: 0xb2, // Timer/Counter2 + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x60, // Watchdog Timer Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 1 + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, + } + + // Controller Area Network + CAN = struct { + CANGCON __reg + CANGSTA __reg + CANGIT __reg + CANGIE __reg + CANEN2 __reg + CANEN1 __reg + CANIE2 __reg + CANIE1 __reg + CANSIT2 __reg + CANSIT1 __reg + CANBT1 __reg + CANBT2 __reg + CANBT3 __reg + CANTCON __reg + CANTIML __reg + CANTIMH __reg + CANTTCL __reg + CANTTCH __reg + CANTEC __reg + CANREC __reg + CANHPMOB __reg + CANPAGE __reg + CANSTMOB __reg + CANCDMOB __reg + CANIDT4 __reg + CANIDT3 __reg + CANIDT2 __reg + CANIDT1 __reg + CANIDM4 __reg + CANIDM3 __reg + CANIDM2 __reg + CANIDM1 __reg + CANSTML __reg + CANSTMH __reg + CANMSG __reg + }{ + CANGCON: 0xd8, // CAN General Control Register + CANGSTA: 0xd9, // CAN General Status Register + CANGIT: 0xda, // CAN General Interrupt Register + CANGIE: 0xdb, // CAN General Interrupt Enable Register + CANEN2: 0xdc, // Enable MOb Register + CANEN1: 0xdd, // Enable MOb Register + CANIE2: 0xde, // Enable Interrupt MOb Register + CANIE1: 0xdf, // Enable Interrupt MOb Register + CANSIT2: 0xe0, // CAN Status Interrupt MOb Register + CANSIT1: 0xe1, // CAN Status Interrupt MOb Register + CANBT1: 0xe2, // Bit Timing Register 1 + CANBT2: 0xe3, // Bit Timing Register 2 + CANBT3: 0xe4, // Bit Timing Register 3 + CANTCON: 0xe5, // Timer Control Register + CANTIML: 0xe6, // Timer Register + CANTIMH: 0xe6, // Timer Register + CANTTCL: 0xe8, // TTC Timer Register + CANTTCH: 0xe8, // TTC Timer Register + CANTEC: 0xea, // Transmit Error Counter Register + CANREC: 0xeb, // Receive Error Counter Register + CANHPMOB: 0xec, // Highest Priority MOb Register + CANPAGE: 0xed, // Page MOb Register + CANSTMOB: 0xee, // MOb Status Register + CANCDMOB: 0xef, // MOb Control and DLC Register + CANIDT4: 0xf0, // Identifier Tag Register 4 + CANIDT3: 0xf1, // Identifier Tag Register 3 + CANIDT2: 0xf2, // Identifier Tag Register 2 + CANIDT1: 0xf3, // Identifier Tag Register 1 + CANIDM4: 0xf4, // Identifier Mask Register 4 + CANIDM3: 0xf5, // Identifier Mask Register 3 + CANIDM2: 0xf6, // Identifier Mask Register 2 + CANIDM1: 0xf7, // Identifier Mask Register 1 + CANSTML: 0xf8, // Time Stamp Register + CANSTMH: 0xf8, // Time Stamp Register + CANMSG: 0xfa, // Message Data Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0xe // Brown-out Detector trigger level + EXTENDED_TA0SEL = 0x1 // Reserved for factory tests + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally; [CKDIV8=0] + LOW_CKOUT = 0x40 // Clock output on PORTC7; [CKOUT=0] + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPDR: SPI Data Register + SPDR_SPD = 0xff // SPI Data Register +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0x40 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity + + // UCSR1A: USART Control and Status Register A + UCSR1A_RXC1 = 0x80 // USART Receive Complete + UCSR1A_TXC1 = 0x40 // USART Transmitt Complete + UCSR1A_UDRE1 = 0x20 // USART Data Register Empty + UCSR1A_FE1 = 0x10 // Framing Error + UCSR1A_DOR1 = 0x8 // Data overRun + UCSR1A_UPE1 = 0x4 // Parity Error + UCSR1A_U2X1 = 0x2 // Double the USART transmission speed + UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode + + // UCSR1B: USART Control and Status Register B + UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable + UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable + UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable + UCSR1B_RXEN1 = 0x10 // Receiver Enable + UCSR1B_TXEN1 = 0x8 // Transmitter Enable + UCSR1B_UCSZ12 = 0x4 // Character Size + UCSR1B_RXB81 = 0x2 // Receive Data Bit 8 + UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8 + + // UCSR1C: USART Control and Status Register C + UCSR1C_UMSEL1 = 0x40 // USART Mode Select + UCSR1C_UPM1 = 0x30 // Parity Mode Bits + UCSR1C_USBS1 = 0x8 // Stop Bit Select + UCSR1C_UCSZ1 = 0x6 // Character Size + UCSR1C_UCPOL1 = 0x1 // Clock Polarity +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // XMCRA: External Memory Control Register A + XMCRA_SRE = 0x80 // External SRAM Enable + XMCRA_SRL = 0x70 // Wait state page limit + XMCRA_SRW1 = 0xc // Wait state select bit upper page + XMCRA_SRW0 = 0x3 // Wait state select bit lower page + + // XMCRB: External Memory Control Register B + XMCRB_XMBK = 0x80 // External Memory Bus Keeper Enable + XMCRB_XMM = 0x7 // External Memory High Mask + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // RAMPZ: RAM Page Z Select Register - Not used. + RAMPZ_RAMPZ0 = 0x1 // RAM Page Z Select Register Bit 0 + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EICRB: External Interrupt Control Register B + EICRB_ISC7 = 0xc0 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC6 = 0x30 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC5 = 0xc // External Interrupt 7-4 Sense Control Bit + EICRB_ISC4 = 0x3 // External Interrupt 7-4 Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xff // External Interrupt Request 7 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xff // External Interrupt Flags +) + +// Bitfields for EEPROM: EEPROM +const ( + // EEARL: EEPROM Read/Write Access Bytes + + // EEARH: EEPROM Read/Write Access Bytes + EEAR_EEAR = 0xfff // EEPROM Address bits + + // EEDR: EEPROM Data Register + EEDR_EEDR = 0xff // EEPROM Data bits + + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0A: Timer/Counter0 Control Register + TCCR0A_FOC0A = 0x80 // Force Output Compare + TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0A_COM0A = 0x30 // Compare Match Output Modes + TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0A_CS0 = 0x7 // Clock Selects + + // OCR0A: Timer/Counter0 Output Compare Register + OCR0A_OCR0A = 0xff // Output Compare A bits + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0 + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_COM1C = 0xc // Compare Output Mode 1C, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + TCCR1C_FOC1C = 0x20 // Force Output Compare 1C + + // TIMSK1: Timer/Counter Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1C = 0x8 // Timer/Counter1 Output CompareC Match Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output CompareB Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output CompareA Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1C = 0x8 // Output Compare Flag 1C + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR3A: Timer/Counter3 Control Register A + TCCR3A_COM3A = 0xc0 // Compare Output Mode 3A, bits + TCCR3A_COM3B = 0x30 // Compare Output Mode 3B, bits + TCCR3A_COM3C = 0xc // Compare Output Mode 3C, bits + TCCR3A_WGM3 = 0x3 // Waveform Generation Mode + + // TCCR3B: Timer/Counter3 Control Register B + TCCR3B_ICNC3 = 0x80 // Input Capture 3 Noise Canceler + TCCR3B_ICES3 = 0x40 // Input Capture 3 Edge Select + TCCR3B_WGM3 = 0x18 // Waveform Generation Mode + TCCR3B_CS3 = 0x7 // Prescaler source of Timer/Counter 3 + + // TCCR3C: Timer/Counter 3 Control Register C + TCCR3C_FOC3A = 0x80 // Force Output Compare 3A + TCCR3C_FOC3B = 0x40 // Force Output Compare 3B + TCCR3C_FOC3C = 0x20 // Force Output Compare 3C + + // TIMSK3: Timer/Counter Interrupt Mask Register + TIMSK3_ICIE3 = 0x20 // Timer/Counter3 Input Capture Interrupt Enable + TIMSK3_OCIE3C = 0x8 // Timer/Counter3 Output CompareC Match Interrupt Enable + TIMSK3_OCIE3B = 0x4 // Timer/Counter3 Output CompareB Match Interrupt Enable + TIMSK3_OCIE3A = 0x2 // Timer/Counter3 Output CompareA Match Interrupt Enable + TIMSK3_TOIE3 = 0x1 // Timer/Counter3 Overflow Interrupt Enable + + // TIFR3: Timer/Counter Interrupt Flag register + TIFR3_ICF3 = 0x20 // Input Capture Flag 3 + TIFR3_OCF3C = 0x8 // Output Compare Flag 3C + TIFR3_OCF3B = 0x4 // Output Compare Flag 3B + TIFR3_OCF3A = 0x2 // Output Compare Flag 3A + TIFR3_TOV3 = 0x1 // Timer/Counter3 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2A: Timer/Counter2 Control Register + TCCR2A_FOC2A = 0x80 // Force Output Compare + TCCR2A_WGM20 = 0x40 // Waveform Genration Mode + TCCR2A_COM2A = 0x30 // Compare Output Mode bits + TCCR2A_WGM21 = 0x8 // Waveform Generation Mode + TCCR2A_CS2 = 0x7 // Clock Select bits + + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2A = 0x2 // Output Compare Flag 2 + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x10 // Enable External Clock Interrupt + ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register 1 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for CAN: Controller Area Network +const ( + // CANGCON: CAN General Control Register + CANGCON_ABRQ = 0x80 // Abort Request + CANGCON_OVRQ = 0x40 // Overload Frame Request + CANGCON_TTC = 0x20 // Time Trigger Communication + CANGCON_SYNTTC = 0x10 // Synchronization of TTC + CANGCON_LISTEN = 0x8 // Listening Mode + CANGCON_TEST = 0x4 // Test Mode + CANGCON_ENASTB = 0x2 // Enable / Standby + CANGCON_SWRES = 0x1 // Software Reset Request + + // CANGSTA: CAN General Status Register + CANGSTA_OVRG = 0x40 // Overload Frame Flag + CANGSTA_TXBSY = 0x10 // Transmitter Busy + CANGSTA_RXBSY = 0x8 // Receiver Busy + CANGSTA_ENFG = 0x4 // Enable Flag + CANGSTA_BOFF = 0x2 // Bus Off Mode + CANGSTA_ERRP = 0x1 // Error Passive Mode + + // CANGIT: CAN General Interrupt Register + CANGIT_CANIT = 0x80 // General Interrupt Flag + CANGIT_BOFFIT = 0x40 // Bus Off Interrupt Flag + CANGIT_OVRTIM = 0x20 // Overrun CAN Timer + CANGIT_BXOK = 0x10 // Burst Receive Interrupt + CANGIT_SERG = 0x8 // Stuff Error General + CANGIT_CERG = 0x4 // CRC Error General + CANGIT_FERG = 0x2 // Form Error General + CANGIT_AERG = 0x1 // Ackknowledgement Error General + + // CANGIE: CAN General Interrupt Enable Register + CANGIE_ENIT = 0x80 // Enable all Interrupts + CANGIE_ENBOFF = 0x40 // Enable Bus Off INterrupt + CANGIE_ENRX = 0x20 // Enable Receive Interrupt + CANGIE_ENTX = 0x10 // Enable Transmitt Interrupt + CANGIE_ENERR = 0x8 // Enable MOb Error Interrupt + CANGIE_ENBX = 0x4 // Enable Burst Receive Interrupt + CANGIE_ENERG = 0x2 // Enable General Error Interrupt + CANGIE_ENOVRT = 0x1 // Enable CAN Timer Overrun Interrupt + + // CANEN2: Enable MOb Register + CANEN2_ENMOB = 0xff // Enable MOb + + // CANEN1: Enable MOb Register + CANEN1_ENMOB = 0x7f // Enable MOb + + // CANIE2: Enable Interrupt MOb Register + CANIE2_IEMOB = 0xff // Interrupt Enable by MOb + + // CANIE1: Enable Interrupt MOb Register + CANIE1_IEMOB = 0x7f // Interrupt Enable by MOb + + // CANSIT2: CAN Status Interrupt MOb Register + CANSIT2_SIT = 0xff // Status of Interrupt by MOb + + // CANSIT1: CAN Status Interrupt MOb Register + CANSIT1_SIT = 0x7f // Status of Interrupt by MOb + + // CANBT1: Bit Timing Register 1 + CANBT1_BRP = 0x7e // Baud Rate Prescaler bits + + // CANBT2: Bit Timing Register 2 + CANBT2_SJW = 0x60 // Re-Sync Jump Width + CANBT2_PRS = 0xe // Propagation Time Segment + + // CANBT3: Bit Timing Register 3 + CANBT3_PHS2 = 0x70 // Phase Segments + CANBT3_PHS1 = 0xe // Phase Segment 1 + CANBT3_SMP = 0x1 // Sample Type + + // CANTCON: Timer Control Register + CANTCON_TPRSC = 0xff // CAN Timer Prescaler + + // CANTIML: Timer Register + + // CANTIMH: Timer Register + CANTIM_CANTIM = 0xffff // CAN Timer Count + + // CANTTCL: TTC Timer Register + + // CANTTCH: TTC Timer Register + CANTTC_TIMTTC = 0xffff // TTC Timer Count + + // CANTEC: Transmit Error Counter Register + CANTEC_TEC = 0xff // Trasnmit Error Count + + // CANREC: Receive Error Counter Register + CANREC_REC = 0xff // Receive Error Count + + // CANHPMOB: Highest Priority MOb Register + CANHPMOB_HPMOB = 0xf0 // Highest Priority MOb number + CANHPMOB_CGP = 0xf // CAN General purpose bits + + // CANPAGE: Page MOb Register + CANPAGE_MOBNB = 0xf0 // MOb Number Bits + CANPAGE_AINC = 0x8 // MOb Data Buffer Auto Increment + CANPAGE_INDX = 0x7 // Data Buffer Index Bits + + // CANSTMOB: MOb Status Register + CANSTMOB_DLCW = 0x80 // Data Length Code Warning + CANSTMOB_TXOK = 0x40 // Transmit OK + CANSTMOB_RXOK = 0x20 // Receive OK + CANSTMOB_BERR = 0x10 // Bit Error + CANSTMOB_SERR = 0x8 // Stuff Error + CANSTMOB_CERR = 0x4 // CRC Error + CANSTMOB_FERR = 0x2 // Form Error + CANSTMOB_AERR = 0x1 // Ackknowledgement Error + + // CANCDMOB: MOb Control and DLC Register + CANCDMOB_CONMOB = 0xc0 // MOb Config Bits + CANCDMOB_RPLV = 0x20 // Reply Valid + CANCDMOB_IDE = 0x10 // Identifier Extension + CANCDMOB_DLC = 0xf // Data Length Code Bits + + // CANIDT4: Identifier Tag Register 4 + CANIDT4_IDT = 0xf8 // Identifier Tag + CANIDT4_RTRTAG = 0x4 // Remote Trasnmission Request Tag + CANIDT4_RB1TAG = 0x2 // Reserved Bit 1 Tag + CANIDT4_RB0TAG = 0x1 // Reserved Bit 0 Tag + + // CANIDT3: Identifier Tag Register 3 + CANIDT3_IDT = 0xff // Identifier Tag + + // CANIDT2: Identifier Tag Register 2 + CANIDT2_IDT = 0xff // Identifier Tag + + // CANIDT1: Identifier Tag Register 1 + CANIDT1_IDT = 0xff // Identifier Tag + + // CANIDM4: Identifier Mask Register 4 + CANIDM4_IDMSK = 0xf8 // Identifier Mask + CANIDM4_RTRMSK = 0x4 // Remote Transmission Request Mask + CANIDM4_IDEMSK = 0x1 // Identifier Extension Mask + + // CANIDM3: Identifier Mask Register 3 + CANIDM3_IDMSK = 0xff // Identifier Mask + + // CANIDM2: Identifier Mask Register 2 + CANIDM2_IDMSK = 0xff // Identifier Mask + + // CANIDM1: Identifier Mask Register 1 + CANIDM1_IDMSK = 0xff // Identifier Mask + + // CANSTML: Time Stamp Register + + // CANSTMH: Time Stamp Register + CANSTM_TIMSTM = 0xffff // Time Stamp Count + + // CANMSG: Message Data Register + CANMSG_MSG = 0xff // Message Data +) diff --git a/src/device/avr/at90can32.ld b/src/device/avr/at90can32.ld new file mode 100644 index 00000000..f0245e9f --- /dev/null +++ b/src/device/avr/at90can32.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from AT90CAN32.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_size = 0x800; +__num_isrs = 37; diff --git a/src/device/avr/at90can64.go b/src/device/avr/at90can64.go new file mode 100644 index 00000000..2386ab71 --- /dev/null +++ b/src/device/avr/at90can64.go @@ -0,0 +1,1000 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from AT90CAN64.atdf, see http://packs.download.atmel.com/ + +// +build avr,at90can64 + +// Device information for the AT90CAN64. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "AT90CAN64" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_INT3 = 4 // External Interrupt Request 3 + IRQ_INT4 = 5 // External Interrupt Request 4 + IRQ_INT5 = 6 // External Interrupt Request 5 + IRQ_INT6 = 7 // External Interrupt Request 6 + IRQ_INT7 = 8 // External Interrupt Request 7 + IRQ_TIMER2_COMP = 9 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 10 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 11 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 12 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 13 // Timer/Counter Compare Match B + IRQ_TIMER1_COMPC = 14 // Timer/Counter1 Compare Match C + IRQ_TIMER1_OVF = 15 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 16 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 17 // Timer/Counter0 Overflow + IRQ_CANIT = 18 // CAN Transfer Complete or Error + IRQ_OVRIT = 19 // CAN Timer Overrun + IRQ_SPI_STC = 20 // SPI Serial Transfer Complete + IRQ_USART0_RX = 21 // USART0, Rx Complete + IRQ_USART0_UDRE = 22 // USART0 Data Register Empty + IRQ_USART0_TX = 23 // USART0, Tx Complete + IRQ_ANALOG_COMP = 24 // Analog Comparator + IRQ_ADC = 25 // ADC Conversion Complete + IRQ_EE_READY = 26 // EEPROM Ready + IRQ_TIMER3_CAPT = 27 // Timer/Counter3 Capture Event + IRQ_TIMER3_COMPA = 28 // Timer/Counter3 Compare Match A + IRQ_TIMER3_COMPB = 29 // Timer/Counter3 Compare Match B + IRQ_TIMER3_COMPC = 30 // Timer/Counter3 Compare Match C + IRQ_TIMER3_OVF = 31 // Timer/Counter3 Overflow + IRQ_USART1_RX = 32 // USART1, Rx Complete + IRQ_USART1_UDRE = 33 // USART1, Data Register Empty + IRQ_USART1_TX = 34 // USART1, Tx Complete + IRQ_TWI = 35 // 2-wire Serial Interface + IRQ_SPM_READY = 36 // Store Program Memory Read + IRQ_max = 36 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + PORTG: 0x34, // Data Register, Port G + DDRG: 0x33, // Data Direction Register, Port G + PING: 0x32, // Input Pins, Port G + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // Two Wire Serial Interface + TWI = struct { + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + UDR1 __reg + UCSR1A __reg + UCSR1B __reg + UCSR1C __reg + UBRR1L __reg + UBRR1H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register t Bytes + UBRR0H: 0xc4, // USART Baud Rate Register t Bytes + UDR1: 0xce, // USART I/O Data Register + UCSR1A: 0xc8, // USART Control and Status Register A + UCSR1B: 0xc9, // USART Control and Status Register B + UCSR1C: 0xca, // USART Control and Status Register C + UBRR1L: 0xcc, // USART Baud Rate Register t Bytes + UBRR1H: 0xcc, // USART Baud Rate Register t Bytes + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + XMCRA __reg + XMCRB __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + RAMPZ __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + XMCRA: 0x74, // External Memory Control Register A + XMCRB: 0x75, // External Memory Control Register B + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + SMCR: 0x53, // Sleep Mode Control Register + RAMPZ: 0x5b, // RAM Page Z Select Register - Not used. + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EICRB __reg + EIMSK __reg + EIFR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EICRB: 0x6a, // External Interrupt Control Register B + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access Bytes - Only bit 10..8 are used in AT90CAN64 - Only bit 9..8 are used in AT90CAN32 + EEARH: 0x41, // EEPROM Read/Write Access Bytes - Only bit 10..8 are used in AT90CAN64 - Only bit 9..8 are used in AT90CAN32 + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0A __reg + TCNT0 __reg + OCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR0A: 0x44, // Timer/Counter0 Control Register + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + OCR1CL __reg + OCR1CH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + TCCR3A __reg + TCCR3B __reg + TCCR3C __reg + TCNT3L __reg + TCNT3H __reg + OCR3AL __reg + OCR3AH __reg + OCR3BL __reg + OCR3BH __reg + OCR3CL __reg + OCR3CH __reg + ICR3L __reg + ICR3H __reg + TIMSK3 __reg + TIFR3 __reg + }{ + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register Bytes + OCR1CL: 0x8c, // Timer/Counter1 Output Compare Register Bytes + OCR1CH: 0x8c, // Timer/Counter1 Output Compare Register Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR3A: 0x90, // Timer/Counter3 Control Register A + TCCR3B: 0x91, // Timer/Counter3 Control Register B + TCCR3C: 0x92, // Timer/Counter 3 Control Register C + TCNT3L: 0x94, // Timer/Counter3 Bytes + TCNT3H: 0x94, // Timer/Counter3 Bytes + OCR3AL: 0x98, // Timer/Counter3 Output Compare Register Bytes + OCR3AH: 0x98, // Timer/Counter3 Output Compare Register Bytes + OCR3BL: 0x9a, // Timer/Counter3 Output Compare Register Bytes + OCR3BH: 0x9a, // Timer/Counter3 Output Compare Register Bytes + OCR3CL: 0x9c, // Timer/Counter3 Output Compare Register Bytes + OCR3CH: 0x9c, // Timer/Counter3 Output Compare Register Bytes + ICR3L: 0x96, // Timer/Counter3 Input Capture Register Bytes + ICR3H: 0x96, // Timer/Counter3 Input Capture Register Bytes + TIMSK3: 0x71, // Timer/Counter Interrupt Mask Register + TIFR3: 0x38, // Timer/Counter Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2A __reg + TCNT2 __reg + OCR2A __reg + TIMSK2 __reg + TIFR2 __reg + ASSR __reg + }{ + TCCR2A: 0xb0, // Timer/Counter2 Control Register + TCNT2: 0xb2, // Timer/Counter2 + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x60, // Watchdog Timer Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 1 + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, + } + + // Controller Area Network + CAN = struct { + CANGCON __reg + CANGSTA __reg + CANGIT __reg + CANGIE __reg + CANEN2 __reg + CANEN1 __reg + CANIE2 __reg + CANIE1 __reg + CANSIT2 __reg + CANSIT1 __reg + CANBT1 __reg + CANBT2 __reg + CANBT3 __reg + CANTCON __reg + CANTIML __reg + CANTIMH __reg + CANTTCL __reg + CANTTCH __reg + CANTEC __reg + CANREC __reg + CANHPMOB __reg + CANPAGE __reg + CANSTMOB __reg + CANCDMOB __reg + CANIDT4 __reg + CANIDT3 __reg + CANIDT2 __reg + CANIDT1 __reg + CANIDM4 __reg + CANIDM3 __reg + CANIDM2 __reg + CANIDM1 __reg + CANSTML __reg + CANSTMH __reg + CANMSG __reg + }{ + CANGCON: 0xd8, // CAN General Control Register + CANGSTA: 0xd9, // CAN General Status Register + CANGIT: 0xda, // CAN General Interrupt Register + CANGIE: 0xdb, // CAN General Interrupt Enable Register + CANEN2: 0xdc, // Enable MOb Register + CANEN1: 0xdd, // Enable MOb Register + CANIE2: 0xde, // Enable Interrupt MOb Register + CANIE1: 0xdf, // Enable Interrupt MOb Register + CANSIT2: 0xe0, // CAN Status Interrupt MOb Register + CANSIT1: 0xe1, // CAN Status Interrupt MOb Register + CANBT1: 0xe2, // Bit Timing Register 1 + CANBT2: 0xe3, // Bit Timing Register 2 + CANBT3: 0xe4, // Bit Timing Register 3 + CANTCON: 0xe5, // Timer Control Register + CANTIML: 0xe6, // Timer Register + CANTIMH: 0xe6, // Timer Register + CANTTCL: 0xe8, // TTC Timer Register + CANTTCH: 0xe8, // TTC Timer Register + CANTEC: 0xea, // Transmit Error Counter Register + CANREC: 0xeb, // Receive Error Counter Register + CANHPMOB: 0xec, // Highest Priority MOb Register + CANPAGE: 0xed, // Page MOb Register + CANSTMOB: 0xee, // MOb Status Register + CANCDMOB: 0xef, // MOb Control and DLC Register + CANIDT4: 0xf0, // Identifier Tag Register 4 + CANIDT3: 0xf1, // Identifier Tag Register 3 + CANIDT2: 0xf2, // Identifier Tag Register 2 + CANIDT1: 0xf3, // Identifier Tag Register 1 + CANIDM4: 0xf4, // Identifier Mask Register 4 + CANIDM3: 0xf5, // Identifier Mask Register 3 + CANIDM2: 0xf6, // Identifier Mask Register 2 + CANIDM1: 0xf7, // Identifier Mask Register 1 + CANSTML: 0xf8, // Time Stamp Register + CANSTMH: 0xf8, // Time Stamp Register + CANMSG: 0xfa, // Message Data Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0xe // Brown-out Detector trigger level + EXTENDED_TA0SEL = 0x1 // Reserved for factory tests + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally; [CKDIV8=0] + LOW_CKOUT = 0x40 // Clock output on PORTC7; [CKOUT=0] + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPDR: SPI Data Register + SPDR_SPD = 0xff // SPI Data Register +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0x40 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity + + // UCSR1A: USART Control and Status Register A + UCSR1A_RXC1 = 0x80 // USART Receive Complete + UCSR1A_TXC1 = 0x40 // USART Transmitt Complete + UCSR1A_UDRE1 = 0x20 // USART Data Register Empty + UCSR1A_FE1 = 0x10 // Framing Error + UCSR1A_DOR1 = 0x8 // Data overRun + UCSR1A_UPE1 = 0x4 // Parity Error + UCSR1A_U2X1 = 0x2 // Double the USART transmission speed + UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode + + // UCSR1B: USART Control and Status Register B + UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable + UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable + UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable + UCSR1B_RXEN1 = 0x10 // Receiver Enable + UCSR1B_TXEN1 = 0x8 // Transmitter Enable + UCSR1B_UCSZ12 = 0x4 // Character Size + UCSR1B_RXB81 = 0x2 // Receive Data Bit 8 + UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8 + + // UCSR1C: USART Control and Status Register C + UCSR1C_UMSEL1 = 0x40 // USART Mode Select + UCSR1C_UPM1 = 0x30 // Parity Mode Bits + UCSR1C_USBS1 = 0x8 // Stop Bit Select + UCSR1C_UCSZ1 = 0x6 // Character Size + UCSR1C_UCPOL1 = 0x1 // Clock Polarity +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // XMCRA: External Memory Control Register A + XMCRA_SRE = 0x80 // External SRAM Enable + XMCRA_SRL = 0x70 // Wait state page limit + XMCRA_SRW1 = 0xc // Wait state select bit upper page + XMCRA_SRW0 = 0x3 // Wait state select bit lower page + + // XMCRB: External Memory Control Register B + XMCRB_XMBK = 0x80 // External Memory Bus Keeper Enable + XMCRB_XMM = 0x7 // External Memory High Mask + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // RAMPZ: RAM Page Z Select Register - Not used. + RAMPZ_RAMPZ0 = 0x1 // RAM Page Z Select Register Bit 0 + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EICRB: External Interrupt Control Register B + EICRB_ISC7 = 0xc0 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC6 = 0x30 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC5 = 0xc // External Interrupt 7-4 Sense Control Bit + EICRB_ISC4 = 0x3 // External Interrupt 7-4 Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xff // External Interrupt Request 7 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xff // External Interrupt Flags +) + +// Bitfields for EEPROM: EEPROM +const ( + // EEARL: EEPROM Read/Write Access Bytes - Only bit 10..8 are used in AT90CAN64 - Only bit 9..8 are used in AT90CAN32 + + // EEARH: EEPROM Read/Write Access Bytes - Only bit 10..8 are used in AT90CAN64 - Only bit 9..8 are used in AT90CAN32 + EEAR_EEAR = 0xfff // EEPROM Address bits + + // EEDR: EEPROM Data Register + EEDR_EEDR = 0xff // EEPROM Data bits + + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0A: Timer/Counter0 Control Register + TCCR0A_FOC0A = 0x80 // Force Output Compare + TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0A_COM0A = 0x30 // Compare Match Output Modes + TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0A_CS0 = 0x7 // Clock Selects + + // OCR0A: Timer/Counter0 Output Compare Register + OCR0A_OCR0A = 0xff // Output Compare A bits + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0 + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_COM1C = 0xc // Compare Output Mode 1C, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + TCCR1C_FOC1C = 0x20 // Force Output Compare 1C + + // TIMSK1: Timer/Counter Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1C = 0x8 // Timer/Counter1 Output CompareC Match Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output CompareB Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output CompareA Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1C = 0x8 // Output Compare Flag 1C + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR3A: Timer/Counter3 Control Register A + TCCR3A_COM3A = 0xc0 // Compare Output Mode 3A, bits + TCCR3A_COM3B = 0x30 // Compare Output Mode 3B, bits + TCCR3A_COM3C = 0xc // Compare Output Mode 3C, bits + TCCR3A_WGM3 = 0x3 // Waveform Generation Mode + + // TCCR3B: Timer/Counter3 Control Register B + TCCR3B_ICNC3 = 0x80 // Input Capture 3 Noise Canceler + TCCR3B_ICES3 = 0x40 // Input Capture 3 Edge Select + TCCR3B_WGM3 = 0x18 // Waveform Generation Mode + TCCR3B_CS3 = 0x7 // Prescaler source of Timer/Counter 3 + + // TCCR3C: Timer/Counter 3 Control Register C + TCCR3C_FOC3A = 0x80 // Force Output Compare 3A + TCCR3C_FOC3B = 0x40 // Force Output Compare 3B + TCCR3C_FOC3C = 0x20 // Force Output Compare 3C + + // TIMSK3: Timer/Counter Interrupt Mask Register + TIMSK3_ICIE3 = 0x20 // Timer/Counter3 Input Capture Interrupt Enable + TIMSK3_OCIE3C = 0x8 // Timer/Counter3 Output CompareC Match Interrupt Enable + TIMSK3_OCIE3B = 0x4 // Timer/Counter3 Output CompareB Match Interrupt Enable + TIMSK3_OCIE3A = 0x2 // Timer/Counter3 Output CompareA Match Interrupt Enable + TIMSK3_TOIE3 = 0x1 // Timer/Counter3 Overflow Interrupt Enable + + // TIFR3: Timer/Counter Interrupt Flag register + TIFR3_ICF3 = 0x20 // Input Capture Flag 3 + TIFR3_OCF3C = 0x8 // Output Compare Flag 3C + TIFR3_OCF3B = 0x4 // Output Compare Flag 3B + TIFR3_OCF3A = 0x2 // Output Compare Flag 3A + TIFR3_TOV3 = 0x1 // Timer/Counter3 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2A: Timer/Counter2 Control Register + TCCR2A_FOC2A = 0x80 // Force Output Compare + TCCR2A_WGM20 = 0x40 // Waveform Genration Mode + TCCR2A_COM2A = 0x30 // Compare Output Mode bits + TCCR2A_WGM21 = 0x8 // Waveform Generation Mode + TCCR2A_CS2 = 0x7 // Clock Select bits + + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2A = 0x2 // Output Compare Flag 2 + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x10 // Enable External Clock Interrupt + ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register 1 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for CAN: Controller Area Network +const ( + // CANGCON: CAN General Control Register + CANGCON_ABRQ = 0x80 // Abort Request + CANGCON_OVRQ = 0x40 // Overload Frame Request + CANGCON_TTC = 0x20 // Time Trigger Communication + CANGCON_SYNTTC = 0x10 // Synchronization of TTC + CANGCON_LISTEN = 0x8 // Listening Mode + CANGCON_TEST = 0x4 // Test Mode + CANGCON_ENASTB = 0x2 // Enable / Standby + CANGCON_SWRES = 0x1 // Software Reset Request + + // CANGSTA: CAN General Status Register + CANGSTA_OVRG = 0x40 // Overload Frame Flag + CANGSTA_TXBSY = 0x10 // Transmitter Busy + CANGSTA_RXBSY = 0x8 // Receiver Busy + CANGSTA_ENFG = 0x4 // Enable Flag + CANGSTA_BOFF = 0x2 // Bus Off Mode + CANGSTA_ERRP = 0x1 // Error Passive Mode + + // CANGIT: CAN General Interrupt Register + CANGIT_CANIT = 0x80 // General Interrupt Flag + CANGIT_BOFFIT = 0x40 // Bus Off Interrupt Flag + CANGIT_OVRTIM = 0x20 // Overrun CAN Timer + CANGIT_BXOK = 0x10 // Burst Receive Interrupt + CANGIT_SERG = 0x8 // Stuff Error General + CANGIT_CERG = 0x4 // CRC Error General + CANGIT_FERG = 0x2 // Form Error General + CANGIT_AERG = 0x1 // Ackknowledgement Error General + + // CANGIE: CAN General Interrupt Enable Register + CANGIE_ENIT = 0x80 // Enable all Interrupts + CANGIE_ENBOFF = 0x40 // Enable Bus Off INterrupt + CANGIE_ENRX = 0x20 // Enable Receive Interrupt + CANGIE_ENTX = 0x10 // Enable Transmitt Interrupt + CANGIE_ENERR = 0x8 // Enable MOb Error Interrupt + CANGIE_ENBX = 0x4 // Enable Burst Receive Interrupt + CANGIE_ENERG = 0x2 // Enable General Error Interrupt + CANGIE_ENOVRT = 0x1 // Enable CAN Timer Overrun Interrupt + + // CANEN2: Enable MOb Register + CANEN2_ENMOB = 0xff // Enable MOb + + // CANEN1: Enable MOb Register + CANEN1_ENMOB = 0x7f // Enable MOb + + // CANIE2: Enable Interrupt MOb Register + CANIE2_IEMOB = 0xff // Interrupt Enable by MOb + + // CANIE1: Enable Interrupt MOb Register + CANIE1_IEMOB = 0x7f // Interrupt Enable by MOb + + // CANSIT2: CAN Status Interrupt MOb Register + CANSIT2_SIT = 0xff // Status of Interrupt by MOb + + // CANSIT1: CAN Status Interrupt MOb Register + CANSIT1_SIT = 0x7f // Status of Interrupt by MOb + + // CANBT1: Bit Timing Register 1 + CANBT1_BRP = 0x7e // Baud Rate Prescaler bits + + // CANBT2: Bit Timing Register 2 + CANBT2_SJW = 0x60 // Re-Sync Jump Width + CANBT2_PRS = 0xe // Propagation Time Segment + + // CANBT3: Bit Timing Register 3 + CANBT3_PHS2 = 0x70 // Phase Segments + CANBT3_PHS1 = 0xe // Phase Segment 1 + CANBT3_SMP = 0x1 // Sample Type + + // CANTCON: Timer Control Register + CANTCON_TPRSC = 0xff // CAN Timer Prescaler + + // CANTIML: Timer Register + + // CANTIMH: Timer Register + CANTIM_CANTIM = 0xffff // CAN Timer Count + + // CANTTCL: TTC Timer Register + + // CANTTCH: TTC Timer Register + CANTTC_TIMTTC = 0xffff // TTC Timer Count + + // CANTEC: Transmit Error Counter Register + CANTEC_TEC = 0xff // Trasnmit Error Count + + // CANREC: Receive Error Counter Register + CANREC_REC = 0xff // Receive Error Count + + // CANHPMOB: Highest Priority MOb Register + CANHPMOB_HPMOB = 0xf0 // Highest Priority MOb number + CANHPMOB_CGP = 0xf // CAN General purpose bits + + // CANPAGE: Page MOb Register + CANPAGE_MOBNB = 0xf0 // MOb Number Bits + CANPAGE_AINC = 0x8 // MOb Data Buffer Auto Increment + CANPAGE_INDX = 0x7 // Data Buffer Index Bits + + // CANSTMOB: MOb Status Register + CANSTMOB_DLCW = 0x80 // Data Length Code Warning + CANSTMOB_TXOK = 0x40 // Transmit OK + CANSTMOB_RXOK = 0x20 // Receive OK + CANSTMOB_BERR = 0x10 // Bit Error + CANSTMOB_SERR = 0x8 // Stuff Error + CANSTMOB_CERR = 0x4 // CRC Error + CANSTMOB_FERR = 0x2 // Form Error + CANSTMOB_AERR = 0x1 // Ackknowledgement Error + + // CANCDMOB: MOb Control and DLC Register + CANCDMOB_CONMOB = 0xc0 // MOb Config Bits + CANCDMOB_RPLV = 0x20 // Reply Valid + CANCDMOB_IDE = 0x10 // Identifier Extension + CANCDMOB_DLC = 0xf // Data Length Code Bits + + // CANIDT4: Identifier Tag Register 4 + CANIDT4_IDT = 0xf8 // Identifier Tag + CANIDT4_RTRTAG = 0x4 // Remote Trasnmission Request Tag + CANIDT4_RB1TAG = 0x2 // Reserved Bit 1 Tag + CANIDT4_RB0TAG = 0x1 // Reserved Bit 0 Tag + + // CANIDT3: Identifier Tag Register 3 + CANIDT3_IDT = 0xff // Identifier Tag + + // CANIDT2: Identifier Tag Register 2 + CANIDT2_IDT = 0xff // Identifier Tag + + // CANIDT1: Identifier Tag Register 1 + CANIDT1_IDT = 0xff // Identifier Tag + + // CANIDM4: Identifier Mask Register 4 + CANIDM4_IDMSK = 0xf8 // Identifier Mask + CANIDM4_RTRMSK = 0x4 // Remote Transmission Request Mask + CANIDM4_IDEMSK = 0x1 // Identifier Extension Mask + + // CANIDM3: Identifier Mask Register 3 + CANIDM3_IDMSK = 0xff // Identifier Mask + + // CANIDM2: Identifier Mask Register 2 + CANIDM2_IDMSK = 0xff // Identifier Mask + + // CANIDM1: Identifier Mask Register 1 + CANIDM1_IDMSK = 0xff // Identifier Mask + + // CANSTML: Time Stamp Register + + // CANSTMH: Time Stamp Register + CANSTM_TIMSTM = 0xffff // Time Stamp Count + + // CANMSG: Message Data Register + CANMSG_MSG = 0xff // Message Data +) diff --git a/src/device/avr/at90can64.ld b/src/device/avr/at90can64.ld new file mode 100644 index 00000000..993bf55f --- /dev/null +++ b/src/device/avr/at90can64.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from AT90CAN64.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_size = 0x1000; +__num_isrs = 37; diff --git a/src/device/avr/at90pwm1.go b/src/device/avr/at90pwm1.go new file mode 100644 index 00000000..fc71cbb0 --- /dev/null +++ b/src/device/avr/at90pwm1.go @@ -0,0 +1,841 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from AT90PWM1.atdf, see http://packs.download.atmel.com/ + +// +build avr,at90pwm1 + +// Device information for the AT90PWM1. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "AT90PWM1" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset + IRQ_PSC2_CAPT = 1 // PSC2 Capture Event + IRQ_PSC2_EC = 2 // PSC2 End Cycle + IRQ_PSC1_CAPT = 3 // PSC1 Capture Event + IRQ_PSC1_EC = 4 // PSC1 End Cycle + IRQ_PSC0_CAPT = 5 // PSC0 Capture Event + IRQ_PSC0_EC = 6 // PSC0 End Cycle + IRQ_ANALOG_COMP_0 = 7 // Analog Comparator 0 + IRQ_ANALOG_COMP_1 = 8 // Analog Comparator 1 + IRQ_ANALOG_COMP_2 = 9 // Analog Comparator 2 + IRQ_INT0 = 10 // External Interrupt Request 0 + IRQ_TIMER1_CAPT = 11 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 12 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 13 // Timer/Counter Compare Match B + IRQ_RESERVED15 = 14 // + IRQ_TIMER1_OVF = 15 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP_A = 16 // Timer/Counter0 Compare Match A + IRQ_TIMER0_OVF = 17 // Timer/Counter0 Overflow + IRQ_ADC = 18 // ADC Conversion Complete + IRQ_INT1 = 19 // External Interrupt Request 1 + IRQ_SPI_STC = 20 // SPI Serial Transfer Complete + IRQ_USART_RX = 21 // USART, Rx Complete + IRQ_USART_UDRE = 22 // USART Data Register Empty + IRQ_USART_TX = 23 // USART, Tx Complete + IRQ_INT2 = 24 // External Interrupt Request 2 + IRQ_WDT = 25 // Watchdog Timeout Interrupt + IRQ_EE_READY = 26 // EEPROM Ready + IRQ_TIMER0_COMPB = 27 // Timer Counter 0 Compare Match B + IRQ_INT3 = 28 // External Interrupt Request 3 + IRQ_RESERVED30 = 29 // + IRQ_RESERVED31 = 30 // + IRQ_SPM_READY = 31 // Store Program Memory Read + IRQ_max = 31 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // I/O Port + PORT = struct { + PORTB __reg + DDRB __reg + PINB __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + }{ + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Port E Data Register + DDRE: 0x2d, // Port E Data Direction Register + PINE: 0x2c, // Port E Input Pins + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // Power Stage Controller + PSC = struct { + PICR0L __reg + PICR0H __reg + PFRC0B __reg + PFRC0A __reg + PCTL0 __reg + PCNF0 __reg + OCR0RBL __reg + OCR0RBH __reg + OCR0SBL __reg + OCR0SBH __reg + OCR0RAL __reg + OCR0RAH __reg + OCR0SAL __reg + OCR0SAH __reg + PSOC0 __reg + PIM0 __reg + PIFR0 __reg + PICR2L __reg + PICR2H __reg + PFRC2B __reg + PFRC2A __reg + PCTL2 __reg + PCNF2 __reg + OCR2RBL __reg + OCR2RBH __reg + OCR2SBL __reg + OCR2SBH __reg + OCR2RAL __reg + OCR2RAH __reg + OCR2SAL __reg + OCR2SAH __reg + POM2 __reg + PSOC2 __reg + PIM2 __reg + PIFR2 __reg + PICR1L __reg + PICR1H __reg + PFRC1B __reg + PFRC1A __reg + PCTL1 __reg + PSOC1 __reg + }{ + PICR0L: 0xde, // PSC 0 Input Capture Register + PICR0H: 0xde, // PSC 0 Input Capture Register + PFRC0B: 0xdd, // PSC 0 Input B Control + PFRC0A: 0xdc, // PSC 0 Input A Control + PCTL0: 0xdb, // PSC 0 Control Register + PCNF0: 0xda, // PSC 0 Configuration Register + OCR0RBL: 0xd8, // Output Compare RB Register + OCR0RBH: 0xd8, // Output Compare RB Register + OCR0SBL: 0xd6, // Output Compare SB Register + OCR0SBH: 0xd6, // Output Compare SB Register + OCR0RAL: 0xd4, // Output Compare RA Register + OCR0RAH: 0xd4, // Output Compare RA Register + OCR0SAL: 0xd2, // Output Compare SA Register + OCR0SAH: 0xd2, // Output Compare SA Register + PSOC0: 0xd0, // PSC0 Synchro and Output Configuration + PIM0: 0xa1, // PSC0 Interrupt Mask Register + PIFR0: 0xa0, // PSC0 Interrupt Flag Register + PICR2L: 0xfe, // PSC 2 Input Capture Register + PICR2H: 0xfe, // PSC 2 Input Capture Register + PFRC2B: 0xfd, // PSC 2 Input B Control + PFRC2A: 0xfc, // PSC 2 Input B Control + PCTL2: 0xfb, // PSC 2 Control Register + PCNF2: 0xfa, // PSC 2 Configuration Register + OCR2RBL: 0xf8, // Output Compare RB Register + OCR2RBH: 0xf8, // Output Compare RB Register + OCR2SBL: 0xf6, // Output Compare SB Register + OCR2SBH: 0xf6, // Output Compare SB Register + OCR2RAL: 0xf4, // Output Compare RA Register + OCR2RAH: 0xf4, // Output Compare RA Register + OCR2SAL: 0xf2, // Output Compare SA Register + OCR2SAH: 0xf2, // Output Compare SA Register + POM2: 0xf1, // PSC 2 Output Matrix + PSOC2: 0xf0, // PSC2 Synchro and Output Configuration + PIM2: 0xa5, // PSC2 Interrupt Mask Register + PIFR2: 0xa4, // PSC2 Interrupt Flag Register + PICR1L: 0xee, // PSC 1 Input Capture Register + PICR1H: 0xee, // PSC 1 Input Capture Register + PFRC1B: 0xed, // PSC 1 Input B Control + PFRC1A: 0xec, // PSC 1 Input B Control + PCTL1: 0xeb, // PSC 1 Control Register + PSOC1: 0xe0, // PSC1 Synchro and Output Configuration + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + MCUCR __reg + MCUSR __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + GPIOR3 __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PLLCSR __reg + PRR __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, + SMCR: 0x53, // Sleep Mode Control Register + GPIOR3: 0x3b, // General Purpose IO Register 3 + GPIOR2: 0x3a, // General Purpose IO Register 2 + GPIOR1: 0x39, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PLLCSR: 0x49, // PLL Control And Status Register + PRR: 0x64, // Power Reduction Register + } + + // Timer/Counter, 8-bit + TC8 = struct { + TIMSK0 __reg + TIFR0 __reg + TCCR0A __reg + TCCR0B __reg + TCNT0 __reg + OCR0A __reg + OCR0B __reg + }{ + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + TCCR0A: 0x44, // Timer/Counter Control Register A + TCCR0B: 0x45, // Timer/Counter Control Register B + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + ADCSRB __reg + DIDR0 __reg + DIDR1 __reg + AMP0CSR __reg + AMP1CSR __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRB: 0x7b, // ADC Control and Status Register B + DIDR0: 0x7e, // Digital Input Disable Register 0 + DIDR1: 0x7f, // Digital Input Disable Register 1 + AMP0CSR: 0x76, + AMP1CSR: 0x77, + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access Bytes + EEARH: 0x41, // EEPROM Read/Write Access Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Analog Comparator + AC = struct { + AC0CON __reg + AC2CON __reg + ACSR __reg + }{ + AC0CON: 0xad, // Analog Comparator 0 Control Register + AC2CON: 0xaf, // Analog Comparator 2 Control Register + ACSR: 0x50, // Analog Comparator Status Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_PSC2RB = 0x80 // PSC2 Reset Behavior + EXTENDED_PSC0RB = 0x20 // PSC0 Reset Behavior + EXTENDED_PSCRV = 0x10 // PSCOUT Reset Value + EXTENDED_BOOTSZ = 0x6 // Select Boot Size + EXTENDED_BOOTRST = 0x1 // Select Reset Vector + + // HIGH + HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PC6 as i/o pin) + HIGH_DWEN = 0x40 // Debug Wire enable + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watch-dog Timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BODLEVEL = 0x7 // Brown-out Detector Trigger Level + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTB0 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for PSC: Power Stage Controller +const ( + // PICR0L: PSC 0 Input Capture Register + + // PICR0H: PSC 0 Input Capture Register + PICR0_PCST0 = 0x8000 // PSC 0 Capture Software Trig bit + PICR0_PICR0 = 0xfff // PSC 0 Capture Register + + // PFRC0B: PSC 0 Input B Control + PFRC0B_PCAE0B = 0x80 // PSC 0 Capture Enable Input Part B + PFRC0B_PISEL0B = 0x40 // PSC 0 Input Select for Part B + PFRC0B_PELEV0B = 0x20 // PSC 0 Edge Level Selector on Input Part B + PFRC0B_PFLTE0B = 0x10 // PSC 0 Filter Enable on Input Part B + PFRC0B_PRFM0B = 0xf // PSC 0 Retrigger and Fault Mode for Part B + + // PFRC0A: PSC 0 Input A Control + PFRC0A_PCAE0A = 0x80 // PSC 0 Capture Enable Input Part A + PFRC0A_PISEL0A = 0x40 // PSC 0 Input Select for Part A + PFRC0A_PELEV0A = 0x20 // PSC 0 Edge Level Selector on Input Part A + PFRC0A_PFLTE0A = 0x10 // PSC 0 Filter Enable on Input Part A + PFRC0A_PRFM0A = 0xf // PSC 0 Retrigger and Fault Mode for Part A + + // PCTL0: PSC 0 Control Register + PCTL0_PPRE0 = 0xc0 // PSC 0 Prescaler Selects + PCTL0_PBFM0 = 0x20 // PSC 0 Balance Flank Width Modulation + PCTL0_PAOC0B = 0x10 // PSC 0 Asynchronous Output Control B + PCTL0_PAOC0A = 0x8 // PSC 0 Asynchronous Output Control A + PCTL0_PARUN0 = 0x4 // PSC0 Auto Run + PCTL0_PCCYC0 = 0x2 // PSC0 Complete Cycle + PCTL0_PRUN0 = 0x1 // PSC 0 Run + + // PCNF0: PSC 0 Configuration Register + PCNF0_PFIFTY0 = 0x80 // PSC 0 Fifty + PCNF0_PALOCK0 = 0x40 // PSC 0 Autolock + PCNF0_PLOCK0 = 0x20 // PSC 0 Lock + PCNF0_PMODE0 = 0x18 // PSC 0 Mode + PCNF0_POP0 = 0x4 // PSC 0 Output Polarity + PCNF0_PCLKSEL0 = 0x2 // PSC 0 Input Clock Select + + // PSOC0: PSC0 Synchro and Output Configuration + PSOC0_PSYNC0 = 0x30 // Synchronization Out for ADC Selection + PSOC0_POEN0B = 0x4 // PSCOUT01 Output Enable + PSOC0_POEN0A = 0x1 // PSCOUT00 Output Enable + + // PIM0: PSC0 Interrupt Mask Register + PIM0_PSEIE0 = 0x20 // PSC 0 Synchro Error Interrupt Enable + PIM0_PEVE0B = 0x10 // External Event B Interrupt Enable + PIM0_PEVE0A = 0x8 // External Event A Interrupt Enable + PIM0_PEOPE0 = 0x1 // End of Cycle Interrupt Enable + + // PIFR0: PSC0 Interrupt Flag Register + PIFR0_PSEI0 = 0x20 // PSC 0 Synchro Error Interrupt + PIFR0_PEV0B = 0x10 // External Event B Interrupt + PIFR0_PEV0A = 0x8 // External Event A Interrupt + PIFR0_PRN0 = 0x6 // Ramp Number + PIFR0_PEOP0 = 0x1 // End of PSC0 Interrupt + + // PICR2L: PSC 2 Input Capture Register + + // PICR2H: PSC 2 Input Capture Register + PICR2_PCST2 = 0x8000 // PSC 2 Capture Software Trig bit + PICR2_PICR2 = 0xfff // PSC 2 Input Capture Register + + // PFRC2B: PSC 2 Input B Control + PFRC2B_PCAE2B = 0x80 // PSC 2 Capture Enable Input Part B + PFRC2B_PISEL2B = 0x40 // PSC 2 Input Select for Part B + PFRC2B_PELEV2B = 0x20 // PSC 2 Edge Level Selector on Input Part B + PFRC2B_PFLTE2B = 0x10 // PSC 2 Filter Enable on Input Part B + PFRC2B_PRFM2B = 0xf // PSC 2 Retrigger and Fault Mode for Part B + + // PFRC2A: PSC 2 Input B Control + PFRC2A_PCAE2A = 0x80 // PSC 2 Capture Enable Input Part A + PFRC2A_PISEL2A = 0x40 // PSC 2 Input Select for Part A + PFRC2A_PELEV2A = 0x20 // PSC 2 Edge Level Selector on Input Part A + PFRC2A_PFLTE2A = 0x10 // PSC 2 Filter Enable on Input Part A + PFRC2A_PRFM2A = 0xf // PSC 2 Retrigger and Fault Mode for Part A + + // PCTL2: PSC 2 Control Register + PCTL2_PPRE2 = 0xc0 // PSC 2 Prescaler Selects + PCTL2_PBFM2 = 0x20 // Balance Flank Width Modulation + PCTL2_PAOC2B = 0x10 // PSC 2 Asynchronous Output Control B + PCTL2_PAOC2A = 0x8 // PSC 2 Asynchronous Output Control A + PCTL2_PARUN2 = 0x4 // PSC2 Auto Run + PCTL2_PCCYC2 = 0x2 // PSC2 Complete Cycle + PCTL2_PRUN2 = 0x1 // PSC 2 Run + + // PCNF2: PSC 2 Configuration Register + PCNF2_PFIFTY2 = 0x80 // PSC 2 Fifty + PCNF2_PALOCK2 = 0x40 // PSC 2 Autolock + PCNF2_PLOCK2 = 0x20 // PSC 2 Lock + PCNF2_PMODE2 = 0x18 // PSC 2 Mode + PCNF2_POP2 = 0x4 // PSC 2 Output Polarity + PCNF2_PCLKSEL2 = 0x2 // PSC 2 Input Clock Select + PCNF2_POME2 = 0x1 // PSC 2 Output Matrix Enable + + // POM2: PSC 2 Output Matrix + POM2_POMV2B = 0xf0 // Output Matrix Output B Ramps + POM2_POMV2A = 0xf // Output Matrix Output A Ramps + + // PSOC2: PSC2 Synchro and Output Configuration + PSOC2_POS2 = 0xc0 // PSC 2 Output 23 Select + PSOC2_PSYNC2 = 0x30 // Synchronization Out for ADC Selection + PSOC2_POEN2D = 0x8 // PSCOUT23 Output Enable + PSOC2_POEN2B = 0x4 // PSCOUT21 Output Enable + PSOC2_POEN2C = 0x2 // PSCOUT22 Output Enable + PSOC2_POEN2A = 0x1 // PSCOUT20 Output Enable + + // PIM2: PSC2 Interrupt Mask Register + PIM2_PSEIE2 = 0x20 // PSC 2 Synchro Error Interrupt Enable + PIM2_PEVE2B = 0x10 // External Event B Interrupt Enable + PIM2_PEVE2A = 0x8 // External Event A Interrupt Enable + PIM2_PEOPE2 = 0x1 // End of Cycle Interrupt Enable + + // PIFR2: PSC2 Interrupt Flag Register + PIFR2_PSEI2 = 0x20 // PSC 2 Synchro Error Interrupt + PIFR2_PEV2B = 0x10 // External Event B Interrupt + PIFR2_PEV2A = 0x8 // External Event A Interrupt + PIFR2_PRN2 = 0x6 // Ramp Number + PIFR2_PEOP2 = 0x1 // End of PSC2 Interrupt + + // PFRC1B: PSC 1 Input B Control + PFRC1B_PCAE1B = 0x80 // PSC 1 Capture Enable Input Part B + PFRC1B_PISEL1B = 0x40 // PSC 1 Input Select for Part B + PFRC1B_PELEV1B = 0x20 // PSC 1 Edge Level Selector on Input Part B + PFRC1B_PFLTE1B = 0x10 // PSC 1 Filter Enable on Input Part B + PFRC1B_PRFM1B = 0xf // PSC 1 Retrigger and Fault Mode for Part B + + // PFRC1A: PSC 1 Input B Control + PFRC1A_PCAE1A = 0x80 // PSC 1 Capture Enable Input Part A + PFRC1A_PISEL1A = 0x40 // PSC 1 Input Select for Part A + PFRC1A_PELEV1A = 0x20 // PSC 1 Edge Level Selector on Input Part A + PFRC1A_PFLTE1A = 0x10 // PSC 1 Filter Enable on Input Part A + PFRC1A_PRFM1A = 0xf // PSC 1 Retrigger and Fault Mode for Part A + + // PCTL1: PSC 1 Control Register + PCTL1_PPRE1 = 0xc0 // PSC 1 Prescaler Selects + PCTL1_PBFM1 = 0x20 // Balance Flank Width Modulation + PCTL1_PAOC1B = 0x10 // PSC 1 Asynchronous Output Control B + PCTL1_PAOC1A = 0x8 // PSC 1 Asynchronous Output Control A + PCTL1_PARUN1 = 0x4 // PSC1 Auto Run + PCTL1_PCCYC1 = 0x2 // PSC1 Complete Cycle + PCTL1_PRUN1 = 0x1 // PSC 1 Run + + // PSOC1: PSC1 Synchro and Output Configuration + PSOC1_PSYNC1 = 0x30 // Synchronization Out for ADC Selection + PSOC1_POEN1B = 0x4 // PSCOUT11 Output Enable + PSOC1_POEN1A = 0x1 // PSCOUT10 Output Enable +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // MCUCR: MCU Control Register + MCUCR_SPIPS = 0x80 // SPI Pin Select + MCUCR_PUD = 0x10 // Pull-up disable + MCUCR_IVSEL = 0x2 // Interrupt Vector Select + MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable + + // MCUSR: MCU Status Register + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BORF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR3: General Purpose IO Register 3 + GPIOR3_GPIOR = 0xff // General Purpose IO Register 3 bis + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 + + // PLLCSR: PLL Control And Status Register + PLLCSR_PLLF = 0x4 // PLL Factor + PLLCSR_PLLE = 0x2 // PLL Enable + PLLCSR_PLOCK = 0x1 // PLL Lock Detector + + // PRR: Power Reduction Register + PRR_PRPSC2 = 0x80 // Power Reduction PSC2 + PRR_PRPSC1 = 0x40 // Power Reduction PSC1 + PRR_PRPSC0 = 0x20 // Power Reduction PSC0 + PRR_PRTIM1 = 0x10 // Power Reduction Timer/Counter1 + PRR_PRTIM0 = 0x8 // Power Reduction Timer/Counter0 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCNT0: Timer/Counter0 + TCNT0_TCNT0 = 0xff // Timer Counter 0 value + + // OCR0A: Timer/Counter0 Output Compare Register + OCR0A_OCR0A = 0xff // Output Compare A value + + // OCR0B: Timer/Counter0 Output Compare Register + OCR0B_OCR0B = 0xff // Output Compare B value +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TIMSK1: Timer/Counter Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output CompareB Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output CompareA Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 + TCCR1C_FOC1B = 0x40 + + // TCNT1L: Timer/Counter1 Bytes + + // TCNT1H: Timer/Counter1 Bytes + TCNT1_TCNT1 = 0xffff // Timer/Counter1 + + // OCR1AL: Timer/Counter1 Output Compare Register Bytes + + // OCR1AH: Timer/Counter1 Output Compare Register Bytes + OCR1A_OCR1A = 0xffff // Timer/Counter1 Output Compare A Register + + // OCR1BL: Timer/Counter1 Output Compare Register Bytes + + // OCR1BH: Timer/Counter1 Output Compare Register Bytes + OCR1B_OCR1B = 0xffff // Timer/Counter1 Output Compare B Register + + // ICR1L: Timer/Counter1 Input Capture Register Bytes + + // ICR1H: Timer/Counter1 Input Capture Register Bytes + ICR1_ICR1 = 0xffff // Timer/Counter Input Capture +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0xf // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCSRB: ADC Control and Status Register B + ADCSRB_ADHSM = 0x80 // ADC High Speed Mode + ADCSRB_ADASCR = 0x10 // ADC Start Conversion + ADCSRB_ADTS3 = 0x8 // ADC Auto Trigger Source Selection 3 + ADCSRB_ADTS2 = 0x4 // ADC Auto Trigger Source Selection 2 + ADCSRB_ADTS1 = 0x2 // ADC Auto Trigger Source Selection 1 + ADCSRB_ADTS0 = 0x1 // ADC Auto Trigger Source Selection 0 + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 + DIDR0_ADC6D = 0x40 + DIDR0_ADC5D = 0x20 + DIDR0_ADC4D = 0x10 + DIDR0_ADC3D = 0x8 + DIDR0_ADC2D = 0x4 + DIDR0_ADC1D = 0x2 + DIDR0_ADC0D = 0x1 + + // DIDR1: Digital Input Disable Register 1 + DIDR1_ACMP0D = 0x20 + DIDR1_AMP0PD = 0x10 + DIDR1_AMP0ND = 0x8 + DIDR1_ADC10D = 0x4 + DIDR1_ADC9D = 0x2 + DIDR1_ADC8D = 0x1 + + // AMP0CSR + AMP0CSR_AMP0EN = 0x80 + AMP0CSR_AMP0IS = 0x40 + AMP0CSR_AMP0G = 0x30 + AMP0CSR_AMP0TS = 0x3 + + // AMP1CSR + AMP1CSR_AMP1EN = 0x80 + AMP1CSR_AMP1IS = 0x40 + AMP1CSR_AMP1G = 0x30 + AMP1CSR_AMP1TS = 0x3 +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPDR: SPI Data Register + SPDR_SPD = 0xff // SPI Data +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xf // External Interrupt Mask + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xf // External Interrupt Flags +) + +// Bitfields for EEPROM: EEPROM +const ( + // EEARL: EEPROM Read/Write Access Bytes + + // EEARH: EEPROM Read/Write Access Bytes + EEAR_EEAR = 0xfff // EEPROM Address bytes + + // EEDR: EEPROM Data Register + EEDR_EEDR = 0xff // EEPROM Data Bits + + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for AC: Analog Comparator +const ( + // AC0CON: Analog Comparator 0 Control Register + AC0CON_AC0EN = 0x80 // Analog Comparator 0 Enable Bit + AC0CON_AC0IE = 0x40 // Analog Comparator 0 Interrupt Enable Bit + AC0CON_AC0IS = 0x30 // Analog Comparator 0 Interrupt Select Bit + AC0CON_AC0M = 0x7 // Analog Comparator 0 Multiplexer Register + + // AC2CON: Analog Comparator 2 Control Register + AC2CON_AC2EN = 0x80 // Analog Comparator 2 Enable Bit + AC2CON_AC2IE = 0x40 // Analog Comparator 2 Interrupt Enable Bit + AC2CON_AC2IS = 0x30 // Analog Comparator 2 Interrupt Select Bit + AC2CON_AC2M = 0x7 // Analog Comparator 2 Multiplexer Register + + // ACSR: Analog Comparator Status Register + ACSR_ACCKDIV = 0x80 // Analog Comparator Clock Divider + ACSR_AC2IF = 0x40 // Analog Comparator 2 Interrupt Flag Bit + ACSR_AC1IF = 0x20 // Analog Comparator 1 Interrupt Flag Bit + ACSR_AC0IF = 0x10 // Analog Comparator 0 Interrupt Flag Bit + ACSR_AC2O = 0x4 // Analog Comparator 2 Output Bit + ACSR_AC1O = 0x2 // Analog Comparator 1 Output Bit + ACSR_AC0O = 0x1 // Analog Comparator 0 Output Bit +) diff --git a/src/device/avr/at90pwm1.ld b/src/device/avr/at90pwm1.ld new file mode 100644 index 00000000..bc6a246e --- /dev/null +++ b/src/device/avr/at90pwm1.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from AT90PWM1.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_size = 0x200; +__num_isrs = 32; diff --git a/src/device/avr/at90pwm161.go b/src/device/avr/at90pwm161.go new file mode 100644 index 00000000..7b2be0c4 --- /dev/null +++ b/src/device/avr/at90pwm161.go @@ -0,0 +1,757 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from AT90PWM161.atdf, see http://packs.download.atmel.com/ + +// +build avr,at90pwm161 + +// Device information for the AT90PWM161. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "AT90PWM161" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset + IRQ_PSC2_CAPT = 1 // PSC2 Capture Event + IRQ_PSC2_EC = 2 // PSC2 End Cycle + IRQ_PSC2_EEC = 3 // PSC2 End Of Enhanced Cycle + IRQ_PSC0_CAPT = 4 // PSC0 Capture Event + IRQ_PSC0_EC = 5 // PSC0 End Cycle + IRQ_PSC0_EEC = 6 // PSC0 End Of Enhanced Cycle + IRQ_ANALOG_COMP_1 = 7 // Analog Comparator 1 + IRQ_ANALOG_COMP_2 = 8 // Analog Comparator 2 + IRQ_ANALOG_COMP_3 = 9 // Analog Comparator 3 + IRQ_INT0 = 10 // External Interrupt Request 0 + IRQ_TIMER1_CAPT = 11 // Timer/Counter1 Capture Event + IRQ_TIMER1_OVF = 12 // Timer/Counter1 Overflow + IRQ_ADC = 13 // ADC Conversion Complete + IRQ_INT1 = 14 // External Interrupt Request 1 + IRQ_SPI_STC = 15 // SPI Serial Transfer Complet + IRQ_INT2 = 16 // External Interrupt Request 2 + IRQ_WDT = 17 // Watchdog Timeout Interrupt + IRQ_EE_READY = 18 // EEPROM Ready + IRQ_SPM_READY = 19 // Store Program Memory Read + IRQ_max = 19 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // I/O Port + PORT = struct { + PORTB __reg + DDRB __reg + PINB __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + }{ + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Port E Data Register + DDRE: 0x2d, // Port E Data Direction Register + PINE: 0x2c, // Port E Input Pins + } + + // Digital-to-Analog Converter + DAC = struct { + DACH __reg + DACL __reg + DACON __reg + }{ + DACH: 0x59, // DAC Data Register High Byte + DACL: 0x58, // DAC Data Register Low Byte + DACON: 0x76, // DAC Control Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x37, // SPI Control Register + SPSR: 0x38, // SPI Status Register + SPDR: 0x56, // SPI Data Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x82, // Watchdog Timer Control Register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + }{ + EICRA: 0x89, // External Interrupt Control Register A + EIMSK: 0x41, // External Interrupt Mask Register + EIFR: 0x40, // External Interrupt Flag Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + ADCSRB __reg + DIDR0 __reg + DIDR1 __reg + AMP0CSR __reg + }{ + ADMUX: 0x28, // The ADC multiplexer Selection Register + ADCSRA: 0x26, // The ADC Control and Status register + ADCL: 0x4c, // ADC Data Register Bytes + ADCH: 0x4c, // ADC Data Register Bytes + ADCSRB: 0x27, // ADC Control and Status Register B + DIDR0: 0x77, // Digital Input Disable Register 0 + DIDR1: 0x78, // Digital Input Disable Register 0 + AMP0CSR: 0x79, + } + + // Analog Comparator + AC = struct { + AC3CON __reg + AC1CON __reg + AC2CON __reg + ACSR __reg + AC3ECON __reg + AC2ECON __reg + AC1ECON __reg + }{ + AC3CON: 0x7f, // Analog Comparator3 Control Register + AC1CON: 0x7d, // Analog Comparator 1 Control Register + AC2CON: 0x7e, // Analog Comparator 2 Control Register + ACSR: 0x20, // Analog Comparator Status Register + AC3ECON: 0x7c, + AC2ECON: 0x7b, + AC1ECON: 0x7a, + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + MCUCR __reg + MCUSR __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PLLCSR __reg + PRR __reg + CLKCSR __reg + CLKSELR __reg + BGCCR __reg + BGCRR __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + OSCCAL: 0x88, // Oscillator Calibration Value + CLKPR: 0x83, + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x3b, // General Purpose IO Register 2 + GPIOR1: 0x3a, // General Purpose IO Register 1 + GPIOR0: 0x39, // General Purpose IO Register 0 + PLLCSR: 0x87, // PLL Control And Status Register + PRR: 0x86, // Power Reduction Register + CLKCSR: 0x84, + CLKSELR: 0x85, + BGCCR: 0x81, // BandGap Current Calibration Register + BGCRR: 0x80, // BandGap Resistor Calibration Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x3e, // EEPROM Read/Write Access Bytes + EEARH: 0x3e, // EEPROM Read/Write Access Bytes + EEDR: 0x3d, // EEPROM Data Register + EECR: 0x3c, // EEPROM Control Register + } + + // Power Stage Controller + PSC = struct { + PICR0L __reg + PICR0H __reg + PFRC0B __reg + PFRC0A __reg + PCTL0 __reg + PCNF0 __reg + OCR0RBL __reg + OCR0RBH __reg + OCR0SBL __reg + OCR0SBH __reg + OCR0RAL __reg + OCR0RAH __reg + OCR0SAL __reg + OCR0SAH __reg + PSOC0 __reg + PIM0 __reg + PIFR0 __reg + PICR2H __reg + PICR2L __reg + PFRC2B __reg + PFRC2A __reg + PCTL2 __reg + PCNF2 __reg + PCNFE2 __reg + OCR2RBL __reg + OCR2RBH __reg + OCR2SBL __reg + OCR2SBH __reg + OCR2RAL __reg + OCR2RAH __reg + OCR2SAL __reg + OCR2SAH __reg + POM2 __reg + PSOC2 __reg + PIM2 __reg + PIFR2 __reg + PASDLY2 __reg + }{ + PICR0L: 0x68, // PSC 0 Input Capture Register + PICR0H: 0x68, // PSC 0 Input Capture Register + PFRC0B: 0x63, // PSC 0 Input B Control + PFRC0A: 0x62, // PSC 0 Input A Control + PCTL0: 0x32, // PSC 0 Control Register + PCNF0: 0x31, // PSC 0 Configuration Register + OCR0RBL: 0x44, // Output Compare RB Register + OCR0RBH: 0x44, // Output Compare RB Register + OCR0SBL: 0x42, // Output Compare SB Register + OCR0SBH: 0x42, // Output Compare SB Register + OCR0RAL: 0x4a, // Output Compare RA Register + OCR0RAH: 0x4a, // Output Compare RA Register + OCR0SAL: 0x60, // Output Compare SA Register + OCR0SAH: 0x60, // Output Compare SA Register + PSOC0: 0x6a, // PSC0 Synchro and Output Configuration + PIM0: 0x2f, // PSC0 Interrupt Mask Register + PIFR0: 0x30, // PSC0 Interrupt Flag Register + PICR2H: 0x6d, // PSC 2 Input Capture Register High + PICR2L: 0x6c, // PSC 2 Input Capture Register Low + PFRC2B: 0x67, // PSC 2 Input B Control + PFRC2A: 0x66, // PSC 2 Input B Control + PCTL2: 0x36, // PSC 2 Control Register + PCNF2: 0x35, // PSC 2 Configuration Register + PCNFE2: 0x70, // PSC 2 Enhanced Configuration Register + OCR2RBL: 0x48, // Output Compare RB Register + OCR2RBH: 0x48, // Output Compare RB Register + OCR2SBL: 0x46, // Output Compare SB Register + OCR2SBH: 0x46, // Output Compare SB Register + OCR2RAL: 0x4e, // Output Compare RA Register + OCR2RAH: 0x4e, // Output Compare RA Register + OCR2SAL: 0x64, // Output Compare SA Register + OCR2SAH: 0x64, // Output Compare SA Register + POM2: 0x6f, // PSC 2 Output Matrix + PSOC2: 0x6e, // PSC2 Synchro and Output Configuration + PIM2: 0x33, // PSC2 Interrupt Mask Register + PIFR2: 0x34, // PSC2 Interrupt Flag Register + PASDLY2: 0x71, // Analog Synchronization Delay Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1B __reg + TCNT1L __reg + TCNT1H __reg + ICR1L __reg + ICR1H __reg + }{ + TIMSK1: 0x21, // Timer/Counter Interrupt Mask Register + TIFR1: 0x22, // Timer/Counter Interrupt Flag register + TCCR1B: 0x8a, // Timer/Counter1 Control Register B + TCNT1L: 0x5a, // Timer/Counter1 Bytes + TCNT1H: 0x5a, // Timer/Counter1 Bytes + ICR1L: 0x8c, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x8c, // Timer/Counter1 Input Capture Register Bytes + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_PSC2RB = 0x80 // PSC2 Reset Behavior + EXTENDED_PSC2RBA = 0x40 // PSC2 Reset Behavior for 22 and 23 + EXTENDED_PSC0RB = 0x20 // PSC0 Reset Behavior + EXTENDED_PSCRV = 0x10 // PSC Reset Value + EXTENDED_PSCINRB = 0x8 // PSC2 and PSC0 input Reset Behavior + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector Trigger Level + + // HIGH + HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PE0 as I/O pin) + HIGH_DWEN = 0x40 // Debug Wire enable + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watch-dog Timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Select Reset Vector + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTD1 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for DAC: Digital-to-Analog Converter +const ( + // DACH: DAC Data Register High Byte + DACH_DACH = 0xff // DAC Data Register High Byte Bits + + // DACL: DAC Data Register Low Byte + DACL_DACL = 0xff // DAC Data Register Low Byte Bits + + // DACON: DAC Control Register + DACON_DAATE = 0x80 // DAC Auto Trigger Enable Bit + DACON_DATS = 0x70 // DAC Trigger Selection Bits + DACON_DALA = 0x4 // DAC Left Adjust + DACON_DAEN = 0x1 // DAC Enable Bit +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0x7 // External Interrupt Request 2 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0x7 // External Interrupt Flags +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0xf // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCSRB: ADC Control and Status Register B + ADCSRB_ADHSM = 0x80 // ADC High Speed Mode + ADCSRB_ADNCDIS = 0x40 // ADC Noise Canceller Disable + ADCSRB_ADSSEN = 0x10 // ADC Single Shot Enable on PSC's Synchronisation Signals + ADCSRB_ADTS = 0xf // ADC Auto Trigger Sources + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 + DIDR0_ADC6D = 0x40 // ADC7 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable + + // DIDR1: Digital Input Disable Register 0 + DIDR1_ACMP1MD = 0x8 + DIDR1_AMP0POSD = 0x4 + DIDR1_ADC10D = 0x2 + DIDR1_ADC9D = 0x1 + + // AMP0CSR + AMP0CSR_AMP0EN = 0x80 + AMP0CSR_AMP0IS = 0x40 + AMP0CSR_AMP0G = 0x30 + AMP0CSR_AMP0GS = 0x8 + AMP0CSR_AMP0TS = 0x3 +) + +// Bitfields for AC: Analog Comparator +const ( + // AC3CON: Analog Comparator3 Control Register + AC3CON_AC3EN = 0x80 // Analog Comparator3 Enable Bit + AC3CON_AC3IE = 0x40 // Analog Comparator 3 Interrupt Enable Bit + AC3CON_AC3IS = 0x30 // Analog Comparator 3 Interrupt Select Bit + AC3CON_AC3OEA = 0x8 // Analog Comparator 3 Alternate Output Enable + AC3CON_AC3M = 0x7 // Analog Comparator 3 Multiplexer Register + + // AC1CON: Analog Comparator 1 Control Register + AC1CON_AC1EN = 0x80 // Analog Comparator 1 Enable Bit + AC1CON_AC1IE = 0x40 // Analog Comparator 1 Interrupt Enable Bit + AC1CON_AC1IS = 0x30 // Analog Comparator 1 Interrupt Select Bit + AC1CON_AC1M = 0x7 // Analog Comparator 1 Multiplexer Register + + // AC2CON: Analog Comparator 2 Control Register + AC2CON_AC2EN = 0x80 // Analog Comparator 2 Enable Bit + AC2CON_AC2IE = 0x40 // Analog Comparator 2 Interrupt Enable Bit + AC2CON_AC2IS = 0x30 // Analog Comparator 2 Interrupt Select Bit + AC2CON_AC2M = 0x7 // Analog Comparator 2 Multiplexer Register + + // ACSR: Analog Comparator Status Register + ACSR_AC3IF = 0x80 // Analog Comparator 3 Interrupt Flag Bit + ACSR_AC2IF = 0x40 // Analog Comparator 2 Interrupt Flag Bit + ACSR_AC1IF = 0x20 // Analog Comparator 1 Interrupt Flag Bit + ACSR_AC3O = 0x8 // Analog Comparator 3 Output Bit + ACSR_AC2O = 0x4 // Analog Comparator 2 Output Bit + ACSR_AC1O = 0x2 // Analog Comparator 1 Output Bit + + // AC3ECON + AC3ECON_AC3OI = 0x20 // Analog Comparator Ouput Invert + AC3ECON_AC3OE = 0x10 // Analog Comparator Ouput Enable + AC3ECON_AC3H = 0x7 // Analog Comparator Hysteresis Select + + // AC2ECON + AC2ECON_AC2OI = 0x20 // Analog Comparator Ouput Invert + AC2ECON_AC2OE = 0x10 // Analog Comparator Ouput Enable + AC2ECON_AC2H = 0x7 // Analog Comparator Hysteresis Select + + // AC1ECON + AC1ECON_AC1OI = 0x20 // Analog Comparator Ouput Invert + AC1ECON_AC1OE = 0x10 // Analog Comparator Ouput Enable + AC1ECON_AC1ICE = 0x8 // Analog Comparator Interrupt Capture Enable + AC1ECON_AC1H = 0x7 // Analog Comparator Hysteresis Select +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // MCUCR: MCU Control Register + MCUCR_PUD = 0x10 // Pull-up disable + MCUCR_RSTDIS = 0x8 // Reset Pin Disable + MCUCR_CKRC81 = 0x4 // Frequency Selection of the Calibrated RC Oscillator + MCUCR_IVSEL = 0x2 // Interrupt Vector Select + MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable + + // MCUSR: MCU Status Register + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BORF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 + + // PLLCSR: PLL Control And Status Register + PLLCSR_PLLF = 0x3c + PLLCSR_PLLE = 0x2 // PLL Enable + PLLCSR_PLOCK = 0x1 // PLL Lock Detector + + // PRR: Power Reduction Register + PRR_PRPSC2 = 0x80 // Power Reduction PSC2 + PRR_PRPSCR = 0x20 // Power Reduction PSC0 + PRR_PRTIM1 = 0x10 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRADC = 0x1 // Power Reduction ADC + + // CLKCSR + CLKCSR_CLKCCE = 0x80 // Clock Control Change Enable + CLKCSR_CLKRDY = 0x10 // Clock Ready Flag + CLKCSR_CLKC = 0xf // Clock Control + + // CLKSELR + CLKSELR_COUT = 0x40 // Clock OUT + CLKSELR_CSUT = 0x30 // Clock Start up Time + CLKSELR_CKSEL = 0xf // Clock Source Select + + // BGCCR: BandGap Current Calibration Register + BGCCR_BGCC = 0xf + + // BGCRR: BandGap Resistor Calibration Register + BGCRR_BGCR = 0xf +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_NVMBSY = 0x80 // None Volatile Busy Memory Busy + EECR_EEPAGE = 0x40 // EEPROM Page Access + EECR_EEPM = 0x30 // EEPROM Programming Mode + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for PSC: Power Stage Controller +const ( + // PFRC0B: PSC 0 Input B Control + PFRC0B_PCAE0B = 0x80 // PSC 0 Capture Enable Input Part B + PFRC0B_PISEL0B = 0x40 // PSC 0 Input Select for Part B + PFRC0B_PELEV0B = 0x20 // PSC 0 Edge Level Selector on Input Part B + PFRC0B_PFLTE0B = 0x10 // PSC 0 Filter Enable on Input Part B + PFRC0B_PRFM0B = 0xf // PSC 0 Retrigger and Fault Mode for Part B + + // PFRC0A: PSC 0 Input A Control + PFRC0A_PCAE0A = 0x80 // PSC 0 Capture Enable Input Part A + PFRC0A_PISEL0A = 0x40 // PSC 0 Input Select for Part A + PFRC0A_PELEV0A = 0x20 // PSC 0 Edge Level Selector on Input Part A + PFRC0A_PFLTE0A = 0x10 // PSC 0 Filter Enable on Input Part A + PFRC0A_PRFM0A = 0xf // PSC 0 Retrigger and Fault Mode for Part A + + // PCTL0: PSC 0 Control Register + PCTL0_PPRE0 = 0xc0 // PSC 0 Prescaler Selects + PCTL0_PBFM0 = 0x24 // PSC 0 Balance Flank Width Modulation + PCTL0_PAOC0B = 0x10 // PSC 0 Asynchronous Output Control B + PCTL0_PAOC0A = 0x8 // PSC 0 Asynchronous Output Control A + PCTL0_PCCYC0 = 0x2 // PSC0 Complete Cycle + PCTL0_PRUN0 = 0x1 // PSC 0 Run + + // PCNF0: PSC 0 Configuration Register + PCNF0_PFIFTY0 = 0x80 // PSC 0 Fifty + PCNF0_PALOCK0 = 0x40 // PSC 0 Autolock + PCNF0_PLOCK0 = 0x20 // PSC 0 Lock + PCNF0_PMODE0 = 0x18 // PSC 0 Mode + PCNF0_POP0 = 0x4 // PSC 0 Output Polarity + PCNF0_PCLKSEL0 = 0x2 // PSC 0 Input Clock Select + + // PSOC0: PSC0 Synchro and Output Configuration + PSOC0_PISEL0A1 = 0x80 // PSC Input Select + PSOC0_PISEL0B1 = 0x40 // PSC Input Select + PSOC0_PSYNC0 = 0x30 // Synchronisation out for ADC selection + PSOC0_POEN0B = 0x4 // PSCOUT01 Output Enable + PSOC0_POEN0A = 0x1 // PSCOUT00 Output Enable + + // PIM0: PSC0 Interrupt Mask Register + PIM0_PEVE0B = 0x10 // External Event B Interrupt Enable + PIM0_PEVE0A = 0x8 // External Event A Interrupt Enable + PIM0_PEOEPE0 = 0x2 // End of Enhanced Cycle Enable + PIM0_PEOPE0 = 0x1 // End of Cycle Interrupt Enable + + // PIFR0: PSC0 Interrupt Flag Register + PIFR0_POAC0B = 0x80 // PSC 0 Output A Activity + PIFR0_POAC0A = 0x40 // PSC 0 Output A Activity + PIFR0_PEV0B = 0x10 // External Event B Interrupt + PIFR0_PEV0A = 0x8 // External Event A Interrupt + PIFR0_PRN0 = 0x6 // Ramp Number + PIFR0_PEOP0 = 0x1 // End of PSC0 Interrupt + + // PICR2H: PSC 2 Input Capture Register High + PICR2H_PCST2 = 0x80 // PSC 2 Capture Software Trigger Bit + PICR2H_PICR21 = 0xc + PICR2H_PICR2 = 0x3 + + // PFRC2B: PSC 2 Input B Control + PFRC2B_PCAE2B = 0x80 // PSC 2 Capture Enable Input Part B + PFRC2B_PISEL2B = 0x40 // PSC 2 Input Select for Part B + PFRC2B_PELEV2B = 0x20 // PSC 2 Edge Level Selector on Input Part B + PFRC2B_PFLTE2B = 0x10 // PSC 2 Filter Enable on Input Part B + PFRC2B_PRFM2B = 0xf // PSC 2 Retrigger and Fault Mode for Part B + + // PFRC2A: PSC 2 Input B Control + PFRC2A_PCAE2A = 0x80 // PSC 2 Capture Enable Input Part A + PFRC2A_PISEL2A = 0x40 // PSC 2 Input Select for Part A + PFRC2A_PELEV2A = 0x20 // PSC 2 Edge Level Selector on Input Part A + PFRC2A_PFLTE2A = 0x10 // PSC 2 Filter Enable on Input Part A + PFRC2A_PRFM2A = 0xf // PSC 2 Retrigger and Fault Mode for Part A + + // PCTL2: PSC 2 Control Register + PCTL2_PPRE2 = 0xc0 // PSC 2 Prescaler Selects + PCTL2_PBFM2 = 0x20 // Balance Flank Width Modulation + PCTL2_PAOC2B = 0x10 // PSC 2 Asynchronous Output Control B + PCTL2_PAOC2A = 0x8 // PSC 2 Asynchronous Output Control A + PCTL2_PARUN2 = 0x4 // PSC2 Auto Run + PCTL2_PCCYC2 = 0x2 // PSC2 Complete Cycle + PCTL2_PRUN2 = 0x1 // PSC 2 Run + + // PCNF2: PSC 2 Configuration Register + PCNF2_PFIFTY2 = 0x80 // PSC 2 Fifty + PCNF2_PALOCK2 = 0x40 // PSC 2 Autolock + PCNF2_PLOCK2 = 0x20 // PSC 2 Lock + PCNF2_PMODE2 = 0x18 // PSC 2 Mode + PCNF2_POP2 = 0x4 // PSC 2 Output Polarity + PCNF2_PCLKSEL2 = 0x2 // PSC 2 Input Clock Select + PCNF2_POME2 = 0x1 // PSC 2 Output Matrix Enable + + // PCNFE2: PSC 2 Enhanced Configuration Register + PCNFE2_PASDLK2 = 0xe0 + PCNFE2_PBFM21 = 0x10 + PCNFE2_PELEV2A1 = 0x8 + PCNFE2_PELEV2B1 = 0x4 + PCNFE2_PISEL2A1 = 0x2 + PCNFE2_PISEL2B1 = 0x1 + + // POM2: PSC 2 Output Matrix + POM2_POMV2B = 0xf0 // Output Matrix Output B Ramps + POM2_POMV2A = 0xf // Output Matrix Output A Ramps + + // PSOC2: PSC2 Synchro and Output Configuration + PSOC2_POS2 = 0xc0 // PSC 2 Output 23 Select + PSOC2_PSYNC2 = 0x30 // Synchronization Out for ADC Selection + PSOC2_POEN2D = 0x8 // PSCOUT23 Output Enable + PSOC2_POEN2B = 0x4 // PSCOUT21 Output Enable + PSOC2_POEN2C = 0x2 // PSCOUT22 Output Enable + PSOC2_POEN2A = 0x1 // PSCOUT20 Output Enable + + // PIM2: PSC2 Interrupt Mask Register + PIM2_PSEIE2 = 0x20 // PSC 2 Synchro Error Interrupt Enable + PIM2_PEVE2B = 0x10 // External Event B Interrupt Enable + PIM2_PEVE2A = 0x8 // External Event A Interrupt Enable + PIM2_PEOEPE2 = 0x2 // End of Enhanced Cycle Interrupt Enable + PIM2_PEOPE2 = 0x1 // End of Cycle Interrupt Enable + + // PIFR2: PSC2 Interrupt Flag Register + PIFR2_POAC2B = 0x80 // PSC 2 Output A Activity + PIFR2_POAC2A = 0x40 // PSC 2 Output A Activity + PIFR2_PSEI2 = 0x20 // PSC 2 Synchro Error Interrupt + PIFR2_PEV2B = 0x10 // External Event B Interrupt + PIFR2_PEV2A = 0x8 // External Event A Interrupt + PIFR2_PRN2 = 0x6 // Ramp Number + PIFR2_PEOP2 = 0x1 // End of PSC2 Interrupt +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TIMSK1: Timer/Counter Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM13 = 0x10 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) diff --git a/src/device/avr/at90pwm161.ld b/src/device/avr/at90pwm161.ld new file mode 100644 index 00000000..0d902e74 --- /dev/null +++ b/src/device/avr/at90pwm161.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from AT90PWM161.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_size = 0x400; +__num_isrs = 20; diff --git a/src/device/avr/at90pwm216.go b/src/device/avr/at90pwm216.go new file mode 100644 index 00000000..e1b38905 --- /dev/null +++ b/src/device/avr/at90pwm216.go @@ -0,0 +1,934 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from AT90PWM216.atdf, see http://packs.download.atmel.com/ + +// +build avr,at90pwm216 + +// Device information for the AT90PWM216. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "AT90PWM216" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset + IRQ_PSC2_CAPT = 1 // PSC2 Capture Event + IRQ_PSC2_EC = 2 // PSC2 End Cycle + IRQ_PSC1_CAPT = 3 // PSC1 Capture Event + IRQ_PSC1_EC = 4 // PSC1 End Cycle + IRQ_PSC0_CAPT = 5 // PSC0 Capture Event + IRQ_PSC0_EC = 6 // PSC0 End Cycle + IRQ_ANALOG_COMP_0 = 7 // Analog Comparator 0 + IRQ_ANALOG_COMP_1 = 8 // Analog Comparator 1 + IRQ_ANALOG_COMP_2 = 9 // Analog Comparator 2 + IRQ_INT0 = 10 // External Interrupt Request 0 + IRQ_TIMER1_CAPT = 11 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 12 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 13 // Timer/Counter Compare Match B + IRQ_RESERVED15 = 14 // + IRQ_TIMER1_OVF = 15 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP_A = 16 // Timer/Counter0 Compare Match A + IRQ_TIMER0_OVF = 17 // Timer/Counter0 Overflow + IRQ_ADC = 18 // ADC Conversion Complete + IRQ_INT1 = 19 // External Interrupt Request 1 + IRQ_SPI_STC = 20 // SPI Serial Transfer Complete + IRQ_USART_RX = 21 // USART, Rx Complete + IRQ_USART_UDRE = 22 // USART Data Register Empty + IRQ_USART_TX = 23 // USART, Tx Complete + IRQ_INT2 = 24 // External Interrupt Request 2 + IRQ_WDT = 25 // Watchdog Timeout Interrupt + IRQ_EE_READY = 26 // EEPROM Ready + IRQ_TIMER0_COMPB = 27 // Timer Counter 0 Compare Match B + IRQ_INT3 = 28 // External Interrupt Request 3 + IRQ_RESERVED30 = 29 // + IRQ_RESERVED31 = 30 // + IRQ_SPM_READY = 31 // Store Program Memory Read + IRQ_max = 31 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // I/O Port + PORT = struct { + PORTB __reg + DDRB __reg + PINB __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + }{ + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Port E Data Register + DDRE: 0x2d, // Port E Data Direction Register + PINE: 0x2c, // Port E Input Pins + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // Extended USART + EUSART = struct { + EUDR __reg + EUCSRA __reg + EUCSRB __reg + EUCSRC __reg + MUBRRH __reg + MUBRRL __reg + }{ + EUDR: 0xce, // EUSART I/O Data Register + EUCSRA: 0xc8, // EUSART Control and Status Register A + EUCSRB: 0xc9, // EUSART Control Register B + EUCSRC: 0xca, // EUSART Status Register C + MUBRRH: 0xcd, // Manchester Receiver Baud Rate Register High Byte + MUBRRL: 0xcc, // Manchester Receiver Baud Rate Register Low Byte + } + + // Analog Comparator + AC = struct { + AC0CON __reg + AC1CON __reg + AC2CON __reg + ACSR __reg + }{ + AC0CON: 0xad, // Analog Comparator 0 Control Register + AC1CON: 0xae, // Analog Comparator 1 Control Register + AC2CON: 0xaf, // Analog Comparator 2 Control Register + ACSR: 0x50, // Analog Comparator Status Register + } + + // Digital-to-Analog Converter + DAC = struct { + DACL __reg + DACH __reg + DACON __reg + }{ + DACL: 0xab, // DAC Data Register Bytes + DACH: 0xab, // DAC Data Register Bytes + DACON: 0xaa, // DAC Control Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + MCUCR __reg + MCUSR __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + GPIOR3 __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PLLCSR __reg + PRR __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, + SMCR: 0x53, // Sleep Mode Control Register + GPIOR3: 0x3b, // General Purpose IO Register 3 + GPIOR2: 0x3a, // General Purpose IO Register 2 + GPIOR1: 0x39, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PLLCSR: 0x49, // PLL Control And Status Register + PRR: 0x64, // Power Reduction Register + } + + // Timer/Counter, 8-bit + TC8 = struct { + TIMSK0 __reg + TIFR0 __reg + TCCR0A __reg + TCCR0B __reg + TCNT0 __reg + OCR0A __reg + OCR0B __reg + }{ + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + TCCR0A: 0x44, // Timer/Counter Control Register A + TCCR0B: 0x45, // Timer/Counter Control Register B + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + ADCSRB __reg + DIDR0 __reg + DIDR1 __reg + AMP0CSR __reg + AMP1CSR __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRB: 0x7b, // ADC Control and Status Register B + DIDR0: 0x7e, // Digital Input Disable Register 0 + DIDR1: 0x7f, // Digital Input Disable Register 1 + AMP0CSR: 0x76, + AMP1CSR: 0x77, + } + + // USART + USART = struct { + UDR __reg + UCSRA __reg + UCSRB __reg + UCSRC __reg + UBRRH __reg + UBRRL __reg + }{ + UDR: 0xc6, // USART I/O Data Register + UCSRA: 0xc0, // USART Control and Status register A + UCSRB: 0xc1, // USART Control an Status register B + UCSRC: 0xc2, // USART Control an Status register C + UBRRH: 0xc5, // USART Baud Rate Register High Byte + UBRRL: 0xc4, // USART Baud Rate Register Low Byte + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access Bytes + EEARH: 0x41, // EEPROM Read/Write Access Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Power Stage Controller + PSC = struct { + PICR0L __reg + PICR0H __reg + PFRC0B __reg + PFRC0A __reg + PCTL0 __reg + PCNF0 __reg + OCR0RBL __reg + OCR0RBH __reg + OCR0SBL __reg + OCR0SBH __reg + OCR0RAL __reg + OCR0RAH __reg + OCR0SAL __reg + OCR0SAH __reg + PSOC0 __reg + PIM0 __reg + PIFR0 __reg + PICR2L __reg + PICR2H __reg + PFRC2B __reg + PFRC2A __reg + PCTL2 __reg + PCNF2 __reg + OCR2RBL __reg + OCR2RBH __reg + OCR2SBL __reg + OCR2SBH __reg + OCR2RAL __reg + OCR2RAH __reg + OCR2SAL __reg + OCR2SAH __reg + POM2 __reg + PSOC2 __reg + PIM2 __reg + PIFR2 __reg + }{ + PICR0L: 0xde, // PSC 0 Input Capture Register + PICR0H: 0xde, // PSC 0 Input Capture Register + PFRC0B: 0xdd, // PSC 0 Input B Control + PFRC0A: 0xdc, // PSC 0 Input A Control + PCTL0: 0xdb, // PSC 0 Control Register + PCNF0: 0xda, // PSC 0 Configuration Register + OCR0RBL: 0xd8, // Output Compare RB Register + OCR0RBH: 0xd8, // Output Compare RB Register + OCR0SBL: 0xd6, // Output Compare SB Register + OCR0SBH: 0xd6, // Output Compare SB Register + OCR0RAL: 0xd4, // Output Compare RA Register + OCR0RAH: 0xd4, // Output Compare RA Register + OCR0SAL: 0xd2, // Output Compare SA Register + OCR0SAH: 0xd2, // Output Compare SA Register + PSOC0: 0xd0, // PSC0 Synchro and Output Configuration + PIM0: 0xa1, // PSC0 Interrupt Mask Register + PIFR0: 0xa0, // PSC0 Interrupt Flag Register + PICR2L: 0xfe, // PSC 2 Input Capture Register + PICR2H: 0xfe, // PSC 2 Input Capture Register + PFRC2B: 0xfd, // PSC 2 Input B Control + PFRC2A: 0xfc, // PSC 2 Input B Control + PCTL2: 0xfb, // PSC 2 Control Register + PCNF2: 0xfa, // PSC 2 Configuration Register + OCR2RBL: 0xf8, // Output Compare RB Register + OCR2RBH: 0xf8, // Output Compare RB Register + OCR2SBL: 0xf6, // Output Compare SB Register + OCR2SBH: 0xf6, // Output Compare SB Register + OCR2RAL: 0xf4, // Output Compare RA Register + OCR2RAH: 0xf4, // Output Compare RA Register + OCR2SAL: 0xf2, // Output Compare SA Register + OCR2SAH: 0xf2, // Output Compare SA Register + POM2: 0xf1, // PSC 2 Output Matrix + PSOC2: 0xf0, // PSC2 Synchro and Output Configuration + PIM2: 0xa5, // PSC2 Interrupt Mask Register + PIFR2: 0xa4, // PSC2 Interrupt Flag Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_PSC2RB = 0x80 // PSC2 Reset Behavior + EXTENDED_PSC1RB = 0x40 // PSC1 Reset Behavior + EXTENDED_PSC0RB = 0x20 // PSC0 Reset Behavior + EXTENDED_PSCRV = 0x10 // PSCOUT Reset Value + EXTENDED_BOOTSZ = 0x6 // Select Boot Size + EXTENDED_BOOTRST = 0x1 // Select Reset Vector + + // HIGH + HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PC6 as i/o pin) + HIGH_DWEN = 0x40 // Debug Wire enable + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watch-dog Timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BODLEVEL = 0x7 // Brown-out Detector Trigger Level + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTB0 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for EUSART: Extended USART +const ( + // EUCSRA: EUSART Control and Status Register A + EUCSRA_UTxS = 0xf0 // EUSART Control and Status Register A Bits + EUCSRA_URxS = 0xf // EUSART Control and Status Register A Bits + + // EUCSRB: EUSART Control Register B + EUCSRB_EUSART = 0x10 // EUSART Enable Bit + EUCSRB_EUSBS = 0x8 // EUSBS Enable Bit + EUCSRB_EMCH = 0x2 // Manchester Mode Bit + EUCSRB_BODR = 0x1 // Order Bit + + // EUCSRC: EUSART Status Register C + EUCSRC_FEM = 0x8 // Frame Error Manchester Bit + EUCSRC_F1617 = 0x4 // F1617 Bit + EUCSRC_STP = 0x3 // Stop Bits + + // MUBRRH: Manchester Receiver Baud Rate Register High Byte + MUBRRH_MUBRR = 0xff // Manchester Receiver Baud Rate Register Bits + + // MUBRRL: Manchester Receiver Baud Rate Register Low Byte + MUBRRL_MUBRR = 0xff // Manchester Receiver Baud Rate Register Bits +) + +// Bitfields for AC: Analog Comparator +const ( + // AC0CON: Analog Comparator 0 Control Register + AC0CON_AC0EN = 0x80 // Analog Comparator 0 Enable Bit + AC0CON_AC0IE = 0x40 // Analog Comparator 0 Interrupt Enable Bit + AC0CON_AC0IS = 0x30 // Analog Comparator 0 Interrupt Select Bit + AC0CON_AC0M = 0x7 // Analog Comparator 0 Multiplexer Register + + // AC1CON: Analog Comparator 1 Control Register + AC1CON_AC1EN = 0x80 // Analog Comparator 1 Enable Bit + AC1CON_AC1IE = 0x40 // Analog Comparator 1 Interrupt Enable Bit + AC1CON_AC1IS = 0x30 // Analog Comparator 1 Interrupt Select Bit + AC1CON_AC1ICE = 0x8 // Analog Comparator 1 Interrupt Capture Enable Bit + AC1CON_AC1M = 0x7 // Analog Comparator 1 Multiplexer Register + + // AC2CON: Analog Comparator 2 Control Register + AC2CON_AC2EN = 0x80 // Analog Comparator 2 Enable Bit + AC2CON_AC2IE = 0x40 // Analog Comparator 2 Interrupt Enable Bit + AC2CON_AC2IS = 0x30 // Analog Comparator 2 Interrupt Select Bit + AC2CON_AC2M = 0x7 // Analog Comparator 2 Multiplexer Register + + // ACSR: Analog Comparator Status Register + ACSR_ACCKDIV = 0x80 // Analog Comparator Clock Divider + ACSR_AC2IF = 0x40 // Analog Comparator 2 Interrupt Flag Bit + ACSR_AC1IF = 0x20 // Analog Comparator 1 Interrupt Flag Bit + ACSR_AC0IF = 0x10 // Analog Comparator 0 Interrupt Flag Bit + ACSR_AC2O = 0x4 // Analog Comparator 2 Output Bit + ACSR_AC1O = 0x2 // Analog Comparator 1 Output Bit + ACSR_AC0O = 0x1 // Analog Comparator 0 Output Bit +) + +// Bitfields for DAC: Digital-to-Analog Converter +const ( + // DACL: DAC Data Register Bytes + + // DACH: DAC Data Register Bytes + DAC_DAC = 0xffff // DAC Data Register Bits + + // DACON: DAC Control Register + DACON_DAATE = 0x80 // DAC Auto Trigger Enable Bit + DACON_DATS = 0x70 // DAC Trigger Selection Bits + DACON_DALA = 0x4 // DAC Left Adjust + DACON_DAOE = 0x2 // DAC Output Enable + DACON_DAEN = 0x1 // DAC Enable Bit +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // MCUCR: MCU Control Register + MCUCR_SPIPS = 0x80 // SPI Pin Select + MCUCR_PUD = 0x10 // Pull-up disable + MCUCR_IVSEL = 0x2 // Interrupt Vector Select + MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable + + // MCUSR: MCU Status Register + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BORF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR3: General Purpose IO Register 3 + GPIOR3_GPIOR = 0xff // General Purpose IO Register 3 bis + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 + + // PLLCSR: PLL Control And Status Register + PLLCSR_PLLF = 0x4 // PLL Factor + PLLCSR_PLLE = 0x2 // PLL Enable + PLLCSR_PLOCK = 0x1 // PLL Lock Detector + + // PRR: Power Reduction Register + PRR_PRPSC2 = 0x80 // Power Reduction PSC2 + PRR_PRPSC1 = 0x40 // Power Reduction PSC1 + PRR_PRPSC0 = 0x20 // Power Reduction PSC0 + PRR_PRTIM1 = 0x10 // Power Reduction Timer/Counter1 + PRR_PRTIM0 = 0x8 // Power Reduction Timer/Counter0 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCNT0: Timer/Counter0 + TCNT0_TCNT0 = 0xff // Timer Counter 0 value + + // OCR0A: Timer/Counter0 Output Compare Register + OCR0A_OCR0A = 0xff // Output Compare A value + + // OCR0B: Timer/Counter0 Output Compare Register + OCR0B_OCR0B = 0xff // Output Compare B value +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TIMSK1: Timer/Counter Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output CompareB Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output CompareA Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 + TCCR1C_FOC1B = 0x40 + + // TCNT1L: Timer/Counter1 Bytes + + // TCNT1H: Timer/Counter1 Bytes + TCNT1_TCNT1 = 0xffff // Timer/Counter1 + + // OCR1AL: Timer/Counter1 Output Compare Register Bytes + + // OCR1AH: Timer/Counter1 Output Compare Register Bytes + OCR1A_OCR1A = 0xffff // Timer/Counter1 Output Compare A Register + + // OCR1BL: Timer/Counter1 Output Compare Register Bytes + + // OCR1BH: Timer/Counter1 Output Compare Register Bytes + OCR1B_OCR1B = 0xffff // Timer/Counter1 Output Compare B Register + + // ICR1L: Timer/Counter1 Input Capture Register Bytes + + // ICR1H: Timer/Counter1 Input Capture Register Bytes + ICR1_ICR1 = 0xffff // Timer/Counter Input Capture +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0xf // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCSRB: ADC Control and Status Register B + ADCSRB_ADHSM = 0x80 // ADC High Speed Mode + ADCSRB_ADTS3 = 0x8 // ADC Auto Trigger Source Selection 3 + ADCSRB_ADTS2 = 0x4 // ADC Auto Trigger Source Selection 2 + ADCSRB_ADTS1 = 0x2 // ADC Auto Trigger Source Selection 1 + ADCSRB_ADTS0 = 0x1 // ADC Auto Trigger Source Selection 0 + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 + DIDR0_ADC6D = 0x40 + DIDR0_ADC5D = 0x20 + DIDR0_ADC4D = 0x10 + DIDR0_ADC3D = 0x8 + DIDR0_ADC2D = 0x4 + DIDR0_ADC1D = 0x2 + DIDR0_ADC0D = 0x1 + + // DIDR1: Digital Input Disable Register 1 + DIDR1_ACMP0D = 0x20 + DIDR1_AMP0PD = 0x10 + DIDR1_AMP0ND = 0x8 + DIDR1_ADC10D = 0x4 + DIDR1_ADC9D = 0x2 + DIDR1_ADC8D = 0x1 + + // AMP0CSR + AMP0CSR_AMP0EN = 0x80 + AMP0CSR_AMP0IS = 0x40 + AMP0CSR_AMP0G = 0x30 + AMP0CSR_AMP0TS = 0x3 + + // AMP1CSR + AMP1CSR_AMP1EN = 0x80 + AMP1CSR_AMP1IS = 0x40 + AMP1CSR_AMP1G = 0x30 + AMP1CSR_AMP1TS = 0x3 +) + +// Bitfields for USART: USART +const ( + // UCSRA: USART Control and Status register A + UCSRA_RXC = 0x80 // USART Receive Complete + UCSRA_TXC = 0x40 // USART Transmitt Complete + UCSRA_UDRE = 0x20 // USART Data Register Empty + UCSRA_FE = 0x10 // Framing Error + UCSRA_DOR = 0x8 // Data Overrun + UCSRA_UPE = 0x4 // USART Parity Error + UCSRA_U2X = 0x2 // Double USART Transmission Bit + UCSRA_MPCM = 0x1 // Multi-processor Communication Mode + + // UCSRB: USART Control an Status register B + UCSRB_RXCIE = 0x80 // RX Complete Interrupt Enable + UCSRB_TXCIE = 0x40 // TX Complete Interrupt Enable + UCSRB_UDRIE = 0x20 // USART Data Register Empty Interrupt Enable + UCSRB_RXEN = 0x10 // Receiver Enable + UCSRB_TXEN = 0x8 // Transmitter Enable + UCSRB_UCSZ2 = 0x4 // Character Size + UCSRB_RXB8 = 0x2 // Receive Data Bit 8 + UCSRB_TXB8 = 0x1 // Transmit Data Bit 8 + + // UCSRC: USART Control an Status register C + UCSRC_UMSEL0 = 0x40 // USART Mode Select + UCSRC_UPM = 0x30 // Parity Mode Bits + UCSRC_USBS = 0x8 // Stop Bit Select + UCSRC_UCSZ = 0x6 // Character Size Bits + UCSRC_UCPOL = 0x1 // Clock Polarity + + // UBRRH: USART Baud Rate Register High Byte + UBRRH_UBRR = 0xf // USART Baud Rate Register Bits + + // UBRRL: USART Baud Rate Register Low Byte + UBRRL_UBRR = 0xff // USART Baud Rate Register bits +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPDR: SPI Data Register + SPDR_SPD = 0xff // SPI Data +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xf // External Interrupt Mask + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xf // External Interrupt Flags +) + +// Bitfields for EEPROM: EEPROM +const ( + // EEARL: EEPROM Read/Write Access Bytes + + // EEARH: EEPROM Read/Write Access Bytes + EEAR_EEAR = 0xfff // EEPROM Address bytes + + // EEDR: EEPROM Data Register + EEDR_EEDR = 0xff // EEPROM Data Bits + + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for PSC: Power Stage Controller +const ( + // PICR0L: PSC 0 Input Capture Register + + // PICR0H: PSC 0 Input Capture Register + PICR0_PCST0 = 0x8000 // PSC 0 Input Capture Software Trig + PICR0_PICR0 = 0xfff // PSC 0 Input Capture Bytes + + // PFRC0B: PSC 0 Input B Control + PFRC0B_PCAE0B = 0x80 // PSC 0 Capture Enable Input Part B + PFRC0B_PISEL0B = 0x40 // PSC 0 Input Select for Part B + PFRC0B_PELEV0B = 0x20 // PSC 0 Edge Level Selector on Input Part B + PFRC0B_PFLTE0B = 0x10 // PSC 0 Filter Enable on Input Part B + PFRC0B_PRFM0B = 0xf // PSC 0 Retrigger and Fault Mode for Part B + + // PFRC0A: PSC 0 Input A Control + PFRC0A_PCAE0A = 0x80 // PSC 0 Capture Enable Input Part A + PFRC0A_PISEL0A = 0x40 // PSC 0 Input Select for Part A + PFRC0A_PELEV0A = 0x20 // PSC 0 Edge Level Selector on Input Part A + PFRC0A_PFLTE0A = 0x10 // PSC 0 Filter Enable on Input Part A + PFRC0A_PRFM0A = 0xf // PSC 0 Retrigger and Fault Mode for Part A + + // PCTL0: PSC 0 Control Register + PCTL0_PPRE0 = 0xc0 // PSC 0 Prescaler Selects + PCTL0_PBFM0 = 0x20 // PSC 0 Balance Flank Width Modulation + PCTL0_PAOC0B = 0x10 // PSC 0 Asynchronous Output Control B + PCTL0_PAOC0A = 0x8 // PSC 0 Asynchronous Output Control A + PCTL0_PARUN0 = 0x4 // PSC0 Auto Run + PCTL0_PCCYC0 = 0x2 // PSC0 Complete Cycle + PCTL0_PRUN0 = 0x1 // PSC 0 Run + + // PCNF0: PSC 0 Configuration Register + PCNF0_PFIFTY0 = 0x80 // PSC 0 Fifty + PCNF0_PALOCK0 = 0x40 // PSC 0 Autolock + PCNF0_PLOCK0 = 0x20 // PSC 0 Lock + PCNF0_PMODE0 = 0x18 // PSC 0 Mode + PCNF0_POP0 = 0x4 // PSC 0 Output Polarity + PCNF0_PCLKSEL0 = 0x2 // PSC 0 Input Clock Select + + // PSOC0: PSC0 Synchro and Output Configuration + PSOC0_PSYNC0 = 0x30 // Synchronization Out for ADC Selection + PSOC0_POEN0B = 0x4 // PSCOUT01 Output Enable + PSOC0_POEN0A = 0x1 // PSCOUT00 Output Enable + + // PIM0: PSC0 Interrupt Mask Register + PIM0_PSEIE0 = 0x20 // PSC 0 Synchro Error Interrupt Enable + PIM0_PEVE0B = 0x10 // External Event B Interrupt Enable + PIM0_PEVE0A = 0x8 // External Event A Interrupt Enable + PIM0_PEOPE0 = 0x1 // End of Cycle Interrupt Enable + + // PIFR0: PSC0 Interrupt Flag Register + PIFR0_POAC0B = 0x80 // PSC 0 Output A Activity + PIFR0_POAC0A = 0x40 // PSC 0 Output A Activity + PIFR0_PSEI0 = 0x20 // PSC 0 Synchro Error Interrupt + PIFR0_PEV0B = 0x10 // External Event B Interrupt + PIFR0_PEV0A = 0x8 // External Event A Interrupt + PIFR0_PRN0 = 0x6 // Ramp Number + PIFR0_PEOP0 = 0x1 // End of PSC0 Interrupt + + // PICR2L: PSC 2 Input Capture Register + + // PICR2H: PSC 2 Input Capture Register + PICR2_PCST2 = 0x8000 // PSC 2 Input Capture Software Trig + PICR2_PICR2 = 0xfff // PSC 2 Input Capture Bytes + + // PFRC2B: PSC 2 Input B Control + PFRC2B_PCAE2B = 0x80 // PSC 2 Capture Enable Input Part B + PFRC2B_PISEL2B = 0x40 // PSC 2 Input Select for Part B + PFRC2B_PELEV2B = 0x20 // PSC 2 Edge Level Selector on Input Part B + PFRC2B_PFLTE2B = 0x10 // PSC 2 Filter Enable on Input Part B + PFRC2B_PRFM2B = 0xf // PSC 2 Retrigger and Fault Mode for Part B + + // PFRC2A: PSC 2 Input B Control + PFRC2A_PCAE2A = 0x80 // PSC 2 Capture Enable Input Part A + PFRC2A_PISEL2A = 0x40 // PSC 2 Input Select for Part A + PFRC2A_PELEV2A = 0x20 // PSC 2 Edge Level Selector on Input Part A + PFRC2A_PFLTE2A = 0x10 // PSC 2 Filter Enable on Input Part A + PFRC2A_PRFM2A = 0xf // PSC 2 Retrigger and Fault Mode for Part A + + // PCTL2: PSC 2 Control Register + PCTL2_PPRE2 = 0xc0 // PSC 2 Prescaler Selects + PCTL2_PBFM2 = 0x20 // Balance Flank Width Modulation + PCTL2_PAOC2B = 0x10 // PSC 2 Asynchronous Output Control B + PCTL2_PAOC2A = 0x8 // PSC 2 Asynchronous Output Control A + PCTL2_PARUN2 = 0x4 // PSC2 Auto Run + PCTL2_PCCYC2 = 0x2 // PSC2 Complete Cycle + PCTL2_PRUN2 = 0x1 // PSC 2 Run + + // PCNF2: PSC 2 Configuration Register + PCNF2_PFIFTY2 = 0x80 // PSC 2 Fifty + PCNF2_PALOCK2 = 0x40 // PSC 2 Autolock + PCNF2_PLOCK2 = 0x20 // PSC 2 Lock + PCNF2_PMODE2 = 0x18 // PSC 2 Mode + PCNF2_POP2 = 0x4 // PSC 2 Output Polarity + PCNF2_PCLKSEL2 = 0x2 // PSC 2 Input Clock Select + PCNF2_POME2 = 0x1 // PSC 2 Output Matrix Enable + + // POM2: PSC 2 Output Matrix + POM2_POMV2B = 0xf0 // Output Matrix Output B Ramps + POM2_POMV2A = 0xf // Output Matrix Output A Ramps + + // PSOC2: PSC2 Synchro and Output Configuration + PSOC2_POS2 = 0xc0 // PSC 2 Output 23 Select + PSOC2_PSYNC2 = 0x30 // Synchronization Out for ADC Selection + PSOC2_POEN2D = 0x8 // PSCOUT23 Output Enable + PSOC2_POEN2B = 0x4 // PSCOUT21 Output Enable + PSOC2_POEN2C = 0x2 // PSCOUT22 Output Enable + PSOC2_POEN2A = 0x1 // PSCOUT20 Output Enable + + // PIM2: PSC2 Interrupt Mask Register + PIM2_PSEIE2 = 0x20 // PSC 2 Synchro Error Interrupt Enable + PIM2_PEVE2B = 0x10 // External Event B Interrupt Enable + PIM2_PEVE2A = 0x8 // External Event A Interrupt Enable + PIM2_PEOPE2 = 0x1 // End of Cycle Interrupt Enable + + // PIFR2: PSC2 Interrupt Flag Register + PIFR2_POAC2B = 0x80 // PSC 2 Output A Activity + PIFR2_POAC2A = 0x40 // PSC 2 Output A Activity + PIFR2_PSEI2 = 0x20 // PSC 2 Synchro Error Interrupt + PIFR2_PEV2B = 0x10 // External Event B Interrupt + PIFR2_PEV2A = 0x8 // External Event A Interrupt + PIFR2_PRN2 = 0x6 // Ramp Number + PIFR2_PEOP2 = 0x1 // End of PSC2 Interrupt +) diff --git a/src/device/avr/at90pwm216.ld b/src/device/avr/at90pwm216.ld new file mode 100644 index 00000000..5db0c09d --- /dev/null +++ b/src/device/avr/at90pwm216.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from AT90PWM216.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_size = 0x400; +__num_isrs = 32; diff --git a/src/device/avr/at90pwm2b.go b/src/device/avr/at90pwm2b.go new file mode 100644 index 00000000..21e2cf6a --- /dev/null +++ b/src/device/avr/at90pwm2b.go @@ -0,0 +1,970 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from AT90PWM2B.atdf, see http://packs.download.atmel.com/ + +// +build avr,at90pwm2b + +// Device information for the AT90PWM2B. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "AT90PWM2B" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset + IRQ_PSC2_CAPT = 1 // PSC2 Capture Event + IRQ_PSC2_EC = 2 // PSC2 End Cycle + IRQ_PSC1_CAPT = 3 // PSC1 Capture Event + IRQ_PSC1_EC = 4 // PSC1 End Cycle + IRQ_PSC0_CAPT = 5 // PSC0 Capture Event + IRQ_PSC0_EC = 6 // PSC0 End Cycle + IRQ_ANALOG_COMP_0 = 7 // Analog Comparator 0 + IRQ_ANALOG_COMP_1 = 8 // Analog Comparator 1 + IRQ_ANALOG_COMP_2 = 9 // Analog Comparator 2 + IRQ_INT0 = 10 // External Interrupt Request 0 + IRQ_TIMER1_CAPT = 11 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 12 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 13 // Timer/Counter Compare Match B + IRQ_RESERVED15 = 14 // + IRQ_TIMER1_OVF = 15 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 16 // Timer/Counter0 Compare Match A + IRQ_TIMER0_OVF = 17 // Timer/Counter0 Overflow + IRQ_ADC = 18 // ADC Conversion Complete + IRQ_INT1 = 19 // External Interrupt Request 1 + IRQ_SPI_STC = 20 // SPI Serial Transfer Complete + IRQ_USART_RX = 21 // USART, Rx Complete + IRQ_USART_UDRE = 22 // USART Data Register Empty + IRQ_USART_TX = 23 // USART, Tx Complete + IRQ_INT2 = 24 // External Interrupt Request 2 + IRQ_WDT = 25 // Watchdog Timeout Interrupt + IRQ_EE_READY = 26 // EEPROM Ready + IRQ_TIMER0_COMPB = 27 // Timer Counter 0 Compare Match B + IRQ_INT3 = 28 // External Interrupt Request 3 + IRQ_RESERVED30 = 29 // + IRQ_RESERVED31 = 30 // + IRQ_SPM_READY = 31 // Store Program Memory Read + IRQ_max = 31 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // I/O Port + PORT = struct { + PORTB __reg + DDRB __reg + PINB __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + }{ + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Port E Data Register + DDRE: 0x2d, // Port E Data Direction Register + PINE: 0x2c, // Port E Input Pins + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // Extended USART + EUSART = struct { + EUDR __reg + EUCSRA __reg + EUCSRB __reg + EUCSRC __reg + MUBRRL __reg + MUBRRH __reg + }{ + EUDR: 0xce, // EUSART I/O Data Register + EUCSRA: 0xc8, // EUSART Control and Status Register A + EUCSRB: 0xc9, // EUSART Control Register B + EUCSRC: 0xca, // EUSART Status Register C + MUBRRL: 0xcc, // Manchester Receiver Baud Rate Register + MUBRRH: 0xcc, // Manchester Receiver Baud Rate Register + } + + // Analog Comparator + AC = struct { + AC0CON __reg + AC1CON __reg + AC2CON __reg + ACSR __reg + }{ + AC0CON: 0xad, // Analog Comparator 0 Control Register + AC1CON: 0xae, // Analog Comparator 1 Control Register + AC2CON: 0xaf, // Analog Comparator 2 Control Register + ACSR: 0x50, // Analog Comparator Status Register + } + + // Digital-to-Analog Converter + DAC = struct { + DACL __reg + DACH __reg + DACON __reg + }{ + DACL: 0xab, // DAC Data Register + DACH: 0xab, // DAC Data Register + DACON: 0xaa, // DAC Control Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + MCUCR __reg + MCUSR __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + GPIOR3 __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PLLCSR __reg + PRR __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, + SMCR: 0x53, // Sleep Mode Control Register + GPIOR3: 0x3b, // General Purpose IO Register 3 + GPIOR2: 0x3a, // General Purpose IO Register 2 + GPIOR1: 0x39, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PLLCSR: 0x49, // PLL Control And Status Register + PRR: 0x64, // Power Reduction Register + } + + // Timer/Counter, 8-bit + TC8 = struct { + TIMSK0 __reg + TIFR0 __reg + TCCR0A __reg + TCCR0B __reg + TCNT0 __reg + OCR0A __reg + OCR0B __reg + }{ + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + TCCR0A: 0x44, // Timer/Counter Control Register A + TCCR0B: 0x45, // Timer/Counter Control Register B + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + ADCSRB __reg + DIDR0 __reg + DIDR1 __reg + AMP0CSR __reg + AMP1CSR __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRB: 0x7b, // ADC Control and Status Register B + DIDR0: 0x7e, // Digital Input Disable Register 0 + DIDR1: 0x7f, // Digital Input Disable Register 1 + AMP0CSR: 0x76, + AMP1CSR: 0x77, + } + + // USART + USART = struct { + UDR __reg + UCSRA __reg + UCSRB __reg + UCSRC __reg + UBRRL __reg + UBRRH __reg + }{ + UDR: 0xc6, // USART I/O Data Register + UCSRA: 0xc0, // USART Control and Status register A + UCSRB: 0xc1, // USART Control an Status register B + UCSRC: 0xc2, // USART Control an Status register C + UBRRL: 0xc4, // USART Baud Rate Register + UBRRH: 0xc4, // USART Baud Rate Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access Bytes + EEARH: 0x41, // EEPROM Read/Write Access Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Power Stage Controller + PSC = struct { + PICR0L __reg + PICR0H __reg + PFRC0B __reg + PFRC0A __reg + PCTL0 __reg + PCNF0 __reg + OCR0RBL __reg + OCR0RBH __reg + OCR0SBL __reg + OCR0SBH __reg + OCR0RAL __reg + OCR0RAH __reg + OCR0SAL __reg + OCR0SAH __reg + PSOC0 __reg + PIM0 __reg + PIFR0 __reg + PICR2L __reg + PICR2H __reg + PFRC2B __reg + PFRC2A __reg + PCTL2 __reg + PCNF2 __reg + OCR2RBL __reg + OCR2RBH __reg + OCR2SBL __reg + OCR2SBH __reg + OCR2RAL __reg + OCR2RAH __reg + OCR2SAL __reg + OCR2SAH __reg + POM2 __reg + PSOC2 __reg + PIM2 __reg + PIFR2 __reg + }{ + PICR0L: 0xde, // PSC 0 Input Capture Register + PICR0H: 0xde, // PSC 0 Input Capture Register + PFRC0B: 0xdd, // PSC 0 Input B Control + PFRC0A: 0xdc, // PSC 0 Input A Control + PCTL0: 0xdb, // PSC 0 Control Register + PCNF0: 0xda, // PSC 0 Configuration Register + OCR0RBL: 0xd8, // Output Compare 0 RB Register + OCR0RBH: 0xd8, // Output Compare 0 RB Register + OCR0SBL: 0xd6, // Output Compare 0 SB Register + OCR0SBH: 0xd6, // Output Compare 0 SB Register + OCR0RAL: 0xd4, // Output Compare 0 RA Register + OCR0RAH: 0xd4, // Output Compare 0 RA Register + OCR0SAL: 0xd2, // Output Compare 0 SA Register + OCR0SAH: 0xd2, // Output Compare 0 SA Register + PSOC0: 0xd0, // PSC0 Synchro and Output Configuration + PIM0: 0xa1, // PSC0 Interrupt Mask Register + PIFR0: 0xa0, // PSC0 Interrupt Flag Register + PICR2L: 0xfe, // PSC 2 Input Capture Register + PICR2H: 0xfe, // PSC 2 Input Capture Register + PFRC2B: 0xfd, // PSC 2 Input B Control + PFRC2A: 0xfc, // PSC 2 Input B Control + PCTL2: 0xfb, // PSC 2 Control Register + PCNF2: 0xfa, // PSC 2 Configuration Register + OCR2RBL: 0xf8, // Output Compare 2 RB Register + OCR2RBH: 0xf8, // Output Compare 2 RB Register + OCR2SBL: 0xf6, // Output Compare 2 SB Register + OCR2SBH: 0xf6, // Output Compare 2 SB Register + OCR2RAL: 0xf4, // Output Compare 2 RA Register + OCR2RAH: 0xf4, // Output Compare 2 RA Register + OCR2SAL: 0xf2, // Output Compare 2 SA Register + OCR2SAH: 0xf2, // Output Compare 2 SA Register + POM2: 0xf1, // PSC 2 Output Matrix + PSOC2: 0xf0, // PSC2 Synchro and Output Configuration + PIM2: 0xa5, // PSC2 Interrupt Mask Register + PIFR2: 0xa4, // PSC2 Interrupt Flag Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_PSC2RB = 0x80 // PSC2 Reset Behavior + EXTENDED_PSC1RB = 0x40 // PSC1 Reset Behavior + EXTENDED_PSC0RB = 0x20 // PSC0 Reset Behavior + EXTENDED_PSCRV = 0x10 // PSCOUT Reset Value + EXTENDED_BOOTSZ = 0x6 // Select Boot Size + EXTENDED_BOOTRST = 0x1 // Select Reset Vector + + // HIGH + HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PC6 as i/o pin) + HIGH_DWEN = 0x40 // Debug Wire enable + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watch-dog Timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BODLEVEL = 0x7 // Brown-out Detector Trigger Level + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTB0 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for EUSART: Extended USART +const ( + // EUDR: EUSART I/O Data Register + EUDR_EUDR = 0xff // EUSART Extended data bits + + // EUCSRA: EUSART Control and Status Register A + EUCSRA_UTxS = 0xf0 // EUSART Control and Status Register A Bits + EUCSRA_URxS = 0xf // EUSART Control and Status Register A Bits + + // EUCSRB: EUSART Control Register B + EUCSRB_EUSART = 0x10 // EUSART Enable Bit + EUCSRB_EUSBS = 0x8 // EUSBS Enable Bit + EUCSRB_EMCH = 0x2 // Manchester Mode Bit + EUCSRB_BODR = 0x1 // Order Bit + + // EUCSRC: EUSART Status Register C + EUCSRC_FEM = 0x8 // Frame Error Manchester Bit + EUCSRC_F1617 = 0x4 // F1617 Bit + EUCSRC_STP = 0x3 // Stop Bits + + // MUBRRL: Manchester Receiver Baud Rate Register + + // MUBRRH: Manchester Receiver Baud Rate Register + MUBRR_MUBRR = 0xffff // Manchester Receiver Baud Rate Register Bits +) + +// Bitfields for AC: Analog Comparator +const ( + // AC0CON: Analog Comparator 0 Control Register + AC0CON_AC0EN = 0x80 // Analog Comparator 0 Enable Bit + AC0CON_AC0IE = 0x40 // Analog Comparator 0 Interrupt Enable Bit + AC0CON_AC0IS = 0x30 // Analog Comparator 0 Interrupt Select Bit + AC0CON_AC0M = 0x7 // Analog Comparator 0 Multiplexer Register + + // AC1CON: Analog Comparator 1 Control Register + AC1CON_AC1EN = 0x80 // Analog Comparator 1 Enable Bit + AC1CON_AC1IE = 0x40 // Analog Comparator 1 Interrupt Enable Bit + AC1CON_AC1IS = 0x30 // Analog Comparator 1 Interrupt Select Bit + AC1CON_AC1ICE = 0x8 // Analog Comparator 1 Interrupt Capture Enable Bit + AC1CON_AC1M = 0x7 // Analog Comparator 1 Multiplexer Register + + // AC2CON: Analog Comparator 2 Control Register + AC2CON_AC2EN = 0x80 // Analog Comparator 2 Enable Bit + AC2CON_AC2IE = 0x40 // Analog Comparator 2 Interrupt Enable Bit + AC2CON_AC2IS = 0x30 // Analog Comparator 2 Interrupt Select Bit + AC2CON_AC2M = 0x7 // Analog Comparator 2 Multiplexer Register + + // ACSR: Analog Comparator Status Register + ACSR_ACCKDIV = 0x80 // Analog Comparator Clock Divider + ACSR_AC2IF = 0x40 // Analog Comparator 2 Interrupt Flag Bit + ACSR_AC1IF = 0x20 // Analog Comparator 1 Interrupt Flag Bit + ACSR_AC0IF = 0x10 // Analog Comparator 0 Interrupt Flag Bit + ACSR_AC2O = 0x4 // Analog Comparator 2 Output Bit + ACSR_AC1O = 0x2 // Analog Comparator 1 Output Bit + ACSR_AC0O = 0x1 // Analog Comparator 0 Output Bit +) + +// Bitfields for DAC: Digital-to-Analog Converter +const ( + // DACL: DAC Data Register + + // DACH: DAC Data Register + DAC_DAC = 0xffff // DAC Data Register Bits + + // DACON: DAC Control Register + DACON_DAATE = 0x80 // DAC Auto Trigger Enable Bit + DACON_DATS = 0x70 // DAC Trigger Selection Bits + DACON_DALA = 0x4 // DAC Left Adjust + DACON_DAOE = 0x2 // DAC Output Enable + DACON_DAEN = 0x1 // DAC Enable Bit +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // MCUCR: MCU Control Register + MCUCR_SPIPS = 0x80 // SPI Pin Select + MCUCR_PUD = 0x10 // Pull-up disable + MCUCR_IVSEL = 0x2 // Interrupt Vector Select + MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable + + // MCUSR: MCU Status Register + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BORF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR3: General Purpose IO Register 3 + GPIOR3_GPIOR = 0xff // General Purpose IO Register 3 bis + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 + + // PLLCSR: PLL Control And Status Register + PLLCSR_PLLF = 0x4 // PLL Factor + PLLCSR_PLLE = 0x2 // PLL Enable + PLLCSR_PLOCK = 0x1 // PLL Lock Detector + + // PRR: Power Reduction Register + PRR_PRPSC2 = 0x80 // Power Reduction PSC2 + PRR_PRPSC1 = 0x40 // Power Reduction PSC1 + PRR_PRPSC0 = 0x20 // Power Reduction PSC0 + PRR_PRTIM1 = 0x10 // Power Reduction Timer/Counter1 + PRR_PRTIM0 = 0x8 // Power Reduction Timer/Counter0 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCNT0: Timer/Counter0 + TCNT0_TCNT0 = 0xff // Timer Counter 0 value + + // OCR0A: Timer/Counter0 Output Compare Register + OCR0A_OCR0A = 0xff // Timer/Counter0 Output Compare A + + // OCR0B: Timer/Counter0 Output Compare Register + OCR0B_OCR0B = 0xff // Timer/Counter0 Output Compare B +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TIMSK1: Timer/Counter Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output CompareB Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output CompareA Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 + TCCR1C_FOC1B = 0x40 + + // TCNT1L: Timer/Counter1 Bytes + + // TCNT1H: Timer/Counter1 Bytes + TCNT1_TCNT1 = 0xffff // Timer/Counter1 + + // ICR1L: Timer/Counter1 Input Capture Register Bytes + + // ICR1H: Timer/Counter1 Input Capture Register Bytes + ICR1_ICR1 = 0xffff // Timer/Counter1 Input Capture +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0xf // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCL: ADC Data Register Bytes + + // ADCH: ADC Data Register Bytes + ADC_ADC = 0xffff // ADC Data Register + + // ADCSRB: ADC Control and Status Register B + ADCSRB_ADHSM = 0x80 // ADC High Speed Mode + ADCSRB_ADTS = 0xf // ADC Auto Trigger Source + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 + DIDR0_ADC6D = 0x40 + DIDR0_ADC5D = 0x20 + DIDR0_ADC4D = 0x10 + DIDR0_ADC3D = 0x8 + DIDR0_ADC2D = 0x4 + DIDR0_ADC1D = 0x2 + DIDR0_ADC0D = 0x1 + + // DIDR1: Digital Input Disable Register 1 + DIDR1_ACMP0D = 0x20 + DIDR1_AMP0PD = 0x10 + DIDR1_AMP0ND = 0x8 + DIDR1_ADC10D = 0x4 + DIDR1_ADC9D = 0x2 + DIDR1_ADC8D = 0x1 + + // AMP0CSR + AMP0CSR_AMP0EN = 0x80 + AMP0CSR_AMP0IS = 0x40 + AMP0CSR_AMP0G = 0x30 + AMP0CSR_AMP0TS = 0x3 + + // AMP1CSR + AMP1CSR_AMP1EN = 0x80 + AMP1CSR_AMP1IS = 0x40 + AMP1CSR_AMP1G = 0x30 + AMP1CSR_AMP1TS = 0x3 +) + +// Bitfields for USART: USART +const ( + // UDR: USART I/O Data Register + UDR_UDR = 0xff // USART I/O Data + + // UCSRA: USART Control and Status register A + UCSRA_RXC = 0x80 // USART Receive Complete + UCSRA_TXC = 0x40 // USART Transmitt Complete + UCSRA_UDRE = 0x20 // USART Data Register Empty + UCSRA_FE = 0x10 // Framing Error + UCSRA_DOR = 0x8 // Data Overrun + UCSRA_UPE = 0x4 // USART Parity Error + UCSRA_U2X = 0x2 // Double USART Transmission Bit + UCSRA_MPCM = 0x1 // Multi-processor Communication Mode + + // UCSRB: USART Control an Status register B + UCSRB_RXCIE = 0x80 // RX Complete Interrupt Enable + UCSRB_TXCIE = 0x40 // TX Complete Interrupt Enable + UCSRB_UDRIE = 0x20 // USART Data Register Empty Interrupt Enable + UCSRB_RXEN = 0x10 // Receiver Enable + UCSRB_TXEN = 0x8 // Transmitter Enable + UCSRB_UCSZ2 = 0x4 // Character Size + UCSRB_RXB8 = 0x2 // Receive Data Bit 8 + UCSRB_TXB8 = 0x1 // Transmit Data Bit 8 + + // UCSRC: USART Control an Status register C + UCSRC_UMSEL0 = 0x40 // USART Mode Select + UCSRC_UPM = 0x30 // Parity Mode Bits + UCSRC_USBS = 0x8 // Stop Bit Select + UCSRC_UCSZ = 0x6 // Character Size Bits + UCSRC_UCPOL = 0x1 // Clock Polarity + + // UBRRL: USART Baud Rate Register + + // UBRRH: USART Baud Rate Register + UBRR_UBRR = 0xfff // USART Baud Rate Register Bits +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPDR: SPI Data Register + SPDR_SPD = 0xff // SPI Data bits +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0x7 // External Interrupt Request Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0x7 // External Interrupt Flags +) + +// Bitfields for EEPROM: EEPROM +const ( + // EEARL: EEPROM Read/Write Access Bytes + + // EEARH: EEPROM Read/Write Access Bytes + EEAR_EEAR = 0xfff // EEPROM Address bytes + + // EEDR: EEPROM Data Register + EEDR_EEDR = 0xff // EEPROM Data Bits + + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for PSC: Power Stage Controller +const ( + // PICR0L: PSC 0 Input Capture Register + + // PICR0H: PSC 0 Input Capture Register + PICR0_PCST0 = 0x8000 // PSC 0 Input Capture Software Trig + PICR0_PICR0 = 0xfff // PSC 0 Input Capture Bytes + + // PFRC0B: PSC 0 Input B Control + PFRC0B_PCAE0B = 0x80 // PSC 0 Capture Enable Input Part B + PFRC0B_PISEL0B = 0x40 // PSC 0 Input Select for Part B + PFRC0B_PELEV0B = 0x20 // PSC 0 Edge Level Selector on Input Part B + PFRC0B_PFLTE0B = 0x10 // PSC 0 Filter Enable on Input Part B + PFRC0B_PRFM0B = 0xf // PSC 0 Retrigger and Fault Mode for Part B + + // PFRC0A: PSC 0 Input A Control + PFRC0A_PCAE0A = 0x80 // PSC 0 Capture Enable Input Part A + PFRC0A_PISEL0A = 0x40 // PSC 0 Input Select for Part A + PFRC0A_PELEV0A = 0x20 // PSC 0 Edge Level Selector on Input Part A + PFRC0A_PFLTE0A = 0x10 // PSC 0 Filter Enable on Input Part A + PFRC0A_PRFM0A = 0xf // PSC 0 Retrigger and Fault Mode for Part A + + // PCTL0: PSC 0 Control Register + PCTL0_PPRE0 = 0xc0 // PSC 0 Prescaler Selects + PCTL0_PBFM0 = 0x20 // PSC 0 Balance Flank Width Modulation + PCTL0_PAOC0B = 0x10 // PSC 0 Asynchronous Output Control B + PCTL0_PAOC0A = 0x8 // PSC 0 Asynchronous Output Control A + PCTL0_PARUN0 = 0x4 // PSC0 Auto Run + PCTL0_PCCYC0 = 0x2 // PSC0 Complete Cycle + PCTL0_PRUN0 = 0x1 // PSC 0 Run + + // PCNF0: PSC 0 Configuration Register + PCNF0_PFIFTY0 = 0x80 // PSC 0 Fifty + PCNF0_PALOCK0 = 0x40 // PSC 0 Autolock + PCNF0_PLOCK0 = 0x20 // PSC 0 Lock + PCNF0_PMODE0 = 0x18 // PSC 0 Mode + PCNF0_POP0 = 0x4 // PSC 0 Output Polarity + PCNF0_PCLKSEL0 = 0x2 // PSC 0 Input Clock Select + + // OCR0RBL: Output Compare 0 RB Register + + // OCR0RBH: Output Compare 0 RB Register + OCR0RB_OCR0RB = 0xffff // Output Compare RB + + // OCR0SBL: Output Compare 0 SB Register + + // OCR0SBH: Output Compare 0 SB Register + OCR0SB_OCR0SB = 0xfff // Output Compare SB + + // OCR0RAL: Output Compare 0 RA Register + + // OCR0RAH: Output Compare 0 RA Register + OCR0RA_OCR0RA = 0xfff // Output Compare RA + + // OCR0SAL: Output Compare 0 SA Register + + // OCR0SAH: Output Compare 0 SA Register + OCR0SA_OCR0SA = 0xfff // Output Compare SA + + // PSOC0: PSC0 Synchro and Output Configuration + PSOC0_PSYNC0 = 0x30 // Synchronization Out for ADC Selection + PSOC0_POEN0B = 0x4 // PSCOUT01 Output Enable + PSOC0_POEN0A = 0x1 // PSCOUT00 Output Enable + + // PIM0: PSC0 Interrupt Mask Register + PIM0_PSEIE0 = 0x20 // PSC 0 Synchro Error Interrupt Enable + PIM0_PEVE0B = 0x10 // External Event B Interrupt Enable + PIM0_PEVE0A = 0x8 // External Event A Interrupt Enable + PIM0_PEOPE0 = 0x1 // End of Cycle Interrupt Enable + + // PIFR0: PSC0 Interrupt Flag Register + PIFR0_POAC0B = 0x80 // PSC 0 Output A Activity + PIFR0_POAC0A = 0x40 // PSC 0 Output A Activity + PIFR0_PSEI0 = 0x20 // PSC 0 Synchro Error Interrupt + PIFR0_PEV0B = 0x10 // External Event B Interrupt + PIFR0_PEV0A = 0x8 // External Event A Interrupt + PIFR0_PRN0 = 0x6 // Ramp Number + PIFR0_PEOP0 = 0x1 // End of PSC0 Interrupt + + // PICR2L: PSC 2 Input Capture Register + + // PICR2H: PSC 2 Input Capture Register + PICR2_PCST2 = 0x8000 // PSC 2 Input Capture Software Trig + PICR2_PICR2 = 0xfff // PSC 2 Input Capture Bytes + + // PFRC2B: PSC 2 Input B Control + PFRC2B_PCAE2B = 0x80 // PSC 2 Capture Enable Input Part B + PFRC2B_PISEL2B = 0x40 // PSC 2 Input Select for Part B + PFRC2B_PELEV2B = 0x20 // PSC 2 Edge Level Selector on Input Part B + PFRC2B_PFLTE2B = 0x10 // PSC 2 Filter Enable on Input Part B + PFRC2B_PRFM2B = 0xf // PSC 2 Retrigger and Fault Mode for Part B + + // PFRC2A: PSC 2 Input B Control + PFRC2A_PCAE2A = 0x80 // PSC 2 Capture Enable Input Part A + PFRC2A_PISEL2A = 0x40 // PSC 2 Input Select for Part A + PFRC2A_PELEV2A = 0x20 // PSC 2 Edge Level Selector on Input Part A + PFRC2A_PFLTE2A = 0x10 // PSC 2 Filter Enable on Input Part A + PFRC2A_PRFM2A = 0xf // PSC 2 Retrigger and Fault Mode for Part A + + // PCTL2: PSC 2 Control Register + PCTL2_PPRE2 = 0xc0 // PSC 2 Prescaler Selects + PCTL2_PBFM2 = 0x20 // Balance Flank Width Modulation + PCTL2_PAOC2B = 0x10 // PSC 2 Asynchronous Output Control B + PCTL2_PAOC2A = 0x8 // PSC 2 Asynchronous Output Control A + PCTL2_PARUN2 = 0x4 // PSC2 Auto Run + PCTL2_PCCYC2 = 0x2 // PSC2 Complete Cycle + PCTL2_PRUN2 = 0x1 // PSC 2 Run + + // PCNF2: PSC 2 Configuration Register + PCNF2_PFIFTY2 = 0x80 // PSC 2 Fifty + PCNF2_PALOCK2 = 0x40 // PSC 2 Autolock + PCNF2_PLOCK2 = 0x20 // PSC 2 Lock + PCNF2_PMODE2 = 0x18 // PSC 2 Mode + PCNF2_POP2 = 0x4 // PSC 2 Output Polarity + PCNF2_PCLKSEL2 = 0x2 // PSC 2 Input Clock Select + PCNF2_POME2 = 0x1 // PSC 2 Output Matrix Enable + + // OCR2RBL: Output Compare 2 RB Register + + // OCR2RBH: Output Compare 2 RB Register + OCR2RB_OCR2RB = 0xffff // Output Compare RB + + // OCR2SBL: Output Compare 2 SB Register + + // OCR2SBH: Output Compare 2 SB Register + OCR2SB_OCR2SB = 0xfff // Output Compare SB + + // OCR2RAL: Output Compare 2 RA Register + + // OCR2RAH: Output Compare 2 RA Register + OCR2RA_OCR2RA = 0xfff // Output Compare RA + + // OCR2SAL: Output Compare 2 SA Register + + // OCR2SAH: Output Compare 2 SA Register + OCR2SA_OCR2SA = 0xfff // Output Compare SA + + // POM2: PSC 2 Output Matrix + POM2_POMV2B = 0xf0 // Output Matrix Output B Ramps + POM2_POMV2A = 0xf // Output Matrix Output A Ramps + + // PSOC2: PSC2 Synchro and Output Configuration + PSOC2_POS2 = 0xc0 // PSC 2 Output 23 Select + PSOC2_PSYNC2_ = 0x30 // Synchronization Out for ADC Selection + PSOC2_POEN2D = 0x8 // PSCOUT23 Output Enable + PSOC2_POEN2B = 0x4 // PSCOUT21 Output Enable + PSOC2_POEN2C = 0x2 // PSCOUT22 Output Enable + PSOC2_POEN2A = 0x1 // PSCOUT20 Output Enable + + // PIM2: PSC2 Interrupt Mask Register + PIM2_PSEIE2 = 0x20 // PSC 2 Synchro Error Interrupt Enable + PIM2_PEVE2B = 0x10 // External Event B Interrupt Enable + PIM2_PEVE2A = 0x8 // External Event A Interrupt Enable + PIM2_PEOPE2 = 0x1 // End of Cycle Interrupt Enable + + // PIFR2: PSC2 Interrupt Flag Register + PIFR2_POAC2B = 0x80 // PSC 2 Output A Activity + PIFR2_POAC2A = 0x40 // PSC 2 Output A Activity + PIFR2_PSEI2 = 0x20 // PSC 2 Synchro Error Interrupt + PIFR2_PEV2B = 0x10 // External Event B Interrupt + PIFR2_PEV2A = 0x8 // External Event A Interrupt + PIFR2_PRN2 = 0x6 // Ramp Number + PIFR2_PEOP2 = 0x1 // End of PSC2 Interrupt +) diff --git a/src/device/avr/at90pwm2b.ld b/src/device/avr/at90pwm2b.ld new file mode 100644 index 00000000..28912bf8 --- /dev/null +++ b/src/device/avr/at90pwm2b.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from AT90PWM2B.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_size = 0x200; +__num_isrs = 32; diff --git a/src/device/avr/at90pwm316.go b/src/device/avr/at90pwm316.go new file mode 100644 index 00000000..d2fe0877 --- /dev/null +++ b/src/device/avr/at90pwm316.go @@ -0,0 +1,1025 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from AT90PWM316.atdf, see http://packs.download.atmel.com/ + +// +build avr,at90pwm316 + +// Device information for the AT90PWM316. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "AT90PWM316" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset + IRQ_PSC2_CAPT = 1 // PSC2 Capture Event + IRQ_PSC2_EC = 2 // PSC2 End Cycle + IRQ_PSC1_CAPT = 3 // PSC1 Capture Event + IRQ_PSC1_EC = 4 // PSC1 End Cycle + IRQ_PSC0_CAPT = 5 // PSC0 Capture Event + IRQ_PSC0_EC = 6 // PSC0 End Cycle + IRQ_ANALOG_COMP_0 = 7 // Analog Comparator 0 + IRQ_ANALOG_COMP_1 = 8 // Analog Comparator 1 + IRQ_ANALOG_COMP_2 = 9 // Analog Comparator 2 + IRQ_INT0 = 10 // External Interrupt Request 0 + IRQ_TIMER1_CAPT = 11 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 12 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 13 // Timer/Counter Compare Match B + IRQ_RESERVED15 = 14 // + IRQ_TIMER1_OVF = 15 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP_A = 16 // Timer/Counter0 Compare Match A + IRQ_TIMER0_OVF = 17 // Timer/Counter0 Overflow + IRQ_ADC = 18 // ADC Conversion Complete + IRQ_INT1 = 19 // External Interrupt Request 1 + IRQ_SPI_STC = 20 // SPI Serial Transfer Complete + IRQ_USART_RX = 21 // USART, Rx Complete + IRQ_USART_UDRE = 22 // USART Data Register Empty + IRQ_USART_TX = 23 // USART, Tx Complete + IRQ_INT2 = 24 // External Interrupt Request 2 + IRQ_WDT = 25 // Watchdog Timeout Interrupt + IRQ_EE_READY = 26 // EEPROM Ready + IRQ_TIMER0_COMPB = 27 // Timer Counter 0 Compare Match B + IRQ_INT3 = 28 // External Interrupt Request 3 + IRQ_RESERVED30 = 29 // + IRQ_RESERVED31 = 30 // + IRQ_SPM_READY = 31 // Store Program Memory Read + IRQ_max = 31 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // I/O Port + PORT = struct { + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + }{ + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Port E Data Register + DDRE: 0x2d, // Port E Data Direction Register + PINE: 0x2c, // Port E Input Pins + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // Extended USART + EUSART = struct { + EUDR __reg + EUCSRA __reg + EUCSRB __reg + EUCSRC __reg + MUBRRH __reg + MUBRRL __reg + }{ + EUDR: 0xce, // EUSART I/O Data Register + EUCSRA: 0xc8, // EUSART Control and Status Register A + EUCSRB: 0xc9, // EUSART Control Register B + EUCSRC: 0xca, // EUSART Status Register C + MUBRRH: 0xcd, // Manchester Receiver Baud Rate Register High Byte + MUBRRL: 0xcc, // Manchester Receiver Baud Rate Register Low Byte + } + + // Analog Comparator + AC = struct { + AC0CON __reg + AC1CON __reg + AC2CON __reg + ACSR __reg + }{ + AC0CON: 0xad, // Analog Comparator 0 Control Register + AC1CON: 0xae, // Analog Comparator 1 Control Register + AC2CON: 0xaf, // Analog Comparator 2 Control Register + ACSR: 0x50, // Analog Comparator Status Register + } + + // Digital-to-Analog Converter + DAC = struct { + DACL __reg + DACH __reg + DACON __reg + }{ + DACL: 0xab, // DAC Data Register Bytes + DACH: 0xab, // DAC Data Register Bytes + DACON: 0xaa, // DAC Control Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + MCUCR __reg + MCUSR __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + GPIOR3 __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PLLCSR __reg + PRR __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, + SMCR: 0x53, // Sleep Mode Control Register + GPIOR3: 0x3b, // General Purpose IO Register 3 + GPIOR2: 0x3a, // General Purpose IO Register 2 + GPIOR1: 0x39, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PLLCSR: 0x49, // PLL Control And Status Register + PRR: 0x64, // Power Reduction Register + } + + // Timer/Counter, 8-bit + TC8 = struct { + TIMSK0 __reg + TIFR0 __reg + TCCR0A __reg + TCCR0B __reg + TCNT0 __reg + OCR0A __reg + OCR0B __reg + }{ + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + TCCR0A: 0x44, // Timer/Counter Control Register A + TCCR0B: 0x45, // Timer/Counter Control Register B + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + ADCSRB __reg + DIDR0 __reg + DIDR1 __reg + AMP0CSR __reg + AMP1CSR __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRB: 0x7b, // ADC Control and Status Register B + DIDR0: 0x7e, // Digital Input Disable Register 0 + DIDR1: 0x7f, // Digital Input Disable Register 1 + AMP0CSR: 0x76, + AMP1CSR: 0x77, + } + + // USART + USART = struct { + UDR __reg + UCSRA __reg + UCSRB __reg + UCSRC __reg + UBRRH __reg + UBRRL __reg + }{ + UDR: 0xc6, // USART I/O Data Register + UCSRA: 0xc0, // USART Control and Status register A + UCSRB: 0xc1, // USART Control an Status register B + UCSRC: 0xc2, // USART Control an Status register C + UBRRH: 0xc5, // USART Baud Rate Register High Byte + UBRRL: 0xc4, // USART Baud Rate Register Low Byte + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access Bytes + EEARH: 0x41, // EEPROM Read/Write Access Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Power Stage Controller + PSC = struct { + PICR0L __reg + PICR0H __reg + PFRC0B __reg + PFRC0A __reg + PCTL0 __reg + PCNF0 __reg + OCR0RBL __reg + OCR0RBH __reg + OCR0SBL __reg + OCR0SBH __reg + OCR0RAL __reg + OCR0RAH __reg + OCR0SAL __reg + OCR0SAH __reg + PSOC0 __reg + PIM0 __reg + PIFR0 __reg + PICR1L __reg + PICR1H __reg + PFRC1B __reg + PFRC1A __reg + PCTL1 __reg + PCNF1 __reg + OCR1RBL __reg + OCR1RBH __reg + OCR1SBL __reg + OCR1SBH __reg + OCR1RAL __reg + OCR1RAH __reg + OCR1SAL __reg + OCR1SAH __reg + PSOC1 __reg + PIM1 __reg + PIFR1 __reg + PICR2L __reg + PICR2H __reg + PFRC2B __reg + PFRC2A __reg + PCTL2 __reg + PCNF2 __reg + OCR2RBL __reg + OCR2RBH __reg + OCR2SBL __reg + OCR2SBH __reg + OCR2RAL __reg + OCR2RAH __reg + OCR2SAL __reg + OCR2SAH __reg + POM2 __reg + PSOC2 __reg + PIM2 __reg + PIFR2 __reg + }{ + PICR0L: 0xde, // PSC 0 Input Capture Register + PICR0H: 0xde, // PSC 0 Input Capture Register + PFRC0B: 0xdd, // PSC 0 Input B Control + PFRC0A: 0xdc, // PSC 0 Input A Control + PCTL0: 0xdb, // PSC 0 Control Register + PCNF0: 0xda, // PSC 0 Configuration Register + OCR0RBL: 0xd8, // Output Compare RB Register + OCR0RBH: 0xd8, // Output Compare RB Register + OCR0SBL: 0xd6, // Output Compare SB Register + OCR0SBH: 0xd6, // Output Compare SB Register + OCR0RAL: 0xd4, // Output Compare RA Register + OCR0RAH: 0xd4, // Output Compare RA Register + OCR0SAL: 0xd2, // Output Compare SA Register + OCR0SAH: 0xd2, // Output Compare SA Register + PSOC0: 0xd0, // PSC0 Synchro and Output Configuration + PIM0: 0xa1, // PSC0 Interrupt Mask Register + PIFR0: 0xa0, // PSC0 Interrupt Flag Register + PICR1L: 0xee, // PSC 1 Input Capture Register + PICR1H: 0xee, // PSC 1 Input Capture Register + PFRC1B: 0xed, // PSC 1 Input B Control + PFRC1A: 0xec, // PSC 1 Input B Control + PCTL1: 0xeb, // PSC 1 Control Register + PCNF1: 0xea, // PSC 1 Configuration Register + OCR1RBL: 0xe8, // Output Compare RB Register + OCR1RBH: 0xe8, // Output Compare RB Register + OCR1SBL: 0xe6, // Output Compare SB Register + OCR1SBH: 0xe6, // Output Compare SB Register + OCR1RAL: 0xe4, // Output Compare RA Register + OCR1RAH: 0xe4, // Output Compare RA Register + OCR1SAL: 0xe2, // Output Compare SA Register + OCR1SAH: 0xe2, // Output Compare SA Register + PSOC1: 0xe0, // PSC1 Synchro and Output Configuration + PIM1: 0xa3, // PSC1 Interrupt Mask Register + PIFR1: 0xa2, // PSC1 Interrupt Flag Register + PICR2L: 0xfe, // PSC 2 Input Capture Register + PICR2H: 0xfe, // PSC 2 Input Capture Register + PFRC2B: 0xfd, // PSC 2 Input B Control + PFRC2A: 0xfc, // PSC 2 Input B Control + PCTL2: 0xfb, // PSC 2 Control Register + PCNF2: 0xfa, // PSC 2 Configuration Register + OCR2RBL: 0xf8, // Output Compare RB Register + OCR2RBH: 0xf8, // Output Compare RB Register + OCR2SBL: 0xf6, // Output Compare SB Register + OCR2SBH: 0xf6, // Output Compare SB Register + OCR2RAL: 0xf4, // Output Compare RA Register + OCR2RAH: 0xf4, // Output Compare RA Register + OCR2SAL: 0xf2, // Output Compare SA Register + OCR2SAH: 0xf2, // Output Compare SA Register + POM2: 0xf1, // PSC 2 Output Matrix + PSOC2: 0xf0, // PSC2 Synchro and Output Configuration + PIM2: 0xa5, // PSC2 Interrupt Mask Register + PIFR2: 0xa4, // PSC2 Interrupt Flag Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_PSC2RB = 0x80 // PSC2 Reset Behavior + EXTENDED_PSC1RB = 0x40 // PSC1 Reset Behavior + EXTENDED_PSC0RB = 0x20 // PSC0 Reset Behavior + EXTENDED_PSCRV = 0x10 // PSCOUT Reset Value + EXTENDED_BOOTSZ = 0x6 // Select Boot Size + EXTENDED_BOOTRST = 0x1 // Select Reset Vector + + // HIGH + HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PC6 as i/o pin) + HIGH_DWEN = 0x40 // Debug Wire enable + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watch-dog Timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BODLEVEL = 0x7 // Brown-out Detector Trigger Level + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTB0 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for EUSART: Extended USART +const ( + // EUCSRA: EUSART Control and Status Register A + EUCSRA_UTxS = 0xf0 // EUSART Control and Status Register A Bits + EUCSRA_URxS = 0xf // EUSART Control and Status Register A Bits + + // EUCSRB: EUSART Control Register B + EUCSRB_EUSART = 0x10 // EUSART Enable Bit + EUCSRB_EUSBS = 0x8 // EUSBS Enable Bit + EUCSRB_EMCH = 0x2 // Manchester Mode Bit + EUCSRB_BODR = 0x1 // Order Bit + + // EUCSRC: EUSART Status Register C + EUCSRC_FEM = 0x8 // Frame Error Manchester Bit + EUCSRC_F1617 = 0x4 // F1617 Bit + EUCSRC_STP = 0x3 // Stop Bits + + // MUBRRH: Manchester Receiver Baud Rate Register High Byte + MUBRRH_MUBRR = 0xff // Manchester Receiver Baud Rate Register Bits + + // MUBRRL: Manchester Receiver Baud Rate Register Low Byte + MUBRRL_MUBRR = 0xff // Manchester Receiver Baud Rate Register Bits +) + +// Bitfields for AC: Analog Comparator +const ( + // AC0CON: Analog Comparator 0 Control Register + AC0CON_AC0EN = 0x80 // Analog Comparator 0 Enable Bit + AC0CON_AC0IE = 0x40 // Analog Comparator 0 Interrupt Enable Bit + AC0CON_AC0IS = 0x30 // Analog Comparator 0 Interrupt Select Bit + AC0CON_AC0M = 0x7 // Analog Comparator 0 Multiplexer Register + + // AC1CON: Analog Comparator 1 Control Register + AC1CON_AC1EN = 0x80 // Analog Comparator 1 Enable Bit + AC1CON_AC1IE = 0x40 // Analog Comparator 1 Interrupt Enable Bit + AC1CON_AC1IS = 0x30 // Analog Comparator 1 Interrupt Select Bit + AC1CON_AC1ICE = 0x8 // Analog Comparator 1 Interrupt Capture Enable Bit + AC1CON_AC1M = 0x7 // Analog Comparator 1 Multiplexer Register + + // AC2CON: Analog Comparator 2 Control Register + AC2CON_AC2EN = 0x80 // Analog Comparator 2 Enable Bit + AC2CON_AC2IE = 0x40 // Analog Comparator 2 Interrupt Enable Bit + AC2CON_AC2IS = 0x30 // Analog Comparator 2 Interrupt Select Bit + AC2CON_AC2M = 0x7 // Analog Comparator 2 Multiplexer Register + + // ACSR: Analog Comparator Status Register + ACSR_ACCKDIV = 0x80 // Analog Comparator Clock Divider + ACSR_AC2IF = 0x40 // Analog Comparator 2 Interrupt Flag Bit + ACSR_AC1IF = 0x20 // Analog Comparator 1 Interrupt Flag Bit + ACSR_AC0IF = 0x10 // Analog Comparator 0 Interrupt Flag Bit + ACSR_AC2O = 0x4 // Analog Comparator 2 Output Bit + ACSR_AC1O = 0x2 // Analog Comparator 1 Output Bit + ACSR_AC0O = 0x1 // Analog Comparator 0 Output Bit +) + +// Bitfields for DAC: Digital-to-Analog Converter +const ( + // DACL: DAC Data Register Bytes + + // DACH: DAC Data Register Bytes + DAC_DAC = 0xffff // DAC Data Register Bits + + // DACON: DAC Control Register + DACON_DAATE = 0x80 // DAC Auto Trigger Enable Bit + DACON_DATS = 0x70 // DAC Trigger Selection Bits + DACON_DALA = 0x4 // DAC Left Adjust + DACON_DAOE = 0x2 // DAC Output Enable + DACON_DAEN = 0x1 // DAC Enable Bit +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // MCUCR: MCU Control Register + MCUCR_SPIPS = 0x80 // SPI Pin Select + MCUCR_PUD = 0x10 // Pull-up disable + MCUCR_IVSEL = 0x2 // Interrupt Vector Select + MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable + + // MCUSR: MCU Status Register + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BORF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR3: General Purpose IO Register 3 + GPIOR3_GPIOR = 0xff // General Purpose IO Register 3 bis + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 + + // PLLCSR: PLL Control And Status Register + PLLCSR_PLLF = 0x4 // PLL Factor + PLLCSR_PLLE = 0x2 // PLL Enable + PLLCSR_PLOCK = 0x1 // PLL Lock Detector + + // PRR: Power Reduction Register + PRR_PRPSC2 = 0x80 // Power Reduction PSC2 + PRR_PRPSC1 = 0x40 // Power Reduction PSC1 + PRR_PRPSC0 = 0x20 // Power Reduction PSC0 + PRR_PRTIM1 = 0x10 // Power Reduction Timer/Counter1 + PRR_PRTIM0 = 0x8 // Power Reduction Timer/Counter0 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCNT0: Timer/Counter0 + TCNT0_TCNT0 = 0xff // Timer Counter 0 value + + // OCR0A: Timer/Counter0 Output Compare Register + OCR0A_OCR0A = 0xff // Output Compare A value + + // OCR0B: Timer/Counter0 Output Compare Register + OCR0B_OCR0B = 0xff // Output Compare B value +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TIMSK1: Timer/Counter Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output CompareB Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output CompareA Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 + TCCR1C_FOC1B = 0x40 + + // TCNT1L: Timer/Counter1 Bytes + + // TCNT1H: Timer/Counter1 Bytes + TCNT1_TCNT1 = 0xffff // Timer/Counter1 + + // OCR1AL: Timer/Counter1 Output Compare Register Bytes + + // OCR1AH: Timer/Counter1 Output Compare Register Bytes + OCR1A_OCR1A = 0xffff // Timer/Counter1 Output Compare A Register + + // OCR1BL: Timer/Counter1 Output Compare Register Bytes + + // OCR1BH: Timer/Counter1 Output Compare Register Bytes + OCR1B_OCR1B = 0xffff // Timer/Counter1 Output Compare B Register +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0xf // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCSRB: ADC Control and Status Register B + ADCSRB_ADHSM = 0x80 // ADC High Speed Mode + ADCSRB_ADTS3 = 0x8 // ADC Auto Trigger Source Selection 3 + ADCSRB_ADTS2 = 0x4 // ADC Auto Trigger Source Selection 2 + ADCSRB_ADTS1 = 0x2 // ADC Auto Trigger Source Selection 1 + ADCSRB_ADTS0 = 0x1 // ADC Auto Trigger Source Selection 0 + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 + DIDR0_ADC6D = 0x40 + DIDR0_ADC5D = 0x20 + DIDR0_ADC4D = 0x10 + DIDR0_ADC3D = 0x8 + DIDR0_ADC2D = 0x4 + DIDR0_ADC1D = 0x2 + DIDR0_ADC0D = 0x1 + + // DIDR1: Digital Input Disable Register 1 + DIDR1_ACMP0D = 0x20 + DIDR1_AMP0PD = 0x10 + DIDR1_AMP0ND = 0x8 + DIDR1_ADC10D = 0x4 + DIDR1_ADC9D = 0x2 + DIDR1_ADC8D = 0x1 + + // AMP0CSR + AMP0CSR_AMP0EN = 0x80 + AMP0CSR_AMP0IS = 0x40 + AMP0CSR_AMP0G = 0x30 + AMP0CSR_AMP0TS = 0x3 + + // AMP1CSR + AMP1CSR_AMP1EN = 0x80 + AMP1CSR_AMP1IS = 0x40 + AMP1CSR_AMP1G = 0x30 + AMP1CSR_AMP1TS = 0x3 +) + +// Bitfields for USART: USART +const ( + // UCSRA: USART Control and Status register A + UCSRA_RXC = 0x80 // USART Receive Complete + UCSRA_TXC = 0x40 // USART Transmitt Complete + UCSRA_UDRE = 0x20 // USART Data Register Empty + UCSRA_FE = 0x10 // Framing Error + UCSRA_DOR = 0x8 // Data Overrun + UCSRA_UPE = 0x4 // USART Parity Error + UCSRA_U2X = 0x2 // Double USART Transmission Bit + UCSRA_MPCM = 0x1 // Multi-processor Communication Mode + + // UCSRB: USART Control an Status register B + UCSRB_RXCIE = 0x80 // RX Complete Interrupt Enable + UCSRB_TXCIE = 0x40 // TX Complete Interrupt Enable + UCSRB_UDRIE = 0x20 // USART Data Register Empty Interrupt Enable + UCSRB_RXEN = 0x10 // Receiver Enable + UCSRB_TXEN = 0x8 // Transmitter Enable + UCSRB_UCSZ2 = 0x4 // Character Size + UCSRB_RXB8 = 0x2 // Receive Data Bit 8 + UCSRB_TXB8 = 0x1 // Transmit Data Bit 8 + + // UCSRC: USART Control an Status register C + UCSRC_UMSEL0 = 0x40 // USART Mode Select + UCSRC_UPM = 0x30 // Parity Mode Bits + UCSRC_USBS = 0x8 // Stop Bit Select + UCSRC_UCSZ = 0x6 // Character Size Bits + UCSRC_UCPOL = 0x1 // Clock Polarity + + // UBRRH: USART Baud Rate Register High Byte + UBRRH_UBRR = 0xf // USART Baud Rate Register Bits + + // UBRRL: USART Baud Rate Register Low Byte + UBRRL_UBRR = 0xff // USART Baud Rate Register bits +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPDR: SPI Data Register + SPDR_SPD = 0xff // SPI Data +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xf // External Interrupt Request 3 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xf // External Interrupt Flags +) + +// Bitfields for EEPROM: EEPROM +const ( + // EEARL: EEPROM Read/Write Access Bytes + + // EEARH: EEPROM Read/Write Access Bytes + EEAR_EEAR = 0xfff // EEPROM Address bytes + + // EEDR: EEPROM Data Register + EEDR_EEDR = 0xff // EEPROM Data Bits + + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for PSC: Power Stage Controller +const ( + // PICR0L: PSC 0 Input Capture Register + + // PICR0H: PSC 0 Input Capture Register + PICR0_PCST0 = 0x8000 // PSC 0 Input Capture Software Trig + PICR0_PICR0 = 0xfff // PSC 0 Input Capture Bytes + + // PFRC0B: PSC 0 Input B Control + PFRC0B_PCAE0B = 0x80 // PSC 0 Capture Enable Input Part B + PFRC0B_PISEL0B = 0x40 // PSC 0 Input Select for Part B + PFRC0B_PELEV0B = 0x20 // PSC 0 Edge Level Selector on Input Part B + PFRC0B_PFLTE0B = 0x10 // PSC 0 Filter Enable on Input Part B + PFRC0B_PRFM0B = 0xf // PSC 0 Retrigger and Fault Mode for Part B + + // PFRC0A: PSC 0 Input A Control + PFRC0A_PCAE0A = 0x80 // PSC 0 Capture Enable Input Part A + PFRC0A_PISEL0A = 0x40 // PSC 0 Input Select for Part A + PFRC0A_PELEV0A = 0x20 // PSC 0 Edge Level Selector on Input Part A + PFRC0A_PFLTE0A = 0x10 // PSC 0 Filter Enable on Input Part A + PFRC0A_PRFM0A = 0xf // PSC 0 Retrigger and Fault Mode for Part A + + // PCTL0: PSC 0 Control Register + PCTL0_PPRE0 = 0xc0 // PSC 0 Prescaler Selects + PCTL0_PBFM0 = 0x20 // PSC 0 Balance Flank Width Modulation + PCTL0_PAOC0B = 0x10 // PSC 0 Asynchronous Output Control B + PCTL0_PAOC0A = 0x8 // PSC 0 Asynchronous Output Control A + PCTL0_PARUN0 = 0x4 // PSC0 Auto Run + PCTL0_PCCYC0 = 0x2 // PSC0 Complete Cycle + PCTL0_PRUN0 = 0x1 // PSC 0 Run + + // PCNF0: PSC 0 Configuration Register + PCNF0_PFIFTY0 = 0x80 // PSC 0 Fifty + PCNF0_PALOCK0 = 0x40 // PSC 0 Autolock + PCNF0_PLOCK0 = 0x20 // PSC 0 Lock + PCNF0_PMODE0 = 0x18 // PSC 0 Mode + PCNF0_POP0 = 0x4 // PSC 0 Output Polarity + PCNF0_PCLKSEL0 = 0x2 // PSC 0 Input Clock Select + + // PSOC0: PSC0 Synchro and Output Configuration + PSOC0_PSYNC0 = 0x30 // Synchronization Out for ADC Selection + PSOC0_POEN0B = 0x4 // PSCOUT01 Output Enable + PSOC0_POEN0A = 0x1 // PSCOUT00 Output Enable + + // PIM0: PSC0 Interrupt Mask Register + PIM0_PSEIE0 = 0x20 // PSC 0 Synchro Error Interrupt Enable + PIM0_PEVE0B = 0x10 // External Event B Interrupt Enable + PIM0_PEVE0A = 0x8 // External Event A Interrupt Enable + PIM0_PEOPE0 = 0x1 // End of Cycle Interrupt Enable + + // PIFR0: PSC0 Interrupt Flag Register + PIFR0_POAC0B = 0x80 // PSC 0 Output A Activity + PIFR0_POAC0A = 0x40 // PSC 0 Output A Activity + PIFR0_PSEI0 = 0x20 // PSC 0 Synchro Error Interrupt + PIFR0_PEV0B = 0x10 // External Event B Interrupt + PIFR0_PEV0A = 0x8 // External Event A Interrupt + PIFR0_PRN0 = 0x6 // Ramp Number + PIFR0_PEOP0 = 0x1 // End of PSC0 Interrupt + + // PICR1L: PSC 1 Input Capture Register + + // PICR1H: PSC 1 Input Capture Register + PICR1_PCST1 = 0x8000 // PSC 1 Input Capture Software Trig + PICR1_PICR1 = 0xfff // PSC 1 Input Capture Bytes + + // PFRC1B: PSC 1 Input B Control + PFRC1B_PCAE1B = 0x80 // PSC 1 Capture Enable Input Part B + PFRC1B_PISEL1B = 0x40 // PSC 1 Input Select for Part B + PFRC1B_PELEV1B = 0x20 // PSC 1 Edge Level Selector on Input Part B + PFRC1B_PFLTE1B = 0x10 // PSC 1 Filter Enable on Input Part B + PFRC1B_PRFM1B = 0xf // PSC 1 Retrigger and Fault Mode for Part B + + // PFRC1A: PSC 1 Input B Control + PFRC1A_PCAE1A = 0x80 // PSC 1 Capture Enable Input Part A + PFRC1A_PISEL1A = 0x40 // PSC 1 Input Select for Part A + PFRC1A_PELEV1A = 0x20 // PSC 1 Edge Level Selector on Input Part A + PFRC1A_PFLTE1A = 0x10 // PSC 1 Filter Enable on Input Part A + PFRC1A_PRFM1A = 0xf // PSC 1 Retrigger and Fault Mode for Part A + + // PCTL1: PSC 1 Control Register + PCTL1_PPRE1 = 0xc0 // PSC 1 Prescaler Selects + PCTL1_PBFM1 = 0x20 // Balance Flank Width Modulation + PCTL1_PAOC1B = 0x10 // PSC 1 Asynchronous Output Control B + PCTL1_PAOC1A = 0x8 // PSC 1 Asynchronous Output Control A + PCTL1_PARUN1 = 0x4 // PSC1 Auto Run + PCTL1_PCCYC1 = 0x2 // PSC1 Complete Cycle + PCTL1_PRUN1 = 0x1 // PSC 1 Run + + // PCNF1: PSC 1 Configuration Register + PCNF1_PFIFTY1 = 0x80 // PSC 1 Fifty + PCNF1_PALOCK1 = 0x40 // PSC 1 Autolock + PCNF1_PLOCK1 = 0x20 // PSC 1 Lock + PCNF1_PMODE1 = 0x18 // PSC 1 Mode + PCNF1_POP1 = 0x4 // PSC 1 Output Polarity + PCNF1_PCLKSEL1 = 0x2 // PSC 1 Input Clock Select + + // PSOC1: PSC1 Synchro and Output Configuration + PSOC1_PSYNC1_ = 0x30 // Synchronization Out for ADC Selection + PSOC1_POEN1B = 0x4 // PSCOUT11 Output Enable + PSOC1_POEN1A = 0x1 // PSCOUT10 Output Enable + + // PIM1: PSC1 Interrupt Mask Register + PIM1_PSEIE1 = 0x20 // PSC 1 Synchro Error Interrupt Enable + PIM1_PEVE1B = 0x10 // External Event B Interrupt Enable + PIM1_PEVE1A = 0x8 // External Event A Interrupt Enable + PIM1_PEOPE1 = 0x1 // End of Cycle Interrupt Enable + + // PIFR1: PSC1 Interrupt Flag Register + PIFR1_POAC1B = 0x80 // PSC 1 Output B Activity + PIFR1_POAC1A = 0x40 // PSC 1 Output A Activity + PIFR1_PSEI1 = 0x20 // PSC 1 Synchro Error Interrupt + PIFR1_PEV1B = 0x10 // External Event B Interrupt + PIFR1_PEV1A = 0x8 // External Event A Interrupt + PIFR1_PRN1 = 0x6 // Ramp Number + PIFR1_PEOP1 = 0x1 // End of PSC1 Interrupt + + // PICR2L: PSC 2 Input Capture Register + + // PICR2H: PSC 2 Input Capture Register + PICR2_PCST2 = 0x8000 // PSC 2 Input Capture Software Trig + PICR2_PICR2 = 0xfff // PSC 2 Input Capture Bytes + + // PFRC2B: PSC 2 Input B Control + PFRC2B_PCAE2B = 0x80 // PSC 2 Capture Enable Input Part B + PFRC2B_PISEL2B = 0x40 // PSC 2 Input Select for Part B + PFRC2B_PELEV2B = 0x20 // PSC 2 Edge Level Selector on Input Part B + PFRC2B_PFLTE2B = 0x10 // PSC 2 Filter Enable on Input Part B + PFRC2B_PRFM2B = 0xf // PSC 2 Retrigger and Fault Mode for Part B + + // PFRC2A: PSC 2 Input B Control + PFRC2A_PCAE2A = 0x80 // PSC 2 Capture Enable Input Part A + PFRC2A_PISEL2A = 0x40 // PSC 2 Input Select for Part A + PFRC2A_PELEV2A = 0x20 // PSC 2 Edge Level Selector on Input Part A + PFRC2A_PFLTE2A = 0x10 // PSC 2 Filter Enable on Input Part A + PFRC2A_PRFM2A = 0xf // PSC 2 Retrigger and Fault Mode for Part A + + // PCTL2: PSC 2 Control Register + PCTL2_PPRE2 = 0xc0 // PSC 2 Prescaler Selects + PCTL2_PBFM2 = 0x20 // Balance Flank Width Modulation + PCTL2_PAOC2B = 0x10 // PSC 2 Asynchronous Output Control B + PCTL2_PAOC2A = 0x8 // PSC 2 Asynchronous Output Control A + PCTL2_PARUN2 = 0x4 // PSC2 Auto Run + PCTL2_PCCYC2 = 0x2 // PSC2 Complete Cycle + PCTL2_PRUN2 = 0x1 // PSC 2 Run + + // PCNF2: PSC 2 Configuration Register + PCNF2_PFIFTY2 = 0x80 // PSC 2 Fifty + PCNF2_PALOCK2 = 0x40 // PSC 2 Autolock + PCNF2_PLOCK2 = 0x20 // PSC 2 Lock + PCNF2_PMODE2 = 0x18 // PSC 2 Mode + PCNF2_POP2 = 0x4 // PSC 2 Output Polarity + PCNF2_PCLKSEL2 = 0x2 // PSC 2 Input Clock Select + PCNF2_POME2 = 0x1 // PSC 2 Output Matrix Enable + + // POM2: PSC 2 Output Matrix + POM2_POMV2B = 0xf0 // Output Matrix Output B Ramps + POM2_POMV2A = 0xf // Output Matrix Output A Ramps + + // PSOC2: PSC2 Synchro and Output Configuration + PSOC2_POS2 = 0xc0 // PSC 2 Output 23 Select + PSOC2_PSYNC2_ = 0x30 // Synchronization Out for ADC Selection + PSOC2_POEN2D = 0x8 // PSCOUT23 Output Enable + PSOC2_POEN2B = 0x4 // PSCOUT21 Output Enable + PSOC2_POEN2C = 0x2 // PSCOUT22 Output Enable + PSOC2_POEN2A = 0x1 // PSCOUT20 Output Enable + + // PIM2: PSC2 Interrupt Mask Register + PIM2_PSEIE2 = 0x20 // PSC 2 Synchro Error Interrupt Enable + PIM2_PEVE2B = 0x10 // External Event B Interrupt Enable + PIM2_PEVE2A = 0x8 // External Event A Interrupt Enable + PIM2_PEOPE2 = 0x1 // End of Cycle Interrupt Enable + + // PIFR2: PSC2 Interrupt Flag Register + PIFR2_POAC2B = 0x80 // PSC 2 Output A Activity + PIFR2_POAC2A = 0x40 // PSC 2 Output A Activity + PIFR2_PSEI2 = 0x20 // PSC 2 Synchro Error Interrupt + PIFR2_PEV2B = 0x10 // External Event B Interrupt + PIFR2_PEV2A = 0x8 // External Event A Interrupt + PIFR2_PRN2 = 0x6 // Ramp Number + PIFR2_PEOP2 = 0x1 // End of PSC2 Interrupt +) diff --git a/src/device/avr/at90pwm316.ld b/src/device/avr/at90pwm316.ld new file mode 100644 index 00000000..ee0a17c0 --- /dev/null +++ b/src/device/avr/at90pwm316.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from AT90PWM316.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_size = 0x400; +__num_isrs = 32; diff --git a/src/device/avr/at90pwm3b.go b/src/device/avr/at90pwm3b.go new file mode 100644 index 00000000..e35c601c --- /dev/null +++ b/src/device/avr/at90pwm3b.go @@ -0,0 +1,1097 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from AT90PWM3B.atdf, see http://packs.download.atmel.com/ + +// +build avr,at90pwm3b + +// Device information for the AT90PWM3B. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "AT90PWM3B" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset + IRQ_PSC2_CAPT = 1 // PSC2 Capture Event + IRQ_PSC2_EC = 2 // PSC2 End Cycle + IRQ_PSC1_CAPT = 3 // PSC1 Capture Event + IRQ_PSC1_EC = 4 // PSC1 End Cycle + IRQ_PSC0_CAPT = 5 // PSC0 Capture Event + IRQ_PSC0_EC = 6 // PSC0 End Cycle + IRQ_ANALOG_COMP_0 = 7 // Analog Comparator 0 + IRQ_ANALOG_COMP_1 = 8 // Analog Comparator 1 + IRQ_ANALOG_COMP_2 = 9 // Analog Comparator 2 + IRQ_INT0 = 10 // External Interrupt Request 0 + IRQ_TIMER1_CAPT = 11 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 12 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 13 // Timer/Counter Compare Match B + IRQ_RESERVED15 = 14 // + IRQ_TIMER1_OVF = 15 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 16 // Timer/Counter0 Compare Match A + IRQ_TIMER0_OVF = 17 // Timer/Counter0 Overflow + IRQ_ADC = 18 // ADC Conversion Complete + IRQ_INT1 = 19 // External Interrupt Request 1 + IRQ_SPI_STC = 20 // SPI Serial Transfer Complete + IRQ_USART_RX = 21 // USART, Rx Complete + IRQ_USART_UDRE = 22 // USART Data Register Empty + IRQ_USART_TX = 23 // USART, Tx Complete + IRQ_INT2 = 24 // External Interrupt Request 2 + IRQ_WDT = 25 // Watchdog Timeout Interrupt + IRQ_EE_READY = 26 // EEPROM Ready + IRQ_TIMER0_COMPB = 27 // Timer Counter 0 Compare Match B + IRQ_INT3 = 28 // External Interrupt Request 3 + IRQ_RESERVED30 = 29 // + IRQ_RESERVED31 = 30 // + IRQ_SPM_READY = 31 // Store Program Memory Read + IRQ_max = 31 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // I/O Port + PORT = struct { + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + }{ + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Port E Data Register + DDRE: 0x2d, // Port E Data Direction Register + PINE: 0x2c, // Port E Input Pins + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // Extended USART + EUSART = struct { + EUDR __reg + EUCSRA __reg + EUCSRB __reg + EUCSRC __reg + MUBRRL __reg + MUBRRH __reg + }{ + EUDR: 0xce, // EUSART I/O Data Register + EUCSRA: 0xc8, // EUSART Control and Status Register A + EUCSRB: 0xc9, // EUSART Control Register B + EUCSRC: 0xca, // EUSART Status Register C + MUBRRL: 0xcc, // Manchester Receiver Baud Rate Register + MUBRRH: 0xcc, // Manchester Receiver Baud Rate Register + } + + // Analog Comparator + AC = struct { + AC0CON __reg + AC1CON __reg + AC2CON __reg + ACSR __reg + }{ + AC0CON: 0xad, // Analog Comparator 0 Control Register + AC1CON: 0xae, // Analog Comparator 1 Control Register + AC2CON: 0xaf, // Analog Comparator 2 Control Register + ACSR: 0x50, // Analog Comparator Status Register + } + + // Digital-to-Analog Converter + DAC = struct { + DACL __reg + DACH __reg + DACON __reg + }{ + DACL: 0xab, // DAC Data Register + DACH: 0xab, // DAC Data Register + DACON: 0xaa, // DAC Control Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + MCUCR __reg + MCUSR __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + GPIOR3 __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PLLCSR __reg + PRR __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, + SMCR: 0x53, // Sleep Mode Control Register + GPIOR3: 0x3b, // General Purpose IO Register 3 + GPIOR2: 0x3a, // General Purpose IO Register 2 + GPIOR1: 0x39, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PLLCSR: 0x49, // PLL Control And Status Register + PRR: 0x64, // Power Reduction Register + } + + // Timer/Counter, 8-bit + TC8 = struct { + TIMSK0 __reg + TIFR0 __reg + TCCR0A __reg + TCCR0B __reg + TCNT0 __reg + OCR0A __reg + OCR0B __reg + }{ + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + TCCR0A: 0x44, // Timer/Counter Control Register A + TCCR0B: 0x45, // Timer/Counter Control Register B + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + ADCSRB __reg + DIDR0 __reg + DIDR1 __reg + AMP0CSR __reg + AMP1CSR __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRB: 0x7b, // ADC Control and Status Register B + DIDR0: 0x7e, // Digital Input Disable Register 0 + DIDR1: 0x7f, // Digital Input Disable Register 1 + AMP0CSR: 0x76, + AMP1CSR: 0x77, + } + + // USART + USART = struct { + UDR __reg + UCSRA __reg + UCSRB __reg + UCSRC __reg + UBRRL __reg + UBRRH __reg + }{ + UDR: 0xc6, // USART I/O Data Register + UCSRA: 0xc0, // USART Control and Status register A + UCSRB: 0xc1, // USART Control an Status register B + UCSRC: 0xc2, // USART Control an Status register C + UBRRL: 0xc4, // USART Baud Rate Register + UBRRH: 0xc4, // USART Baud Rate Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access Bytes + EEARH: 0x41, // EEPROM Read/Write Access Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Power Stage Controller + PSC = struct { + PICR0L __reg + PICR0H __reg + PFRC0B __reg + PFRC0A __reg + PCTL0 __reg + PCNF0 __reg + OCR0RBL __reg + OCR0RBH __reg + OCR0SBL __reg + OCR0SBH __reg + OCR0RAL __reg + OCR0RAH __reg + OCR0SAL __reg + OCR0SAH __reg + PSOC0 __reg + PIM0 __reg + PIFR0 __reg + PICR1L __reg + PICR1H __reg + PFRC1B __reg + PFRC1A __reg + PCTL1 __reg + PCNF1 __reg + OCR1RBL __reg + OCR1RBH __reg + OCR1SBL __reg + OCR1SBH __reg + OCR1RAL __reg + OCR1RAH __reg + OCR1SAL __reg + OCR1SAH __reg + PSOC1 __reg + PIM1 __reg + PIFR1 __reg + PICR2L __reg + PICR2H __reg + PFRC2B __reg + PFRC2A __reg + PCTL2 __reg + PCNF2 __reg + OCR2RBL __reg + OCR2RBH __reg + OCR2SBL __reg + OCR2SBH __reg + OCR2RAL __reg + OCR2RAH __reg + OCR2SAL __reg + OCR2SAH __reg + POM2 __reg + PSOC2 __reg + PIM2 __reg + PIFR2 __reg + }{ + PICR0L: 0xde, // PSC 0 Input Capture Register + PICR0H: 0xde, // PSC 0 Input Capture Register + PFRC0B: 0xdd, // PSC 0 Input B Control + PFRC0A: 0xdc, // PSC 0 Input A Control + PCTL0: 0xdb, // PSC 0 Control Register + PCNF0: 0xda, // PSC 0 Configuration Register + OCR0RBL: 0xd8, // Output Compare 0 RB Register + OCR0RBH: 0xd8, // Output Compare 0 RB Register + OCR0SBL: 0xd6, // Output Compare 0 SB Register + OCR0SBH: 0xd6, // Output Compare 0 SB Register + OCR0RAL: 0xd4, // Output Compare 0 RA Register + OCR0RAH: 0xd4, // Output Compare 0 RA Register + OCR0SAL: 0xd2, // Output Compare 0 SA Register + OCR0SAH: 0xd2, // Output Compare 0 SA Register + PSOC0: 0xd0, // PSC0 Synchro and Output Configuration + PIM0: 0xa1, // PSC0 Interrupt Mask Register + PIFR0: 0xa0, // PSC0 Interrupt Flag Register + PICR1L: 0xee, // PSC 1 Input Capture Register + PICR1H: 0xee, // PSC 1 Input Capture Register + PFRC1B: 0xed, // PSC 1 Input B Control + PFRC1A: 0xec, // PSC 1 Input B Control + PCTL1: 0xeb, // PSC 1 Control Register + PCNF1: 0xea, // PSC 1 Configuration Register + OCR1RBL: 0xe8, // Output Compare RB Register + OCR1RBH: 0xe8, // Output Compare RB Register + OCR1SBL: 0xe6, // Output Compare SB Register + OCR1SBH: 0xe6, // Output Compare SB Register + OCR1RAL: 0xe4, // Output Compare RA Register + OCR1RAH: 0xe4, // Output Compare RA Register + OCR1SAL: 0xe2, // Output Compare SA Register + OCR1SAH: 0xe2, // Output Compare SA Register + PSOC1: 0xe0, // PSC1 Synchro and Output Configuration + PIM1: 0xa3, // PSC1 Interrupt Mask Register + PIFR1: 0xa2, // PSC1 Interrupt Flag Register + PICR2L: 0xfe, // PSC 2 Input Capture Register + PICR2H: 0xfe, // PSC 2 Input Capture Register + PFRC2B: 0xfd, // PSC 2 Input B Control + PFRC2A: 0xfc, // PSC 2 Input B Control + PCTL2: 0xfb, // PSC 2 Control Register + PCNF2: 0xfa, // PSC 2 Configuration Register + OCR2RBL: 0xf8, // Output Compare 2 RB Register + OCR2RBH: 0xf8, // Output Compare 2 RB Register + OCR2SBL: 0xf6, // Output Compare 2 SB Register + OCR2SBH: 0xf6, // Output Compare 2 SB Register + OCR2RAL: 0xf4, // Output Compare 2 RA Register + OCR2RAH: 0xf4, // Output Compare 2 RA Register + OCR2SAL: 0xf2, // Output Compare 2 SA Register + OCR2SAH: 0xf2, // Output Compare 2 SA Register + POM2: 0xf1, // PSC 2 Output Matrix + PSOC2: 0xf0, // PSC2 Synchro and Output Configuration + PIM2: 0xa5, // PSC2 Interrupt Mask Register + PIFR2: 0xa4, // PSC2 Interrupt Flag Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_PSC2RB = 0x80 // PSC2 Reset Behavior + EXTENDED_PSC1RB = 0x40 // PSC1 Reset Behavior + EXTENDED_PSC0RB = 0x20 // PSC0 Reset Behavior + EXTENDED_PSCRV = 0x10 // PSCOUT Reset Value + EXTENDED_BOOTSZ = 0x6 // Select Boot Size + EXTENDED_BOOTRST = 0x1 // Select Reset Vector + + // HIGH + HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PC6 as i/o pin) + HIGH_DWEN = 0x40 // Debug Wire enable + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watch-dog Timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BODLEVEL = 0x7 // Brown-out Detector Trigger Level + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTB0 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for EUSART: Extended USART +const ( + // EUDR: EUSART I/O Data Register + EUDR_EUDR = 0xff // EUSART Extended data bits + + // EUCSRA: EUSART Control and Status Register A + EUCSRA_UTxS = 0xf0 // EUSART Control and Status Register A Bits + EUCSRA_URxS = 0xf // EUSART Control and Status Register A Bits + + // EUCSRB: EUSART Control Register B + EUCSRB_EUSART = 0x10 // EUSART Enable Bit + EUCSRB_EUSBS = 0x8 // EUSBS Enable Bit + EUCSRB_EMCH = 0x2 // Manchester Mode Bit + EUCSRB_BODR = 0x1 // Order Bit + + // EUCSRC: EUSART Status Register C + EUCSRC_FEM = 0x8 // Frame Error Manchester Bit + EUCSRC_F1617 = 0x4 // F1617 Bit + EUCSRC_STP = 0x3 // Stop Bits + + // MUBRRL: Manchester Receiver Baud Rate Register + + // MUBRRH: Manchester Receiver Baud Rate Register + MUBRR_MUBRR = 0xffff // Manchester Receiver Baud Rate Register Bits +) + +// Bitfields for AC: Analog Comparator +const ( + // AC0CON: Analog Comparator 0 Control Register + AC0CON_AC0EN = 0x80 // Analog Comparator 0 Enable Bit + AC0CON_AC0IE = 0x40 // Analog Comparator 0 Interrupt Enable Bit + AC0CON_AC0IS = 0x30 // Analog Comparator 0 Interrupt Select Bit + AC0CON_AC0M = 0x7 // Analog Comparator 0 Multiplexer Register + + // AC1CON: Analog Comparator 1 Control Register + AC1CON_AC1EN = 0x80 // Analog Comparator 1 Enable Bit + AC1CON_AC1IE = 0x40 // Analog Comparator 1 Interrupt Enable Bit + AC1CON_AC1IS = 0x30 // Analog Comparator 1 Interrupt Select Bit + AC1CON_AC1ICE = 0x8 // Analog Comparator 1 Interrupt Capture Enable Bit + AC1CON_AC1M = 0x7 // Analog Comparator 1 Multiplexer Register + + // AC2CON: Analog Comparator 2 Control Register + AC2CON_AC2EN = 0x80 // Analog Comparator 2 Enable Bit + AC2CON_AC2IE = 0x40 // Analog Comparator 2 Interrupt Enable Bit + AC2CON_AC2IS = 0x30 // Analog Comparator 2 Interrupt Select Bit + AC2CON_AC2M = 0x7 // Analog Comparator 2 Multiplexer Register + + // ACSR: Analog Comparator Status Register + ACSR_ACCKDIV = 0x80 // Analog Comparator Clock Divider + ACSR_AC2IF = 0x40 // Analog Comparator 2 Interrupt Flag Bit + ACSR_AC1IF = 0x20 // Analog Comparator 1 Interrupt Flag Bit + ACSR_AC0IF = 0x10 // Analog Comparator 0 Interrupt Flag Bit + ACSR_AC2O = 0x4 // Analog Comparator 2 Output Bit + ACSR_AC1O = 0x2 // Analog Comparator 1 Output Bit + ACSR_AC0O = 0x1 // Analog Comparator 0 Output Bit +) + +// Bitfields for DAC: Digital-to-Analog Converter +const ( + // DACL: DAC Data Register + + // DACH: DAC Data Register + DAC_DAC = 0xffff // DAC Data Register Bits + + // DACON: DAC Control Register + DACON_DAATE = 0x80 // DAC Auto Trigger Enable Bit + DACON_DATS = 0x70 // DAC Trigger Selection Bits + DACON_DALA = 0x4 // DAC Left Adjust + DACON_DAOE = 0x2 // DAC Output Enable + DACON_DAEN = 0x1 // DAC Enable Bit +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // MCUCR: MCU Control Register + MCUCR_SPIPS = 0x80 // SPI Pin Select + MCUCR_PUD = 0x10 // Pull-up disable + MCUCR_IVSEL = 0x2 // Interrupt Vector Select + MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable + + // MCUSR: MCU Status Register + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BORF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR3: General Purpose IO Register 3 + GPIOR3_GPIOR = 0xff // General Purpose IO Register 3 bis + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 + + // PLLCSR: PLL Control And Status Register + PLLCSR_PLLF = 0x4 // PLL Factor + PLLCSR_PLLE = 0x2 // PLL Enable + PLLCSR_PLOCK = 0x1 // PLL Lock Detector + + // PRR: Power Reduction Register + PRR_PRPSC2 = 0x80 // Power Reduction PSC2 + PRR_PRPSC1 = 0x40 // Power Reduction PSC1 + PRR_PRPSC0 = 0x20 // Power Reduction PSC0 + PRR_PRTIM1 = 0x10 // Power Reduction Timer/Counter1 + PRR_PRTIM0 = 0x8 // Power Reduction Timer/Counter0 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCNT0: Timer/Counter0 + TCNT0_TCNT0 = 0xff // Timer Counter 0 value + + // OCR0A: Timer/Counter0 Output Compare Register + OCR0A_OCR0A = 0xff // Timer/Counter0 Output Compare A + + // OCR0B: Timer/Counter0 Output Compare Register + OCR0B_OCR0B = 0xff // Timer/Counter0 Output Compare B +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TIMSK1: Timer/Counter Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output CompareB Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output CompareA Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 + TCCR1C_FOC1B = 0x40 + + // TCNT1L: Timer/Counter1 Bytes + + // TCNT1H: Timer/Counter1 Bytes + TCNT1_TCNT1 = 0xffff // Timer/Counter1 + + // OCR1AL: Timer/Counter1 Output Compare Register Bytes + + // OCR1AH: Timer/Counter1 Output Compare Register Bytes + OCR1A_OCR1A = 0xffff // Timer/Counter1 Output Compare A + + // OCR1BL: Timer/Counter1 Output Compare Register Bytes + + // OCR1BH: Timer/Counter1 Output Compare Register Bytes + OCR1B_OCR1B = 0xffff // Timer/Counter1 Output Compare B + + // ICR1L: Timer/Counter1 Input Capture Register Bytes + + // ICR1H: Timer/Counter1 Input Capture Register Bytes + ICR1_ICR1 = 0xffff // Timer/Counter1 Input Capture +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0xf // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCL: ADC Data Register Bytes + + // ADCH: ADC Data Register Bytes + ADC_ADC = 0xffff // ADC Data Register + + // ADCSRB: ADC Control and Status Register B + ADCSRB_ADHSM = 0x80 // ADC High Speed Mode + ADCSRB_ADTS = 0xf // ADC Auto Trigger Source + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 + DIDR0_ADC6D = 0x40 + DIDR0_ADC5D = 0x20 + DIDR0_ADC4D = 0x10 + DIDR0_ADC3D = 0x8 + DIDR0_ADC2D = 0x4 + DIDR0_ADC1D = 0x2 + DIDR0_ADC0D = 0x1 + + // DIDR1: Digital Input Disable Register 1 + DIDR1_ACMP0D = 0x20 + DIDR1_AMP0PD = 0x10 + DIDR1_AMP0ND = 0x8 + DIDR1_ADC10D = 0x4 + DIDR1_ADC9D = 0x2 + DIDR1_ADC8D = 0x1 + + // AMP0CSR + AMP0CSR_AMP0EN = 0x80 + AMP0CSR_AMP0IS = 0x40 + AMP0CSR_AMP0G = 0x30 + AMP0CSR_AMP0TS = 0x3 + + // AMP1CSR + AMP1CSR_AMP1EN = 0x80 + AMP1CSR_AMP1IS = 0x40 + AMP1CSR_AMP1G = 0x30 + AMP1CSR_AMP1TS = 0x3 +) + +// Bitfields for USART: USART +const ( + // UDR: USART I/O Data Register + UDR_UDR = 0xff // USART I/O Data + + // UCSRA: USART Control and Status register A + UCSRA_RXC = 0x80 // USART Receive Complete + UCSRA_TXC = 0x40 // USART Transmitt Complete + UCSRA_UDRE = 0x20 // USART Data Register Empty + UCSRA_FE = 0x10 // Framing Error + UCSRA_DOR = 0x8 // Data Overrun + UCSRA_UPE = 0x4 // USART Parity Error + UCSRA_U2X = 0x2 // Double USART Transmission Bit + UCSRA_MPCM = 0x1 // Multi-processor Communication Mode + + // UCSRB: USART Control an Status register B + UCSRB_RXCIE = 0x80 // RX Complete Interrupt Enable + UCSRB_TXCIE = 0x40 // TX Complete Interrupt Enable + UCSRB_UDRIE = 0x20 // USART Data Register Empty Interrupt Enable + UCSRB_RXEN = 0x10 // Receiver Enable + UCSRB_TXEN = 0x8 // Transmitter Enable + UCSRB_UCSZ2 = 0x4 // Character Size + UCSRB_RXB8 = 0x2 // Receive Data Bit 8 + UCSRB_TXB8 = 0x1 // Transmit Data Bit 8 + + // UCSRC: USART Control an Status register C + UCSRC_UMSEL0 = 0x40 // USART Mode Select + UCSRC_UPM = 0x30 // Parity Mode Bits + UCSRC_USBS = 0x8 // Stop Bit Select + UCSRC_UCSZ = 0x6 // Character Size Bits + UCSRC_UCPOL = 0x1 // Clock Polarity + + // UBRRL: USART Baud Rate Register + + // UBRRH: USART Baud Rate Register + UBRR_UBRR = 0xfff // USART Baud Rate Register Bits +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPDR: SPI Data Register + SPDR_SPD = 0xff // SPI Data bits +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xf // External Interrupt Request Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xf // External Interrupt Flags +) + +// Bitfields for EEPROM: EEPROM +const ( + // EEARL: EEPROM Read/Write Access Bytes + + // EEARH: EEPROM Read/Write Access Bytes + EEAR_EEAR = 0xfff // EEPROM Address bytes + + // EEDR: EEPROM Data Register + EEDR_EEDR = 0xff // EEPROM Data Bits + + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for PSC: Power Stage Controller +const ( + // PICR0L: PSC 0 Input Capture Register + + // PICR0H: PSC 0 Input Capture Register + PICR0_PCST0 = 0x8000 // PSC 0 Input Capture Software Trig + PICR0_PICR0 = 0xfff // PSC 0 Input Capture Bytes + + // PFRC0B: PSC 0 Input B Control + PFRC0B_PCAE0B = 0x80 // PSC 0 Capture Enable Input Part B + PFRC0B_PISEL0B = 0x40 // PSC 0 Input Select for Part B + PFRC0B_PELEV0B = 0x20 // PSC 0 Edge Level Selector on Input Part B + PFRC0B_PFLTE0B = 0x10 // PSC 0 Filter Enable on Input Part B + PFRC0B_PRFM0B = 0xf // PSC 0 Retrigger and Fault Mode for Part B + + // PFRC0A: PSC 0 Input A Control + PFRC0A_PCAE0A = 0x80 // PSC 0 Capture Enable Input Part A + PFRC0A_PISEL0A = 0x40 // PSC 0 Input Select for Part A + PFRC0A_PELEV0A = 0x20 // PSC 0 Edge Level Selector on Input Part A + PFRC0A_PFLTE0A = 0x10 // PSC 0 Filter Enable on Input Part A + PFRC0A_PRFM0A = 0xf // PSC 0 Retrigger and Fault Mode for Part A + + // PCTL0: PSC 0 Control Register + PCTL0_PPRE0 = 0xc0 // PSC 0 Prescaler Selects + PCTL0_PBFM0 = 0x20 // PSC 0 Balance Flank Width Modulation + PCTL0_PAOC0B = 0x10 // PSC 0 Asynchronous Output Control B + PCTL0_PAOC0A = 0x8 // PSC 0 Asynchronous Output Control A + PCTL0_PARUN0 = 0x4 // PSC0 Auto Run + PCTL0_PCCYC0 = 0x2 // PSC0 Complete Cycle + PCTL0_PRUN0 = 0x1 // PSC 0 Run + + // PCNF0: PSC 0 Configuration Register + PCNF0_PFIFTY0 = 0x80 // PSC 0 Fifty + PCNF0_PALOCK0 = 0x40 // PSC 0 Autolock + PCNF0_PLOCK0 = 0x20 // PSC 0 Lock + PCNF0_PMODE0 = 0x18 // PSC 0 Mode + PCNF0_POP0 = 0x4 // PSC 0 Output Polarity + PCNF0_PCLKSEL0 = 0x2 // PSC 0 Input Clock Select + + // OCR0RBL: Output Compare 0 RB Register + + // OCR0RBH: Output Compare 0 RB Register + OCR0RB_OCR0RB = 0xffff // Output Compare RB + + // OCR0SBL: Output Compare 0 SB Register + + // OCR0SBH: Output Compare 0 SB Register + OCR0SB_OCR0SB = 0xfff // Output Compare SB + + // OCR0RAL: Output Compare 0 RA Register + + // OCR0RAH: Output Compare 0 RA Register + OCR0RA_OCR0RA = 0xfff // Output Compare RA + + // OCR0SAL: Output Compare 0 SA Register + + // OCR0SAH: Output Compare 0 SA Register + OCR0SA_OCR0SA = 0xfff // Output Compare SA + + // PSOC0: PSC0 Synchro and Output Configuration + PSOC0_PSYNC0 = 0x30 // Synchronization Out for ADC Selection + PSOC0_POEN0B = 0x4 // PSCOUT01 Output Enable + PSOC0_POEN0A = 0x1 // PSCOUT00 Output Enable + + // PIM0: PSC0 Interrupt Mask Register + PIM0_PSEIE0 = 0x20 // PSC 0 Synchro Error Interrupt Enable + PIM0_PEVE0B = 0x10 // External Event B Interrupt Enable + PIM0_PEVE0A = 0x8 // External Event A Interrupt Enable + PIM0_PEOPE0 = 0x1 // End of Cycle Interrupt Enable + + // PIFR0: PSC0 Interrupt Flag Register + PIFR0_POAC0B = 0x80 // PSC 0 Output A Activity + PIFR0_POAC0A = 0x40 // PSC 0 Output A Activity + PIFR0_PSEI0 = 0x20 // PSC 0 Synchro Error Interrupt + PIFR0_PEV0B = 0x10 // External Event B Interrupt + PIFR0_PEV0A = 0x8 // External Event A Interrupt + PIFR0_PRN0 = 0x6 // Ramp Number + PIFR0_PEOP0 = 0x1 // End of PSC0 Interrupt + + // PICR1L: PSC 1 Input Capture Register + + // PICR1H: PSC 1 Input Capture Register + PICR1_PCST1 = 0x8000 // PSC 1 Input Capture Software Trig + PICR1_PICR1 = 0xfff // PSC 1 Input Capture Bytes + + // PFRC1B: PSC 1 Input B Control + PFRC1B_PCAE1B = 0x80 // PSC 1 Capture Enable Input Part B + PFRC1B_PISEL1B = 0x40 // PSC 1 Input Select for Part B + PFRC1B_PELEV1B = 0x20 // PSC 1 Edge Level Selector on Input Part B + PFRC1B_PFLTE1B = 0x10 // PSC 1 Filter Enable on Input Part B + PFRC1B_PRFM1B = 0xf // PSC 1 Retrigger and Fault Mode for Part B + + // PFRC1A: PSC 1 Input B Control + PFRC1A_PCAE1A = 0x80 // PSC 1 Capture Enable Input Part A + PFRC1A_PISEL1A = 0x40 // PSC 1 Input Select for Part A + PFRC1A_PELEV1A = 0x20 // PSC 1 Edge Level Selector on Input Part A + PFRC1A_PFLTE1A = 0x10 // PSC 1 Filter Enable on Input Part A + PFRC1A_PRFM1A = 0xf // PSC 1 Retrigger and Fault Mode for Part A + + // PCTL1: PSC 1 Control Register + PCTL1_PPRE1 = 0xc0 // PSC 1 Prescaler Selects + PCTL1_PBFM1 = 0x20 // Balance Flank Width Modulation + PCTL1_PAOC1B = 0x10 // PSC 1 Asynchronous Output Control B + PCTL1_PAOC1A = 0x8 // PSC 1 Asynchronous Output Control A + PCTL1_PARUN1 = 0x4 // PSC1 Auto Run + PCTL1_PCCYC1 = 0x2 // PSC1 Complete Cycle + PCTL1_PRUN1 = 0x1 // PSC 1 Run + + // PCNF1: PSC 1 Configuration Register + PCNF1_PFIFTY1 = 0x80 // PSC 1 Fifty + PCNF1_PALOCK1 = 0x40 // PSC 1 Autolock + PCNF1_PLOCK1 = 0x20 // PSC 1 Lock + PCNF1_PMODE1 = 0x18 // PSC 1 Mode + PCNF1_POP1 = 0x4 // PSC 1 Output Polarity + PCNF1_PCLKSEL1 = 0x2 // PSC 1 Input Clock Select + + // OCR1RBL: Output Compare RB Register + + // OCR1RBH: Output Compare RB Register + OCR1RB_OCR1RB = 0xffff // Output Compare 1 RB + + // OCR1SBL: Output Compare SB Register + + // OCR1SBH: Output Compare SB Register + OCR1SB_OCR1SB = 0xfff // Output Compare 1 SB + + // OCR1RAL: Output Compare RA Register + + // OCR1RAH: Output Compare RA Register + OCR1RA_OCR1RA = 0xfff // Output Compare 1 RA + + // OCR1SAL: Output Compare SA Register + + // OCR1SAH: Output Compare SA Register + OCR1SA_OCR1SA = 0xfff // Output Compare 1 SA + + // PSOC1: PSC1 Synchro and Output Configuration + PSOC1_PSYNC1_ = 0x30 // Synchronization Out for ADC Selection + PSOC1_POEN1B = 0x4 // PSCOUT11 Output Enable + PSOC1_POEN1A = 0x1 // PSCOUT10 Output Enable + + // PIM1: PSC1 Interrupt Mask Register + PIM1_PSEIE1 = 0x20 // PSC 1 Synchro Error Interrupt Enable + PIM1_PEVE1B = 0x10 // External Event B Interrupt Enable + PIM1_PEVE1A = 0x8 // External Event A Interrupt Enable + PIM1_PEOPE1 = 0x1 // End of Cycle Interrupt Enable + + // PIFR1: PSC1 Interrupt Flag Register + PIFR1_POAC1B = 0x80 // PSC 1 Output B Activity + PIFR1_POAC1A = 0x40 // PSC 1 Output A Activity + PIFR1_PSEI1 = 0x20 // PSC 1 Synchro Error Interrupt + PIFR1_PEV1B = 0x10 // External Event B Interrupt + PIFR1_PEV1A = 0x8 // External Event A Interrupt + PIFR1_PRN1 = 0x6 // Ramp Number + PIFR1_PEOP1 = 0x1 // End of PSC1 Interrupt + + // PICR2L: PSC 2 Input Capture Register + + // PICR2H: PSC 2 Input Capture Register + PICR2_PCST2 = 0x8000 // PSC 2 Input Capture Software Trig + PICR2_PICR2 = 0xfff // PSC 2 Input Capture Bytes + + // PFRC2B: PSC 2 Input B Control + PFRC2B_PCAE2B = 0x80 // PSC 2 Capture Enable Input Part B + PFRC2B_PISEL2B = 0x40 // PSC 2 Input Select for Part B + PFRC2B_PELEV2B = 0x20 // PSC 2 Edge Level Selector on Input Part B + PFRC2B_PFLTE2B = 0x10 // PSC 2 Filter Enable on Input Part B + PFRC2B_PRFM2B = 0xf // PSC 2 Retrigger and Fault Mode for Part B + + // PFRC2A: PSC 2 Input B Control + PFRC2A_PCAE2A = 0x80 // PSC 2 Capture Enable Input Part A + PFRC2A_PISEL2A = 0x40 // PSC 2 Input Select for Part A + PFRC2A_PELEV2A = 0x20 // PSC 2 Edge Level Selector on Input Part A + PFRC2A_PFLTE2A = 0x10 // PSC 2 Filter Enable on Input Part A + PFRC2A_PRFM2A = 0xf // PSC 2 Retrigger and Fault Mode for Part A + + // PCTL2: PSC 2 Control Register + PCTL2_PPRE2 = 0xc0 // PSC 2 Prescaler Selects + PCTL2_PBFM2 = 0x20 // Balance Flank Width Modulation + PCTL2_PAOC2B = 0x10 // PSC 2 Asynchronous Output Control B + PCTL2_PAOC2A = 0x8 // PSC 2 Asynchronous Output Control A + PCTL2_PARUN2 = 0x4 // PSC2 Auto Run + PCTL2_PCCYC2 = 0x2 // PSC2 Complete Cycle + PCTL2_PRUN2 = 0x1 // PSC 2 Run + + // PCNF2: PSC 2 Configuration Register + PCNF2_PFIFTY2 = 0x80 // PSC 2 Fifty + PCNF2_PALOCK2 = 0x40 // PSC 2 Autolock + PCNF2_PLOCK2 = 0x20 // PSC 2 Lock + PCNF2_PMODE2 = 0x18 // PSC 2 Mode + PCNF2_POP2 = 0x4 // PSC 2 Output Polarity + PCNF2_PCLKSEL2 = 0x2 // PSC 2 Input Clock Select + PCNF2_POME2 = 0x1 // PSC 2 Output Matrix Enable + + // OCR2RBL: Output Compare 2 RB Register + + // OCR2RBH: Output Compare 2 RB Register + OCR2RB_OCR2RB = 0xffff // Output Compare RB + + // OCR2SBL: Output Compare 2 SB Register + + // OCR2SBH: Output Compare 2 SB Register + OCR2SB_OCR2SB = 0xfff // Output Compare SB + + // OCR2RAL: Output Compare 2 RA Register + + // OCR2RAH: Output Compare 2 RA Register + OCR2RA_OCR2RA = 0xfff // Output Compare RA + + // OCR2SAL: Output Compare 2 SA Register + + // OCR2SAH: Output Compare 2 SA Register + OCR2SA_OCR2SA = 0xfff // Output Compare SA + + // POM2: PSC 2 Output Matrix + POM2_POMV2B = 0xf0 // Output Matrix Output B Ramps + POM2_POMV2A = 0xf // Output Matrix Output A Ramps + + // PSOC2: PSC2 Synchro and Output Configuration + PSOC2_POS2 = 0xc0 // PSC 2 Output 23 Select + PSOC2_PSYNC2_ = 0x30 // Synchronization Out for ADC Selection + PSOC2_POEN2D = 0x8 // PSCOUT23 Output Enable + PSOC2_POEN2B = 0x4 // PSCOUT21 Output Enable + PSOC2_POEN2C = 0x2 // PSCOUT22 Output Enable + PSOC2_POEN2A = 0x1 // PSCOUT20 Output Enable + + // PIM2: PSC2 Interrupt Mask Register + PIM2_PSEIE2 = 0x20 // PSC 2 Synchro Error Interrupt Enable + PIM2_PEVE2B = 0x10 // External Event B Interrupt Enable + PIM2_PEVE2A = 0x8 // External Event A Interrupt Enable + PIM2_PEOPE2 = 0x1 // End of Cycle Interrupt Enable + + // PIFR2: PSC2 Interrupt Flag Register + PIFR2_POAC2B = 0x80 // PSC 2 Output A Activity + PIFR2_POAC2A = 0x40 // PSC 2 Output A Activity + PIFR2_PSEI2 = 0x20 // PSC 2 Synchro Error Interrupt + PIFR2_PEV2B = 0x10 // External Event B Interrupt + PIFR2_PEV2A = 0x8 // External Event A Interrupt + PIFR2_PRN2 = 0x6 // Ramp Number + PIFR2_PEOP2 = 0x1 // End of PSC2 Interrupt +) diff --git a/src/device/avr/at90pwm3b.ld b/src/device/avr/at90pwm3b.ld new file mode 100644 index 00000000..e0452b68 --- /dev/null +++ b/src/device/avr/at90pwm3b.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from AT90PWM3B.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_size = 0x200; +__num_isrs = 32; diff --git a/src/device/avr/at90pwm81.go b/src/device/avr/at90pwm81.go new file mode 100644 index 00000000..72929485 --- /dev/null +++ b/src/device/avr/at90pwm81.go @@ -0,0 +1,832 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from AT90PWM81.atdf, see http://packs.download.atmel.com/ + +// +build avr,at90pwm81 + +// Device information for the AT90PWM81. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "AT90PWM81" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset + IRQ_PSC2_CAPT = 1 // PSC2 Capture Event + IRQ_PSC2_EC = 2 // PSC2 End Cycle + IRQ_PSC2_EEC = 3 // PSC2 End Of Enhanced Cycle + IRQ_PSC0_CAPT = 4 // PSC0 Capture Event + IRQ_PSC0_EC = 5 // PSC0 End Cycle + IRQ_PSC0_EEC = 6 // PSC0 End Of Enhanced Cycle + IRQ_ANALOG_COMP_1 = 7 // Analog Comparator 1 + IRQ_ANALOG_COMP_2 = 8 // Analog Comparator 2 + IRQ_ANALOG_COMP_3 = 9 // Analog Comparator 3 + IRQ_INT0 = 10 // External Interrupt Request 0 + IRQ_TIMER1_CAPT = 11 // Timer/Counter1 Capture Event + IRQ_TIMER1_OVF = 12 // Timer/Counter1 Overflow + IRQ_ADC = 13 // ADC Conversion Complete + IRQ_INT1 = 14 // External Interrupt Request 1 + IRQ_SPI_STC = 15 // SPI Serial Transfer Complet + IRQ_INT2 = 16 // External Interrupt Request 2 + IRQ_WDT = 17 // Watchdog Timeout Interrupt + IRQ_EE_READY = 18 // EEPROM Ready + IRQ_SPM_READY = 19 // Store Program Memory Read + IRQ_max = 19 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // I/O Port + PORT = struct { + PORTB __reg + DDRB __reg + PINB __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + }{ + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Port E Data Register + DDRE: 0x2d, // Port E Data Direction Register + PINE: 0x2c, // Port E Input Pins + } + + // Digital-to-Analog Converter + DAC = struct { + DACL __reg + DACH __reg + DACON __reg + }{ + DACL: 0x58, // DAC Data Register + DACH: 0x58, // DAC Data Register + DACON: 0x76, // DAC Control Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x37, // SPI Control Register + SPSR: 0x38, // SPI Status Register + SPDR: 0x56, // SPI Data Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x82, // Watchdog Timer Control Register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + }{ + EICRA: 0x89, // External Interrupt Control Register A + EIMSK: 0x41, // External Interrupt Mask Register + EIFR: 0x40, // External Interrupt Flag Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + ADCSRB __reg + DIDR0 __reg + DIDR1 __reg + AMP0CSR __reg + }{ + ADMUX: 0x28, // The ADC multiplexer Selection Register + ADCSRA: 0x26, // The ADC Control and Status register + ADCL: 0x4c, // ADC Data Register Bytes + ADCH: 0x4c, // ADC Data Register Bytes + ADCSRB: 0x27, // ADC Control and Status Register B + DIDR0: 0x77, // Digital Input Disable Register 0 + DIDR1: 0x78, // Digital Input Disable Register 1 + AMP0CSR: 0x79, + } + + // Analog Comparator + AC = struct { + AC3CON __reg + AC1CON __reg + AC2CON __reg + ACSR __reg + AC3ECON __reg + AC2ECON __reg + AC1ECON __reg + }{ + AC3CON: 0x7f, // Analog Comparator3 Control Register + AC1CON: 0x7d, // Analog Comparator 1 Control Register + AC2CON: 0x7e, // Analog Comparator 2 Control Register + ACSR: 0x20, // Analog Comparator Status Register + AC3ECON: 0x7c, + AC2ECON: 0x7b, + AC1ECON: 0x7a, + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + MCUCR __reg + MCUSR __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PLLCSR __reg + PRR __reg + CLKCSR __reg + CLKSELR __reg + BGCCR __reg + BGCRR __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + OSCCAL: 0x88, // Oscillator Calibration Value + CLKPR: 0x83, + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x3b, // General Purpose IO Register 2 + GPIOR1: 0x3a, // General Purpose IO Register 1 + GPIOR0: 0x39, // General Purpose IO Register 0 + PLLCSR: 0x87, // PLL Control And Status Register + PRR: 0x86, // Power Reduction Register + CLKCSR: 0x84, + CLKSELR: 0x85, + BGCCR: 0x81, // BandGap Current Calibration Register + BGCRR: 0x80, // BandGap Resistor Calibration Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x3e, // EEPROM Read/Write Access Bytes + EEARH: 0x3e, // EEPROM Read/Write Access Bytes + EEDR: 0x3d, // EEPROM Data Register + EECR: 0x3c, // EEPROM Control Register + } + + // Power Stage Controller + PSC = struct { + PICR0L __reg + PICR0H __reg + PFRC0B __reg + PFRC0A __reg + PCTL0 __reg + PCNF0 __reg + OCR0RBL __reg + OCR0RBH __reg + OCR0SBL __reg + OCR0SBH __reg + OCR0RAL __reg + OCR0RAH __reg + OCR0SAL __reg + OCR0SAH __reg + PSOC0 __reg + PIM0 __reg + PIFR0 __reg + PICR2L __reg + PICR2H __reg + PFRC2B __reg + PFRC2A __reg + PCTL2 __reg + PCNF2 __reg + PCNFE2 __reg + OCR2RBL __reg + OCR2RBH __reg + OCR2SBL __reg + OCR2SBH __reg + OCR2RAL __reg + OCR2RAH __reg + OCR2SAL __reg + OCR2SAH __reg + POM2 __reg + PSOC2 __reg + PIM2 __reg + PIFR2 __reg + PASDLY2 __reg + }{ + PICR0L: 0x68, // PSC 0 Input Capture Register + PICR0H: 0x68, // PSC 0 Input Capture Register + PFRC0B: 0x63, // PSC 0 Input B Control + PFRC0A: 0x62, // PSC 0 Input A Control + PCTL0: 0x32, // PSC 0 Control Register + PCNF0: 0x31, // PSC 0 Configuration Register + OCR0RBL: 0x44, // Output Compare RB Register + OCR0RBH: 0x44, // Output Compare RB Register + OCR0SBL: 0x42, // Output Compare SB Register + OCR0SBH: 0x42, // Output Compare SB Register + OCR0RAL: 0x4a, // Output Compare RA Register + OCR0RAH: 0x4a, // Output Compare RA Register + OCR0SAL: 0x60, // Output Compare SA Register + OCR0SAH: 0x60, // Output Compare SA Register + PSOC0: 0x6a, // PSC0 Synchro and Output Configuration + PIM0: 0x2f, // PSC0 Interrupt Mask Register + PIFR0: 0x30, // PSC0 Interrupt Flag Register + PICR2L: 0x6c, // PSC 2 Input Capture Register + PICR2H: 0x6c, // PSC 2 Input Capture Register + PFRC2B: 0x67, // PSC 2 Input B Control + PFRC2A: 0x66, // PSC 2 Input B Control + PCTL2: 0x36, // PSC 2 Control Register + PCNF2: 0x35, // PSC 2 Configuration Register + PCNFE2: 0x70, // PSC 2 Enhanced Configuration Register + OCR2RBL: 0x48, // Output Compare RB Register + OCR2RBH: 0x48, // Output Compare RB Register + OCR2SBL: 0x46, // Output Compare SB Register + OCR2SBH: 0x46, // Output Compare SB Register + OCR2RAL: 0x4e, // Output Compare RA Register + OCR2RAH: 0x4e, // Output Compare RA Register + OCR2SAL: 0x64, // Output Compare SA Register + OCR2SAH: 0x64, // Output Compare SA Register + POM2: 0x6f, // PSC 2 Output Matrix + PSOC2: 0x6e, // PSC2 Synchro and Output Configuration + PIM2: 0x33, // PSC2 Interrupt Mask Register + PIFR2: 0x34, // PSC2 Interrupt Flag Register + PASDLY2: 0x71, // Analog Synchronization Delay Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1B __reg + TCNT1L __reg + TCNT1H __reg + ICR1L __reg + ICR1H __reg + }{ + TIMSK1: 0x21, // Timer/Counter Interrupt Mask Register + TIFR1: 0x22, // Timer/Counter Interrupt Flag register + TCCR1B: 0x8a, // Timer/Counter1 Control Register B + TCNT1L: 0x5a, // Timer/Counter1 Bytes + TCNT1H: 0x5a, // Timer/Counter1 Bytes + ICR1L: 0x8c, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x8c, // Timer/Counter1 Input Capture Register Bytes + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_PSC2RB = 0x80 // PSC2 Reset Behavior + EXTENDED_PSC2RBA = 0x40 // PSC2 Reset Behavior for 22 and 23 + EXTENDED_PSC0RB = 0x20 // PSC0 Reset Behavior + EXTENDED_PSCRV = 0x10 // PSC Reset Value + EXTENDED_PSCINRB = 0x8 // PSC2 and PSC0 input Reset Behavior + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector Trigger Level + + // HIGH + HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PE0 as I/O pin) + HIGH_DWEN = 0x40 // Debug Wire enable + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watch-dog Timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Select Reset Vector + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTD1 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for DAC: Digital-to-Analog Converter +const ( + // DACL: DAC Data Register + + // DACH: DAC Data Register + DAC_DACH = 0x3ff // DAC Data Register Bits + + // DACON: DAC Control Register + DACON_DAATE = 0x80 // DAC Auto Trigger Enable Bit + DACON_DATS = 0x70 // DAC Trigger Selection Bits + DACON_DALA = 0x4 // DAC Left Adjust + DACON_DAEN = 0x1 // DAC Enable Bit +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPDR: SPI Data Register + SPDR_SPD = 0xff // SPI Data bits +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0x7 // External Interrupt Request 2 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0x7 // External Interrupt Flags +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0xf // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCL: ADC Data Register Bytes + + // ADCH: ADC Data Register Bytes + ADC_ADC = 0xffff // ADC Data Register + + // ADCSRB: ADC Control and Status Register B + ADCSRB_ADHSM = 0x80 // ADC High Speed Mode + ADCSRB_ADNCDIS = 0x40 // ADC Noise Canceller Disable + ADCSRB_ADSSEN = 0x10 // ADC Single Shot Enable on PSC's Synchronisation Signals + ADCSRB_ADTS = 0xf // ADC Auto Trigger Sources + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC8D = 0x80 // ADC8 Digital input Disable + DIDR0_ADC7D = 0x40 // ADC7 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable + + // DIDR1: Digital Input Disable Register 1 + DIDR1_ACMP1MD = 0x8 + DIDR1_AMP0PD = 0x4 + DIDR1_ADC10D = 0x2 // ADC10 Digital input Disable + DIDR1_ADC9D = 0x1 // ADC9 Digital input Disable + + // AMP0CSR + AMP0CSR_AMP0EN = 0x80 + AMP0CSR_AMP0IS = 0x40 + AMP0CSR_AMP0G = 0x30 + AMP0CSR_AMP0GS = 0x8 + AMP0CSR_AMP0TS = 0x3 +) + +// Bitfields for AC: Analog Comparator +const ( + // AC3CON: Analog Comparator3 Control Register + AC3CON_AC3EN = 0x80 // Analog Comparator3 Enable Bit + AC3CON_AC3IE = 0x40 // Analog Comparator 3 Interrupt Enable Bit + AC3CON_AC3IS = 0x30 // Analog Comparator 3 Interrupt Select Bit + AC3CON_AC3OEA = 0x8 // Analog Comparator 3 Alternate Output Enable + AC3CON_AC3M = 0x7 // Analog Comparator 3 Multiplexer Register + + // AC1CON: Analog Comparator 1 Control Register + AC1CON_AC1EN = 0x80 // Analog Comparator 1 Enable Bit + AC1CON_AC1IE = 0x40 // Analog Comparator 1 Interrupt Enable Bit + AC1CON_AC1IS = 0x30 // Analog Comparator 1 Interrupt Select Bit + AC1CON_AC1M = 0x7 // Analog Comparator 1 Multiplexer Register + + // AC2CON: Analog Comparator 2 Control Register + AC2CON_AC2EN = 0x80 // Analog Comparator 2 Enable Bit + AC2CON_AC2IE = 0x40 // Analog Comparator 2 Interrupt Enable Bit + AC2CON_AC2IS = 0x30 // Analog Comparator 2 Interrupt Select Bit + AC2CON_AC2M = 0x7 // Analog Comparator 2 Multiplexer Register + + // ACSR: Analog Comparator Status Register + ACSR_AC3IF = 0x80 // Analog Comparator 3 Interrupt Flag Bit + ACSR_AC2IF = 0x40 // Analog Comparator 2 Interrupt Flag Bit + ACSR_AC1IF = 0x20 // Analog Comparator 1 Interrupt Flag Bit + ACSR_AC3O = 0x8 // Analog Comparator 3 Output Bit + ACSR_AC2O = 0x4 // Analog Comparator 2 Output Bit + ACSR_AC1O = 0x2 // Analog Comparator 1 Output Bit + + // AC3ECON + AC3ECON_AC3OI = 0x20 // Analog Comparator Ouput Invert + AC3ECON_AC3OE = 0x10 // Analog Comparator Ouput Enable + AC3ECON_AC3H = 0x7 // Analog Comparator Hysteresis Select + + // AC2ECON + AC2ECON_AC2OI = 0x20 // Analog Comparator Ouput Invert + AC2ECON_AC2OE = 0x10 // Analog Comparator Ouput Enable + AC2ECON_AC2H = 0x7 // Analog Comparator Hysteresis Select + + // AC1ECON + AC1ECON_AC1OI = 0x20 // Analog Comparator Ouput Invert + AC1ECON_AC1OE = 0x10 // Analog Comparator Ouput Enable + AC1ECON_AC1ICE = 0x8 // Analog Comparator Interrupt Capture Enable + AC1ECON_AC1H = 0x7 // Analog Comparator Hysteresis Select +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // MCUCR: MCU Control Register + MCUCR_PUD = 0x10 // Pull-up disable + MCUCR_RSTDIS = 0x8 // Reset Pin Disable + MCUCR_CKRC81 = 0x4 // Frequency Selection of the Calibrated RC Oscillator + MCUCR_IVSEL = 0x2 // Interrupt Vector Select + MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable + + // MCUSR: MCU Status Register + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BORF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 + + // PLLCSR: PLL Control And Status Register + PLLCSR_PLLF = 0x3c + PLLCSR_PLLE = 0x2 // PLL Enable + PLLCSR_PLOCK = 0x1 // PLL Lock Detector + + // PRR: Power Reduction Register + PRR_PRPSC2 = 0x80 // Power Reduction PSC2 + PRR_PRPSCR = 0x20 // Power Reduction PSC0 + PRR_PRTIM1 = 0x10 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRADC = 0x1 // Power Reduction ADC + + // CLKCSR + CLKCSR_CLKCCE = 0x80 // Clock Control Change Enable + CLKCSR_CLKRDY = 0x10 // Clock Ready Flag + CLKCSR_CLKC = 0xf // Clock Control + + // CLKSELR + CLKSELR_COUT = 0x40 // Clock OUT + CLKSELR_CSUT = 0x30 // Clock Start up Time + CLKSELR_CKSEL = 0xf // Clock Source Select + + // BGCCR: BandGap Current Calibration Register + BGCCR_BGCC = 0xf + + // BGCRR: BandGap Resistor Calibration Register + BGCRR_BGCR = 0xf +) + +// Bitfields for EEPROM: EEPROM +const ( + // EEARL: EEPROM Read/Write Access Bytes + + // EEARH: EEPROM Read/Write Access Bytes + EEAR_EEAR = 0x1ff // EEPROM Address bytes + + // EEDR: EEPROM Data Register + EEDR_EEDR = 0xff // EEPROM Data bits + + // EECR: EEPROM Control Register + EECR_NVMBSY = 0x80 // None Volatile Busy Memory Busy + EECR_EEPAGE = 0x40 // EEPROM Page Access + EECR_EEPM = 0x30 // EEPROM Programming Mode + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for PSC: Power Stage Controller +const ( + // PICR0L: PSC 0 Input Capture Register + + // PICR0H: PSC 0 Input Capture Register + PICR0_PCST0 = 0x8000 // PSC 0 Capture Software Trigger Bit + PICR0_PICR0 = 0xfff // PSC 0 Input Capture Bytes + + // PFRC0B: PSC 0 Input B Control + PFRC0B_PCAE0B = 0x80 // PSC 0 Capture Enable Input Part B + PFRC0B_PISEL0B = 0x40 // PSC 0 Input Select for Part B + PFRC0B_PELEV0B = 0x20 // PSC 0 Edge Level Selector on Input Part B + PFRC0B_PFLTE0B = 0x10 // PSC 0 Filter Enable on Input Part B + PFRC0B_PRFM0B = 0xf // PSC 0 Retrigger and Fault Mode for Part B + + // PFRC0A: PSC 0 Input A Control + PFRC0A_PCAE0A = 0x80 // PSC 0 Capture Enable Input Part A + PFRC0A_PISEL0A = 0x40 // PSC 0 Input Select for Part A + PFRC0A_PELEV0A = 0x20 // PSC 0 Edge Level Selector on Input Part A + PFRC0A_PFLTE0A = 0x10 // PSC 0 Filter Enable on Input Part A + PFRC0A_PRFM0A = 0xf // PSC 0 Retrigger and Fault Mode for Part A + + // PCTL0: PSC 0 Control Register + PCTL0_PPRE0 = 0xc0 // PSC 0 Prescaler Selects + PCTL0_PBFM0 = 0x24 // PSC 0 Balance Flank Width Modulation + PCTL0_PAOC0B = 0x10 // PSC 0 Asynchronous Output Control B + PCTL0_PAOC0A = 0x8 // PSC 0 Asynchronous Output Control A + PCTL0_PCCYC0 = 0x2 // PSC0 Complete Cycle + PCTL0_PRUN0 = 0x1 // PSC 0 Run + + // PCNF0: PSC 0 Configuration Register + PCNF0_PFIFTY0 = 0x80 // PSC 0 Fifty + PCNF0_PALOCK0 = 0x40 // PSC 0 Autolock + PCNF0_PLOCK0 = 0x20 // PSC 0 Lock + PCNF0_PMODE0 = 0x18 // PSC 0 Mode + PCNF0_POP0 = 0x4 // PSC 0 Output Polarity + PCNF0_PCLKSEL0 = 0x2 // PSC 0 Input Clock Select + + // OCR0RBL: Output Compare RB Register + + // OCR0RBH: Output Compare RB Register + OCR0RB_OCR0RB = 0xffff // Output Compare 0 RB + + // OCR0SBL: Output Compare SB Register + + // OCR0SBH: Output Compare SB Register + OCR0SB_OCR0SB = 0xfff // Output Compare 0 SB + + // OCR0RAL: Output Compare RA Register + + // OCR0RAH: Output Compare RA Register + OCR0RA_OCR0RA = 0xfff // Output Compare 0 RA + + // OCR0SAL: Output Compare SA Register + + // OCR0SAH: Output Compare SA Register + OCR0SA_OCR0SA = 0xfff // Output Compare 0 SA + + // PSOC0: PSC0 Synchro and Output Configuration + PSOC0_PISEL0A1 = 0x80 // PSC Input Select + PSOC0_PISEL0B1 = 0x40 // PSC Input Select + PSOC0_PSYNC0 = 0x30 // Synchronisation out for ADC selection + PSOC0_POEN0B = 0x4 // PSCOUT01 Output Enable + PSOC0_POEN0A = 0x1 // PSCOUT00 Output Enable + + // PIM0: PSC0 Interrupt Mask Register + PIM0_PEVE0B = 0x10 // External Event B Interrupt Enable + PIM0_PEVE0A = 0x8 // External Event A Interrupt Enable + PIM0_PEOEPE0 = 0x2 // End of Enhanced Cycle Enable + PIM0_PEOPE0 = 0x1 // End of Cycle Interrupt Enable + + // PIFR0: PSC0 Interrupt Flag Register + PIFR0_POAC0B = 0x80 // PSC 0 Output A Activity + PIFR0_POAC0A = 0x40 // PSC 0 Output A Activity + PIFR0_PEV0B = 0x10 // External Event B Interrupt + PIFR0_PEV0A = 0x8 // External Event A Interrupt + PIFR0_PRN0 = 0x6 // Ramp Number + PIFR0_PEOP0 = 0x1 // End of PSC0 Interrupt + + // PICR2L: PSC 2 Input Capture Register + + // PICR2H: PSC 2 Input Capture Register + PICR2_PCST2 = 0x8000 // PSC 2 Capture Software Trigger Bit + PICR2_PICR2 = 0xfff // PSC 2 Input Capture Bytes + + // PFRC2B: PSC 2 Input B Control + PFRC2B_PCAE2B = 0x80 // PSC 2 Capture Enable Input Part B + PFRC2B_PISEL2B = 0x40 // PSC 2 Input Select for Part B + PFRC2B_PELEV2B = 0x20 // PSC 2 Edge Level Selector on Input Part B + PFRC2B_PFLTE2B = 0x10 // PSC 2 Filter Enable on Input Part B + PFRC2B_PRFM2B = 0xf // PSC 2 Retrigger and Fault Mode for Part B + + // PFRC2A: PSC 2 Input B Control + PFRC2A_PCAE2A = 0x80 // PSC 2 Capture Enable Input Part A + PFRC2A_PISEL2A = 0x40 // PSC 2 Input Select for Part A + PFRC2A_PELEV2A = 0x20 // PSC 2 Edge Level Selector on Input Part A + PFRC2A_PFLTE2A = 0x10 // PSC 2 Filter Enable on Input Part A + PFRC2A_PRFM2A = 0xf // PSC 2 Retrigger and Fault Mode for Part A + + // PCTL2: PSC 2 Control Register + PCTL2_PPRE2 = 0xc0 // PSC 2 Prescaler Selects + PCTL2_PBFM2 = 0x20 // Balance Flank Width Modulation + PCTL2_PAOC2B = 0x10 // PSC 2 Asynchronous Output Control B + PCTL2_PAOC2A = 0x8 // PSC 2 Asynchronous Output Control A + PCTL2_PARUN2 = 0x4 // PSC2 Auto Run + PCTL2_PCCYC2 = 0x2 // PSC2 Complete Cycle + PCTL2_PRUN2 = 0x1 // PSC 2 Run + + // PCNF2: PSC 2 Configuration Register + PCNF2_PFIFTY2 = 0x80 // PSC 2 Fifty + PCNF2_PALOCK2 = 0x40 // PSC 2 Autolock + PCNF2_PLOCK2 = 0x20 // PSC 2 Lock + PCNF2_PMODE2 = 0x18 // PSC 2 Mode + PCNF2_POP2 = 0x4 // PSC 2 Output Polarity + PCNF2_PCLKSEL2 = 0x2 // PSC 2 Input Clock Select + PCNF2_POME2 = 0x1 // PSC 2 Output Matrix Enable + + // PCNFE2: PSC 2 Enhanced Configuration Register + PCNFE2_PASDLK2 = 0xe0 + PCNFE2_PBFM21 = 0x10 + PCNFE2_PELEV2A1 = 0x8 + PCNFE2_PELEV2B1 = 0x4 + PCNFE2_PISEL2A1 = 0x2 + PCNFE2_PISEL2B1 = 0x1 + + // OCR2RBL: Output Compare RB Register + + // OCR2RBH: Output Compare RB Register + OCR2RB_OCR2RB = 0xffff // Output Compare 2 RB + + // OCR2SBL: Output Compare SB Register + + // OCR2SBH: Output Compare SB Register + OCR2SB_OCR2SB = 0xfff // Output Compare 2 SB + + // OCR2RAL: Output Compare RA Register + + // OCR2RAH: Output Compare RA Register + OCR2RA_OCR2RA = 0xfff // Output Compare 2 RA + + // OCR2SAL: Output Compare SA Register + + // OCR2SAH: Output Compare SA Register + OCR2SA_OCR2SA = 0xfff // Output Compare 2 SA + + // POM2: PSC 2 Output Matrix + POM2_POMV2B = 0xf0 // Output Matrix Output B Ramps + POM2_POMV2A = 0xf // Output Matrix Output A Ramps + + // PSOC2: PSC2 Synchro and Output Configuration + PSOC2_POS2 = 0xc0 // PSC 2 Output 23 Select + PSOC2_PSYNC2 = 0x30 // Synchronization Out for ADC Selection + PSOC2_POEN2D = 0x8 // PSCOUT23 Output Enable + PSOC2_POEN2B = 0x4 // PSCOUT21 Output Enable + PSOC2_POEN2C = 0x2 // PSCOUT22 Output Enable + PSOC2_POEN2A = 0x1 // PSCOUT20 Output Enable + + // PIM2: PSC2 Interrupt Mask Register + PIM2_PSEIE2 = 0x20 // PSC 2 Synchro Error Interrupt Enable + PIM2_PEVE2B = 0x10 // External Event B Interrupt Enable + PIM2_PEVE2A = 0x8 // External Event A Interrupt Enable + PIM2_PEOEPE2 = 0x2 // End of Enhanced Cycle Interrupt Enable + PIM2_PEOPE2 = 0x1 // End of Cycle Interrupt Enable + + // PIFR2: PSC2 Interrupt Flag Register + PIFR2_POAC2B = 0x80 // PSC 2 Output A Activity + PIFR2_POAC2A = 0x40 // PSC 2 Output A Activity + PIFR2_PSEI2 = 0x20 // PSC 2 Synchro Error Interrupt + PIFR2_PEV2B = 0x10 // External Event B Interrupt + PIFR2_PEV2A = 0x8 // External Event A Interrupt + PIFR2_PRN2 = 0x6 // Ramp Number + PIFR2_PEOP2 = 0x1 // End of PSC2 Interrupt + + // PASDLY2: Analog Synchronization Delay Register + PASDLY2_PASDLY2 = 0xff // Analog Synchronization Delay bits +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TIMSK1: Timer/Counter Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM13 = 0x10 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCNT1L: Timer/Counter1 Bytes + + // TCNT1H: Timer/Counter1 Bytes + TCNT1_TCNT1 = 0xffff // Timer/Counter 1 bits + + // ICR1L: Timer/Counter1 Input Capture Register Bytes + + // ICR1H: Timer/Counter1 Input Capture Register Bytes + ICR1_ICR1 = 0xffff // Timer/Counter1 Input Capture bits +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) diff --git a/src/device/avr/at90pwm81.ld b/src/device/avr/at90pwm81.ld new file mode 100644 index 00000000..104edfb3 --- /dev/null +++ b/src/device/avr/at90pwm81.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from AT90PWM81.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_size = 0x100; +__num_isrs = 20; diff --git a/src/device/avr/at90usb1286.go b/src/device/avr/at90usb1286.go new file mode 100644 index 00000000..858db480 --- /dev/null +++ b/src/device/avr/at90usb1286.go @@ -0,0 +1,952 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from AT90USB1286.atdf, see http://packs.download.atmel.com/ + +// +build avr,at90usb1286 + +// Device information for the AT90USB1286. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "AT90USB1286" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_INT3 = 4 // External Interrupt Request 3 + IRQ_INT4 = 5 // External Interrupt Request 4 + IRQ_INT5 = 6 // External Interrupt Request 5 + IRQ_INT6 = 7 // External Interrupt Request 6 + IRQ_INT7 = 8 // External Interrupt Request 7 + IRQ_PCINT0 = 9 // Pin Change Interrupt Request 0 + IRQ_USB_GEN = 10 // USB General Interrupt Request + IRQ_USB_COM = 11 // USB Endpoint/Pipe Interrupt Communication Request + IRQ_WDT = 12 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 13 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 14 // Timer/Counter2 Compare Match B + IRQ_TIMER2_OVF = 15 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 16 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 17 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 18 // Timer/Counter1 Compare Match B + IRQ_TIMER1_COMPC = 19 // Timer/Counter1 Compare Match C + IRQ_TIMER1_OVF = 20 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 21 // Timer/Counter0 Compare Match A + IRQ_TIMER0_COMPB = 22 // Timer/Counter0 Compare Match B + IRQ_TIMER0_OVF = 23 // Timer/Counter0 Overflow + IRQ_SPI_STC = 24 // SPI Serial Transfer Complete + IRQ_USART1_RX = 25 // USART1, Rx Complete + IRQ_USART1_UDRE = 26 // USART1 Data register Empty + IRQ_USART1_TX = 27 // USART1, Tx Complete + IRQ_ANALOG_COMP = 28 // Analog Comparator + IRQ_ADC = 29 // ADC Conversion Complete + IRQ_EE_READY = 30 // EEPROM Ready + IRQ_TIMER3_CAPT = 31 // Timer/Counter3 Capture Event + IRQ_TIMER3_COMPA = 32 // Timer/Counter3 Compare Match A + IRQ_TIMER3_COMPB = 33 // Timer/Counter3 Compare Match B + IRQ_TIMER3_COMPC = 34 // Timer/Counter3 Compare Match C + IRQ_TIMER3_OVF = 35 // Timer/Counter3 Overflow + IRQ_TWI = 36 // 2-wire Serial Interface + IRQ_SPM_READY = 37 // Store Program Memory Read + IRQ_max = 37 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + XMCRA __reg + XMCRB __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + EIND __reg + RAMPZ __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PRR1 __reg + PRR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + XMCRA: 0x74, // External Memory Control Register A + XMCRB: 0x75, // External Memory Control Register B + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, + SMCR: 0x53, // Sleep Mode Control Register + EIND: 0x5c, // Extended Indirect Register + RAMPZ: 0x5b, // RAM Page Z Select Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PRR1: 0x65, // Power Reduction Register1 + PRR0: 0x64, // Power Reduction Register0 + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // USART + USART = struct { + UDR1 __reg + UCSR1A __reg + UCSR1B __reg + UCSR1C __reg + UBRR1L __reg + UBRR1H __reg + }{ + UDR1: 0xce, // USART I/O Data Register + UCSR1A: 0xc8, // USART Control and Status Register A + UCSR1B: 0xc9, // USART Control and Status Register B + UCSR1C: 0xca, // USART Control and Status Register C + UBRR1L: 0xcc, // USART Baud Rate Register Bytes + UBRR1H: 0xcc, // USART Baud Rate Register Bytes + } + + // USB Device Registers + USB_DEVICE = struct { + UEINT __reg + UEBCHX __reg + UEBCLX __reg + UEDATX __reg + UEIENX __reg + UESTA1X __reg + UESTA0X __reg + UECFG1X __reg + UECFG0X __reg + UECONX __reg + UERST __reg + UENUM __reg + UEINTX __reg + UDMFN __reg + UDFNUML __reg + UDFNUMH __reg + UDADDR __reg + UDIEN __reg + UDINT __reg + UDCON __reg + }{ + UEINT: 0xf4, + UEBCHX: 0xf3, + UEBCLX: 0xf2, + UEDATX: 0xf1, + UEIENX: 0xf0, + UESTA1X: 0xef, + UESTA0X: 0xee, + UECFG1X: 0xed, + UECFG0X: 0xec, + UECONX: 0xeb, + UERST: 0xea, + UENUM: 0xe9, + UEINTX: 0xe8, + UDMFN: 0xe6, + UDFNUML: 0xe4, + UDFNUMH: 0xe4, + UDADDR: 0xe3, + UDIEN: 0xe2, + UDINT: 0xe1, + UDCON: 0xe0, + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Low Bytes + EEARH: 0x41, // EEPROM Address Register Low Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR3A __reg + TCCR3B __reg + TCCR3C __reg + TCNT3L __reg + TCNT3H __reg + OCR3AL __reg + OCR3AH __reg + OCR3BL __reg + OCR3BH __reg + OCR3CL __reg + OCR3CH __reg + ICR3L __reg + ICR3H __reg + TIMSK3 __reg + TIFR3 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + OCR1CL __reg + OCR1CH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR3A: 0x90, // Timer/Counter3 Control Register A + TCCR3B: 0x91, // Timer/Counter3 Control Register B + TCCR3C: 0x92, // Timer/Counter 3 Control Register C + TCNT3L: 0x94, // Timer/Counter3 Bytes + TCNT3H: 0x94, // Timer/Counter3 Bytes + OCR3AL: 0x98, // Timer/Counter3 Output Compare Register A Bytes + OCR3AH: 0x98, // Timer/Counter3 Output Compare Register A Bytes + OCR3BL: 0x9a, // Timer/Counter3 Output Compare Register B Bytes + OCR3BH: 0x9a, // Timer/Counter3 Output Compare Register B Bytes + OCR3CL: 0x9c, // Timer/Counter3 Output Compare Register B Bytes + OCR3CH: 0x9c, // Timer/Counter3 Output Compare Register B Bytes + ICR3L: 0x96, // Timer/Counter3 Input Capture Register Bytes + ICR3H: 0x96, // Timer/Counter3 Input Capture Register Bytes + TIMSK3: 0x71, // Timer/Counter3 Interrupt Mask Register + TIFR3: 0x38, // Timer/Counter3 Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1CL: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + OCR1CH: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EICRB __reg + EIMSK __reg + EIFR __reg + PCMSK0 __reg + PCIFR __reg + PCICR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EICRB: 0x6a, // External Interrupt Control Register B + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 1 + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, + } + + // Phase Locked Loop + PLL = struct { + PLLCSR __reg + }{ + PLLCSR: 0x49, // PLL Status and Control register + } + + // USB Controller + USB_GLOBAL = struct { + USBINT __reg + USBSTA __reg + USBCON __reg + UHWCON __reg + }{ + USBINT: 0xda, + USBSTA: 0xd9, + USBCON: 0xd8, // USB General Control Register + UHWCON: 0xd7, // USB Hardware Configuration Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level + EXTENDED_HWBE = 0x8 // Hardware Boot Enable + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTC7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // XMCRA: External Memory Control Register A + XMCRA_SRE = 0x80 // External SRAM Enable + XMCRA_SRL = 0x70 // Wait state page limit + XMCRA_SRW1 = 0xc // Wait state select bit upper page + XMCRA_SRW0 = 0x3 // Wait state select bit lower page + + // XMCRB: External Memory Control Register B + XMCRB_XMBK = 0x80 // External Memory Bus Keeper Enable + XMCRB_XMM = 0x7 // External Memory High Mask + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 + + // PRR1: Power Reduction Register1 + PRR1_PRUSB = 0x80 // Power Reduction USB + PRR1_PRTIM3 = 0x8 // Power Reduction Timer/Counter3 + PRR1_PRUSART1 = 0x1 // Power Reduction USART1 + + // PRR0: Power Reduction Register0 + PRR0_PRTWI = 0x80 // Power Reduction TWI + PRR0_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR0_PRADC = 0x1 // Power Reduction ADC +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for USART: USART +const ( + // UCSR1A: USART Control and Status Register A + UCSR1A_RXC1 = 0x80 // USART Receive Complete + UCSR1A_TXC1 = 0x40 // USART Transmitt Complete + UCSR1A_UDRE1 = 0x20 // USART Data Register Empty + UCSR1A_FE1 = 0x10 // Framing Error + UCSR1A_DOR1 = 0x8 // Data overRun + UCSR1A_UPE1 = 0x4 // Parity Error + UCSR1A_U2X1 = 0x2 // Double the USART transmission speed + UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode + + // UCSR1B: USART Control and Status Register B + UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable + UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable + UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable + UCSR1B_RXEN1 = 0x10 // Receiver Enable + UCSR1B_TXEN1 = 0x8 // Transmitter Enable + UCSR1B_UCSZ12 = 0x4 // Character Size + UCSR1B_RXB81 = 0x2 // Receive Data Bit 8 + UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8 + + // UCSR1C: USART Control and Status Register C + UCSR1C_UMSEL1 = 0xc0 // USART Mode Select + UCSR1C_UPM1 = 0x30 // Parity Mode Bits + UCSR1C_USBS1 = 0x8 // Stop Bit Select + UCSR1C_UCSZ1 = 0x6 // Character Size + UCSR1C_UCPOL1 = 0x1 // Clock Polarity +) + +// Bitfields for USB_DEVICE: USB Device Registers +const ( + // UEIENX + UEIENX_FLERRE = 0x80 + UEIENX_NAKINE = 0x40 + UEIENX_NAKOUTE = 0x10 + UEIENX_RXSTPE = 0x8 + UEIENX_RXOUTE = 0x4 + UEIENX_STALLEDE = 0x2 + UEIENX_TXINE = 0x1 + + // UESTA1X + UESTA1X_CTRLDIR = 0x4 + UESTA1X_CURRBK = 0x3 + + // UESTA0X + UESTA0X_CFGOK = 0x80 + UESTA0X_OVERFI = 0x40 + UESTA0X_UNDERFI = 0x20 + UESTA0X_DTSEQ = 0xc + UESTA0X_NBUSYBK = 0x3 + + // UECFG1X + UECFG1X_EPSIZE = 0x70 + UECFG1X_EPBK = 0xc + UECFG1X_ALLOC = 0x2 + + // UECFG0X + UECFG0X_EPTYPE = 0xc0 + UECFG0X_EPDIR = 0x1 + + // UECONX + UECONX_STALLRQ = 0x20 + UECONX_STALLRQC = 0x10 + UECONX_RSTDT = 0x8 + UECONX_EPEN = 0x1 + + // UERST + UERST_EPRST = 0x7f + + // UEINTX + UEINTX_FIFOCON = 0x80 + UEINTX_NAKINI = 0x40 + UEINTX_RWAL = 0x20 + UEINTX_NAKOUTI = 0x10 + UEINTX_RXSTPI = 0x8 + UEINTX_RXOUTI = 0x4 + UEINTX_STALLEDI = 0x2 + UEINTX_TXINI = 0x1 + + // UDMFN + UDMFN_FNCERR = 0x10 + + // UDADDR + UDADDR_ADDEN = 0x80 + UDADDR_UADD = 0x7f + + // UDIEN + UDIEN_UPRSME = 0x40 + UDIEN_EORSME = 0x20 + UDIEN_WAKEUPE = 0x10 + UDIEN_EORSTE = 0x8 + UDIEN_SOFE = 0x4 + UDIEN_SUSPE = 0x1 + + // UDINT + UDINT_UPRSMI = 0x40 + UDINT_EORSMI = 0x20 + UDINT_WAKEUPI = 0x10 + UDINT_EORSTI = 0x8 + UDINT_SOFI = 0x4 + UDINT_SUSPI = 0x1 + + // UDCON + UDCON_LSM = 0x4 + UDCON_RMWKUP = 0x2 + UDCON_DETACH = 0x1 +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2B = 0x4 // Output Compare Flag 2B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Output Mode bits + TCCR2A_COM2B = 0x30 // Compare Output Mode bits + TCCR2A_WGM2 = 0x3 // Waveform Genration Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy + ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR3A: Timer/Counter3 Control Register A + TCCR3A_COM3A = 0xc0 // Compare Output Mode 1A, bits + TCCR3A_COM3B = 0x30 // Compare Output Mode 3B, bits + TCCR3A_COM3C = 0xc // Compare Output Mode 3C, bits + TCCR3A_WGM3 = 0x3 // Waveform Generation Mode + + // TCCR3B: Timer/Counter3 Control Register B + TCCR3B_ICNC3 = 0x80 // Input Capture 3 Noise Canceler + TCCR3B_ICES3 = 0x40 // Input Capture 3 Edge Select + TCCR3B_WGM3 = 0x18 // Waveform Generation Mode + TCCR3B_CS3 = 0x7 // Prescaler source of Timer/Counter 3 + + // TCCR3C: Timer/Counter 3 Control Register C + TCCR3C_FOC3A = 0x80 // Force Output Compare 3A + TCCR3C_FOC3B = 0x40 // Force Output Compare 3B + TCCR3C_FOC3C = 0x20 // Force Output Compare 3C + + // TIMSK3: Timer/Counter3 Interrupt Mask Register + TIMSK3_ICIE3 = 0x20 // Timer/Counter3 Input Capture Interrupt Enable + TIMSK3_OCIE3C = 0x8 // Timer/Counter3 Output Compare C Match Interrupt Enable + TIMSK3_OCIE3B = 0x4 // Timer/Counter3 Output Compare B Match Interrupt Enable + TIMSK3_OCIE3A = 0x2 // Timer/Counter3 Output Compare A Match Interrupt Enable + TIMSK3_TOIE3 = 0x1 // Timer/Counter3 Overflow Interrupt Enable + + // TIFR3: Timer/Counter3 Interrupt Flag register + TIFR3_ICF3 = 0x20 // Input Capture Flag 3 + TIFR3_OCF3C = 0x8 // Output Compare Flag 3C + TIFR3_OCF3B = 0x4 // Output Compare Flag 3B + TIFR3_OCF3A = 0x2 // Output Compare Flag 3A + TIFR3_TOV3 = 0x1 // Timer/Counter3 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_COM1C = 0xc // Compare Output Mode 1C, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + TCCR1C_FOC1C = 0x20 // Force Output Compare 1C + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1C = 0x8 // Timer/Counter1 Output Compare C Match Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1C = 0x8 // Output Compare Flag 1C + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EICRB: External Interrupt Control Register B + EICRB_ISC7 = 0xc0 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC6 = 0x30 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC5 = 0xc // External Interrupt 7-4 Sense Control Bit + EICRB_ISC4 = 0x3 // External Interrupt 7-4 Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xff // External Interrupt Request 7 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xff // External Interrupt Flags + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF0 = 0x1 // Pin Change Interrupt Flag 0 + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE0 = 0x1 // Pin Change Interrupt Enable 0 +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register 1 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for PLL: Phase Locked Loop +const ( + // PLLCSR: PLL Status and Control register + PLLCSR_PLLP = 0x1c // PLL prescaler Bits + PLLCSR_PLLE = 0x2 // PLL Enable Bit + PLLCSR_PLOCK = 0x1 // PLL Lock Status Bit +) + +// Bitfields for USB_GLOBAL: USB Controller +const ( + // USBINT + USBINT_IDTI = 0x2 + USBINT_VBUSTI = 0x1 + + // USBSTA + USBSTA_SPEED = 0x8 + USBSTA_ID = 0x2 + USBSTA_VBUS = 0x1 + + // USBCON: USB General Control Register + USBCON_USBE = 0x80 + USBCON_HOST = 0x40 + USBCON_FRZCLK = 0x20 + USBCON_OTGPADE = 0x10 + USBCON_IDTE = 0x2 + USBCON_VBUSTE = 0x1 + + // UHWCON: USB Hardware Configuration Register + UHWCON_UIMOD = 0x80 + UHWCON_UIDE = 0x40 + UHWCON_UVCONE = 0x10 + UHWCON_UVREGE = 0x1 +) diff --git a/src/device/avr/at90usb1286.ld b/src/device/avr/at90usb1286.ld new file mode 100644 index 00000000..62df6c2f --- /dev/null +++ b/src/device/avr/at90usb1286.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from AT90USB1286.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x20000; +__ram_size = 0x2000; +__num_isrs = 38; diff --git a/src/device/avr/at90usb1287.go b/src/device/avr/at90usb1287.go new file mode 100644 index 00000000..38e3c87f --- /dev/null +++ b/src/device/avr/at90usb1287.go @@ -0,0 +1,1117 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from AT90USB1287.atdf, see http://packs.download.atmel.com/ + +// +build avr,at90usb1287 + +// Device information for the AT90USB1287. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "AT90USB1287" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_INT3 = 4 // External Interrupt Request 3 + IRQ_INT4 = 5 // External Interrupt Request 4 + IRQ_INT5 = 6 // External Interrupt Request 5 + IRQ_INT6 = 7 // External Interrupt Request 6 + IRQ_INT7 = 8 // External Interrupt Request 7 + IRQ_PCINT0 = 9 // Pin Change Interrupt Request 0 + IRQ_USB_GEN = 10 // USB General Interrupt Request + IRQ_USB_COM = 11 // USB Endpoint/Pipe Interrupt Communication Request + IRQ_WDT = 12 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 13 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 14 // Timer/Counter2 Compare Match B + IRQ_TIMER2_OVF = 15 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 16 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 17 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 18 // Timer/Counter1 Compare Match B + IRQ_TIMER1_COMPC = 19 // Timer/Counter1 Compare Match C + IRQ_TIMER1_OVF = 20 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 21 // Timer/Counter0 Compare Match A + IRQ_TIMER0_COMPB = 22 // Timer/Counter0 Compare Match B + IRQ_TIMER0_OVF = 23 // Timer/Counter0 Overflow + IRQ_SPI_STC = 24 // SPI Serial Transfer Complete + IRQ_USART1_RX = 25 // USART1, Rx Complete + IRQ_USART1_UDRE = 26 // USART1 Data register Empty + IRQ_USART1_TX = 27 // USART1, Tx Complete + IRQ_ANALOG_COMP = 28 // Analog Comparator + IRQ_ADC = 29 // ADC Conversion Complete + IRQ_EE_READY = 30 // EEPROM Ready + IRQ_TIMER3_CAPT = 31 // Timer/Counter3 Capture Event + IRQ_TIMER3_COMPA = 32 // Timer/Counter3 Compare Match A + IRQ_TIMER3_COMPB = 33 // Timer/Counter3 Compare Match B + IRQ_TIMER3_COMPC = 34 // Timer/Counter3 Compare Match C + IRQ_TIMER3_OVF = 35 // Timer/Counter3 Overflow + IRQ_TWI = 36 // 2-wire Serial Interface + IRQ_SPM_READY = 37 // Store Program Memory Read + IRQ_max = 37 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + XMCRA __reg + XMCRB __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + EIND __reg + RAMPZ __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PRR1 __reg + PRR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + XMCRA: 0x74, // External Memory Control Register A + XMCRB: 0x75, // External Memory Control Register B + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, + SMCR: 0x53, // Sleep Mode Control Register + EIND: 0x5c, // Extended Indirect Register + RAMPZ: 0x5b, // RAM Page Z Select Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PRR1: 0x65, // Power Reduction Register1 + PRR0: 0x64, // Power Reduction Register0 + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // USART + USART = struct { + UDR1 __reg + UCSR1A __reg + UCSR1B __reg + UCSR1C __reg + UBRR1L __reg + UBRR1H __reg + }{ + UDR1: 0xce, // USART I/O Data Register + UCSR1A: 0xc8, // USART Control and Status Register A + UCSR1B: 0xc9, // USART Control and Status Register B + UCSR1C: 0xca, // USART Control and Status Register C + UBRR1L: 0xcc, // USART Baud Rate Register Bytes + UBRR1H: 0xcc, // USART Baud Rate Register Bytes + } + + // USB Device Registers + USB_DEVICE = struct { + UEINT __reg + UEBCHX __reg + UEBCLX __reg + UEDATX __reg + UEIENX __reg + UESTA1X __reg + UESTA0X __reg + UECFG1X __reg + UECFG0X __reg + UECONX __reg + UERST __reg + UENUM __reg + UEINTX __reg + UDMFN __reg + UDFNUML __reg + UDFNUMH __reg + UDADDR __reg + UDIEN __reg + UDINT __reg + UDCON __reg + }{ + UEINT: 0xf4, + UEBCHX: 0xf3, + UEBCLX: 0xf2, + UEDATX: 0xf1, + UEIENX: 0xf0, + UESTA1X: 0xef, + UESTA0X: 0xee, + UECFG1X: 0xed, + UECFG0X: 0xec, + UECONX: 0xeb, + UERST: 0xea, + UENUM: 0xe9, + UEINTX: 0xe8, + UDMFN: 0xe6, + UDFNUML: 0xe4, + UDFNUMH: 0xe4, + UDADDR: 0xe3, + UDIEN: 0xe2, + UDINT: 0xe1, + UDCON: 0xe0, + } + + // USB Controller + USB_GLOBAL = struct { + OTGINT __reg + OTGIEN __reg + OTGCON __reg + OTGTCON __reg + USBINT __reg + USBSTA __reg + USBCON __reg + UHWCON __reg + }{ + OTGINT: 0xdf, + OTGIEN: 0xde, + OTGCON: 0xdd, + OTGTCON: 0xf9, + USBINT: 0xda, + USBSTA: 0xd9, + USBCON: 0xd8, // USB General Control Register + UHWCON: 0xd7, // USB Hardware Configuration Register + } + + // USB Host Registers + USB_HOST = struct { + UPERRX __reg + UPINT __reg + UPBCHX __reg + UPBCLX __reg + UPDATX __reg + UPIENX __reg + UPCFG2X __reg + UPSTAX __reg + UPCFG1X __reg + UPCFG0X __reg + UPCONX __reg + UPRST __reg + UPNUM __reg + UPINTX __reg + UPINRQX __reg + UHFLEN __reg + UHFNUML __reg + UHFNUMH __reg + UHADDR __reg + UHIEN __reg + UHINT __reg + UHCON __reg + }{ + UPERRX: 0xf5, + UPINT: 0xf8, + UPBCHX: 0xf7, + UPBCLX: 0xf6, + UPDATX: 0xaf, + UPIENX: 0xae, + UPCFG2X: 0xad, + UPSTAX: 0xac, + UPCFG1X: 0xab, + UPCFG0X: 0xaa, + UPCONX: 0xa9, + UPRST: 0xa8, + UPNUM: 0xa7, + UPINTX: 0xa6, + UPINRQX: 0xa5, + UHFLEN: 0xa4, + UHFNUML: 0xa2, + UHFNUMH: 0xa2, + UHADDR: 0xa1, + UHIEN: 0xa0, + UHINT: 0x9f, + UHCON: 0x9e, + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Low Bytes + EEARH: 0x41, // EEPROM Address Register Low Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR3A __reg + TCCR3B __reg + TCCR3C __reg + TCNT3L __reg + TCNT3H __reg + OCR3AL __reg + OCR3AH __reg + OCR3BL __reg + OCR3BH __reg + OCR3CL __reg + OCR3CH __reg + ICR3L __reg + ICR3H __reg + TIMSK3 __reg + TIFR3 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + OCR1CL __reg + OCR1CH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR3A: 0x90, // Timer/Counter3 Control Register A + TCCR3B: 0x91, // Timer/Counter3 Control Register B + TCCR3C: 0x92, // Timer/Counter 3 Control Register C + TCNT3L: 0x94, // Timer/Counter3 Bytes + TCNT3H: 0x94, // Timer/Counter3 Bytes + OCR3AL: 0x98, // Timer/Counter3 Output Compare Register A Bytes + OCR3AH: 0x98, // Timer/Counter3 Output Compare Register A Bytes + OCR3BL: 0x9a, // Timer/Counter3 Output Compare Register B Bytes + OCR3BH: 0x9a, // Timer/Counter3 Output Compare Register B Bytes + OCR3CL: 0x9c, // Timer/Counter3 Output Compare Register B Bytes + OCR3CH: 0x9c, // Timer/Counter3 Output Compare Register B Bytes + ICR3L: 0x96, // Timer/Counter3 Input Capture Register Bytes + ICR3H: 0x96, // Timer/Counter3 Input Capture Register Bytes + TIMSK3: 0x71, // Timer/Counter3 Interrupt Mask Register + TIFR3: 0x38, // Timer/Counter3 Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1CL: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + OCR1CH: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EICRB __reg + EIMSK __reg + EIFR __reg + PCMSK0 __reg + PCIFR __reg + PCICR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EICRB: 0x6a, // External Interrupt Control Register B + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 1 + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, + } + + // Phase Locked Loop + PLL = struct { + PLLCSR __reg + }{ + PLLCSR: 0x49, // PLL Status and Control register + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level + EXTENDED_HWBE = 0x8 // Hardware Boot Enable + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTC7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // XMCRA: External Memory Control Register A + XMCRA_SRE = 0x80 // External SRAM Enable + XMCRA_SRL = 0x70 // Wait state page limit + XMCRA_SRW1 = 0xc // Wait state select bit upper page + XMCRA_SRW0 = 0x3 // Wait state select bit lower page + + // XMCRB: External Memory Control Register B + XMCRB_XMBK = 0x80 // External Memory Bus Keeper Enable + XMCRB_XMM = 0x7 // External Memory High Mask + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 + + // PRR1: Power Reduction Register1 + PRR1_PRUSB = 0x80 // Power Reduction USB + PRR1_PRTIM3 = 0x8 // Power Reduction Timer/Counter3 + PRR1_PRUSART1 = 0x1 // Power Reduction USART1 + + // PRR0: Power Reduction Register0 + PRR0_PRTWI = 0x80 // Power Reduction TWI + PRR0_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR0_PRADC = 0x1 // Power Reduction ADC +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for USART: USART +const ( + // UCSR1A: USART Control and Status Register A + UCSR1A_RXC1 = 0x80 // USART Receive Complete + UCSR1A_TXC1 = 0x40 // USART Transmitt Complete + UCSR1A_UDRE1 = 0x20 // USART Data Register Empty + UCSR1A_FE1 = 0x10 // Framing Error + UCSR1A_DOR1 = 0x8 // Data overRun + UCSR1A_UPE1 = 0x4 // Parity Error + UCSR1A_U2X1 = 0x2 // Double the USART transmission speed + UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode + + // UCSR1B: USART Control and Status Register B + UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable + UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable + UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable + UCSR1B_RXEN1 = 0x10 // Receiver Enable + UCSR1B_TXEN1 = 0x8 // Transmitter Enable + UCSR1B_UCSZ12 = 0x4 // Character Size + UCSR1B_RXB81 = 0x2 // Receive Data Bit 8 + UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8 + + // UCSR1C: USART Control and Status Register C + UCSR1C_UMSEL1 = 0xc0 // USART Mode Select + UCSR1C_UPM1 = 0x30 // Parity Mode Bits + UCSR1C_USBS1 = 0x8 // Stop Bit Select + UCSR1C_UCSZ1 = 0x6 // Character Size + UCSR1C_UCPOL1 = 0x1 // Clock Polarity +) + +// Bitfields for USB_DEVICE: USB Device Registers +const ( + // UEIENX + UEIENX_FLERRE = 0x80 + UEIENX_NAKINE = 0x40 + UEIENX_NAKOUTE = 0x10 + UEIENX_RXSTPE = 0x8 + UEIENX_RXOUTE = 0x4 + UEIENX_STALLEDE = 0x2 + UEIENX_TXINE = 0x1 + + // UESTA1X + UESTA1X_CTRLDIR = 0x4 + UESTA1X_CURRBK = 0x3 + + // UESTA0X + UESTA0X_CFGOK = 0x80 + UESTA0X_OVERFI = 0x40 + UESTA0X_UNDERFI = 0x20 + UESTA0X_DTSEQ = 0xc + UESTA0X_NBUSYBK = 0x3 + + // UECFG1X + UECFG1X_EPSIZE = 0x70 + UECFG1X_EPBK = 0xc + UECFG1X_ALLOC = 0x2 + + // UECFG0X + UECFG0X_EPTYPE = 0xc0 + UECFG0X_EPDIR = 0x1 + + // UECONX + UECONX_STALLRQ = 0x20 + UECONX_STALLRQC = 0x10 + UECONX_RSTDT = 0x8 + UECONX_EPEN = 0x1 + + // UERST + UERST_EPRST = 0x7f + + // UEINTX + UEINTX_FIFOCON = 0x80 + UEINTX_NAKINI = 0x40 + UEINTX_RWAL = 0x20 + UEINTX_NAKOUTI = 0x10 + UEINTX_RXSTPI = 0x8 + UEINTX_RXOUTI = 0x4 + UEINTX_STALLEDI = 0x2 + UEINTX_TXINI = 0x1 + + // UDMFN + UDMFN_FNCERR = 0x10 + + // UDADDR + UDADDR_ADDEN = 0x80 + UDADDR_UADD = 0x7f + + // UDIEN + UDIEN_UPRSME = 0x40 + UDIEN_EORSME = 0x20 + UDIEN_WAKEUPE = 0x10 + UDIEN_EORSTE = 0x8 + UDIEN_SOFE = 0x4 + UDIEN_SUSPE = 0x1 + + // UDINT + UDINT_UPRSMI = 0x40 + UDINT_EORSMI = 0x20 + UDINT_WAKEUPI = 0x10 + UDINT_EORSTI = 0x8 + UDINT_SOFI = 0x4 + UDINT_SUSPI = 0x1 + + // UDCON + UDCON_LSM = 0x4 + UDCON_RMWKUP = 0x2 + UDCON_DETACH = 0x1 +) + +// Bitfields for USB_GLOBAL: USB Controller +const ( + // OTGINT + OTGINT_STOI = 0x20 + OTGINT_HNPERRI = 0x10 + OTGINT_ROLEEXI = 0x8 + OTGINT_BCERRI = 0x4 + OTGINT_VBERRI = 0x2 + OTGINT_SRPI = 0x1 + + // OTGIEN + OTGIEN_STOE = 0x20 + OTGIEN_HNPERRE = 0x10 + OTGIEN_ROLEEXE = 0x8 + OTGIEN_BCERRE = 0x4 + OTGIEN_VBERRE = 0x2 + OTGIEN_SRPE = 0x1 + + // OTGCON + OTGCON_HNPREQ = 0x20 + OTGCON_SRPREQ = 0x10 + OTGCON_SRPSEL = 0x8 + OTGCON_VBUSHWC = 0x4 + OTGCON_VBUSREQ = 0x2 + OTGCON_VBUSRQC = 0x1 + + // OTGTCON + OTGTCON_OTGTCON_7 = 0x80 + OTGTCON_PAGE = 0x60 + OTGTCON_VALUE_2 = 0x7 + + // USBINT + USBINT_IDTI = 0x2 + USBINT_VBUSTI = 0x1 + + // USBSTA + USBSTA_SPEED = 0x8 + USBSTA_ID = 0x2 + USBSTA_VBUS = 0x1 + + // USBCON: USB General Control Register + USBCON_USBE = 0x80 + USBCON_HOST = 0x40 + USBCON_FRZCLK = 0x20 + USBCON_OTGPADE = 0x10 + USBCON_IDTE = 0x2 + USBCON_VBUSTE = 0x1 + + // UHWCON: USB Hardware Configuration Register + UHWCON_UIMOD = 0x80 + UHWCON_UIDE = 0x40 + UHWCON_UVCONE = 0x10 + UHWCON_UVREGE = 0x1 +) + +// Bitfields for USB_HOST: USB Host Registers +const ( + // UPERRX + UPERRX_COUNTER = 0x60 + UPERRX_CRC16 = 0x10 + UPERRX_TIMEOUT = 0x8 + UPERRX_PID = 0x4 + UPERRX_DATAPID = 0x2 + UPERRX_DATATGL = 0x1 + + // UPIENX + UPIENX_FLERRE = 0x80 + UPIENX_NAKEDE = 0x40 + UPIENX_PERRE = 0x10 + UPIENX_TXSTPE = 0x8 + UPIENX_TXOUTE = 0x4 + UPIENX_RXSTALLE = 0x2 + UPIENX_RXINE = 0x1 + + // UPSTAX + UPSTAX_CFGOK = 0x80 + UPSTAX_OVERFI = 0x40 + UPSTAX_UNDERFI = 0x20 + UPSTAX_DTSEQ = 0xc + UPSTAX_NBUSYK = 0x3 + + // UPCFG1X + UPCFG1X_PSIZE = 0x70 + UPCFG1X_PBK = 0xc + UPCFG1X_ALLOC = 0x2 + + // UPCFG0X + UPCFG0X_PTYPE = 0xc0 + UPCFG0X_PTOKEN = 0x30 + UPCFG0X_PEPNUM = 0xf + + // UPCONX + UPCONX_PFREEZE = 0x40 + UPCONX_INMODE = 0x20 + UPCONX_RSTDT = 0x8 + UPCONX_PEN = 0x1 + + // UPRST + UPRST_PRST = 0x7f + + // UPINTX + UPINTX_FIFOCON = 0x80 + UPINTX_NAKEDI = 0x40 + UPINTX_RWAL = 0x20 + UPINTX_PERRI = 0x10 + UPINTX_TXSTPI = 0x8 + UPINTX_TXOUTI = 0x4 + UPINTX_RXSTALLI = 0x2 + UPINTX_RXINI = 0x1 + + // UHIEN + UHIEN_HWUPE = 0x40 + UHIEN_HSOFE = 0x20 + UHIEN_RXRSME = 0x10 + UHIEN_RSMEDE = 0x8 + UHIEN_RSTE = 0x4 + UHIEN_DDISCE = 0x2 + UHIEN_DCONNE = 0x1 + + // UHINT + UHINT_UHUPI = 0x40 + UHINT_HSOFI = 0x20 + UHINT_RXRSMI = 0x10 + UHINT_RSMEDI = 0x8 + UHINT_RSTI = 0x4 + UHINT_DDISCI = 0x2 + UHINT_DCONNI = 0x1 + + // UHCON + UHCON_RESUME = 0x4 + UHCON_RESET = 0x2 + UHCON_SOFEN = 0x1 +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2B = 0x4 // Output Compare Flag 2B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Output Mode bits + TCCR2A_COM2B = 0x30 // Compare Output Mode bits + TCCR2A_WGM2 = 0x3 // Waveform Genration Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy + ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR3A: Timer/Counter3 Control Register A + TCCR3A_COM3A = 0xc0 // Compare Output Mode 1A, bits + TCCR3A_COM3B = 0x30 // Compare Output Mode 3B, bits + TCCR3A_COM3C = 0xc // Compare Output Mode 3C, bits + TCCR3A_WGM3 = 0x3 // Waveform Generation Mode + + // TCCR3B: Timer/Counter3 Control Register B + TCCR3B_ICNC3 = 0x80 // Input Capture 3 Noise Canceler + TCCR3B_ICES3 = 0x40 // Input Capture 3 Edge Select + TCCR3B_WGM3 = 0x18 // Waveform Generation Mode + TCCR3B_CS3 = 0x7 // Prescaler source of Timer/Counter 3 + + // TCCR3C: Timer/Counter 3 Control Register C + TCCR3C_FOC3A = 0x80 // Force Output Compare 3A + TCCR3C_FOC3B = 0x40 // Force Output Compare 3B + TCCR3C_FOC3C = 0x20 // Force Output Compare 3C + + // TIMSK3: Timer/Counter3 Interrupt Mask Register + TIMSK3_ICIE3 = 0x20 // Timer/Counter3 Input Capture Interrupt Enable + TIMSK3_OCIE3C = 0x8 // Timer/Counter3 Output Compare C Match Interrupt Enable + TIMSK3_OCIE3B = 0x4 // Timer/Counter3 Output Compare B Match Interrupt Enable + TIMSK3_OCIE3A = 0x2 // Timer/Counter3 Output Compare A Match Interrupt Enable + TIMSK3_TOIE3 = 0x1 // Timer/Counter3 Overflow Interrupt Enable + + // TIFR3: Timer/Counter3 Interrupt Flag register + TIFR3_ICF3 = 0x20 // Input Capture Flag 3 + TIFR3_OCF3C = 0x8 // Output Compare Flag 3C + TIFR3_OCF3B = 0x4 // Output Compare Flag 3B + TIFR3_OCF3A = 0x2 // Output Compare Flag 3A + TIFR3_TOV3 = 0x1 // Timer/Counter3 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_COM1C = 0xc // Compare Output Mode 1C, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + TCCR1C_FOC1C = 0x20 // Force Output Compare 1C + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1C = 0x8 // Timer/Counter1 Output Compare C Match Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1C = 0x8 // Output Compare Flag 1C + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EICRB: External Interrupt Control Register B + EICRB_ISC7 = 0xc0 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC6 = 0x30 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC5 = 0xc // External Interrupt 7-4 Sense Control Bit + EICRB_ISC4 = 0x3 // External Interrupt 7-4 Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xff // External Interrupt Request 7 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xff // External Interrupt Flags + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF0 = 0x1 // Pin Change Interrupt Flag 0 + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE0 = 0x1 // Pin Change Interrupt Enable 0 +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register 1 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for PLL: Phase Locked Loop +const ( + // PLLCSR: PLL Status and Control register + PLLCSR_PLLP = 0x1c // PLL prescaler Bits + PLLCSR_PLLE = 0x2 // PLL Enable Bit + PLLCSR_PLOCK = 0x1 // PLL Lock Status Bit +) diff --git a/src/device/avr/at90usb1287.ld b/src/device/avr/at90usb1287.ld new file mode 100644 index 00000000..16111432 --- /dev/null +++ b/src/device/avr/at90usb1287.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from AT90USB1287.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x20000; +__ram_size = 0x2000; +__num_isrs = 38; diff --git a/src/device/avr/at90usb162.go b/src/device/avr/at90usb162.go new file mode 100644 index 00000000..b5b65fc3 --- /dev/null +++ b/src/device/avr/at90usb162.go @@ -0,0 +1,776 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from AT90USB162.atdf, see http://packs.download.atmel.com/ + +// +build avr,at90usb162 + +// Device information for the AT90USB162. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "AT90USB162" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_INT3 = 4 // External Interrupt Request 3 + IRQ_INT4 = 5 // External Interrupt Request 4 + IRQ_INT5 = 6 // External Interrupt Request 5 + IRQ_INT6 = 7 // External Interrupt Request 6 + IRQ_INT7 = 8 // External Interrupt Request 7 + IRQ_PCINT0 = 9 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 10 // Pin Change Interrupt Request 1 + IRQ_USB_GEN = 11 // USB General Interrupt Request + IRQ_USB_COM = 12 // USB Endpoint/Pipe Interrupt Communication Request + IRQ_WDT = 13 // Watchdog Time-out Interrupt + IRQ_TIMER1_CAPT = 14 // Timer/Counter2 Capture Event + IRQ_TIMER1_COMPA = 15 // Timer/Counter2 Compare Match B + IRQ_TIMER1_COMPB = 16 // Timer/Counter2 Compare Match B + IRQ_TIMER1_COMPC = 17 // Timer/Counter2 Compare Match C + IRQ_TIMER1_OVF = 18 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 19 // Timer/Counter0 Compare Match A + IRQ_TIMER0_COMPB = 20 // Timer/Counter0 Compare Match B + IRQ_TIMER0_OVF = 21 // Timer/Counter0 Overflow + IRQ_SPI_STC = 22 // SPI Serial Transfer Complete + IRQ_USART1_RX = 23 // USART1, Rx Complete + IRQ_USART1_UDRE = 24 // USART1 Data register Empty + IRQ_USART1_TX = 25 // USART1, Tx Complete + IRQ_ANALOG_COMP = 26 // Analog Comparator + IRQ_EE_READY = 27 // EEPROM Ready + IRQ_SPM_READY = 28 // Store Program Memory Read + IRQ_max = 28 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // I/O Port + PORT = struct { + PORTB __reg + DDRB __reg + PINB __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTC __reg + DDRC __reg + PINC __reg + }{ + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Low Bytes + EEARH: 0x41, // EEPROM Address Register Low Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + GTCCR __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + GTCCR: 0x43, // General Timer/Counter Control Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + OCR1CL __reg + OCR1CH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1CL: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + OCR1CH: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // Phase Locked Loop + PLL = struct { + PLLCSR __reg + }{ + PLLCSR: 0x49, // PLL Status and Control register + } + + // USB Device Registers + USB_DEVICE = struct { + UEINT __reg + UEBCLX __reg + UEDATX __reg + UEIENX __reg + UESTA1X __reg + UESTA0X __reg + UECFG1X __reg + UECFG0X __reg + UECONX __reg + UERST __reg + UENUM __reg + UEINTX __reg + UDMFN __reg + UDFNUML __reg + UDFNUMH __reg + UDADDR __reg + UDIEN __reg + UDINT __reg + UDCON __reg + USBCON __reg + REGCR __reg + }{ + UEINT: 0xf4, + UEBCLX: 0xf2, + UEDATX: 0xf1, + UEIENX: 0xf0, + UESTA1X: 0xef, + UESTA0X: 0xee, + UECFG1X: 0xed, + UECFG0X: 0xec, + UECONX: 0xeb, + UERST: 0xea, + UENUM: 0xe9, + UEINTX: 0xe8, + UDMFN: 0xe6, + UDFNUML: 0xe4, + UDFNUMH: 0xe4, + UDADDR: 0xe3, + UDIEN: 0xe2, + UDINT: 0xe1, + UDCON: 0xe0, + USBCON: 0xd8, // USB General Control Register + REGCR: 0x63, // Regulator Control Register + } + + // PS/2 Controller + PS2 = struct { + UPOE __reg + PS2CON __reg + }{ + UPOE: 0xfb, + PS2CON: 0xfa, // PS2 Pad Enable register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + MCUCR __reg + MCUSR __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + EIND __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PRR1 __reg + PRR0 __reg + CLKSTA __reg + CLKSEL1 __reg + CLKSEL0 __reg + DWDR __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, + SMCR: 0x53, // Sleep Mode Control Register + EIND: 0x5c, // Extended Indirect Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PRR1: 0x65, // Power Reduction Register1 + PRR0: 0x64, // Power Reduction Register0 + CLKSTA: 0xd2, + CLKSEL1: 0xd1, + CLKSEL0: 0xd0, + DWDR: 0x51, // debugWire communication register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EICRB __reg + EIMSK __reg + EIFR __reg + PCMSK0 __reg + PCMSK1 __reg + PCIFR __reg + PCICR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EICRB: 0x6a, // External Interrupt Control Register B + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + } + + // USART + USART = struct { + UDR1 __reg + UCSR1A __reg + UCSR1B __reg + UCSR1C __reg + UCSR1D __reg + UBRR1L __reg + UBRR1H __reg + }{ + UDR1: 0xce, // USART I/O Data Register + UCSR1A: 0xc8, // USART Control and Status Register A + UCSR1B: 0xc9, // USART Control and Status Register B + UCSR1C: 0xca, // USART Control and Status Register C + UCSR1D: 0xcb, // USART Control and Status Register D + UBRR1L: 0xcc, // USART Baud Rate Register Bytes + UBRR1H: 0xcc, // USART Baud Rate Register Bytes + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + WDTCKD __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + WDTCKD: 0x62, // Watchdog Timer Clock Divider + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level + EXTENDED_HWBE = 0x8 // Hardware Boot Enable + + // HIGH + HIGH_DWEN = 0x80 // Debug Wire enable + HIGH_RSTDISBL = 0x40 // Reset Disabled (Enable PC6 as i/o pin) + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTC7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for PORT: I/O Port +const ( + // PORTC: Port C Data Register + PORTC_PORTC = 0xf0 // Port C Data Register bits + PORTC_PORTC = 0x7 // Port C Data Register bits + + // DDRC: Port C Data Direction Register + DDRC_DDC = 0xf0 // Port C Data Direction Register bits + DDRC_DDC = 0x7 // Port C Data Direction Register bits + + // PINC: Port C Input Pins + PINC_PINC = 0xf0 // Port C Input Pins bits + PINC_PINC = 0x7 // Port C Input Pins bits +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag + + // GTCCR: General Timer/Counter Control Register + GTCCR_TSM = 0x80 // Timer/Counter Synchronization Mode + GTCCR_PSRSYNC = 0x1 // Prescaler Reset Timer/Counter1 and Timer/Counter0 +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_COM1C = 0xc // Compare Output Mode 1C, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + TCCR1C_FOC1C = 0x20 // Force Output Compare 1C + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1C = 0x8 // Timer/Counter1 Output Compare C Match Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1C = 0x8 // Output Compare Flag 1C + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for PLL: Phase Locked Loop +const ( + // PLLCSR: PLL Status and Control register + PLLCSR_PLLP = 0x1c // PLL prescaler Bits + PLLCSR_PLLE = 0x2 // PLL Enable Bit + PLLCSR_PLOCK = 0x1 // PLL Lock Status Bit +) + +// Bitfields for USB_DEVICE: USB Device Registers +const ( + // UEIENX + UEIENX_FLERRE = 0x80 + UEIENX_NAKINE = 0x40 + UEIENX_NAKOUTE = 0x10 + UEIENX_RXSTPE = 0x8 + UEIENX_RXOUTE = 0x4 + UEIENX_STALLEDE = 0x2 + UEIENX_TXINE = 0x1 + + // UESTA1X + UESTA1X_CTRLDIR = 0x4 + UESTA1X_CURRBK = 0x3 + + // UESTA0X + UESTA0X_CFGOK = 0x80 + UESTA0X_OVERFI = 0x40 + UESTA0X_UNDERFI = 0x20 + UESTA0X_DTSEQ = 0xc + UESTA0X_NBUSYBK = 0x3 + + // UECFG1X + UECFG1X_EPSIZE = 0x70 + UECFG1X_EPBK = 0xc + UECFG1X_ALLOC = 0x2 + + // UECFG0X + UECFG0X_EPTYPE = 0xc0 + UECFG0X_EPDIR = 0x1 + + // UECONX + UECONX_STALLRQ = 0x20 + UECONX_STALLRQC = 0x10 + UECONX_RSTDT = 0x8 + UECONX_EPEN = 0x1 + + // UERST + UERST_EPRST = 0x1f + + // UEINTX + UEINTX_FIFOCON = 0x80 + UEINTX_NAKINI = 0x40 + UEINTX_RWAL = 0x20 + UEINTX_NAKOUTI = 0x10 + UEINTX_RXSTPI = 0x8 + UEINTX_RXOUTI = 0x4 + UEINTX_STALLEDI = 0x2 + UEINTX_TXINI = 0x1 + + // UDMFN + UDMFN_FNCERR = 0x10 + + // UDADDR + UDADDR_ADDEN = 0x80 + UDADDR_UADD = 0x7f + + // UDIEN + UDIEN_UPRSME = 0x40 + UDIEN_EORSME = 0x20 + UDIEN_WAKEUPE = 0x10 + UDIEN_EORSTE = 0x8 + UDIEN_SOFE = 0x4 + UDIEN_SUSPE = 0x1 + + // UDINT + UDINT_UPRSMI = 0x40 + UDINT_EORSMI = 0x20 + UDINT_WAKEUPI = 0x10 + UDINT_EORSTI = 0x8 + UDINT_SOFI = 0x4 + UDINT_SUSPI = 0x1 + + // UDCON + UDCON_RSTCPU = 0x4 + UDCON_RMWKUP = 0x2 + UDCON_DETACH = 0x1 + + // USBCON: USB General Control Register + USBCON_USBE = 0x80 + USBCON_FRZCLK = 0x20 + + // REGCR: Regulator Control Register + REGCR_REGDIS = 0x1 +) + +// Bitfields for PS2: PS/2 Controller +const ( + // UPOE + UPOE_UPWE = 0xc0 + UPOE_UPDRV = 0x30 + UPOE_SCKI = 0x8 + UPOE_DATAI = 0x4 + UPOE_DPI = 0x2 + UPOE_DMI = 0x1 + + // PS2CON: PS2 Pad Enable register + PS2CON_PS2EN = 0x1 // Enable +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // MCUCR: MCU Control Register + MCUCR_PUD = 0x10 // Pull-up disable + MCUCR_IVSEL = 0x2 // Interrupt Vector Select + MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable + + // MCUSR: MCU Status Register + MCUSR_USBRF = 0x20 // USB reset flag + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BORF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 + + // PRR1: Power Reduction Register1 + PRR1_PRUSB = 0x80 // Power Reduction USB + PRR1_PRUSART1 = 0x1 // Power Reduction USART1 + + // PRR0: Power Reduction Register0 + PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + + // CLKSTA + CLKSTA_RCON = 0x2 + CLKSTA_EXTON = 0x1 + + // CLKSEL1 + CLKSEL1_RCCKSEL = 0xf0 + CLKSEL1_EXCKSEL = 0xf + + // CLKSEL0 + CLKSEL0_RCSUT = 0xc0 + CLKSEL0_EXSUT = 0x30 + CLKSEL0_RCE = 0x8 + CLKSEL0_EXTE = 0x4 + CLKSEL0_CLKS = 0x1 +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EICRB: External Interrupt Control Register B + EICRB_ISC7 = 0xc0 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC6 = 0x30 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC5 = 0xc // External Interrupt 7-4 Sense Control Bit + EICRB_ISC4 = 0x3 // External Interrupt 7-4 Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xff // External Interrupt Request 7 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xff // External Interrupt Flags + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0x1f + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0x3 // Pin Change Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0x3 // Pin Change Interrupt Enables +) + +// Bitfields for USART: USART +const ( + // UCSR1A: USART Control and Status Register A + UCSR1A_RXC1 = 0x80 // USART Receive Complete + UCSR1A_TXC1 = 0x40 // USART Transmitt Complete + UCSR1A_UDRE1 = 0x20 // USART Data Register Empty + UCSR1A_FE1 = 0x10 // Framing Error + UCSR1A_DOR1 = 0x8 // Data overRun + UCSR1A_UPE1 = 0x4 // Parity Error + UCSR1A_U2X1 = 0x2 // Double the USART transmission speed + UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode + + // UCSR1B: USART Control and Status Register B + UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable + UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable + UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable + UCSR1B_RXEN1 = 0x10 // Receiver Enable + UCSR1B_TXEN1 = 0x8 // Transmitter Enable + UCSR1B_UCSZ12 = 0x4 // Character Size + UCSR1B_RXB81 = 0x2 // Receive Data Bit 8 + UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8 + + // UCSR1C: USART Control and Status Register C + UCSR1C_UMSEL1 = 0xc0 // USART Mode Select + UCSR1C_UPM1 = 0x30 // Parity Mode Bits + UCSR1C_USBS1 = 0x8 // Stop Bit Select + UCSR1C_UCSZ1 = 0x6 // Character Size + UCSR1C_UCPOL1 = 0x1 // Clock Polarity + + // UCSR1D: USART Control and Status Register D + UCSR1D_CTSEN = 0x2 // CTS Enable + UCSR1D_RTSEN = 0x1 // RTS Enable +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable + + // WDTCKD: Watchdog Timer Clock Divider + WDTCKD_WDEWIF = 0x8 // Watchdog Early Warning Interrupt Flag + WDTCKD_WDEWIE = 0x4 // Watchdog Early Warning Interrupt Enable + WDTCKD_WCLKD = 0x3 // Watchdog Timer Clock Dividers +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) diff --git a/src/device/avr/at90usb162.ld b/src/device/avr/at90usb162.ld new file mode 100644 index 00000000..92586231 --- /dev/null +++ b/src/device/avr/at90usb162.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from AT90USB162.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_size = 0x200; +__num_isrs = 29; diff --git a/src/device/avr/at90usb646.go b/src/device/avr/at90usb646.go new file mode 100644 index 00000000..745c08cd --- /dev/null +++ b/src/device/avr/at90usb646.go @@ -0,0 +1,1117 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from AT90USB646.atdf, see http://packs.download.atmel.com/ + +// +build avr,at90usb646 + +// Device information for the AT90USB646. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "AT90USB646" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_INT3 = 4 // External Interrupt Request 3 + IRQ_INT4 = 5 // External Interrupt Request 4 + IRQ_INT5 = 6 // External Interrupt Request 5 + IRQ_INT6 = 7 // External Interrupt Request 6 + IRQ_INT7 = 8 // External Interrupt Request 7 + IRQ_PCINT0 = 9 // Pin Change Interrupt Request 0 + IRQ_USB_GEN = 10 // USB General Interrupt Request + IRQ_USB_COM = 11 // USB Endpoint/Pipe Interrupt Communication Request + IRQ_WDT = 12 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 13 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 14 // Timer/Counter2 Compare Match B + IRQ_TIMER2_OVF = 15 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 16 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 17 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 18 // Timer/Counter1 Compare Match B + IRQ_TIMER1_COMPC = 19 // Timer/Counter1 Compare Match C + IRQ_TIMER1_OVF = 20 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 21 // Timer/Counter0 Compare Match A + IRQ_TIMER0_COMPB = 22 // Timer/Counter0 Compare Match B + IRQ_TIMER0_OVF = 23 // Timer/Counter0 Overflow + IRQ_SPI_STC = 24 // SPI Serial Transfer Complete + IRQ_USART1_RX = 25 // USART1, Rx Complete + IRQ_USART1_UDRE = 26 // USART1 Data register Empty + IRQ_USART1_TX = 27 // USART1, Tx Complete + IRQ_ANALOG_COMP = 28 // Analog Comparator + IRQ_ADC = 29 // ADC Conversion Complete + IRQ_EE_READY = 30 // EEPROM Ready + IRQ_TIMER3_CAPT = 31 // Timer/Counter3 Capture Event + IRQ_TIMER3_COMPA = 32 // Timer/Counter3 Compare Match A + IRQ_TIMER3_COMPB = 33 // Timer/Counter3 Compare Match B + IRQ_TIMER3_COMPC = 34 // Timer/Counter3 Compare Match C + IRQ_TIMER3_OVF = 35 // Timer/Counter3 Overflow + IRQ_TWI = 36 // 2-wire Serial Interface + IRQ_SPM_READY = 37 // Store Program Memory Read + IRQ_max = 37 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + XMCRA __reg + XMCRB __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + EIND __reg + RAMPZ __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PRR1 __reg + PRR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + XMCRA: 0x74, // External Memory Control Register A + XMCRB: 0x75, // External Memory Control Register B + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, + SMCR: 0x53, // Sleep Mode Control Register + EIND: 0x5c, // Extended Indirect Register + RAMPZ: 0x5b, // RAM Page Z Select Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PRR1: 0x65, // Power Reduction Register1 + PRR0: 0x64, // Power Reduction Register0 + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // USART + USART = struct { + UDR1 __reg + UCSR1A __reg + UCSR1B __reg + UCSR1C __reg + UBRR1L __reg + UBRR1H __reg + }{ + UDR1: 0xce, // USART I/O Data Register + UCSR1A: 0xc8, // USART Control and Status Register A + UCSR1B: 0xc9, // USART Control and Status Register B + UCSR1C: 0xca, // USART Control and Status Register C + UBRR1L: 0xcc, // USART Baud Rate Register Bytes + UBRR1H: 0xcc, // USART Baud Rate Register Bytes + } + + // USB Device Registers + USB_DEVICE = struct { + UEINT __reg + UEBCHX __reg + UEBCLX __reg + UEDATX __reg + UEIENX __reg + UESTA1X __reg + UESTA0X __reg + UECFG1X __reg + UECFG0X __reg + UECONX __reg + UERST __reg + UENUM __reg + UEINTX __reg + UDMFN __reg + UDFNUML __reg + UDFNUMH __reg + UDADDR __reg + UDIEN __reg + UDINT __reg + UDCON __reg + }{ + UEINT: 0xf4, + UEBCHX: 0xf3, + UEBCLX: 0xf2, + UEDATX: 0xf1, + UEIENX: 0xf0, + UESTA1X: 0xef, + UESTA0X: 0xee, + UECFG1X: 0xed, + UECFG0X: 0xec, + UECONX: 0xeb, + UERST: 0xea, + UENUM: 0xe9, + UEINTX: 0xe8, + UDMFN: 0xe6, + UDFNUML: 0xe4, + UDFNUMH: 0xe4, + UDADDR: 0xe3, + UDIEN: 0xe2, + UDINT: 0xe1, + UDCON: 0xe0, + } + + // USB Controller + USB_GLOBAL = struct { + OTGINT __reg + OTGIEN __reg + OTGCON __reg + OTGTCON __reg + USBINT __reg + USBSTA __reg + USBCON __reg + UHWCON __reg + }{ + OTGINT: 0xdf, + OTGIEN: 0xde, + OTGCON: 0xdd, + OTGTCON: 0xf9, + USBINT: 0xda, + USBSTA: 0xd9, + USBCON: 0xd8, // USB General Control Register + UHWCON: 0xd7, // USB Hardware Configuration Register + } + + // USB Host Registers + USB_HOST = struct { + UPERRX __reg + UPINT __reg + UPBCHX __reg + UPBCLX __reg + UPDATX __reg + UPIENX __reg + UPCFG2X __reg + UPSTAX __reg + UPCFG1X __reg + UPCFG0X __reg + UPCONX __reg + UPRST __reg + UPNUM __reg + UPINTX __reg + UPINRQX __reg + UHFLEN __reg + UHFNUML __reg + UHFNUMH __reg + UHADDR __reg + UHIEN __reg + UHINT __reg + UHCON __reg + }{ + UPERRX: 0xf5, + UPINT: 0xf8, + UPBCHX: 0xf7, + UPBCLX: 0xf6, + UPDATX: 0xaf, + UPIENX: 0xae, + UPCFG2X: 0xad, + UPSTAX: 0xac, + UPCFG1X: 0xab, + UPCFG0X: 0xaa, + UPCONX: 0xa9, + UPRST: 0xa8, + UPNUM: 0xa7, + UPINTX: 0xa6, + UPINRQX: 0xa5, + UHFLEN: 0xa4, + UHFNUML: 0xa2, + UHFNUMH: 0xa2, + UHADDR: 0xa1, + UHIEN: 0xa0, + UHINT: 0x9f, + UHCON: 0x9e, + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Low Bytes + EEARH: 0x41, // EEPROM Address Register Low Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR3A __reg + TCCR3B __reg + TCCR3C __reg + TCNT3L __reg + TCNT3H __reg + OCR3AL __reg + OCR3AH __reg + OCR3BL __reg + OCR3BH __reg + OCR3CL __reg + OCR3CH __reg + ICR3L __reg + ICR3H __reg + TIMSK3 __reg + TIFR3 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + OCR1CL __reg + OCR1CH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR3A: 0x90, // Timer/Counter3 Control Register A + TCCR3B: 0x91, // Timer/Counter3 Control Register B + TCCR3C: 0x92, // Timer/Counter 3 Control Register C + TCNT3L: 0x94, // Timer/Counter3 Bytes + TCNT3H: 0x94, // Timer/Counter3 Bytes + OCR3AL: 0x98, // Timer/Counter3 Output Compare Register A Bytes + OCR3AH: 0x98, // Timer/Counter3 Output Compare Register A Bytes + OCR3BL: 0x9a, // Timer/Counter3 Output Compare Register B Bytes + OCR3BH: 0x9a, // Timer/Counter3 Output Compare Register B Bytes + OCR3CL: 0x9c, // Timer/Counter3 Output Compare Register B Bytes + OCR3CH: 0x9c, // Timer/Counter3 Output Compare Register B Bytes + ICR3L: 0x96, // Timer/Counter3 Input Capture Register Bytes + ICR3H: 0x96, // Timer/Counter3 Input Capture Register Bytes + TIMSK3: 0x71, // Timer/Counter3 Interrupt Mask Register + TIFR3: 0x38, // Timer/Counter3 Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1CL: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + OCR1CH: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EICRB __reg + EIMSK __reg + EIFR __reg + PCMSK0 __reg + PCIFR __reg + PCICR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EICRB: 0x6a, // External Interrupt Control Register B + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 1 + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, + } + + // Phase Locked Loop + PLL = struct { + PLLCSR __reg + }{ + PLLCSR: 0x49, // PLL Status and Control register + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level + EXTENDED_HWBE = 0x8 // Hardware Boot Enable + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTC7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // XMCRA: External Memory Control Register A + XMCRA_SRE = 0x80 // External SRAM Enable + XMCRA_SRL = 0x70 // Wait state page limit + XMCRA_SRW1 = 0xc // Wait state select bit upper page + XMCRA_SRW0 = 0x3 // Wait state select bit lower page + + // XMCRB: External Memory Control Register B + XMCRB_XMBK = 0x80 // External Memory Bus Keeper Enable + XMCRB_XMM = 0x7 // External Memory High Mask + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 + + // PRR1: Power Reduction Register1 + PRR1_PRUSB = 0x80 // Power Reduction USB + PRR1_PRTIM3 = 0x8 // Power Reduction Timer/Counter3 + PRR1_PRUSART1 = 0x1 // Power Reduction USART1 + + // PRR0: Power Reduction Register0 + PRR0_PRTWI = 0x80 // Power Reduction TWI + PRR0_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR0_PRADC = 0x1 // Power Reduction ADC +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for USART: USART +const ( + // UCSR1A: USART Control and Status Register A + UCSR1A_RXC1 = 0x80 // USART Receive Complete + UCSR1A_TXC1 = 0x40 // USART Transmitt Complete + UCSR1A_UDRE1 = 0x20 // USART Data Register Empty + UCSR1A_FE1 = 0x10 // Framing Error + UCSR1A_DOR1 = 0x8 // Data overRun + UCSR1A_UPE1 = 0x4 // Parity Error + UCSR1A_U2X1 = 0x2 // Double the USART transmission speed + UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode + + // UCSR1B: USART Control and Status Register B + UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable + UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable + UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable + UCSR1B_RXEN1 = 0x10 // Receiver Enable + UCSR1B_TXEN1 = 0x8 // Transmitter Enable + UCSR1B_UCSZ12 = 0x4 // Character Size + UCSR1B_RXB81 = 0x2 // Receive Data Bit 8 + UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8 + + // UCSR1C: USART Control and Status Register C + UCSR1C_UMSEL1 = 0xc0 // USART Mode Select + UCSR1C_UPM1 = 0x30 // Parity Mode Bits + UCSR1C_USBS1 = 0x8 // Stop Bit Select + UCSR1C_UCSZ1 = 0x6 // Character Size + UCSR1C_UCPOL1 = 0x1 // Clock Polarity +) + +// Bitfields for USB_DEVICE: USB Device Registers +const ( + // UEIENX + UEIENX_FLERRE = 0x80 + UEIENX_NAKINE = 0x40 + UEIENX_NAKOUTE = 0x10 + UEIENX_RXSTPE = 0x8 + UEIENX_RXOUTE = 0x4 + UEIENX_STALLEDE = 0x2 + UEIENX_TXINE = 0x1 + + // UESTA1X + UESTA1X_CTRLDIR = 0x4 + UESTA1X_CURRBK = 0x3 + + // UESTA0X + UESTA0X_CFGOK = 0x80 + UESTA0X_OVERFI = 0x40 + UESTA0X_UNDERFI = 0x20 + UESTA0X_DTSEQ = 0xc + UESTA0X_NBUSYBK = 0x3 + + // UECFG1X + UECFG1X_EPSIZE = 0x70 + UECFG1X_EPBK = 0xc + UECFG1X_ALLOC = 0x2 + + // UECFG0X + UECFG0X_EPTYPE = 0xc0 + UECFG0X_EPDIR = 0x1 + + // UECONX + UECONX_STALLRQ = 0x20 + UECONX_STALLRQC = 0x10 + UECONX_RSTDT = 0x8 + UECONX_EPEN = 0x1 + + // UERST + UERST_EPRST = 0x7f + + // UEINTX + UEINTX_FIFOCON = 0x80 + UEINTX_NAKINI = 0x40 + UEINTX_RWAL = 0x20 + UEINTX_NAKOUTI = 0x10 + UEINTX_RXSTPI = 0x8 + UEINTX_RXOUTI = 0x4 + UEINTX_STALLEDI = 0x2 + UEINTX_TXINI = 0x1 + + // UDMFN + UDMFN_FNCERR = 0x10 + + // UDADDR + UDADDR_ADDEN = 0x80 + UDADDR_UADD = 0x7f + + // UDIEN + UDIEN_UPRSME = 0x40 + UDIEN_EORSME = 0x20 + UDIEN_WAKEUPE = 0x10 + UDIEN_EORSTE = 0x8 + UDIEN_SOFE = 0x4 + UDIEN_SUSPE = 0x1 + + // UDINT + UDINT_UPRSMI = 0x40 + UDINT_EORSMI = 0x20 + UDINT_WAKEUPI = 0x10 + UDINT_EORSTI = 0x8 + UDINT_SOFI = 0x4 + UDINT_SUSPI = 0x1 + + // UDCON + UDCON_LSM = 0x4 + UDCON_RMWKUP = 0x2 + UDCON_DETACH = 0x1 +) + +// Bitfields for USB_GLOBAL: USB Controller +const ( + // OTGINT + OTGINT_STOI = 0x20 + OTGINT_HNPERRI = 0x10 + OTGINT_ROLEEXI = 0x8 + OTGINT_BCERRI = 0x4 + OTGINT_VBERRI = 0x2 + OTGINT_SRPI = 0x1 + + // OTGIEN + OTGIEN_STOE = 0x20 + OTGIEN_HNPERRE = 0x10 + OTGIEN_ROLEEXE = 0x8 + OTGIEN_BCERRE = 0x4 + OTGIEN_VBERRE = 0x2 + OTGIEN_SRPE = 0x1 + + // OTGCON + OTGCON_HNPREQ = 0x20 + OTGCON_SRPREQ = 0x10 + OTGCON_SRPSEL = 0x8 + OTGCON_VBUSHWC = 0x4 + OTGCON_VBUSREQ = 0x2 + OTGCON_VBUSRQC = 0x1 + + // OTGTCON + OTGTCON_OTGTCON_7 = 0x80 + OTGTCON_PAGE = 0x60 + OTGTCON_VALUE_2 = 0x7 + + // USBINT + USBINT_IDTI = 0x2 + USBINT_VBUSTI = 0x1 + + // USBSTA + USBSTA_SPEED = 0x8 + USBSTA_ID = 0x2 + USBSTA_VBUS = 0x1 + + // USBCON: USB General Control Register + USBCON_USBE = 0x80 + USBCON_HOST = 0x40 + USBCON_FRZCLK = 0x20 + USBCON_OTGPADE = 0x10 + USBCON_IDTE = 0x2 + USBCON_VBUSTE = 0x1 + + // UHWCON: USB Hardware Configuration Register + UHWCON_UIMOD = 0x80 + UHWCON_UIDE = 0x40 + UHWCON_UVCONE = 0x10 + UHWCON_UVREGE = 0x1 +) + +// Bitfields for USB_HOST: USB Host Registers +const ( + // UPERRX + UPERRX_COUNTER = 0x60 + UPERRX_CRC16 = 0x10 + UPERRX_TIMEOUT = 0x8 + UPERRX_PID = 0x4 + UPERRX_DATAPID = 0x2 + UPERRX_DATATGL = 0x1 + + // UPIENX + UPIENX_FLERRE = 0x80 + UPIENX_NAKEDE = 0x40 + UPIENX_PERRE = 0x10 + UPIENX_TXSTPE = 0x8 + UPIENX_TXOUTE = 0x4 + UPIENX_RXSTALLE = 0x2 + UPIENX_RXINE = 0x1 + + // UPSTAX + UPSTAX_CFGOK = 0x80 + UPSTAX_OVERFI = 0x40 + UPSTAX_UNDERFI = 0x20 + UPSTAX_DTSEQ = 0xc + UPSTAX_NBUSYK = 0x3 + + // UPCFG1X + UPCFG1X_PSIZE = 0x70 + UPCFG1X_PBK = 0xc + UPCFG1X_ALLOC = 0x2 + + // UPCFG0X + UPCFG0X_PTYPE = 0xc0 + UPCFG0X_PTOKEN = 0x30 + UPCFG0X_PEPNUM = 0xf + + // UPCONX + UPCONX_PFREEZE = 0x40 + UPCONX_INMODE = 0x20 + UPCONX_RSTDT = 0x8 + UPCONX_PEN = 0x1 + + // UPRST + UPRST_PRST = 0x7f + + // UPINTX + UPINTX_FIFOCON = 0x80 + UPINTX_NAKEDI = 0x40 + UPINTX_RWAL = 0x20 + UPINTX_PERRI = 0x10 + UPINTX_TXSTPI = 0x8 + UPINTX_TXOUTI = 0x4 + UPINTX_RXSTALLI = 0x2 + UPINTX_RXINI = 0x1 + + // UHIEN + UHIEN_HWUPE = 0x40 + UHIEN_HSOFE = 0x20 + UHIEN_RXRSME = 0x10 + UHIEN_RSMEDE = 0x8 + UHIEN_RSTE = 0x4 + UHIEN_DDISCE = 0x2 + UHIEN_DCONNE = 0x1 + + // UHINT + UHINT_UHUPI = 0x40 + UHINT_HSOFI = 0x20 + UHINT_RXRSMI = 0x10 + UHINT_RSMEDI = 0x8 + UHINT_RSTI = 0x4 + UHINT_DDISCI = 0x2 + UHINT_DCONNI = 0x1 + + // UHCON + UHCON_RESUME = 0x4 + UHCON_RESET = 0x2 + UHCON_SOFEN = 0x1 +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2B = 0x4 // Output Compare Flag 2B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Output Mode bits + TCCR2A_COM2B = 0x30 // Compare Output Mode bits + TCCR2A_WGM2 = 0x3 // Waveform Genration Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy + ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR3A: Timer/Counter3 Control Register A + TCCR3A_COM3A = 0xc0 // Compare Output Mode 1A, bits + TCCR3A_COM3B = 0x30 // Compare Output Mode 3B, bits + TCCR3A_COM3C = 0xc // Compare Output Mode 3C, bits + TCCR3A_WGM3 = 0x3 // Waveform Generation Mode + + // TCCR3B: Timer/Counter3 Control Register B + TCCR3B_ICNC3 = 0x80 // Input Capture 3 Noise Canceler + TCCR3B_ICES3 = 0x40 // Input Capture 3 Edge Select + TCCR3B_WGM3 = 0x18 // Waveform Generation Mode + TCCR3B_CS3 = 0x7 // Prescaler source of Timer/Counter 3 + + // TCCR3C: Timer/Counter 3 Control Register C + TCCR3C_FOC3A = 0x80 // Force Output Compare 3A + TCCR3C_FOC3B = 0x40 // Force Output Compare 3B + TCCR3C_FOC3C = 0x20 // Force Output Compare 3C + + // TIMSK3: Timer/Counter3 Interrupt Mask Register + TIMSK3_ICIE3 = 0x20 // Timer/Counter3 Input Capture Interrupt Enable + TIMSK3_OCIE3C = 0x8 // Timer/Counter3 Output Compare C Match Interrupt Enable + TIMSK3_OCIE3B = 0x4 // Timer/Counter3 Output Compare B Match Interrupt Enable + TIMSK3_OCIE3A = 0x2 // Timer/Counter3 Output Compare A Match Interrupt Enable + TIMSK3_TOIE3 = 0x1 // Timer/Counter3 Overflow Interrupt Enable + + // TIFR3: Timer/Counter3 Interrupt Flag register + TIFR3_ICF3 = 0x20 // Input Capture Flag 3 + TIFR3_OCF3C = 0x8 // Output Compare Flag 3C + TIFR3_OCF3B = 0x4 // Output Compare Flag 3B + TIFR3_OCF3A = 0x2 // Output Compare Flag 3A + TIFR3_TOV3 = 0x1 // Timer/Counter3 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_COM1C = 0xc // Compare Output Mode 1C, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + TCCR1C_FOC1C = 0x20 // Force Output Compare 1C + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1C = 0x8 // Timer/Counter1 Output Compare C Match Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1C = 0x8 // Output Compare Flag 1C + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EICRB: External Interrupt Control Register B + EICRB_ISC7 = 0xc0 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC6 = 0x30 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC5 = 0xc // External Interrupt 7-4 Sense Control Bit + EICRB_ISC4 = 0x3 // External Interrupt 7-4 Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xff // External Interrupt Request 7 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xff // External Interrupt Flags + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF0 = 0x1 // Pin Change Interrupt Flag 0 + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE0 = 0x1 // Pin Change Interrupt Enable 0 +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register 1 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for PLL: Phase Locked Loop +const ( + // PLLCSR: PLL Status and Control register + PLLCSR_PLLP = 0x1c // PLL prescaler Bits + PLLCSR_PLLE = 0x2 // PLL Enable Bit + PLLCSR_PLOCK = 0x1 // PLL Lock Status Bit +) diff --git a/src/device/avr/at90usb646.ld b/src/device/avr/at90usb646.ld new file mode 100644 index 00000000..5d4a5d93 --- /dev/null +++ b/src/device/avr/at90usb646.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from AT90USB646.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_size = 0x1000; +__num_isrs = 38; diff --git a/src/device/avr/at90usb647.go b/src/device/avr/at90usb647.go new file mode 100644 index 00000000..ce0c18b7 --- /dev/null +++ b/src/device/avr/at90usb647.go @@ -0,0 +1,1117 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from AT90USB647.atdf, see http://packs.download.atmel.com/ + +// +build avr,at90usb647 + +// Device information for the AT90USB647. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "AT90USB647" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_INT3 = 4 // External Interrupt Request 3 + IRQ_INT4 = 5 // External Interrupt Request 4 + IRQ_INT5 = 6 // External Interrupt Request 5 + IRQ_INT6 = 7 // External Interrupt Request 6 + IRQ_INT7 = 8 // External Interrupt Request 7 + IRQ_PCINT0 = 9 // Pin Change Interrupt Request 0 + IRQ_USB_GEN = 10 // USB General Interrupt Request + IRQ_USB_COM = 11 // USB Endpoint/Pipe Interrupt Communication Request + IRQ_WDT = 12 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 13 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 14 // Timer/Counter2 Compare Match B + IRQ_TIMER2_OVF = 15 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 16 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 17 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 18 // Timer/Counter1 Compare Match B + IRQ_TIMER1_COMPC = 19 // Timer/Counter1 Compare Match C + IRQ_TIMER1_OVF = 20 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 21 // Timer/Counter0 Compare Match A + IRQ_TIMER0_COMPB = 22 // Timer/Counter0 Compare Match B + IRQ_TIMER0_OVF = 23 // Timer/Counter0 Overflow + IRQ_SPI_STC = 24 // SPI Serial Transfer Complete + IRQ_USART1_RX = 25 // USART1, Rx Complete + IRQ_USART1_UDRE = 26 // USART1 Data register Empty + IRQ_USART1_TX = 27 // USART1, Tx Complete + IRQ_ANALOG_COMP = 28 // Analog Comparator + IRQ_ADC = 29 // ADC Conversion Complete + IRQ_EE_READY = 30 // EEPROM Ready + IRQ_TIMER3_CAPT = 31 // Timer/Counter3 Capture Event + IRQ_TIMER3_COMPA = 32 // Timer/Counter3 Compare Match A + IRQ_TIMER3_COMPB = 33 // Timer/Counter3 Compare Match B + IRQ_TIMER3_COMPC = 34 // Timer/Counter3 Compare Match C + IRQ_TIMER3_OVF = 35 // Timer/Counter3 Overflow + IRQ_TWI = 36 // 2-wire Serial Interface + IRQ_SPM_READY = 37 // Store Program Memory Read + IRQ_max = 37 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + XMCRA __reg + XMCRB __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + EIND __reg + RAMPZ __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PRR1 __reg + PRR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + XMCRA: 0x74, // External Memory Control Register A + XMCRB: 0x75, // External Memory Control Register B + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, + SMCR: 0x53, // Sleep Mode Control Register + EIND: 0x5c, // Extended Indirect Register + RAMPZ: 0x5b, // RAM Page Z Select Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PRR1: 0x65, // Power Reduction Register1 + PRR0: 0x64, // Power Reduction Register0 + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // USART + USART = struct { + UDR1 __reg + UCSR1A __reg + UCSR1B __reg + UCSR1C __reg + UBRR1L __reg + UBRR1H __reg + }{ + UDR1: 0xce, // USART I/O Data Register + UCSR1A: 0xc8, // USART Control and Status Register A + UCSR1B: 0xc9, // USART Control and Status Register B + UCSR1C: 0xca, // USART Control and Status Register C + UBRR1L: 0xcc, // USART Baud Rate Register Bytes + UBRR1H: 0xcc, // USART Baud Rate Register Bytes + } + + // USB Device Registers + USB_DEVICE = struct { + UEINT __reg + UEBCHX __reg + UEBCLX __reg + UEDATX __reg + UEIENX __reg + UESTA1X __reg + UESTA0X __reg + UECFG1X __reg + UECFG0X __reg + UECONX __reg + UERST __reg + UENUM __reg + UEINTX __reg + UDMFN __reg + UDFNUML __reg + UDFNUMH __reg + UDADDR __reg + UDIEN __reg + UDINT __reg + UDCON __reg + }{ + UEINT: 0xf4, + UEBCHX: 0xf3, + UEBCLX: 0xf2, + UEDATX: 0xf1, + UEIENX: 0xf0, + UESTA1X: 0xef, + UESTA0X: 0xee, + UECFG1X: 0xed, + UECFG0X: 0xec, + UECONX: 0xeb, + UERST: 0xea, + UENUM: 0xe9, + UEINTX: 0xe8, + UDMFN: 0xe6, + UDFNUML: 0xe4, + UDFNUMH: 0xe4, + UDADDR: 0xe3, + UDIEN: 0xe2, + UDINT: 0xe1, + UDCON: 0xe0, + } + + // USB Controller + USB_GLOBAL = struct { + OTGINT __reg + OTGIEN __reg + OTGCON __reg + OTGTCON __reg + USBINT __reg + USBSTA __reg + USBCON __reg + UHWCON __reg + }{ + OTGINT: 0xdf, + OTGIEN: 0xde, + OTGCON: 0xdd, + OTGTCON: 0xf9, + USBINT: 0xda, + USBSTA: 0xd9, + USBCON: 0xd8, // USB General Control Register + UHWCON: 0xd7, // USB Hardware Configuration Register + } + + // USB Host Registers + USB_HOST = struct { + UPERRX __reg + UPINT __reg + UPBCHX __reg + UPBCLX __reg + UPDATX __reg + UPIENX __reg + UPCFG2X __reg + UPSTAX __reg + UPCFG1X __reg + UPCFG0X __reg + UPCONX __reg + UPRST __reg + UPNUM __reg + UPINTX __reg + UPINRQX __reg + UHFLEN __reg + UHFNUML __reg + UHFNUMH __reg + UHADDR __reg + UHIEN __reg + UHINT __reg + UHCON __reg + }{ + UPERRX: 0xf5, + UPINT: 0xf8, + UPBCHX: 0xf7, + UPBCLX: 0xf6, + UPDATX: 0xaf, + UPIENX: 0xae, + UPCFG2X: 0xad, + UPSTAX: 0xac, + UPCFG1X: 0xab, + UPCFG0X: 0xaa, + UPCONX: 0xa9, + UPRST: 0xa8, + UPNUM: 0xa7, + UPINTX: 0xa6, + UPINRQX: 0xa5, + UHFLEN: 0xa4, + UHFNUML: 0xa2, + UHFNUMH: 0xa2, + UHADDR: 0xa1, + UHIEN: 0xa0, + UHINT: 0x9f, + UHCON: 0x9e, + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Low Bytes + EEARH: 0x41, // EEPROM Address Register Low Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR3A __reg + TCCR3B __reg + TCCR3C __reg + TCNT3L __reg + TCNT3H __reg + OCR3AL __reg + OCR3AH __reg + OCR3BL __reg + OCR3BH __reg + OCR3CL __reg + OCR3CH __reg + ICR3L __reg + ICR3H __reg + TIMSK3 __reg + TIFR3 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + OCR1CL __reg + OCR1CH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR3A: 0x90, // Timer/Counter3 Control Register A + TCCR3B: 0x91, // Timer/Counter3 Control Register B + TCCR3C: 0x92, // Timer/Counter 3 Control Register C + TCNT3L: 0x94, // Timer/Counter3 Bytes + TCNT3H: 0x94, // Timer/Counter3 Bytes + OCR3AL: 0x98, // Timer/Counter3 Output Compare Register A Bytes + OCR3AH: 0x98, // Timer/Counter3 Output Compare Register A Bytes + OCR3BL: 0x9a, // Timer/Counter3 Output Compare Register B Bytes + OCR3BH: 0x9a, // Timer/Counter3 Output Compare Register B Bytes + OCR3CL: 0x9c, // Timer/Counter3 Output Compare Register B Bytes + OCR3CH: 0x9c, // Timer/Counter3 Output Compare Register B Bytes + ICR3L: 0x96, // Timer/Counter3 Input Capture Register Bytes + ICR3H: 0x96, // Timer/Counter3 Input Capture Register Bytes + TIMSK3: 0x71, // Timer/Counter3 Interrupt Mask Register + TIFR3: 0x38, // Timer/Counter3 Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1CL: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + OCR1CH: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EICRB __reg + EIMSK __reg + EIFR __reg + PCMSK0 __reg + PCIFR __reg + PCICR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EICRB: 0x6a, // External Interrupt Control Register B + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 1 + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, + } + + // Phase Locked Loop + PLL = struct { + PLLCSR __reg + }{ + PLLCSR: 0x49, // PLL Status and Control register + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level + EXTENDED_HWBE = 0x8 // Hardware Boot Enable + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTC7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // XMCRA: External Memory Control Register A + XMCRA_SRE = 0x80 // External SRAM Enable + XMCRA_SRL = 0x70 // Wait state page limit + XMCRA_SRW1 = 0xc // Wait state select bit upper page + XMCRA_SRW0 = 0x3 // Wait state select bit lower page + + // XMCRB: External Memory Control Register B + XMCRB_XMBK = 0x80 // External Memory Bus Keeper Enable + XMCRB_XMM = 0x7 // External Memory High Mask + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 + + // PRR1: Power Reduction Register1 + PRR1_PRUSB = 0x80 // Power Reduction USB + PRR1_PRTIM3 = 0x8 // Power Reduction Timer/Counter3 + PRR1_PRUSART1 = 0x1 // Power Reduction USART1 + + // PRR0: Power Reduction Register0 + PRR0_PRTWI = 0x80 // Power Reduction TWI + PRR0_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR0_PRADC = 0x1 // Power Reduction ADC +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for USART: USART +const ( + // UCSR1A: USART Control and Status Register A + UCSR1A_RXC1 = 0x80 // USART Receive Complete + UCSR1A_TXC1 = 0x40 // USART Transmitt Complete + UCSR1A_UDRE1 = 0x20 // USART Data Register Empty + UCSR1A_FE1 = 0x10 // Framing Error + UCSR1A_DOR1 = 0x8 // Data overRun + UCSR1A_UPE1 = 0x4 // Parity Error + UCSR1A_U2X1 = 0x2 // Double the USART transmission speed + UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode + + // UCSR1B: USART Control and Status Register B + UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable + UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable + UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable + UCSR1B_RXEN1 = 0x10 // Receiver Enable + UCSR1B_TXEN1 = 0x8 // Transmitter Enable + UCSR1B_UCSZ12 = 0x4 // Character Size + UCSR1B_RXB81 = 0x2 // Receive Data Bit 8 + UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8 + + // UCSR1C: USART Control and Status Register C + UCSR1C_UMSEL1 = 0xc0 // USART Mode Select + UCSR1C_UPM1 = 0x30 // Parity Mode Bits + UCSR1C_USBS1 = 0x8 // Stop Bit Select + UCSR1C_UCSZ1 = 0x6 // Character Size + UCSR1C_UCPOL1 = 0x1 // Clock Polarity +) + +// Bitfields for USB_DEVICE: USB Device Registers +const ( + // UEIENX + UEIENX_FLERRE = 0x80 + UEIENX_NAKINE = 0x40 + UEIENX_NAKOUTE = 0x10 + UEIENX_RXSTPE = 0x8 + UEIENX_RXOUTE = 0x4 + UEIENX_STALLEDE = 0x2 + UEIENX_TXINE = 0x1 + + // UESTA1X + UESTA1X_CTRLDIR = 0x4 + UESTA1X_CURRBK = 0x3 + + // UESTA0X + UESTA0X_CFGOK = 0x80 + UESTA0X_OVERFI = 0x40 + UESTA0X_UNDERFI = 0x20 + UESTA0X_DTSEQ = 0xc + UESTA0X_NBUSYBK = 0x3 + + // UECFG1X + UECFG1X_EPSIZE = 0x70 + UECFG1X_EPBK = 0xc + UECFG1X_ALLOC = 0x2 + + // UECFG0X + UECFG0X_EPTYPE = 0xc0 + UECFG0X_EPDIR = 0x1 + + // UECONX + UECONX_STALLRQ = 0x20 + UECONX_STALLRQC = 0x10 + UECONX_RSTDT = 0x8 + UECONX_EPEN = 0x1 + + // UERST + UERST_EPRST = 0x7f + + // UEINTX + UEINTX_FIFOCON = 0x80 + UEINTX_NAKINI = 0x40 + UEINTX_RWAL = 0x20 + UEINTX_NAKOUTI = 0x10 + UEINTX_RXSTPI = 0x8 + UEINTX_RXOUTI = 0x4 + UEINTX_STALLEDI = 0x2 + UEINTX_TXINI = 0x1 + + // UDMFN + UDMFN_FNCERR = 0x10 + + // UDADDR + UDADDR_ADDEN = 0x80 + UDADDR_UADD = 0x7f + + // UDIEN + UDIEN_UPRSME = 0x40 + UDIEN_EORSME = 0x20 + UDIEN_WAKEUPE = 0x10 + UDIEN_EORSTE = 0x8 + UDIEN_SOFE = 0x4 + UDIEN_SUSPE = 0x1 + + // UDINT + UDINT_UPRSMI = 0x40 + UDINT_EORSMI = 0x20 + UDINT_WAKEUPI = 0x10 + UDINT_EORSTI = 0x8 + UDINT_SOFI = 0x4 + UDINT_SUSPI = 0x1 + + // UDCON + UDCON_LSM = 0x4 + UDCON_RMWKUP = 0x2 + UDCON_DETACH = 0x1 +) + +// Bitfields for USB_GLOBAL: USB Controller +const ( + // OTGINT + OTGINT_STOI = 0x20 + OTGINT_HNPERRI = 0x10 + OTGINT_ROLEEXI = 0x8 + OTGINT_BCERRI = 0x4 + OTGINT_VBERRI = 0x2 + OTGINT_SRPI = 0x1 + + // OTGIEN + OTGIEN_STOE = 0x20 + OTGIEN_HNPERRE = 0x10 + OTGIEN_ROLEEXE = 0x8 + OTGIEN_BCERRE = 0x4 + OTGIEN_VBERRE = 0x2 + OTGIEN_SRPE = 0x1 + + // OTGCON + OTGCON_HNPREQ = 0x20 + OTGCON_SRPREQ = 0x10 + OTGCON_SRPSEL = 0x8 + OTGCON_VBUSHWC = 0x4 + OTGCON_VBUSREQ = 0x2 + OTGCON_VBUSRQC = 0x1 + + // OTGTCON + OTGTCON_OTGTCON_7 = 0x80 + OTGTCON_PAGE = 0x60 + OTGTCON_VALUE_2 = 0x7 + + // USBINT + USBINT_IDTI = 0x2 + USBINT_VBUSTI = 0x1 + + // USBSTA + USBSTA_SPEED = 0x8 + USBSTA_ID = 0x2 + USBSTA_VBUS = 0x1 + + // USBCON: USB General Control Register + USBCON_USBE = 0x80 + USBCON_HOST = 0x40 + USBCON_FRZCLK = 0x20 + USBCON_OTGPADE = 0x10 + USBCON_IDTE = 0x2 + USBCON_VBUSTE = 0x1 + + // UHWCON: USB Hardware Configuration Register + UHWCON_UIMOD = 0x80 + UHWCON_UIDE = 0x40 + UHWCON_UVCONE = 0x10 + UHWCON_UVREGE = 0x1 +) + +// Bitfields for USB_HOST: USB Host Registers +const ( + // UPERRX + UPERRX_COUNTER = 0x60 + UPERRX_CRC16 = 0x10 + UPERRX_TIMEOUT = 0x8 + UPERRX_PID = 0x4 + UPERRX_DATAPID = 0x2 + UPERRX_DATATGL = 0x1 + + // UPIENX + UPIENX_FLERRE = 0x80 + UPIENX_NAKEDE = 0x40 + UPIENX_PERRE = 0x10 + UPIENX_TXSTPE = 0x8 + UPIENX_TXOUTE = 0x4 + UPIENX_RXSTALLE = 0x2 + UPIENX_RXINE = 0x1 + + // UPSTAX + UPSTAX_CFGOK = 0x80 + UPSTAX_OVERFI = 0x40 + UPSTAX_UNDERFI = 0x20 + UPSTAX_DTSEQ = 0xc + UPSTAX_NBUSYK = 0x3 + + // UPCFG1X + UPCFG1X_PSIZE = 0x70 + UPCFG1X_PBK = 0xc + UPCFG1X_ALLOC = 0x2 + + // UPCFG0X + UPCFG0X_PTYPE = 0xc0 + UPCFG0X_PTOKEN = 0x30 + UPCFG0X_PEPNUM = 0xf + + // UPCONX + UPCONX_PFREEZE = 0x40 + UPCONX_INMODE = 0x20 + UPCONX_RSTDT = 0x8 + UPCONX_PEN = 0x1 + + // UPRST + UPRST_PRST = 0x7f + + // UPINTX + UPINTX_FIFOCON = 0x80 + UPINTX_NAKEDI = 0x40 + UPINTX_RWAL = 0x20 + UPINTX_PERRI = 0x10 + UPINTX_TXSTPI = 0x8 + UPINTX_TXOUTI = 0x4 + UPINTX_RXSTALLI = 0x2 + UPINTX_RXINI = 0x1 + + // UHIEN + UHIEN_HWUPE = 0x40 + UHIEN_HSOFE = 0x20 + UHIEN_RXRSME = 0x10 + UHIEN_RSMEDE = 0x8 + UHIEN_RSTE = 0x4 + UHIEN_DDISCE = 0x2 + UHIEN_DCONNE = 0x1 + + // UHINT + UHINT_UHUPI = 0x40 + UHINT_HSOFI = 0x20 + UHINT_RXRSMI = 0x10 + UHINT_RSMEDI = 0x8 + UHINT_RSTI = 0x4 + UHINT_DDISCI = 0x2 + UHINT_DCONNI = 0x1 + + // UHCON + UHCON_RESUME = 0x4 + UHCON_RESET = 0x2 + UHCON_SOFEN = 0x1 +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2B = 0x4 // Output Compare Flag 2B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Output Mode bits + TCCR2A_COM2B = 0x30 // Compare Output Mode bits + TCCR2A_WGM2 = 0x3 // Waveform Genration Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy + ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR3A: Timer/Counter3 Control Register A + TCCR3A_COM3A = 0xc0 // Compare Output Mode 1A, bits + TCCR3A_COM3B = 0x30 // Compare Output Mode 3B, bits + TCCR3A_COM3C = 0xc // Compare Output Mode 3C, bits + TCCR3A_WGM3 = 0x3 // Waveform Generation Mode + + // TCCR3B: Timer/Counter3 Control Register B + TCCR3B_ICNC3 = 0x80 // Input Capture 3 Noise Canceler + TCCR3B_ICES3 = 0x40 // Input Capture 3 Edge Select + TCCR3B_WGM3 = 0x18 // Waveform Generation Mode + TCCR3B_CS3 = 0x7 // Prescaler source of Timer/Counter 3 + + // TCCR3C: Timer/Counter 3 Control Register C + TCCR3C_FOC3A = 0x80 // Force Output Compare 3A + TCCR3C_FOC3B = 0x40 // Force Output Compare 3B + TCCR3C_FOC3C = 0x20 // Force Output Compare 3C + + // TIMSK3: Timer/Counter3 Interrupt Mask Register + TIMSK3_ICIE3 = 0x20 // Timer/Counter3 Input Capture Interrupt Enable + TIMSK3_OCIE3C = 0x8 // Timer/Counter3 Output Compare C Match Interrupt Enable + TIMSK3_OCIE3B = 0x4 // Timer/Counter3 Output Compare B Match Interrupt Enable + TIMSK3_OCIE3A = 0x2 // Timer/Counter3 Output Compare A Match Interrupt Enable + TIMSK3_TOIE3 = 0x1 // Timer/Counter3 Overflow Interrupt Enable + + // TIFR3: Timer/Counter3 Interrupt Flag register + TIFR3_ICF3 = 0x20 // Input Capture Flag 3 + TIFR3_OCF3C = 0x8 // Output Compare Flag 3C + TIFR3_OCF3B = 0x4 // Output Compare Flag 3B + TIFR3_OCF3A = 0x2 // Output Compare Flag 3A + TIFR3_TOV3 = 0x1 // Timer/Counter3 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_COM1C = 0xc // Compare Output Mode 1C, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + TCCR1C_FOC1C = 0x20 // Force Output Compare 1C + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1C = 0x8 // Timer/Counter1 Output Compare C Match Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1C = 0x8 // Output Compare Flag 1C + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EICRB: External Interrupt Control Register B + EICRB_ISC7 = 0xc0 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC6 = 0x30 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC5 = 0xc // External Interrupt 7-4 Sense Control Bit + EICRB_ISC4 = 0x3 // External Interrupt 7-4 Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xff // External Interrupt Request 7 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xff // External Interrupt Flags + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF0 = 0x1 // Pin Change Interrupt Flag 0 + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE0 = 0x1 // Pin Change Interrupt Enable 0 +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register 1 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for PLL: Phase Locked Loop +const ( + // PLLCSR: PLL Status and Control register + PLLCSR_PLLP = 0x1c // PLL prescaler Bits + PLLCSR_PLLE = 0x2 // PLL Enable Bit + PLLCSR_PLOCK = 0x1 // PLL Lock Status Bit +) diff --git a/src/device/avr/at90usb647.ld b/src/device/avr/at90usb647.ld new file mode 100644 index 00000000..9deb1602 --- /dev/null +++ b/src/device/avr/at90usb647.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from AT90USB647.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_size = 0x1000; +__num_isrs = 38; diff --git a/src/device/avr/at90usb82.go b/src/device/avr/at90usb82.go new file mode 100644 index 00000000..c050e774 --- /dev/null +++ b/src/device/avr/at90usb82.go @@ -0,0 +1,776 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from AT90USB82.atdf, see http://packs.download.atmel.com/ + +// +build avr,at90usb82 + +// Device information for the AT90USB82. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "AT90USB82" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_INT3 = 4 // External Interrupt Request 3 + IRQ_INT4 = 5 // External Interrupt Request 4 + IRQ_INT5 = 6 // External Interrupt Request 5 + IRQ_INT6 = 7 // External Interrupt Request 6 + IRQ_INT7 = 8 // External Interrupt Request 7 + IRQ_PCINT0 = 9 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 10 // Pin Change Interrupt Request 1 + IRQ_USB_GEN = 11 // USB General Interrupt Request + IRQ_USB_COM = 12 // USB Endpoint/Pipe Interrupt Communication Request + IRQ_WDT = 13 // Watchdog Time-out Interrupt + IRQ_TIMER1_CAPT = 14 // Timer/Counter2 Capture Event + IRQ_TIMER1_COMPA = 15 // Timer/Counter2 Compare Match B + IRQ_TIMER1_COMPB = 16 // Timer/Counter2 Compare Match B + IRQ_TIMER1_COMPC = 17 // Timer/Counter2 Compare Match C + IRQ_TIMER1_OVF = 18 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 19 // Timer/Counter0 Compare Match A + IRQ_TIMER0_COMPB = 20 // Timer/Counter0 Compare Match B + IRQ_TIMER0_OVF = 21 // Timer/Counter0 Overflow + IRQ_SPI_STC = 22 // SPI Serial Transfer Complete + IRQ_USART1_RX = 23 // USART1, Rx Complete + IRQ_USART1_UDRE = 24 // USART1 Data register Empty + IRQ_USART1_TX = 25 // USART1, Tx Complete + IRQ_ANALOG_COMP = 26 // Analog Comparator + IRQ_EE_READY = 27 // EEPROM Ready + IRQ_SPM_READY = 28 // Store Program Memory Read + IRQ_max = 28 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // I/O Port + PORT = struct { + PORTB __reg + DDRB __reg + PINB __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTC __reg + DDRC __reg + PINC __reg + }{ + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Low Bytes + EEARH: 0x41, // EEPROM Address Register Low Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + GTCCR __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + GTCCR: 0x43, // General Timer/Counter Control Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + OCR1CL __reg + OCR1CH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1CL: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + OCR1CH: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // Phase Locked Loop + PLL = struct { + PLLCSR __reg + }{ + PLLCSR: 0x49, // PLL Status and Control register + } + + // USB Device Registers + USB_DEVICE = struct { + UEINT __reg + UEBCLX __reg + UEDATX __reg + UEIENX __reg + UESTA1X __reg + UESTA0X __reg + UECFG1X __reg + UECFG0X __reg + UECONX __reg + UERST __reg + UENUM __reg + UEINTX __reg + UDMFN __reg + UDFNUML __reg + UDFNUMH __reg + UDADDR __reg + UDIEN __reg + UDINT __reg + UDCON __reg + USBCON __reg + REGCR __reg + }{ + UEINT: 0xf4, + UEBCLX: 0xf2, + UEDATX: 0xf1, + UEIENX: 0xf0, + UESTA1X: 0xef, + UESTA0X: 0xee, + UECFG1X: 0xed, + UECFG0X: 0xec, + UECONX: 0xeb, + UERST: 0xea, + UENUM: 0xe9, + UEINTX: 0xe8, + UDMFN: 0xe6, + UDFNUML: 0xe4, + UDFNUMH: 0xe4, + UDADDR: 0xe3, + UDIEN: 0xe2, + UDINT: 0xe1, + UDCON: 0xe0, + USBCON: 0xd8, // USB General Control Register + REGCR: 0x63, // Regulator Control Register + } + + // PS/2 Controller + PS2 = struct { + UPOE __reg + PS2CON __reg + }{ + UPOE: 0xfb, + PS2CON: 0xfa, // PS2 Pad Enable register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + MCUCR __reg + MCUSR __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + EIND __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PRR1 __reg + PRR0 __reg + CLKSTA __reg + CLKSEL1 __reg + CLKSEL0 __reg + DWDR __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, + SMCR: 0x53, // Sleep Mode Control Register + EIND: 0x5c, // Extended Indirect Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PRR1: 0x65, // Power Reduction Register1 + PRR0: 0x64, // Power Reduction Register0 + CLKSTA: 0xd2, + CLKSEL1: 0xd1, + CLKSEL0: 0xd0, + DWDR: 0x51, // debugWire communication register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EICRB __reg + EIMSK __reg + EIFR __reg + PCMSK0 __reg + PCMSK1 __reg + PCIFR __reg + PCICR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EICRB: 0x6a, // External Interrupt Control Register B + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + } + + // USART + USART = struct { + UDR1 __reg + UCSR1A __reg + UCSR1B __reg + UCSR1C __reg + UCSR1D __reg + UBRR1L __reg + UBRR1H __reg + }{ + UDR1: 0xce, // USART I/O Data Register + UCSR1A: 0xc8, // USART Control and Status Register A + UCSR1B: 0xc9, // USART Control and Status Register B + UCSR1C: 0xca, // USART Control and Status Register C + UCSR1D: 0xcb, // USART Control and Status Register D + UBRR1L: 0xcc, // USART Baud Rate Register Bytes + UBRR1H: 0xcc, // USART Baud Rate Register Bytes + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + WDTCKD __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + WDTCKD: 0x62, // Watchdog Timer Clock Divider + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level + EXTENDED_HWBE = 0x8 // Hardware Boot Enable + + // HIGH + HIGH_DWEN = 0x80 // Debug Wire enable + HIGH_RSTDISBL = 0x40 // Reset Disabled (Enable PC6 as i/o pin) + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTC7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for PORT: I/O Port +const ( + // PORTC: Port C Data Register + PORTC_PORTC = 0xf0 // Port C Data Register bits + PORTC_PORTC = 0x7 // Port C Data Register bits + + // DDRC: Port C Data Direction Register + DDRC_DDC = 0xf0 // Port C Data Direction Register bits + DDRC_DDC = 0x7 // Port C Data Direction Register bits + + // PINC: Port C Input Pins + PINC_PINC = 0xf0 // Port C Input Pins bits + PINC_PINC = 0x7 // Port C Input Pins bits +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag + + // GTCCR: General Timer/Counter Control Register + GTCCR_TSM = 0x80 // Timer/Counter Synchronization Mode + GTCCR_PSRSYNC = 0x1 // Prescaler Reset Timer/Counter1 and Timer/Counter0 +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_COM1C = 0xc // Compare Output Mode 1C, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + TCCR1C_FOC1C = 0x20 // Force Output Compare 1C + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1C = 0x8 // Timer/Counter1 Output Compare C Match Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1C = 0x8 // Output Compare Flag 1C + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for PLL: Phase Locked Loop +const ( + // PLLCSR: PLL Status and Control register + PLLCSR_PLLP = 0x1c // PLL prescaler Bits + PLLCSR_PLLE = 0x2 // PLL Enable Bit + PLLCSR_PLOCK = 0x1 // PLL Lock Status Bit +) + +// Bitfields for USB_DEVICE: USB Device Registers +const ( + // UEIENX + UEIENX_FLERRE = 0x80 + UEIENX_NAKINE = 0x40 + UEIENX_NAKOUTE = 0x10 + UEIENX_RXSTPE = 0x8 + UEIENX_RXOUTE = 0x4 + UEIENX_STALLEDE = 0x2 + UEIENX_TXINE = 0x1 + + // UESTA1X + UESTA1X_CTRLDIR = 0x4 + UESTA1X_CURRBK = 0x3 + + // UESTA0X + UESTA0X_CFGOK = 0x80 + UESTA0X_OVERFI = 0x40 + UESTA0X_UNDERFI = 0x20 + UESTA0X_DTSEQ = 0xc + UESTA0X_NBUSYBK = 0x3 + + // UECFG1X + UECFG1X_EPSIZE = 0x70 + UECFG1X_EPBK = 0xc + UECFG1X_ALLOC = 0x2 + + // UECFG0X + UECFG0X_EPTYPE = 0xc0 + UECFG0X_EPDIR = 0x1 + + // UECONX + UECONX_STALLRQ = 0x20 + UECONX_STALLRQC = 0x10 + UECONX_RSTDT = 0x8 + UECONX_EPEN = 0x1 + + // UERST + UERST_EPRST = 0x1f + + // UEINTX + UEINTX_FIFOCON = 0x80 + UEINTX_NAKINI = 0x40 + UEINTX_RWAL = 0x20 + UEINTX_NAKOUTI = 0x10 + UEINTX_RXSTPI = 0x8 + UEINTX_RXOUTI = 0x4 + UEINTX_STALLEDI = 0x2 + UEINTX_TXINI = 0x1 + + // UDMFN + UDMFN_FNCERR = 0x10 + + // UDADDR + UDADDR_ADDEN = 0x80 + UDADDR_UADD = 0x7f + + // UDIEN + UDIEN_UPRSME = 0x40 + UDIEN_EORSME = 0x20 + UDIEN_WAKEUPE = 0x10 + UDIEN_EORSTE = 0x8 + UDIEN_SOFE = 0x4 + UDIEN_SUSPE = 0x1 + + // UDINT + UDINT_UPRSMI = 0x40 + UDINT_EORSMI = 0x20 + UDINT_WAKEUPI = 0x10 + UDINT_EORSTI = 0x8 + UDINT_SOFI = 0x4 + UDINT_SUSPI = 0x1 + + // UDCON + UDCON_RSTCPU = 0x4 + UDCON_RMWKUP = 0x2 + UDCON_DETACH = 0x1 + + // USBCON: USB General Control Register + USBCON_USBE = 0x80 + USBCON_FRZCLK = 0x20 + + // REGCR: Regulator Control Register + REGCR_REGDIS = 0x1 +) + +// Bitfields for PS2: PS/2 Controller +const ( + // UPOE + UPOE_UPWE = 0xc0 + UPOE_UPDRV = 0x30 + UPOE_SCKI = 0x8 + UPOE_DATAI = 0x4 + UPOE_DPI = 0x2 + UPOE_DMI = 0x1 + + // PS2CON: PS2 Pad Enable register + PS2CON_PS2EN = 0x1 // Enable +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // MCUCR: MCU Control Register + MCUCR_PUD = 0x10 // Pull-up disable + MCUCR_IVSEL = 0x2 // Interrupt Vector Select + MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable + + // MCUSR: MCU Status Register + MCUSR_USBRF = 0x20 // USB reset flag + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BORF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 + + // PRR1: Power Reduction Register1 + PRR1_PRUSB = 0x80 // Power Reduction USB + PRR1_PRUSART1 = 0x1 // Power Reduction USART1 + + // PRR0: Power Reduction Register0 + PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + + // CLKSTA + CLKSTA_RCON = 0x2 + CLKSTA_EXTON = 0x1 + + // CLKSEL1 + CLKSEL1_RCCKSEL = 0xf0 + CLKSEL1_EXCKSEL = 0xf + + // CLKSEL0 + CLKSEL0_RCSUT = 0xc0 + CLKSEL0_EXSUT = 0x30 + CLKSEL0_RCE = 0x8 + CLKSEL0_EXTE = 0x4 + CLKSEL0_CLKS = 0x1 +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EICRB: External Interrupt Control Register B + EICRB_ISC7 = 0xc0 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC6 = 0x30 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC5 = 0xc // External Interrupt 7-4 Sense Control Bit + EICRB_ISC4 = 0x3 // External Interrupt 7-4 Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xff // External Interrupt Request 7 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xff // External Interrupt Flags + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0x1f + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0x3 // Pin Change Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0x3 // Pin Change Interrupt Enables +) + +// Bitfields for USART: USART +const ( + // UCSR1A: USART Control and Status Register A + UCSR1A_RXC1 = 0x80 // USART Receive Complete + UCSR1A_TXC1 = 0x40 // USART Transmitt Complete + UCSR1A_UDRE1 = 0x20 // USART Data Register Empty + UCSR1A_FE1 = 0x10 // Framing Error + UCSR1A_DOR1 = 0x8 // Data overRun + UCSR1A_UPE1 = 0x4 // Parity Error + UCSR1A_U2X1 = 0x2 // Double the USART transmission speed + UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode + + // UCSR1B: USART Control and Status Register B + UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable + UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable + UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable + UCSR1B_RXEN1 = 0x10 // Receiver Enable + UCSR1B_TXEN1 = 0x8 // Transmitter Enable + UCSR1B_UCSZ12 = 0x4 // Character Size + UCSR1B_RXB81 = 0x2 // Receive Data Bit 8 + UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8 + + // UCSR1C: USART Control and Status Register C + UCSR1C_UMSEL1 = 0xc0 // USART Mode Select + UCSR1C_UPM1 = 0x30 // Parity Mode Bits + UCSR1C_USBS1 = 0x8 // Stop Bit Select + UCSR1C_UCSZ1 = 0x6 // Character Size + UCSR1C_UCPOL1 = 0x1 // Clock Polarity + + // UCSR1D: USART Control and Status Register D + UCSR1D_CTSEN = 0x2 // CTS Enable + UCSR1D_RTSEN = 0x1 // RTS Enable +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable + + // WDTCKD: Watchdog Timer Clock Divider + WDTCKD_WDEWIF = 0x8 // Watchdog Early Warning Interrupt Flag + WDTCKD_WDEWIE = 0x4 // Watchdog Early Warning Interrupt Enable + WDTCKD_WCLKD = 0x3 // Watchdog Timer Clock Dividers +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) diff --git a/src/device/avr/at90usb82.ld b/src/device/avr/at90usb82.ld new file mode 100644 index 00000000..95b2d793 --- /dev/null +++ b/src/device/avr/at90usb82.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from AT90USB82.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_size = 0x200; +__num_isrs = 29; diff --git a/src/device/avr/atmega128.go b/src/device/avr/atmega128.go new file mode 100644 index 00000000..c5281415 --- /dev/null +++ b/src/device/avr/atmega128.go @@ -0,0 +1,676 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega128.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega128 + +// Device information for the ATmega128. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega128" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_INT3 = 4 // External Interrupt Request 3 + IRQ_INT4 = 5 // External Interrupt Request 4 + IRQ_INT5 = 6 // External Interrupt Request 5 + IRQ_INT6 = 7 // External Interrupt Request 6 + IRQ_INT7 = 8 // External Interrupt Request 7 + IRQ_TIMER2_COMP = 9 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 10 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 11 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 12 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 13 // Timer/Counter Compare Match B + IRQ_TIMER1_OVF = 14 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 15 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 16 // Timer/Counter0 Overflow + IRQ_SPI_STC = 17 // SPI Serial Transfer Complete + IRQ_USART0_RX = 18 // USART0, Rx Complete + IRQ_USART0_UDRE = 19 // USART0 Data Register Empty + IRQ_USART0_TX = 20 // USART0, Tx Complete + IRQ_ADC = 21 // ADC Conversion Complete + IRQ_EE_READY = 22 // EEPROM Ready + IRQ_ANALOG_COMP = 23 // Analog Comparator + IRQ_TIMER1_COMPC = 24 // Timer/Counter1 Compare Match C + IRQ_TIMER3_CAPT = 25 // Timer/Counter3 Capture Event + IRQ_TIMER3_COMPA = 26 // Timer/Counter3 Compare Match A + IRQ_TIMER3_COMPB = 27 // Timer/Counter3 Compare Match B + IRQ_TIMER3_COMPC = 28 // Timer/Counter3 Compare Match C + IRQ_TIMER3_OVF = 29 // Timer/Counter3 Overflow + IRQ_USART1_RX = 30 // USART1, Rx Complete + IRQ_USART1_UDRE = 31 // USART1, Data Register Empty + IRQ_USART1_TX = 32 // USART1, Tx Complete + IRQ_TWI = 33 // 2-wire Serial Interface + IRQ_SPM_READY = 34 // Store Program Memory Read + IRQ_max = 34 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog Comparator + AC = struct { + ACSR __reg + }{ + ACSR: 0x28, // Analog Comparator Control And Status Register + } + + // Serial Peripheral Interface + SPI = struct { + SPDR __reg + SPSR __reg + SPCR __reg + }{ + SPDR: 0x2f, // SPI Data Register + SPSR: 0x2e, // SPI Status Register + SPCR: 0x2d, // SPI Control Register + } + + // Two Wire Serial Interface + TWI = struct { + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWBR: 0x70, // TWI Bit Rate register + TWCR: 0x74, // TWI Control Register + TWSR: 0x71, // TWI Status Register + TWDR: 0x73, // TWI Data register + TWAR: 0x72, // TWI (Slave) Address register + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0H __reg + UBRR0L __reg + UDR1 __reg + UCSR1A __reg + UCSR1B __reg + UCSR1C __reg + UBRR1H __reg + UBRR1L __reg + }{ + UDR0: 0x2c, // USART I/O Data Register + UCSR0A: 0x2b, // USART Control and Status Register A + UCSR0B: 0x2a, // USART Control and Status Register B + UCSR0C: 0x95, // USART Control and Status Register C + UBRR0H: 0x90, // USART Baud Rate Register Hight Byte + UBRR0L: 0x29, // USART Baud Rate Register Low Byte + UDR1: 0x9c, // USART I/O Data Register + UCSR1A: 0x9b, // USART Control and Status Register A + UCSR1B: 0x9a, // USART Control and Status Register B + UCSR1C: 0x9d, // USART Control and Status Register C + UBRR1H: 0x98, // USART Baud Rate Register Hight Byte + UBRR1L: 0x99, // USART Baud Rate Register Low Byte + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + MCUCR __reg + XDIV __reg + XMCRA __reg + XMCRB __reg + OSCCAL __reg + RAMPZ __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + MCUCR: 0x55, // MCU Control Register + XDIV: 0x5c, // XTAL Divide Control Register + XMCRA: 0x6d, // External Memory Control Register A + XMCRB: 0x6c, // External Memory Control Register B + OSCCAL: 0x6f, // Oscillator Calibration Value + RAMPZ: 0x5b, // RAM Page Z Select Register + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x68, // Store Program Memory Control Register + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x42, // On-Chip Debug Related Register in I/O Memory + } + + // Other Registers + MISC = struct { + }{} + + // External Interrupts + EXINT = struct { + EICRA __reg + EICRB __reg + EIMSK __reg + EIFR __reg + }{ + EICRA: 0x6a, // External Interrupt Control Register A + EICRB: 0x5a, // External Interrupt Control Register B + EIMSK: 0x59, // External Interrupt Mask Register + EIFR: 0x58, // External Interrupt Flag Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x3e, // EEPROM Read/Write Access Bytes + EEARH: 0x3e, // EEPROM Read/Write Access Bytes + EEDR: 0x3d, // EEPROM Data Register + EECR: 0x3c, // EEPROM Control Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + }{ + PORTA: 0x3b, // Port A Data Register + DDRA: 0x3a, // Port A Data Direction Register + PINA: 0x39, // Port A Input Pins + PORTB: 0x38, // Port B Data Register + DDRB: 0x37, // Port B Data Direction Register + PINB: 0x36, // Port B Input Pins + PORTC: 0x35, // Port C Data Register + DDRC: 0x34, // Port C Data Direction Register + PINC: 0x33, // Port C Input Pins + PORTD: 0x32, // Port D Data Register + DDRD: 0x31, // Port D Data Direction Register + PIND: 0x30, // Port D Input Pins + PORTE: 0x23, // Data Register, Port E + DDRE: 0x22, // Data Direction Register, Port E + PINE: 0x21, // Input Pins, Port E + PORTF: 0x62, // Data Register, Port F + DDRF: 0x61, // Data Direction Register, Port F + PINF: 0x20, // Input Pins, Port F + PORTG: 0x65, // Data Register, Port G + DDRG: 0x64, // Data Direction Register, Port G + PING: 0x63, // Input Pins, Port G + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR0 __reg + TCNT0 __reg + OCR0 __reg + ASSR __reg + }{ + TCCR0: 0x53, // Timer/Counter Control Register + TCNT0: 0x52, // Timer/Counter Register + OCR0: 0x51, // Output Compare Register + ASSR: 0x50, // Asynchronus Status Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + OCR1CL __reg + OCR1CH __reg + ICR1L __reg + ICR1H __reg + TCCR3A __reg + TCCR3B __reg + TCCR3C __reg + TCNT3L __reg + TCNT3H __reg + OCR3AL __reg + OCR3AH __reg + OCR3BL __reg + OCR3BH __reg + OCR3CL __reg + OCR3CH __reg + ICR3L __reg + ICR3H __reg + }{ + TCCR1A: 0x4f, // Timer/Counter1 Control Register A + TCCR1B: 0x4e, // Timer/Counter1 Control Register B + TCCR1C: 0x7a, // Timer/Counter1 Control Register C + TCNT1L: 0x4c, // Timer/Counter1 Bytes + TCNT1H: 0x4c, // Timer/Counter1 Bytes + OCR1AL: 0x4a, // Timer/Counter1 Output Compare Register Bytes + OCR1AH: 0x4a, // Timer/Counter1 Output Compare Register Bytes + OCR1BL: 0x48, // Timer/Counter1 Output Compare Register Bytes + OCR1BH: 0x48, // Timer/Counter1 Output Compare Register Bytes + OCR1CL: 0x78, // Timer/Counter1 Output Compare Register Bytes + OCR1CH: 0x78, // Timer/Counter1 Output Compare Register Bytes + ICR1L: 0x46, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x46, // Timer/Counter1 Input Capture Register Bytes + TCCR3A: 0x8b, // Timer/Counter3 Control Register A + TCCR3B: 0x8a, // Timer/Counter3 Control Register B + TCCR3C: 0x8c, // Timer/Counter3 Control Register C + TCNT3L: 0x88, // Timer/Counter3 Bytes + TCNT3H: 0x88, // Timer/Counter3 Bytes + OCR3AL: 0x86, // Timer/Counter3 Output Compare Register A Bytes + OCR3AH: 0x86, // Timer/Counter3 Output Compare Register A Bytes + OCR3BL: 0x84, // Timer/Counter3 Output Compare Register B Bytes + OCR3BH: 0x84, // Timer/Counter3 Output Compare Register B Bytes + OCR3CL: 0x82, // Timer/Counter3 Output compare Register C Bytes + OCR3CH: 0x82, // Timer/Counter3 Output compare Register C Bytes + ICR3L: 0x80, // Timer/Counter3 Input Capture Register Bytes + ICR3H: 0x80, // Timer/Counter3 Input Capture Register Bytes + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR2 __reg + TCNT2 __reg + OCR2 __reg + }{ + TCCR2: 0x45, // Timer/Counter Control Register + TCNT2: 0x44, // Timer/Counter Register + OCR2: 0x43, // Output Compare Register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x41, // Watchdog Timer Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + }{ + ADMUX: 0x27, // The ADC multiplexer Selection Register + ADCSRA: 0x26, // The ADC Control and Status register + ADCL: 0x24, // ADC Data Register Bytes + ADCH: 0x24, // ADC Data Register Bytes + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_M103C = 0x2 // ATmega103 Compatibility Mode + EXTENDED_WDTON = 0x1 // Watchdog Timer always on + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + HIGH_CKOPT = 0x10 // CKOPT fuse (operation dependent of CKSEL fuses) + + // LOW + LOW_BODLEVEL = 0x80 // Brownout detector trigger level + LOW_BODEN = 0x40 // Brown-out detection enabled + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0x40 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity + + // UCSR1A: USART Control and Status Register A + UCSR1A_RXC1 = 0x80 // USART Receive Complete + UCSR1A_TXC1 = 0x40 // USART Transmitt Complete + UCSR1A_UDRE1 = 0x20 // USART Data Register Empty + UCSR1A_FE1 = 0x10 // Framing Error + UCSR1A_DOR1 = 0x8 // Data overRun + UCSR1A_UPE1 = 0x4 // Parity Error + UCSR1A_U2X1 = 0x2 // Double the USART transmission speed + UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode + + // UCSR1B: USART Control and Status Register B + UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable + UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable + UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable + UCSR1B_RXEN1 = 0x10 // Receiver Enable + UCSR1B_TXEN1 = 0x8 // Transmitter Enable + UCSR1B_UCSZ12 = 0x4 // Character Size + UCSR1B_RXB81 = 0x2 // Receive Data Bit 8 + UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8 + + // UCSR1C: USART Control and Status Register C + UCSR1C_UMSEL1 = 0x40 // USART Mode Select + UCSR1C_UPM1 = 0x30 // Parity Mode Bits + UCSR1C_USBS1 = 0x8 // Stop Bit Select + UCSR1C_UCSZ1 = 0x6 // Character Size + UCSR1C_UCPOL1 = 0x1 // Clock Polarity +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // MCUCR: MCU Control Register + MCUCR_SRE = 0x80 // External SRAM Enable + MCUCR_SRW10 = 0x40 // External SRAM Wait State Select + MCUCR_SE = 0x20 // Sleep Enable + MCUCR_SM = 0x18 // Sleep Mode Select + MCUCR_SM2 = 0x4 // Sleep Mode Select + MCUCR_IVSEL = 0x2 // Interrupt Vector Select + MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable + + // XDIV: XTAL Divide Control Register + XDIV_XDIVEN = 0x80 // XTAL Divide Enable + XDIV_XDIV6 = 0x40 // XTAL Divide Select Bit 6 + XDIV_XDIV5 = 0x20 // XTAL Divide Select Bit 5 + XDIV_XDIV4 = 0x10 // XTAL Divide Select Bit 4 + XDIV_XDIV3 = 0x8 // XTAL Divide Select Bit 3 + XDIV_XDIV2 = 0x4 // XTAL Divide Select Bit 2 + XDIV_XDIV1 = 0x2 // XTAL Divide Select Bit 1 + XDIV_XDIV0 = 0x1 // XTAL Divide Select Bit 0 + + // XMCRA: External Memory Control Register A + XMCRA_SRL = 0x70 // Wait state page limit + XMCRA_SRW0 = 0xc // Wait state select bit lower page + XMCRA_SRW11 = 0x2 // Wait state select bit upper page + + // XMCRB: External Memory Control Register B + XMCRB_XMBK = 0x80 // External Memory Bus Keeper Enable + XMCRB_XMM = 0x7 // External Memory High Mask + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // RAMPZ: RAM Page Z Select Register + RAMPZ_RAMPZ0 = 0x1 // RAM Page Z Select Register Bit 0 +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for JTAG: JTAG Interface +const ( + // OCDR: On-Chip Debug Related Register in I/O Memory + OCDR_OCDR = 0xff // On-Chip Debug Register Bits +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EICRB: External Interrupt Control Register B + EICRB_ISC7 = 0xc0 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC6 = 0x30 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC5 = 0xc // External Interrupt 7-4 Sense Control Bit + EICRB_ISC4 = 0x3 // External Interrupt 7-4 Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xff // External Interrupt Request 7 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xff // External Interrupt Flags +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR0: Timer/Counter Control Register + TCCR0_FOC0 = 0x80 // Force Output Compare + TCCR0_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0_COM0 = 0x30 // Compare Match Output Modes + TCCR0_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0_CS0 = 0x7 // Clock Selects + + // ASSR: Asynchronus Status Register + ASSR_AS0 = 0x8 // Asynchronus Timer/Counter 0 + ASSR_TCN0UB = 0x4 // Timer/Counter0 Update Busy + ASSR_OCR0UB = 0x2 // Output Compare register 0 Busy + ASSR_TCR0UB = 0x1 // Timer/Counter Control Register 0 Update Busy +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_COM1C = 0xc // Compare Output Mode 1C, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode Bits + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Clock Select1 bits + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare for channel A + TCCR1C_FOC1B = 0x40 // Force Output Compare for channel B + TCCR1C_FOC1C = 0x20 // Force Output Compare for channel C + + // TCCR3A: Timer/Counter3 Control Register A + TCCR3A_COM3A = 0xc0 // Compare Output Mode 3A, bits + TCCR3A_COM3B = 0x30 // Compare Output Mode 3B, bits + TCCR3A_COM3C = 0xc // Compare Output Mode 3C, bits + TCCR3A_WGM3 = 0x3 // Waveform Generation Mode Bits + + // TCCR3B: Timer/Counter3 Control Register B + TCCR3B_ICNC3 = 0x80 // Input Capture 3 Noise Canceler + TCCR3B_ICES3 = 0x40 // Input Capture 3 Edge Select + TCCR3B_WGM3 = 0x18 // Waveform Generation Mode + TCCR3B_CS3 = 0x7 // Clock Select3 bits + + // TCCR3C: Timer/Counter3 Control Register C + TCCR3C_FOC3A = 0x80 // Force Output Compare for channel A + TCCR3C_FOC3B = 0x40 // Force Output Compare for channel B + TCCR3C_FOC3C = 0x20 // Force Output Compare for channel C +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR2: Timer/Counter Control Register + TCCR2_FOC2 = 0x80 // Force Output Compare + TCCR2_WGM20 = 0x40 // Wafeform Generation Mode + TCCR2_COM2 = 0x30 // Compare Match Output Mode + TCCR2_WGM21 = 0x8 // Waveform Generation Mode + TCCR2_CS2 = 0x7 // Clock Select +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADFR = 0x20 // ADC Free Running Select + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits +) diff --git a/src/device/avr/atmega128.ld b/src/device/avr/atmega128.ld new file mode 100644 index 00000000..138d9db7 --- /dev/null +++ b/src/device/avr/atmega128.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega128.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x20000; +__ram_size = 0x1000; +__num_isrs = 35; diff --git a/src/device/avr/atmega1280.go b/src/device/avr/atmega1280.go new file mode 100644 index 00000000..bfb2141b --- /dev/null +++ b/src/device/avr/atmega1280.go @@ -0,0 +1,1090 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega1280.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega1280 + +// Device information for the ATmega1280. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega1280" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_INT3 = 4 // External Interrupt Request 3 + IRQ_INT4 = 5 // External Interrupt Request 4 + IRQ_INT5 = 6 // External Interrupt Request 5 + IRQ_INT6 = 7 // External Interrupt Request 6 + IRQ_INT7 = 8 // External Interrupt Request 7 + IRQ_PCINT0 = 9 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 10 // Pin Change Interrupt Request 1 + IRQ_PCINT2 = 11 // Pin Change Interrupt Request 2 + IRQ_WDT = 12 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 13 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 14 // Timer/Counter2 Compare Match B + IRQ_TIMER2_OVF = 15 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 16 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 17 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 18 // Timer/Counter1 Compare Match B + IRQ_TIMER1_COMPC = 19 // Timer/Counter1 Compare Match C + IRQ_TIMER1_OVF = 20 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 21 // Timer/Counter0 Compare Match A + IRQ_TIMER0_COMPB = 22 // Timer/Counter0 Compare Match B + IRQ_TIMER0_OVF = 23 // Timer/Counter0 Overflow + IRQ_SPI_STC = 24 // SPI Serial Transfer Complete + IRQ_USART0_RX = 25 // USART0, Rx Complete + IRQ_USART0_UDRE = 26 // USART0 Data register Empty + IRQ_USART0_TX = 27 // USART0, Tx Complete + IRQ_ANALOG_COMP = 28 // Analog Comparator + IRQ_ADC = 29 // ADC Conversion Complete + IRQ_EE_READY = 30 // EEPROM Ready + IRQ_TIMER3_CAPT = 31 // Timer/Counter3 Capture Event + IRQ_TIMER3_COMPA = 32 // Timer/Counter3 Compare Match A + IRQ_TIMER3_COMPB = 33 // Timer/Counter3 Compare Match B + IRQ_TIMER3_COMPC = 34 // Timer/Counter3 Compare Match C + IRQ_TIMER3_OVF = 35 // Timer/Counter3 Overflow + IRQ_USART1_RX = 36 // USART1, Rx Complete + IRQ_USART1_UDRE = 37 // USART1 Data register Empty + IRQ_USART1_TX = 38 // USART1, Tx Complete + IRQ_TWI = 39 // 2-wire Serial Interface + IRQ_SPM_READY = 40 // Store Program Memory Read + IRQ_TIMER4_CAPT = 41 // Timer/Counter4 Capture Event + IRQ_TIMER4_COMPA = 42 // Timer/Counter4 Compare Match A + IRQ_TIMER4_COMPB = 43 // Timer/Counter4 Compare Match B + IRQ_TIMER4_COMPC = 44 // Timer/Counter4 Compare Match C + IRQ_TIMER4_OVF = 45 // Timer/Counter4 Overflow + IRQ_TIMER5_CAPT = 46 // Timer/Counter5 Capture Event + IRQ_TIMER5_COMPA = 47 // Timer/Counter5 Compare Match A + IRQ_TIMER5_COMPB = 48 // Timer/Counter5 Compare Match B + IRQ_TIMER5_COMPC = 49 // Timer/Counter5 Compare Match C + IRQ_TIMER5_OVF = 50 // Timer/Counter5 Overflow + IRQ_USART2_RX = 51 // USART2, Rx Complete + IRQ_USART2_UDRE = 52 // USART2 Data register Empty + IRQ_USART2_TX = 53 // USART2, Tx Complete + IRQ_USART3_RX = 54 // USART3, Rx Complete + IRQ_USART3_UDRE = 55 // USART3 Data register Empty + IRQ_USART3_TX = 56 // USART3, Tx Complete + IRQ_max = 56 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + UDR1 __reg + UCSR1A __reg + UCSR1B __reg + UCSR1C __reg + UBRR1L __reg + UBRR1H __reg + UDR2 __reg + UCSR2A __reg + UCSR2B __reg + UCSR2C __reg + UBRR2L __reg + UBRR2H __reg + UDR3 __reg + UCSR3A __reg + UCSR3B __reg + UCSR3C __reg + UBRR3L __reg + UBRR3H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + UDR1: 0xce, // USART I/O Data Register + UCSR1A: 0xc8, // USART Control and Status Register A + UCSR1B: 0xc9, // USART Control and Status Register B + UCSR1C: 0xca, // USART Control and Status Register C + UBRR1L: 0xcc, // USART Baud Rate Register Bytes + UBRR1H: 0xcc, // USART Baud Rate Register Bytes + UDR2: 0xd6, // USART I/O Data Register + UCSR2A: 0xd0, // USART Control and Status Register A + UCSR2B: 0xd1, // USART Control and Status Register B + UCSR2C: 0xd2, // USART Control and Status Register C + UBRR2L: 0xd4, // USART Baud Rate Register Bytes + UBRR2H: 0xd4, // USART Baud Rate Register Bytes + UDR3: 0x136, // USART I/O Data Register + UCSR3A: 0x130, // USART Control and Status Register A + UCSR3B: 0x131, // USART Control and Status Register B + UCSR3C: 0x132, // USART Control and Status Register C + UBRR3L: 0x134, // USART Baud Rate Register Bytes + UBRR3H: 0x134, // USART Baud Rate Register Bytes + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + PORTH __reg + DDRH __reg + PINH __reg + PORTJ __reg + DDRJ __reg + PINJ __reg + PORTK __reg + DDRK __reg + PINK __reg + PORTL __reg + DDRL __reg + PINL __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + PORTG: 0x34, // Data Register, Port G + DDRG: 0x33, // Data Direction Register, Port G + PING: 0x32, // Input Pins, Port G + PORTH: 0x102, // PORT H Data Register + DDRH: 0x101, // PORT H Data Direction Register + PINH: 0x100, // PORT H Input Pins + PORTJ: 0x105, // PORT J Data Register + DDRJ: 0x104, // PORT J Data Direction Register + PINJ: 0x103, // PORT J Input Pins + PORTK: 0x108, // PORT K Data Register + DDRK: 0x107, // PORT K Data Direction Register + PINK: 0x106, // PORT K Input Pins + PORTL: 0x10b, // PORT L Data Register + DDRL: 0x10a, // PORT L Data Direction Register + PINL: 0x109, // PORT L Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Low Bytes + EEARH: 0x41, // EEPROM Address Register Low Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR5A __reg + TCCR5B __reg + TCCR5C __reg + TCNT5L __reg + TCNT5H __reg + OCR5AL __reg + OCR5AH __reg + OCR5BL __reg + OCR5BH __reg + OCR5CL __reg + OCR5CH __reg + ICR5L __reg + ICR5H __reg + TIMSK5 __reg + TIFR5 __reg + TCCR4A __reg + TCCR4B __reg + TCCR4C __reg + TCNT4L __reg + TCNT4H __reg + OCR4AL __reg + OCR4AH __reg + OCR4BL __reg + OCR4BH __reg + OCR4CL __reg + OCR4CH __reg + ICR4L __reg + ICR4H __reg + TIMSK4 __reg + TIFR4 __reg + TCCR3A __reg + TCCR3B __reg + TCCR3C __reg + TCNT3L __reg + TCNT3H __reg + OCR3AL __reg + OCR3AH __reg + OCR3BL __reg + OCR3BH __reg + OCR3CL __reg + OCR3CH __reg + ICR3L __reg + ICR3H __reg + TIMSK3 __reg + TIFR3 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + OCR1CL __reg + OCR1CH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR5A: 0x120, // Timer/Counter5 Control Register A + TCCR5B: 0x121, // Timer/Counter5 Control Register B + TCCR5C: 0x122, // Timer/Counter 5 Control Register C + TCNT5L: 0x124, // Timer/Counter5 Bytes + TCNT5H: 0x124, // Timer/Counter5 Bytes + OCR5AL: 0x128, // Timer/Counter5 Output Compare Register A Bytes + OCR5AH: 0x128, // Timer/Counter5 Output Compare Register A Bytes + OCR5BL: 0x12a, // Timer/Counter5 Output Compare Register B Bytes + OCR5BH: 0x12a, // Timer/Counter5 Output Compare Register B Bytes + OCR5CL: 0x12c, // Timer/Counter5 Output Compare Register B Bytes + OCR5CH: 0x12c, // Timer/Counter5 Output Compare Register B Bytes + ICR5L: 0x126, // Timer/Counter5 Input Capture Register Bytes + ICR5H: 0x126, // Timer/Counter5 Input Capture Register Bytes + TIMSK5: 0x73, // Timer/Counter5 Interrupt Mask Register + TIFR5: 0x3a, // Timer/Counter5 Interrupt Flag register + TCCR4A: 0xa0, // Timer/Counter4 Control Register A + TCCR4B: 0xa1, // Timer/Counter4 Control Register B + TCCR4C: 0xa2, // Timer/Counter 4 Control Register C + TCNT4L: 0xa4, // Timer/Counter4 Bytes + TCNT4H: 0xa4, // Timer/Counter4 Bytes + OCR4AL: 0xa8, // Timer/Counter4 Output Compare Register A Bytes + OCR4AH: 0xa8, // Timer/Counter4 Output Compare Register A Bytes + OCR4BL: 0xaa, // Timer/Counter4 Output Compare Register B Bytes + OCR4BH: 0xaa, // Timer/Counter4 Output Compare Register B Bytes + OCR4CL: 0xac, // Timer/Counter4 Output Compare Register B Bytes + OCR4CH: 0xac, // Timer/Counter4 Output Compare Register B Bytes + ICR4L: 0xa6, // Timer/Counter4 Input Capture Register Bytes + ICR4H: 0xa6, // Timer/Counter4 Input Capture Register Bytes + TIMSK4: 0x72, // Timer/Counter4 Interrupt Mask Register + TIFR4: 0x39, // Timer/Counter4 Interrupt Flag register + TCCR3A: 0x90, // Timer/Counter3 Control Register A + TCCR3B: 0x91, // Timer/Counter3 Control Register B + TCCR3C: 0x92, // Timer/Counter 3 Control Register C + TCNT3L: 0x94, // Timer/Counter3 Bytes + TCNT3H: 0x94, // Timer/Counter3 Bytes + OCR3AL: 0x98, // Timer/Counter3 Output Compare Register A Bytes + OCR3AH: 0x98, // Timer/Counter3 Output Compare Register A Bytes + OCR3BL: 0x9a, // Timer/Counter3 Output Compare Register B Bytes + OCR3BH: 0x9a, // Timer/Counter3 Output Compare Register B Bytes + OCR3CL: 0x9c, // Timer/Counter3 Output Compare Register B Bytes + OCR3CH: 0x9c, // Timer/Counter3 Output Compare Register B Bytes + ICR3L: 0x96, // Timer/Counter3 Input Capture Register Bytes + ICR3H: 0x96, // Timer/Counter3 Input Capture Register Bytes + TIMSK3: 0x71, // Timer/Counter3 Interrupt Mask Register + TIFR3: 0x38, // Timer/Counter3 Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1CL: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + OCR1CH: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EICRB __reg + EIMSK __reg + EIFR __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + PCICR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EICRB: 0x6a, // External Interrupt Control Register B + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + XMCRA __reg + XMCRB __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + EIND __reg + RAMPZ __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PRR1 __reg + PRR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + XMCRA: 0x74, // External Memory Control Register A + XMCRB: 0x75, // External Memory Control Register B + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, + SMCR: 0x53, // Sleep Mode Control Register + EIND: 0x5c, // Extended Indirect Register + RAMPZ: 0x5b, // RAM Page Z Select Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PRR1: 0x65, // Power Reduction Register1 + PRR0: 0x64, // Power Reduction Register0 + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + DIDR2 __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // The ADC Control and Status register A + DIDR2: 0x7d, // Digital Input Disable Register + DIDR0: 0x7e, // Digital Input Disable Register + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0xc0 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity + + // UCSR1A: USART Control and Status Register A + UCSR1A_RXC1 = 0x80 // USART Receive Complete + UCSR1A_TXC1 = 0x40 // USART Transmitt Complete + UCSR1A_UDRE1 = 0x20 // USART Data Register Empty + UCSR1A_FE1 = 0x10 // Framing Error + UCSR1A_DOR1 = 0x8 // Data overRun + UCSR1A_UPE1 = 0x4 // Parity Error + UCSR1A_U2X1 = 0x2 // Double the USART transmission speed + UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode + + // UCSR1B: USART Control and Status Register B + UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable + UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable + UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable + UCSR1B_RXEN1 = 0x10 // Receiver Enable + UCSR1B_TXEN1 = 0x8 // Transmitter Enable + UCSR1B_UCSZ12 = 0x4 // Character Size + UCSR1B_RXB81 = 0x2 // Receive Data Bit 8 + UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8 + + // UCSR1C: USART Control and Status Register C + UCSR1C_UMSEL1 = 0xc0 // USART Mode Select + UCSR1C_UPM1 = 0x30 // Parity Mode Bits + UCSR1C_USBS1 = 0x8 // Stop Bit Select + UCSR1C_UCSZ1 = 0x6 // Character Size + UCSR1C_UCPOL1 = 0x1 // Clock Polarity + + // UCSR2A: USART Control and Status Register A + UCSR2A_RXC2 = 0x80 // USART Receive Complete + UCSR2A_TXC2 = 0x40 // USART Transmitt Complete + UCSR2A_UDRE2 = 0x20 // USART Data Register Empty + UCSR2A_FE2 = 0x10 // Framing Error + UCSR2A_DOR2 = 0x8 // Data overRun + UCSR2A_UPE2 = 0x4 // Parity Error + UCSR2A_U2X2 = 0x2 // Double the USART transmission speed + UCSR2A_MPCM2 = 0x1 // Multi-processor Communication Mode + + // UCSR2B: USART Control and Status Register B + UCSR2B_RXCIE2 = 0x80 // RX Complete Interrupt Enable + UCSR2B_TXCIE2 = 0x40 // TX Complete Interrupt Enable + UCSR2B_UDRIE2 = 0x20 // USART Data register Empty Interrupt Enable + UCSR2B_RXEN2 = 0x10 // Receiver Enable + UCSR2B_TXEN2 = 0x8 // Transmitter Enable + UCSR2B_UCSZ22 = 0x4 // Character Size + UCSR2B_RXB82 = 0x2 // Receive Data Bit 8 + UCSR2B_TXB82 = 0x1 // Transmit Data Bit 8 + + // UCSR2C: USART Control and Status Register C + UCSR2C_UMSEL2 = 0xc0 // USART Mode Select + UCSR2C_UPM2 = 0x30 // Parity Mode Bits + UCSR2C_USBS2 = 0x8 // Stop Bit Select + UCSR2C_UCSZ2 = 0x6 // Character Size + UCSR2C_UCPOL2 = 0x1 // Clock Polarity + + // UCSR3A: USART Control and Status Register A + UCSR3A_RXC3 = 0x80 // USART Receive Complete + UCSR3A_TXC3 = 0x40 // USART Transmitt Complete + UCSR3A_UDRE3 = 0x20 // USART Data Register Empty + UCSR3A_FE3 = 0x10 // Framing Error + UCSR3A_DOR3 = 0x8 // Data overRun + UCSR3A_UPE3 = 0x4 // Parity Error + UCSR3A_U2X3 = 0x2 // Double the USART transmission speed + UCSR3A_MPCM3 = 0x1 // Multi-processor Communication Mode + + // UCSR3B: USART Control and Status Register B + UCSR3B_RXCIE3 = 0x80 // RX Complete Interrupt Enable + UCSR3B_TXCIE3 = 0x40 // TX Complete Interrupt Enable + UCSR3B_UDRIE3 = 0x20 // USART Data register Empty Interrupt Enable + UCSR3B_RXEN3 = 0x10 // Receiver Enable + UCSR3B_TXEN3 = 0x8 // Transmitter Enable + UCSR3B_UCSZ32 = 0x4 // Character Size + UCSR3B_RXB83 = 0x2 // Receive Data Bit 8 + UCSR3B_TXB83 = 0x1 // Transmit Data Bit 8 + + // UCSR3C: USART Control and Status Register C + UCSR3C_UMSEL3 = 0xc0 // USART Mode Select + UCSR3C_UPM3 = 0x30 // Parity Mode Bits + UCSR3C_USBS3 = 0x8 // Stop Bit Select + UCSR3C_UCSZ3 = 0x6 // Character Size + UCSR3C_UCPOL3 = 0x1 // Clock Polarity +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2B = 0x4 // Output Compare Flag 2B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Output Mode bits + TCCR2A_COM2B = 0x30 // Compare Output Mode bits + TCCR2A_WGM2 = 0x3 // Waveform Genration Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy + ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR5A: Timer/Counter5 Control Register A + TCCR5A_COM5A = 0xc0 // Compare Output Mode 1A, bits + TCCR5A_COM5B = 0x30 // Compare Output Mode 5B, bits + TCCR5A_COM5C = 0xc // Compare Output Mode 5C, bits + TCCR5A_WGM5 = 0x3 // Waveform Generation Mode + + // TCCR5B: Timer/Counter5 Control Register B + TCCR5B_ICNC5 = 0x80 // Input Capture 5 Noise Canceler + TCCR5B_ICES5 = 0x40 // Input Capture 5 Edge Select + TCCR5B_WGM5 = 0x18 // Waveform Generation Mode + TCCR5B_CS5 = 0x7 // Prescaler source of Timer/Counter 5 + + // TCCR5C: Timer/Counter 5 Control Register C + TCCR5C_FOC5A = 0x80 // Force Output Compare 5A + TCCR5C_FOC5B = 0x40 // Force Output Compare 5B + TCCR5C_FOC5C = 0x20 // Force Output Compare 5C + + // TIMSK5: Timer/Counter5 Interrupt Mask Register + TIMSK5_ICIE5 = 0x20 // Timer/Counter5 Input Capture Interrupt Enable + TIMSK5_OCIE5C = 0x8 // Timer/Counter5 Output Compare C Match Interrupt Enable + TIMSK5_OCIE5B = 0x4 // Timer/Counter5 Output Compare B Match Interrupt Enable + TIMSK5_OCIE5A = 0x2 // Timer/Counter5 Output Compare A Match Interrupt Enable + TIMSK5_TOIE5 = 0x1 // Timer/Counter5 Overflow Interrupt Enable + + // TIFR5: Timer/Counter5 Interrupt Flag register + TIFR5_ICF5 = 0x20 // Input Capture Flag 5 + TIFR5_OCF5C = 0x8 // Output Compare Flag 5C + TIFR5_OCF5B = 0x4 // Output Compare Flag 5B + TIFR5_OCF5A = 0x2 // Output Compare Flag 5A + TIFR5_TOV5 = 0x1 // Timer/Counter5 Overflow Flag + + // TCCR4A: Timer/Counter4 Control Register A + TCCR4A_COM4A = 0xc0 // Compare Output Mode 1A, bits + TCCR4A_COM4B = 0x30 // Compare Output Mode 4B, bits + TCCR4A_COM4C = 0xc // Compare Output Mode 4C, bits + TCCR4A_WGM4 = 0x3 // Waveform Generation Mode + + // TCCR4B: Timer/Counter4 Control Register B + TCCR4B_ICNC4 = 0x80 // Input Capture 4 Noise Canceler + TCCR4B_ICES4 = 0x40 // Input Capture 4 Edge Select + TCCR4B_WGM4 = 0x18 // Waveform Generation Mode + TCCR4B_CS4 = 0x7 // Prescaler source of Timer/Counter 4 + + // TCCR4C: Timer/Counter 4 Control Register C + TCCR4C_FOC4A = 0x80 // Force Output Compare 4A + TCCR4C_FOC4B = 0x40 // Force Output Compare 4B + TCCR4C_FOC4C = 0x20 // Force Output Compare 4C + + // TIMSK4: Timer/Counter4 Interrupt Mask Register + TIMSK4_ICIE4 = 0x20 // Timer/Counter4 Input Capture Interrupt Enable + TIMSK4_OCIE4C = 0x8 // Timer/Counter4 Output Compare C Match Interrupt Enable + TIMSK4_OCIE4B = 0x4 // Timer/Counter4 Output Compare B Match Interrupt Enable + TIMSK4_OCIE4A = 0x2 // Timer/Counter4 Output Compare A Match Interrupt Enable + TIMSK4_TOIE4 = 0x1 // Timer/Counter4 Overflow Interrupt Enable + + // TIFR4: Timer/Counter4 Interrupt Flag register + TIFR4_ICF4 = 0x20 // Input Capture Flag 4 + TIFR4_OCF4C = 0x8 // Output Compare Flag 4C + TIFR4_OCF4B = 0x4 // Output Compare Flag 4B + TIFR4_OCF4A = 0x2 // Output Compare Flag 4A + TIFR4_TOV4 = 0x1 // Timer/Counter4 Overflow Flag + + // TCCR3A: Timer/Counter3 Control Register A + TCCR3A_COM3A = 0xc0 // Compare Output Mode 1A, bits + TCCR3A_COM3B = 0x30 // Compare Output Mode 3B, bits + TCCR3A_COM3C = 0xc // Compare Output Mode 3C, bits + TCCR3A_WGM3 = 0x3 // Waveform Generation Mode + + // TCCR3B: Timer/Counter3 Control Register B + TCCR3B_ICNC3 = 0x80 // Input Capture 3 Noise Canceler + TCCR3B_ICES3 = 0x40 // Input Capture 3 Edge Select + TCCR3B_WGM3 = 0x18 // Waveform Generation Mode + TCCR3B_CS3 = 0x7 // Prescaler source of Timer/Counter 3 + + // TCCR3C: Timer/Counter 3 Control Register C + TCCR3C_FOC3A = 0x80 // Force Output Compare 3A + TCCR3C_FOC3B = 0x40 // Force Output Compare 3B + TCCR3C_FOC3C = 0x20 // Force Output Compare 3C + + // TIMSK3: Timer/Counter3 Interrupt Mask Register + TIMSK3_ICIE3 = 0x20 // Timer/Counter3 Input Capture Interrupt Enable + TIMSK3_OCIE3C = 0x8 // Timer/Counter3 Output Compare C Match Interrupt Enable + TIMSK3_OCIE3B = 0x4 // Timer/Counter3 Output Compare B Match Interrupt Enable + TIMSK3_OCIE3A = 0x2 // Timer/Counter3 Output Compare A Match Interrupt Enable + TIMSK3_TOIE3 = 0x1 // Timer/Counter3 Overflow Interrupt Enable + + // TIFR3: Timer/Counter3 Interrupt Flag register + TIFR3_ICF3 = 0x20 // Input Capture Flag 3 + TIFR3_OCF3C = 0x8 // Output Compare Flag 3C + TIFR3_OCF3B = 0x4 // Output Compare Flag 3B + TIFR3_OCF3A = 0x2 // Output Compare Flag 3A + TIFR3_TOV3 = 0x1 // Timer/Counter3 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_COM1C = 0xc // Compare Output Mode 1C, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + TCCR1C_FOC1C = 0x20 // Force Output Compare 1C + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1C = 0x8 // Timer/Counter1 Output Compare C Match Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1C = 0x8 // Output Compare Flag 1C + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EICRB: External Interrupt Control Register B + EICRB_ISC7 = 0xc0 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC6 = 0x30 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC5 = 0xc // External Interrupt 7-4 Sense Control Bit + EICRB_ISC4 = 0x3 // External Interrupt 7-4 Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xff // External Interrupt Request 7 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xff // External Interrupt Flags + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable bits + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Enable bits + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable bits + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0x7 // Pin Change Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0x7 // Pin Change Interrupt Enables +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // XMCRA: External Memory Control Register A + XMCRA_SRE = 0x80 // External SRAM Enable + XMCRA_SRL = 0x70 // Wait state page limit + XMCRA_SRW1 = 0xc // Wait state select bit upper page + XMCRA_SRW0 = 0x3 // Wait state select bit lower page + + // XMCRB: External Memory Control Register B + XMCRB_XMBK = 0x80 // External Memory Bus Keeper Enable + XMCRB_XMM = 0x7 // External Memory High Mask + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 + + // PRR1: Power Reduction Register1 + PRR1_PRTIM5 = 0x20 // Power Reduction Timer/Counter5 + PRR1_PRTIM4 = 0x10 // Power Reduction Timer/Counter4 + PRR1_PRTIM3 = 0x8 // Power Reduction Timer/Counter3 + PRR1_PRUSART3 = 0x4 // Power Reduction USART3 + PRR1_PRUSART2 = 0x2 // Power Reduction USART2 + PRR1_PRUSART1 = 0x1 // Power Reduction USART1 + + // PRR0: Power Reduction Register0 + PRR0_PRTWI = 0x80 // Power Reduction TWI + PRR0_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR0_PRUSART0 = 0x2 // Power Reduction USART0 + PRR0_PRADC = 0x1 // Power Reduction ADC +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR2: Digital Input Disable Register + DIDR2_ADC15D = 0x80 + DIDR2_ADC14D = 0x40 + DIDR2_ADC13D = 0x20 + DIDR2_ADC12D = 0x10 + DIDR2_ADC11D = 0x8 + DIDR2_ADC10D = 0x4 + DIDR2_ADC9D = 0x2 + DIDR2_ADC8D = 0x1 + + // DIDR0: Digital Input Disable Register + DIDR0_ADC7D = 0x80 + DIDR0_ADC6D = 0x40 + DIDR0_ADC5D = 0x20 + DIDR0_ADC4D = 0x10 + DIDR0_ADC3D = 0x8 + DIDR0_ADC2D = 0x4 + DIDR0_ADC1D = 0x2 + DIDR0_ADC0D = 0x1 +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) diff --git a/src/device/avr/atmega1280.ld b/src/device/avr/atmega1280.ld new file mode 100644 index 00000000..761b3bff --- /dev/null +++ b/src/device/avr/atmega1280.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega1280.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x20000; +__ram_size = 0x2000; +__num_isrs = 57; diff --git a/src/device/avr/atmega1281.go b/src/device/avr/atmega1281.go new file mode 100644 index 00000000..71f7b880 --- /dev/null +++ b/src/device/avr/atmega1281.go @@ -0,0 +1,986 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega1281.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega1281 + +// Device information for the ATmega1281. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega1281" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_INT3 = 4 // External Interrupt Request 3 + IRQ_INT4 = 5 // External Interrupt Request 4 + IRQ_INT5 = 6 // External Interrupt Request 5 + IRQ_INT6 = 7 // External Interrupt Request 6 + IRQ_INT7 = 8 // External Interrupt Request 7 + IRQ_PCINT0 = 9 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 10 // Pin Change Interrupt Request 1 + IRQ_PCINT2 = 11 // Pin Change Interrupt Request 2 + IRQ_WDT = 12 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 13 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 14 // Timer/Counter2 Compare Match B + IRQ_TIMER2_OVF = 15 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 16 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 17 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 18 // Timer/Counter1 Compare Match B + IRQ_TIMER1_COMPC = 19 // Timer/Counter1 Compare Match C + IRQ_TIMER1_OVF = 20 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 21 // Timer/Counter0 Compare Match A + IRQ_TIMER0_COMPB = 22 // Timer/Counter0 Compare Match B + IRQ_TIMER0_OVF = 23 // Timer/Counter0 Overflow + IRQ_SPI_STC = 24 // SPI Serial Transfer Complete + IRQ_USART0_RX = 25 // USART0, Rx Complete + IRQ_USART0_UDRE = 26 // USART0 Data register Empty + IRQ_USART0_TX = 27 // USART0, Tx Complete + IRQ_ANALOG_COMP = 28 // Analog Comparator + IRQ_ADC = 29 // ADC Conversion Complete + IRQ_EE_READY = 30 // EEPROM Ready + IRQ_TIMER3_CAPT = 31 // Timer/Counter3 Capture Event + IRQ_TIMER3_COMPA = 32 // Timer/Counter3 Compare Match A + IRQ_TIMER3_COMPB = 33 // Timer/Counter3 Compare Match B + IRQ_TIMER3_COMPC = 34 // Timer/Counter3 Compare Match C + IRQ_TIMER3_OVF = 35 // Timer/Counter3 Overflow + IRQ_USART1_RX = 36 // USART1, Rx Complete + IRQ_USART1_UDRE = 37 // USART1 Data register Empty + IRQ_USART1_TX = 38 // USART1, Tx Complete + IRQ_TWI = 39 // 2-wire Serial Interface + IRQ_SPM_READY = 40 // Store Program Memory Read + IRQ_TIMER4_CAPT = 41 // Timer/Counter4 Capture Event + IRQ_TIMER4_COMPA = 42 // Timer/Counter4 Compare Match A + IRQ_TIMER4_COMPB = 43 // Timer/Counter4 Compare Match B + IRQ_TIMER4_COMPC = 44 // Timer/Counter4 Compare Match C + IRQ_TIMER4_OVF = 45 // Timer/Counter4 Overflow + IRQ_TIMER5_CAPT = 46 // Timer/Counter5 Capture Event + IRQ_TIMER5_COMPA = 47 // Timer/Counter5 Compare Match A + IRQ_TIMER5_COMPB = 48 // Timer/Counter5 Compare Match B + IRQ_TIMER5_COMPC = 49 // Timer/Counter5 Compare Match C + IRQ_TIMER5_OVF = 50 // Timer/Counter5 Overflow + IRQ_USART2_RX = 51 // USART2, Rx Complete + IRQ_USART2_UDRE = 52 // USART2 Data register Empty + IRQ_USART2_TX = 53 // USART2, Tx Complete + IRQ_USART3_RX = 54 // USART3, Rx Complete + IRQ_USART3_UDRE = 55 // USART3 Data register Empty + IRQ_USART3_TX = 56 // USART3, Tx Complete + IRQ_max = 56 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + UDR1 __reg + UCSR1A __reg + UCSR1B __reg + UCSR1C __reg + UBRR1L __reg + UBRR1H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + UDR1: 0xce, // USART I/O Data Register + UCSR1A: 0xc8, // USART Control and Status Register A + UCSR1B: 0xc9, // USART Control and Status Register B + UCSR1C: 0xca, // USART Control and Status Register C + UBRR1L: 0xcc, // USART Baud Rate Register Bytes + UBRR1H: 0xcc, // USART Baud Rate Register Bytes + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + PORTG: 0x34, // Data Register, Port G + DDRG: 0x33, // Data Direction Register, Port G + PING: 0x32, // Input Pins, Port G + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR5A __reg + TCCR5B __reg + TCCR5C __reg + TCNT5L __reg + TCNT5H __reg + OCR5AL __reg + OCR5AH __reg + OCR5BL __reg + OCR5BH __reg + OCR5CL __reg + OCR5CH __reg + ICR5L __reg + ICR5H __reg + TIMSK5 __reg + TIFR5 __reg + TCCR4A __reg + TCCR4B __reg + TCCR4C __reg + TCNT4L __reg + TCNT4H __reg + OCR4AL __reg + OCR4AH __reg + OCR4BL __reg + OCR4BH __reg + OCR4CL __reg + OCR4CH __reg + ICR4L __reg + ICR4H __reg + TIMSK4 __reg + TIFR4 __reg + TCCR3A __reg + TCCR3B __reg + TCCR3C __reg + TCNT3L __reg + TCNT3H __reg + OCR3AL __reg + OCR3AH __reg + OCR3BL __reg + OCR3BH __reg + OCR3CL __reg + OCR3CH __reg + ICR3L __reg + ICR3H __reg + TIMSK3 __reg + TIFR3 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + OCR1CL __reg + OCR1CH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR5A: 0x120, // Timer/Counter5 Control Register A + TCCR5B: 0x121, // Timer/Counter5 Control Register B + TCCR5C: 0x122, // Timer/Counter 5 Control Register C + TCNT5L: 0x124, // Timer/Counter5 Bytes + TCNT5H: 0x124, // Timer/Counter5 Bytes + OCR5AL: 0x128, // Timer/Counter5 Output Compare Register A Bytes + OCR5AH: 0x128, // Timer/Counter5 Output Compare Register A Bytes + OCR5BL: 0x12a, // Timer/Counter5 Output Compare Register B Bytes + OCR5BH: 0x12a, // Timer/Counter5 Output Compare Register B Bytes + OCR5CL: 0x12c, // Timer/Counter5 Output Compare Register B Bytes + OCR5CH: 0x12c, // Timer/Counter5 Output Compare Register B Bytes + ICR5L: 0x126, // Timer/Counter5 Input Capture Register Bytes + ICR5H: 0x126, // Timer/Counter5 Input Capture Register Bytes + TIMSK5: 0x73, // Timer/Counter5 Interrupt Mask Register + TIFR5: 0x3a, // Timer/Counter5 Interrupt Flag register + TCCR4A: 0xa0, // Timer/Counter4 Control Register A + TCCR4B: 0xa1, // Timer/Counter4 Control Register B + TCCR4C: 0xa2, // Timer/Counter 4 Control Register C + TCNT4L: 0xa4, // Timer/Counter4 Bytes + TCNT4H: 0xa4, // Timer/Counter4 Bytes + OCR4AL: 0xa8, // Timer/Counter4 Output Compare Register A Bytes + OCR4AH: 0xa8, // Timer/Counter4 Output Compare Register A Bytes + OCR4BL: 0xaa, // Timer/Counter4 Output Compare Register B Bytes + OCR4BH: 0xaa, // Timer/Counter4 Output Compare Register B Bytes + OCR4CL: 0xac, // Timer/Counter4 Output Compare Register B Bytes + OCR4CH: 0xac, // Timer/Counter4 Output Compare Register B Bytes + ICR4L: 0xa6, // Timer/Counter4 Input Capture Register Bytes + ICR4H: 0xa6, // Timer/Counter4 Input Capture Register Bytes + TIMSK4: 0x72, // Timer/Counter4 Interrupt Mask Register + TIFR4: 0x39, // Timer/Counter4 Interrupt Flag register + TCCR3A: 0x90, // Timer/Counter3 Control Register A + TCCR3B: 0x91, // Timer/Counter3 Control Register B + TCCR3C: 0x92, // Timer/Counter 3 Control Register C + TCNT3L: 0x94, // Timer/Counter3 Bytes + TCNT3H: 0x94, // Timer/Counter3 Bytes + OCR3AL: 0x98, // Timer/Counter3 Output Compare Register A Bytes + OCR3AH: 0x98, // Timer/Counter3 Output Compare Register A Bytes + OCR3BL: 0x9a, // Timer/Counter3 Output Compare Register B Bytes + OCR3BH: 0x9a, // Timer/Counter3 Output Compare Register B Bytes + OCR3CL: 0x9c, // Timer/Counter3 Output Compare Register B Bytes + OCR3CH: 0x9c, // Timer/Counter3 Output Compare Register B Bytes + ICR3L: 0x96, // Timer/Counter3 Input Capture Register Bytes + ICR3H: 0x96, // Timer/Counter3 Input Capture Register Bytes + TIMSK3: 0x71, // Timer/Counter3 Interrupt Mask Register + TIFR3: 0x38, // Timer/Counter3 Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1CL: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + OCR1CH: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Low Bytes + EEARH: 0x41, // EEPROM Address Register Low Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EICRB __reg + EIMSK __reg + EIFR __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + PCICR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EICRB: 0x6a, // External Interrupt Control Register B + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + DIDR2 __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // The ADC Control and Status register A + DIDR2: 0x7d, // Digital Input Disable Register + DIDR0: 0x7e, // Digital Input Disable Register + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + XMCRA __reg + XMCRB __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + RAMPZ __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PRR1 __reg + PRR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + XMCRA: 0x74, // External Memory Control Register A + XMCRB: 0x75, // External Memory Control Register B + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, + SMCR: 0x53, // Sleep Mode Control Register + RAMPZ: 0x5b, // RAM Page Z Select Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PRR1: 0x65, // Power Reduction Register1 + PRR0: 0x64, // Power Reduction Register0 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0xc0 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity + + // UCSR1A: USART Control and Status Register A + UCSR1A_RXC1 = 0x80 // USART Receive Complete + UCSR1A_TXC1 = 0x40 // USART Transmitt Complete + UCSR1A_UDRE1 = 0x20 // USART Data Register Empty + UCSR1A_FE1 = 0x10 // Framing Error + UCSR1A_DOR1 = 0x8 // Data overRun + UCSR1A_UPE1 = 0x4 // Parity Error + UCSR1A_U2X1 = 0x2 // Double the USART transmission speed + UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode + + // UCSR1B: USART Control and Status Register B + UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable + UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable + UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable + UCSR1B_RXEN1 = 0x10 // Receiver Enable + UCSR1B_TXEN1 = 0x8 // Transmitter Enable + UCSR1B_UCSZ12 = 0x4 // Character Size + UCSR1B_RXB81 = 0x2 // Receive Data Bit 8 + UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8 + + // UCSR1C: USART Control and Status Register C + UCSR1C_UMSEL1 = 0xc0 // USART Mode Select + UCSR1C_UPM1 = 0x30 // Parity Mode Bits + UCSR1C_USBS1 = 0x8 // Stop Bit Select + UCSR1C_UCSZ1 = 0x6 // Character Size + UCSR1C_UCPOL1 = 0x1 // Clock Polarity +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2B = 0x4 // Output Compare Flag 2B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Output Mode bits + TCCR2A_COM2B = 0x30 // Compare Output Mode bits + TCCR2A_WGM2 = 0x3 // Waveform Genration Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy + ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR5A: Timer/Counter5 Control Register A + TCCR5A_COM5A = 0xc0 // Compare Output Mode 1A, bits + TCCR5A_COM5B = 0x30 // Compare Output Mode 5B, bits + TCCR5A_COM5C = 0xc // Compare Output Mode 5C, bits + TCCR5A_WGM5 = 0x3 // Waveform Generation Mode + + // TCCR5B: Timer/Counter5 Control Register B + TCCR5B_ICNC5 = 0x80 // Input Capture 5 Noise Canceler + TCCR5B_ICES5 = 0x40 // Input Capture 5 Edge Select + TCCR5B_WGM5 = 0x18 // Waveform Generation Mode + TCCR5B_CS5 = 0x7 // Prescaler source of Timer/Counter 5 + + // TCCR5C: Timer/Counter 5 Control Register C + TCCR5C_FOC5A = 0x80 // Force Output Compare 5A + TCCR5C_FOC5B = 0x40 // Force Output Compare 5B + TCCR5C_FOC5C = 0x20 // Force Output Compare 5C + + // TIMSK5: Timer/Counter5 Interrupt Mask Register + TIMSK5_ICIE5 = 0x20 // Timer/Counter5 Input Capture Interrupt Enable + TIMSK5_OCIE5C = 0x8 // Timer/Counter5 Output Compare C Match Interrupt Enable + TIMSK5_OCIE5B = 0x4 // Timer/Counter5 Output Compare B Match Interrupt Enable + TIMSK5_OCIE5A = 0x2 // Timer/Counter5 Output Compare A Match Interrupt Enable + TIMSK5_TOIE5 = 0x1 // Timer/Counter5 Overflow Interrupt Enable + + // TIFR5: Timer/Counter5 Interrupt Flag register + TIFR5_ICF5 = 0x20 // Input Capture Flag 5 + TIFR5_OCF5C = 0x8 // Output Compare Flag 5C + TIFR5_OCF5B = 0x4 // Output Compare Flag 5B + TIFR5_OCF5A = 0x2 // Output Compare Flag 5A + TIFR5_TOV5 = 0x1 // Timer/Counter5 Overflow Flag + + // TCCR4A: Timer/Counter4 Control Register A + TCCR4A_COM4A = 0xc0 // Compare Output Mode 1A, bits + TCCR4A_COM4B = 0x30 // Compare Output Mode 4B, bits + TCCR4A_COM4C = 0xc // Compare Output Mode 4C, bits + TCCR4A_WGM4 = 0x3 // Waveform Generation Mode + + // TCCR4B: Timer/Counter4 Control Register B + TCCR4B_ICNC4 = 0x80 // Input Capture 4 Noise Canceler + TCCR4B_ICES4 = 0x40 // Input Capture 4 Edge Select + TCCR4B_WGM4 = 0x18 // Waveform Generation Mode + TCCR4B_CS4 = 0x7 // Prescaler source of Timer/Counter 4 + + // TCCR4C: Timer/Counter 4 Control Register C + TCCR4C_FOC4A = 0x80 // Force Output Compare 4A + TCCR4C_FOC4B = 0x40 // Force Output Compare 4B + TCCR4C_FOC4C = 0x20 // Force Output Compare 4C + + // TIMSK4: Timer/Counter4 Interrupt Mask Register + TIMSK4_ICIE4 = 0x20 // Timer/Counter4 Input Capture Interrupt Enable + TIMSK4_OCIE4C = 0x8 // Timer/Counter4 Output Compare C Match Interrupt Enable + TIMSK4_OCIE4B = 0x4 // Timer/Counter4 Output Compare B Match Interrupt Enable + TIMSK4_OCIE4A = 0x2 // Timer/Counter4 Output Compare A Match Interrupt Enable + TIMSK4_TOIE4 = 0x1 // Timer/Counter4 Overflow Interrupt Enable + + // TIFR4: Timer/Counter4 Interrupt Flag register + TIFR4_ICF4 = 0x20 // Input Capture Flag 4 + TIFR4_OCF4C = 0x8 // Output Compare Flag 4C + TIFR4_OCF4B = 0x4 // Output Compare Flag 4B + TIFR4_OCF4A = 0x2 // Output Compare Flag 4A + TIFR4_TOV4 = 0x1 // Timer/Counter4 Overflow Flag + + // TCCR3A: Timer/Counter3 Control Register A + TCCR3A_COM3A = 0xc0 // Compare Output Mode 1A, bits + TCCR3A_COM3B = 0x30 // Compare Output Mode 3B, bits + TCCR3A_COM3C = 0xc // Compare Output Mode 3C, bits + TCCR3A_WGM3 = 0x3 // Waveform Generation Mode + + // TCCR3B: Timer/Counter3 Control Register B + TCCR3B_ICNC3 = 0x80 // Input Capture 3 Noise Canceler + TCCR3B_ICES3 = 0x40 // Input Capture 3 Edge Select + TCCR3B_WGM3 = 0x18 // Waveform Generation Mode + TCCR3B_CS3 = 0x7 // Prescaler source of Timer/Counter 3 + + // TCCR3C: Timer/Counter 3 Control Register C + TCCR3C_FOC3A = 0x80 // Force Output Compare 3A + TCCR3C_FOC3B = 0x40 // Force Output Compare 3B + TCCR3C_FOC3C = 0x20 // Force Output Compare 3C + + // TIMSK3: Timer/Counter3 Interrupt Mask Register + TIMSK3_ICIE3 = 0x20 // Timer/Counter3 Input Capture Interrupt Enable + TIMSK3_OCIE3C = 0x8 // Timer/Counter3 Output Compare C Match Interrupt Enable + TIMSK3_OCIE3B = 0x4 // Timer/Counter3 Output Compare B Match Interrupt Enable + TIMSK3_OCIE3A = 0x2 // Timer/Counter3 Output Compare A Match Interrupt Enable + TIMSK3_TOIE3 = 0x1 // Timer/Counter3 Overflow Interrupt Enable + + // TIFR3: Timer/Counter3 Interrupt Flag register + TIFR3_ICF3 = 0x20 // Input Capture Flag 3 + TIFR3_OCF3C = 0x8 // Output Compare Flag 3C + TIFR3_OCF3B = 0x4 // Output Compare Flag 3B + TIFR3_OCF3A = 0x2 // Output Compare Flag 3A + TIFR3_TOV3 = 0x1 // Timer/Counter3 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_COM1C = 0xc // Compare Output Mode 1C, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + TCCR1C_FOC1C = 0x20 // Force Output Compare 1C + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1C = 0x8 // Timer/Counter1 Output Compare C Match Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1C = 0x8 // Output Compare Flag 1C + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EICRB: External Interrupt Control Register B + EICRB_ISC7 = 0xc0 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC6 = 0x30 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC5 = 0xc // External Interrupt 7-4 Sense Control Bit + EICRB_ISC4 = 0x3 // External Interrupt 7-4 Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xff // External Interrupt Request 7 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xff // External Interrupt Flags + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable mask + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Enable mask + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable mask + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0x7 // Pin Change Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0x7 // Pin Change Interrupt Enables +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR2: Digital Input Disable Register + DIDR2_ADC15D = 0x80 + DIDR2_ADC14D = 0x40 + DIDR2_ADC13D = 0x20 + DIDR2_ADC12D = 0x10 + DIDR2_ADC11D = 0x8 + DIDR2_ADC10D = 0x4 + DIDR2_ADC9D = 0x2 + DIDR2_ADC8D = 0x1 + + // DIDR0: Digital Input Disable Register + DIDR0_ADC7D = 0x80 + DIDR0_ADC6D = 0x40 + DIDR0_ADC5D = 0x20 + DIDR0_ADC4D = 0x10 + DIDR0_ADC3D = 0x8 + DIDR0_ADC2D = 0x4 + DIDR0_ADC1D = 0x2 + DIDR0_ADC0D = 0x1 +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // XMCRA: External Memory Control Register A + XMCRA_SRE = 0x80 // External SRAM Enable + XMCRA_SRL = 0x70 // Wait state page limit + XMCRA_SRW1 = 0xc // Wait state select bit upper page + XMCRA_SRW0 = 0x3 // Wait state select bit lower page + + // XMCRB: External Memory Control Register B + XMCRB_XMBK = 0x80 // External Memory Bus Keeper Enable + XMCRB_XMM = 0x7 // External Memory High Mask + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 + + // PRR1: Power Reduction Register1 + PRR1_PRTIM5 = 0x20 // Power Reduction Timer/Counter5 + PRR1_PRTIM4 = 0x10 // Power Reduction Timer/Counter4 + PRR1_PRTIM3 = 0x8 // Power Reduction Timer/Counter3 + PRR1_PRUSART3 = 0x4 // Power Reduction USART3 + PRR1_PRUSART2 = 0x2 // Power Reduction USART2 + PRR1_PRUSART1 = 0x1 // Power Reduction USART1 + + // PRR0: Power Reduction Register0 + PRR0_PRTWI = 0x80 // Power Reduction TWI + PRR0_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR0_PRUSART0 = 0x2 // Power Reduction USART0 + PRR0_PRADC = 0x1 // Power Reduction ADC +) diff --git a/src/device/avr/atmega1281.ld b/src/device/avr/atmega1281.ld new file mode 100644 index 00000000..340bab39 --- /dev/null +++ b/src/device/avr/atmega1281.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega1281.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x20000; +__ram_size = 0x2000; +__num_isrs = 57; diff --git a/src/device/avr/atmega1284.go b/src/device/avr/atmega1284.go new file mode 100644 index 00000000..4631b316 --- /dev/null +++ b/src/device/avr/atmega1284.go @@ -0,0 +1,774 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega1284.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega1284 + +// Device information for the ATmega1284. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega1284" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_PCINT0 = 4 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 5 // Pin Change Interrupt Request 1 + IRQ_PCINT2 = 6 // Pin Change Interrupt Request 2 + IRQ_PCINT3 = 7 // Pin Change Interrupt Request 3 + IRQ_WDT = 8 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 9 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 10 // Timer/Counter2 Compare Match B + IRQ_TIMER2_OVF = 11 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 12 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 13 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 14 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 15 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 16 // Timer/Counter0 Compare Match A + IRQ_TIMER0_COMPB = 17 // Timer/Counter0 Compare Match B + IRQ_TIMER0_OVF = 18 // Timer/Counter0 Overflow + IRQ_SPI_STC = 19 // SPI Serial Transfer Complete + IRQ_USART0_RX = 20 // USART0, Rx Complete + IRQ_USART0_UDRE = 21 // USART0 Data register Empty + IRQ_USART0_TX = 22 // USART0, Tx Complete + IRQ_ANALOG_COMP = 23 // Analog Comparator + IRQ_ADC = 24 // ADC Conversion Complete + IRQ_EE_READY = 25 // EEPROM Ready + IRQ_TWI = 26 // 2-wire Serial Interface + IRQ_SPM_READY = 27 // Store Program Memory Read + IRQ_USART1_RX = 28 // USART1 RX complete + IRQ_USART1_UDRE = 29 // USART1 Data Register Empty + IRQ_USART1_TX = 30 // USART1 TX complete + IRQ_TIMER3_CAPT = 31 // Timer/Counter3 Capture Event + IRQ_TIMER3_COMPA = 32 // Timer/Counter3 Compare Match A + IRQ_TIMER3_COMPB = 33 // Timer/Counter3 Compare Match B + IRQ_TIMER3_OVF = 34 // Timer/Counter3 Overflow + IRQ_max = 34 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + UDR1 __reg + UCSR1A __reg + UCSR1B __reg + UCSR1C __reg + UBRR1L __reg + UBRR1H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + UDR1: 0xce, // USART I/O Data Register + UCSR1A: 0xc8, // USART Control and Status Register A + UCSR1B: 0xc9, // USART Control and Status Register B + UCSR1C: 0xca, // USART Control and Status Register C + UBRR1L: 0xcc, // USART Baud Rate Register Bytes + UBRR1H: 0xcc, // USART Baud Rate Register Bytes + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + TIMSK3 __reg + TIFR3 __reg + TCCR3A __reg + TCCR3B __reg + TCCR3C __reg + TCNT3L __reg + TCNT3H __reg + OCR3AL __reg + OCR3AH __reg + OCR3BL __reg + OCR3BH __reg + ICR3L __reg + ICR3H __reg + }{ + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK3: 0x71, // Timer/Counter3 Interrupt Mask Register + TIFR3: 0x38, // Timer/Counter Interrupt Flag register + TCCR3A: 0x90, // Timer/Counter3 Control Register A + TCCR3B: 0x91, // Timer/Counter3 Control Register B + TCCR3C: 0x92, // Timer/Counter3 Control Register C + TCNT3L: 0x94, // Timer/Counter3 Bytes + TCNT3H: 0x94, // Timer/Counter3 Bytes + OCR3AL: 0x98, // Timer/Counter3 Output Compare Register A Bytes + OCR3AH: 0x98, // Timer/Counter3 Output Compare Register A Bytes + OCR3BL: 0x9a, // Timer/Counter3 Output Compare Register B Bytes + OCR3BH: 0x9a, // Timer/Counter3 Output Compare Register B Bytes + ICR3L: 0x96, // Timer/Counter3 Input Capture Register Bytes + ICR3H: 0x96, // Timer/Counter3 Input Capture Register Bytes + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK3 __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + PCICR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK3: 0x73, // Pin Change Mask Register 3 + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // The ADC Control and Status register A + DIDR0: 0x7e, // Digital Input Disable Register + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Low Bytes + EEARH: 0x41, // EEPROM Address Register Low Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // Serial Peripheral Interface + SPI = struct { + SPDR __reg + SPSR __reg + SPCR __reg + }{ + SPDR: 0x4e, // SPI Data Register + SPSR: 0x4d, // SPI Status Register + SPCR: 0x4c, // SPI Control Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + RAMPZ __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PRR0 __reg + PRR1 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, + SMCR: 0x53, // Sleep Mode Control Register + RAMPZ: 0x5b, // RAM Page Z Select Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PRR0: 0x64, // Power Reduction Register0 + PRR1: 0x65, // Power Reduction Register1 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTB1 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0xc0 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity + + // UCSR1A: USART Control and Status Register A + UCSR1A_RXC1 = 0x80 // USART Receive Complete + UCSR1A_TXC1 = 0x40 // USART Transmitt Complete + UCSR1A_UDRE1 = 0x20 // USART Data Register Empty + UCSR1A_FE1 = 0x10 // Framing Error + UCSR1A_DOR1 = 0x8 // Data overRun + UCSR1A_UPE1 = 0x4 // Parity Error + UCSR1A_U2X1 = 0x2 // Double the USART transmission speed + UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode + + // UCSR1B: USART Control and Status Register B + UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable + UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable + UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable + UCSR1B_RXEN1 = 0x10 // Receiver Enable + UCSR1B_TXEN1 = 0x8 // Transmitter Enable + UCSR1B_UCSZ12 = 0x4 // Character Size + UCSR1B_RXB81 = 0x2 // Receive Data Bit 8 + UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8 + + // UCSR1C: USART Control and Status Register C + UCSR1C_UMSEL1 = 0xc0 // USART Mode Select + UCSR1C_UPM1 = 0x30 // Parity Mode Bits + UCSR1C_USBS1 = 0x8 // Stop Bit Select + UCSR1C_UCSZ1 = 0x6 // Character Size + UCSR1C_UCPOL1 = 0x1 // Clock Polarity +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Timer/Counter1 Input Capture Flag + TIFR1_OCF1B = 0x4 // Timer/Counter1 Output Compare B Match Flag + TIFR1_OCF1A = 0x2 // Timer/Counter1 Output Compare A Match Flag + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Pulse Width Modulator Select Bits + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode Bits + TCCR1B_CS1 = 0x7 // Clock Select1 bits + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare for Channel A + TCCR1C_FOC1B = 0x40 // Force Output Compare for Channel B + + // TIMSK3: Timer/Counter3 Interrupt Mask Register + TIMSK3_ICIE3 = 0x20 // Timer/Counter3 Input Capture Interrupt Enable + TIMSK3_OCIE3B = 0x4 // Timer/Counter3 Output Compare B Match Interrupt Enable + TIMSK3_OCIE3A = 0x2 // Timer/Counter3 Output Compare A Match Interrupt Enable + TIMSK3_TOIE3 = 0x1 // Timer/Counter3 Overflow Interrupt Enable + + // TIFR3: Timer/Counter Interrupt Flag register + TIFR3_ICF3 = 0x20 // Timer/Counter3 Input Capture Flag + TIFR3_OCF3B = 0x4 // Timer/Counter3 Output Compare B Match Flag + TIFR3_OCF3A = 0x2 // Timer/Counter3 Output Compare A Match Flag + TIFR3_TOV3 = 0x1 // Timer/Counter3 Overflow Flag + + // TCCR3A: Timer/Counter3 Control Register A + TCCR3A_COM3A = 0xc0 // Compare Output Mode 3A, bits + TCCR3A_COM3B = 0x30 // Compare Output Mode 3B, bits + TCCR3A_WGM3 = 0x3 // Pulse Width Modulator Select Bits + + // TCCR3B: Timer/Counter3 Control Register B + TCCR3B_ICNC3 = 0x80 // Input Capture 3 Noise Canceler + TCCR3B_ICES3 = 0x40 // Input Capture 3 Edge Select + TCCR3B_WGM3 = 0x18 // Waveform Generation Mode Bits + TCCR3B_CS3 = 0x7 // Clock Select3 bits + + // TCCR3C: Timer/Counter3 Control Register C + TCCR3C_FOC3A = 0x80 // Force Output Compare for Channel A + TCCR3C_FOC3B = 0x40 // Force Output Compare for Channel B +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2B = 0x4 // Output Compare Flag 2B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Output Mode bits + TCCR2A_COM2B = 0x30 // Compare Output Mode bits + TCCR2A_WGM2 = 0x3 // Waveform Genration Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy + ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0x7 // External Interrupt Request 2 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0x7 // External Interrupt Flags + + // PCMSK3: Pin Change Mask Register 3 + PCMSK3_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0xf // Pin Change Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0xf // Pin Change Interrupt Enables +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register + DIDR0_ADC7D = 0x80 + DIDR0_ADC6D = 0x40 + DIDR0_ADC5D = 0x20 + DIDR0_ADC4D = 0x10 + DIDR0_ADC3D = 0x8 + DIDR0_ADC2D = 0x4 + DIDR0_ADC1D = 0x2 + DIDR0_ADC0D = 0x1 +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 + + // PRR0: Power Reduction Register0 + PRR0_PRTWI = 0x80 // Power Reduction TWI + PRR0_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR0_PRUSART1 = 0x10 // Power Reduction USART1 + PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR0_PRUSART0 = 0x2 // Power Reduction USART0 + PRR0_PRADC = 0x1 // Power Reduction ADC + + // PRR1: Power Reduction Register1 + PRR1_PRTIM3 = 0x1 // Power Reduction Timer/Counter3 +) diff --git a/src/device/avr/atmega1284.ld b/src/device/avr/atmega1284.ld new file mode 100644 index 00000000..05c8cad3 --- /dev/null +++ b/src/device/avr/atmega1284.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega1284.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x20000; +__ram_size = 0x4000; +__num_isrs = 35; diff --git a/src/device/avr/atmega1284p.go b/src/device/avr/atmega1284p.go new file mode 100644 index 00000000..89ef6e28 --- /dev/null +++ b/src/device/avr/atmega1284p.go @@ -0,0 +1,870 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega1284P.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega1284p + +// Device information for the ATmega1284P. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega1284P" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_PCINT0 = 4 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 5 // Pin Change Interrupt Request 1 + IRQ_PCINT2 = 6 // Pin Change Interrupt Request 2 + IRQ_PCINT3 = 7 // Pin Change Interrupt Request 3 + IRQ_WDT = 8 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 9 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 10 // Timer/Counter2 Compare Match B + IRQ_TIMER2_OVF = 11 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 12 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 13 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 14 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 15 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 16 // Timer/Counter0 Compare Match A + IRQ_TIMER0_COMPB = 17 // Timer/Counter0 Compare Match B + IRQ_TIMER0_OVF = 18 // Timer/Counter0 Overflow + IRQ_SPI_STC = 19 // SPI Serial Transfer Complete + IRQ_USART0_RX = 20 // USART0, Rx Complete + IRQ_USART0_UDRE = 21 // USART0 Data register Empty + IRQ_USART0_TX = 22 // USART0, Tx Complete + IRQ_ANALOG_COMP = 23 // Analog Comparator + IRQ_ADC = 24 // ADC Conversion Complete + IRQ_EE_READY = 25 // EEPROM Ready + IRQ_TWI = 26 // 2-wire Serial Interface + IRQ_SPM_READY = 27 // Store Program Memory Read + IRQ_USART1_RX = 28 // USART1 RX complete + IRQ_USART1_UDRE = 29 // USART1 Data Register Empty + IRQ_USART1_TX = 30 // USART1 TX complete + IRQ_TIMER3_CAPT = 31 // Timer/Counter3 Capture Event + IRQ_TIMER3_COMPA = 32 // Timer/Counter3 Compare Match A + IRQ_TIMER3_COMPB = 33 // Timer/Counter3 Compare Match B + IRQ_TIMER3_OVF = 34 // Timer/Counter3 Overflow + IRQ_max = 34 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + UDR1 __reg + UCSR1A __reg + UCSR1B __reg + UCSR1C __reg + UBRR1L __reg + UBRR1H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + UDR1: 0xce, // USART I/O Data Register + UCSR1A: 0xc8, // USART Control and Status Register A + UCSR1B: 0xc9, // USART Control and Status Register B + UCSR1C: 0xca, // USART Control and Status Register C + UBRR1L: 0xcc, // USART Baud Rate Register Bytes + UBRR1H: 0xcc, // USART Baud Rate Register Bytes + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register B + OCR0A: 0x47, // Timer/Counter0 Output Compare Register A + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + TIMSK3 __reg + TIFR3 __reg + TCCR3A __reg + TCCR3B __reg + TCCR3C __reg + TCNT3L __reg + TCNT3H __reg + OCR3AL __reg + OCR3AH __reg + OCR3BL __reg + OCR3BH __reg + ICR3L __reg + ICR3H __reg + }{ + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK3: 0x71, // Timer/Counter3 Interrupt Mask Register + TIFR3: 0x38, // Timer/Counter Interrupt Flag register + TCCR3A: 0x90, // Timer/Counter3 Control Register A + TCCR3B: 0x91, // Timer/Counter3 Control Register B + TCCR3C: 0x92, // Timer/Counter3 Control Register C + TCNT3L: 0x94, // Timer/Counter3 Bytes + TCNT3H: 0x94, // Timer/Counter3 Bytes + OCR3AL: 0x98, // Timer/Counter3 Output Compare Register A Bytes + OCR3AH: 0x98, // Timer/Counter3 Output Compare Register A Bytes + OCR3BL: 0x9a, // Timer/Counter3 Output Compare Register B Bytes + OCR3BH: 0x9a, // Timer/Counter3 Output Compare Register B Bytes + ICR3L: 0x96, // Timer/Counter3 Input Capture Register Bytes + ICR3H: 0x96, // Timer/Counter3 Input Capture Register Bytes + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK3 __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + PCICR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK3: 0x73, // Pin Change Mask Register 3 + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // The ADC Control and Status register A + DIDR0: 0x7e, // Digital Input Disable Register + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Low Bytes + EEARH: 0x41, // EEPROM Address Register Low Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // Serial Peripheral Interface + SPI = struct { + SPDR __reg + SPSR __reg + SPCR __reg + }{ + SPDR: 0x4e, // SPI Data Register + SPSR: 0x4d, // SPI Status Register + SPCR: 0x4c, // SPI Control Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + RAMPZ __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PRR0 __reg + PRR1 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, + SMCR: 0x53, // Sleep Mode Control Register + RAMPZ: 0x5b, // RAM Page Z Select Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PRR0: 0x64, // Power Reduction Register0 + PRR1: 0x65, // Power Reduction Register1 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTB1 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for USART: USART +const ( + // UDR0: USART I/O Data Register + UDR0_UDR0 = 0xff // USART I/O Data bits + + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0xc0 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity + + // UBRR0L: USART Baud Rate Register Bytes + + // UBRR0H: USART Baud Rate Register Bytes + UBRR0_UBRR0 = 0xfff // USART Baud Rate Register + + // UDR1: USART I/O Data Register + UDR1_UDR1 = 0xff // USART I/O Data bits + + // UCSR1A: USART Control and Status Register A + UCSR1A_RXC1 = 0x80 // USART Receive Complete + UCSR1A_TXC1 = 0x40 // USART Transmitt Complete + UCSR1A_UDRE1 = 0x20 // USART Data Register Empty + UCSR1A_FE1 = 0x10 // Framing Error + UCSR1A_DOR1 = 0x8 // Data overRun + UCSR1A_UPE1 = 0x4 // Parity Error + UCSR1A_U2X1 = 0x2 // Double the USART transmission speed + UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode + + // UCSR1B: USART Control and Status Register B + UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable + UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable + UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable + UCSR1B_RXEN1 = 0x10 // Receiver Enable + UCSR1B_TXEN1 = 0x8 // Transmitter Enable + UCSR1B_UCSZ12 = 0x4 // Character Size + UCSR1B_RXB81 = 0x2 // Receive Data Bit 8 + UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8 + + // UCSR1C: USART Control and Status Register C + UCSR1C_UMSEL1 = 0xc0 // USART Mode Select + UCSR1C_UPM1 = 0x30 // Parity Mode Bits + UCSR1C_USBS1 = 0x8 // Stop Bit Select + UCSR1C_UCSZ1 = 0x6 // Character Size + UCSR1C_UCPOL1 = 0x1 // Clock Polarity + + // UBRR1L: USART Baud Rate Register Bytes + + // UBRR1H: USART Baud Rate Register Bytes + UBRR1_UBRR1 = 0xfff // USART Baud Rate Register +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // OCR0B: Timer/Counter0 Output Compare Register B + OCR0B_OCR0B = 0xff // Timer/Counter0 Output Compare B bits + + // OCR0A: Timer/Counter0 Output Compare Register A + OCR0A_OCR0A = 0xff // Timer/Counter0 Output Compare A bits + + // TCNT0: Timer/Counter0 + TCNT0_TCNT0 = 0xff // Timer/Counter0 bits + + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Timer/Counter1 Input Capture Flag + TIFR1_OCF1B = 0x4 // Timer/Counter1 Output Compare B Match Flag + TIFR1_OCF1A = 0x2 // Timer/Counter1 Output Compare A Match Flag + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Pulse Width Modulator Select Bits + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode Bits + TCCR1B_CS1 = 0x7 // Clock Select1 bits + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare for Channel A + TCCR1C_FOC1B = 0x40 // Force Output Compare for Channel B + + // TCNT1L: Timer/Counter1 Bytes + + // TCNT1H: Timer/Counter1 Bytes + TCNT1_TCNT1 = 0xffff // Timer/Counter1 bits + + // OCR1AL: Timer/Counter1 Output Compare Register A Bytes + + // OCR1AH: Timer/Counter1 Output Compare Register A Bytes + OCR1A_OCR1A = 0xffff // Timer/Counter1 Output Compare A bits + + // OCR1BL: Timer/Counter1 Output Compare Register B Bytes + + // OCR1BH: Timer/Counter1 Output Compare Register B Bytes + OCR1B_OCR1B = 0xffff // Timer/Counter1 Output Compare B bits + + // ICR1L: Timer/Counter1 Input Capture Register Bytes + + // ICR1H: Timer/Counter1 Input Capture Register Bytes + ICR1_ICR1 = 0xffff // Timer/Counter1 Input Capture bits + + // TIMSK3: Timer/Counter3 Interrupt Mask Register + TIMSK3_ICIE3 = 0x20 // Timer/Counter3 Input Capture Interrupt Enable + TIMSK3_OCIE3B = 0x4 // Timer/Counter3 Output Compare B Match Interrupt Enable + TIMSK3_OCIE3A = 0x2 // Timer/Counter3 Output Compare A Match Interrupt Enable + TIMSK3_TOIE3 = 0x1 // Timer/Counter3 Overflow Interrupt Enable + + // TIFR3: Timer/Counter Interrupt Flag register + TIFR3_ICF3 = 0x20 // Timer/Counter3 Input Capture Flag + TIFR3_OCF3B = 0x4 // Timer/Counter3 Output Compare B Match Flag + TIFR3_OCF3A = 0x2 // Timer/Counter3 Output Compare A Match Flag + TIFR3_TOV3 = 0x1 // Timer/Counter3 Overflow Flag + + // TCCR3A: Timer/Counter3 Control Register A + TCCR3A_COM3A = 0xc0 // Compare Output Mode 3A, bits + TCCR3A_COM3B = 0x30 // Compare Output Mode 3B, bits + TCCR3A_WGM3 = 0x3 // Pulse Width Modulator Select Bits + + // TCCR3B: Timer/Counter3 Control Register B + TCCR3B_ICNC3 = 0x80 // Input Capture 3 Noise Canceler + TCCR3B_ICES3 = 0x40 // Input Capture 3 Edge Select + TCCR3B_WGM3 = 0x18 // Waveform Generation Mode Bits + TCCR3B_CS3 = 0x7 // Clock Select3 bits + + // TCCR3C: Timer/Counter3 Control Register C + TCCR3C_FOC3A = 0x80 // Force Output Compare for Channel A + TCCR3C_FOC3B = 0x40 // Force Output Compare for Channel B + + // TCNT3L: Timer/Counter3 Bytes + + // TCNT3H: Timer/Counter3 Bytes + TCNT3_TCNT3 = 0xffff // Timer/Counter3 bits + + // OCR3AL: Timer/Counter3 Output Compare Register A Bytes + + // OCR3AH: Timer/Counter3 Output Compare Register A Bytes + OCR3A_OCR3A = 0xffff // Timer/Counter3 Output Compare A bits + + // OCR3BL: Timer/Counter3 Output Compare Register B Bytes + + // OCR3BH: Timer/Counter3 Output Compare Register B Bytes + OCR3B_OCR3B = 0xffff // Timer/Counter3 Output Compare B bits + + // ICR3L: Timer/Counter3 Input Capture Register Bytes + + // ICR3H: Timer/Counter3 Input Capture Register Bytes + ICR3_ICR3 = 0xffff // Timer/Counter3 Input Capture bits +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2B = 0x4 // Output Compare Flag 2B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Output Mode bits + TCCR2A_COM2B = 0x30 // Compare Output Mode bits + TCCR2A_WGM2 = 0x3 // Waveform Genration Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select bits + + // TCNT2: Timer/Counter2 + TCNT2_TCNT2 = 0xff // Timer/Counter2 bits + + // OCR2B: Timer/Counter2 Output Compare Register B + OCR2B_OCR2B = 0xff // Timer/Counter2 Output Compare B bits + + // OCR2A: Timer/Counter2 Output Compare Register A + OCR2A_OCR2A = 0xff // Timer/Counter2 Output Compare A bits + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy + ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0x7 // External Interrupt Request 2 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0x7 // External Interrupt Flags + + // PCMSK3: Pin Change Mask Register 3 + PCMSK3_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0xf // Pin Change Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0xf // Pin Change Interrupt Enables +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCL: ADC Data Register Bytes + + // ADCH: ADC Data Register Bytes + ADC_ADC = 0xffff // ADC Data bits + + // ADCSRA: The ADC Control and Status register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register + DIDR0_ADC7D = 0x80 + DIDR0_ADC6D = 0x40 + DIDR0_ADC5D = 0x20 + DIDR0_ADC4D = 0x10 + DIDR0_ADC3D = 0x8 + DIDR0_ADC2D = 0x4 + DIDR0_ADC1D = 0x2 + DIDR0_ADC0D = 0x1 +) + +// Bitfields for EEPROM: EEPROM +const ( + // EEARL: EEPROM Address Register Low Bytes + + // EEARH: EEPROM Address Register Low Bytes + EEAR_EEAR = 0xfff // EEPROM Address bits + + // EEDR: EEPROM Data Register + EEDR_EEDR = 0xff // EEPROM Data bits + + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWBR: TWI Bit Rate register + TWBR_TWBR = 0xff // TWI Bit Rate bits + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWDR: TWI Data register + TWDR_TWD = 0xff // TWI Data bits + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPDR: SPI Data Register + SPDR_SPD = 0xff // SPI Data bits + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 + + // PRR0: Power Reduction Register0 + PRR0_PRTWI = 0x80 // Power Reduction TWI + PRR0_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR0_PRUSART1 = 0x10 // Power Reduction USART1 + PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR0_PRUSART0 = 0x2 // Power Reduction USART0 + PRR0_PRADC = 0x1 // Power Reduction ADC + + // PRR1: Power Reduction Register1 + PRR1_PRTIM3 = 0x1 // Power Reduction Timer/Counter3 +) diff --git a/src/device/avr/atmega1284p.ld b/src/device/avr/atmega1284p.ld new file mode 100644 index 00000000..a3de2534 --- /dev/null +++ b/src/device/avr/atmega1284p.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega1284P.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x20000; +__ram_size = 0x4000; +__num_isrs = 35; diff --git a/src/device/avr/atmega1284rfr2.go b/src/device/avr/atmega1284rfr2.go new file mode 100644 index 00000000..f7f3e79b --- /dev/null +++ b/src/device/avr/atmega1284rfr2.go @@ -0,0 +1,1793 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega1284RFR2.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega1284rfr2 + +// Device information for the ATmega1284RFR2. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega1284RFR2" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_INT3 = 4 // External Interrupt Request 3 + IRQ_INT4 = 5 // External Interrupt Request 4 + IRQ_INT5 = 6 // External Interrupt Request 5 + IRQ_INT6 = 7 // External Interrupt Request 6 + IRQ_INT7 = 8 // External Interrupt Request 7 + IRQ_PCINT0 = 9 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 10 // Pin Change Interrupt Request 1 + IRQ_PCINT2 = 11 // Pin Change Interrupt Request 2 + IRQ_WDT = 12 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 13 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 14 // Timer/Counter2 Compare Match B + IRQ_TIMER2_OVF = 15 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 16 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 17 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 18 // Timer/Counter1 Compare Match B + IRQ_TIMER1_COMPC = 19 // Timer/Counter1 Compare Match C + IRQ_TIMER1_OVF = 20 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 21 // Timer/Counter0 Compare Match A + IRQ_TIMER0_COMPB = 22 // Timer/Counter0 Compare Match B + IRQ_TIMER0_OVF = 23 // Timer/Counter0 Overflow + IRQ_SPI_STC = 24 // SPI Serial Transfer Complete + IRQ_USART0_RX = 25 // USART0, Rx Complete + IRQ_USART0_UDRE = 26 // USART0 Data register Empty + IRQ_USART0_TX = 27 // USART0, Tx Complete + IRQ_ANALOG_COMP = 28 // Analog Comparator + IRQ_ADC = 29 // ADC Conversion Complete + IRQ_EE_READY = 30 // EEPROM Ready + IRQ_TIMER3_CAPT = 31 // Timer/Counter3 Capture Event + IRQ_TIMER3_COMPA = 32 // Timer/Counter3 Compare Match A + IRQ_TIMER3_COMPB = 33 // Timer/Counter3 Compare Match B + IRQ_TIMER3_COMPC = 34 // Timer/Counter3 Compare Match C + IRQ_TIMER3_OVF = 35 // Timer/Counter3 Overflow + IRQ_USART1_RX = 36 // USART1, Rx Complete + IRQ_USART1_UDRE = 37 // USART1 Data register Empty + IRQ_USART1_TX = 38 // USART1, Tx Complete + IRQ_TWI = 39 // 2-wire Serial Interface + IRQ_SPM_READY = 40 // Store Program Memory Read + IRQ_TIMER4_CAPT = 41 // Timer/Counter4 Capture Event + IRQ_TIMER4_COMPA = 42 // Timer/Counter4 Compare Match A + IRQ_TIMER4_COMPB = 43 // Timer/Counter4 Compare Match B + IRQ_TIMER4_COMPC = 44 // Timer/Counter4 Compare Match C + IRQ_TIMER4_OVF = 45 // Timer/Counter4 Overflow + IRQ_TIMER5_CAPT = 46 // Timer/Counter5 Capture Event + IRQ_TIMER5_COMPA = 47 // Timer/Counter5 Compare Match A + IRQ_TIMER5_COMPB = 48 // Timer/Counter5 Compare Match B + IRQ_TIMER5_COMPC = 49 // Timer/Counter5 Compare Match C + IRQ_TIMER5_OVF = 50 // Timer/Counter5 Overflow + IRQ_TRX24_PLL_LOCK = 57 // TRX24 - PLL lock interrupt + IRQ_TRX24_PLL_UNLOCK = 58 // TRX24 - PLL unlock interrupt + IRQ_TRX24_RX_START = 59 // TRX24 - Receive start interrupt + IRQ_TRX24_RX_END = 60 // TRX24 - RX_END interrupt + IRQ_TRX24_CCA_ED_DONE = 61 // TRX24 - CCA/ED done interrupt + IRQ_TRX24_XAH_AMI = 62 // TRX24 - XAH - AMI + IRQ_TRX24_TX_END = 63 // TRX24 - TX_END interrupt + IRQ_TRX24_AWAKE = 64 // TRX24 AWAKE - tranceiver is reaching state TRX_OFF + IRQ_SCNT_CMP1 = 65 // Symbol counter - compare match 1 interrupt + IRQ_SCNT_CMP2 = 66 // Symbol counter - compare match 2 interrupt + IRQ_SCNT_CMP3 = 67 // Symbol counter - compare match 3 interrupt + IRQ_SCNT_OVFL = 68 // Symbol counter - overflow interrupt + IRQ_SCNT_BACKOFF = 69 // Symbol counter - backoff interrupt + IRQ_AES_READY = 70 // AES engine ready interrupt + IRQ_BAT_LOW = 71 // Battery monitor indicates supply voltage below threshold + IRQ_TRX24_TX_START = 72 // TRX24 TX start interrupt + IRQ_TRX24_AMI0 = 73 // Address match interrupt of address filter 0 + IRQ_TRX24_AMI1 = 74 // Address match interrupt of address filter 1 + IRQ_TRX24_AMI2 = 75 // Address match interrupt of address filter 2 + IRQ_TRX24_AMI3 = 76 // Address match interrupt of address filter 3 + IRQ_max = 76 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // USART + USART = struct { + UDR0 __reg + UBRR0L __reg + UBRR0H __reg + UDR1 __reg + UBRR1L __reg + UBRR1H __reg + }{ + UDR0: 0xc6, // USART0 I/O Data Register + UBRR0L: 0xc4, // USART0 Baud Rate Register Bytes + UBRR0H: 0xc4, // USART0 Baud Rate Register Bytes + UDR1: 0xce, // USART1 I/O Data Register + UBRR1L: 0xcc, // USART1 Baud Rate Register Bytes + UBRR1H: 0xcc, // USART1 Baud Rate Register Bytes + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate Register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data Register + TWAR: 0xba, // TWI (Slave) Address Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins Address + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins Address + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins Address + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins Address + PORTE: 0x2e, // Port E Data Register + DDRE: 0x2d, // Port E Data Direction Register + PINE: 0x2c, // Port E Input Pins Address + PORTF: 0x31, // Port F Data Register + DDRF: 0x30, // Port F Data Direction Register + PINF: 0x2f, // Port F Input Pins Address + PORTG: 0x34, // Port G Data Register + DDRG: 0x33, // Port G Data Direction Register + PING: 0x32, // Port G Input Pins Address + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register B + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 Register + TCCR0B: 0x45, // Timer/Counter0 Control Register B + TCCR0A: 0x44, // Timer/Counter0 Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag Register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR5A __reg + TCCR5B __reg + TCCR5C __reg + TCNT5L __reg + TCNT5H __reg + OCR5AL __reg + OCR5AH __reg + OCR5BL __reg + OCR5BH __reg + OCR5CL __reg + OCR5CH __reg + ICR5L __reg + ICR5H __reg + TIMSK5 __reg + TIFR5 __reg + TCCR4A __reg + TCCR4B __reg + TCCR4C __reg + TCNT4L __reg + TCNT4H __reg + OCR4AL __reg + OCR4AH __reg + OCR4BL __reg + OCR4BH __reg + OCR4CL __reg + OCR4CH __reg + ICR4L __reg + ICR4H __reg + TIMSK4 __reg + TIFR4 __reg + TCCR3A __reg + TCCR3B __reg + TCCR3C __reg + TCNT3L __reg + TCNT3H __reg + OCR3AL __reg + OCR3AH __reg + OCR3BL __reg + OCR3BH __reg + OCR3CL __reg + OCR3CH __reg + ICR3L __reg + ICR3H __reg + TIMSK3 __reg + TIFR3 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + OCR1CL __reg + OCR1CH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR5A: 0x120, // Timer/Counter5 Control Register A + TCCR5B: 0x121, // Timer/Counter5 Control Register B + TCCR5C: 0x122, // Timer/Counter5 Control Register C + TCNT5L: 0x124, // Timer/Counter5 Bytes + TCNT5H: 0x124, // Timer/Counter5 Bytes + OCR5AL: 0x128, // Timer/Counter5 Output Compare Register A Bytes + OCR5AH: 0x128, // Timer/Counter5 Output Compare Register A Bytes + OCR5BL: 0x12a, // Timer/Counter5 Output Compare Register B Bytes + OCR5BH: 0x12a, // Timer/Counter5 Output Compare Register B Bytes + OCR5CL: 0x12c, // Timer/Counter5 Output Compare Register C Bytes + OCR5CH: 0x12c, // Timer/Counter5 Output Compare Register C Bytes + ICR5L: 0x126, // Timer/Counter5 Input Capture Register Bytes + ICR5H: 0x126, // Timer/Counter5 Input Capture Register Bytes + TIMSK5: 0x73, // Timer/Counter5 Interrupt Mask Register + TIFR5: 0x3a, // Timer/Counter5 Interrupt Flag Register + TCCR4A: 0xa0, // Timer/Counter4 Control Register A + TCCR4B: 0xa1, // Timer/Counter4 Control Register B + TCCR4C: 0xa2, // Timer/Counter4 Control Register C + TCNT4L: 0xa4, // Timer/Counter4 Bytes + TCNT4H: 0xa4, // Timer/Counter4 Bytes + OCR4AL: 0xa8, // Timer/Counter4 Output Compare Register A Bytes + OCR4AH: 0xa8, // Timer/Counter4 Output Compare Register A Bytes + OCR4BL: 0xaa, // Timer/Counter4 Output Compare Register B Bytes + OCR4BH: 0xaa, // Timer/Counter4 Output Compare Register B Bytes + OCR4CL: 0xac, // Timer/Counter4 Output Compare Register C Bytes + OCR4CH: 0xac, // Timer/Counter4 Output Compare Register C Bytes + ICR4L: 0xa6, // Timer/Counter4 Input Capture Register Bytes + ICR4H: 0xa6, // Timer/Counter4 Input Capture Register Bytes + TIMSK4: 0x72, // Timer/Counter4 Interrupt Mask Register + TIFR4: 0x39, // Timer/Counter4 Interrupt Flag Register + TCCR3A: 0x90, // Timer/Counter3 Control Register A + TCCR3B: 0x91, // Timer/Counter3 Control Register B + TCCR3C: 0x92, // Timer/Counter3 Control Register C + TCNT3L: 0x94, // Timer/Counter3 Bytes + TCNT3H: 0x94, // Timer/Counter3 Bytes + OCR3AL: 0x98, // Timer/Counter3 Output Compare Register A Bytes + OCR3AH: 0x98, // Timer/Counter3 Output Compare Register A Bytes + OCR3BL: 0x9a, // Timer/Counter3 Output Compare Register B Bytes + OCR3BH: 0x9a, // Timer/Counter3 Output Compare Register B Bytes + OCR3CL: 0x9c, // Timer/Counter3 Output Compare Register C Bytes + OCR3CH: 0x9c, // Timer/Counter3 Output Compare Register C Bytes + ICR3L: 0x96, // Timer/Counter3 Input Capture Register Bytes + ICR3H: 0x96, // Timer/Counter3 Input Capture Register Bytes + TIMSK3: 0x71, // Timer/Counter3 Interrupt Mask Register + TIFR3: 0x38, // Timer/Counter3 Interrupt Flag Register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1CL: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + OCR1CH: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag Register + } + + // Low-Power 2.4 GHz Transceiver + TRX24 = struct { + PARCR __reg + MAFSA0L __reg + MAFSA0H __reg + MAFPA0L __reg + MAFPA0H __reg + MAFSA1L __reg + MAFSA1H __reg + MAFPA1L __reg + MAFPA1H __reg + MAFSA2L __reg + MAFSA2H __reg + MAFPA2L __reg + MAFPA2H __reg + MAFSA3L __reg + MAFSA3H __reg + MAFPA3L __reg + MAFPA3H __reg + MAFCR0 __reg + MAFCR1 __reg + AES_CTRL __reg + AES_STATUS __reg + AES_STATE __reg + AES_KEY __reg + TRX_STATUS __reg + TRX_STATE __reg + TRX_CTRL_0 __reg + TRX_CTRL_1 __reg + PHY_TX_PWR __reg + PHY_RSSI __reg + PHY_ED_LEVEL __reg + PHY_CC_CCA __reg + CCA_THRES __reg + RX_CTRL __reg + SFD_VALUE __reg + TRX_CTRL_2 __reg + ANT_DIV __reg + IRQ_MASK __reg + IRQ_STATUS __reg + IRQ_MASK1 __reg + IRQ_STATUS1 __reg + VREG_CTRL __reg + BATMON __reg + XOSC_CTRL __reg + CC_CTRL_0 __reg + CC_CTRL_1 __reg + RX_SYN __reg + TRX_RPC __reg + XAH_CTRL_1 __reg + FTN_CTRL __reg + PLL_CF __reg + PLL_DCU __reg + PART_NUM __reg + VERSION_NUM __reg + MAN_ID_0 __reg + MAN_ID_1 __reg + SHORT_ADDR_0 __reg + SHORT_ADDR_1 __reg + PAN_ID_0 __reg + PAN_ID_1 __reg + IEEE_ADDR_0 __reg + IEEE_ADDR_1 __reg + IEEE_ADDR_2 __reg + IEEE_ADDR_3 __reg + IEEE_ADDR_4 __reg + IEEE_ADDR_5 __reg + IEEE_ADDR_6 __reg + IEEE_ADDR_7 __reg + XAH_CTRL_0 __reg + CSMA_SEED_0 __reg + CSMA_SEED_1 __reg + CSMA_BE __reg + TST_CTRL_DIGI __reg + TST_RX_LENGTH __reg + TRXFBST __reg + TRXFBEND __reg + }{ + PARCR: 0x138, // Power Amplifier Ramp up/down Control Register + MAFSA0L: 0x10e, // Transceiver MAC Short Address Register for Frame Filter 0 (Low Byte) + MAFSA0H: 0x10f, // Transceiver MAC Short Address Register for Frame Filter 0 (High Byte) + MAFPA0L: 0x110, // Transceiver Personal Area Network ID Register for Frame Filter 0 (Low Byte) + MAFPA0H: 0x111, // Transceiver Personal Area Network ID Register for Frame Filter 0 (High Byte) + MAFSA1L: 0x112, // Transceiver MAC Short Address Register for Frame Filter 1 (Low Byte) + MAFSA1H: 0x113, // Transceiver MAC Short Address Register for Frame Filter 1 (High Byte) + MAFPA1L: 0x114, // Transceiver Personal Area Network ID Register for Frame Filter 1 (Low Byte) + MAFPA1H: 0x115, // Transceiver Personal Area Network ID Register for Frame Filter 1 (High Byte) + MAFSA2L: 0x116, // Transceiver MAC Short Address Register for Frame Filter 2 (Low Byte) + MAFSA2H: 0x117, // Transceiver MAC Short Address Register for Frame Filter 2 (High Byte) + MAFPA2L: 0x118, // Transceiver Personal Area Network ID Register for Frame Filter 2 (Low Byte) + MAFPA2H: 0x119, // Transceiver Personal Area Network ID Register for Frame Filter 2 (High Byte) + MAFSA3L: 0x11a, // Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte) + MAFSA3H: 0x11b, // Transceiver MAC Short Address Register for Frame Filter 3 (High Byte) + MAFPA3L: 0x11c, // Transceiver Personal Area Network ID Register for Frame Filter 3 (Low Byte) + MAFPA3H: 0x11d, // Transceiver Personal Area Network ID Register for Frame Filter 3 (High Byte) + MAFCR0: 0x10c, // Multiple Address Filter Configuration Register 0 + MAFCR1: 0x10d, // Multiple Address Filter Configuration Register 1 + AES_CTRL: 0x13c, // AES Control Register + AES_STATUS: 0x13d, // AES Status Register + AES_STATE: 0x13e, // AES Plain and Cipher Text Buffer Register + AES_KEY: 0x13f, // AES Encryption and Decryption Key Buffer Register + TRX_STATUS: 0x141, // Transceiver Status Register + TRX_STATE: 0x142, // Transceiver State Control Register + TRX_CTRL_0: 0x143, // Reserved + TRX_CTRL_1: 0x144, // Transceiver Control Register 1 + PHY_TX_PWR: 0x145, // Transceiver Transmit Power Control Register + PHY_RSSI: 0x146, // Receiver Signal Strength Indicator Register + PHY_ED_LEVEL: 0x147, // Transceiver Energy Detection Level Register + PHY_CC_CCA: 0x148, // Transceiver Clear Channel Assessment (CCA) Control Register + CCA_THRES: 0x149, // Transceiver CCA Threshold Setting Register + RX_CTRL: 0x14a, // Transceiver Receive Control Register + SFD_VALUE: 0x14b, // Start of Frame Delimiter Value Register + TRX_CTRL_2: 0x14c, // Transceiver Control Register 2 + ANT_DIV: 0x14d, // Antenna Diversity Control Register + IRQ_MASK: 0x14e, // Transceiver Interrupt Enable Register + IRQ_STATUS: 0x14f, // Transceiver Interrupt Status Register + IRQ_MASK1: 0xbe, // Transceiver Interrupt Enable Register 1 + IRQ_STATUS1: 0xbf, // Transceiver Interrupt Status Register 1 + VREG_CTRL: 0x150, // Voltage Regulator Control and Status Register + BATMON: 0x151, // Battery Monitor Control and Status Register + XOSC_CTRL: 0x152, // Crystal Oscillator Control Register + CC_CTRL_0: 0x153, // Channel Control Register 0 + CC_CTRL_1: 0x154, // Channel Control Register 1 + RX_SYN: 0x155, // Transceiver Receiver Sensitivity Control Register + TRX_RPC: 0x156, // Transceiver Reduced Power Consumption Control + XAH_CTRL_1: 0x157, // Transceiver Acknowledgment Frame Control Register 1 + FTN_CTRL: 0x158, // Transceiver Filter Tuning Control Register + PLL_CF: 0x15a, // Transceiver Center Frequency Calibration Control Register + PLL_DCU: 0x15b, // Transceiver Delay Cell Calibration Control Register + PART_NUM: 0x15c, // Device Identification Register (Part Number) + VERSION_NUM: 0x15d, // Device Identification Register (Version Number) + MAN_ID_0: 0x15e, // Device Identification Register (Manufacture ID Low Byte) + MAN_ID_1: 0x15f, // Device Identification Register (Manufacture ID High Byte) + SHORT_ADDR_0: 0x160, // Transceiver MAC Short Address Register (Low Byte) + SHORT_ADDR_1: 0x161, // Transceiver MAC Short Address Register (High Byte) + PAN_ID_0: 0x162, // Transceiver Personal Area Network ID Register (Low Byte) + PAN_ID_1: 0x163, // Transceiver Personal Area Network ID Register (High Byte) + IEEE_ADDR_0: 0x164, // Transceiver MAC IEEE Address Register 0 + IEEE_ADDR_1: 0x165, // Transceiver MAC IEEE Address Register 1 + IEEE_ADDR_2: 0x166, // Transceiver MAC IEEE Address Register 2 + IEEE_ADDR_3: 0x167, // Transceiver MAC IEEE Address Register 3 + IEEE_ADDR_4: 0x168, // Transceiver MAC IEEE Address Register 4 + IEEE_ADDR_5: 0x169, // Transceiver MAC IEEE Address Register 5 + IEEE_ADDR_6: 0x16a, // Transceiver MAC IEEE Address Register 6 + IEEE_ADDR_7: 0x16b, // Transceiver MAC IEEE Address Register 7 + XAH_CTRL_0: 0x16c, // Transceiver Extended Operating Mode Control Register + CSMA_SEED_0: 0x16d, // Transceiver CSMA-CA Random Number Generator Seed Register + CSMA_SEED_1: 0x16e, // Transceiver Acknowledgment Frame Control Register 2 + CSMA_BE: 0x16f, // Transceiver CSMA-CA Back-off Exponent Control Register + TST_CTRL_DIGI: 0x176, // Transceiver Digital Test Control Register + TST_RX_LENGTH: 0x17b, // Transceiver Received Frame Length Register + TRXFBST: 0x180, // Start of frame buffer + TRXFBEND: 0x1ff, // End of frame buffer + } + + // MAC Symbol Counter + SYMCNT = struct { + SCTSTRHH __reg + SCTSTRHL __reg + SCTSTRLH __reg + SCTSTRLL __reg + SCOCR1HH __reg + SCOCR1HL __reg + SCOCR1LH __reg + SCOCR1LL __reg + SCOCR2HH __reg + SCOCR2HL __reg + SCOCR2LH __reg + SCOCR2LL __reg + SCOCR3HH __reg + SCOCR3HL __reg + SCOCR3LH __reg + SCOCR3LL __reg + SCTSRHH __reg + SCTSRHL __reg + SCTSRLH __reg + SCTSRLL __reg + SCBTSRHH __reg + SCBTSRHL __reg + SCBTSRLH __reg + SCBTSRLL __reg + SCCNTHH __reg + SCCNTHL __reg + SCCNTLH __reg + SCCNTLL __reg + SCIRQS __reg + SCIRQM __reg + SCSR __reg + SCCR1 __reg + SCCR0 __reg + SCCSR __reg + SCRSTRHH __reg + SCRSTRHL __reg + SCRSTRLH __reg + SCRSTRLL __reg + }{ + SCTSTRHH: 0xfc, // Symbol Counter Transmit Frame Timestamp Register HH-Byte + SCTSTRHL: 0xfb, // Symbol Counter Transmit Frame Timestamp Register HL-Byte + SCTSTRLH: 0xfa, // Symbol Counter Transmit Frame Timestamp Register LH-Byte + SCTSTRLL: 0xf9, // Symbol Counter Transmit Frame Timestamp Register LL-Byte + SCOCR1HH: 0xf8, // Symbol Counter Output Compare Register 1 HH-Byte + SCOCR1HL: 0xf7, // Symbol Counter Output Compare Register 1 HL-Byte + SCOCR1LH: 0xf6, // Symbol Counter Output Compare Register 1 LH-Byte + SCOCR1LL: 0xf5, // Symbol Counter Output Compare Register 1 LL-Byte + SCOCR2HH: 0xf4, // Symbol Counter Output Compare Register 2 HH-Byte + SCOCR2HL: 0xf3, // Symbol Counter Output Compare Register 2 HL-Byte + SCOCR2LH: 0xf2, // Symbol Counter Output Compare Register 2 LH-Byte + SCOCR2LL: 0xf1, // Symbol Counter Output Compare Register 2 LL-Byte + SCOCR3HH: 0xf0, // Symbol Counter Output Compare Register 3 HH-Byte + SCOCR3HL: 0xef, // Symbol Counter Output Compare Register 3 HL-Byte + SCOCR3LH: 0xee, // Symbol Counter Output Compare Register 3 LH-Byte + SCOCR3LL: 0xed, // Symbol Counter Output Compare Register 3 LL-Byte + SCTSRHH: 0xec, // Symbol Counter Frame Timestamp Register HH-Byte + SCTSRHL: 0xeb, // Symbol Counter Frame Timestamp Register HL-Byte + SCTSRLH: 0xea, // Symbol Counter Frame Timestamp Register LH-Byte + SCTSRLL: 0xe9, // Symbol Counter Frame Timestamp Register LL-Byte + SCBTSRHH: 0xe8, // Symbol Counter Beacon Timestamp Register HH-Byte + SCBTSRHL: 0xe7, // Symbol Counter Beacon Timestamp Register HL-Byte + SCBTSRLH: 0xe6, // Symbol Counter Beacon Timestamp Register LH-Byte + SCBTSRLL: 0xe5, // Symbol Counter Beacon Timestamp Register LL-Byte + SCCNTHH: 0xe4, // Symbol Counter Register HH-Byte + SCCNTHL: 0xe3, // Symbol Counter Register HL-Byte + SCCNTLH: 0xe2, // Symbol Counter Register LH-Byte + SCCNTLL: 0xe1, // Symbol Counter Register LL-Byte + SCIRQS: 0xe0, // Symbol Counter Interrupt Status Register + SCIRQM: 0xdf, // Symbol Counter Interrupt Mask Register + SCSR: 0xde, // Symbol Counter Status Register + SCCR1: 0xdd, // Symbol Counter Control Register 1 + SCCR0: 0xdc, // Symbol Counter Control Register 0 + SCCSR: 0xdb, // Symbol Counter Compare Source Register + SCRSTRHH: 0xda, // Symbol Counter Received Frame Timestamp Register HH-Byte + SCRSTRHL: 0xd9, // Symbol Counter Received Frame Timestamp Register HL-Byte + SCRSTRLH: 0xd8, // Symbol Counter Received Frame Timestamp Register LH-Byte + SCRSTRLL: 0xd7, // Symbol Counter Received Frame Timestamp Register LL-Byte + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Bytes + EEARH: 0x41, // EEPROM Address Register Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EICRB __reg + EIMSK __reg + EIFR __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + PCICR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EICRB: 0x6a, // External Interrupt Control Register B + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + ADCSRC __reg + DIDR2 __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC Multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // The ADC Control and Status Register A + ADCSRC: 0x77, // The ADC Control and Status Register C + DIDR2: 0x7d, // Digital Input Disable Register 2 + DIDR0: 0x7e, // Digital Input Disable Register 0 + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + RAMPZ __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PRR2 __reg + PRR1 __reg + PRR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + SMCR: 0x53, // Sleep Mode Control Register + RAMPZ: 0x5b, // Extended Z-pointer Register for ELPM/SPM + GPIOR2: 0x4b, // General Purpose I/O Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PRR2: 0x63, // Power Reduction Register 2 + PRR1: 0x65, // Power Reduction Register 1 + PRR0: 0x64, // Power Reduction Register0 + } + + // FLASH Controller + FLASH = struct { + NEMCR __reg + BGCR __reg + }{ + NEMCR: 0x75, // Flash Extended-Mode Control-Register + BGCR: 0x67, // Reference Voltage Calibration Register + } + + // Power Controller + PWRCTRL = struct { + TRXPR __reg + DRTRAM0 __reg + DRTRAM1 __reg + DRTRAM2 __reg + DRTRAM3 __reg + LLDRL __reg + LLDRH __reg + LLCR __reg + DPDS0 __reg + DPDS1 __reg + }{ + TRXPR: 0x139, // Transceiver Pin Register + DRTRAM0: 0x135, // Data Retention Configuration Register #0 + DRTRAM1: 0x134, // Data Retention Configuration Register #1 + DRTRAM2: 0x133, // Data Retention Configuration Register #2 + DRTRAM3: 0x132, // Data Retention Configuration Register #3 + LLDRL: 0x130, // Low Leakage Voltage Regulator Data Register (Low-Byte) + LLDRH: 0x131, // Low Leakage Voltage Regulator Data Register (High-Byte) + LLCR: 0x12f, // Low Leakage Voltage Regulator Control Register + DPDS0: 0x136, // Port Driver Strength Register 0 + DPDS1: 0x137, // Port Driver Strength Register 1 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_CKSEL_SUT = 0x3f // Select Clock Source : Start-up time +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe // TWI Address Mask + TWAMR_Res = 0x1 // Reserved Bit + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI START Condition Bit + TWCR_TWSTO = 0x10 // TWI STOP Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collision Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_Res = 0x2 // Reserved Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_Res = 0x4 // Reserved Bit + TWSR_TWPS = 0x3 // TWI Prescaler Bits + + // TWAR: TWI (Slave) Address Register + TWAR_TWA = 0xfe // TWI (Slave) Address + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Select 1 and 0 + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_Res = 0x3e // Reserved + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter0 Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_Res = 0x30 // Reserved Bit + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter0 Control Register A + TCCR0A_COM0A = 0xc0 // Compare Match Output A Mode + TCCR0A_COM0B = 0x30 // Compare Match Output B Mode + TCCR0A_Res = 0xc // Reserved Bit + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_Res = 0xf8 // Reserved + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag Register + TIFR0_Res = 0xf8 // Reserved + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare B Match Flag + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare A Match Flag + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_Res = 0xf8 // Reserved Bit + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_Res = 0xf8 // Reserved Bit + TIFR2_OCF2B = 0x4 // Output Compare Flag 2 B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2 A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Match Output A Mode + TCCR2A_COM2B = 0x30 // Compare Match Output B Mode + TCCR2A_Res = 0xc // Reserved + TCCR2A_WGM2 = 0x3 // Waveform Generation Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_Res = 0x30 // Reserved + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select + + // ASSR: Asynchronous Status Register + ASSR_EXCLKAMR = 0x80 // Enable External Clock Input for AMR + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Timer/Counter2 Asynchronous Mode + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Timer/Counter2 Output Compare Register A Update Busy + ASSR_OCR2BUB = 0x4 // Timer/Counter2 Output Compare Register B Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter2 Control Register A Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter2 Control Register B Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR5A: Timer/Counter5 Control Register A + TCCR5A_COM5A = 0xc0 // Compare Output Mode for Channel A + TCCR5A_COM5B = 0x30 // Compare Output Mode for Channel B + TCCR5A_COM5C = 0xc // Compare Output Mode for Channel C + TCCR5A_WGM5 = 0x3 // Waveform Generation Mode + + // TCCR5B: Timer/Counter5 Control Register B + TCCR5B_ICNC5 = 0x80 // Input Capture 5 Noise Canceller + TCCR5B_ICES5 = 0x40 // Input Capture 5 Edge Select + TCCR5B_Res = 0x20 // Reserved Bit + TCCR5B_WGM5 = 0x18 // Waveform Generation Mode + TCCR5B_CS5 = 0x7 // Clock Select + + // TCCR5C: Timer/Counter5 Control Register C + TCCR5C_FOC5A = 0x80 // Force Output Compare for Channel A + TCCR5C_FOC5B = 0x40 // Force Output Compare for Channel B + TCCR5C_FOC5C = 0x20 // Force Output Compare for Channel C + TCCR5C_Res = 0x1f // Reserved + + // TIMSK5: Timer/Counter5 Interrupt Mask Register + TIMSK5_ICIE5 = 0x20 // Timer/Counter5 Input Capture Interrupt Enable + TIMSK5_OCIE5C = 0x8 // Timer/Counter5 Output Compare C Match Interrupt Enable + TIMSK5_OCIE5B = 0x4 // Timer/Counter5 Output Compare B Match Interrupt Enable + TIMSK5_OCIE5A = 0x2 // Timer/Counter5 Output Compare A Match Interrupt Enable + TIMSK5_TOIE5 = 0x1 // Timer/Counter5 Overflow Interrupt Enable + + // TIFR5: Timer/Counter5 Interrupt Flag Register + TIFR5_ICF5 = 0x20 // Timer/Counter5 Input Capture Flag + TIFR5_OCF5C = 0x8 // Timer/Counter5 Output Compare C Match Flag + TIFR5_OCF5B = 0x4 // Timer/Counter5 Output Compare B Match Flag + TIFR5_OCF5A = 0x2 // Timer/Counter5 Output Compare A Match Flag + TIFR5_TOV5 = 0x1 // Timer/Counter5 Overflow Flag + + // TCCR4A: Timer/Counter4 Control Register A + TCCR4A_COM4A = 0xc0 // Compare Output Mode for Channel A + TCCR4A_COM4B = 0x30 // Compare Output Mode for Channel B + TCCR4A_COM4C = 0xc // Compare Output Mode for Channel C + TCCR4A_WGM4 = 0x3 // Waveform Generation Mode + + // TCCR4B: Timer/Counter4 Control Register B + TCCR4B_ICNC4 = 0x80 // Input Capture 4 Noise Canceller + TCCR4B_ICES4 = 0x40 // Input Capture 4 Edge Select + TCCR4B_Res = 0x20 // Reserved Bit + TCCR4B_WGM4 = 0x18 // Waveform Generation Mode + TCCR4B_CS4 = 0x7 // Clock Select + + // TCCR4C: Timer/Counter4 Control Register C + TCCR4C_FOC4A = 0x80 // Force Output Compare for Channel A + TCCR4C_FOC4B = 0x40 // Force Output Compare for Channel B + TCCR4C_FOC4C = 0x20 // Force Output Compare for Channel C + TCCR4C_Res = 0x1f // Reserved + + // TIMSK4: Timer/Counter4 Interrupt Mask Register + TIMSK4_ICIE4 = 0x20 // Timer/Counter4 Input Capture Interrupt Enable + TIMSK4_OCIE4C = 0x8 // Timer/Counter4 Output Compare C Match Interrupt Enable + TIMSK4_OCIE4B = 0x4 // Timer/Counter4 Output Compare B Match Interrupt Enable + TIMSK4_OCIE4A = 0x2 // Timer/Counter4 Output Compare A Match Interrupt Enable + TIMSK4_TOIE4 = 0x1 // Timer/Counter4 Overflow Interrupt Enable + + // TIFR4: Timer/Counter4 Interrupt Flag Register + TIFR4_ICF4 = 0x20 // Timer/Counter4 Input Capture Flag + TIFR4_OCF4C = 0x8 // Timer/Counter4 Output Compare C Match Flag + TIFR4_OCF4B = 0x4 // Timer/Counter4 Output Compare B Match Flag + TIFR4_OCF4A = 0x2 // Timer/Counter4 Output Compare A Match Flag + TIFR4_TOV4 = 0x1 // Timer/Counter4 Overflow Flag + + // TCCR3A: Timer/Counter3 Control Register A + TCCR3A_COM3A = 0xc0 // Compare Output Mode for Channel A + TCCR3A_COM3B = 0x30 // Compare Output Mode for Channel B + TCCR3A_COM3C = 0xc // Compare Output Mode for Channel C + TCCR3A_WGM3 = 0x3 // Waveform Generation Mode + + // TCCR3B: Timer/Counter3 Control Register B + TCCR3B_ICNC3 = 0x80 // Input Capture 3 Noise Canceller + TCCR3B_ICES3 = 0x40 // Input Capture 3 Edge Select + TCCR3B_Res = 0x20 // Reserved Bit + TCCR3B_WGM3 = 0x18 // Waveform Generation Mode + TCCR3B_CS3 = 0x7 // Clock Select + + // TCCR3C: Timer/Counter3 Control Register C + TCCR3C_FOC3A = 0x80 // Force Output Compare for Channel A + TCCR3C_FOC3B = 0x40 // Force Output Compare for Channel B + TCCR3C_FOC3C = 0x20 // Force Output Compare for Channel C + TCCR3C_Res = 0x1f // Reserved + + // TIMSK3: Timer/Counter3 Interrupt Mask Register + TIMSK3_ICIE3 = 0x20 // Timer/Counter3 Input Capture Interrupt Enable + TIMSK3_OCIE3C = 0x8 // Timer/Counter3 Output Compare C Match Interrupt Enable + TIMSK3_OCIE3B = 0x4 // Timer/Counter3 Output Compare B Match Interrupt Enable + TIMSK3_OCIE3A = 0x2 // Timer/Counter3 Output Compare A Match Interrupt Enable + TIMSK3_TOIE3 = 0x1 // Timer/Counter3 Overflow Interrupt Enable + + // TIFR3: Timer/Counter3 Interrupt Flag Register + TIFR3_ICF3 = 0x20 // Timer/Counter3 Input Capture Flag + TIFR3_OCF3C = 0x8 // Timer/Counter3 Output Compare C Match Flag + TIFR3_OCF3B = 0x4 // Timer/Counter3 Output Compare B Match Flag + TIFR3_OCF3A = 0x2 // Timer/Counter3 Output Compare A Match Flag + TIFR3_TOV3 = 0x1 // Timer/Counter3 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode for Channel A + TCCR1A_COM1B = 0x30 // Compare Output Mode for Channel B + TCCR1A_COM1C = 0xc // Compare Output Mode for Channel C + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceller + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_Res = 0x20 // Reserved Bit + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Clock Select + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare for Channel A + TCCR1C_FOC1B = 0x40 // Force Output Compare for Channel B + TCCR1C_FOC1C = 0x20 // Force Output Compare for Channel C + TCCR1C_Res = 0x1f // Reserved + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1C = 0x8 // Timer/Counter1 Output Compare C Match Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag Register + TIFR1_ICF1 = 0x20 // Timer/Counter1 Input Capture Flag + TIFR1_OCF1C = 0x8 // Timer/Counter1 Output Compare C Match Flag + TIFR1_OCF1B = 0x4 // Timer/Counter1 Output Compare B Match Flag + TIFR1_OCF1A = 0x2 // Timer/Counter1 Output Compare A Match Flag + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for TRX24: Low-Power 2.4 GHz Transceiver +const ( + // PARCR: Power Amplifier Ramp up/down Control Register + PARCR_PALTD = 0xe0 // ext. PA Ramp Down Lead Time + PARCR_PALTU = 0x1c // ext. PA Ramp Up Lead Time + PARCR_PARDFI = 0x2 // Power Amplifier Ramp Down Frequency Inversion + PARCR_PARUFI = 0x1 // Power Amplifier Ramp Up Frequency Inversion + + // MAFSA0L: Transceiver MAC Short Address Register for Frame Filter 0 (Low Byte) + MAFSA0L_MAFSA0L = 0xff // MAC Short Address low Byte for Frame Filter 0 + + // MAFSA0H: Transceiver MAC Short Address Register for Frame Filter 0 (High Byte) + MAFSA0H_MAFSA0H = 0xff // MAC Short Address high Byte for Frame Filter 0 + + // MAFPA0L: Transceiver Personal Area Network ID Register for Frame Filter 0 (Low Byte) + MAFPA0L_MAFPA0L = 0xff // MAC Personal Area Network ID low Byte for Frame Filter 0 + + // MAFPA0H: Transceiver Personal Area Network ID Register for Frame Filter 0 (High Byte) + MAFPA0H_MAFPA0H = 0xff // MAC Personal Area Network ID high Byte for Frame Filter 0 + + // MAFSA1L: Transceiver MAC Short Address Register for Frame Filter 1 (Low Byte) + MAFSA1L_MAFSA1L = 0xff // MAC Short Address low Byte for Frame Filter 1 + + // MAFSA1H: Transceiver MAC Short Address Register for Frame Filter 1 (High Byte) + MAFSA1H_MAFSA1H = 0xff // MAC Short Address high Byte for Frame Filter 1 + + // MAFPA1L: Transceiver Personal Area Network ID Register for Frame Filter 1 (Low Byte) + MAFPA1L_MAFPA1L = 0xff // MAC Personal Area Network ID low Byte for Frame Filter 1 + + // MAFPA1H: Transceiver Personal Area Network ID Register for Frame Filter 1 (High Byte) + MAFPA1H_MAFPA1H = 0xff // MAC Personal Area Network ID high Byte for Frame Filter 1 + + // MAFSA2L: Transceiver MAC Short Address Register for Frame Filter 2 (Low Byte) + MAFSA2L_MAFSA2L = 0xff // MAC Short Address low Byte for Frame Filter 2 + + // MAFSA2H: Transceiver MAC Short Address Register for Frame Filter 2 (High Byte) + MAFSA2H_MAFSA2H = 0xff // MAC Short Address high Byte for Frame Filter 2 + + // MAFPA2L: Transceiver Personal Area Network ID Register for Frame Filter 2 (Low Byte) + MAFPA2L_MAFPA2L = 0xff // MAC Personal Area Network ID low Byte for Frame Filter 2 + + // MAFPA2H: Transceiver Personal Area Network ID Register for Frame Filter 2 (High Byte) + MAFPA2H_MAFPA2H = 0xff // MAC Personal Area Network ID high Byte for Frame Filter 2 + + // MAFSA3L: Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte) + MAFSA3L_MAFSA3L = 0xff // MAC Short Address low Byte for Frame Filter 3 + + // MAFSA3H: Transceiver MAC Short Address Register for Frame Filter 3 (High Byte) + MAFSA3H_MAFSA3H = 0xff // MAC Short Address high Byte for Frame Filter 3 + + // MAFPA3L: Transceiver Personal Area Network ID Register for Frame Filter 3 (Low Byte) + MAFPA3L_MAFPA3L = 0xff // MAC Personal Area Network ID low Byte for Frame Filter 3 + + // MAFPA3H: Transceiver Personal Area Network ID Register for Frame Filter 3 (High Byte) + MAFPA3H_MAFPA3H = 0xff // MAC Personal Area Network ID high Byte for Frame Filter 3 + + // MAFCR0: Multiple Address Filter Configuration Register 0 + MAFCR0_Res = 0xf0 // Reserved Bit + MAFCR0_MAF3EN = 0x8 // Multiple Address Filter 3 Enable + MAFCR0_MAF2EN = 0x4 // Multiple Address Filter 2 Enable + MAFCR0_MAF1EN = 0x2 // Multiple Address Filter 1 Enable + MAFCR0_MAF0EN = 0x1 // Multiple Address Filter 0 Enable + + // MAFCR1: Multiple Address Filter Configuration Register 1 + MAFCR1_AACK_3_SET_PD = 0x80 // Set Data Pending bit for address filter 3. + MAFCR1_AACK_3_I_AM_COORD = 0x40 // Enable PAN Coordinator mode for address filter 3. + MAFCR1_AACK_2_SET_PD = 0x20 // Set Data Pending bit for address filter 2. + MAFCR1_AACK_2_I_AM_COORD = 0x10 // Enable PAN Coordinator mode for address filter 2. + MAFCR1_AACK_1_SET_PD = 0x8 // Set Data Pending bit for address filter 1. + MAFCR1_AACK_1_I_AM_COORD = 0x4 // Enable PAN Coordinator mode for address filter 1. + MAFCR1_AACK_0_SET_PD = 0x2 // Set Data Pending bit for address filter 0. + MAFCR1_AACK_0_I_AM_COORD = 0x1 // Enable PAN Coordinator mode for address filter 0. + + // AES_CTRL: AES Control Register + AES_CTRL_AES_REQUEST = 0x80 // Request AES Operation. + AES_CTRL_AES_MODE = 0x20 // Set AES Operation Mode + AES_CTRL_AES_DIR = 0x8 // Set AES Operation Direction + AES_CTRL_AES_IM = 0x4 // AES Interrupt Enable + + // AES_STATUS: AES Status Register + AES_STATUS_AES_ER = 0x80 // AES Operation Finished with Error + AES_STATUS_Res = 0x7e // Reserved + AES_STATUS_AES_DONE = 0x1 // AES Operation Finished with Success + + // AES_STATE: AES Plain and Cipher Text Buffer Register + AES_STATE_AES_STATE = 0xff // AES Plain and Cipher Text Buffer + + // AES_KEY: AES Encryption and Decryption Key Buffer Register + AES_KEY_AES_KEY = 0xff // AES Encryption/Decryption Key Buffer + + // TRX_STATUS: Transceiver Status Register + TRX_STATUS_CCA_DONE = 0x80 // CCA Algorithm Status + TRX_STATUS_CCA_STATUS = 0x40 // CCA Status Result + TRX_STATUS_TST_STATUS = 0x20 // Test mode status + TRX_STATUS_TRX_STATUS = 0x1f // Transceiver Main Status + + // TRX_STATE: Transceiver State Control Register + TRX_STATE_TRAC_STATUS = 0xe0 // Transaction Status + TRX_STATE_TRX_CMD = 0x1f // State Control Command + + // TRX_CTRL_0: Reserved + TRX_CTRL_0_Res7 = 0x80 // Reserved + TRX_CTRL_0_PMU_EN = 0x40 // Enable Phase Measurement Unit + TRX_CTRL_0_PMU_START = 0x20 // Start of Phase Measurement Unit + TRX_CTRL_0_PMU_IF_INV = 0x10 // PMU IF Inverse + TRX_CTRL_0_Res = 0xf // Reserved + + // TRX_CTRL_1: Transceiver Control Register 1 + TRX_CTRL_1_PA_EXT_EN = 0x80 // External PA support enable + TRX_CTRL_1_IRQ_2_EXT_EN = 0x40 // Connect Frame Start IRQ to TC1 + TRX_CTRL_1_TX_AUTO_CRC_ON = 0x20 // Enable Automatic CRC Calculation + TRX_CTRL_1_PLL_TX_FLT = 0x10 // Enable PLL TX filter + TRX_CTRL_1_Res = 0xf // Reserved + + // PHY_TX_PWR: Transceiver Transmit Power Control Register + PHY_TX_PWR_Res = 0xf0 // Reserved + PHY_TX_PWR_TX_PWR = 0xf // Transmit Power Setting + + // PHY_RSSI: Receiver Signal Strength Indicator Register + PHY_RSSI_RX_CRC_VALID = 0x80 // Received Frame CRC Status + PHY_RSSI_RND_VALUE = 0x60 // Random Value + PHY_RSSI_RSSI = 0x1f // Receiver Signal Strength Indicator + + // PHY_ED_LEVEL: Transceiver Energy Detection Level Register + PHY_ED_LEVEL_ED_LEVEL = 0xff // Energy Detection Level + + // PHY_CC_CCA: Transceiver Clear Channel Assessment (CCA) Control Register + PHY_CC_CCA_CCA_REQUEST = 0x80 // Manual CCA Measurement Request + PHY_CC_CCA_CCA_MODE = 0x60 // Select CCA Measurement Mode + PHY_CC_CCA_CHANNEL = 0x1f // RX/TX Channel Selection + + // CCA_THRES: Transceiver CCA Threshold Setting Register + CCA_THRES_CCA_CS_THRES = 0xf0 // CS Threshold Level for CCA Measurement + CCA_THRES_CCA_ED_THRES = 0xf // ED Threshold Level for CCA Measurement + + // RX_CTRL: Transceiver Receive Control Register + RX_CTRL_PDT_THRES = 0xf // Receiver Sensitivity Control + + // SFD_VALUE: Start of Frame Delimiter Value Register + SFD_VALUE_SFD_VALUE = 0xff // Start of Frame Delimiter Value + + // TRX_CTRL_2: Transceiver Control Register 2 + TRX_CTRL_2_RX_SAFE_MODE = 0x80 // RX Safe Mode + TRX_CTRL_2_Res = 0x7c // Reserved + TRX_CTRL_2_OQPSK_DATA_RATE = 0x3 // Data Rate Selection + + // ANT_DIV: Antenna Diversity Control Register + ANT_DIV_ANT_SEL = 0x80 // Antenna Diversity Antenna Status + ANT_DIV_Res = 0x70 // Reserved + ANT_DIV_ANT_DIV_EN = 0x8 // Enable Antenna Diversity + ANT_DIV_ANT_EXT_SW_EN = 0x4 // Enable External Antenna Switch Control + ANT_DIV_ANT_CTRL = 0x3 // Static Antenna Diversity Switch Control + + // IRQ_MASK: Transceiver Interrupt Enable Register + IRQ_MASK_AWAKE_EN = 0x80 // Awake Interrupt Enable + IRQ_MASK_TX_END_EN = 0x40 // TX_END Interrupt Enable + IRQ_MASK_AMI_EN = 0x20 // Address Match Interrupt Enable + IRQ_MASK_CCA_ED_DONE_EN = 0x10 // End of ED Measurement Interrupt Enable + IRQ_MASK_RX_END_EN = 0x8 // RX_END Interrupt Enable + IRQ_MASK_RX_START_EN = 0x4 // RX_START Interrupt Enable + IRQ_MASK_PLL_UNLOCK_EN = 0x2 // PLL Unlock Interrupt Enable + IRQ_MASK_PLL_LOCK_EN = 0x1 // PLL Lock Interrupt Enable + + // IRQ_STATUS: Transceiver Interrupt Status Register + IRQ_STATUS_AWAKE = 0x80 // Awake Interrupt Status + IRQ_STATUS_TX_END = 0x40 // TX_END Interrupt Status + IRQ_STATUS_AMI = 0x20 // Address Match Interrupt Status + IRQ_STATUS_CCA_ED_DONE = 0x10 // End of ED Measurement Interrupt Status + IRQ_STATUS_RX_END = 0x8 // RX_END Interrupt Status + IRQ_STATUS_RX_START = 0x4 // RX_START Interrupt Status + IRQ_STATUS_PLL_UNLOCK = 0x2 // PLL Unlock Interrupt Status + IRQ_STATUS_PLL_LOCK = 0x1 // PLL Lock Interrupt Status + + // IRQ_MASK1: Transceiver Interrupt Enable Register 1 + IRQ_MASK1_Res = 0xe0 // Reserved Bit + IRQ_MASK1_MAF_3_AMI_EN = 0x10 // Address Match Interrupt enable Address filter 3 + IRQ_MASK1_MAF_2_AMI_EN = 0x8 // Address Match Interrupt enable Address filter 2 + IRQ_MASK1_MAF_1_AMI_EN = 0x4 // Address Match Interrupt enable Address filter 1 + IRQ_MASK1_MAF_0_AMI_EN = 0x2 // Address Match Interrupt enable Address filter 0 + IRQ_MASK1_TX_START_EN = 0x1 // Transmit Start Interrupt enable + + // IRQ_STATUS1: Transceiver Interrupt Status Register 1 + IRQ_STATUS1_Res = 0xe0 // Reserved Bit + IRQ_STATUS1_MAF_3_AMI = 0x10 // Address Match Interrupt Status Address filter 3 + IRQ_STATUS1_MAF_2_AMI = 0x8 // Address Match Interrupt Status Address filter 2 + IRQ_STATUS1_MAF_1_AMI = 0x4 // Address Match Interrupt Status Address filter 1 + IRQ_STATUS1_MAF_0_AMI = 0x2 // Address Match Interrupt Status Address filter 0 + IRQ_STATUS1_TX_START = 0x1 // Transmit Start Interrupt Status + + // VREG_CTRL: Voltage Regulator Control and Status Register + VREG_CTRL_AVREG_EXT = 0x80 // Use External AVDD Regulator + VREG_CTRL_AVDD_OK = 0x40 // AVDD Supply Voltage Valid + VREG_CTRL_DVREG_EXT = 0x8 // Use External DVDD Regulator + VREG_CTRL_DVDD_OK = 0x4 // DVDD Supply Voltage Valid + + // BATMON: Battery Monitor Control and Status Register + BATMON_BAT_LOW = 0x80 // Battery Monitor Interrupt Status + BATMON_BAT_LOW_EN = 0x40 // Battery Monitor Interrupt Enable + BATMON_BATMON_OK = 0x20 // Battery Monitor Status + BATMON_BATMON_HR = 0x10 // Battery Monitor Voltage Range + BATMON_BATMON_VTH = 0xf // Battery Monitor Threshold Voltage + + // XOSC_CTRL: Crystal Oscillator Control Register + XOSC_CTRL_XTAL_MODE = 0xf0 // Crystal Oscillator Operating Mode + XOSC_CTRL_XTAL_TRIM = 0xf // Crystal Oscillator Load Capacitance Trimming + + // CC_CTRL_0: Channel Control Register 0 + CC_CTRL_0_CC_NUMBER = 0xff // Channel Number + + // CC_CTRL_1: Channel Control Register 1 + CC_CTRL_1_CC_BAND = 0xf // Channel Band + + // RX_SYN: Transceiver Receiver Sensitivity Control Register + RX_SYN_RX_PDT_DIS = 0x80 // Prevent Frame Reception + RX_SYN_RX_OVERRIDE = 0x40 // Receiver Override Function + RX_SYN_Res = 0x30 // Reserved + RX_SYN_RX_PDT_LEVEL = 0xf // Reduce Receiver Sensitivity + + // TRX_RPC: Transceiver Reduced Power Consumption Control + TRX_RPC_RX_RPC_CTRL = 0xc0 // Smart Receiving Mode Timing + TRX_RPC_RX_RPC_EN = 0x20 // Reciver Smart Receiving Mode Enable + TRX_RPC_PDT_RPC_EN = 0x10 // Smart Receiving Mode Reduced Sensitivity Enable + TRX_RPC_PLL_RPC_EN = 0x8 // PLL Smart Receiving Mode Enable + TRX_RPC_Res0 = 0x4 // Reserved + TRX_RPC_IPAN_RPC_EN = 0x2 // Smart Receiving Mode IPAN Handling Enable + TRX_RPC_XAH_RPC_EN = 0x1 // Smart Receiving in Extended Operating Modes Enable + + // XAH_CTRL_1: Transceiver Acknowledgment Frame Control Register 1 + XAH_CTRL_1_AACK_FLTR_RES_FT = 0x20 // Filter Reserved Frames + XAH_CTRL_1_AACK_UPLD_RES_FT = 0x10 // Process Reserved Frames + XAH_CTRL_1_AACK_ACK_TIME = 0x4 // Reduce Acknowledgment Time + XAH_CTRL_1_AACK_PROM_MODE = 0x2 // Enable Promiscuous Mode + + // FTN_CTRL: Transceiver Filter Tuning Control Register + FTN_CTRL_FTN_START = 0x80 // Start Calibration Loop of Filter Tuning Network + + // PLL_CF: Transceiver Center Frequency Calibration Control Register + PLL_CF_PLL_CF_START = 0x80 // Start Center Frequency Calibration + + // PLL_DCU: Transceiver Delay Cell Calibration Control Register + PLL_DCU_PLL_DCU_START = 0x80 // Start Delay Cell Calibration + + // PART_NUM: Device Identification Register (Part Number) + PART_NUM_PART_NUM = 0xff // Part Number + + // VERSION_NUM: Device Identification Register (Version Number) + VERSION_NUM_VERSION_NUM = 0xff // Version Number + + // MAN_ID_0: Device Identification Register (Manufacture ID Low Byte) + MAN_ID_0_MAN_ID_07 = 0x80 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_06 = 0x40 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_05 = 0x20 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_04 = 0x10 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_03 = 0x8 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_02 = 0x4 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_01 = 0x2 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_00 = 0x1 // Manufacturer ID (Low Byte) + + // MAN_ID_1: Device Identification Register (Manufacture ID High Byte) + MAN_ID_1_MAN_ID_ = 0xff // Manufacturer ID (High Byte) + + // SHORT_ADDR_0: Transceiver MAC Short Address Register (Low Byte) + SHORT_ADDR_0_SHORT_ADDR_07 = 0x80 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_06 = 0x40 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_05 = 0x20 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_04 = 0x10 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_03 = 0x8 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_02 = 0x4 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_01 = 0x2 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_00 = 0x1 // MAC Short Address + + // SHORT_ADDR_1: Transceiver MAC Short Address Register (High Byte) + SHORT_ADDR_1_SHORT_ADDR_ = 0xff // MAC Short Address + + // PAN_ID_0: Transceiver Personal Area Network ID Register (Low Byte) + PAN_ID_0_PAN_ID_07 = 0x80 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_06 = 0x40 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_05 = 0x20 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_04 = 0x10 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_03 = 0x8 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_02 = 0x4 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_01 = 0x2 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_00 = 0x1 // MAC Personal Area Network ID + + // PAN_ID_1: Transceiver Personal Area Network ID Register (High Byte) + PAN_ID_1_PAN_ID_ = 0xff // MAC Personal Area Network ID + + // IEEE_ADDR_0: Transceiver MAC IEEE Address Register 0 + IEEE_ADDR_0_IEEE_ADDR_07 = 0x80 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_06 = 0x40 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_05 = 0x20 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_04 = 0x10 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_03 = 0x8 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_02 = 0x4 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_01 = 0x2 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_00 = 0x1 // MAC IEEE Address + + // IEEE_ADDR_1: Transceiver MAC IEEE Address Register 1 + IEEE_ADDR_1_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // IEEE_ADDR_2: Transceiver MAC IEEE Address Register 2 + IEEE_ADDR_2_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // IEEE_ADDR_3: Transceiver MAC IEEE Address Register 3 + IEEE_ADDR_3_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // IEEE_ADDR_4: Transceiver MAC IEEE Address Register 4 + IEEE_ADDR_4_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // IEEE_ADDR_5: Transceiver MAC IEEE Address Register 5 + IEEE_ADDR_5_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // IEEE_ADDR_6: Transceiver MAC IEEE Address Register 6 + IEEE_ADDR_6_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // IEEE_ADDR_7: Transceiver MAC IEEE Address Register 7 + IEEE_ADDR_7_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // XAH_CTRL_0: Transceiver Extended Operating Mode Control Register + XAH_CTRL_0_MAX_FRAME_RETRIES = 0xf0 // Maximum Number of Frame Re-transmission Attempts + XAH_CTRL_0_MAX_CSMA_RETRIES = 0xe // Maximum Number of CSMA-CA Procedure Repetition Attempts + XAH_CTRL_0_SLOTTED_OPERATION = 0x1 // Set Slotted Acknowledgment + + // CSMA_SEED_0: Transceiver CSMA-CA Random Number Generator Seed Register + CSMA_SEED_0_CSMA_SEED_07 = 0x80 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_06 = 0x40 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_05 = 0x20 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_04 = 0x10 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_03 = 0x8 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_02 = 0x4 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_01 = 0x2 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_00 = 0x1 // Seed Value for CSMA Random Number Generator + + // CSMA_SEED_1: Transceiver Acknowledgment Frame Control Register 2 + CSMA_SEED_1_AACK_FVN_MODE = 0xc0 // Acknowledgment Frame Filter Mode + CSMA_SEED_1_AACK_SET_PD = 0x20 // Set Frame Pending Sub-field + CSMA_SEED_1_AACK_DIS_ACK = 0x10 // Disable Acknowledgment Frame Transmission + CSMA_SEED_1_AACK_I_AM_COORD = 0x8 // Set Personal Area Network Coordinator + CSMA_SEED_1_CSMA_SEED_1 = 0x7 // Seed Value for CSMA Random Number Generator + + // CSMA_BE: Transceiver CSMA-CA Back-off Exponent Control Register + CSMA_BE_MAX_BE = 0xf0 // Maximum Back-off Exponent + CSMA_BE_MIN_BE = 0xf // Minimum Back-off Exponent + + // TST_CTRL_DIGI: Transceiver Digital Test Control Register + TST_CTRL_DIGI_TST_CTRL_DIG = 0xf // Digital Test Controller Register + + // TST_RX_LENGTH: Transceiver Received Frame Length Register + TST_RX_LENGTH_RX_LENGTH = 0xff // Received Frame Length +) + +// Bitfields for SYMCNT: MAC Symbol Counter +const ( + // SCTSTRHH: Symbol Counter Transmit Frame Timestamp Register HH-Byte + SCTSTRHH_SCTSTRHH = 0xff // Symbol Counter Transmit Frame Timestamp Register HH-Byte + + // SCTSTRHL: Symbol Counter Transmit Frame Timestamp Register HL-Byte + SCTSTRHL_SCTSTRHL = 0xff // Symbol Counter Transmit Frame Timestamp Register HL-Byte + + // SCTSTRLH: Symbol Counter Transmit Frame Timestamp Register LH-Byte + SCTSTRLH_SCTSTRLH = 0xff // Symbol Counter Transmit Frame Timestamp Register LH-Byte + + // SCTSTRLL: Symbol Counter Transmit Frame Timestamp Register LL-Byte + SCTSTRLL_SCTSTRLL = 0xff // Symbol Counter Transmit Frame Timestamp Register LL-Byte + + // SCOCR1HH: Symbol Counter Output Compare Register 1 HH-Byte + SCOCR1HH_SCOCR1HH = 0xff // Symbol Counter Output Compare Register 1 HH-Byte + + // SCOCR1HL: Symbol Counter Output Compare Register 1 HL-Byte + SCOCR1HL_SCOCR1HL = 0xff // Symbol Counter Output Compare Register 1 HL-Byte + + // SCOCR1LH: Symbol Counter Output Compare Register 1 LH-Byte + SCOCR1LH_SCOCR1LH = 0xff // Symbol Counter Output Compare Register 1 LH-Byte + + // SCOCR1LL: Symbol Counter Output Compare Register 1 LL-Byte + SCOCR1LL_SCOCR1LL = 0xff // Symbol Counter Output Compare Register 1 LL-Byte + + // SCOCR2HH: Symbol Counter Output Compare Register 2 HH-Byte + SCOCR2HH_SCOCR2HH = 0xff // Symbol Counter Output Compare Register 2 HH-Byte + + // SCOCR2HL: Symbol Counter Output Compare Register 2 HL-Byte + SCOCR2HL_SCOCR2HL = 0xff // Symbol Counter Output Compare Register 2 HL-Byte + + // SCOCR2LH: Symbol Counter Output Compare Register 2 LH-Byte + SCOCR2LH_SCOCR2LH = 0xff // Symbol Counter Output Compare Register 2 LH-Byte + + // SCOCR2LL: Symbol Counter Output Compare Register 2 LL-Byte + SCOCR2LL_SCOCR2LL = 0xff // Symbol Counter Output Compare Register 2 LL-Byte + + // SCOCR3HH: Symbol Counter Output Compare Register 3 HH-Byte + SCOCR3HH_SCOCR3HH = 0xff // Symbol Counter Output Compare Register 3 HH-Byte + + // SCOCR3HL: Symbol Counter Output Compare Register 3 HL-Byte + SCOCR3HL_SCOCR3HL = 0xff // Symbol Counter Output Compare Register 3 HL-Byte + + // SCOCR3LH: Symbol Counter Output Compare Register 3 LH-Byte + SCOCR3LH_SCOCR3LH = 0xff // Symbol Counter Output Compare Register 3 LH-Byte + + // SCOCR3LL: Symbol Counter Output Compare Register 3 LL-Byte + SCOCR3LL_SCOCR3LL = 0xff // Symbol Counter Output Compare Register 3 LL-Byte + + // SCTSRHH: Symbol Counter Frame Timestamp Register HH-Byte + SCTSRHH_SCTSRHH = 0xff // Symbol Counter Frame Timestamp Register HH-Byte + + // SCTSRHL: Symbol Counter Frame Timestamp Register HL-Byte + SCTSRHL_SCTSRHL = 0xff // Symbol Counter Frame Timestamp Register HL-Byte + + // SCTSRLH: Symbol Counter Frame Timestamp Register LH-Byte + SCTSRLH_SCTSRLH = 0xff // Symbol Counter Frame Timestamp Register LH-Byte + + // SCTSRLL: Symbol Counter Frame Timestamp Register LL-Byte + SCTSRLL_SCTSRLL = 0xff // Symbol Counter Frame Timestamp Register LL-Byte + + // SCBTSRHH: Symbol Counter Beacon Timestamp Register HH-Byte + SCBTSRHH_SCBTSRHH = 0xff // Symbol Counter Beacon Timestamp Register HH-Byte + + // SCBTSRHL: Symbol Counter Beacon Timestamp Register HL-Byte + SCBTSRHL_SCBTSRHL = 0xff // Symbol Counter Beacon Timestamp Register HL-Byte + + // SCBTSRLH: Symbol Counter Beacon Timestamp Register LH-Byte + SCBTSRLH_SCBTSRLH = 0xff // Symbol Counter Beacon Timestamp Register LH-Byte + + // SCBTSRLL: Symbol Counter Beacon Timestamp Register LL-Byte + SCBTSRLL_SCBTSRLL = 0xff // Symbol Counter Beacon Timestamp Register LL-Byte + + // SCCNTHH: Symbol Counter Register HH-Byte + SCCNTHH_SCCNTHH = 0xff // Symbol Counter Register HH-Byte + + // SCCNTHL: Symbol Counter Register HL-Byte + SCCNTHL_SCCNTHL = 0xff // Symbol Counter Register HL-Byte + + // SCCNTLH: Symbol Counter Register LH-Byte + SCCNTLH_SCCNTLH = 0xff // Symbol Counter Register LH-Byte + + // SCCNTLL: Symbol Counter Register LL-Byte + SCCNTLL_SCCNTLL = 0xff // Symbol Counter Register LL-Byte + + // SCIRQS: Symbol Counter Interrupt Status Register + SCIRQS_Res = 0xe0 // Reserved Bit + SCIRQS_IRQSBO = 0x10 // Backoff Slot Counter IRQ + SCIRQS_IRQSOF = 0x8 // Symbol Counter Overflow IRQ + SCIRQS_IRQSCP = 0x7 // Compare Unit 3 Compare Match IRQ + + // SCIRQM: Symbol Counter Interrupt Mask Register + SCIRQM_Res = 0xe0 // Reserved Bit + SCIRQM_IRQMBO = 0x10 // Backoff Slot Counter IRQ enable + SCIRQM_IRQMOF = 0x8 // Symbol Counter Overflow IRQ enable + SCIRQM_IRQMCP = 0x7 // Symbol Counter Compare Match 3 IRQ enable + + // SCSR: Symbol Counter Status Register + SCSR_Res = 0xfe // Reserved Bit + SCSR_SCBSY = 0x1 // Symbol Counter busy + + // SCCR1: Symbol Counter Control Register 1 + SCCR1_Res = 0xc0 // Reserved Bit + SCCR1_SCBTSM = 0x20 // Symbol Counter Beacon Timestamp Mask Register + SCCR1_SCCKDIV = 0x1c // Clock divider for synchronous clock source (16MHz Transceiver Clock) + SCCR1_SCEECLK = 0x2 // Enable External Clock Source on PG2 + SCCR1_SCENBO = 0x1 // Backoff Slot Counter enable + + // SCCR0: Symbol Counter Control Register 0 + SCCR0_SCRES = 0x80 // Symbol Counter Synchronization + SCCR0_SCMBTS = 0x40 // Manual Beacon Timestamp + SCCR0_SCEN = 0x20 // Symbol Counter enable + SCCR0_SCCKSEL = 0x10 // Symbol Counter Clock Source select + SCCR0_SCTSE = 0x8 // Symbol Counter Automatic Timestamping enable + SCCR0_SCCMP = 0x7 // Symbol Counter Compare Unit 3 Mode select + + // SCCSR: Symbol Counter Compare Source Register + SCCSR_Res = 0xc0 // Reserved Bit + SCCSR_SCCS3 = 0x30 // Symbol Counter Compare Source select register for Compare Unit 3 + SCCSR_SCCS2 = 0xc // Symbol Counter Compare Source select register for Compare Unit 2 + SCCSR_SCCS1 = 0x3 // Symbol Counter Compare Source select register for Compare Units + + // SCRSTRHH: Symbol Counter Received Frame Timestamp Register HH-Byte + SCRSTRHH_SCRSTRHH = 0xff // Symbol Counter Received Frame Timestamp Register HH-Byte + + // SCRSTRHL: Symbol Counter Received Frame Timestamp Register HL-Byte + SCRSTRHL_SCRSTRHL = 0xff // Symbol Counter Received Frame Timestamp Register HL-Byte + + // SCRSTRLH: Symbol Counter Received Frame Timestamp Register LH-Byte + SCRSTRLH_SCRSTRLH = 0xff // Symbol Counter Received Frame Timestamp Register LH-Byte + + // SCRSTRLL: Symbol Counter Received Frame Timestamp Register LL-Byte + SCRSTRLL_SCRSTRLL = 0xff // Symbol Counter Received Frame Timestamp Register LL-Byte +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_Res = 0xc0 // Reserved + EECR_EEPM = 0x30 // EEPROM Programming Mode + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Programming Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for JTAG: JTAG Interface +const ( + // OCDR: On-Chip Debug Register + OCDR_OCDR = 0xff // On-Chip Debug Register Data +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC3 = 0xc0 // External Interrupt 3 Sense Control Bit + EICRA_ISC2 = 0x30 // External Interrupt 2 Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt 1 Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt 0 Sense Control Bit + + // EICRB: External Interrupt Control Register B + EICRB_ISC7 = 0xc0 // External Interrupt 7 Sense Control Bit + EICRB_ISC6 = 0x30 // External Interrupt 6 Sense Control Bit + EICRB_ISC5 = 0xc // External Interrupt 5 Sense Control Bit + EICRB_ISC4 = 0x3 // External Interrupt 4 Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xff // External Interrupt Request Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xff // External Interrupt Flag + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Mask + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Enable Mask + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Mask + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_Res = 0xf8 // Reserved Bit + PCIFR_PCIF = 0x7 // Pin Change Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_Res = 0xf8 // Reserved Bit + PCICR_PCIE = 0x7 // Pin Change Interrupt Enables +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC Multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // ADC Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status Register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCSRC: The ADC Control and Status Register C + ADCSRC_ADTHT = 0xc0 // ADC Track-and-Hold Time + ADCSRC_Res0 = 0x20 // Reserved + ADCSRC_ADSUT = 0x1f // ADC Start-up Time + + // DIDR2: Digital Input Disable Register 2 + DIDR2_ADC15D = 0x80 // Reserved Bits + DIDR2_ADC14D = 0x40 // Reserved Bits + DIDR2_ADC13D = 0x20 // Reserved Bits + DIDR2_ADC12D = 0x10 // Reserved Bits + DIDR2_ADC11D = 0x8 // Reserved Bits + DIDR2_ADC10D = 0x4 // Reserved Bits + DIDR2_ADC9D = 0x2 // Reserved Bits + DIDR2_ADC8D = 0x1 // Reserved Bits + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // Disable ADC7:0 Digital Input + DIDR0_ADC6D = 0x40 // Disable ADC7:0 Digital Input + DIDR0_ADC5D = 0x20 // Disable ADC7:0 Digital Input + DIDR0_ADC4D = 0x10 // Disable ADC7:0 Digital Input + DIDR0_ADC3D = 0x8 // Disable ADC7:0 Digital Input + DIDR0_ADC2D = 0x4 // Disable ADC7:0 Digital Input + DIDR0_ADC1D = 0x2 // Disable ADC7:0 Digital Input + DIDR0_ADC0D = 0x1 // Disable ADC7:0 Digital Input +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write Section Read Enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_CAL = 0xff // Oscillator Calibration Tuning Value + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_Res = 0x70 // Reserved + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // SMCR: Sleep Mode Control Register + SMCR_Res = 0xf0 // Reserved + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // RAMPZ: Extended Z-pointer Register for ELPM/SPM + RAMPZ_Res = 0xfe // Reserved + RAMPZ_RAMPZ0 = 0x1 // Extended Z-Pointer Value + + // GPIOR2: General Purpose I/O Register 2 + GPIOR2_GPIOR = 0xff // General Purpose I/O Register 2 Value + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose I/O Register 1 Value + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR06 = 0x40 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR05 = 0x20 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR04 = 0x10 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR03 = 0x8 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR02 = 0x4 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR01 = 0x2 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR00 = 0x1 // General Purpose I/O Register 0 Value + + // PRR2: Power Reduction Register 2 + PRR2_PRRAM3 = 0x8 // Power Reduction SRAM3 + PRR2_PRRAM2 = 0x4 // Power Reduction SRAM2 + PRR2_PRRAM1 = 0x2 // Power Reduction SRAM1 + PRR2_PRRAM0 = 0x1 // Power Reduction SRAM0 + + // PRR1: Power Reduction Register 1 + PRR1_Res = 0x80 // Reserved Bit + PRR1_PRTRX24 = 0x40 // Power Reduction Transceiver + PRR1_PRTIM5 = 0x20 // Power Reduction Timer/Counter5 + PRR1_PRTIM4 = 0x10 // Power Reduction Timer/Counter4 + PRR1_PRTIM3 = 0x8 // Power Reduction Timer/Counter3 + PRR1_PRUSART1 = 0x1 // Power Reduction USART1 + + // PRR0: Power Reduction Register0 + PRR0_PRTWI = 0x80 // Power Reduction TWI + PRR0_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR0_PRPGA = 0x10 // Power Reduction PGA + PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR0_PRUSART0 = 0x2 // Power Reduction USART + PRR0_PRADC = 0x1 // Power Reduction ADC +) + +// Bitfields for FLASH: FLASH Controller +const ( + // NEMCR: Flash Extended-Mode Control-Register + NEMCR_ENEAM = 0x40 // Enable Extended Address Mode for Extra Rows + NEMCR_AEAM = 0x30 // Address for Extended Address Mode of Extra Rows + + // BGCR: Reference Voltage Calibration Register + BGCR_Res = 0x80 // Reserved Bit + BGCR_BGCAL_FINE = 0x78 // Fine Calibration Bits + BGCR_BGCAL = 0x7 // Coarse Calibration Bits +) + +// Bitfields for PWRCTRL: Power Controller +const ( + // TRXPR: Transceiver Pin Register + TRXPR_Res = 0xf0 // Reserved + TRXPR_SLPTR = 0x2 // Multi-purpose Transceiver Control Bit + TRXPR_TRXRST = 0x1 // Force Transceiver Reset + + // DRTRAM0: Data Retention Configuration Register #0 + DRTRAM0_Res = 0xc0 // Reserved + DRTRAM0_DRTSWOK = 0x20 // DRT Switch OK + DRTRAM0_ENDRT = 0x10 // Enable SRAM Data Retention + + // DRTRAM1: Data Retention Configuration Register #1 + DRTRAM1_Res = 0xc0 // Reserved + DRTRAM1_DRTSWOK = 0x20 // DRT Switch OK + DRTRAM1_ENDRT = 0x10 // Enable SRAM Data Retention + + // DRTRAM2: Data Retention Configuration Register #2 + DRTRAM2_Res = 0x40 // Reserved Bit + DRTRAM2_DRTSWOK = 0x20 // DRT Switch OK + DRTRAM2_ENDRT = 0x10 // Enable SRAM Data Retention + + // DRTRAM3: Data Retention Configuration Register #3 + DRTRAM3_Res = 0xc0 // Reserved + DRTRAM3_DRTSWOK = 0x20 // DRT Switch OK + DRTRAM3_ENDRT = 0x10 // Enable SRAM Data Retention + + // LLDRL: Low Leakage Voltage Regulator Data Register (Low-Byte) + LLDRL_Res = 0xf0 // Reserved + LLDRL_LLDRL = 0xf // Low-Byte Data Register Bits + + // LLDRH: Low Leakage Voltage Regulator Data Register (High-Byte) + LLDRH_Res = 0xe0 // Reserved + LLDRH_LLDRH = 0x1f // High-Byte Data Register Bits + + // LLCR: Low Leakage Voltage Regulator Control Register + LLCR_Res = 0xc0 // Reserved Bit + LLCR_LLDONE = 0x20 // Calibration Done + LLCR_LLCOMP = 0x10 // Comparator Output + LLCR_LLCAL = 0x8 // Calibration Active + LLCR_LLTCO = 0x4 // Temperature Coefficient of Current Source + LLCR_LLSHORT = 0x2 // Short Lower Calibration Circuit + LLCR_LLENCAL = 0x1 // Enable Automatic Calibration + + // DPDS0: Port Driver Strength Register 0 + DPDS0_PFDRV = 0xc0 // Driver Strength Port F + DPDS0_PEDRV = 0x30 // Driver Strength Port E + DPDS0_PDDRV = 0xc // Driver Strength Port D + DPDS0_PBDRV = 0x3 // Driver Strength Port B + + // DPDS1: Port Driver Strength Register 1 + DPDS1_Res = 0xfc // Reserved + DPDS1_PGDRV = 0x3 // Driver Strength Port G +) diff --git a/src/device/avr/atmega1284rfr2.ld b/src/device/avr/atmega1284rfr2.ld new file mode 100644 index 00000000..1f42e29b --- /dev/null +++ b/src/device/avr/atmega1284rfr2.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega1284RFR2.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x20000; +__ram_size = 0x4000; +__num_isrs = 71; diff --git a/src/device/avr/atmega128a.go b/src/device/avr/atmega128a.go new file mode 100644 index 00000000..56849fbe --- /dev/null +++ b/src/device/avr/atmega128a.go @@ -0,0 +1,666 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega128A.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega128a + +// Device information for the ATmega128A. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega128A" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_INT3 = 4 // External Interrupt Request 3 + IRQ_INT4 = 5 // External Interrupt Request 4 + IRQ_INT5 = 6 // External Interrupt Request 5 + IRQ_INT6 = 7 // External Interrupt Request 6 + IRQ_INT7 = 8 // External Interrupt Request 7 + IRQ_TIMER2_COMP = 9 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 10 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 11 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 12 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 13 // Timer/Counter Compare Match B + IRQ_TIMER1_OVF = 14 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 15 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 16 // Timer/Counter0 Overflow + IRQ_SPI_STC = 17 // SPI Serial Transfer Complete + IRQ_USART0_RX = 18 // USART0, Rx Complete + IRQ_USART0_UDRE = 19 // USART0 Data Register Empty + IRQ_USART0_TX = 20 // USART0, Tx Complete + IRQ_ADC = 21 // ADC Conversion Complete + IRQ_EE_READY = 22 // EEPROM Ready + IRQ_ANALOG_COMP = 23 // Analog Comparator + IRQ_TIMER1_COMPC = 24 // Timer/Counter1 Compare Match C + IRQ_TIMER3_CAPT = 25 // Timer/Counter3 Capture Event + IRQ_TIMER3_COMPA = 26 // Timer/Counter3 Compare Match A + IRQ_TIMER3_COMPB = 27 // Timer/Counter3 Compare Match B + IRQ_TIMER3_COMPC = 28 // Timer/Counter3 Compare Match C + IRQ_TIMER3_OVF = 29 // Timer/Counter3 Overflow + IRQ_USART1_RX = 30 // USART1, Rx Complete + IRQ_USART1_UDRE = 31 // USART1, Data Register Empty + IRQ_USART1_TX = 32 // USART1, Tx Complete + IRQ_TWI = 33 // 2-wire Serial Interface + IRQ_SPM_READY = 34 // Store Program Memory Read + IRQ_max = 34 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog Comparator + AC = struct { + ACSR __reg + }{ + ACSR: 0x28, // Analog Comparator Control And Status Register + } + + // Serial Peripheral Interface + SPI = struct { + SPDR __reg + SPSR __reg + SPCR __reg + }{ + SPDR: 0x2f, // SPI Data Register + SPSR: 0x2e, // SPI Status Register + SPCR: 0x2d, // SPI Control Register + } + + // Two Wire Serial Interface + TWI = struct { + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWBR: 0x70, // TWI Bit Rate register + TWCR: 0x74, // TWI Control Register + TWSR: 0x71, // TWI Status Register + TWDR: 0x73, // TWI Data register + TWAR: 0x72, // TWI (Slave) Address register + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0H __reg + UBRR0L __reg + UDR1 __reg + UCSR1A __reg + UCSR1B __reg + UCSR1C __reg + UBRR1H __reg + UBRR1L __reg + }{ + UDR0: 0x2c, // USART I/O Data Register + UCSR0A: 0x2b, // USART Control and Status Register A + UCSR0B: 0x2a, // USART Control and Status Register B + UCSR0C: 0x95, // USART Control and Status Register C + UBRR0H: 0x90, // USART Baud Rate Register Hight Byte + UBRR0L: 0x29, // USART Baud Rate Register Low Byte + UDR1: 0x9c, // USART I/O Data Register + UCSR1A: 0x9b, // USART Control and Status Register A + UCSR1B: 0x9a, // USART Control and Status Register B + UCSR1C: 0x9d, // USART Control and Status Register C + UBRR1H: 0x98, // USART Baud Rate Register Hight Byte + UBRR1L: 0x99, // USART Baud Rate Register Low Byte + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + MCUCR __reg + XMCRA __reg + XMCRB __reg + OSCCAL __reg + XDIV __reg + RAMPZ __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + MCUCR: 0x55, // MCU Control Register + XMCRA: 0x6d, // External Memory Control Register A + XMCRB: 0x6c, // External Memory Control Register B + OSCCAL: 0x6f, // Oscillator Calibration Value + XDIV: 0x5c, // XTAL Divide Control Register + RAMPZ: 0x5b, // RAM Page Z Select Register + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x68, // Store Program Memory Control Register + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x42, // On-Chip Debug Related Register in I/O Memory + } + + // Other Registers + MISC = struct { + }{} + + // External Interrupts + EXINT = struct { + EICRA __reg + EICRB __reg + EIMSK __reg + EIFR __reg + }{ + EICRA: 0x6a, // External Interrupt Control Register A + EICRB: 0x5a, // External Interrupt Control Register B + EIMSK: 0x59, // External Interrupt Mask Register + EIFR: 0x58, // External Interrupt Flag Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x3e, // EEPROM Read/Write Access Bytes + EEARH: 0x3e, // EEPROM Read/Write Access Bytes + EEDR: 0x3d, // EEPROM Data Register + EECR: 0x3c, // EEPROM Control Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + }{ + PORTA: 0x3b, // Port A Data Register + DDRA: 0x3a, // Port A Data Direction Register + PINA: 0x39, // Port A Input Pins + PORTB: 0x38, // Port B Data Register + DDRB: 0x37, // Port B Data Direction Register + PINB: 0x36, // Port B Input Pins + PORTC: 0x35, // Port C Data Register + DDRC: 0x34, // Port C Data Direction Register + PINC: 0x33, // Port C Input Pins + PORTD: 0x32, // Port D Data Register + DDRD: 0x31, // Port D Data Direction Register + PIND: 0x30, // Port D Input Pins + PORTE: 0x23, // Data Register, Port E + DDRE: 0x22, // Data Direction Register, Port E + PINE: 0x21, // Input Pins, Port E + PORTF: 0x62, // Data Register, Port F + DDRF: 0x61, // Data Direction Register, Port F + PINF: 0x20, // Input Pins, Port F + PORTG: 0x65, // Data Register, Port G + DDRG: 0x64, // Data Direction Register, Port G + PING: 0x63, // Input Pins, Port G + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR0 __reg + TCNT0 __reg + OCR0 __reg + ASSR __reg + }{ + TCCR0: 0x53, // Timer/Counter Control Register + TCNT0: 0x52, // Timer/Counter Register + OCR0: 0x51, // Output Compare Register + ASSR: 0x50, // Asynchronus Status Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + OCR1CL __reg + OCR1CH __reg + ICR1L __reg + ICR1H __reg + TCCR3A __reg + TCCR3B __reg + TCCR3C __reg + TCNT3L __reg + TCNT3H __reg + OCR3AL __reg + OCR3AH __reg + OCR3BL __reg + OCR3BH __reg + OCR3CL __reg + OCR3CH __reg + ICR3L __reg + ICR3H __reg + }{ + TCCR1A: 0x4f, // Timer/Counter1 Control Register A + TCCR1B: 0x4e, // Timer/Counter1 Control Register B + TCCR1C: 0x7a, // Timer/Counter1 Control Register C + TCNT1L: 0x4c, // Timer/Counter1 Bytes + TCNT1H: 0x4c, // Timer/Counter1 Bytes + OCR1AL: 0x4a, // Timer/Counter1 Output Compare Register Bytes + OCR1AH: 0x4a, // Timer/Counter1 Output Compare Register Bytes + OCR1BL: 0x48, // Timer/Counter1 Output Compare Register Bytes + OCR1BH: 0x48, // Timer/Counter1 Output Compare Register Bytes + OCR1CL: 0x78, // Timer/Counter1 Output Compare Register Bytes + OCR1CH: 0x78, // Timer/Counter1 Output Compare Register Bytes + ICR1L: 0x46, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x46, // Timer/Counter1 Input Capture Register Bytes + TCCR3A: 0x8b, // Timer/Counter3 Control Register A + TCCR3B: 0x8a, // Timer/Counter3 Control Register B + TCCR3C: 0x8c, // Timer/Counter3 Control Register C + TCNT3L: 0x88, // Timer/Counter3 Bytes + TCNT3H: 0x88, // Timer/Counter3 Bytes + OCR3AL: 0x86, // Timer/Counter3 Output Compare Register A Bytes + OCR3AH: 0x86, // Timer/Counter3 Output Compare Register A Bytes + OCR3BL: 0x84, // Timer/Counter3 Output Compare Register B Bytes + OCR3BH: 0x84, // Timer/Counter3 Output Compare Register B Bytes + OCR3CL: 0x82, // Timer/Counter3 Output compare Register C Bytes + OCR3CH: 0x82, // Timer/Counter3 Output compare Register C Bytes + ICR3L: 0x80, // Timer/Counter3 Input Capture Register Bytes + ICR3H: 0x80, // Timer/Counter3 Input Capture Register Bytes + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR2 __reg + TCNT2 __reg + OCR2 __reg + }{ + TCCR2: 0x45, // Timer/Counter Control Register + TCNT2: 0x44, // Timer/Counter Register + OCR2: 0x43, // Output Compare Register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x41, // Watchdog Timer Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + }{ + ADMUX: 0x27, // The ADC multiplexer Selection Register + ADCSRA: 0x26, // The ADC Control and Status register + ADCL: 0x24, // ADC Data Register Bytes + ADCH: 0x24, // ADC Data Register Bytes + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_M103C = 0x2 // ATmega103 Compatibility Mode + EXTENDED_WDTON = 0x1 // Watchdog Timer always on + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + HIGH_CKOPT = 0x10 // CKOPT fuse (operation dependent of CKSEL fuses) + + // LOW + LOW_BODLEVEL = 0x80 // Brownout detector trigger level + LOW_BODEN = 0x40 // Brown-out detection enabled + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0x40 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity + + // UCSR1A: USART Control and Status Register A + UCSR1A_RXC1 = 0x80 // USART Receive Complete + UCSR1A_TXC1 = 0x40 // USART Transmitt Complete + UCSR1A_UDRE1 = 0x20 // USART Data Register Empty + UCSR1A_FE1 = 0x10 // Framing Error + UCSR1A_DOR1 = 0x8 // Data overRun + UCSR1A_UPE1 = 0x4 // Parity Error + UCSR1A_U2X1 = 0x2 // Double the USART transmission speed + UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode + + // UCSR1B: USART Control and Status Register B + UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable + UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable + UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable + UCSR1B_RXEN1 = 0x10 // Receiver Enable + UCSR1B_TXEN1 = 0x8 // Transmitter Enable + UCSR1B_UCSZ12 = 0x4 // Character Size + UCSR1B_RXB81 = 0x2 // Receive Data Bit 8 + UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8 + + // UCSR1C: USART Control and Status Register C + UCSR1C_UMSEL1 = 0x40 // USART Mode Select + UCSR1C_UPM1 = 0x30 // Parity Mode Bits + UCSR1C_USBS1 = 0x8 // Stop Bit Select + UCSR1C_UCSZ1 = 0x6 // Character Size + UCSR1C_UCPOL1 = 0x1 // Clock Polarity +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // MCUCR: MCU Control Register + MCUCR_SRE = 0x80 // External SRAM Enable + MCUCR_SRW10 = 0x40 // External SRAM Wait State Select + MCUCR_SE = 0x20 // Sleep Enable + MCUCR_SM = 0x18 // Sleep Mode Select + MCUCR_SM2 = 0x4 // Sleep Mode Select + MCUCR_IVSEL = 0x2 // Interrupt Vector Select + MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable + + // XMCRA: External Memory Control Register A + XMCRA_SRL = 0x70 // Wait state page limit + XMCRA_SRW0 = 0xc // Wait state select bit lower page + XMCRA_SRW11 = 0x2 // Wait state select bit upper page + + // XMCRB: External Memory Control Register B + XMCRB_XMBK = 0x80 // External Memory Bus Keeper Enable + XMCRB_XMM = 0x7 // External Memory High Mask + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // RAMPZ: RAM Page Z Select Register + RAMPZ_RAMPZ0 = 0x1 // RAM Page Z Select Register Bit 0 +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for JTAG: JTAG Interface +const ( + // OCDR: On-Chip Debug Related Register in I/O Memory + OCDR_OCDR = 0xff // On-Chip Debug Register Bits +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EICRB: External Interrupt Control Register B + EICRB_ISC7 = 0xc0 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC6 = 0x30 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC5 = 0xc // External Interrupt 7-4 Sense Control Bit + EICRB_ISC4 = 0x3 // External Interrupt 7-4 Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xff // External Interrupt Request 7 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xff // External Interrupt Flags +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR0: Timer/Counter Control Register + TCCR0_FOC0 = 0x80 // Force Output Compare + TCCR0_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0_COM0 = 0x30 // Compare Match Output Modes + TCCR0_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0_CS0 = 0x7 // Clock Selects + + // ASSR: Asynchronus Status Register + ASSR_AS0 = 0x8 // Asynchronus Timer/Counter 0 + ASSR_TCN0UB = 0x4 // Timer/Counter0 Update Busy + ASSR_OCR0UB = 0x2 // Output Compare register 0 Busy + ASSR_TCR0UB = 0x1 // Timer/Counter Control Register 0 Update Busy +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_COM1C = 0xc // Compare Output Mode 1C, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode Bits + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Clock Select1 bits + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare for channel A + TCCR1C_FOC1B = 0x40 // Force Output Compare for channel B + TCCR1C_FOC1C = 0x20 // Force Output Compare for channel C + + // TCCR3A: Timer/Counter3 Control Register A + TCCR3A_COM3A = 0xc0 // Compare Output Mode 3A, bits + TCCR3A_COM3B = 0x30 // Compare Output Mode 3B, bits + TCCR3A_COM3C = 0xc // Compare Output Mode 3C, bits + TCCR3A_WGM3 = 0x3 // Waveform Generation Mode Bits + + // TCCR3B: Timer/Counter3 Control Register B + TCCR3B_ICNC3 = 0x80 // Input Capture 3 Noise Canceler + TCCR3B_ICES3 = 0x40 // Input Capture 3 Edge Select + TCCR3B_WGM3 = 0x18 // Waveform Generation Mode + TCCR3B_CS3 = 0x7 // Clock Select3 bits + + // TCCR3C: Timer/Counter3 Control Register C + TCCR3C_FOC3A = 0x80 // Force Output Compare for channel A + TCCR3C_FOC3B = 0x40 // Force Output Compare for channel B + TCCR3C_FOC3C = 0x20 // Force Output Compare for channel C +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR2: Timer/Counter Control Register + TCCR2_FOC2 = 0x80 // Force Output Compare + TCCR2_WGM20 = 0x40 // Wafeform Generation Mode + TCCR2_COM2 = 0x30 // Compare Match Output Mode + TCCR2_WGM21 = 0x8 // Waveform Generation Mode + TCCR2_CS2 = 0x7 // Clock Select +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADFR = 0x20 // ADC Free Running Select + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits +) diff --git a/src/device/avr/atmega128a.ld b/src/device/avr/atmega128a.ld new file mode 100644 index 00000000..d9ea1ca8 --- /dev/null +++ b/src/device/avr/atmega128a.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega128A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x20000; +__ram_size = 0x1000; +__num_isrs = 35; diff --git a/src/device/avr/atmega128rfa1.go b/src/device/avr/atmega128rfa1.go new file mode 100644 index 00000000..d11df473 --- /dev/null +++ b/src/device/avr/atmega128rfa1.go @@ -0,0 +1,1585 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega128RFA1.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega128rfa1 + +// Device information for the ATmega128RFA1. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega128RFA1" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_INT3 = 4 // External Interrupt Request 3 + IRQ_INT4 = 5 // External Interrupt Request 4 + IRQ_INT5 = 6 // External Interrupt Request 5 + IRQ_INT6 = 7 // External Interrupt Request 6 + IRQ_INT7 = 8 // External Interrupt Request 7 + IRQ_PCINT0 = 9 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 10 // Pin Change Interrupt Request 1 + IRQ_PCINT2 = 11 // Pin Change Interrupt Request 2 + IRQ_WDT = 12 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 13 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 14 // Timer/Counter2 Compare Match B + IRQ_TIMER2_OVF = 15 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 16 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 17 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 18 // Timer/Counter1 Compare Match B + IRQ_TIMER1_COMPC = 19 // Timer/Counter1 Compare Match C + IRQ_TIMER1_OVF = 20 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 21 // Timer/Counter0 Compare Match A + IRQ_TIMER0_COMPB = 22 // Timer/Counter0 Compare Match B + IRQ_TIMER0_OVF = 23 // Timer/Counter0 Overflow + IRQ_SPI_STC = 24 // SPI Serial Transfer Complete + IRQ_USART0_RX = 25 // USART0, Rx Complete + IRQ_USART0_UDRE = 26 // USART0 Data register Empty + IRQ_USART0_TX = 27 // USART0, Tx Complete + IRQ_ANALOG_COMP = 28 // Analog Comparator + IRQ_ADC = 29 // ADC Conversion Complete + IRQ_EE_READY = 30 // EEPROM Ready + IRQ_TIMER3_CAPT = 31 // Timer/Counter3 Capture Event + IRQ_TIMER3_COMPA = 32 // Timer/Counter3 Compare Match A + IRQ_TIMER3_COMPB = 33 // Timer/Counter3 Compare Match B + IRQ_TIMER3_COMPC = 34 // Timer/Counter3 Compare Match C + IRQ_TIMER3_OVF = 35 // Timer/Counter3 Overflow + IRQ_USART1_RX = 36 // USART1, Rx Complete + IRQ_USART1_UDRE = 37 // USART1 Data register Empty + IRQ_USART1_TX = 38 // USART1, Tx Complete + IRQ_TWI = 39 // 2-wire Serial Interface + IRQ_SPM_READY = 40 // Store Program Memory Read + IRQ_TIMER4_CAPT = 41 // Timer/Counter4 Capture Event + IRQ_TIMER4_COMPA = 42 // Timer/Counter4 Compare Match A + IRQ_TIMER4_COMPB = 43 // Timer/Counter4 Compare Match B + IRQ_TIMER4_COMPC = 44 // Timer/Counter4 Compare Match C + IRQ_TIMER4_OVF = 45 // Timer/Counter4 Overflow + IRQ_TIMER5_CAPT = 46 // Timer/Counter5 Capture Event + IRQ_TIMER5_COMPA = 47 // Timer/Counter5 Compare Match A + IRQ_TIMER5_COMPB = 48 // Timer/Counter5 Compare Match B + IRQ_TIMER5_COMPC = 49 // Timer/Counter5 Compare Match C + IRQ_TIMER5_OVF = 50 // Timer/Counter5 Overflow + IRQ_USART2_RX = 51 // USART2, Rx Complete + IRQ_USART2_UDRE = 52 // USART2 Data register Empty + IRQ_USART2_TX = 53 // USART2, Tx Complete + IRQ_USART3_RX = 54 // USART3, Rx Complete + IRQ_USART3_UDRE = 55 // USART3 Data register Empty + IRQ_USART3_TX = 56 // USART3, Tx Complete + IRQ_TRX24_PLL_LOCK = 57 // TRX24 - PLL lock interrupt + IRQ_TRX24_PLL_UNLOCK = 58 // TRX24 - PLL unlock interrupt + IRQ_TRX24_RX_START = 59 // TRX24 - Receive start interrupt + IRQ_TRX24_RX_END = 60 // TRX24 - RX_END interrupt + IRQ_TRX24_CCA_ED_DONE = 61 // TRX24 - CCA/ED done interrupt + IRQ_TRX24_XAH_AMI = 62 // TRX24 - XAH - AMI + IRQ_TRX24_TX_END = 63 // TRX24 - TX_END interrupt + IRQ_TRX24_AWAKE = 64 // TRX24 AWAKE - tranceiver is reaching state TRX_OFF + IRQ_SCNT_CMP1 = 65 // Symbol counter - compare match 1 interrupt + IRQ_SCNT_CMP2 = 66 // Symbol counter - compare match 2 interrupt + IRQ_SCNT_CMP3 = 67 // Symbol counter - compare match 3 interrupt + IRQ_SCNT_OVFL = 68 // Symbol counter - overflow interrupt + IRQ_SCNT_BACKOFF = 69 // Symbol counter - backoff interrupt + IRQ_AES_READY = 70 // AES engine ready interrupt + IRQ_BAT_LOW = 71 // Battery monitor indicates supply voltage below threshold + IRQ_max = 71 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // USART + USART = struct { + UDR0 __reg + UBRR0L __reg + UBRR0H __reg + UDR1 __reg + UBRR1L __reg + UBRR1H __reg + }{ + UDR0: 0xc6, // USART0 I/O Data Register + UBRR0L: 0xc4, // USART0 Baud Rate Register Bytes + UBRR0H: 0xc4, // USART0 Baud Rate Register Bytes + UDR1: 0xce, // USART1 I/O Data Register + UBRR1L: 0xcc, // USART1 Baud Rate Register Bytes + UBRR1H: 0xcc, // USART1 Baud Rate Register Bytes + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate Register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data Register + TWAR: 0xba, // TWI (Slave) Address Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins Address + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins Address + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins Address + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins Address + PORTE: 0x2e, // Port E Data Register + DDRE: 0x2d, // Port E Data Direction Register + PINE: 0x2c, // Port E Input Pins Address + PORTF: 0x31, // Port F Data Register + DDRF: 0x30, // Port F Data Direction Register + PINF: 0x2f, // Port F Input Pins Address + PORTG: 0x34, // Port G Data Register + DDRG: 0x33, // Port G Data Direction Register + PING: 0x32, // Port G Input Pins Address + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register B + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 Register + TCCR0B: 0x45, // Timer/Counter0 Control Register B + TCCR0A: 0x44, // Timer/Counter0 Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag Register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR5A __reg + TCCR5B __reg + TCCR5C __reg + TCNT5L __reg + TCNT5H __reg + OCR5AL __reg + OCR5AH __reg + OCR5BL __reg + OCR5BH __reg + OCR5CL __reg + OCR5CH __reg + ICR5L __reg + ICR5H __reg + TIMSK5 __reg + TIFR5 __reg + TCCR4A __reg + TCCR4B __reg + TCCR4C __reg + TCNT4L __reg + TCNT4H __reg + OCR4AL __reg + OCR4AH __reg + OCR4BL __reg + OCR4BH __reg + OCR4CL __reg + OCR4CH __reg + ICR4L __reg + ICR4H __reg + TIMSK4 __reg + TIFR4 __reg + TCCR3A __reg + TCCR3B __reg + TCCR3C __reg + TCNT3L __reg + TCNT3H __reg + OCR3AL __reg + OCR3AH __reg + OCR3BL __reg + OCR3BH __reg + OCR3CL __reg + OCR3CH __reg + ICR3L __reg + ICR3H __reg + TIMSK3 __reg + TIFR3 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + OCR1CL __reg + OCR1CH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR5A: 0x120, // Timer/Counter5 Control Register A + TCCR5B: 0x121, // Timer/Counter5 Control Register B + TCCR5C: 0x122, // Timer/Counter5 Control Register C + TCNT5L: 0x124, // Timer/Counter5 Bytes + TCNT5H: 0x124, // Timer/Counter5 Bytes + OCR5AL: 0x128, // Timer/Counter5 Output Compare Register A Bytes + OCR5AH: 0x128, // Timer/Counter5 Output Compare Register A Bytes + OCR5BL: 0x12a, // Timer/Counter5 Output Compare Register B Bytes + OCR5BH: 0x12a, // Timer/Counter5 Output Compare Register B Bytes + OCR5CL: 0x12c, // Timer/Counter5 Output Compare Register C Bytes + OCR5CH: 0x12c, // Timer/Counter5 Output Compare Register C Bytes + ICR5L: 0x126, // Timer/Counter5 Input Capture Register Bytes + ICR5H: 0x126, // Timer/Counter5 Input Capture Register Bytes + TIMSK5: 0x73, // Timer/Counter5 Interrupt Mask Register + TIFR5: 0x3a, // Timer/Counter5 Interrupt Flag Register + TCCR4A: 0xa0, // Timer/Counter4 Control Register A + TCCR4B: 0xa1, // Timer/Counter4 Control Register B + TCCR4C: 0xa2, // Timer/Counter4 Control Register C + TCNT4L: 0xa4, // Timer/Counter4 Bytes + TCNT4H: 0xa4, // Timer/Counter4 Bytes + OCR4AL: 0xa8, // Timer/Counter4 Output Compare Register A Bytes + OCR4AH: 0xa8, // Timer/Counter4 Output Compare Register A Bytes + OCR4BL: 0xaa, // Timer/Counter4 Output Compare Register B Bytes + OCR4BH: 0xaa, // Timer/Counter4 Output Compare Register B Bytes + OCR4CL: 0xac, // Timer/Counter4 Output Compare Register C Bytes + OCR4CH: 0xac, // Timer/Counter4 Output Compare Register C Bytes + ICR4L: 0xa6, // Timer/Counter4 Input Capture Register Bytes + ICR4H: 0xa6, // Timer/Counter4 Input Capture Register Bytes + TIMSK4: 0x72, // Timer/Counter4 Interrupt Mask Register + TIFR4: 0x39, // Timer/Counter4 Interrupt Flag Register + TCCR3A: 0x90, // Timer/Counter3 Control Register A + TCCR3B: 0x91, // Timer/Counter3 Control Register B + TCCR3C: 0x92, // Timer/Counter3 Control Register C + TCNT3L: 0x94, // Timer/Counter3 Bytes + TCNT3H: 0x94, // Timer/Counter3 Bytes + OCR3AL: 0x98, // Timer/Counter3 Output Compare Register A Bytes + OCR3AH: 0x98, // Timer/Counter3 Output Compare Register A Bytes + OCR3BL: 0x9a, // Timer/Counter3 Output Compare Register B Bytes + OCR3BH: 0x9a, // Timer/Counter3 Output Compare Register B Bytes + OCR3CL: 0x9c, // Timer/Counter3 Output Compare Register C Bytes + OCR3CH: 0x9c, // Timer/Counter3 Output Compare Register C Bytes + ICR3L: 0x96, // Timer/Counter3 Input Capture Register Bytes + ICR3H: 0x96, // Timer/Counter3 Input Capture Register Bytes + TIMSK3: 0x71, // Timer/Counter3 Interrupt Mask Register + TIFR3: 0x38, // Timer/Counter3 Interrupt Flag Register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1CL: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + OCR1CH: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag Register + } + + // Low-Power 2.4 GHz Transceiver + TRX24 = struct { + AES_CTRL __reg + AES_STATUS __reg + AES_STATE __reg + AES_KEY __reg + TRX_STATUS __reg + TRX_STATE __reg + TRX_CTRL_0 __reg + TRX_CTRL_1 __reg + PHY_TX_PWR __reg + PHY_RSSI __reg + PHY_ED_LEVEL __reg + PHY_CC_CCA __reg + CCA_THRES __reg + RX_CTRL __reg + SFD_VALUE __reg + TRX_CTRL_2 __reg + ANT_DIV __reg + IRQ_MASK __reg + IRQ_STATUS __reg + VREG_CTRL __reg + BATMON __reg + XOSC_CTRL __reg + RX_SYN __reg + XAH_CTRL_1 __reg + FTN_CTRL __reg + PLL_CF __reg + PLL_DCU __reg + PART_NUM __reg + VERSION_NUM __reg + MAN_ID_0 __reg + MAN_ID_1 __reg + SHORT_ADDR_0 __reg + SHORT_ADDR_1 __reg + PAN_ID_0 __reg + PAN_ID_1 __reg + IEEE_ADDR_0 __reg + IEEE_ADDR_1 __reg + IEEE_ADDR_2 __reg + IEEE_ADDR_3 __reg + IEEE_ADDR_4 __reg + IEEE_ADDR_5 __reg + IEEE_ADDR_6 __reg + IEEE_ADDR_7 __reg + XAH_CTRL_0 __reg + CSMA_SEED_0 __reg + CSMA_SEED_1 __reg + CSMA_BE __reg + TST_CTRL_DIGI __reg + TST_RX_LENGTH __reg + TRXFBST __reg + TRXFBEND __reg + }{ + AES_CTRL: 0x13c, // AES Control Register + AES_STATUS: 0x13d, // AES Status Register + AES_STATE: 0x13e, // AES Plain and Cipher Text Buffer Register + AES_KEY: 0x13f, // AES Encryption and Decryption Key Buffer Register + TRX_STATUS: 0x141, // Transceiver Status Register + TRX_STATE: 0x142, // Transceiver State Control Register + TRX_CTRL_0: 0x143, // Reserved + TRX_CTRL_1: 0x144, // Transceiver Control Register 1 + PHY_TX_PWR: 0x145, // Transceiver Transmit Power Control Register + PHY_RSSI: 0x146, // Receiver Signal Strength Indicator Register + PHY_ED_LEVEL: 0x147, // Transceiver Energy Detection Level Register + PHY_CC_CCA: 0x148, // Transceiver Clear Channel Assessment (CCA) Control Register + CCA_THRES: 0x149, // Transceiver CCA Threshold Setting Register + RX_CTRL: 0x14a, // Transceiver Receive Control Register + SFD_VALUE: 0x14b, // Start of Frame Delimiter Value Register + TRX_CTRL_2: 0x14c, // Transceiver Control Register 2 + ANT_DIV: 0x14d, // Antenna Diversity Control Register + IRQ_MASK: 0x14e, // Transceiver Interrupt Enable Register + IRQ_STATUS: 0x14f, // Transceiver Interrupt Status Register + VREG_CTRL: 0x150, // Voltage Regulator Control and Status Register + BATMON: 0x151, // Battery Monitor Control and Status Register + XOSC_CTRL: 0x152, // Crystal Oscillator Control Register + RX_SYN: 0x155, // Transceiver Receiver Sensitivity Control Register + XAH_CTRL_1: 0x157, // Transceiver Acknowledgment Frame Control Register 1 + FTN_CTRL: 0x158, // Transceiver Filter Tuning Control Register + PLL_CF: 0x15a, // Transceiver Center Frequency Calibration Control Register + PLL_DCU: 0x15b, // Transceiver Delay Cell Calibration Control Register + PART_NUM: 0x15c, // Device Identification Register (Part Number) + VERSION_NUM: 0x15d, // Device Identification Register (Version Number) + MAN_ID_0: 0x15e, // Device Identification Register (Manufacture ID Low Byte) + MAN_ID_1: 0x15f, // Device Identification Register (Manufacture ID High Byte) + SHORT_ADDR_0: 0x160, // Transceiver MAC Short Address Register (Low Byte) + SHORT_ADDR_1: 0x161, // Transceiver MAC Short Address Register (High Byte) + PAN_ID_0: 0x162, // Transceiver Personal Area Network ID Register (Low Byte) + PAN_ID_1: 0x163, // Transceiver Personal Area Network ID Register (High Byte) + IEEE_ADDR_0: 0x164, // Transceiver MAC IEEE Address Register 0 + IEEE_ADDR_1: 0x165, // Transceiver MAC IEEE Address Register 1 + IEEE_ADDR_2: 0x166, // Transceiver MAC IEEE Address Register 2 + IEEE_ADDR_3: 0x167, // Transceiver MAC IEEE Address Register 3 + IEEE_ADDR_4: 0x168, // Transceiver MAC IEEE Address Register 4 + IEEE_ADDR_5: 0x169, // Transceiver MAC IEEE Address Register 5 + IEEE_ADDR_6: 0x16a, // Transceiver MAC IEEE Address Register 6 + IEEE_ADDR_7: 0x16b, // Transceiver MAC IEEE Address Register 7 + XAH_CTRL_0: 0x16c, // Transceiver Extended Operating Mode Control Register + CSMA_SEED_0: 0x16d, // Transceiver CSMA-CA Random Number Generator Seed Register + CSMA_SEED_1: 0x16e, // Transceiver Acknowledgment Frame Control Register 2 + CSMA_BE: 0x16f, // Transceiver CSMA-CA Back-off Exponent Control Register + TST_CTRL_DIGI: 0x176, // Transceiver Digital Test Control Register + TST_RX_LENGTH: 0x17b, // Transceiver Received Frame Length Register + TRXFBST: 0x180, // Start of frame buffer + TRXFBEND: 0x1ff, // End of frame buffer + } + + // MAC Symbol Counter + SYMCNT = struct { + SCOCR1HH __reg + SCOCR1HL __reg + SCOCR1LH __reg + SCOCR1LL __reg + SCOCR2HH __reg + SCOCR2HL __reg + SCOCR2LH __reg + SCOCR2LL __reg + SCOCR3HH __reg + SCOCR3HL __reg + SCOCR3LH __reg + SCOCR3LL __reg + SCTSRHH __reg + SCTSRHL __reg + SCTSRLH __reg + SCTSRLL __reg + SCBTSRHH __reg + SCBTSRHL __reg + SCBTSRLH __reg + SCBTSRLL __reg + SCCNTHH __reg + SCCNTHL __reg + SCCNTLH __reg + SCCNTLL __reg + SCIRQS __reg + SCIRQM __reg + SCSR __reg + SCCR1 __reg + SCCR0 __reg + }{ + SCOCR1HH: 0xf8, // Symbol Counter Output Compare Register 1 HH-Byte + SCOCR1HL: 0xf7, // Symbol Counter Output Compare Register 1 HL-Byte + SCOCR1LH: 0xf6, // Symbol Counter Output Compare Register 1 LH-Byte + SCOCR1LL: 0xf5, // Symbol Counter Output Compare Register 1 LL-Byte + SCOCR2HH: 0xf4, // Symbol Counter Output Compare Register 2 HH-Byte + SCOCR2HL: 0xf3, // Symbol Counter Output Compare Register 2 HL-Byte + SCOCR2LH: 0xf2, // Symbol Counter Output Compare Register 2 LH-Byte + SCOCR2LL: 0xf1, // Symbol Counter Output Compare Register 2 LL-Byte + SCOCR3HH: 0xf0, // Symbol Counter Output Compare Register 3 HH-Byte + SCOCR3HL: 0xef, // Symbol Counter Output Compare Register 3 HL-Byte + SCOCR3LH: 0xee, // Symbol Counter Output Compare Register 3 LH-Byte + SCOCR3LL: 0xed, // Symbol Counter Output Compare Register 3 LL-Byte + SCTSRHH: 0xec, // Symbol Counter Frame Timestamp Register HH-Byte + SCTSRHL: 0xeb, // Symbol Counter Frame Timestamp Register HL-Byte + SCTSRLH: 0xea, // Symbol Counter Frame Timestamp Register LH-Byte + SCTSRLL: 0xe9, // Symbol Counter Frame Timestamp Register LL-Byte + SCBTSRHH: 0xe8, // Symbol Counter Beacon Timestamp Register HH-Byte + SCBTSRHL: 0xe7, // Symbol Counter Beacon Timestamp Register HL-Byte + SCBTSRLH: 0xe6, // Symbol Counter Beacon Timestamp Register LH-Byte + SCBTSRLL: 0xe5, // Symbol Counter Beacon Timestamp Register LL-Byte + SCCNTHH: 0xe4, // Symbol Counter Register HH-Byte + SCCNTHL: 0xe3, // Symbol Counter Register HL-Byte + SCCNTLH: 0xe2, // Symbol Counter Register LH-Byte + SCCNTLL: 0xe1, // Symbol Counter Register LL-Byte + SCIRQS: 0xe0, // Symbol Counter Interrupt Status Register + SCIRQM: 0xdf, // Symbol Counter Interrupt Mask Register + SCSR: 0xde, // Symbol Counter Status Register + SCCR1: 0xdd, // Symbol Counter Control Register 1 + SCCR0: 0xdc, // Symbol Counter Control Register 0 + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Bytes + EEARH: 0x41, // EEPROM Address Register Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EICRB __reg + EIMSK __reg + EIFR __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + PCICR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EICRB: 0x6a, // External Interrupt Control Register B + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + ADCSRC __reg + DIDR2 __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC Multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // The ADC Control and Status Register A + ADCSRC: 0x77, // The ADC Control and Status Register C + DIDR2: 0x7d, // Digital Input Disable Register 2 + DIDR0: 0x7e, // Digital Input Disable Register 0 + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + RAMPZ __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PRR2 __reg + PRR1 __reg + PRR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + SMCR: 0x53, // Sleep Mode Control Register + RAMPZ: 0x5b, // Extended Z-pointer Register for ELPM/SPM + GPIOR2: 0x4b, // General Purpose I/O Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PRR2: 0x63, // Power Reduction Register 2 + PRR1: 0x65, // Power Reduction Register 1 + PRR0: 0x64, // Power Reduction Register0 + } + + // FLASH Controller + FLASH = struct { + NEMCR __reg + BGCR __reg + }{ + NEMCR: 0x75, // Flash Extended-Mode Control-Register + BGCR: 0x67, // Reference Voltage Calibration Register + } + + // Power Controller + PWRCTRL = struct { + TRXPR __reg + DRTRAM0 __reg + DRTRAM1 __reg + DRTRAM2 __reg + DRTRAM3 __reg + LLDRL __reg + LLDRH __reg + LLCR __reg + DPDS0 __reg + DPDS1 __reg + }{ + TRXPR: 0x139, // Transceiver Pin Register + DRTRAM0: 0x135, // Data Retention Configuration Register of SRAM 0 + DRTRAM1: 0x134, // Data Retention Configuration Register of SRAM 1 + DRTRAM2: 0x133, // Data Retention Configuration Register of SRAM 2 + DRTRAM3: 0x132, // Data Retention Configuration Register of SRAM 3 + LLDRL: 0x130, // Low Leakage Voltage Regulator Data Register (Low-Byte) + LLDRH: 0x131, // Low Leakage Voltage Regulator Data Register (High-Byte) + LLCR: 0x12f, // Low Leakage Voltage Regulator Control Register + DPDS0: 0x136, // Port Driver Strength Register 0 + DPDS1: 0x137, // Port Driver Strength Register 1 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_CKSEL_SUT = 0x3f // Select Clock Source : Start-up time +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe // TWI Address Mask + TWAMR_Res = 0x1 // Reserved Bit + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI START Condition Bit + TWCR_TWSTO = 0x10 // TWI STOP Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collision Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_Res = 0x2 // Reserved Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_Res = 0x4 // Reserved Bit + TWSR_TWPS = 0x3 // TWI Prescaler Bits + + // TWAR: TWI (Slave) Address Register + TWAR_TWA = 0xfe // TWI (Slave) Address + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Select 1 and 0 + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_Res = 0x3e // Reserved + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter0 Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_Res = 0x30 // Reserved Bit + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter0 Control Register A + TCCR0A_COM0A = 0xc0 // Compare Match Output A Mode + TCCR0A_COM0B = 0x30 // Compare Match Output B Mode + TCCR0A_Res = 0xc // Reserved Bit + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_Res = 0xf8 // Reserved + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag Register + TIFR0_Res = 0xf8 // Reserved + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare B Match Flag + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare A Match Flag + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_Res = 0xf8 // Reserved Bit + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_Res = 0xf8 // Reserved Bit + TIFR2_OCF2B = 0x4 // Output Compare Flag 2 B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2 A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Match Output A Mode + TCCR2A_COM2B = 0x30 // Compare Match Output B Mode + TCCR2A_Res = 0xc // Reserved + TCCR2A_WGM2 = 0x3 // Waveform Generation Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_Res = 0x30 // Reserved + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select + + // ASSR: Asynchronous Status Register + ASSR_EXCLKAMR = 0x80 // Enable External Clock Input for AMR + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Timer/Counter2 Asynchronous Mode + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Timer/Counter2 Output Compare Register A Update Busy + ASSR_OCR2BUB = 0x4 // Timer/Counter2 Output Compare Register B Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter2 Control Register A Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter2 Control Register B Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR5A: Timer/Counter5 Control Register A + TCCR5A_COM5A = 0xc0 // Compare Output Mode for Channel A + TCCR5A_COM5B = 0x30 // Compare Output Mode for Channel B + TCCR5A_COM5C = 0xc // Compare Output Mode for Channel C + TCCR5A_WGM5 = 0x3 // Waveform Generation Mode + + // TCCR5B: Timer/Counter5 Control Register B + TCCR5B_ICNC5 = 0x80 // Input Capture 5 Noise Canceller + TCCR5B_ICES5 = 0x40 // Input Capture 5 Edge Select + TCCR5B_Res = 0x20 // Reserved Bit + TCCR5B_WGM5 = 0x18 // Waveform Generation Mode + TCCR5B_CS5 = 0x7 // Clock Select + + // TCCR5C: Timer/Counter5 Control Register C + TCCR5C_FOC5A = 0x80 // Force Output Compare for Channel A + TCCR5C_FOC5B = 0x40 // Force Output Compare for Channel B + TCCR5C_FOC5C = 0x20 // Force Output Compare for Channel C + TCCR5C_Res = 0x1f // Reserved + + // TIMSK5: Timer/Counter5 Interrupt Mask Register + TIMSK5_ICIE5 = 0x20 // Timer/Counter5 Input Capture Interrupt Enable + TIMSK5_OCIE5C = 0x8 // Timer/Counter5 Output Compare C Match Interrupt Enable + TIMSK5_OCIE5B = 0x4 // Timer/Counter5 Output Compare B Match Interrupt Enable + TIMSK5_OCIE5A = 0x2 // Timer/Counter5 Output Compare A Match Interrupt Enable + TIMSK5_TOIE5 = 0x1 // Timer/Counter5 Overflow Interrupt Enable + + // TIFR5: Timer/Counter5 Interrupt Flag Register + TIFR5_ICF5 = 0x20 // Timer/Counter5 Input Capture Flag + TIFR5_OCF5C = 0x8 // Timer/Counter5 Output Compare C Match Flag + TIFR5_OCF5B = 0x4 // Timer/Counter5 Output Compare B Match Flag + TIFR5_OCF5A = 0x2 // Timer/Counter5 Output Compare A Match Flag + TIFR5_TOV5 = 0x1 // Timer/Counter5 Overflow Flag + + // TCCR4A: Timer/Counter4 Control Register A + TCCR4A_COM4A = 0xc0 // Compare Output Mode for Channel A + TCCR4A_COM4B = 0x30 // Compare Output Mode for Channel B + TCCR4A_COM4C = 0xc // Compare Output Mode for Channel C + TCCR4A_WGM4 = 0x3 // Waveform Generation Mode + + // TCCR4B: Timer/Counter4 Control Register B + TCCR4B_ICNC4 = 0x80 // Input Capture 4 Noise Canceller + TCCR4B_ICES4 = 0x40 // Input Capture 4 Edge Select + TCCR4B_Res = 0x20 // Reserved Bit + TCCR4B_WGM4 = 0x18 // Waveform Generation Mode + TCCR4B_CS4 = 0x7 // Clock Select + + // TCCR4C: Timer/Counter4 Control Register C + TCCR4C_FOC4A = 0x80 // Force Output Compare for Channel A + TCCR4C_FOC4B = 0x40 // Force Output Compare for Channel B + TCCR4C_FOC4C = 0x20 // Force Output Compare for Channel C + TCCR4C_Res = 0x1f // Reserved + + // TIMSK4: Timer/Counter4 Interrupt Mask Register + TIMSK4_ICIE4 = 0x20 // Timer/Counter4 Input Capture Interrupt Enable + TIMSK4_OCIE4C = 0x8 // Timer/Counter4 Output Compare C Match Interrupt Enable + TIMSK4_OCIE4B = 0x4 // Timer/Counter4 Output Compare B Match Interrupt Enable + TIMSK4_OCIE4A = 0x2 // Timer/Counter4 Output Compare A Match Interrupt Enable + TIMSK4_TOIE4 = 0x1 // Timer/Counter4 Overflow Interrupt Enable + + // TIFR4: Timer/Counter4 Interrupt Flag Register + TIFR4_ICF4 = 0x20 // Timer/Counter4 Input Capture Flag + TIFR4_OCF4C = 0x8 // Timer/Counter4 Output Compare C Match Flag + TIFR4_OCF4B = 0x4 // Timer/Counter4 Output Compare B Match Flag + TIFR4_OCF4A = 0x2 // Timer/Counter4 Output Compare A Match Flag + TIFR4_TOV4 = 0x1 // Timer/Counter4 Overflow Flag + + // TCCR3A: Timer/Counter3 Control Register A + TCCR3A_COM3A = 0xc0 // Compare Output Mode for Channel A + TCCR3A_COM3B = 0x30 // Compare Output Mode for Channel B + TCCR3A_COM3C = 0xc // Compare Output Mode for Channel C + TCCR3A_WGM3 = 0x3 // Waveform Generation Mode + + // TCCR3B: Timer/Counter3 Control Register B + TCCR3B_ICNC3 = 0x80 // Input Capture 3 Noise Canceller + TCCR3B_ICES3 = 0x40 // Input Capture 3 Edge Select + TCCR3B_Res = 0x20 // Reserved Bit + TCCR3B_WGM3 = 0x18 // Waveform Generation Mode + TCCR3B_CS3 = 0x7 // Clock Select + + // TCCR3C: Timer/Counter3 Control Register C + TCCR3C_FOC3A = 0x80 // Force Output Compare for Channel A + TCCR3C_FOC3B = 0x40 // Force Output Compare for Channel B + TCCR3C_FOC3C = 0x20 // Force Output Compare for Channel C + TCCR3C_Res = 0x1f // Reserved + + // TIMSK3: Timer/Counter3 Interrupt Mask Register + TIMSK3_ICIE3 = 0x20 // Timer/Counter3 Input Capture Interrupt Enable + TIMSK3_OCIE3C = 0x8 // Timer/Counter3 Output Compare C Match Interrupt Enable + TIMSK3_OCIE3B = 0x4 // Timer/Counter3 Output Compare B Match Interrupt Enable + TIMSK3_OCIE3A = 0x2 // Timer/Counter3 Output Compare A Match Interrupt Enable + TIMSK3_TOIE3 = 0x1 // Timer/Counter3 Overflow Interrupt Enable + + // TIFR3: Timer/Counter3 Interrupt Flag Register + TIFR3_ICF3 = 0x20 // Timer/Counter3 Input Capture Flag + TIFR3_OCF3C = 0x8 // Timer/Counter3 Output Compare C Match Flag + TIFR3_OCF3B = 0x4 // Timer/Counter3 Output Compare B Match Flag + TIFR3_OCF3A = 0x2 // Timer/Counter3 Output Compare A Match Flag + TIFR3_TOV3 = 0x1 // Timer/Counter3 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode for Channel A + TCCR1A_COM1B = 0x30 // Compare Output Mode for Channel B + TCCR1A_COM1C = 0xc // Compare Output Mode for Channel C + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceller + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_Res = 0x20 // Reserved Bit + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Clock Select + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare for Channel A + TCCR1C_FOC1B = 0x40 // Force Output Compare for Channel B + TCCR1C_FOC1C = 0x20 // Force Output Compare for Channel C + TCCR1C_Res = 0x1f // Reserved + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1C = 0x8 // Timer/Counter1 Output Compare C Match Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag Register + TIFR1_ICF1 = 0x20 // Timer/Counter1 Input Capture Flag + TIFR1_OCF1C = 0x8 // Timer/Counter1 Output Compare C Match Flag + TIFR1_OCF1B = 0x4 // Timer/Counter1 Output Compare B Match Flag + TIFR1_OCF1A = 0x2 // Timer/Counter1 Output Compare A Match Flag + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for TRX24: Low-Power 2.4 GHz Transceiver +const ( + // AES_CTRL: AES Control Register + AES_CTRL_AES_REQUEST = 0x80 // Request AES Operation. + AES_CTRL_AES_MODE = 0x20 // Set AES Operation Mode + AES_CTRL_AES_DIR = 0x8 // Set AES Operation Direction + AES_CTRL_AES_IM = 0x4 // AES Interrupt Enable + + // AES_STATUS: AES Status Register + AES_STATUS_AES_ER = 0x80 // AES Operation Finished with Error + AES_STATUS_Res = 0x7e // Reserved + AES_STATUS_AES_DONE = 0x1 // AES Operation Finished with Success + + // AES_STATE: AES Plain and Cipher Text Buffer Register + AES_STATE_AES_STATE = 0xff // AES Plain and Cipher Text Buffer + + // AES_KEY: AES Encryption and Decryption Key Buffer Register + AES_KEY_AES_KEY = 0xff // AES Encryption/Decryption Key Buffer + + // TRX_STATUS: Transceiver Status Register + TRX_STATUS_CCA_DONE = 0x80 // CCA Algorithm Status + TRX_STATUS_CCA_STATUS = 0x40 // CCA Status Result + TRX_STATUS_TST_STATUS = 0x20 // Test mode status + TRX_STATUS_TRX_STATUS = 0x1f // Transceiver Main Status + + // TRX_STATE: Transceiver State Control Register + TRX_STATE_TRAC_STATUS = 0xe0 // Transaction Status + TRX_STATE_TRX_CMD = 0x1f // State Control Command + + // TRX_CTRL_0: Reserved + TRX_CTRL_0_Res = 0xff // Reserved + + // TRX_CTRL_1: Transceiver Control Register 1 + TRX_CTRL_1_PA_EXT_EN = 0x80 // External PA support enable + TRX_CTRL_1_IRQ_2_EXT_EN = 0x40 // Connect Frame Start IRQ to TC1 + TRX_CTRL_1_TX_AUTO_CRC_ON = 0x20 // Enable Automatic CRC Calculation + TRX_CTRL_1_Res = 0x1f // Reserved + + // PHY_TX_PWR: Transceiver Transmit Power Control Register + PHY_TX_PWR_PA_BUF_LT = 0xc0 // Power Amplifier Buffer Lead Time + PHY_TX_PWR_PA_LT = 0x30 // Power Amplifier Lead Time + PHY_TX_PWR_TX_PWR = 0xf // Transmit Power Setting + + // PHY_RSSI: Receiver Signal Strength Indicator Register + PHY_RSSI_RX_CRC_VALID = 0x80 // Received Frame CRC Status + PHY_RSSI_RND_VALUE = 0x60 // Random Value + PHY_RSSI_RSSI = 0x1f // Receiver Signal Strength Indicator + + // PHY_ED_LEVEL: Transceiver Energy Detection Level Register + PHY_ED_LEVEL_ED_LEVEL = 0xff // Energy Detection Level + + // PHY_CC_CCA: Transceiver Clear Channel Assessment (CCA) Control Register + PHY_CC_CCA_CCA_REQUEST = 0x80 // Manual CCA Measurement Request + PHY_CC_CCA_CCA_MODE = 0x60 // Select CCA Measurement Mode + PHY_CC_CCA_CHANNEL = 0x1f // RX/TX Channel Selection + + // CCA_THRES: Transceiver CCA Threshold Setting Register + CCA_THRES_CCA_CS_THRES = 0xf0 // CS Threshold Level for CCA Measurement + CCA_THRES_CCA_ED_THRES = 0xf // ED Threshold Level for CCA Measurement + + // RX_CTRL: Transceiver Receive Control Register + RX_CTRL_PDT_THRES = 0xf // Receiver Sensitivity Control + + // SFD_VALUE: Start of Frame Delimiter Value Register + SFD_VALUE_SFD_VALUE = 0xff // Start of Frame Delimiter Value + + // TRX_CTRL_2: Transceiver Control Register 2 + TRX_CTRL_2_RX_SAFE_MODE = 0x80 // RX Safe Mode + TRX_CTRL_2_Res = 0x7c // Reserved + TRX_CTRL_2_OQPSK_DATA_RATE = 0x3 // Data Rate Selection + + // ANT_DIV: Antenna Diversity Control Register + ANT_DIV_ANT_SEL = 0x80 // Antenna Diversity Antenna Status + ANT_DIV_Res = 0x70 // Reserved + ANT_DIV_ANT_DIV_EN = 0x8 // Enable Antenna Diversity + ANT_DIV_ANT_EXT_SW_EN = 0x4 // Enable External Antenna Switch Control + ANT_DIV_ANT_CTRL = 0x3 // Static Antenna Diversity Switch Control + + // IRQ_MASK: Transceiver Interrupt Enable Register + IRQ_MASK_AWAKE_EN = 0x80 // Awake Interrupt Enable + IRQ_MASK_TX_END_EN = 0x40 // TX_END Interrupt Enable + IRQ_MASK_AMI_EN = 0x20 // Address Match Interrupt Enable + IRQ_MASK_CCA_ED_DONE_EN = 0x10 // End of ED Measurement Interrupt Enable + IRQ_MASK_RX_END_EN = 0x8 // RX_END Interrupt Enable + IRQ_MASK_RX_START_EN = 0x4 // RX_START Interrupt Enable + IRQ_MASK_PLL_UNLOCK_EN = 0x2 // PLL Unlock Interrupt Enable + IRQ_MASK_PLL_LOCK_EN = 0x1 // PLL Lock Interrupt Enable + + // IRQ_STATUS: Transceiver Interrupt Status Register + IRQ_STATUS_AWAKE = 0x80 // Awake Interrupt Status + IRQ_STATUS_TX_END = 0x40 // TX_END Interrupt Status + IRQ_STATUS_AMI = 0x20 // Address Match Interrupt Status + IRQ_STATUS_CCA_ED_DONE = 0x10 // End of ED Measurement Interrupt Status + IRQ_STATUS_RX_END = 0x8 // RX_END Interrupt Status + IRQ_STATUS_RX_START = 0x4 // RX_START Interrupt Status + IRQ_STATUS_PLL_UNLOCK = 0x2 // PLL Unlock Interrupt Status + IRQ_STATUS_PLL_LOCK = 0x1 // PLL Lock Interrupt Status + + // VREG_CTRL: Voltage Regulator Control and Status Register + VREG_CTRL_AVREG_EXT = 0x80 // Use External AVDD Regulator + VREG_CTRL_AVDD_OK = 0x40 // AVDD Supply Voltage Valid + VREG_CTRL_DVREG_EXT = 0x8 // Use External DVDD Regulator + VREG_CTRL_DVDD_OK = 0x4 // DVDD Supply Voltage Valid + + // BATMON: Battery Monitor Control and Status Register + BATMON_BAT_LOW = 0x80 // Battery Monitor Interrupt Status + BATMON_BAT_LOW_EN = 0x40 // Battery Monitor Interrupt Enable + BATMON_BATMON_OK = 0x20 // Battery Monitor Status + BATMON_BATMON_HR = 0x10 // Battery Monitor Voltage Range + BATMON_BATMON_VTH = 0xf // Battery Monitor Threshold Voltage + + // XOSC_CTRL: Crystal Oscillator Control Register + XOSC_CTRL_XTAL_MODE = 0xf0 // Crystal Oscillator Operating Mode + XOSC_CTRL_XTAL_TRIM = 0xf // Crystal Oscillator Load Capacitance Trimming + + // RX_SYN: Transceiver Receiver Sensitivity Control Register + RX_SYN_RX_PDT_DIS = 0x80 // Prevent Frame Reception + RX_SYN_Res = 0x70 // Reserved + RX_SYN_RX_PDT_LEVEL = 0xf // Reduce Receiver Sensitivity + + // XAH_CTRL_1: Transceiver Acknowledgment Frame Control Register 1 + XAH_CTRL_1_AACK_FLTR_RES_FT = 0x20 // Filter Reserved Frames + XAH_CTRL_1_AACK_UPLD_RES_FT = 0x10 // Process Reserved Frames + XAH_CTRL_1_AACK_ACK_TIME = 0x4 // Reduce Acknowledgment Time + XAH_CTRL_1_AACK_PROM_MODE = 0x2 // Enable Promiscuous Mode + + // FTN_CTRL: Transceiver Filter Tuning Control Register + FTN_CTRL_FTN_START = 0x80 // Start Calibration Loop of Filter Tuning Network + + // PLL_CF: Transceiver Center Frequency Calibration Control Register + PLL_CF_PLL_CF_START = 0x80 // Start Center Frequency Calibration + + // PLL_DCU: Transceiver Delay Cell Calibration Control Register + PLL_DCU_PLL_DCU_START = 0x80 // Start Delay Cell Calibration + + // PART_NUM: Device Identification Register (Part Number) + PART_NUM_PART_NUM = 0xff // Part Number + + // VERSION_NUM: Device Identification Register (Version Number) + VERSION_NUM_VERSION_NUM = 0xff // Version Number + + // MAN_ID_0: Device Identification Register (Manufacture ID Low Byte) + MAN_ID_0_MAN_ID_07 = 0x80 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_06 = 0x40 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_05 = 0x20 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_04 = 0x10 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_03 = 0x8 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_02 = 0x4 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_01 = 0x2 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_00 = 0x1 // Manufacturer ID (Low Byte) + + // MAN_ID_1: Device Identification Register (Manufacture ID High Byte) + MAN_ID_1_MAN_ID_ = 0xff // Manufacturer ID (High Byte) + + // SHORT_ADDR_0: Transceiver MAC Short Address Register (Low Byte) + SHORT_ADDR_0_SHORT_ADDR_07 = 0x80 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_06 = 0x40 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_05 = 0x20 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_04 = 0x10 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_03 = 0x8 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_02 = 0x4 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_01 = 0x2 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_00 = 0x1 // MAC Short Address + + // SHORT_ADDR_1: Transceiver MAC Short Address Register (High Byte) + SHORT_ADDR_1_SHORT_ADDR_ = 0xff // MAC Short Address + + // PAN_ID_0: Transceiver Personal Area Network ID Register (Low Byte) + PAN_ID_0_PAN_ID_07 = 0x80 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_06 = 0x40 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_05 = 0x20 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_04 = 0x10 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_03 = 0x8 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_02 = 0x4 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_01 = 0x2 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_00 = 0x1 // MAC Personal Area Network ID + + // PAN_ID_1: Transceiver Personal Area Network ID Register (High Byte) + PAN_ID_1_PAN_ID_ = 0xff // MAC Personal Area Network ID + + // IEEE_ADDR_0: Transceiver MAC IEEE Address Register 0 + IEEE_ADDR_0_IEEE_ADDR_07 = 0x80 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_06 = 0x40 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_05 = 0x20 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_04 = 0x10 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_03 = 0x8 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_02 = 0x4 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_01 = 0x2 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_00 = 0x1 // MAC IEEE Address + + // IEEE_ADDR_1: Transceiver MAC IEEE Address Register 1 + IEEE_ADDR_1_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // IEEE_ADDR_2: Transceiver MAC IEEE Address Register 2 + IEEE_ADDR_2_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // IEEE_ADDR_3: Transceiver MAC IEEE Address Register 3 + IEEE_ADDR_3_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // IEEE_ADDR_4: Transceiver MAC IEEE Address Register 4 + IEEE_ADDR_4_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // IEEE_ADDR_5: Transceiver MAC IEEE Address Register 5 + IEEE_ADDR_5_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // IEEE_ADDR_6: Transceiver MAC IEEE Address Register 6 + IEEE_ADDR_6_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // IEEE_ADDR_7: Transceiver MAC IEEE Address Register 7 + IEEE_ADDR_7_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // XAH_CTRL_0: Transceiver Extended Operating Mode Control Register + XAH_CTRL_0_MAX_FRAME_RETRIES = 0xf0 // Maximum Number of Frame Re-transmission Attempts + XAH_CTRL_0_MAX_CSMA_RETRIES = 0xe // Maximum Number of CSMA-CA Procedure Repetition Attempts + XAH_CTRL_0_SLOTTED_OPERATION = 0x1 // Set Slotted Acknowledgment + + // CSMA_SEED_0: Transceiver CSMA-CA Random Number Generator Seed Register + CSMA_SEED_0_CSMA_SEED_07 = 0x80 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_06 = 0x40 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_05 = 0x20 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_04 = 0x10 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_03 = 0x8 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_02 = 0x4 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_01 = 0x2 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_00 = 0x1 // Seed Value for CSMA Random Number Generator + + // CSMA_SEED_1: Transceiver Acknowledgment Frame Control Register 2 + CSMA_SEED_1_AACK_FVN_MODE = 0xc0 // Acknowledgment Frame Filter Mode + CSMA_SEED_1_AACK_SET_PD = 0x20 // Set Frame Pending Sub-field + CSMA_SEED_1_AACK_DIS_ACK = 0x10 // Disable Acknowledgment Frame Transmission + CSMA_SEED_1_AACK_I_AM_COORD = 0x8 // Set Personal Area Network Coordinator + CSMA_SEED_1_CSMA_SEED_1 = 0x7 // Seed Value for CSMA Random Number Generator + + // CSMA_BE: Transceiver CSMA-CA Back-off Exponent Control Register + CSMA_BE_MAX_BE = 0xf0 // Maximum Back-off Exponent + CSMA_BE_MIN_BE = 0xf // Minimum Back-off Exponent + + // TST_CTRL_DIGI: Transceiver Digital Test Control Register + TST_CTRL_DIGI_TST_CTRL_DIG = 0xf // Digital Test Controller Register + + // TST_RX_LENGTH: Transceiver Received Frame Length Register + TST_RX_LENGTH_RX_LENGTH = 0xff // Received Frame Length +) + +// Bitfields for SYMCNT: MAC Symbol Counter +const ( + // SCOCR1HH: Symbol Counter Output Compare Register 1 HH-Byte + SCOCR1HH_SCOCR1HH = 0xff // Symbol Counter Output Compare Register 1 HH-Byte + + // SCOCR1HL: Symbol Counter Output Compare Register 1 HL-Byte + SCOCR1HL_SCOCR1HL = 0xff // Symbol Counter Output Compare Register 1 HL-Byte + + // SCOCR1LH: Symbol Counter Output Compare Register 1 LH-Byte + SCOCR1LH_SCOCR1LH = 0xff // Symbol Counter Output Compare Register 1 LH-Byte + + // SCOCR1LL: Symbol Counter Output Compare Register 1 LL-Byte + SCOCR1LL_SCOCR1LL = 0xff // Symbol Counter Output Compare Register 1 LL-Byte + + // SCOCR2HH: Symbol Counter Output Compare Register 2 HH-Byte + SCOCR2HH_SCOCR2HH = 0xff // Symbol Counter Output Compare Register 2 HH-Byte + + // SCOCR2HL: Symbol Counter Output Compare Register 2 HL-Byte + SCOCR2HL_SCOCR2HL = 0xff // Symbol Counter Output Compare Register 2 HL-Byte + + // SCOCR2LH: Symbol Counter Output Compare Register 2 LH-Byte + SCOCR2LH_SCOCR2LH = 0xff // Symbol Counter Output Compare Register 2 LH-Byte + + // SCOCR2LL: Symbol Counter Output Compare Register 2 LL-Byte + SCOCR2LL_SCOCR2LL = 0xff // Symbol Counter Output Compare Register 2 LL-Byte + + // SCOCR3HH: Symbol Counter Output Compare Register 3 HH-Byte + SCOCR3HH_SCOCR3HH = 0xff // Symbol Counter Output Compare Register 3 HH-Byte + + // SCOCR3HL: Symbol Counter Output Compare Register 3 HL-Byte + SCOCR3HL_SCOCR3HL = 0xff // Symbol Counter Output Compare Register 3 HL-Byte + + // SCOCR3LH: Symbol Counter Output Compare Register 3 LH-Byte + SCOCR3LH_SCOCR3LH = 0xff // Symbol Counter Output Compare Register 3 LH-Byte + + // SCOCR3LL: Symbol Counter Output Compare Register 3 LL-Byte + SCOCR3LL_SCOCR3LL = 0xff // Symbol Counter Output Compare Register 3 LL-Byte + + // SCTSRHH: Symbol Counter Frame Timestamp Register HH-Byte + SCTSRHH_SCTSRHH = 0xff // Symbol Counter Frame Timestamp Register HH-Byte + + // SCTSRHL: Symbol Counter Frame Timestamp Register HL-Byte + SCTSRHL_SCTSRHL = 0xff // Symbol Counter Frame Timestamp Register HL-Byte + + // SCTSRLH: Symbol Counter Frame Timestamp Register LH-Byte + SCTSRLH_SCTSRLH = 0xff // Symbol Counter Frame Timestamp Register LH-Byte + + // SCTSRLL: Symbol Counter Frame Timestamp Register LL-Byte + SCTSRLL_SCTSRLL = 0xff // Symbol Counter Frame Timestamp Register LL-Byte + + // SCBTSRHH: Symbol Counter Beacon Timestamp Register HH-Byte + SCBTSRHH_SCBTSRHH = 0xff // Symbol Counter Beacon Timestamp Register HH-Byte + + // SCBTSRHL: Symbol Counter Beacon Timestamp Register HL-Byte + SCBTSRHL_SCBTSRHL = 0xff // Symbol Counter Beacon Timestamp Register HL-Byte + + // SCBTSRLH: Symbol Counter Beacon Timestamp Register LH-Byte + SCBTSRLH_SCBTSRLH = 0xff // Symbol Counter Beacon Timestamp Register LH-Byte + + // SCBTSRLL: Symbol Counter Beacon Timestamp Register LL-Byte + SCBTSRLL_SCBTSRLL = 0xff // Symbol Counter Beacon Timestamp Register LL-Byte + + // SCCNTHH: Symbol Counter Register HH-Byte + SCCNTHH_SCCNTHH = 0xff // Symbol Counter Register HH-Byte + + // SCCNTHL: Symbol Counter Register HL-Byte + SCCNTHL_SCCNTHL = 0xff // Symbol Counter Register HL-Byte + + // SCCNTLH: Symbol Counter Register LH-Byte + SCCNTLH_SCCNTLH = 0xff // Symbol Counter Register LH-Byte + + // SCCNTLL: Symbol Counter Register LL-Byte + SCCNTLL_SCCNTLL = 0xff // Symbol Counter Register LL-Byte + + // SCIRQS: Symbol Counter Interrupt Status Register + SCIRQS_Res = 0xe0 // Reserved Bit + SCIRQS_IRQSBO = 0x10 // Backoff Slot Counter IRQ + SCIRQS_IRQSOF = 0x8 // Symbol Counter Overflow IRQ + SCIRQS_IRQSCP = 0x7 // Compare Unit 3 Compare Match IRQ + + // SCIRQM: Symbol Counter Interrupt Mask Register + SCIRQM_Res = 0xe0 // Reserved Bit + SCIRQM_IRQMBO = 0x10 // Backoff Slot Counter IRQ enable + SCIRQM_IRQMOF = 0x8 // Symbol Counter Overflow IRQ enable + SCIRQM_IRQMCP = 0x7 // Symbol Counter Compare Match 3 IRQ enable + + // SCSR: Symbol Counter Status Register + SCSR_Res = 0xfe // Reserved Bit + SCSR_SCBSY = 0x1 // Symbol Counter busy + + // SCCR1: Symbol Counter Control Register 1 + SCCR1_Res = 0xfe // Reserved Bit + SCCR1_SCENBO = 0x1 // Backoff Slot Counter enable + + // SCCR0: Symbol Counter Control Register 0 + SCCR0_SCRES = 0x80 // Symbol Counter Synchronization + SCCR0_SCMBTS = 0x40 // Manual Beacon Timestamp + SCCR0_SCEN = 0x20 // Symbol Counter enable + SCCR0_SCCKSEL = 0x10 // Symbol Counter Clock Source select + SCCR0_SCTSE = 0x8 // Symbol Counter Automatic Timestamping enable + SCCR0_SCCMP = 0x7 // Symbol Counter Compare Unit 3 Mode select +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_Res = 0xc0 // Reserved + EECR_EEPM = 0x30 // EEPROM Programming Mode + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Programming Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for JTAG: JTAG Interface +const ( + // OCDR: On-Chip Debug Register + OCDR_OCDR = 0xff // On-Chip Debug Register Data +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC3 = 0xc0 // External Interrupt 3 Sense Control Bit + EICRA_ISC2 = 0x30 // External Interrupt 2 Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt 1 Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt 0 Sense Control Bit + + // EICRB: External Interrupt Control Register B + EICRB_ISC7 = 0xc0 // External Interrupt 7 Sense Control Bit + EICRB_ISC6 = 0x30 // External Interrupt 6 Sense Control Bit + EICRB_ISC5 = 0xc // External Interrupt 5 Sense Control Bit + EICRB_ISC4 = 0x3 // External Interrupt 4 Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xff // External Interrupt Request Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xff // External Interrupt Flag + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Mask + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Enable Mask + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_Res = 0xf8 // Reserved Bit + PCIFR_PCIF = 0x7 // Pin Change Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_Res = 0xf8 // Reserved Bit + PCICR_PCIE = 0x7 // Pin Change Interrupt Enables +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC Multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // ADC Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status Register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCSRC: The ADC Control and Status Register C + ADCSRC_ADTHT = 0xc0 // ADC Track-and-Hold Time + ADCSRC_Res0 = 0x20 // Reserved + ADCSRC_ADSUT = 0x1f // ADC Start-up Time + + // DIDR2: Digital Input Disable Register 2 + DIDR2_ADC15D = 0x80 // Reserved Bits + DIDR2_ADC14D = 0x40 // Reserved Bits + DIDR2_ADC13D = 0x20 // Reserved Bits + DIDR2_ADC12D = 0x10 // Reserved Bits + DIDR2_ADC11D = 0x8 // Reserved Bits + DIDR2_ADC10D = 0x4 // Reserved Bits + DIDR2_ADC9D = 0x2 // Reserved Bits + DIDR2_ADC8D = 0x1 // Reserved Bits + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // Disable ADC7:0 Digital Input + DIDR0_ADC6D = 0x40 // Disable ADC7:0 Digital Input + DIDR0_ADC5D = 0x20 // Disable ADC7:0 Digital Input + DIDR0_ADC4D = 0x10 // Disable ADC7:0 Digital Input + DIDR0_ADC3D = 0x8 // Disable ADC7:0 Digital Input + DIDR0_ADC2D = 0x4 // Disable ADC7:0 Digital Input + DIDR0_ADC1D = 0x2 // Disable ADC7:0 Digital Input + DIDR0_ADC0D = 0x1 // Disable ADC7:0 Digital Input +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write Section Read Enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_CAL = 0xff // Oscillator Calibration Tuning Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_Res = 0x70 // Reserved + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // SMCR: Sleep Mode Control Register + SMCR_Res = 0xf0 // Reserved + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // RAMPZ: Extended Z-pointer Register for ELPM/SPM + RAMPZ_Res = 0xfc // Reserved + RAMPZ_RAMPZ = 0x3 // Extended Z-Pointer Value + + // GPIOR2: General Purpose I/O Register 2 + GPIOR2_GPIOR = 0xff // General Purpose I/O Register 2 Value + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose I/O Register 1 Value + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR06 = 0x40 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR05 = 0x20 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR04 = 0x10 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR03 = 0x8 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR02 = 0x4 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR01 = 0x2 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR00 = 0x1 // General Purpose I/O Register 0 Value + + // PRR2: Power Reduction Register 2 + PRR2_PRRAM3 = 0x8 // Power Reduction SRAM3 + PRR2_PRRAM2 = 0x4 // Power Reduction SRAM2 + PRR2_PRRAM1 = 0x2 // Power Reduction SRAM1 + PRR2_PRRAM0 = 0x1 // Power Reduction SRAM0 + + // PRR1: Power Reduction Register 1 + PRR1_PRTRX24 = 0x40 // Power Reduction Transceiver + PRR1_PRTIM5 = 0x20 // Power Reduction Timer/Counter5 + PRR1_PRTIM4 = 0x10 // Power Reduction Timer/Counter4 + PRR1_PRTIM3 = 0x8 // Power Reduction Timer/Counter3 + PRR1_PRUSART1 = 0x1 // Power Reduction USART1 + + // PRR0: Power Reduction Register0 + PRR0_PRTWI = 0x80 // Power Reduction TWI + PRR0_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR0_PRPGA = 0x10 // Power Reduction PGA + PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR0_PRUSART0 = 0x2 // Power Reduction USART0 + PRR0_PRADC = 0x1 // Power Reduction ADC +) + +// Bitfields for FLASH: FLASH Controller +const ( + // NEMCR: Flash Extended-Mode Control-Register + NEMCR_ENEAM = 0x40 // Enable Extended Address Mode for Extra Rows + NEMCR_AEAM = 0x30 // Address for Extended Address Mode of Extra Rows + + // BGCR: Reference Voltage Calibration Register + BGCR_Res = 0x80 // Reserved Bit + BGCR_BGCAL_FINE = 0x78 // Fine Calibration Bits + BGCR_BGCAL = 0x7 // Coarse Calibration Bits +) + +// Bitfields for PWRCTRL: Power Controller +const ( + // TRXPR: Transceiver Pin Register + TRXPR_Res = 0xf0 // Reserved + TRXPR_SLPTR = 0x2 // Multi-purpose Transceiver Control Bit + TRXPR_TRXRST = 0x1 // Force Transceiver Reset + + // DRTRAM0: Data Retention Configuration Register of SRAM 0 + DRTRAM0_Res = 0xc0 // Reserved + DRTRAM0_DRTSWOK = 0x20 // DRT Switch OK + DRTRAM0_ENDRT = 0x10 // Enable SRAM Data Retention + + // DRTRAM1: Data Retention Configuration Register of SRAM 1 + DRTRAM1_Res = 0xc0 // Reserved + DRTRAM1_DRTSWOK = 0x20 // DRT Switch OK + DRTRAM1_ENDRT = 0x10 // Enable SRAM Data Retention + + // DRTRAM2: Data Retention Configuration Register of SRAM 2 + DRTRAM2_Res = 0x40 // Reserved Bit + DRTRAM2_DRTSWOK = 0x20 // DRT Switch OK + DRTRAM2_ENDRT = 0x10 // Enable SRAM Data Retention + + // DRTRAM3: Data Retention Configuration Register of SRAM 3 + DRTRAM3_Res = 0xc0 // Reserved + DRTRAM3_DRTSWOK = 0x20 // DRT Switch OK + DRTRAM3_ENDRT = 0x10 // Enable SRAM Data Retention + + // LLDRL: Low Leakage Voltage Regulator Data Register (Low-Byte) + LLDRL_Res = 0xf0 // Reserved + LLDRL_LLDRL = 0xf // Low-Byte Data Register Bits + + // LLDRH: Low Leakage Voltage Regulator Data Register (High-Byte) + LLDRH_Res = 0xe0 // Reserved + LLDRH_LLDRH = 0x1f // High-Byte Data Register Bits + + // LLCR: Low Leakage Voltage Regulator Control Register + LLCR_Res = 0xc0 // Reserved Bit + LLCR_LLDONE = 0x20 // Calibration Done + LLCR_LLCOMP = 0x10 // Comparator Output + LLCR_LLCAL = 0x8 // Calibration Active + LLCR_LLTCO = 0x4 // Temperature Coefficient of Current Source + LLCR_LLSHORT = 0x2 // Short Lower Calibration Circuit + LLCR_LLENCAL = 0x1 // Enable Automatic Calibration + + // DPDS0: Port Driver Strength Register 0 + DPDS0_PFDRV = 0xc0 // Driver Strength Port F + DPDS0_PEDRV = 0x30 // Driver Strength Port E + DPDS0_PDDRV = 0xc // Driver Strength Port D + DPDS0_PBDRV = 0x3 // Driver Strength Port B + + // DPDS1: Port Driver Strength Register 1 + DPDS1_Res = 0xfc // Reserved + DPDS1_PGDRV = 0x3 // Driver Strength Port G +) diff --git a/src/device/avr/atmega128rfa1.ld b/src/device/avr/atmega128rfa1.ld new file mode 100644 index 00000000..936d1e2c --- /dev/null +++ b/src/device/avr/atmega128rfa1.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega128RFA1.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x20000; +__ram_size = 0x4000; +__num_isrs = 72; diff --git a/src/device/avr/atmega128rfr2.go b/src/device/avr/atmega128rfr2.go new file mode 100644 index 00000000..613aadd4 --- /dev/null +++ b/src/device/avr/atmega128rfr2.go @@ -0,0 +1,1768 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega128RFR2.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega128rfr2 + +// Device information for the ATmega128RFR2. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega128RFR2" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_INT3 = 4 // External Interrupt Request 3 + IRQ_INT4 = 5 // External Interrupt Request 4 + IRQ_INT5 = 6 // External Interrupt Request 5 + IRQ_INT6 = 7 // External Interrupt Request 6 + IRQ_INT7 = 8 // External Interrupt Request 7 + IRQ_PCINT0 = 9 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 10 // Pin Change Interrupt Request 1 + IRQ_PCINT2 = 11 // Pin Change Interrupt Request 2 + IRQ_WDT = 12 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 13 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 14 // Timer/Counter2 Compare Match B + IRQ_TIMER2_OVF = 15 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 16 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 17 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 18 // Timer/Counter1 Compare Match B + IRQ_TIMER1_COMPC = 19 // Timer/Counter1 Compare Match C + IRQ_TIMER1_OVF = 20 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 21 // Timer/Counter0 Compare Match A + IRQ_TIMER0_COMPB = 22 // Timer/Counter0 Compare Match B + IRQ_TIMER0_OVF = 23 // Timer/Counter0 Overflow + IRQ_SPI_STC = 24 // SPI Serial Transfer Complete + IRQ_USART0_RX = 25 // USART0, Rx Complete + IRQ_USART0_UDRE = 26 // USART0 Data register Empty + IRQ_USART0_TX = 27 // USART0, Tx Complete + IRQ_ANALOG_COMP = 28 // Analog Comparator + IRQ_ADC = 29 // ADC Conversion Complete + IRQ_EE_READY = 30 // EEPROM Ready + IRQ_TIMER3_CAPT = 31 // Timer/Counter3 Capture Event + IRQ_TIMER3_COMPA = 32 // Timer/Counter3 Compare Match A + IRQ_TIMER3_COMPB = 33 // Timer/Counter3 Compare Match B + IRQ_TIMER3_COMPC = 34 // Timer/Counter3 Compare Match C + IRQ_TIMER3_OVF = 35 // Timer/Counter3 Overflow + IRQ_USART1_RX = 36 // USART1, Rx Complete + IRQ_USART1_UDRE = 37 // USART1 Data register Empty + IRQ_USART1_TX = 38 // USART1, Tx Complete + IRQ_TWI = 39 // 2-wire Serial Interface + IRQ_SPM_READY = 40 // Store Program Memory Read + IRQ_TIMER4_CAPT = 41 // Timer/Counter4 Capture Event + IRQ_TIMER4_COMPA = 42 // Timer/Counter4 Compare Match A + IRQ_TIMER4_COMPB = 43 // Timer/Counter4 Compare Match B + IRQ_TIMER4_COMPC = 44 // Timer/Counter4 Compare Match C + IRQ_TIMER4_OVF = 45 // Timer/Counter4 Overflow + IRQ_TIMER5_CAPT = 46 // Timer/Counter5 Capture Event + IRQ_TIMER5_COMPA = 47 // Timer/Counter5 Compare Match A + IRQ_TIMER5_COMPB = 48 // Timer/Counter5 Compare Match B + IRQ_TIMER5_COMPC = 49 // Timer/Counter5 Compare Match C + IRQ_TIMER5_OVF = 50 // Timer/Counter5 Overflow + IRQ_TRX24_PLL_LOCK = 57 // TRX24 - PLL lock interrupt + IRQ_TRX24_PLL_UNLOCK = 58 // TRX24 - PLL unlock interrupt + IRQ_TRX24_RX_START = 59 // TRX24 - Receive start interrupt + IRQ_TRX24_RX_END = 60 // TRX24 - RX_END interrupt + IRQ_TRX24_CCA_ED_DONE = 61 // TRX24 - CCA/ED done interrupt + IRQ_TRX24_XAH_AMI = 62 // TRX24 - XAH - AMI + IRQ_TRX24_TX_END = 63 // TRX24 - TX_END interrupt + IRQ_TRX24_AWAKE = 64 // TRX24 AWAKE - tranceiver is reaching state TRX_OFF + IRQ_SCNT_CMP1 = 65 // Symbol counter - compare match 1 interrupt + IRQ_SCNT_CMP2 = 66 // Symbol counter - compare match 2 interrupt + IRQ_SCNT_CMP3 = 67 // Symbol counter - compare match 3 interrupt + IRQ_SCNT_OVFL = 68 // Symbol counter - overflow interrupt + IRQ_SCNT_BACKOFF = 69 // Symbol counter - backoff interrupt + IRQ_AES_READY = 70 // AES engine ready interrupt + IRQ_BAT_LOW = 71 // Battery monitor indicates supply voltage below threshold + IRQ_TRX24_TX_START = 72 // TRX24 TX start interrupt + IRQ_TRX24_AMI0 = 73 // Address match interrupt of address filter 0 + IRQ_TRX24_AMI1 = 74 // Address match interrupt of address filter 1 + IRQ_TRX24_AMI2 = 75 // Address match interrupt of address filter 2 + IRQ_TRX24_AMI3 = 76 // Address match interrupt of address filter 3 + IRQ_max = 76 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // USART + USART = struct { + UDR0 __reg + UBRR0L __reg + UBRR0H __reg + UDR1 __reg + UBRR1L __reg + UBRR1H __reg + }{ + UDR0: 0xc6, // USART0 I/O Data Register + UBRR0L: 0xc4, // USART0 Baud Rate Register Bytes + UBRR0H: 0xc4, // USART0 Baud Rate Register Bytes + UDR1: 0xce, // USART1 I/O Data Register + UBRR1L: 0xcc, // USART1 Baud Rate Register Bytes + UBRR1H: 0xcc, // USART1 Baud Rate Register Bytes + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate Register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data Register + TWAR: 0xba, // TWI (Slave) Address Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins Address + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins Address + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins Address + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins Address + PORTE: 0x2e, // Port E Data Register + DDRE: 0x2d, // Port E Data Direction Register + PINE: 0x2c, // Port E Input Pins Address + PORTF: 0x31, // Port F Data Register + DDRF: 0x30, // Port F Data Direction Register + PINF: 0x2f, // Port F Input Pins Address + PORTG: 0x34, // Port G Data Register + DDRG: 0x33, // Port G Data Direction Register + PING: 0x32, // Port G Input Pins Address + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register B + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 Register + TCCR0B: 0x45, // Timer/Counter0 Control Register B + TCCR0A: 0x44, // Timer/Counter0 Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag Register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR5A __reg + TCCR5B __reg + TCCR5C __reg + TCNT5L __reg + TCNT5H __reg + OCR5AL __reg + OCR5AH __reg + OCR5BL __reg + OCR5BH __reg + OCR5CL __reg + OCR5CH __reg + ICR5L __reg + ICR5H __reg + TIMSK5 __reg + TIFR5 __reg + TCCR4A __reg + TCCR4B __reg + TCCR4C __reg + TCNT4L __reg + TCNT4H __reg + OCR4AL __reg + OCR4AH __reg + OCR4BL __reg + OCR4BH __reg + OCR4CL __reg + OCR4CH __reg + ICR4L __reg + ICR4H __reg + TIMSK4 __reg + TIFR4 __reg + TCCR3A __reg + TCCR3B __reg + TCCR3C __reg + TCNT3L __reg + TCNT3H __reg + OCR3AL __reg + OCR3AH __reg + OCR3BL __reg + OCR3BH __reg + OCR3CL __reg + OCR3CH __reg + ICR3L __reg + ICR3H __reg + TIMSK3 __reg + TIFR3 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + OCR1CL __reg + OCR1CH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR5A: 0x120, // Timer/Counter5 Control Register A + TCCR5B: 0x121, // Timer/Counter5 Control Register B + TCCR5C: 0x122, // Timer/Counter5 Control Register C + TCNT5L: 0x124, // Timer/Counter5 Bytes + TCNT5H: 0x124, // Timer/Counter5 Bytes + OCR5AL: 0x128, // Timer/Counter5 Output Compare Register A Bytes + OCR5AH: 0x128, // Timer/Counter5 Output Compare Register A Bytes + OCR5BL: 0x12a, // Timer/Counter5 Output Compare Register B Bytes + OCR5BH: 0x12a, // Timer/Counter5 Output Compare Register B Bytes + OCR5CL: 0x12c, // Timer/Counter5 Output Compare Register C Bytes + OCR5CH: 0x12c, // Timer/Counter5 Output Compare Register C Bytes + ICR5L: 0x126, // Timer/Counter5 Input Capture Register Bytes + ICR5H: 0x126, // Timer/Counter5 Input Capture Register Bytes + TIMSK5: 0x73, // Timer/Counter5 Interrupt Mask Register + TIFR5: 0x3a, // Timer/Counter5 Interrupt Flag Register + TCCR4A: 0xa0, // Timer/Counter4 Control Register A + TCCR4B: 0xa1, // Timer/Counter4 Control Register B + TCCR4C: 0xa2, // Timer/Counter4 Control Register C + TCNT4L: 0xa4, // Timer/Counter4 Bytes + TCNT4H: 0xa4, // Timer/Counter4 Bytes + OCR4AL: 0xa8, // Timer/Counter4 Output Compare Register A Bytes + OCR4AH: 0xa8, // Timer/Counter4 Output Compare Register A Bytes + OCR4BL: 0xaa, // Timer/Counter4 Output Compare Register B Bytes + OCR4BH: 0xaa, // Timer/Counter4 Output Compare Register B Bytes + OCR4CL: 0xac, // Timer/Counter4 Output Compare Register C Bytes + OCR4CH: 0xac, // Timer/Counter4 Output Compare Register C Bytes + ICR4L: 0xa6, // Timer/Counter4 Input Capture Register Bytes + ICR4H: 0xa6, // Timer/Counter4 Input Capture Register Bytes + TIMSK4: 0x72, // Timer/Counter4 Interrupt Mask Register + TIFR4: 0x39, // Timer/Counter4 Interrupt Flag Register + TCCR3A: 0x90, // Timer/Counter3 Control Register A + TCCR3B: 0x91, // Timer/Counter3 Control Register B + TCCR3C: 0x92, // Timer/Counter3 Control Register C + TCNT3L: 0x94, // Timer/Counter3 Bytes + TCNT3H: 0x94, // Timer/Counter3 Bytes + OCR3AL: 0x98, // Timer/Counter3 Output Compare Register A Bytes + OCR3AH: 0x98, // Timer/Counter3 Output Compare Register A Bytes + OCR3BL: 0x9a, // Timer/Counter3 Output Compare Register B Bytes + OCR3BH: 0x9a, // Timer/Counter3 Output Compare Register B Bytes + OCR3CL: 0x9c, // Timer/Counter3 Output Compare Register C Bytes + OCR3CH: 0x9c, // Timer/Counter3 Output Compare Register C Bytes + ICR3L: 0x96, // Timer/Counter3 Input Capture Register Bytes + ICR3H: 0x96, // Timer/Counter3 Input Capture Register Bytes + TIMSK3: 0x71, // Timer/Counter3 Interrupt Mask Register + TIFR3: 0x38, // Timer/Counter3 Interrupt Flag Register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1CL: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + OCR1CH: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag Register + } + + // Low-Power 2.4 GHz Transceiver + TRX24 = struct { + PARCR __reg + MAFSA0L __reg + MAFSA0H __reg + MAFPA0L __reg + MAFPA0H __reg + MAFSA1L __reg + MAFSA1H __reg + MAFPA1L __reg + MAFPA1H __reg + MAFSA2L __reg + MAFSA2H __reg + MAFPA2L __reg + MAFPA2H __reg + MAFSA3L __reg + MAFSA3H __reg + MAFPA3L __reg + MAFPA3H __reg + MAFCR0 __reg + MAFCR1 __reg + AES_CTRL __reg + AES_STATUS __reg + AES_STATE __reg + AES_KEY __reg + TRX_STATUS __reg + TRX_STATE __reg + TRX_CTRL_0 __reg + TRX_CTRL_1 __reg + PHY_TX_PWR __reg + PHY_RSSI __reg + PHY_ED_LEVEL __reg + PHY_CC_CCA __reg + CCA_THRES __reg + RX_CTRL __reg + SFD_VALUE __reg + TRX_CTRL_2 __reg + ANT_DIV __reg + IRQ_MASK __reg + IRQ_STATUS __reg + IRQ_MASK1 __reg + IRQ_STATUS1 __reg + VREG_CTRL __reg + BATMON __reg + XOSC_CTRL __reg + CC_CTRL_0 __reg + CC_CTRL_1 __reg + RX_SYN __reg + TRX_RPC __reg + XAH_CTRL_1 __reg + FTN_CTRL __reg + PLL_CF __reg + PLL_DCU __reg + PART_NUM __reg + VERSION_NUM __reg + MAN_ID_0 __reg + MAN_ID_1 __reg + SHORT_ADDR_0 __reg + SHORT_ADDR_1 __reg + PAN_ID_0 __reg + PAN_ID_1 __reg + IEEE_ADDR_0 __reg + IEEE_ADDR_1 __reg + IEEE_ADDR_2 __reg + IEEE_ADDR_3 __reg + IEEE_ADDR_4 __reg + IEEE_ADDR_5 __reg + IEEE_ADDR_6 __reg + IEEE_ADDR_7 __reg + XAH_CTRL_0 __reg + CSMA_SEED_0 __reg + CSMA_SEED_1 __reg + CSMA_BE __reg + TST_CTRL_DIGI __reg + TST_RX_LENGTH __reg + TRXFBST __reg + TRXFBEND __reg + }{ + PARCR: 0x138, // Power Amplifier Ramp up/down Control Register + MAFSA0L: 0x10e, // Transceiver MAC Short Address Register for Frame Filter 0 (Low Byte) + MAFSA0H: 0x10f, // Transceiver MAC Short Address Register for Frame Filter 0 (High Byte) + MAFPA0L: 0x110, // Transceiver Personal Area Network ID Register for Frame Filter 0 (Low Byte) + MAFPA0H: 0x111, // Transceiver Personal Area Network ID Register for Frame Filter 0 (High Byte) + MAFSA1L: 0x112, // Transceiver MAC Short Address Register for Frame Filter 1 (Low Byte) + MAFSA1H: 0x113, // Transceiver MAC Short Address Register for Frame Filter 1 (High Byte) + MAFPA1L: 0x114, // Transceiver Personal Area Network ID Register for Frame Filter 1 (Low Byte) + MAFPA1H: 0x115, // Transceiver Personal Area Network ID Register for Frame Filter 1 (High Byte) + MAFSA2L: 0x116, // Transceiver MAC Short Address Register for Frame Filter 2 (Low Byte) + MAFSA2H: 0x117, // Transceiver MAC Short Address Register for Frame Filter 2 (High Byte) + MAFPA2L: 0x118, // Transceiver Personal Area Network ID Register for Frame Filter 2 (Low Byte) + MAFPA2H: 0x119, // Transceiver Personal Area Network ID Register for Frame Filter 2 (High Byte) + MAFSA3L: 0x11a, // Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte) + MAFSA3H: 0x11b, // Transceiver MAC Short Address Register for Frame Filter 3 (High Byte) + MAFPA3L: 0x11c, // Transceiver Personal Area Network ID Register for Frame Filter 3 (Low Byte) + MAFPA3H: 0x11d, // Transceiver Personal Area Network ID Register for Frame Filter 3 (High Byte) + MAFCR0: 0x10c, // Multiple Address Filter Configuration Register 0 + MAFCR1: 0x10d, // Multiple Address Filter Configuration Register 1 + AES_CTRL: 0x13c, // AES Control Register + AES_STATUS: 0x13d, // AES Status Register + AES_STATE: 0x13e, // AES Plain and Cipher Text Buffer Register + AES_KEY: 0x13f, // AES Encryption and Decryption Key Buffer Register + TRX_STATUS: 0x141, // Transceiver Status Register + TRX_STATE: 0x142, // Transceiver State Control Register + TRX_CTRL_0: 0x143, // Reserved + TRX_CTRL_1: 0x144, // Transceiver Control Register 1 + PHY_TX_PWR: 0x145, // Transceiver Transmit Power Control Register + PHY_RSSI: 0x146, // Receiver Signal Strength Indicator Register + PHY_ED_LEVEL: 0x147, // Transceiver Energy Detection Level Register + PHY_CC_CCA: 0x148, // Transceiver Clear Channel Assessment (CCA) Control Register + CCA_THRES: 0x149, // Transceiver CCA Threshold Setting Register + RX_CTRL: 0x14a, // Transceiver Receive Control Register + SFD_VALUE: 0x14b, // Start of Frame Delimiter Value Register + TRX_CTRL_2: 0x14c, // Transceiver Control Register 2 + ANT_DIV: 0x14d, // Antenna Diversity Control Register + IRQ_MASK: 0x14e, // Transceiver Interrupt Enable Register + IRQ_STATUS: 0x14f, // Transceiver Interrupt Status Register + IRQ_MASK1: 0xbe, // Transceiver Interrupt Enable Register 1 + IRQ_STATUS1: 0xbf, // Transceiver Interrupt Status Register 1 + VREG_CTRL: 0x150, // Voltage Regulator Control and Status Register + BATMON: 0x151, // Battery Monitor Control and Status Register + XOSC_CTRL: 0x152, // Crystal Oscillator Control Register + CC_CTRL_0: 0x153, // Channel Control Register 0 + CC_CTRL_1: 0x154, // Channel Control Register 1 + RX_SYN: 0x155, // Transceiver Receiver Sensitivity Control Register + TRX_RPC: 0x156, // Transceiver Reduced Power Consumption Control + XAH_CTRL_1: 0x157, // Transceiver Acknowledgment Frame Control Register 1 + FTN_CTRL: 0x158, // Transceiver Filter Tuning Control Register + PLL_CF: 0x15a, // Transceiver Center Frequency Calibration Control Register + PLL_DCU: 0x15b, // Transceiver Delay Cell Calibration Control Register + PART_NUM: 0x15c, // Device Identification Register (Part Number) + VERSION_NUM: 0x15d, // Device Identification Register (Version Number) + MAN_ID_0: 0x15e, // Device Identification Register (Manufacture ID Low Byte) + MAN_ID_1: 0x15f, // Device Identification Register (Manufacture ID High Byte) + SHORT_ADDR_0: 0x160, // Transceiver MAC Short Address Register (Low Byte) + SHORT_ADDR_1: 0x161, // Transceiver MAC Short Address Register (High Byte) + PAN_ID_0: 0x162, // Transceiver Personal Area Network ID Register (Low Byte) + PAN_ID_1: 0x163, // Transceiver Personal Area Network ID Register (High Byte) + IEEE_ADDR_0: 0x164, // Transceiver MAC IEEE Address Register 0 + IEEE_ADDR_1: 0x165, // Transceiver MAC IEEE Address Register 1 + IEEE_ADDR_2: 0x166, // Transceiver MAC IEEE Address Register 2 + IEEE_ADDR_3: 0x167, // Transceiver MAC IEEE Address Register 3 + IEEE_ADDR_4: 0x168, // Transceiver MAC IEEE Address Register 4 + IEEE_ADDR_5: 0x169, // Transceiver MAC IEEE Address Register 5 + IEEE_ADDR_6: 0x16a, // Transceiver MAC IEEE Address Register 6 + IEEE_ADDR_7: 0x16b, // Transceiver MAC IEEE Address Register 7 + XAH_CTRL_0: 0x16c, // Transceiver Extended Operating Mode Control Register + CSMA_SEED_0: 0x16d, // Transceiver CSMA-CA Random Number Generator Seed Register + CSMA_SEED_1: 0x16e, // Transceiver Acknowledgment Frame Control Register 2 + CSMA_BE: 0x16f, // Transceiver CSMA-CA Back-off Exponent Control Register + TST_CTRL_DIGI: 0x176, // Transceiver Digital Test Control Register + TST_RX_LENGTH: 0x17b, // Transceiver Received Frame Length Register + TRXFBST: 0x180, // Start of frame buffer + TRXFBEND: 0x1ff, // End of frame buffer + } + + // MAC Symbol Counter + SYMCNT = struct { + SCTSTRHH __reg + SCTSTRHL __reg + SCTSTRLH __reg + SCTSTRLL __reg + SCOCR1HH __reg + SCOCR1HL __reg + SCOCR1LH __reg + SCOCR1LL __reg + SCOCR2HH __reg + SCOCR2HL __reg + SCOCR2LH __reg + SCOCR2LL __reg + SCOCR3HH __reg + SCOCR3HL __reg + SCOCR3LH __reg + SCOCR3LL __reg + SCTSRHH __reg + SCTSRHL __reg + SCTSRLH __reg + SCTSRLL __reg + SCBTSRHH __reg + SCBTSRHL __reg + SCBTSRLH __reg + SCBTSRLL __reg + SCCNTHH __reg + SCCNTHL __reg + SCCNTLH __reg + SCCNTLL __reg + SCIRQS __reg + SCIRQM __reg + SCSR __reg + SCCR1 __reg + SCCR0 __reg + SCCSR __reg + SCRSTRHH __reg + SCRSTRHL __reg + SCRSTRLH __reg + SCRSTRLL __reg + }{ + SCTSTRHH: 0xfc, // Symbol Counter Transmit Frame Timestamp Register HH-Byte + SCTSTRHL: 0xfb, // Symbol Counter Transmit Frame Timestamp Register HL-Byte + SCTSTRLH: 0xfa, // Symbol Counter Transmit Frame Timestamp Register LH-Byte + SCTSTRLL: 0xf9, // Symbol Counter Transmit Frame Timestamp Register LL-Byte + SCOCR1HH: 0xf8, // Symbol Counter Output Compare Register 1 HH-Byte + SCOCR1HL: 0xf7, // Symbol Counter Output Compare Register 1 HL-Byte + SCOCR1LH: 0xf6, // Symbol Counter Output Compare Register 1 LH-Byte + SCOCR1LL: 0xf5, // Symbol Counter Output Compare Register 1 LL-Byte + SCOCR2HH: 0xf4, // Symbol Counter Output Compare Register 2 HH-Byte + SCOCR2HL: 0xf3, // Symbol Counter Output Compare Register 2 HL-Byte + SCOCR2LH: 0xf2, // Symbol Counter Output Compare Register 2 LH-Byte + SCOCR2LL: 0xf1, // Symbol Counter Output Compare Register 2 LL-Byte + SCOCR3HH: 0xf0, // Symbol Counter Output Compare Register 3 HH-Byte + SCOCR3HL: 0xef, // Symbol Counter Output Compare Register 3 HL-Byte + SCOCR3LH: 0xee, // Symbol Counter Output Compare Register 3 LH-Byte + SCOCR3LL: 0xed, // Symbol Counter Output Compare Register 3 LL-Byte + SCTSRHH: 0xec, // Symbol Counter Frame Timestamp Register HH-Byte + SCTSRHL: 0xeb, // Symbol Counter Frame Timestamp Register HL-Byte + SCTSRLH: 0xea, // Symbol Counter Frame Timestamp Register LH-Byte + SCTSRLL: 0xe9, // Symbol Counter Frame Timestamp Register LL-Byte + SCBTSRHH: 0xe8, // Symbol Counter Beacon Timestamp Register HH-Byte + SCBTSRHL: 0xe7, // Symbol Counter Beacon Timestamp Register HL-Byte + SCBTSRLH: 0xe6, // Symbol Counter Beacon Timestamp Register LH-Byte + SCBTSRLL: 0xe5, // Symbol Counter Beacon Timestamp Register LL-Byte + SCCNTHH: 0xe4, // Symbol Counter Register HH-Byte + SCCNTHL: 0xe3, // Symbol Counter Register HL-Byte + SCCNTLH: 0xe2, // Symbol Counter Register LH-Byte + SCCNTLL: 0xe1, // Symbol Counter Register LL-Byte + SCIRQS: 0xe0, // Symbol Counter Interrupt Status Register + SCIRQM: 0xdf, // Symbol Counter Interrupt Mask Register + SCSR: 0xde, // Symbol Counter Status Register + SCCR1: 0xdd, // Symbol Counter Control Register 1 + SCCR0: 0xdc, // Symbol Counter Control Register 0 + SCCSR: 0xdb, // Symbol Counter Compare Source Register + SCRSTRHH: 0xda, // Symbol Counter Received Frame Timestamp Register HH-Byte + SCRSTRHL: 0xd9, // Symbol Counter Received Frame Timestamp Register HL-Byte + SCRSTRLH: 0xd8, // Symbol Counter Received Frame Timestamp Register LH-Byte + SCRSTRLL: 0xd7, // Symbol Counter Received Frame Timestamp Register LL-Byte + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Bytes + EEARH: 0x41, // EEPROM Address Register Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EICRB __reg + EIMSK __reg + EIFR __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + PCICR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EICRB: 0x6a, // External Interrupt Control Register B + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + ADCSRC __reg + DIDR2 __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC Multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // The ADC Control and Status Register A + ADCSRC: 0x77, // The ADC Control and Status Register C + DIDR2: 0x7d, // Digital Input Disable Register 2 + DIDR0: 0x7e, // Digital Input Disable Register 0 + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + RAMPZ __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PRR2 __reg + PRR1 __reg + PRR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + SMCR: 0x53, // Sleep Mode Control Register + RAMPZ: 0x5b, // Extended Z-pointer Register for ELPM/SPM + GPIOR2: 0x4b, // General Purpose I/O Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PRR2: 0x63, // Power Reduction Register 2 + PRR1: 0x65, // Power Reduction Register 1 + PRR0: 0x64, // Power Reduction Register0 + } + + // FLASH Controller + FLASH = struct { + NEMCR __reg + BGCR __reg + }{ + NEMCR: 0x75, // Flash Extended-Mode Control-Register + BGCR: 0x67, // Reference Voltage Calibration Register + } + + // Power Controller + PWRCTRL = struct { + TRXPR __reg + DRTRAM0 __reg + DRTRAM1 __reg + DRTRAM2 __reg + DRTRAM3 __reg + LLDRL __reg + LLDRH __reg + LLCR __reg + DPDS0 __reg + DPDS1 __reg + }{ + TRXPR: 0x139, // Transceiver Pin Register + DRTRAM0: 0x135, // Data Retention Configuration Register #0 + DRTRAM1: 0x134, // Data Retention Configuration Register #1 + DRTRAM2: 0x133, // Data Retention Configuration Register #2 + DRTRAM3: 0x132, // Data Retention Configuration Register #3 + LLDRL: 0x130, // Low Leakage Voltage Regulator Data Register (Low-Byte) + LLDRH: 0x131, // Low Leakage Voltage Regulator Data Register (High-Byte) + LLCR: 0x12f, // Low Leakage Voltage Regulator Control Register + DPDS0: 0x136, // Port Driver Strength Register 0 + DPDS1: 0x137, // Port Driver Strength Register 1 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_CKSEL_SUT = 0x3f // Select Clock Source : Start-up time +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe // TWI Address Mask + TWAMR_Res = 0x1 // Reserved Bit + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI START Condition Bit + TWCR_TWSTO = 0x10 // TWI STOP Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collision Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_Res = 0x2 // Reserved Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_Res = 0x4 // Reserved Bit + TWSR_TWPS = 0x3 // TWI Prescaler Bits + + // TWAR: TWI (Slave) Address Register + TWAR_TWA = 0xfe // TWI (Slave) Address + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Select 1 and 0 + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter0 Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_Res = 0x30 // Reserved Bit + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter0 Control Register A + TCCR0A_COM0A = 0xc0 // Compare Match Output A Mode + TCCR0A_COM0B = 0x30 // Compare Match Output B Mode + TCCR0A_Res = 0xc // Reserved Bit + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag Register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare B Match Flag + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare A Match Flag + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_Res = 0xf8 // Reserved Bit + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_Res = 0xf8 // Reserved Bit + TIFR2_OCF2B = 0x4 // Output Compare Flag 2 B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2 A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Match Output A Mode + TCCR2A_COM2B = 0x30 // Compare Match Output B Mode + TCCR2A_WGM2 = 0x3 // Waveform Generation Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select + + // ASSR: Asynchronous Status Register + ASSR_EXCLKAMR = 0x80 // Enable External Clock Input for AMR + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Timer/Counter2 Asynchronous Mode + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Timer/Counter2 Output Compare Register A Update Busy + ASSR_OCR2BUB = 0x4 // Timer/Counter2 Output Compare Register B Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter2 Control Register A Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter2 Control Register B Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR5A: Timer/Counter5 Control Register A + TCCR5A_COM5A = 0xc0 // Compare Output Mode for Channel A + TCCR5A_COM5B = 0x30 // Compare Output Mode for Channel B + TCCR5A_COM5C = 0xc // Compare Output Mode for Channel C + TCCR5A_WGM5 = 0x3 // Waveform Generation Mode + + // TCCR5B: Timer/Counter5 Control Register B + TCCR5B_ICNC5 = 0x80 // Input Capture 5 Noise Canceller + TCCR5B_ICES5 = 0x40 // Input Capture 5 Edge Select + TCCR5B_Res = 0x20 // Reserved Bit + TCCR5B_WGM5 = 0x18 // Waveform Generation Mode + TCCR5B_CS5 = 0x7 // Clock Select + + // TCCR5C: Timer/Counter5 Control Register C + TCCR5C_FOC5A = 0x80 // Force Output Compare for Channel A + TCCR5C_FOC5B = 0x40 // Force Output Compare for Channel B + TCCR5C_FOC5C = 0x20 // Force Output Compare for Channel C + + // TIMSK5: Timer/Counter5 Interrupt Mask Register + TIMSK5_ICIE5 = 0x20 // Timer/Counter5 Input Capture Interrupt Enable + TIMSK5_OCIE5C = 0x8 // Timer/Counter5 Output Compare C Match Interrupt Enable + TIMSK5_OCIE5B = 0x4 // Timer/Counter5 Output Compare B Match Interrupt Enable + TIMSK5_OCIE5A = 0x2 // Timer/Counter5 Output Compare A Match Interrupt Enable + TIMSK5_TOIE5 = 0x1 // Timer/Counter5 Overflow Interrupt Enable + + // TIFR5: Timer/Counter5 Interrupt Flag Register + TIFR5_ICF5 = 0x20 // Timer/Counter5 Input Capture Flag + TIFR5_OCF5C = 0x8 // Timer/Counter5 Output Compare C Match Flag + TIFR5_OCF5B = 0x4 // Timer/Counter5 Output Compare B Match Flag + TIFR5_OCF5A = 0x2 // Timer/Counter5 Output Compare A Match Flag + TIFR5_TOV5 = 0x1 // Timer/Counter5 Overflow Flag + + // TCCR4A: Timer/Counter4 Control Register A + TCCR4A_COM4A = 0xc0 // Compare Output Mode for Channel A + TCCR4A_COM4B = 0x30 // Compare Output Mode for Channel B + TCCR4A_COM4C = 0xc // Compare Output Mode for Channel C + TCCR4A_WGM4 = 0x3 // Waveform Generation Mode + + // TCCR4B: Timer/Counter4 Control Register B + TCCR4B_ICNC4 = 0x80 // Input Capture 4 Noise Canceller + TCCR4B_ICES4 = 0x40 // Input Capture 4 Edge Select + TCCR4B_Res = 0x20 // Reserved Bit + TCCR4B_WGM4 = 0x18 // Waveform Generation Mode + TCCR4B_CS4 = 0x7 // Clock Select + + // TCCR4C: Timer/Counter4 Control Register C + TCCR4C_FOC4A = 0x80 // Force Output Compare for Channel A + TCCR4C_FOC4B = 0x40 // Force Output Compare for Channel B + TCCR4C_FOC4C = 0x20 // Force Output Compare for Channel C + + // TIMSK4: Timer/Counter4 Interrupt Mask Register + TIMSK4_ICIE4 = 0x20 // Timer/Counter4 Input Capture Interrupt Enable + TIMSK4_OCIE4C = 0x8 // Timer/Counter4 Output Compare C Match Interrupt Enable + TIMSK4_OCIE4B = 0x4 // Timer/Counter4 Output Compare B Match Interrupt Enable + TIMSK4_OCIE4A = 0x2 // Timer/Counter4 Output Compare A Match Interrupt Enable + TIMSK4_TOIE4 = 0x1 // Timer/Counter4 Overflow Interrupt Enable + + // TIFR4: Timer/Counter4 Interrupt Flag Register + TIFR4_ICF4 = 0x20 // Timer/Counter4 Input Capture Flag + TIFR4_OCF4C = 0x8 // Timer/Counter4 Output Compare C Match Flag + TIFR4_OCF4B = 0x4 // Timer/Counter4 Output Compare B Match Flag + TIFR4_OCF4A = 0x2 // Timer/Counter4 Output Compare A Match Flag + TIFR4_TOV4 = 0x1 // Timer/Counter4 Overflow Flag + + // TCCR3A: Timer/Counter3 Control Register A + TCCR3A_COM3A = 0xc0 // Compare Output Mode for Channel A + TCCR3A_COM3B = 0x30 // Compare Output Mode for Channel B + TCCR3A_COM3C = 0xc // Compare Output Mode for Channel C + TCCR3A_WGM3 = 0x3 // Waveform Generation Mode + + // TCCR3B: Timer/Counter3 Control Register B + TCCR3B_ICNC3 = 0x80 // Input Capture 3 Noise Canceller + TCCR3B_ICES3 = 0x40 // Input Capture 3 Edge Select + TCCR3B_Res = 0x20 // Reserved Bit + TCCR3B_WGM3 = 0x18 // Waveform Generation Mode + TCCR3B_CS3 = 0x7 // Clock Select + + // TCCR3C: Timer/Counter3 Control Register C + TCCR3C_FOC3A = 0x80 // Force Output Compare for Channel A + TCCR3C_FOC3B = 0x40 // Force Output Compare for Channel B + TCCR3C_FOC3C = 0x20 // Force Output Compare for Channel C + + // TIMSK3: Timer/Counter3 Interrupt Mask Register + TIMSK3_ICIE3 = 0x20 // Timer/Counter3 Input Capture Interrupt Enable + TIMSK3_OCIE3C = 0x8 // Timer/Counter3 Output Compare C Match Interrupt Enable + TIMSK3_OCIE3B = 0x4 // Timer/Counter3 Output Compare B Match Interrupt Enable + TIMSK3_OCIE3A = 0x2 // Timer/Counter3 Output Compare A Match Interrupt Enable + TIMSK3_TOIE3 = 0x1 // Timer/Counter3 Overflow Interrupt Enable + + // TIFR3: Timer/Counter3 Interrupt Flag Register + TIFR3_ICF3 = 0x20 // Timer/Counter3 Input Capture Flag + TIFR3_OCF3C = 0x8 // Timer/Counter3 Output Compare C Match Flag + TIFR3_OCF3B = 0x4 // Timer/Counter3 Output Compare B Match Flag + TIFR3_OCF3A = 0x2 // Timer/Counter3 Output Compare A Match Flag + TIFR3_TOV3 = 0x1 // Timer/Counter3 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode for Channel A + TCCR1A_COM1B = 0x30 // Compare Output Mode for Channel B + TCCR1A_COM1C = 0xc // Compare Output Mode for Channel C + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceller + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_Res = 0x20 // Reserved Bit + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Clock Select + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare for Channel A + TCCR1C_FOC1B = 0x40 // Force Output Compare for Channel B + TCCR1C_FOC1C = 0x20 // Force Output Compare for Channel C + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1C = 0x8 // Timer/Counter1 Output Compare C Match Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag Register + TIFR1_ICF1 = 0x20 // Timer/Counter1 Input Capture Flag + TIFR1_OCF1C = 0x8 // Timer/Counter1 Output Compare C Match Flag + TIFR1_OCF1B = 0x4 // Timer/Counter1 Output Compare B Match Flag + TIFR1_OCF1A = 0x2 // Timer/Counter1 Output Compare A Match Flag + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for TRX24: Low-Power 2.4 GHz Transceiver +const ( + // PARCR: Power Amplifier Ramp up/down Control Register + PARCR_PALTD = 0xe0 // ext. PA Ramp Down Lead Time + PARCR_PALTU = 0x1c // ext. PA Ramp Up Lead Time + PARCR_PARDFI = 0x2 // Power Amplifier Ramp Down Frequency Inversion + PARCR_PARUFI = 0x1 // Power Amplifier Ramp Up Frequency Inversion + + // MAFSA0L: Transceiver MAC Short Address Register for Frame Filter 0 (Low Byte) + MAFSA0L_MAFSA0L = 0xff // MAC Short Address low Byte for Frame Filter 0 + + // MAFSA0H: Transceiver MAC Short Address Register for Frame Filter 0 (High Byte) + MAFSA0H_MAFSA0H = 0xff // MAC Short Address high Byte for Frame Filter 0 + + // MAFPA0L: Transceiver Personal Area Network ID Register for Frame Filter 0 (Low Byte) + MAFPA0L_MAFPA0L = 0xff // MAC Personal Area Network ID low Byte for Frame Filter 0 + + // MAFPA0H: Transceiver Personal Area Network ID Register for Frame Filter 0 (High Byte) + MAFPA0H_MAFPA0H = 0xff // MAC Personal Area Network ID high Byte for Frame Filter 0 + + // MAFSA1L: Transceiver MAC Short Address Register for Frame Filter 1 (Low Byte) + MAFSA1L_MAFSA1L = 0xff // MAC Short Address low Byte for Frame Filter 1 + + // MAFSA1H: Transceiver MAC Short Address Register for Frame Filter 1 (High Byte) + MAFSA1H_MAFSA1H = 0xff // MAC Short Address high Byte for Frame Filter 1 + + // MAFPA1L: Transceiver Personal Area Network ID Register for Frame Filter 1 (Low Byte) + MAFPA1L_MAFPA1L = 0xff // MAC Personal Area Network ID low Byte for Frame Filter 1 + + // MAFPA1H: Transceiver Personal Area Network ID Register for Frame Filter 1 (High Byte) + MAFPA1H_MAFPA1H = 0xff // MAC Personal Area Network ID high Byte for Frame Filter 1 + + // MAFSA2L: Transceiver MAC Short Address Register for Frame Filter 2 (Low Byte) + MAFSA2L_MAFSA2L = 0xff // MAC Short Address low Byte for Frame Filter 2 + + // MAFSA2H: Transceiver MAC Short Address Register for Frame Filter 2 (High Byte) + MAFSA2H_MAFSA2H = 0xff // MAC Short Address high Byte for Frame Filter 2 + + // MAFPA2L: Transceiver Personal Area Network ID Register for Frame Filter 2 (Low Byte) + MAFPA2L_MAFPA2L = 0xff // MAC Personal Area Network ID low Byte for Frame Filter 2 + + // MAFPA2H: Transceiver Personal Area Network ID Register for Frame Filter 2 (High Byte) + MAFPA2H_MAFPA2H = 0xff // MAC Personal Area Network ID high Byte for Frame Filter 2 + + // MAFSA3L: Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte) + MAFSA3L_MAFSA3L = 0xff // MAC Short Address low Byte for Frame Filter 3 + + // MAFSA3H: Transceiver MAC Short Address Register for Frame Filter 3 (High Byte) + MAFSA3H_MAFSA3H = 0xff // MAC Short Address high Byte for Frame Filter 3 + + // MAFPA3L: Transceiver Personal Area Network ID Register for Frame Filter 3 (Low Byte) + MAFPA3L_MAFPA3L = 0xff // MAC Personal Area Network ID low Byte for Frame Filter 3 + + // MAFPA3H: Transceiver Personal Area Network ID Register for Frame Filter 3 (High Byte) + MAFPA3H_MAFPA3H = 0xff // MAC Personal Area Network ID high Byte for Frame Filter 3 + + // MAFCR0: Multiple Address Filter Configuration Register 0 + MAFCR0_Res = 0xf0 // Reserved Bit + MAFCR0_MAF3EN = 0x8 // Multiple Address Filter 3 Enable + MAFCR0_MAF2EN = 0x4 // Multiple Address Filter 2 Enable + MAFCR0_MAF1EN = 0x2 // Multiple Address Filter 1 Enable + MAFCR0_MAF0EN = 0x1 // Multiple Address Filter 0 Enable + + // MAFCR1: Multiple Address Filter Configuration Register 1 + MAFCR1_AACK_3_SET_PD = 0x80 // Set Data Pending bit for address filter 3. + MAFCR1_AACK_3_I_AM_COORD = 0x40 // Enable PAN Coordinator mode for address filter 3. + MAFCR1_AACK_2_SET_PD = 0x20 // Set Data Pending bit for address filter 2. + MAFCR1_AACK_2_I_AM_COORD = 0x10 // Enable PAN Coordinator mode for address filter 2. + MAFCR1_AACK_1_SET_PD = 0x8 // Set Data Pending bit for address filter 1. + MAFCR1_AACK_1_I_AM_COORD = 0x4 // Enable PAN Coordinator mode for address filter 1. + MAFCR1_AACK_0_SET_PD = 0x2 // Set Data Pending bit for address filter 0. + MAFCR1_AACK_0_I_AM_COORD = 0x1 // Enable PAN Coordinator mode for address filter 0. + + // AES_CTRL: AES Control Register + AES_CTRL_AES_REQUEST = 0x80 // Request AES Operation. + AES_CTRL_AES_MODE = 0x20 // Set AES Operation Mode + AES_CTRL_AES_DIR = 0x8 // Set AES Operation Direction + AES_CTRL_AES_IM = 0x4 // AES Interrupt Enable + + // AES_STATUS: AES Status Register + AES_STATUS_AES_ER = 0x80 // AES Operation Finished with Error + AES_STATUS_AES_DONE = 0x1 // AES Operation Finished with Success + + // AES_STATE: AES Plain and Cipher Text Buffer Register + AES_STATE_AES_STATE = 0xff // AES Plain and Cipher Text Buffer + + // AES_KEY: AES Encryption and Decryption Key Buffer Register + AES_KEY_AES_KEY = 0xff // AES Encryption/Decryption Key Buffer + + // TRX_STATUS: Transceiver Status Register + TRX_STATUS_CCA_DONE = 0x80 // CCA Algorithm Status + TRX_STATUS_CCA_STATUS = 0x40 // CCA Status Result + TRX_STATUS_TST_STATUS = 0x20 // Test mode status + TRX_STATUS_TRX_STATUS = 0x1f // Transceiver Main Status + + // TRX_STATE: Transceiver State Control Register + TRX_STATE_TRAC_STATUS = 0xe0 // Transaction Status + TRX_STATE_TRX_CMD = 0x1f // State Control Command + + // TRX_CTRL_0: Reserved + TRX_CTRL_0_Res7 = 0x80 // Reserved + TRX_CTRL_0_PMU_EN = 0x40 // Enable Phase Measurement Unit + TRX_CTRL_0_PMU_START = 0x20 // Start of Phase Measurement Unit + TRX_CTRL_0_PMU_IF_INV = 0x10 // PMU IF Inverse + + // TRX_CTRL_1: Transceiver Control Register 1 + TRX_CTRL_1_PA_EXT_EN = 0x80 // External PA support enable + TRX_CTRL_1_IRQ_2_EXT_EN = 0x40 // Connect Frame Start IRQ to TC1 + TRX_CTRL_1_TX_AUTO_CRC_ON = 0x20 // Enable Automatic CRC Calculation + TRX_CTRL_1_PLL_TX_FLT = 0x10 // Enable PLL TX filter + + // PHY_TX_PWR: Transceiver Transmit Power Control Register + PHY_TX_PWR_TX_PWR = 0xf // Transmit Power Setting + + // PHY_RSSI: Receiver Signal Strength Indicator Register + PHY_RSSI_RX_CRC_VALID = 0x80 // Received Frame CRC Status + PHY_RSSI_RND_VALUE = 0x60 // Random Value + PHY_RSSI_RSSI = 0x1f // Receiver Signal Strength Indicator + + // PHY_ED_LEVEL: Transceiver Energy Detection Level Register + PHY_ED_LEVEL_ED_LEVEL = 0xff // Energy Detection Level + + // PHY_CC_CCA: Transceiver Clear Channel Assessment (CCA) Control Register + PHY_CC_CCA_CCA_REQUEST = 0x80 // Manual CCA Measurement Request + PHY_CC_CCA_CCA_MODE = 0x60 // Select CCA Measurement Mode + PHY_CC_CCA_CHANNEL = 0x1f // RX/TX Channel Selection + + // CCA_THRES: Transceiver CCA Threshold Setting Register + CCA_THRES_CCA_CS_THRES = 0xf0 // CS Threshold Level for CCA Measurement + CCA_THRES_CCA_ED_THRES = 0xf // ED Threshold Level for CCA Measurement + + // RX_CTRL: Transceiver Receive Control Register + RX_CTRL_PDT_THRES = 0xf // Receiver Sensitivity Control + + // SFD_VALUE: Start of Frame Delimiter Value Register + SFD_VALUE_SFD_VALUE = 0xff // Start of Frame Delimiter Value + + // TRX_CTRL_2: Transceiver Control Register 2 + TRX_CTRL_2_RX_SAFE_MODE = 0x80 // RX Safe Mode + TRX_CTRL_2_OQPSK_DATA_RATE = 0x3 // Data Rate Selection + + // ANT_DIV: Antenna Diversity Control Register + ANT_DIV_ANT_SEL = 0x80 // Antenna Diversity Antenna Status + ANT_DIV_ANT_DIV_EN = 0x8 // Enable Antenna Diversity + ANT_DIV_ANT_EXT_SW_EN = 0x4 // Enable External Antenna Switch Control + ANT_DIV_ANT_CTRL = 0x3 // Static Antenna Diversity Switch Control + + // IRQ_MASK: Transceiver Interrupt Enable Register + IRQ_MASK_AWAKE_EN = 0x80 // Awake Interrupt Enable + IRQ_MASK_TX_END_EN = 0x40 // TX_END Interrupt Enable + IRQ_MASK_AMI_EN = 0x20 // Address Match Interrupt Enable + IRQ_MASK_CCA_ED_DONE_EN = 0x10 // End of ED Measurement Interrupt Enable + IRQ_MASK_RX_END_EN = 0x8 // RX_END Interrupt Enable + IRQ_MASK_RX_START_EN = 0x4 // RX_START Interrupt Enable + IRQ_MASK_PLL_UNLOCK_EN = 0x2 // PLL Unlock Interrupt Enable + IRQ_MASK_PLL_LOCK_EN = 0x1 // PLL Lock Interrupt Enable + + // IRQ_STATUS: Transceiver Interrupt Status Register + IRQ_STATUS_AWAKE = 0x80 // Awake Interrupt Status + IRQ_STATUS_TX_END = 0x40 // TX_END Interrupt Status + IRQ_STATUS_AMI = 0x20 // Address Match Interrupt Status + IRQ_STATUS_CCA_ED_DONE = 0x10 // End of ED Measurement Interrupt Status + IRQ_STATUS_RX_END = 0x8 // RX_END Interrupt Status + IRQ_STATUS_RX_START = 0x4 // RX_START Interrupt Status + IRQ_STATUS_PLL_UNLOCK = 0x2 // PLL Unlock Interrupt Status + IRQ_STATUS_PLL_LOCK = 0x1 // PLL Lock Interrupt Status + + // IRQ_MASK1: Transceiver Interrupt Enable Register 1 + IRQ_MASK1_Res = 0xe0 // Reserved Bit + IRQ_MASK1_MAF_3_AMI_EN = 0x10 // Address Match Interrupt enable Address filter 3 + IRQ_MASK1_MAF_2_AMI_EN = 0x8 // Address Match Interrupt enable Address filter 2 + IRQ_MASK1_MAF_1_AMI_EN = 0x4 // Address Match Interrupt enable Address filter 1 + IRQ_MASK1_MAF_0_AMI_EN = 0x2 // Address Match Interrupt enable Address filter 0 + IRQ_MASK1_TX_START_EN = 0x1 // Transmit Start Interrupt enable + + // IRQ_STATUS1: Transceiver Interrupt Status Register 1 + IRQ_STATUS1_Res = 0xe0 // Reserved Bit + IRQ_STATUS1_MAF_3_AMI = 0x10 // Address Match Interrupt Status Address filter 3 + IRQ_STATUS1_MAF_2_AMI = 0x8 // Address Match Interrupt Status Address filter 2 + IRQ_STATUS1_MAF_1_AMI = 0x4 // Address Match Interrupt Status Address filter 1 + IRQ_STATUS1_MAF_0_AMI = 0x2 // Address Match Interrupt Status Address filter 0 + IRQ_STATUS1_TX_START = 0x1 // Transmit Start Interrupt Status + + // VREG_CTRL: Voltage Regulator Control and Status Register + VREG_CTRL_AVREG_EXT = 0x80 // Use External AVDD Regulator + VREG_CTRL_AVDD_OK = 0x40 // AVDD Supply Voltage Valid + VREG_CTRL_DVREG_EXT = 0x8 // Use External DVDD Regulator + VREG_CTRL_DVDD_OK = 0x4 // DVDD Supply Voltage Valid + + // BATMON: Battery Monitor Control and Status Register + BATMON_BAT_LOW = 0x80 // Battery Monitor Interrupt Status + BATMON_BAT_LOW_EN = 0x40 // Battery Monitor Interrupt Enable + BATMON_BATMON_OK = 0x20 // Battery Monitor Status + BATMON_BATMON_HR = 0x10 // Battery Monitor Voltage Range + BATMON_BATMON_VTH = 0xf // Battery Monitor Threshold Voltage + + // XOSC_CTRL: Crystal Oscillator Control Register + XOSC_CTRL_XTAL_MODE = 0xf0 // Crystal Oscillator Operating Mode + XOSC_CTRL_XTAL_TRIM = 0xf // Crystal Oscillator Load Capacitance Trimming + + // CC_CTRL_0: Channel Control Register 0 + CC_CTRL_0_CC_NUMBER = 0xff // Channel Number + + // CC_CTRL_1: Channel Control Register 1 + CC_CTRL_1_CC_BAND = 0xf // Channel Band + + // RX_SYN: Transceiver Receiver Sensitivity Control Register + RX_SYN_RX_PDT_DIS = 0x80 // Prevent Frame Reception + RX_SYN_RX_OVERRIDE = 0x40 // Receiver Override Function + RX_SYN_RX_PDT_LEVEL = 0xf // Reduce Receiver Sensitivity + + // TRX_RPC: Transceiver Reduced Power Consumption Control + TRX_RPC_RX_RPC_CTRL = 0xc0 // Smart Receiving Mode Timing + TRX_RPC_RX_RPC_EN = 0x20 // Reciver Smart Receiving Mode Enable + TRX_RPC_PDT_RPC_EN = 0x10 // Smart Receiving Mode Reduced Sensitivity Enable + TRX_RPC_PLL_RPC_EN = 0x8 // PLL Smart Receiving Mode Enable + TRX_RPC_Res0 = 0x4 // Reserved + TRX_RPC_IPAN_RPC_EN = 0x2 // Smart Receiving Mode IPAN Handling Enable + TRX_RPC_XAH_RPC_EN = 0x1 // Smart Receiving in Extended Operating Modes Enable + + // XAH_CTRL_1: Transceiver Acknowledgment Frame Control Register 1 + XAH_CTRL_1_AACK_FLTR_RES_FT = 0x20 // Filter Reserved Frames + XAH_CTRL_1_AACK_UPLD_RES_FT = 0x10 // Process Reserved Frames + XAH_CTRL_1_AACK_ACK_TIME = 0x4 // Reduce Acknowledgment Time + XAH_CTRL_1_AACK_PROM_MODE = 0x2 // Enable Promiscuous Mode + + // FTN_CTRL: Transceiver Filter Tuning Control Register + FTN_CTRL_FTN_START = 0x80 // Start Calibration Loop of Filter Tuning Network + + // PLL_CF: Transceiver Center Frequency Calibration Control Register + PLL_CF_PLL_CF_START = 0x80 // Start Center Frequency Calibration + + // PLL_DCU: Transceiver Delay Cell Calibration Control Register + PLL_DCU_PLL_DCU_START = 0x80 // Start Delay Cell Calibration + + // PART_NUM: Device Identification Register (Part Number) + PART_NUM_PART_NUM = 0xff // Part Number + + // VERSION_NUM: Device Identification Register (Version Number) + VERSION_NUM_VERSION_NUM = 0xff // Version Number + + // MAN_ID_0: Device Identification Register (Manufacture ID Low Byte) + MAN_ID_0_MAN_ID_07 = 0x80 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_06 = 0x40 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_05 = 0x20 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_04 = 0x10 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_03 = 0x8 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_02 = 0x4 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_01 = 0x2 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_00 = 0x1 // Manufacturer ID (Low Byte) + + // MAN_ID_1: Device Identification Register (Manufacture ID High Byte) + MAN_ID_1_MAN_ID_ = 0xff // Manufacturer ID (High Byte) + + // SHORT_ADDR_0: Transceiver MAC Short Address Register (Low Byte) + SHORT_ADDR_0_SHORT_ADDR_07 = 0x80 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_06 = 0x40 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_05 = 0x20 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_04 = 0x10 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_03 = 0x8 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_02 = 0x4 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_01 = 0x2 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_00 = 0x1 // MAC Short Address + + // SHORT_ADDR_1: Transceiver MAC Short Address Register (High Byte) + SHORT_ADDR_1_SHORT_ADDR_ = 0xff // MAC Short Address + + // PAN_ID_0: Transceiver Personal Area Network ID Register (Low Byte) + PAN_ID_0_PAN_ID_07 = 0x80 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_06 = 0x40 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_05 = 0x20 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_04 = 0x10 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_03 = 0x8 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_02 = 0x4 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_01 = 0x2 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_00 = 0x1 // MAC Personal Area Network ID + + // PAN_ID_1: Transceiver Personal Area Network ID Register (High Byte) + PAN_ID_1_PAN_ID_ = 0xff // MAC Personal Area Network ID + + // IEEE_ADDR_0: Transceiver MAC IEEE Address Register 0 + IEEE_ADDR_0_IEEE_ADDR_07 = 0x80 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_06 = 0x40 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_05 = 0x20 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_04 = 0x10 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_03 = 0x8 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_02 = 0x4 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_01 = 0x2 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_00 = 0x1 // MAC IEEE Address + + // IEEE_ADDR_1: Transceiver MAC IEEE Address Register 1 + IEEE_ADDR_1_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // IEEE_ADDR_2: Transceiver MAC IEEE Address Register 2 + IEEE_ADDR_2_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // IEEE_ADDR_3: Transceiver MAC IEEE Address Register 3 + IEEE_ADDR_3_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // IEEE_ADDR_4: Transceiver MAC IEEE Address Register 4 + IEEE_ADDR_4_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // IEEE_ADDR_5: Transceiver MAC IEEE Address Register 5 + IEEE_ADDR_5_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // IEEE_ADDR_6: Transceiver MAC IEEE Address Register 6 + IEEE_ADDR_6_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // IEEE_ADDR_7: Transceiver MAC IEEE Address Register 7 + IEEE_ADDR_7_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // XAH_CTRL_0: Transceiver Extended Operating Mode Control Register + XAH_CTRL_0_MAX_FRAME_RETRIES = 0xf0 // Maximum Number of Frame Re-transmission Attempts + XAH_CTRL_0_MAX_CSMA_RETRIES = 0xe // Maximum Number of CSMA-CA Procedure Repetition Attempts + XAH_CTRL_0_SLOTTED_OPERATION = 0x1 // Set Slotted Acknowledgment + + // CSMA_SEED_0: Transceiver CSMA-CA Random Number Generator Seed Register + CSMA_SEED_0_CSMA_SEED_07 = 0x80 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_06 = 0x40 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_05 = 0x20 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_04 = 0x10 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_03 = 0x8 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_02 = 0x4 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_01 = 0x2 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_00 = 0x1 // Seed Value for CSMA Random Number Generator + + // CSMA_SEED_1: Transceiver Acknowledgment Frame Control Register 2 + CSMA_SEED_1_AACK_FVN_MODE = 0xc0 // Acknowledgment Frame Filter Mode + CSMA_SEED_1_AACK_SET_PD = 0x20 // Set Frame Pending Sub-field + CSMA_SEED_1_AACK_DIS_ACK = 0x10 // Disable Acknowledgment Frame Transmission + CSMA_SEED_1_AACK_I_AM_COORD = 0x8 // Set Personal Area Network Coordinator + CSMA_SEED_1_CSMA_SEED_1 = 0x7 // Seed Value for CSMA Random Number Generator + + // CSMA_BE: Transceiver CSMA-CA Back-off Exponent Control Register + CSMA_BE_MAX_BE = 0xf0 // Maximum Back-off Exponent + CSMA_BE_MIN_BE = 0xf // Minimum Back-off Exponent + + // TST_CTRL_DIGI: Transceiver Digital Test Control Register + TST_CTRL_DIGI_TST_CTRL_DIG = 0xf // Digital Test Controller Register + + // TST_RX_LENGTH: Transceiver Received Frame Length Register + TST_RX_LENGTH_RX_LENGTH = 0xff // Received Frame Length +) + +// Bitfields for SYMCNT: MAC Symbol Counter +const ( + // SCTSTRHH: Symbol Counter Transmit Frame Timestamp Register HH-Byte + SCTSTRHH_SCTSTRHH = 0xff // Symbol Counter Transmit Frame Timestamp Register HH-Byte + + // SCTSTRHL: Symbol Counter Transmit Frame Timestamp Register HL-Byte + SCTSTRHL_SCTSTRHL = 0xff // Symbol Counter Transmit Frame Timestamp Register HL-Byte + + // SCTSTRLH: Symbol Counter Transmit Frame Timestamp Register LH-Byte + SCTSTRLH_SCTSTRLH = 0xff // Symbol Counter Transmit Frame Timestamp Register LH-Byte + + // SCTSTRLL: Symbol Counter Transmit Frame Timestamp Register LL-Byte + SCTSTRLL_SCTSTRLL = 0xff // Symbol Counter Transmit Frame Timestamp Register LL-Byte + + // SCOCR1HH: Symbol Counter Output Compare Register 1 HH-Byte + SCOCR1HH_SCOCR1HH = 0xff // Symbol Counter Output Compare Register 1 HH-Byte + + // SCOCR1HL: Symbol Counter Output Compare Register 1 HL-Byte + SCOCR1HL_SCOCR1HL = 0xff // Symbol Counter Output Compare Register 1 HL-Byte + + // SCOCR1LH: Symbol Counter Output Compare Register 1 LH-Byte + SCOCR1LH_SCOCR1LH = 0xff // Symbol Counter Output Compare Register 1 LH-Byte + + // SCOCR1LL: Symbol Counter Output Compare Register 1 LL-Byte + SCOCR1LL_SCOCR1LL = 0xff // Symbol Counter Output Compare Register 1 LL-Byte + + // SCOCR2HH: Symbol Counter Output Compare Register 2 HH-Byte + SCOCR2HH_SCOCR2HH = 0xff // Symbol Counter Output Compare Register 2 HH-Byte + + // SCOCR2HL: Symbol Counter Output Compare Register 2 HL-Byte + SCOCR2HL_SCOCR2HL = 0xff // Symbol Counter Output Compare Register 2 HL-Byte + + // SCOCR2LH: Symbol Counter Output Compare Register 2 LH-Byte + SCOCR2LH_SCOCR2LH = 0xff // Symbol Counter Output Compare Register 2 LH-Byte + + // SCOCR2LL: Symbol Counter Output Compare Register 2 LL-Byte + SCOCR2LL_SCOCR2LL = 0xff // Symbol Counter Output Compare Register 2 LL-Byte + + // SCOCR3HH: Symbol Counter Output Compare Register 3 HH-Byte + SCOCR3HH_SCOCR3HH = 0xff // Symbol Counter Output Compare Register 3 HH-Byte + + // SCOCR3HL: Symbol Counter Output Compare Register 3 HL-Byte + SCOCR3HL_SCOCR3HL = 0xff // Symbol Counter Output Compare Register 3 HL-Byte + + // SCOCR3LH: Symbol Counter Output Compare Register 3 LH-Byte + SCOCR3LH_SCOCR3LH = 0xff // Symbol Counter Output Compare Register 3 LH-Byte + + // SCOCR3LL: Symbol Counter Output Compare Register 3 LL-Byte + SCOCR3LL_SCOCR3LL = 0xff // Symbol Counter Output Compare Register 3 LL-Byte + + // SCTSRHH: Symbol Counter Frame Timestamp Register HH-Byte + SCTSRHH_SCTSRHH = 0xff // Symbol Counter Frame Timestamp Register HH-Byte + + // SCTSRHL: Symbol Counter Frame Timestamp Register HL-Byte + SCTSRHL_SCTSRHL = 0xff // Symbol Counter Frame Timestamp Register HL-Byte + + // SCTSRLH: Symbol Counter Frame Timestamp Register LH-Byte + SCTSRLH_SCTSRLH = 0xff // Symbol Counter Frame Timestamp Register LH-Byte + + // SCTSRLL: Symbol Counter Frame Timestamp Register LL-Byte + SCTSRLL_SCTSRLL = 0xff // Symbol Counter Frame Timestamp Register LL-Byte + + // SCBTSRHH: Symbol Counter Beacon Timestamp Register HH-Byte + SCBTSRHH_SCBTSRHH = 0xff // Symbol Counter Beacon Timestamp Register HH-Byte + + // SCBTSRHL: Symbol Counter Beacon Timestamp Register HL-Byte + SCBTSRHL_SCBTSRHL = 0xff // Symbol Counter Beacon Timestamp Register HL-Byte + + // SCBTSRLH: Symbol Counter Beacon Timestamp Register LH-Byte + SCBTSRLH_SCBTSRLH = 0xff // Symbol Counter Beacon Timestamp Register LH-Byte + + // SCBTSRLL: Symbol Counter Beacon Timestamp Register LL-Byte + SCBTSRLL_SCBTSRLL = 0xff // Symbol Counter Beacon Timestamp Register LL-Byte + + // SCCNTHH: Symbol Counter Register HH-Byte + SCCNTHH_SCCNTHH = 0xff // Symbol Counter Register HH-Byte + + // SCCNTHL: Symbol Counter Register HL-Byte + SCCNTHL_SCCNTHL = 0xff // Symbol Counter Register HL-Byte + + // SCCNTLH: Symbol Counter Register LH-Byte + SCCNTLH_SCCNTLH = 0xff // Symbol Counter Register LH-Byte + + // SCCNTLL: Symbol Counter Register LL-Byte + SCCNTLL_SCCNTLL = 0xff // Symbol Counter Register LL-Byte + + // SCIRQS: Symbol Counter Interrupt Status Register + SCIRQS_Res = 0xe0 // Reserved Bit + SCIRQS_IRQSBO = 0x10 // Backoff Slot Counter IRQ + SCIRQS_IRQSOF = 0x8 // Symbol Counter Overflow IRQ + SCIRQS_IRQSCP = 0x7 // Compare Unit 3 Compare Match IRQ + + // SCIRQM: Symbol Counter Interrupt Mask Register + SCIRQM_Res = 0xe0 // Reserved Bit + SCIRQM_IRQMBO = 0x10 // Backoff Slot Counter IRQ enable + SCIRQM_IRQMOF = 0x8 // Symbol Counter Overflow IRQ enable + SCIRQM_IRQMCP = 0x7 // Symbol Counter Compare Match 3 IRQ enable + + // SCSR: Symbol Counter Status Register + SCSR_Res = 0xfe // Reserved Bit + SCSR_SCBSY = 0x1 // Symbol Counter busy + + // SCCR1: Symbol Counter Control Register 1 + SCCR1_Res = 0xc0 // Reserved Bit + SCCR1_SCBTSM = 0x20 // Symbol Counter Beacon Timestamp Mask Register + SCCR1_SCCKDIV = 0x1c // Clock divider for synchronous clock source (16MHz Transceiver Clock) + SCCR1_SCEECLK = 0x2 // Enable External Clock Source on PG2 + SCCR1_SCENBO = 0x1 // Backoff Slot Counter enable + + // SCCR0: Symbol Counter Control Register 0 + SCCR0_SCRES = 0x80 // Symbol Counter Synchronization + SCCR0_SCMBTS = 0x40 // Manual Beacon Timestamp + SCCR0_SCEN = 0x20 // Symbol Counter enable + SCCR0_SCCKSEL = 0x10 // Symbol Counter Clock Source select + SCCR0_SCTSE = 0x8 // Symbol Counter Automatic Timestamping enable + SCCR0_SCCMP = 0x7 // Symbol Counter Compare Unit 3 Mode select + + // SCCSR: Symbol Counter Compare Source Register + SCCSR_Res = 0xc0 // Reserved Bit + SCCSR_SCCS3 = 0x30 // Symbol Counter Compare Source select register for Compare Unit 3 + SCCSR_SCCS2 = 0xc // Symbol Counter Compare Source select register for Compare Unit 2 + SCCSR_SCCS1 = 0x3 // Symbol Counter Compare Source select register for Compare Units + + // SCRSTRHH: Symbol Counter Received Frame Timestamp Register HH-Byte + SCRSTRHH_SCRSTRHH = 0xff // Symbol Counter Received Frame Timestamp Register HH-Byte + + // SCRSTRHL: Symbol Counter Received Frame Timestamp Register HL-Byte + SCRSTRHL_SCRSTRHL = 0xff // Symbol Counter Received Frame Timestamp Register HL-Byte + + // SCRSTRLH: Symbol Counter Received Frame Timestamp Register LH-Byte + SCRSTRLH_SCRSTRLH = 0xff // Symbol Counter Received Frame Timestamp Register LH-Byte + + // SCRSTRLL: Symbol Counter Received Frame Timestamp Register LL-Byte + SCRSTRLL_SCRSTRLL = 0xff // Symbol Counter Received Frame Timestamp Register LL-Byte +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Programming Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for JTAG: JTAG Interface +const ( + // OCDR: On-Chip Debug Register + OCDR_OCDR = 0xff // On-Chip Debug Register Data +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC3 = 0xc0 // External Interrupt 3 Sense Control Bit + EICRA_ISC2 = 0x30 // External Interrupt 2 Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt 1 Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt 0 Sense Control Bit + + // EICRB: External Interrupt Control Register B + EICRB_ISC7 = 0xc0 // External Interrupt 7 Sense Control Bit + EICRB_ISC6 = 0x30 // External Interrupt 6 Sense Control Bit + EICRB_ISC5 = 0xc // External Interrupt 5 Sense Control Bit + EICRB_ISC4 = 0x3 // External Interrupt 4 Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xff // External Interrupt Request Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xff // External Interrupt Flag + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Mask + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Enable Mask + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Mask + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_Res = 0xf8 // Reserved Bit + PCIFR_PCIF = 0x7 // Pin Change Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_Res = 0xf8 // Reserved Bit + PCICR_PCIE = 0x7 // Pin Change Interrupt Enables +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC Multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // ADC Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status Register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCSRC: The ADC Control and Status Register C + ADCSRC_ADTHT = 0xc0 // ADC Track-and-Hold Time + ADCSRC_Res0 = 0x20 // Reserved + ADCSRC_ADSUT = 0x1f // ADC Start-up Time + + // DIDR2: Digital Input Disable Register 2 + DIDR2_ADC15D = 0x80 // Reserved Bits + DIDR2_ADC14D = 0x40 // Reserved Bits + DIDR2_ADC13D = 0x20 // Reserved Bits + DIDR2_ADC12D = 0x10 // Reserved Bits + DIDR2_ADC11D = 0x8 // Reserved Bits + DIDR2_ADC10D = 0x4 // Reserved Bits + DIDR2_ADC9D = 0x2 // Reserved Bits + DIDR2_ADC8D = 0x1 // Reserved Bits + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // Disable ADC7:0 Digital Input + DIDR0_ADC6D = 0x40 // Disable ADC7:0 Digital Input + DIDR0_ADC5D = 0x20 // Disable ADC7:0 Digital Input + DIDR0_ADC4D = 0x10 // Disable ADC7:0 Digital Input + DIDR0_ADC3D = 0x8 // Disable ADC7:0 Digital Input + DIDR0_ADC2D = 0x4 // Disable ADC7:0 Digital Input + DIDR0_ADC1D = 0x2 // Disable ADC7:0 Digital Input + DIDR0_ADC0D = 0x1 // Disable ADC7:0 Digital Input +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write Section Read Enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_CAL = 0xff // Oscillator Calibration Tuning Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // RAMPZ: Extended Z-pointer Register for ELPM/SPM + RAMPZ_RAMPZ0 = 0x1 // Extended Z-Pointer Value + + // GPIOR2: General Purpose I/O Register 2 + GPIOR2_GPIOR = 0xff // General Purpose I/O Register 2 Value + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose I/O Register 1 Value + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR06 = 0x40 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR05 = 0x20 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR04 = 0x10 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR03 = 0x8 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR02 = 0x4 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR01 = 0x2 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR00 = 0x1 // General Purpose I/O Register 0 Value + + // PRR2: Power Reduction Register 2 + PRR2_Res = 0xf0 // Reserved Bit + PRR2_PRRAM3 = 0x8 // Power Reduction SRAM3 + PRR2_PRRAM2 = 0x4 // Power Reduction SRAM2 + PRR2_PRRAM1 = 0x2 // Power Reduction SRAM1 + PRR2_PRRAM0 = 0x1 // Power Reduction SRAM0 + + // PRR1: Power Reduction Register 1 + PRR1_Res = 0x80 // Reserved Bit + PRR1_PRTRX24 = 0x40 // Power Reduction Transceiver + PRR1_PRTIM5 = 0x20 // Power Reduction Timer/Counter5 + PRR1_PRTIM4 = 0x10 // Power Reduction Timer/Counter4 + PRR1_PRTIM3 = 0x8 // Power Reduction Timer/Counter3 + PRR1_PRUSART1 = 0x1 // Power Reduction USART1 + + // PRR0: Power Reduction Register0 + PRR0_PRTWI = 0x80 // Power Reduction TWI + PRR0_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR0_PRPGA = 0x10 // Power Reduction PGA + PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR0_PRUSART0 = 0x2 // Power Reduction USART + PRR0_PRADC = 0x1 // Power Reduction ADC +) + +// Bitfields for FLASH: FLASH Controller +const ( + // NEMCR: Flash Extended-Mode Control-Register + NEMCR_ENEAM = 0x40 // Enable Extended Address Mode for Extra Rows + NEMCR_AEAM = 0x30 // Address for Extended Address Mode of Extra Rows + + // BGCR: Reference Voltage Calibration Register + BGCR_Res = 0x80 // Reserved Bit + BGCR_BGCAL_FINE = 0x78 // Fine Calibration Bits + BGCR_BGCAL = 0x7 // Coarse Calibration Bits +) + +// Bitfields for PWRCTRL: Power Controller +const ( + // TRXPR: Transceiver Pin Register + TRXPR_SLPTR = 0x2 // Multi-purpose Transceiver Control Bit + TRXPR_TRXRST = 0x1 // Force Transceiver Reset + + // DRTRAM0: Data Retention Configuration Register #0 + DRTRAM0_DRTSWOK = 0x20 // DRT Switch OK + DRTRAM0_ENDRT = 0x10 // Enable SRAM Data Retention + + // DRTRAM1: Data Retention Configuration Register #1 + DRTRAM1_DRTSWOK = 0x20 // DRT Switch OK + DRTRAM1_ENDRT = 0x10 // Enable SRAM Data Retention + + // DRTRAM2: Data Retention Configuration Register #2 + DRTRAM2_Res = 0x40 // Reserved Bit + DRTRAM2_DRTSWOK = 0x20 // DRT Switch OK + DRTRAM2_ENDRT = 0x10 // Enable SRAM Data Retention + + // DRTRAM3: Data Retention Configuration Register #3 + DRTRAM3_DRTSWOK = 0x20 // DRT Switch OK + DRTRAM3_ENDRT = 0x10 // Enable SRAM Data Retention + + // LLDRL: Low Leakage Voltage Regulator Data Register (Low-Byte) + LLDRL_LLDRL = 0xf // Low-Byte Data Register Bits + + // LLDRH: Low Leakage Voltage Regulator Data Register (High-Byte) + LLDRH_LLDRH = 0x1f // High-Byte Data Register Bits + + // LLCR: Low Leakage Voltage Regulator Control Register + LLCR_Res = 0xc0 // Reserved Bit + LLCR_LLDONE = 0x20 // Calibration Done + LLCR_LLCOMP = 0x10 // Comparator Output + LLCR_LLCAL = 0x8 // Calibration Active + LLCR_LLTCO = 0x4 // Temperature Coefficient of Current Source + LLCR_LLSHORT = 0x2 // Short Lower Calibration Circuit + LLCR_LLENCAL = 0x1 // Enable Automatic Calibration + + // DPDS0: Port Driver Strength Register 0 + DPDS0_PFDRV = 0xc0 // Driver Strength Port F + DPDS0_PEDRV = 0x30 // Driver Strength Port E + DPDS0_PDDRV = 0xc // Driver Strength Port D + DPDS0_PBDRV = 0x3 // Driver Strength Port B + + // DPDS1: Port Driver Strength Register 1 + DPDS1_PGDRV = 0x3 // Driver Strength Port G +) diff --git a/src/device/avr/atmega128rfr2.ld b/src/device/avr/atmega128rfr2.ld new file mode 100644 index 00000000..3391556a --- /dev/null +++ b/src/device/avr/atmega128rfr2.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega128RFR2.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x20000; +__ram_size = 0x4000; +__num_isrs = 71; diff --git a/src/device/avr/atmega16.go b/src/device/avr/atmega16.go new file mode 100644 index 00000000..70c9c473 --- /dev/null +++ b/src/device/avr/atmega16.go @@ -0,0 +1,491 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega16.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega16 + +// Device information for the ATmega16. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega16" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_TIMER2_COMP = 3 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 4 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 5 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 6 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 7 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 8 // Timer/Counter1 Overflow + IRQ_TIMER0_OVF = 9 // Timer/Counter0 Overflow + IRQ_SPI_STC = 10 // Serial Transfer Complete + IRQ_USART_RXC = 11 // USART, Rx Complete + IRQ_USART_UDRE = 12 // USART Data Register Empty + IRQ_USART_TXC = 13 // USART, Tx Complete + IRQ_ADC = 14 // ADC Conversion Complete + IRQ_EE_RDY = 15 // EEPROM Ready + IRQ_ANA_COMP = 16 // Analog Comparator + IRQ_TWI = 17 // 2-wire Serial Interface + IRQ_INT2 = 18 // External Interrupt Request 2 + IRQ_TIMER0_COMP = 19 // Timer/Counter0 Compare Match + IRQ_SPM_RDY = 20 // Store Program Memory Ready + IRQ_max = 20 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + HIGH __reg + LOW __reg + }{ + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0 __reg + TCNT0 __reg + OCR0 __reg + }{ + TCCR0: 0x53, // Timer/Counter Control Register + TCNT0: 0x52, // Timer/Counter Register + OCR0: 0x5c, // Output Compare Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TCCR1A: 0x4f, // Timer/Counter1 Control Register A + TCCR1B: 0x4e, // Timer/Counter1 Control Register B + TCNT1L: 0x4c, // Timer/Counter1 Bytes + TCNT1H: 0x4c, // Timer/Counter1 Bytes + OCR1AL: 0x4a, // Timer/Counter1 Output Compare Register Bytes + OCR1AH: 0x4a, // Timer/Counter1 Output Compare Register Bytes + OCR1BL: 0x48, // Timer/Counter1 Output Compare Register Bytes + OCR1BH: 0x48, // Timer/Counter1 Output Compare Register Bytes + ICR1L: 0x46, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x46, // Timer/Counter1 Input Capture Register Bytes + } + + // External Interrupts + EXINT = struct { + GICR __reg + GIFR __reg + }{ + GICR: 0x5b, // General Interrupt Control Register + GIFR: 0x5a, // General Interrupt Flag Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x3e, // EEPROM Address Register Bytes + EEARH: 0x3e, // EEPROM Address Register Bytes + EEDR: 0x3d, // EEPROM Data Register + EECR: 0x3c, // EEPROM Control Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x51, // Oscillator Calibration Value + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2 __reg + TCNT2 __reg + OCR2 __reg + ASSR __reg + }{ + TCCR2: 0x45, // Timer/Counter2 Control Register + TCNT2: 0x44, // Timer/Counter2 + OCR2: 0x43, // Timer/Counter2 Output Compare Register + ASSR: 0x42, // Asynchronous Status Register + } + + // Serial Peripheral Interface + SPI = struct { + SPDR __reg + SPSR __reg + SPCR __reg + }{ + SPDR: 0x2f, // SPI Data Register + SPSR: 0x2e, // SPI Status Register + SPCR: 0x2d, // SPI Control Register + } + + // USART + USART = struct { + UDR __reg + UCSRA __reg + UCSRB __reg + UCSRC __reg + UBRRH __reg + UBRRL __reg + }{ + UDR: 0x2c, // USART I/O Data Register + UCSRA: 0x2b, // USART Control and Status Register A + UCSRB: 0x2a, // USART Control and Status Register B + UCSRC: 0x40, // USART Control and Status Register C + UBRRH: 0x40, // USART Baud Rate Register Hight Byte + UBRRL: 0x29, // USART Baud Rate Register Low Byte + } + + // Two Wire Serial Interface + TWI = struct { + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWBR: 0x20, // TWI Bit Rate register + TWCR: 0x56, // TWI Control Register + TWSR: 0x21, // TWI Status Register + TWDR: 0x23, // TWI Data register + TWAR: 0x22, // TWI (Slave) Address register + } + + // Analog Comparator + AC = struct { + ACSR __reg + }{ + ACSR: 0x28, // Analog Comparator Control And Status Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + }{ + ADMUX: 0x27, // The ADC multiplexer Selection Register + ADCSRA: 0x26, // The ADC Control and Status register + ADCL: 0x24, // ADC Data Register Bytes + ADCH: 0x24, // ADC Data Register Bytes + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + }{ + PORTA: 0x3b, // Port A Data Register + DDRA: 0x3a, // Port A Data Direction Register + PINA: 0x39, // Port A Input Pins + PORTB: 0x38, // Port B Data Register + DDRB: 0x37, // Port B Data Direction Register + PINB: 0x36, // Port B Input Pins + PORTC: 0x35, // Port C Data Register + DDRC: 0x34, // Port C Data Direction Register + PINC: 0x33, // Port C Input Pins + PORTD: 0x32, // Port D Data Register + DDRD: 0x31, // Port D Data Direction Register + PIND: 0x30, // Port D Input Pins + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x41, // Watchdog Timer Control Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + HIGH_CKOPT = 0x10 // CKOPT fuse (operation dependent of CKSEL fuses) + + // LOW + LOW_BODLEVEL = 0x80 // Brownout detector trigger level + LOW_BODEN = 0x40 // Brown-out detection enabled + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0: Timer/Counter Control Register + TCCR0_FOC0 = 0x80 // Force Output Compare + TCCR0_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0_COM0 = 0x30 // Compare Match Output Modes + TCCR0_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0_CS0 = 0x7 // Clock Selects +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_FOC1A = 0x8 // Force Output Compare 1A + TCCR1A_FOC1B = 0x4 // Force Output Compare 1B + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 +) + +// Bitfields for EXINT: External Interrupts +const ( + // GICR: General Interrupt Control Register + GICR_INT0 = 0x40 // External Interrupt Request 0 Enable + GICR_INT1 = 0x80 // External Interrupt Request 1 Enable + GICR_INT2 = 0x20 // External Interrupt Request 2 Enable + GICR_IVSEL = 0x2 // Interrupt Vector Select + GICR_IVCE = 0x1 // Interrupt Vector Change Enable + + // GIFR: General Interrupt Flag Register + GIFR_INTF = 0xc0 // External Interrupt Flags + GIFR_INTF2 = 0x20 // External Interrupt Flag 2 +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2: Timer/Counter2 Control Register + TCCR2_FOC2 = 0x80 // Force Output Compare + TCCR2_WGM20 = 0x40 // Waveform Genration Mode + TCCR2_COM2 = 0x30 // Compare Output Mode bits + TCCR2_WGM21 = 0x8 // Waveform Generation Mode + TCCR2_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_AS2 = 0x8 // Asynchronous Timer/counter2 + ASSR_TCN2UB = 0x4 // Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // Timer/counter Control Register2 Update Busy +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects +) + +// Bitfields for USART: USART +const ( + // UCSRA: USART Control and Status Register A + UCSRA_RXC = 0x80 // USART Receive Complete + UCSRA_TXC = 0x40 // USART Transmitt Complete + UCSRA_UDRE = 0x20 // USART Data Register Empty + UCSRA_FE = 0x10 // Framing Error + UCSRA_DOR = 0x8 // Data overRun + UCSRA_UPE = 0x4 // Parity Error + UCSRA_U2X = 0x2 // Double the USART transmission speed + UCSRA_MPCM = 0x1 // Multi-processor Communication Mode + + // UCSRB: USART Control and Status Register B + UCSRB_RXCIE = 0x80 // RX Complete Interrupt Enable + UCSRB_TXCIE = 0x40 // TX Complete Interrupt Enable + UCSRB_UDRIE = 0x20 // USART Data register Empty Interrupt Enable + UCSRB_RXEN = 0x10 // Receiver Enable + UCSRB_TXEN = 0x8 // Transmitter Enable + UCSRB_UCSZ2 = 0x4 // Character Size + UCSRB_RXB8 = 0x2 // Receive Data Bit 8 + UCSRB_TXB8 = 0x1 // Transmit Data Bit 8 + + // UCSRC: USART Control and Status Register C + UCSRC_URSEL = 0x80 // Register Select + UCSRC_UMSEL = 0x40 // USART Mode Select + UCSRC_UPM = 0x30 // Parity Mode Bits + UCSRC_USBS = 0x8 // Stop Bit Select + UCSRC_UCSZ = 0x6 // Character Size + UCSRC_UCPOL = 0x1 // Clock Polarity +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits +) + +// Bitfields for JTAG: JTAG Interface +const ( + // OCDR: On-Chip Debug Related Register in I/O Memory + OCDR_OCDR = 0xff // On-Chip Debug Register Bits +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDTOE = 0x10 // RW + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) diff --git a/src/device/avr/atmega16.ld b/src/device/avr/atmega16.ld new file mode 100644 index 00000000..a3cd2d77 --- /dev/null +++ b/src/device/avr/atmega16.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega16.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_size = 0x400; +__num_isrs = 21; diff --git a/src/device/avr/atmega162.go b/src/device/avr/atmega162.go new file mode 100644 index 00000000..d53d2936 --- /dev/null +++ b/src/device/avr/atmega162.go @@ -0,0 +1,585 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega162.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega162 + +// Device information for the ATmega162. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega162" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_PCINT0 = 4 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 5 // Pin Change Interrupt Request 1 + IRQ_TIMER3_CAPT = 6 // Timer/Counter3 Capture Event + IRQ_TIMER3_COMPA = 7 // Timer/Counter3 Compare Match A + IRQ_TIMER3_COMPB = 8 // Timer/Counter3 Compare Match B + IRQ_TIMER3_OVF = 9 // Timer/Counter3 Overflow + IRQ_TIMER2_COMP = 10 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 11 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 12 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 13 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 14 // Timer/Counter Compare Match B + IRQ_TIMER1_OVF = 15 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 16 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 17 // Timer/Counter0 Overflow + IRQ_SPI_STC = 18 // SPI Serial Transfer Complete + IRQ_USART0_RXC = 19 // USART0, Rx Complete + IRQ_USART1_RXC = 20 // USART1, Rx Complete + IRQ_USART0_UDRE = 21 // USART0 Data register Empty + IRQ_USART1_UDRE = 22 // USART1, Data register Empty + IRQ_USART0_TXC = 23 // USART0, Tx Complete + IRQ_USART1_TXC = 24 // USART1, Tx Complete + IRQ_EE_RDY = 25 // EEPROM Ready + IRQ_ANA_COMP = 26 // Analog Comparator + IRQ_SPM_RDY = 27 // Store Program Memory Read + IRQ_max = 27 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + ETIMSK __reg + ETIFR __reg + TCCR3A __reg + TCCR3B __reg + TCNT3L __reg + TCNT3H __reg + OCR3AL __reg + OCR3AH __reg + OCR3BL __reg + OCR3BH __reg + ICR3L __reg + ICR3H __reg + }{ + TCCR1A: 0x4f, // Timer/Counter1 Control Register A + TCCR1B: 0x4e, // Timer/Counter1 Control Register B + TCNT1L: 0x4c, // Timer/Counter1 Bytes + TCNT1H: 0x4c, // Timer/Counter1 Bytes + OCR1AL: 0x4a, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x4a, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x48, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x48, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x44, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x44, // Timer/Counter1 Input Capture Register Bytes + ETIMSK: 0x7d, // Extended Timer/Counter Interrupt Mask Register + ETIFR: 0x7c, // Extended Timer/Counter Interrupt Flag register + TCCR3A: 0x8b, // Timer/Counter3 Control Register A + TCCR3B: 0x8a, // Timer/Counter3 Control Register B + TCNT3L: 0x88, // Timer/Counter3 Bytes + TCNT3H: 0x88, // Timer/Counter3 Bytes + OCR3AL: 0x86, // Timer/Counter3 Output Compare Register A Bytes + OCR3AH: 0x86, // Timer/Counter3 Output Compare Register A Bytes + OCR3BL: 0x84, // Timer/Counte3 Output Compare Register B Bytes + OCR3BH: 0x84, // Timer/Counte3 Output Compare Register B Bytes + ICR3L: 0x80, // Timer/Counter3 Input Capture Register Bytes + ICR3H: 0x80, // Timer/Counter3 Input Capture Register Bytes + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2 __reg + TCNT2 __reg + OCR2 __reg + ASSR __reg + }{ + TCCR2: 0x47, // Timer/Counter Control Register + TCNT2: 0x43, // Timer/Counter Register + OCR2: 0x42, // Output Compare Register + ASSR: 0x46, // Asynchronous Status Register + } + + // Analog Comparator + AC = struct { + ACSR __reg + }{ + ACSR: 0x28, // Analog Comparator Control And Status Register + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0H __reg + UBRR0L __reg + UDR1 __reg + UCSR1A __reg + UCSR1B __reg + UCSR1C __reg + UBRR1H __reg + UBRR1L __reg + }{ + UDR0: 0x2c, // USART I/O Data Register + UCSR0A: 0x2b, // USART Control and Status Register A + UCSR0B: 0x2a, // USART Control and Status Register B + UCSR0C: 0x40, // USART Control and Status Register C + UBRR0H: 0x40, // USART Baud Rate Register High Byte + UBRR0L: 0x29, // USART Baud Rate Register Low Byte + UDR1: 0x23, // USART I/O Data Register + UCSR1A: 0x22, // USART Control and Status Register A + UCSR1B: 0x21, // USART Control and Status Register B + UCSR1C: 0x5c, // USART Control and Status Register C + UBRR1H: 0x5c, // USART Baud Rate Register Highg Byte + UBRR1L: 0x20, // USART Baud Rate Register Low Byte + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x2d, // SPI Control Register + SPSR: 0x2e, // SPI Status Register + SPDR: 0x2f, // SPI Data Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + SFIOR __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x24, // Oscillator Calibration Value + CLKPR: 0x61, // Clock prescale register + SFIOR: 0x50, // Special Function IO Register + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x24, // On-Chip Debug Related Register in I/O Memory + } + + // Bootloader + BOOT_LOAD = struct { + SPMCR __reg + }{ + SPMCR: 0x57, // Store Program Memory Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x3e, // EEPROM Address Register Bytes + EEARH: 0x3e, // EEPROM Address Register Bytes + EEDR: 0x3d, // EEPROM Data Register + EECR: 0x3c, // EEPROM Control Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + }{ + PORTA: 0x3b, // Port A Data Register + DDRA: 0x3a, // Port A Data Direction Register + PINA: 0x39, // Port A Input Pins + PORTB: 0x38, // Port B Data Register + DDRB: 0x37, // Port B Data Direction Register + PINB: 0x36, // Port B Input Pins + PORTC: 0x35, // Port C Data Register + DDRC: 0x34, // Port C Data Direction Register + PINC: 0x33, // Port C Input Pins + PORTD: 0x32, // Port D Data Register + DDRD: 0x31, // Port D Data Direction Register + PIND: 0x30, // Port D Input Pins + PORTE: 0x27, // Data Register, Port E + DDRE: 0x26, // Data Direction Register, Port E + PINE: 0x25, // Input Pins, Port E + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0 __reg + TCNT0 __reg + OCR0 __reg + }{ + TCCR0: 0x53, // Timer/Counter 0 Control Register + TCNT0: 0x52, // Timer/Counter 0 Register + OCR0: 0x51, // Timer/Counter 0 Output Compare Register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x41, // Watchdog Timer Control Register + } + + // External Interrupts + EXINT = struct { + GICR __reg + GIFR __reg + PCMSK1 __reg + PCMSK0 __reg + }{ + GICR: 0x5b, // General Interrupt Control Register + GIFR: 0x5a, // General Interrupt Flag Register + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Enable Mask + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_M161C = 0x10 // ATmega161 compability mode + EXTENDED_BODLEVEL = 0xe // Brownout detector trigger level + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTB0 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_FOC1A = 0x8 // Force Output Compare for Channel A + TCCR1A_FOC1B = 0x4 // Force Output Compare for Channel B + TCCR1A_WGM1 = 0x3 // Pulse Width Modulator Select Bits + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Pulse Width Modulator Select Bits + TCCR1B_CS1 = 0x7 // Clock Select1 bits + + // ETIMSK: Extended Timer/Counter Interrupt Mask Register + ETIMSK_TICIE3 = 0x20 // Timer/Counter3 Input Capture Interrupt Enable + ETIMSK_OCIE3A = 0x10 // Timer/Counter3 Output CompareA Match Interrupt Enable + ETIMSK_OCIE3B = 0x8 // Timer/Counter3 Output CompareB Match Interrupt Enable + ETIMSK_TOIE3 = 0x4 // Timer/Counter3 Overflow Interrupt Enable + + // ETIFR: Extended Timer/Counter Interrupt Flag register + ETIFR_ICF3 = 0x20 // Input Capture Flag 3 + ETIFR_OCF3A = 0x10 // Output Compare Flag 3A + ETIFR_OCF3B = 0x8 // Output Compare Flag 3B + ETIFR_TOV3 = 0x4 // Timer/Counter3 Overflow Flag + + // TCCR3A: Timer/Counter3 Control Register A + TCCR3A_COM3A = 0xc0 // Compare Output Mode 3A, bits + TCCR3A_COM3B = 0x30 // Compare Output Mode 3B, bits + TCCR3A_FOC3A = 0x8 // Force Output Compare for Channel A + TCCR3A_FOC3B = 0x4 // Force Output Compare for Channel B + TCCR3A_WGM3 = 0x3 // Pulse Width Modulator Select Bits + + // TCCR3B: Timer/Counter3 Control Register B + TCCR3B_ICNC3 = 0x80 // Input Capture 3 Noise Canceler + TCCR3B_ICES3 = 0x40 // Input Capture 3 Edge Select + TCCR3B_WGM3 = 0x18 // Pulse Width Modulator Select Bits + TCCR3B_CS3 = 0x7 // Clock Select3 bits +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2: Timer/Counter Control Register + TCCR2_FOC2 = 0x80 // Forde Output Compare + TCCR2_WGM20 = 0x40 // Pulse Width Modulator Select Bit 0 + TCCR2_COM2 = 0x30 // Compare Match Output Mode + TCCR2_WGM21 = 0x8 // Pulse Width Modulator Select Bit 1 + TCCR2_CS2 = 0x7 // Clock Select + + // ASSR: Asynchronous Status Register + ASSR_AS2 = 0x8 // Asynchronous Timer 2 + ASSR_TCN2UB = 0x4 // Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // Timer/Counter Control Register2 Update Busy +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_URSEL0 = 0x80 // Register Select + UCSR0C_UMSEL0 = 0x40 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity + + // UBRR0H: USART Baud Rate Register High Byte + UBRR0H_URSEL0 = 0x80 // Register Select + UBRR0H_UBRR0 = 0xf // USART Baud Rate Register High bits + + // UBRR0L: USART Baud Rate Register Low Byte + UBRR0L_UBRR0 = 0xff // USART Baud Rate Register Low bits + + // UCSR1A: USART Control and Status Register A + UCSR1A_RXC1 = 0x80 // USART Receive Complete + UCSR1A_TXC1 = 0x40 // USART Transmitt Complete + UCSR1A_UDRE1 = 0x20 // USART Data Register Empty + UCSR1A_FE1 = 0x10 // Framing Error + UCSR1A_DOR1 = 0x8 // Data overRun + UCSR1A_UPE1 = 0x4 // Parity Error + UCSR1A_U2X1 = 0x2 // Double the USART transmission speed + UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode + + // UCSR1B: USART Control and Status Register B + UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable + UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable + UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable + UCSR1B_RXEN1 = 0x10 // Receiver Enable + UCSR1B_TXEN1 = 0x8 // Transmitter Enable + UCSR1B_UCSZ12 = 0x4 // Character Size + UCSR1B_RXB81 = 0x2 // Receive Data Bit 8 + UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8 + + // UCSR1C: USART Control and Status Register C + UCSR1C_URSEL1 = 0x80 // Register Select + UCSR1C_UMSEL1 = 0x40 // USART Mode Select + UCSR1C_UPM1 = 0x30 // Parity Mode Bits + UCSR1C_USBS1 = 0x8 // Stop Bit Select + UCSR1C_UCSZ1 = 0x6 // Character Size + UCSR1C_UCPOL1 = 0x1 // Clock Polarity + + // UBRR1H: USART Baud Rate Register Highg Byte + UBRR1H_URSEL0 = 0x80 // Register Select + UBRR1H_UBRR1 = 0xf // USART Baud Rate Register High bits + + // UBRR1L: USART Baud Rate Register Low Byte + UBRR1L_UBRR1 = 0xff // USART Baud Rate Register Low bits +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock prescale register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // SFIOR: Special Function IO Register + SFIOR_TSM = 0x80 // Timer/Counter Synchronization Mode + SFIOR_XMBK = 0x40 // External Memory Bus Keeper Enable + SFIOR_XMM = 0x38 // External Memory High Mask Bits + SFIOR_PUD = 0x4 // Pull-up Disable + SFIOR_PSR2 = 0x2 // Prescaler Reset Timer/Counter2 + SFIOR_PSR310 = 0x1 // Prescaler Reset Timer/Counter3, Timer/Counter1 and Timer/Counter0 +) + +// Bitfields for JTAG: JTAG Interface +const ( + // OCDR: On-Chip Debug Related Register in I/O Memory + OCDR_OCDR = 0xff // On-Chip Debug Register Bits +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCR: Store Program Memory Control Register + SPMCR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCR_RWWSB = 0x40 // Read While Write Section Busy + SPMCR_RWWSRE = 0x10 // Read While Write secion read enable + SPMCR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCR_PGWRT = 0x4 // Page Write + SPMCR_PGERS = 0x2 // Page Erase + SPMCR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for EEPROM: EEPROM +const ( + // EEARL: EEPROM Address Register Bytes + + // EEARH: EEPROM Address Register Bytes + EEAR_EEAR = 0x1ff // EEPROM Address Register bits + + // EEDR: EEPROM Data Register + EEDR_EEDR = 0xff // EEPROM Data Register bits + + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0: Timer/Counter 0 Control Register + TCCR0_FOC0 = 0x80 // Force Output Compare + TCCR0_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0_COM0 = 0x30 // Compare Match Output Modes + TCCR0_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0_CS0 = 0x7 // Clock Selects +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for EXINT: External Interrupts +const ( + // GICR: General Interrupt Control Register + GICR_INT0 = 0x40 // External Interrupt Request 0 Enable + GICR_INT1 = 0x80 // External Interrupt Request 1 Enable + GICR_INT2 = 0x20 // External Interrupt Request 2 Enable + GICR_PCIE = 0x18 // Pin Change Interrupt Enables + GICR_IVSEL = 0x2 // Interrupt Vector Select + GICR_IVCE = 0x1 // Interrupt Vector Change Enable + + // GIFR: General Interrupt Flag Register + GIFR_INTF = 0xc0 // External Interrupt Flags + GIFR_INTF2 = 0x20 // External Interrupt Flag 2 + GIFR_PCIF = 0x18 // Pin Change Interrupt Flags + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Interrupt mask bits + + // PCMSK0: Pin Change Enable Mask + PCMSK0_PCINT = 0xff // Pin Change Interrupt mask bits +) diff --git a/src/device/avr/atmega162.ld b/src/device/avr/atmega162.ld new file mode 100644 index 00000000..5e5a3fae --- /dev/null +++ b/src/device/avr/atmega162.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega162.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_size = 0x400; +__num_isrs = 28; diff --git a/src/device/avr/atmega164a.go b/src/device/avr/atmega164a.go new file mode 100644 index 00000000..5a6ab4d5 --- /dev/null +++ b/src/device/avr/atmega164a.go @@ -0,0 +1,711 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega164A.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega164a + +// Device information for the ATmega164A. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega164A" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_PCINT0 = 4 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 5 // Pin Change Interrupt Request 1 + IRQ_PCINT2 = 6 // Pin Change Interrupt Request 2 + IRQ_PCINT3 = 7 // Pin Change Interrupt Request 3 + IRQ_WDT = 8 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 9 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 10 // Timer/Counter2 Compare Match B + IRQ_TIMER2_OVF = 11 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 12 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 13 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 14 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 15 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 16 // Timer/Counter0 Compare Match A + IRQ_TIMER0_COMPB = 17 // Timer/Counter0 Compare Match B + IRQ_TIMER0_OVF = 18 // Timer/Counter0 Overflow + IRQ_SPI_STC = 19 // SPI Serial Transfer Complete + IRQ_USART0_RX = 20 // USART0, Rx Complete + IRQ_USART0_UDRE = 21 // USART0 Data register Empty + IRQ_USART0_TX = 22 // USART0, Tx Complete + IRQ_ANALOG_COMP = 23 // Analog Comparator + IRQ_ADC = 24 // ADC Conversion Complete + IRQ_EE_READY = 25 // EEPROM Ready + IRQ_TWI = 26 // 2-wire Serial Interface + IRQ_SPM_READY = 27 // Store Program Memory Read + IRQ_USART1_RX = 28 // USART1 RX complete + IRQ_USART1_UDRE = 29 // USART1 Data Register Empty + IRQ_USART1_TX = 30 // USART1 TX complete + IRQ_max = 30 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + UDR1 __reg + UCSR1A __reg + UCSR1B __reg + UCSR1C __reg + UBRR1L __reg + UBRR1H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + UDR1: 0xce, // USART I/O Data Register + UCSR1A: 0xc8, // USART Control and Status Register A + UCSR1B: 0xc9, // USART Control and Status Register B + UCSR1C: 0xca, // USART Control and Status Register C + UBRR1L: 0xcc, // USART Baud Rate Register Bytes + UBRR1H: 0xcc, // USART Baud Rate Register Bytes + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK3 __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + PCICR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK3: 0x73, // Pin Change Mask Register 3 + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // The ADC Control and Status register A + DIDR0: 0x7e, // Digital Input Disable Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Low Bytes + EEARH: 0x41, // EEPROM Address Register Low Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Serial Peripheral Interface + SPI = struct { + SPDR0 __reg + SPSR0 __reg + SPCR0 __reg + }{ + SPDR0: 0x4e, // SPI Data Register + SPSR0: 0x4d, // SPI Status Register + SPCR0: 0x4c, // SPI Control Register + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PRR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PRR0: 0x64, // Power Reduction Register0 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTB1 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0xc0 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity + + // UCSR1A: USART Control and Status Register A + UCSR1A_RXC1 = 0x80 // USART Receive Complete + UCSR1A_TXC1 = 0x40 // USART Transmitt Complete + UCSR1A_UDRE1 = 0x20 // USART Data Register Empty + UCSR1A_FE1 = 0x10 // Framing Error + UCSR1A_DOR1 = 0x8 // Data overRun + UCSR1A_UPE1 = 0x4 // Parity Error + UCSR1A_U2X1 = 0x2 // Double the USART transmission speed + UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode + + // UCSR1B: USART Control and Status Register B + UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable + UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable + UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable + UCSR1B_RXEN1 = 0x10 // Receiver Enable + UCSR1B_TXEN1 = 0x8 // Transmitter Enable + UCSR1B_UCSZ12 = 0x4 // Character Size + UCSR1B_RXB81 = 0x2 // Receive Data Bit 8 + UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8 + + // UCSR1C: USART Control and Status Register C + UCSR1C_UMSEL1 = 0xc0 // USART Mode Select + UCSR1C_UPM1 = 0x30 // Parity Mode Bits + UCSR1C_USBS1 = 0x8 // Stop Bit Select + UCSR1C_UCSZ1 = 0x6 // Character Size + UCSR1C_UCPOL1 = 0x1 // Clock Polarity +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2B = 0x4 // Output Compare Flag 2B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Output Mode bits + TCCR2A_COM2B = 0x30 // Compare Output Mode bits + TCCR2A_WGM2 = 0x3 // Waveform Genration Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy + ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0x7 // External Interrupt Request 2 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0x7 // External Interrupt Flags + + // PCMSK3: Pin Change Mask Register 3 + PCMSK3_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0xf // Pin Change Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0xf // Pin Change Interrupt Enables +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register + DIDR0_ADC7D = 0x80 + DIDR0_ADC6D = 0x40 + DIDR0_ADC5D = 0x20 + DIDR0_ADC4D = 0x10 + DIDR0_ADC3D = 0x8 + DIDR0_ADC2D = 0x4 + DIDR0_ADC1D = 0x2 + DIDR0_ADC0D = 0x1 +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Timer/Counter1 Input Capture Flag + TIFR1_OCF1B = 0x4 // Timer/Counter1 Output Compare B Match Flag + TIFR1_OCF1A = 0x2 // Timer/Counter1 Output Compare A Match Flag + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Pulse Width Modulator Select Bits + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode Bits + TCCR1B_CS1 = 0x7 // Clock Select1 bits + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare for Channel A + TCCR1C_FOC1B = 0x40 // Force Output Compare for Channel B +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPSR0: SPI Status Register + SPSR0_SPIF0 = 0x80 // SPI Interrupt Flag + SPSR0_WCOL0 = 0x40 // Write Collision Flag + SPSR0_SPI2X0 = 0x1 // Double SPI Speed Bit + + // SPCR0: SPI Control Register + SPCR0_SPIE0 = 0x80 // SPI Interrupt Enable + SPCR0_SPE0 = 0x40 // SPI Enable + SPCR0_DORD0 = 0x20 // Data Order + SPCR0_MSTR0 = 0x10 // Master/Slave Select + SPCR0_CPOL0 = 0x8 // Clock polarity + SPCR0_CPHA0 = 0x4 // Clock Phase + SPCR0_SPR01 = 0x2 // SPI Clock Rate Select 1 + SPCR0_SPR00 = 0x1 // SPI Clock Rate Select 0 +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 + + // PRR0: Power Reduction Register0 + PRR0_PRTWI = 0x80 // Power Reduction TWI + PRR0_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR0_PRUSART1 = 0x10 // Power Reduction USART1 + PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR0_PRUSART0 = 0x2 // Power Reduction USART0 + PRR0_PRADC = 0x1 // Power Reduction ADC +) diff --git a/src/device/avr/atmega164a.ld b/src/device/avr/atmega164a.ld new file mode 100644 index 00000000..639194b4 --- /dev/null +++ b/src/device/avr/atmega164a.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega164A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_size = 0x400; +__num_isrs = 31; diff --git a/src/device/avr/atmega164p.go b/src/device/avr/atmega164p.go new file mode 100644 index 00000000..8cde311b --- /dev/null +++ b/src/device/avr/atmega164p.go @@ -0,0 +1,711 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega164P.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega164p + +// Device information for the ATmega164P. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega164P" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_PCINT0 = 4 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 5 // Pin Change Interrupt Request 1 + IRQ_PCINT2 = 6 // Pin Change Interrupt Request 2 + IRQ_PCINT3 = 7 // Pin Change Interrupt Request 3 + IRQ_WDT = 8 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 9 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 10 // Timer/Counter2 Compare Match B + IRQ_TIMER2_OVF = 11 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 12 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 13 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 14 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 15 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 16 // Timer/Counter0 Compare Match A + IRQ_TIMER0_COMPB = 17 // Timer/Counter0 Compare Match B + IRQ_TIMER0_OVF = 18 // Timer/Counter0 Overflow + IRQ_SPI_STC = 19 // SPI Serial Transfer Complete + IRQ_USART0_RX = 20 // USART0, Rx Complete + IRQ_USART0_UDRE = 21 // USART0 Data register Empty + IRQ_USART0_TX = 22 // USART0, Tx Complete + IRQ_ANALOG_COMP = 23 // Analog Comparator + IRQ_ADC = 24 // ADC Conversion Complete + IRQ_EE_READY = 25 // EEPROM Ready + IRQ_TWI = 26 // 2-wire Serial Interface + IRQ_SPM_READY = 27 // Store Program Memory Read + IRQ_USART1_RX = 28 // USART1 RX complete + IRQ_USART1_UDRE = 29 // USART1 Data Register Empty + IRQ_USART1_TX = 30 // USART1 TX complete + IRQ_max = 30 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + UDR1 __reg + UCSR1A __reg + UCSR1B __reg + UCSR1C __reg + UBRR1L __reg + UBRR1H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + UDR1: 0xce, // USART I/O Data Register + UCSR1A: 0xc8, // USART Control and Status Register A + UCSR1B: 0xc9, // USART Control and Status Register B + UCSR1C: 0xca, // USART Control and Status Register C + UBRR1L: 0xcc, // USART Baud Rate Register Bytes + UBRR1H: 0xcc, // USART Baud Rate Register Bytes + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK3 __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + PCICR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK3: 0x73, // Pin Change Mask Register 3 + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // The ADC Control and Status register A + DIDR0: 0x7e, // Digital Input Disable Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Low Bytes + EEARH: 0x41, // EEPROM Address Register Low Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Serial Peripheral Interface + SPI = struct { + SPDR0 __reg + SPSR0 __reg + SPCR0 __reg + }{ + SPDR0: 0x4e, // SPI Data Register + SPSR0: 0x4d, // SPI Status Register + SPCR0: 0x4c, // SPI Control Register + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PRR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PRR0: 0x64, // Power Reduction Register0 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTB1 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0xc0 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity + + // UCSR1A: USART Control and Status Register A + UCSR1A_RXC1 = 0x80 // USART Receive Complete + UCSR1A_TXC1 = 0x40 // USART Transmitt Complete + UCSR1A_UDRE1 = 0x20 // USART Data Register Empty + UCSR1A_FE1 = 0x10 // Framing Error + UCSR1A_DOR1 = 0x8 // Data overRun + UCSR1A_UPE1 = 0x4 // Parity Error + UCSR1A_U2X1 = 0x2 // Double the USART transmission speed + UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode + + // UCSR1B: USART Control and Status Register B + UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable + UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable + UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable + UCSR1B_RXEN1 = 0x10 // Receiver Enable + UCSR1B_TXEN1 = 0x8 // Transmitter Enable + UCSR1B_UCSZ12 = 0x4 // Character Size + UCSR1B_RXB81 = 0x2 // Receive Data Bit 8 + UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8 + + // UCSR1C: USART Control and Status Register C + UCSR1C_UMSEL1 = 0xc0 // USART Mode Select + UCSR1C_UPM1 = 0x30 // Parity Mode Bits + UCSR1C_USBS1 = 0x8 // Stop Bit Select + UCSR1C_UCSZ1 = 0x6 // Character Size + UCSR1C_UCPOL1 = 0x1 // Clock Polarity +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2B = 0x4 // Output Compare Flag 2B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Output Mode bits + TCCR2A_COM2B = 0x30 // Compare Output Mode bits + TCCR2A_WGM2 = 0x3 // Waveform Genration Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy + ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0x7 // External Interrupt Request 2 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0x7 // External Interrupt Flags + + // PCMSK3: Pin Change Mask Register 3 + PCMSK3_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0xf // Pin Change Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0xf // Pin Change Interrupt Enables +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register + DIDR0_ADC7D = 0x80 + DIDR0_ADC6D = 0x40 + DIDR0_ADC5D = 0x20 + DIDR0_ADC4D = 0x10 + DIDR0_ADC3D = 0x8 + DIDR0_ADC2D = 0x4 + DIDR0_ADC1D = 0x2 + DIDR0_ADC0D = 0x1 +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Timer/Counter1 Input Capture Flag + TIFR1_OCF1B = 0x4 // Timer/Counter1 Output Compare B Match Flag + TIFR1_OCF1A = 0x2 // Timer/Counter1 Output Compare A Match Flag + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Pulse Width Modulator Select Bits + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode Bits + TCCR1B_CS1 = 0x7 // Clock Select1 bits + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare for Channel A + TCCR1C_FOC1B = 0x40 // Force Output Compare for Channel B +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPSR0: SPI Status Register + SPSR0_SPIF0 = 0x80 // SPI Interrupt Flag + SPSR0_WCOL0 = 0x40 // Write Collision Flag + SPSR0_SPI2X0 = 0x1 // Double SPI Speed Bit + + // SPCR0: SPI Control Register + SPCR0_SPIE0 = 0x80 // SPI Interrupt Enable + SPCR0_SPE0 = 0x40 // SPI Enable + SPCR0_DORD0 = 0x20 // Data Order + SPCR0_MSTR0 = 0x10 // Master/Slave Select + SPCR0_CPOL0 = 0x8 // Clock polarity + SPCR0_CPHA0 = 0x4 // Clock Phase + SPCR0_SPR10 = 0x2 // SPI Clock Rate Select 1 + SPCR0_SPR00 = 0x1 // SPI Clock Rate Select 0 +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 + + // PRR0: Power Reduction Register0 + PRR0_PRTWI = 0x80 // Power Reduction TWI + PRR0_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR0_PRUSART1 = 0x10 // Power Reduction USART1 + PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR0_PRUSART0 = 0x2 // Power Reduction USART0 + PRR0_PRADC = 0x1 // Power Reduction ADC +) diff --git a/src/device/avr/atmega164p.ld b/src/device/avr/atmega164p.ld new file mode 100644 index 00000000..15160294 --- /dev/null +++ b/src/device/avr/atmega164p.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega164P.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_size = 0x400; +__num_isrs = 31; diff --git a/src/device/avr/atmega164pa.go b/src/device/avr/atmega164pa.go new file mode 100644 index 00000000..d6f73164 --- /dev/null +++ b/src/device/avr/atmega164pa.go @@ -0,0 +1,711 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega164PA.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega164pa + +// Device information for the ATmega164PA. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega164PA" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_PCINT0 = 4 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 5 // Pin Change Interrupt Request 1 + IRQ_PCINT2 = 6 // Pin Change Interrupt Request 2 + IRQ_PCINT3 = 7 // Pin Change Interrupt Request 3 + IRQ_WDT = 8 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 9 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 10 // Timer/Counter2 Compare Match B + IRQ_TIMER2_OVF = 11 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 12 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 13 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 14 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 15 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 16 // Timer/Counter0 Compare Match A + IRQ_TIMER0_COMPB = 17 // Timer/Counter0 Compare Match B + IRQ_TIMER0_OVF = 18 // Timer/Counter0 Overflow + IRQ_SPI_STC = 19 // SPI Serial Transfer Complete + IRQ_USART0_RX = 20 // USART0, Rx Complete + IRQ_USART0_UDRE = 21 // USART0 Data register Empty + IRQ_USART0_TX = 22 // USART0, Tx Complete + IRQ_ANALOG_COMP = 23 // Analog Comparator + IRQ_ADC = 24 // ADC Conversion Complete + IRQ_EE_READY = 25 // EEPROM Ready + IRQ_TWI = 26 // 2-wire Serial Interface + IRQ_SPM_READY = 27 // Store Program Memory Read + IRQ_USART1_RX = 28 // USART1 RX complete + IRQ_USART1_UDRE = 29 // USART1 Data Register Empty + IRQ_USART1_TX = 30 // USART1 TX complete + IRQ_max = 30 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + UDR1 __reg + UCSR1A __reg + UCSR1B __reg + UCSR1C __reg + UBRR1L __reg + UBRR1H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + UDR1: 0xce, // USART I/O Data Register + UCSR1A: 0xc8, // USART Control and Status Register A + UCSR1B: 0xc9, // USART Control and Status Register B + UCSR1C: 0xca, // USART Control and Status Register C + UBRR1L: 0xcc, // USART Baud Rate Register Bytes + UBRR1H: 0xcc, // USART Baud Rate Register Bytes + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK3 __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + PCICR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK3: 0x73, // Pin Change Mask Register 3 + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // The ADC Control and Status register A + DIDR0: 0x7e, // Digital Input Disable Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Low Bytes + EEARH: 0x41, // EEPROM Address Register Low Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Serial Peripheral Interface + SPI = struct { + SPDR0 __reg + SPSR0 __reg + SPCR0 __reg + }{ + SPDR0: 0x4e, // SPI Data Register + SPSR0: 0x4d, // SPI Status Register + SPCR0: 0x4c, // SPI Control Register + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PRR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PRR0: 0x64, // Power Reduction Register0 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTB1 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0xc0 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity + + // UCSR1A: USART Control and Status Register A + UCSR1A_RXC1 = 0x80 // USART Receive Complete + UCSR1A_TXC1 = 0x40 // USART Transmitt Complete + UCSR1A_UDRE1 = 0x20 // USART Data Register Empty + UCSR1A_FE1 = 0x10 // Framing Error + UCSR1A_DOR1 = 0x8 // Data overRun + UCSR1A_UPE1 = 0x4 // Parity Error + UCSR1A_U2X1 = 0x2 // Double the USART transmission speed + UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode + + // UCSR1B: USART Control and Status Register B + UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable + UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable + UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable + UCSR1B_RXEN1 = 0x10 // Receiver Enable + UCSR1B_TXEN1 = 0x8 // Transmitter Enable + UCSR1B_UCSZ12 = 0x4 // Character Size + UCSR1B_RXB81 = 0x2 // Receive Data Bit 8 + UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8 + + // UCSR1C: USART Control and Status Register C + UCSR1C_UMSEL1 = 0xc0 // USART Mode Select + UCSR1C_UPM1 = 0x30 // Parity Mode Bits + UCSR1C_USBS1 = 0x8 // Stop Bit Select + UCSR1C_UCSZ1 = 0x6 // Character Size + UCSR1C_UCPOL1 = 0x1 // Clock Polarity +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2B = 0x4 // Output Compare Flag 2B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Output Mode bits + TCCR2A_COM2B = 0x30 // Compare Output Mode bits + TCCR2A_WGM2 = 0x3 // Waveform Genration Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy + ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0x7 // External Interrupt Request 2 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0x7 // External Interrupt Flags + + // PCMSK3: Pin Change Mask Register 3 + PCMSK3_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0xf // Pin Change Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0xf // Pin Change Interrupt Enables +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register + DIDR0_ADC7D = 0x80 + DIDR0_ADC6D = 0x40 + DIDR0_ADC5D = 0x20 + DIDR0_ADC4D = 0x10 + DIDR0_ADC3D = 0x8 + DIDR0_ADC2D = 0x4 + DIDR0_ADC1D = 0x2 + DIDR0_ADC0D = 0x1 +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Timer/Counter1 Input Capture Flag + TIFR1_OCF1B = 0x4 // Timer/Counter1 Output Compare B Match Flag + TIFR1_OCF1A = 0x2 // Timer/Counter1 Output Compare A Match Flag + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Pulse Width Modulator Select Bits + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode Bits + TCCR1B_CS1 = 0x7 // Clock Select1 bits + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare for Channel A + TCCR1C_FOC1B = 0x40 // Force Output Compare for Channel B +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPSR0: SPI Status Register + SPSR0_SPIF0 = 0x80 // SPI Interrupt Flag + SPSR0_WCOL0 = 0x40 // Write Collision Flag + SPSR0_SPI2X0 = 0x1 // Double SPI Speed Bit + + // SPCR0: SPI Control Register + SPCR0_SPIE0 = 0x80 // SPI Interrupt Enable + SPCR0_SPE0 = 0x40 // SPI Enable + SPCR0_DORD0 = 0x20 // Data Order + SPCR0_MSTR0 = 0x10 // Master/Slave Select + SPCR0_CPOL0 = 0x8 // Clock polarity + SPCR0_CPHA0 = 0x4 // Clock Phase + SPCR0_SPR10 = 0x2 // SPI Clock Rate Select 1 + SPCR0_SPR00 = 0x1 // SPI Clock Rate Select 0 +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 + + // PRR0: Power Reduction Register0 + PRR0_PRTWI = 0x80 // Power Reduction TWI + PRR0_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR0_PRUSART1 = 0x10 // Power Reduction USART1 + PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR0_PRUSART0 = 0x2 // Power Reduction USART0 + PRR0_PRADC = 0x1 // Power Reduction ADC +) diff --git a/src/device/avr/atmega164pa.ld b/src/device/avr/atmega164pa.ld new file mode 100644 index 00000000..51783d80 --- /dev/null +++ b/src/device/avr/atmega164pa.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega164PA.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_size = 0x400; +__num_isrs = 31; diff --git a/src/device/avr/atmega165a.go b/src/device/avr/atmega165a.go new file mode 100644 index 00000000..e1f0e4ca --- /dev/null +++ b/src/device/avr/atmega165a.go @@ -0,0 +1,605 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega165A.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega165a + +// Device information for the ATmega165A. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega165A" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_PCINT0 = 2 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 3 // Pin Change Interrupt Request 1 + IRQ_TIMER2_COMP = 4 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 5 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 6 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 7 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 8 // Timer/Counter Compare Match B + IRQ_TIMER1_OVF = 9 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 10 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 11 // Timer/Counter0 Overflow + IRQ_SPI_STC = 12 // SPI Serial Transfer Complete + IRQ_USART0_RX = 13 // USART0, Rx Complete + IRQ_USART0_UDRE = 14 // USART0 Data register Empty + IRQ_USART0_TX = 15 // USART0, Tx Complete + IRQ_USI_START = 16 // USI Start Condition + IRQ_USI_OVERFLOW = 17 // USI Overflow + IRQ_ANALOG_COMP = 18 // Analog Comparator + IRQ_ADC = 19 // ADC Conversion Complete + IRQ_EE_READY = 20 // EEPROM Ready + IRQ_SPM_READY = 21 // Store Program Memory Read + IRQ_max = 21 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0A __reg + TCNT0 __reg + OCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR0A: 0x44, // Timer/Counter0 Control Register + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2A __reg + TCNT2 __reg + OCR2A __reg + TIMSK2 __reg + TIFR2 __reg + ASSR __reg + }{ + TCCR2A: 0xb0, // Timer/Counter2 Control Register + TCNT2: 0xb2, // Timer/Counter2 + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register + TIMSK2: 0x70, // Timer/Counter2 Interrupt Mask register + TIFR2: 0x37, // Timer/Counter2 Interrupt Flag Register + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x60, // Watchdog Timer Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Bytes + EEARH: 0x41, // EEPROM Address Register Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + PORTG: 0x34, // Port G Data Register + DDRG: 0x33, // Port G Data Direction Register + PING: 0x32, // Port G Input Pins + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // Universal Serial Interface + USI = struct { + USIDR __reg + USISR __reg + USICR __reg + }{ + USIDR: 0xba, // USI Data Register + USISR: 0xb9, // USI Status Register + USICR: 0xb8, // USI Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 0 + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK1 __reg + PCMSK0 __reg + }{ + EICRA: 0x69, // External Interrupt Control Register + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + PRR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + PRR: 0x64, // Power Reduction Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0xe // Brown-out Detector trigger level + EXTENDED_RSTDISBL = 0x1 // Disable external reset + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0A: Timer/Counter0 Control Register + TCCR0A_FOC0A = 0x80 // Force Output Compare + TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0A_COM0A = 0x30 // Compare Match Output Modes + TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0A_CS0 = 0x7 // Clock Selects + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0 + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2A: Timer/Counter2 Control Register + TCCR2A_FOC2A = 0x80 // Force Output Compare A + TCCR2A_WGM20 = 0x40 // Waveform Generation Mode + TCCR2A_COM2A = 0x30 // Compare Output Mode bits + TCCR2A_WGM21 = 0x8 // Waveform Generation Mode + TCCR2A_CS2 = 0x7 // Clock Select bits + + // TIMSK2: Timer/Counter2 Interrupt Mask register + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter2 Interrupt Flag Register + TIFR2_OCF2A = 0x2 // Timer/Counter2 Output Compare Flag 2 + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x10 // Enable External Clock Interrupt + ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for USI: Universal Serial Interface +const ( + // USISR: USI Status Register + USISR_USISIF = 0x80 // Start Condition Interrupt Flag + USISR_USIOIF = 0x40 // Counter Overflow Interrupt Flag + USISR_USIPF = 0x20 // Stop Condition Flag + USISR_USIDC = 0x10 // Data Output Collision + USISR_USICNT = 0xf // USI Counter Value Bits + + // USICR: USI Control Register + USICR_USISIE = 0x80 // Start Condition Interrupt Enable + USICR_USIOIE = 0x40 // Counter Overflow Interrupt Enable + USICR_USIWM = 0x30 // USI Wire Mode Bits + USICR_USICS = 0xc // USI Clock Source Select Bits + USICR_USICLK = 0x2 // Clock Strobe + USICR_USITC = 0x1 // Toggle Clock Port Pin +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmit Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data OverRun + UCSR0A_UPE0 = 0x4 // USART Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART Transmission Speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data Register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0x40 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register + EICRA_ISC01 = 0x2 // External Interrupt Sense Control 0 Bit 1 + EICRA_ISC00 = 0x1 // External Interrupt Sense Control 0 Bit 0 + + // EIMSK: External Interrupt Mask Register + EIMSK_PCIE = 0x30 // Pin Change Interrupt Enables + EIMSK_INT0 = 0x1 // External Interrupt Request 0 Enable + + // EIFR: External Interrupt Flag Register + EIFR_PCIF = 0x30 // Pin Change Interrupt Flags + EIFR_INTF0 = 0x1 // External Interrupt Flag 0 + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // PRR: Power Reduction Register + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable +) diff --git a/src/device/avr/atmega165a.ld b/src/device/avr/atmega165a.ld new file mode 100644 index 00000000..b3f3bb7e --- /dev/null +++ b/src/device/avr/atmega165a.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega165A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_size = 0x400; +__num_isrs = 22; diff --git a/src/device/avr/atmega165p.go b/src/device/avr/atmega165p.go new file mode 100644 index 00000000..7af1d4a5 --- /dev/null +++ b/src/device/avr/atmega165p.go @@ -0,0 +1,605 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega165P.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega165p + +// Device information for the ATmega165P. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega165P" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_PCINT0 = 2 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 3 // Pin Change Interrupt Request 1 + IRQ_TIMER2_COMP = 4 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 5 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 6 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 7 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 8 // Timer/Counter Compare Match B + IRQ_TIMER1_OVF = 9 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 10 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 11 // Timer/Counter0 Overflow + IRQ_SPI_STC = 12 // SPI Serial Transfer Complete + IRQ_USART0_RX = 13 // USART0, Rx Complete + IRQ_USART0_UDRE = 14 // USART0 Data register Empty + IRQ_USART0_TX = 15 // USART0, Tx Complete + IRQ_USI_START = 16 // USI Start Condition + IRQ_USI_OVERFLOW = 17 // USI Overflow + IRQ_ANALOG_COMP = 18 // Analog Comparator + IRQ_ADC = 19 // ADC Conversion Complete + IRQ_EE_READY = 20 // EEPROM Ready + IRQ_SPM_READY = 21 // Store Program Memory Read + IRQ_max = 21 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0A __reg + TCNT0 __reg + OCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR0A: 0x44, // Timer/Counter0 Control Register + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2A __reg + TCNT2 __reg + OCR2A __reg + TIMSK2 __reg + TIFR2 __reg + ASSR __reg + }{ + TCCR2A: 0xb0, // Timer/Counter2 Control Register + TCNT2: 0xb2, // Timer/Counter2 + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register + TIMSK2: 0x70, // Timer/Counter2 Interrupt Mask register + TIFR2: 0x37, // Timer/Counter2 Interrupt Flag Register + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x60, // Watchdog Timer Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Bytes + EEARH: 0x41, // EEPROM Address Register Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + PORTG: 0x34, // Port G Data Register + DDRG: 0x33, // Port G Data Direction Register + PING: 0x32, // Port G Input Pins + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK1 __reg + PCMSK0 __reg + }{ + EICRA: 0x69, // External Interrupt Control Register + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + } + + // Universal Serial Interface + USI = struct { + USIDR __reg + USISR __reg + USICR __reg + }{ + USIDR: 0xba, // USI Data Register + USISR: 0xb9, // USI Status Register + USICR: 0xb8, // USI Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 0 + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + PRR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + PRR: 0x64, // Power Reduction Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0xe // Brown-out Detector trigger level + EXTENDED_RSTDISBL = 0x1 // Disable external reset + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0A: Timer/Counter0 Control Register + TCCR0A_FOC0A = 0x80 // Force Output Compare + TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0A_COM0A = 0x30 // Compare Match Output Modes + TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0A_CS0 = 0x7 // Clock Selects + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0 + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2A: Timer/Counter2 Control Register + TCCR2A_FOC2A = 0x80 // Force Output Compare A + TCCR2A_WGM20 = 0x40 // Waveform Generation Mode + TCCR2A_COM2A = 0x30 // Compare Output Mode bits + TCCR2A_WGM21 = 0x8 // Waveform Generation Mode + TCCR2A_CS2 = 0x7 // Clock Select bits + + // TIMSK2: Timer/Counter2 Interrupt Mask register + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter2 Interrupt Flag Register + TIFR2_OCF2A = 0x2 // Timer/Counter2 Output Compare Flag 2 + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x10 // Enable External Clock Interrupt + ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register + EICRA_ISC01 = 0x2 // External Interrupt Sense Control 0 Bit 1 + EICRA_ISC00 = 0x1 // External Interrupt Sense Control 0 Bit 0 + + // EIMSK: External Interrupt Mask Register + EIMSK_PCIE = 0xc0 // Pin Change Interrupt Enables + EIMSK_INT0 = 0x1 // External Interrupt Request 0 Enable + + // EIFR: External Interrupt Flag Register + EIFR_PCIF = 0xc0 // Pin Change Interrupt Flags + EIFR_INTF0 = 0x1 // External Interrupt Flag 0 + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks +) + +// Bitfields for USI: Universal Serial Interface +const ( + // USISR: USI Status Register + USISR_USISIF = 0x80 // Start Condition Interrupt Flag + USISR_USIOIF = 0x40 // Counter Overflow Interrupt Flag + USISR_USIPF = 0x20 // Stop Condition Flag + USISR_USIDC = 0x10 // Data Output Collision + USISR_USICNT = 0xf // USI Counter Value Bits + + // USICR: USI Control Register + USICR_USISIE = 0x80 // Start Condition Interrupt Enable + USICR_USIOIE = 0x40 // Counter Overflow Interrupt Enable + USICR_USIWM = 0x30 // USI Wire Mode Bits + USICR_USICS = 0xc // USI Clock Source Select Bits + USICR_USICLK = 0x2 // Clock Strobe + USICR_USITC = 0x1 // Toggle Clock Port Pin +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmit Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data OverRun + UCSR0A_UPE0 = 0x4 // USART Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART Transmission Speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data Register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0x40 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // PRR: Power Reduction Register + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable +) diff --git a/src/device/avr/atmega165p.ld b/src/device/avr/atmega165p.ld new file mode 100644 index 00000000..b4429513 --- /dev/null +++ b/src/device/avr/atmega165p.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega165P.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_size = 0x400; +__num_isrs = 22; diff --git a/src/device/avr/atmega165pa.go b/src/device/avr/atmega165pa.go new file mode 100644 index 00000000..30f99d5c --- /dev/null +++ b/src/device/avr/atmega165pa.go @@ -0,0 +1,605 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega165PA.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega165pa + +// Device information for the ATmega165PA. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega165PA" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_PCINT0 = 2 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 3 // Pin Change Interrupt Request 1 + IRQ_TIMER2_COMP = 4 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 5 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 6 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 7 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 8 // Timer/Counter Compare Match B + IRQ_TIMER1_OVF = 9 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 10 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 11 // Timer/Counter0 Overflow + IRQ_SPI_STC = 12 // SPI Serial Transfer Complete + IRQ_USART0_RX = 13 // USART0, Rx Complete + IRQ_USART0_UDRE = 14 // USART0 Data register Empty + IRQ_USART0_TX = 15 // USART0, Tx Complete + IRQ_USI_START = 16 // USI Start Condition + IRQ_USI_OVERFLOW = 17 // USI Overflow + IRQ_ANALOG_COMP = 18 // Analog Comparator + IRQ_ADC = 19 // ADC Conversion Complete + IRQ_EE_READY = 20 // EEPROM Ready + IRQ_SPM_READY = 21 // Store Program Memory Read + IRQ_max = 21 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0A __reg + TCNT0 __reg + OCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR0A: 0x44, // Timer/Counter0 Control Register + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2A __reg + TCNT2 __reg + OCR2A __reg + TIMSK2 __reg + TIFR2 __reg + ASSR __reg + }{ + TCCR2A: 0xb0, // Timer/Counter2 Control Register + TCNT2: 0xb2, // Timer/Counter2 + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register + TIMSK2: 0x70, // Timer/Counter2 Interrupt Mask register + TIFR2: 0x37, // Timer/Counter2 Interrupt Flag Register + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x60, // Watchdog Timer Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Bytes + EEARH: 0x41, // EEPROM Address Register Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + PORTG: 0x34, // Port G Data Register + DDRG: 0x33, // Port G Data Direction Register + PING: 0x32, // Port G Input Pins + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // Universal Serial Interface + USI = struct { + USIDR __reg + USISR __reg + USICR __reg + }{ + USIDR: 0xba, // USI Data Register + USISR: 0xb9, // USI Status Register + USICR: 0xb8, // USI Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 0 + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK1 __reg + PCMSK0 __reg + }{ + EICRA: 0x69, // External Interrupt Control Register + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + PRR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + PRR: 0x64, // Power Reduction Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0xe // Brown-out Detector trigger level + EXTENDED_RSTDISBL = 0x1 // Disable external reset + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0A: Timer/Counter0 Control Register + TCCR0A_FOC0A = 0x80 // Force Output Compare + TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0A_COM0A = 0x30 // Compare Match Output Modes + TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0A_CS0 = 0x7 // Clock Selects + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0 + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2A: Timer/Counter2 Control Register + TCCR2A_FOC2A = 0x80 // Force Output Compare A + TCCR2A_WGM20 = 0x40 // Waveform Generation Mode + TCCR2A_COM2A = 0x30 // Compare Output Mode bits + TCCR2A_WGM21 = 0x8 // Waveform Generation Mode + TCCR2A_CS2 = 0x7 // Clock Select bits + + // TIMSK2: Timer/Counter2 Interrupt Mask register + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter2 Interrupt Flag Register + TIFR2_OCF2A = 0x2 // Timer/Counter2 Output Compare Flag 2 + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x10 // Enable External Clock Interrupt + ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for USI: Universal Serial Interface +const ( + // USISR: USI Status Register + USISR_USISIF = 0x80 // Start Condition Interrupt Flag + USISR_USIOIF = 0x40 // Counter Overflow Interrupt Flag + USISR_USIPF = 0x20 // Stop Condition Flag + USISR_USIDC = 0x10 // Data Output Collision + USISR_USICNT = 0xf // USI Counter Value Bits + + // USICR: USI Control Register + USICR_USISIE = 0x80 // Start Condition Interrupt Enable + USICR_USIOIE = 0x40 // Counter Overflow Interrupt Enable + USICR_USIWM = 0x30 // USI Wire Mode Bits + USICR_USICS = 0xc // USI Clock Source Select Bits + USICR_USICLK = 0x2 // Clock Strobe + USICR_USITC = 0x1 // Toggle Clock Port Pin +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmit Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data OverRun + UCSR0A_UPE0 = 0x4 // USART Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART Transmission Speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data Register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0x40 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register + EICRA_ISC01 = 0x2 // External Interrupt Sense Control 0 Bit 1 + EICRA_ISC00 = 0x1 // External Interrupt Sense Control 0 Bit 0 + + // EIMSK: External Interrupt Mask Register + EIMSK_PCIE = 0x30 // Pin Change Interrupt Enables + EIMSK_INT0 = 0x1 // External Interrupt Request 0 Enable + + // EIFR: External Interrupt Flag Register + EIFR_PCIF = 0x30 // Pin Change Interrupt Flags + EIFR_INTF0 = 0x1 // External Interrupt Flag 0 + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // PRR: Power Reduction Register + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable +) diff --git a/src/device/avr/atmega165pa.ld b/src/device/avr/atmega165pa.ld new file mode 100644 index 00000000..74b52e48 --- /dev/null +++ b/src/device/avr/atmega165pa.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega165PA.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_size = 0x400; +__num_isrs = 22; diff --git a/src/device/avr/atmega168.go b/src/device/avr/atmega168.go new file mode 100644 index 00000000..a8ad39c7 --- /dev/null +++ b/src/device/avr/atmega168.go @@ -0,0 +1,640 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega168.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega168 + +// Device information for the ATmega168. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega168" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_PCINT0 = 3 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 4 // Pin Change Interrupt Request 0 + IRQ_PCINT2 = 5 // Pin Change Interrupt Request 1 + IRQ_WDT = 6 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 7 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 8 // Timer/Counter2 Compare Match A + IRQ_TIMER2_OVF = 9 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 10 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 11 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 12 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 13 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 14 // TimerCounter0 Compare Match A + IRQ_TIMER0_COMPB = 15 // TimerCounter0 Compare Match B + IRQ_TIMER0_OVF = 16 // Timer/Couner0 Overflow + IRQ_SPI_STC = 17 // SPI Serial Transfer Complete + IRQ_USART_RX = 18 // USART Rx Complete + IRQ_USART_UDRE = 19 // USART, Data Register Empty + IRQ_USART_TX = 20 // USART Tx Complete + IRQ_ADC = 21 // ADC Conversion Complete + IRQ_EE_READY = 22 // EEPROM Ready + IRQ_ANALOG_COMP = 23 // Analog Comparator + IRQ_TWI = 24 // Two-wire Serial Interface + IRQ_SPM_READY = 25 // Store Program Memory Read + IRQ_max = 25 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + ADCSRB __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // The ADC Control and Status register A + ADCSRB: 0x7b, // The ADC Control and Status register B + DIDR0: 0x7e, // Digital Input Disable Register + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // I/O Port + PORT = struct { + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + }{ + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCICR __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + } + + // Serial Peripheral Interface + SPI = struct { + SPDR __reg + SPSR __reg + SPCR __reg + }{ + SPDR: 0x4e, // SPI Data Register + SPSR: 0x4d, // SPI Status Register + SPCR: 0x4c, // SPI Control Register + } + + // CPU Registers + CPU = struct { + PRR __reg + OSCCAL __reg + CLKPR __reg + SREG __reg + SPL __reg + SPH __reg + SPMCSR __reg + MCUCR __reg + MCUSR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + PRR: 0x64, // Power Reduction Register + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + SPMCSR: 0x57, // Store Program Memory Control and Status Register + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose I/O Register 2 + GPIOR1: 0x4a, // General Purpose I/O Register 1 + GPIOR0: 0x3e, // General Purpose I/O Register 0 + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Bytes + EEARH: 0x41, // EEPROM Address Register Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BOOTSZ = 0x6 // Select boot size + EXTENDED_BOOTRST = 0x1 // Boot Reset vector Enabled + + // HIGH + HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PC6 as i/o pin) + HIGH_DWEN = 0x40 // Debug Wire enable + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watch-dog Timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTB0 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0xc0 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TIMSK1: Timer/Counter Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output CompareB Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output CompareA Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 + TCCR1C_FOC1B = 0x40 +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2B = 0x4 // Output Compare Flag 2B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Output Mode bits + TCCR2A_COM2B = 0x30 // Compare Output Mode bits + TCCR2A_WGM2 = 0x3 // Waveform Genration Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy + ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0xf // Analog Channel Selection Bits + + // ADCSRA: The ADC Control and Status register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCSRB: The ADC Control and Status register B + ADCSRB_ACME = 0x40 + ADCSRB_ADTS = 0x7 // ADC Auto Trigger Source bits + + // DIDR0: Digital Input Disable Register + DIDR0_ADC5D = 0x20 + DIDR0_ADC4D = 0x10 + DIDR0_ADC3D = 0x8 + DIDR0_ADC2D = 0x4 + DIDR0_ADC1D = 0x2 + DIDR0_ADC0D = 0x1 +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register + EICRA_ISC1 = 0xc // External Interrupt Sense Control 1 Bits + EICRA_ISC0 = 0x3 // External Interrupt Sense Control 0 Bits + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0x3 // External Interrupt Request 1 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0x3 // External Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0x7 // Pin Change Interrupt Enables + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0x7f // Pin Change Enable Masks + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0x7 // Pin Change Interrupt Flags +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects +) + +// Bitfields for CPU: CPU Registers +const ( + // PRR: Power Reduction Register + PRR_PRTWI = 0x80 // Power Reduction TWI + PRR_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // SPMCSR: Store Program Memory Control and Status Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read-While-Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read-While-Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SELFPRGEN = 0x1 // Self Programming Enable + + // MCUCR: MCU Control Register + MCUCR_PUD = 0x10 // Pull-up Disable + MCUCR_IVSEL = 0x2 // Interrupt Vector Select + MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable + + // MCUSR: MCU Status Register + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BORF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode + SMCR_SE = 0x1 // Sleep Enable +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) diff --git a/src/device/avr/atmega168.ld b/src/device/avr/atmega168.ld new file mode 100644 index 00000000..7f7cf4df --- /dev/null +++ b/src/device/avr/atmega168.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega168.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_size = 0x400; +__num_isrs = 26; diff --git a/src/device/avr/atmega168a.go b/src/device/avr/atmega168a.go new file mode 100644 index 00000000..16f47b5e --- /dev/null +++ b/src/device/avr/atmega168a.go @@ -0,0 +1,641 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega168A.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega168a + +// Device information for the ATmega168A. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega168A" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_PCINT0 = 3 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 4 // Pin Change Interrupt Request 0 + IRQ_PCINT2 = 5 // Pin Change Interrupt Request 1 + IRQ_WDT = 6 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 7 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 8 // Timer/Counter2 Compare Match A + IRQ_TIMER2_OVF = 9 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 10 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 11 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 12 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 13 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 14 // TimerCounter0 Compare Match A + IRQ_TIMER0_COMPB = 15 // TimerCounter0 Compare Match B + IRQ_TIMER0_OVF = 16 // Timer/Couner0 Overflow + IRQ_SPI_STC = 17 // SPI Serial Transfer Complete + IRQ_USART_RX = 18 // USART Rx Complete + IRQ_USART_UDRE = 19 // USART, Data Register Empty + IRQ_USART_TX = 20 // USART Tx Complete + IRQ_ADC = 21 // ADC Conversion Complete + IRQ_EE_READY = 22 // EEPROM Ready + IRQ_ANALOG_COMP = 23 // Analog Comparator + IRQ_TWI = 24 // Two-wire Serial Interface + IRQ_SPM_Ready = 25 // Store Program Memory Read + IRQ_max = 25 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + ADCSRB __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // The ADC Control and Status register A + ADCSRB: 0x7b, // The ADC Control and Status register B + DIDR0: 0x7e, // Digital Input Disable Register + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // I/O Port + PORT = struct { + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + }{ + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCICR __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + } + + // Serial Peripheral Interface + SPI = struct { + SPDR __reg + SPSR __reg + SPCR __reg + }{ + SPDR: 0x4e, // SPI Data Register + SPSR: 0x4d, // SPI Status Register + SPCR: 0x4c, // SPI Control Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Bytes + EEARH: 0x41, // EEPROM Address Register Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // CPU Registers + CPU = struct { + PRR __reg + OSCCAL __reg + CLKPR __reg + SREG __reg + SPL __reg + SPH __reg + SPMCSR __reg + MCUCR __reg + MCUSR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + PRR: 0x64, // Power Reduction Register + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + SPMCSR: 0x57, // Store Program Memory Control and Status Register + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose I/O Register 2 + GPIOR1: 0x4a, // General Purpose I/O Register 1 + GPIOR0: 0x3e, // General Purpose I/O Register 0 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BOOTSZ = 0x6 // Select boot size + EXTENDED_BOOTRST = 0x1 // Boot Reset vector Enabled + + // HIGH + HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PC6 as i/o pin) + HIGH_DWEN = 0x40 // Debug Wire enable + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watch-dog Timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTB0 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0xc0 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TIMSK1: Timer/Counter Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output CompareB Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output CompareA Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 + TCCR1C_FOC1B = 0x40 +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2B = 0x4 // Output Compare Flag 2B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Output Mode bits + TCCR2A_COM2B = 0x30 // Compare Output Mode bits + TCCR2A_WGM2 = 0x3 // Waveform Genration Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy + ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0xf // Analog Channel Selection Bits + + // ADCSRA: The ADC Control and Status register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCSRB: The ADC Control and Status register B + ADCSRB_ACME = 0x40 + ADCSRB_ADTS = 0x7 // ADC Auto Trigger Source bits + + // DIDR0: Digital Input Disable Register + DIDR0_ADC5D = 0x20 + DIDR0_ADC4D = 0x10 + DIDR0_ADC3D = 0x8 + DIDR0_ADC2D = 0x4 + DIDR0_ADC1D = 0x2 + DIDR0_ADC0D = 0x1 +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register + EICRA_ISC1 = 0xc // External Interrupt Sense Control 1 Bits + EICRA_ISC0 = 0x3 // External Interrupt Sense Control 0 Bits + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0x3 // External Interrupt Request 1 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0x3 // External Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0x7 // Pin Change Interrupt Enables + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0x7f // Pin Change Enable Masks + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0x7 // Pin Change Interrupt Flags +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for CPU: CPU Registers +const ( + // PRR: Power Reduction Register + PRR_PRTWI = 0x80 // Power Reduction TWI + PRR_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // SPMCSR: Store Program Memory Control and Status Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read-While-Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read-While-Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory + + // MCUCR: MCU Control Register + MCUCR_PUD = 0x10 + MCUCR_IVSEL = 0x2 + MCUCR_IVCE = 0x1 + + // MCUSR: MCU Status Register + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BORF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select Bits + SMCR_SE = 0x1 // Sleep Enable +) diff --git a/src/device/avr/atmega168a.ld b/src/device/avr/atmega168a.ld new file mode 100644 index 00000000..ab4c2c55 --- /dev/null +++ b/src/device/avr/atmega168a.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega168A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_size = 0x400; +__num_isrs = 26; diff --git a/src/device/avr/atmega168p.go b/src/device/avr/atmega168p.go new file mode 100644 index 00000000..d9b9ddfe --- /dev/null +++ b/src/device/avr/atmega168p.go @@ -0,0 +1,642 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega168P.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega168p + +// Device information for the ATmega168P. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega168P" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_PCINT0 = 3 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 4 // Pin Change Interrupt Request 0 + IRQ_PCINT2 = 5 // Pin Change Interrupt Request 1 + IRQ_WDT = 6 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 7 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 8 // Timer/Counter2 Compare Match A + IRQ_TIMER2_OVF = 9 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 10 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 11 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 12 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 13 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 14 // TimerCounter0 Compare Match A + IRQ_TIMER0_COMPB = 15 // TimerCounter0 Compare Match B + IRQ_TIMER0_OVF = 16 // Timer/Couner0 Overflow + IRQ_SPI_STC = 17 // SPI Serial Transfer Complete + IRQ_USART_RX = 18 // USART Rx Complete + IRQ_USART_UDRE = 19 // USART, Data Register Empty + IRQ_USART_TX = 20 // USART Tx Complete + IRQ_ADC = 21 // ADC Conversion Complete + IRQ_EE_READY = 22 // EEPROM Ready + IRQ_ANALOG_COMP = 23 // Analog Comparator + IRQ_TWI = 24 // Two-wire Serial Interface + IRQ_SPM_Ready = 25 // Store Program Memory Read + IRQ_max = 25 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + ADCSRB __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // The ADC Control and Status register A + ADCSRB: 0x7b, // The ADC Control and Status register B + DIDR0: 0x7e, // Digital Input Disable Register + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // I/O Port + PORT = struct { + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + }{ + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCICR __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + } + + // Serial Peripheral Interface + SPI = struct { + SPDR __reg + SPSR __reg + SPCR __reg + }{ + SPDR: 0x4e, // SPI Data Register + SPSR: 0x4d, // SPI Status Register + SPCR: 0x4c, // SPI Control Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Bytes + EEARH: 0x41, // EEPROM Address Register Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // CPU Registers + CPU = struct { + PRR __reg + OSCCAL __reg + CLKPR __reg + SREG __reg + SPL __reg + SPH __reg + SPMCSR __reg + MCUCR __reg + MCUSR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + PRR: 0x64, // Power Reduction Register + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + SPMCSR: 0x57, // Store Program Memory Control and Status Register + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose I/O Register 2 + GPIOR1: 0x4a, // General Purpose I/O Register 1 + GPIOR0: 0x3e, // General Purpose I/O Register 0 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BOOTSZ = 0x6 // Select boot size + EXTENDED_BOOTRST = 0x1 // Boot Reset vector Enabled + + // HIGH + HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PC6 as i/o pin) + HIGH_DWEN = 0x40 // Debug Wire enable + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watch-dog Timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTB0 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0xc0 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TIMSK1: Timer/Counter Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output CompareB Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output CompareA Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 + TCCR1C_FOC1B = 0x40 +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2B = 0x4 // Output Compare Flag 2B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Output Mode bits + TCCR2A_COM2B = 0x30 // Compare Output Mode bits + TCCR2A_WGM2 = 0x3 // Waveform Genration Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy + ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0xf // Analog Channel Selection Bits + + // ADCSRA: The ADC Control and Status register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCSRB: The ADC Control and Status register B + ADCSRB_ACME = 0x40 + ADCSRB_ADTS = 0x7 // ADC Auto Trigger Source bits + + // DIDR0: Digital Input Disable Register + DIDR0_ADC5D = 0x20 + DIDR0_ADC4D = 0x10 + DIDR0_ADC3D = 0x8 + DIDR0_ADC2D = 0x4 + DIDR0_ADC1D = 0x2 + DIDR0_ADC0D = 0x1 +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register + EICRA_ISC1 = 0xc // External Interrupt Sense Control 1 Bits + EICRA_ISC0 = 0x3 // External Interrupt Sense Control 0 Bits + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0x3 // External Interrupt Request 1 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0x3 // External Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0x7 // Pin Change Interrupt Enables + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0x7f // Pin Change Enable Masks + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0x7 // Pin Change Interrupt Flags +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for CPU: CPU Registers +const ( + // PRR: Power Reduction Register + PRR_PRTWI = 0x80 // Power Reduction TWI + PRR_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // SPMCSR: Store Program Memory Control and Status Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read-While-Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read-While-Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SELFPRGEN = 0x1 // Self Programming Enable + + // MCUCR: MCU Control Register + MCUCR_BODS = 0x40 // BOD Sleep + MCUCR_BODSE = 0x20 // BOD Sleep Enable + MCUCR_PUD = 0x10 + MCUCR_IVSEL = 0x2 + MCUCR_IVCE = 0x1 + + // MCUSR: MCU Status Register + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BORF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select Bits + SMCR_SE = 0x1 // Sleep Enable +) diff --git a/src/device/avr/atmega168p.ld b/src/device/avr/atmega168p.ld new file mode 100644 index 00000000..e3ae20e8 --- /dev/null +++ b/src/device/avr/atmega168p.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega168P.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_size = 0x400; +__num_isrs = 26; diff --git a/src/device/avr/atmega168pa.go b/src/device/avr/atmega168pa.go new file mode 100644 index 00000000..c77b593d --- /dev/null +++ b/src/device/avr/atmega168pa.go @@ -0,0 +1,643 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega168PA.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega168pa + +// Device information for the ATmega168PA. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega168PA" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_PCINT0 = 3 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 4 // Pin Change Interrupt Request 0 + IRQ_PCINT2 = 5 // Pin Change Interrupt Request 1 + IRQ_WDT = 6 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 7 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 8 // Timer/Counter2 Compare Match A + IRQ_TIMER2_OVF = 9 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 10 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 11 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 12 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 13 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 14 // TimerCounter0 Compare Match A + IRQ_TIMER0_COMPB = 15 // TimerCounter0 Compare Match B + IRQ_TIMER0_OVF = 16 // Timer/Couner0 Overflow + IRQ_SPI_STC = 17 // SPI Serial Transfer Complete + IRQ_USART_RX = 18 // USART Rx Complete + IRQ_USART_UDRE = 19 // USART, Data Register Empty + IRQ_USART_TX = 20 // USART Tx Complete + IRQ_ADC = 21 // ADC Conversion Complete + IRQ_EE_READY = 22 // EEPROM Ready + IRQ_ANALOG_COMP = 23 // Analog Comparator + IRQ_TWI = 24 // Two-wire Serial Interface + IRQ_SPM_Ready = 25 // Store Program Memory Read + IRQ_max = 25 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + ADCSRB __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // The ADC Control and Status register A + ADCSRB: 0x7b, // The ADC Control and Status register B + DIDR0: 0x7e, // Digital Input Disable Register + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // I/O Port + PORT = struct { + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + }{ + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCICR __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + } + + // Serial Peripheral Interface + SPI = struct { + SPDR __reg + SPSR __reg + SPCR __reg + }{ + SPDR: 0x4e, // SPI Data Register + SPSR: 0x4d, // SPI Status Register + SPCR: 0x4c, // SPI Control Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Bytes + EEARH: 0x41, // EEPROM Address Register Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // CPU Registers + CPU = struct { + PRR __reg + OSCCAL __reg + CLKPR __reg + SREG __reg + SPL __reg + SPH __reg + SPMCSR __reg + MCUCR __reg + MCUSR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + PRR: 0x64, // Power Reduction Register + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + SPMCSR: 0x57, // Store Program Memory Control and Status Register + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose I/O Register 2 + GPIOR1: 0x4a, // General Purpose I/O Register 1 + GPIOR0: 0x3e, // General Purpose I/O Register 0 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BOOTSZ = 0x6 // Select boot size + EXTENDED_BOOTRST = 0x1 // Boot Reset vector Enabled + + // HIGH + HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PC6 as i/o pin) + HIGH_DWEN = 0x40 // Debug Wire enable + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watch-dog Timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTB0 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0xc0 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TIMSK1: Timer/Counter Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output CompareB Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output CompareA Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 + TCCR1C_FOC1B = 0x40 +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2B = 0x4 // Output Compare Flag 2B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Output Mode bits + TCCR2A_COM2B = 0x30 // Compare Output Mode bits + TCCR2A_WGM2 = 0x3 // Waveform Genration Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy + ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0xf // Analog Channel Selection Bits + + // ADCSRA: The ADC Control and Status register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCSRB: The ADC Control and Status register B + ADCSRB_ACME = 0x40 + ADCSRB_ADTS = 0x7 // ADC Auto Trigger Source bits + + // DIDR0: Digital Input Disable Register + DIDR0_ADC5D = 0x20 + DIDR0_ADC4D = 0x10 + DIDR0_ADC3D = 0x8 + DIDR0_ADC2D = 0x4 + DIDR0_ADC1D = 0x2 + DIDR0_ADC0D = 0x1 +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register + EICRA_ISC1 = 0xc // External Interrupt Sense Control 1 Bits + EICRA_ISC0 = 0x3 // External Interrupt Sense Control 0 Bits + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0x3 // External Interrupt Request 1 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0x3 // External Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0x7 // Pin Change Interrupt Enables + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0x7f // Pin Change Enable Masks + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0x7 // Pin Change Interrupt Flags +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for CPU: CPU Registers +const ( + // PRR: Power Reduction Register + PRR_PRTWI = 0x80 // Power Reduction TWI + PRR_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // SPMCSR: Store Program Memory Control and Status Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read-While-Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read-While-Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory + + // MCUCR: MCU Control Register + MCUCR_BODS = 0x40 // BOD Sleep + MCUCR_BODSE = 0x20 // BOD Sleep Enable + MCUCR_PUD = 0x10 + MCUCR_IVSEL = 0x2 + MCUCR_IVCE = 0x1 + + // MCUSR: MCU Status Register + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BORF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select Bits + SMCR_SE = 0x1 // Sleep Enable +) diff --git a/src/device/avr/atmega168pa.ld b/src/device/avr/atmega168pa.ld new file mode 100644 index 00000000..8c819f9e --- /dev/null +++ b/src/device/avr/atmega168pa.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega168PA.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_size = 0x400; +__num_isrs = 26; diff --git a/src/device/avr/atmega168pb.go b/src/device/avr/atmega168pb.go new file mode 100644 index 00000000..fc05821f --- /dev/null +++ b/src/device/avr/atmega168pb.go @@ -0,0 +1,685 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega168PB.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega168pb + +// Device information for the ATmega168PB. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega168PB" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_PCINT0 = 3 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 4 // Pin Change Interrupt Request 0 + IRQ_PCINT2 = 5 // Pin Change Interrupt Request 1 + IRQ_WDT = 6 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 7 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 8 // Timer/Counter2 Compare Match A + IRQ_TIMER2_OVF = 9 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 10 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 11 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 12 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 13 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 14 // TimerCounter0 Compare Match A + IRQ_TIMER0_COMPB = 15 // TimerCounter0 Compare Match B + IRQ_TIMER0_OVF = 16 // Timer/Couner0 Overflow + IRQ_SPI_STC = 17 // SPI Serial Transfer Complete + IRQ_USART_RX = 18 // USART Rx Complete + IRQ_USART_UDRE = 19 // USART, Data Register Empty + IRQ_USART_TX = 20 // USART Tx Complete + IRQ_ADC = 21 // ADC Conversion Complete + IRQ_EE_READY = 22 // EEPROM Ready + IRQ_ANALOG_COMP = 23 // Analog Comparator + IRQ_TWI = 24 // Two-wire Serial Interface + IRQ_SPM_Ready = 25 // Store Program Memory Read + IRQ_USART_START = 26 // USART Start Edge Interrupt + IRQ_max = 26 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Device ID + DEVICEID = struct { + DEVID0 __reg + DEVID1 __reg + DEVID2 __reg + DEVID3 __reg + DEVID4 __reg + DEVID5 __reg + DEVID6 __reg + DEVID7 __reg + DEVID8 __reg + }{ + DEVID0: 0xf0, + DEVID1: 0xf1, + DEVID2: 0xf2, + DEVID3: 0xf3, + DEVID4: 0xf4, + DEVID5: 0xf5, + DEVID6: 0xf6, + DEVID7: 0xf7, + DEVID8: 0xf8, + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UCSR0D __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UCSR0D: 0xc3, // USART Control and Status Register D + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + ADCSRB __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // The ADC Control and Status register A + ADCSRB: 0x7b, // The ADC Control and Status register B + DIDR0: 0x7e, // Digital Input Disable Register + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + ACSRB __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + ACSRB: 0x4f, // Analog Comparator Status Register B + } + + // I/O Port + PORT = struct { + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + }{ + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Port E Data Register + DDRE: 0x2d, // Port E Data Direction Register + PINE: 0x2c, // Port E Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCICR __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + } + + // Serial Peripheral Interface + SPI = struct { + SPDR __reg + SPSR __reg + SPCR __reg + }{ + SPDR: 0x4e, // SPI Data Register + SPSR: 0x4d, // SPI Status Register + SPCR: 0x4c, // SPI Control Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Bytes + EEARH: 0x41, // EEPROM Address Register Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // CPU Registers + CPU = struct { + PRR __reg + OSCCAL __reg + CLKPR __reg + SREG __reg + SPL __reg + SPH __reg + SPMCSR __reg + MCUCR __reg + MCUSR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + PRR: 0x64, // Power Reduction Register + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + SPMCSR: 0x57, // Store Program Memory Control and Status Register + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose I/O Register 2 + GPIOR1: 0x4a, // General Purpose I/O Register 1 + GPIOR0: 0x3e, // General Purpose I/O Register 0 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BOOTSZ = 0x6 // Select boot size + EXTENDED_BOOTRST = 0x1 // Boot Reset vector Enabled + + // HIGH + HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PC6 as i/o pin) + HIGH_DWEN = 0x40 // Debug Wire enable + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watch-dog Timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTB0 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0xc0 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity + + // UCSR0D: USART Control and Status Register D + UCSR0D_RXSIE = 0x80 // RX Start Interrupt Enable + UCSR0D_RXS = 0x40 // RX Start + UCSR0D_SFDE = 0x20 // Start Frame Detection Enable +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TIMSK1: Timer/Counter Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output CompareB Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output CompareA Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 + TCCR1C_FOC1B = 0x40 +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2B = 0x4 // Output Compare Flag 2B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Output Mode bits + TCCR2A_COM2B = 0x30 // Compare Output Mode bits + TCCR2A_WGM2 = 0x3 // Waveform Genration Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy + ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0xf // Analog Channel Selection Bits + + // ADCSRA: The ADC Control and Status register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCSRB: The ADC Control and Status register B + ADCSRB_ACME = 0x40 + ADCSRB_ADTS = 0x7 // ADC Auto Trigger Source bits + + // DIDR0: Digital Input Disable Register + DIDR0_ADC5D = 0x20 + DIDR0_ADC4D = 0x10 + DIDR0_ADC3D = 0x8 + DIDR0_ADC2D = 0x4 + DIDR0_ADC1D = 0x2 + DIDR0_ADC0D = 0x1 +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable + + // ACSRB: Analog Comparator Status Register B + ACSRB_ACOE = 0x1 // Analog Comparator Output Enable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register + EICRA_ISC1 = 0xc // External Interrupt Sense Control 1 Bits + EICRA_ISC0 = 0x3 // External Interrupt Sense Control 0 Bits + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0x3 // External Interrupt Request 1 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0x3 // External Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0x7 // Pin Change Interrupt Enables + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0x7f // Pin Change Enable Masks + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0x7 // Pin Change Interrupt Flags +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for CPU: CPU Registers +const ( + // PRR: Power Reduction Register + PRR_PRTWI = 0x80 // Power Reduction TWI + PRR_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // SPMCSR: Store Program Memory Control and Status Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read-While-Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read-While-Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory + + // MCUCR: MCU Control Register + MCUCR_BODS = 0x40 // BOD Sleep + MCUCR_BODSE = 0x20 // BOD Sleep Enable + MCUCR_PUD = 0x10 + MCUCR_IVSEL = 0x2 + MCUCR_IVCE = 0x1 + + // MCUSR: MCU Status Register + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BORF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select Bits + SMCR_SE = 0x1 // Sleep Enable +) diff --git a/src/device/avr/atmega168pb.ld b/src/device/avr/atmega168pb.ld new file mode 100644 index 00000000..0b6738f3 --- /dev/null +++ b/src/device/avr/atmega168pb.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega168PB.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_size = 0x400; +__num_isrs = 27; diff --git a/src/device/avr/atmega169a.go b/src/device/avr/atmega169a.go new file mode 100644 index 00000000..9ec0713b --- /dev/null +++ b/src/device/avr/atmega169a.go @@ -0,0 +1,679 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega169A.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega169a + +// Device information for the ATmega169A. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega169A" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_PCINT0 = 2 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 3 // Pin Change Interrupt Request 1 + IRQ_TIMER2_COMP = 4 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 5 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 6 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 7 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 8 // Timer/Counter Compare Match B + IRQ_TIMER1_OVF = 9 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 10 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 11 // Timer/Counter0 Overflow + IRQ_SPI_STC = 12 // SPI Serial Transfer Complete + IRQ_USART0_RX = 13 // USART0, Rx Complete + IRQ_USART0_UDRE = 14 // USART0 Data register Empty + IRQ_USART0_TX = 15 // USART0, Tx Complete + IRQ_USI_START = 16 // USI Start Condition + IRQ_USI_OVERFLOW = 17 // USI Overflow + IRQ_ANALOG_COMP = 18 // Analog Comparator + IRQ_ADC = 19 // ADC Conversion Complete + IRQ_EE_READY = 20 // EEPROM Ready + IRQ_SPM_READY = 21 // Store Program Memory Read + IRQ_LCD = 22 // LCD Start of Frame + IRQ_max = 22 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0A __reg + TCNT0 __reg + OCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR0A: 0x44, // Timer/Counter0 Control Register + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2A __reg + TCNT2 __reg + OCR2A __reg + TIMSK2 __reg + TIFR2 __reg + ASSR __reg + }{ + TCCR2A: 0xb0, // Timer/Counter2 Control Register + TCNT2: 0xb2, // Timer/Counter2 + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register + TIMSK2: 0x70, // Timer/Counter2 Interrupt Mask register + TIFR2: 0x37, // Timer/Counter2 Interrupt Flag Register + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x60, // Watchdog Timer Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Bytes + EEARH: 0x41, // EEPROM Address Register Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + PORTG: 0x34, // Port G Data Register + DDRG: 0x33, // Port G Data Direction Register + PING: 0x32, // Port G Input Pins + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // Liquid Crystal Display + LCD = struct { + LCDCRA __reg + LCDCRB __reg + LCDFRR __reg + LCDCCR __reg + LCDDR18 __reg + LCDDR17 __reg + LCDDR16 __reg + LCDDR15 __reg + LCDDR13 __reg + LCDDR12 __reg + LCDDR11 __reg + LCDDR10 __reg + LCDDR8 __reg + LCDDR7 __reg + LCDDR6 __reg + LCDDR5 __reg + LCDDR3 __reg + LCDDR2 __reg + LCDDR1 __reg + LCDDR0 __reg + }{ + LCDCRA: 0xe4, // LCD Control Register A + LCDCRB: 0xe5, // LCD Control and Status Register B + LCDFRR: 0xe6, // LCD Frame Rate Register + LCDCCR: 0xe7, // LCD Contrast Control Register + LCDDR18: 0xfe, // LCD Data Register 18 + LCDDR17: 0xfd, // LCD Data Register 17 + LCDDR16: 0xfc, // LCD Data Register 16 + LCDDR15: 0xfb, // LCD Data Register 15 + LCDDR13: 0xf9, // LCD Data Register 13 + LCDDR12: 0xf8, // LCD Data Register 12 + LCDDR11: 0xf7, // LCD Data Register 11 + LCDDR10: 0xf6, // LCD Data Register 10 + LCDDR8: 0xf4, // LCD Data Register 8 + LCDDR7: 0xf3, // LCD Data Register 7 + LCDDR6: 0xf2, // LCD Data Register 6 + LCDDR5: 0xf1, // LCD Data Register 5 + LCDDR3: 0xef, // LCD Data Register 3 + LCDDR2: 0xee, // LCD Data Register 2 + LCDDR1: 0xed, // LCD Data Register 1 + LCDDR0: 0xec, // LCD Data Register 0 + } + + // Universal Serial Interface + USI = struct { + USIDR __reg + USISR __reg + USICR __reg + }{ + USIDR: 0xba, // USI Data Register + USISR: 0xb9, // USI Status Register + USICR: 0xb8, // USI Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 0 + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK1 __reg + PCMSK0 __reg + }{ + EICRA: 0x69, // External Interrupt Control Register + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + PRR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + PRR: 0x64, // Power Reduction Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0xe // Brown-out Detector trigger level + EXTENDED_RSTDISBL = 0x1 // Disable external reset + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0A: Timer/Counter0 Control Register + TCCR0A_FOC0A = 0x80 // Force Output Compare + TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0A_COM0A = 0x30 // Compare Match Output Modes + TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0A_CS0 = 0x7 // Clock Selects + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0 + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2A: Timer/Counter2 Control Register + TCCR2A_FOC2A = 0x80 // Force Output Compare A + TCCR2A_WGM20 = 0x40 // Waveform Generation Mode + TCCR2A_COM2A = 0x30 // Compare Output Mode bits + TCCR2A_WGM21 = 0x8 // Waveform Generation Mode + TCCR2A_CS2 = 0x7 // Clock Select bits + + // TIMSK2: Timer/Counter2 Interrupt Mask register + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter2 Interrupt Flag Register + TIFR2_OCF2A = 0x2 // Timer/Counter2 Output Compare Flag 2 + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x10 // Enable External Clock Interrupt + ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for LCD: Liquid Crystal Display +const ( + // LCDCRA: LCD Control Register A + LCDCRA_LCDEN = 0x80 // LCD Enable + LCDCRA_LCDAB = 0x40 // LCD A or B waveform + LCDCRA_LCDIF = 0x10 // LCD Interrupt Flag + LCDCRA_LCDIE = 0x8 // LCD Interrupt Enable + LCDCRA_LCDBD = 0x4 // LCD Buffer Disable + LCDCRA_LCDCCD = 0x2 // LCD Contrast Control Disable + LCDCRA_LCDBL = 0x1 // LCD Blanking + + // LCDCRB: LCD Control and Status Register B + LCDCRB_LCDCS = 0x80 // LCD CLock Select + LCDCRB_LCD2B = 0x40 // LCD 1/2 Bias Select + LCDCRB_LCDMUX = 0x30 // LCD Mux Selects + LCDCRB_LCDPM = 0x7 // LCD Port Masks + + // LCDFRR: LCD Frame Rate Register + LCDFRR_LCDPS = 0x70 // LCD Prescaler Selects + LCDFRR_LCDCD = 0x7 // LCD Clock Dividers + + // LCDCCR: LCD Contrast Control Register + LCDCCR_LCDDC = 0xe0 // LCD Display Configuration Bits + LCDCCR_LCDMDT = 0x10 // LCD Maximum Drive Time + LCDCCR_LCDCC = 0xf // LCD Contrast Controls +) + +// Bitfields for USI: Universal Serial Interface +const ( + // USISR: USI Status Register + USISR_USISIF = 0x80 // Start Condition Interrupt Flag + USISR_USIOIF = 0x40 // Counter Overflow Interrupt Flag + USISR_USIPF = 0x20 // Stop Condition Flag + USISR_USIDC = 0x10 // Data Output Collision + USISR_USICNT = 0xf // USI Counter Value Bits + + // USICR: USI Control Register + USICR_USISIE = 0x80 // Start Condition Interrupt Enable + USICR_USIOIE = 0x40 // Counter Overflow Interrupt Enable + USICR_USIWM = 0x30 // USI Wire Mode Bits + USICR_USICS = 0xc // USI Clock Source Select Bits + USICR_USICLK = 0x2 // Clock Strobe + USICR_USITC = 0x1 // Toggle Clock Port Pin +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmit Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data OverRun + UCSR0A_UPE0 = 0x4 // USART Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART Transmission Speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data Register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0x40 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register + EICRA_ISC01 = 0x2 // External Interrupt Sense Control 0 Bit 1 + EICRA_ISC00 = 0x1 // External Interrupt Sense Control 0 Bit 0 + + // EIMSK: External Interrupt Mask Register + EIMSK_PCIE = 0x30 // Pin Change Interrupt Enables + EIMSK_INT0 = 0x1 // External Interrupt Request 0 Enable + + // EIFR: External Interrupt Flag Register + EIFR_PCIF = 0x30 // Pin Change Interrupt Flags + EIFR_INTF0 = 0x1 // External Interrupt Flag 0 + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // PRR: Power Reduction Register + PRR_PRLCD = 0x10 // Power Reduction LCD + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable +) diff --git a/src/device/avr/atmega169a.ld b/src/device/avr/atmega169a.ld new file mode 100644 index 00000000..299a8372 --- /dev/null +++ b/src/device/avr/atmega169a.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega169A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_size = 0x400; +__num_isrs = 23; diff --git a/src/device/avr/atmega169p.go b/src/device/avr/atmega169p.go new file mode 100644 index 00000000..835f5905 --- /dev/null +++ b/src/device/avr/atmega169p.go @@ -0,0 +1,679 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega169P.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega169p + +// Device information for the ATmega169P. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega169P" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_PCINT0 = 2 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 3 // Pin Change Interrupt Request 1 + IRQ_TIMER2_COMP = 4 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 5 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 6 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 7 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 8 // Timer/Counter Compare Match B + IRQ_TIMER1_OVF = 9 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 10 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 11 // Timer/Counter0 Overflow + IRQ_SPI_STC = 12 // SPI Serial Transfer Complete + IRQ_USART0_RX = 13 // USART0, Rx Complete + IRQ_USART0_UDRE = 14 // USART0 Data register Empty + IRQ_USART0_TX = 15 // USART0, Tx Complete + IRQ_USI_START = 16 // USI Start Condition + IRQ_USI_OVERFLOW = 17 // USI Overflow + IRQ_ANALOG_COMP = 18 // Analog Comparator + IRQ_ADC = 19 // ADC Conversion Complete + IRQ_EE_READY = 20 // EEPROM Ready + IRQ_SPM_READY = 21 // Store Program Memory Read + IRQ_LCD = 22 // LCD Start of Frame + IRQ_max = 22 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0A __reg + TCNT0 __reg + OCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR0A: 0x44, // Timer/Counter0 Control Register + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2A __reg + TCNT2 __reg + OCR2A __reg + TIMSK2 __reg + TIFR2 __reg + ASSR __reg + }{ + TCCR2A: 0xb0, // Timer/Counter2 Control Register + TCNT2: 0xb2, // Timer/Counter2 + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register + TIMSK2: 0x70, // Timer/Counter2 Interrupt Mask register + TIFR2: 0x37, // Timer/Counter2 Interrupt Flag Register + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x60, // Watchdog Timer Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Bytes + EEARH: 0x41, // EEPROM Address Register Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + PORTG: 0x34, // Port G Data Register + DDRG: 0x33, // Port G Data Direction Register + PING: 0x32, // Port G Input Pins + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // Liquid Crystal Display + LCD = struct { + LCDCRA __reg + LCDCRB __reg + LCDFRR __reg + LCDCCR __reg + LCDDR18 __reg + LCDDR17 __reg + LCDDR16 __reg + LCDDR15 __reg + LCDDR13 __reg + LCDDR12 __reg + LCDDR11 __reg + LCDDR10 __reg + LCDDR8 __reg + LCDDR7 __reg + LCDDR6 __reg + LCDDR5 __reg + LCDDR3 __reg + LCDDR2 __reg + LCDDR1 __reg + LCDDR0 __reg + }{ + LCDCRA: 0xe4, // LCD Control Register A + LCDCRB: 0xe5, // LCD Control and Status Register B + LCDFRR: 0xe6, // LCD Frame Rate Register + LCDCCR: 0xe7, // LCD Contrast Control Register + LCDDR18: 0xfe, // LCD Data Register 18 + LCDDR17: 0xfd, // LCD Data Register 17 + LCDDR16: 0xfc, // LCD Data Register 16 + LCDDR15: 0xfb, // LCD Data Register 15 + LCDDR13: 0xf9, // LCD Data Register 13 + LCDDR12: 0xf8, // LCD Data Register 12 + LCDDR11: 0xf7, // LCD Data Register 11 + LCDDR10: 0xf6, // LCD Data Register 10 + LCDDR8: 0xf4, // LCD Data Register 8 + LCDDR7: 0xf3, // LCD Data Register 7 + LCDDR6: 0xf2, // LCD Data Register 6 + LCDDR5: 0xf1, // LCD Data Register 5 + LCDDR3: 0xef, // LCD Data Register 3 + LCDDR2: 0xee, // LCD Data Register 2 + LCDDR1: 0xed, // LCD Data Register 1 + LCDDR0: 0xec, // LCD Data Register 0 + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK1 __reg + PCMSK0 __reg + }{ + EICRA: 0x69, // External Interrupt Control Register + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + } + + // Universal Serial Interface + USI = struct { + USIDR __reg + USISR __reg + USICR __reg + }{ + USIDR: 0xba, // USI Data Register + USISR: 0xb9, // USI Status Register + USICR: 0xb8, // USI Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 0 + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + PRR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + PRR: 0x64, // Power Reduction Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0xe // Brown-out Detector trigger level + EXTENDED_RSTDISBL = 0x1 // Disable external reset + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0A: Timer/Counter0 Control Register + TCCR0A_FOC0A = 0x80 // Force Output Compare + TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0A_COM0A = 0x30 // Compare Match Output Modes + TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0A_CS0 = 0x7 // Clock Selects + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0 + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2A: Timer/Counter2 Control Register + TCCR2A_FOC2A = 0x80 // Force Output Compare A + TCCR2A_WGM20 = 0x40 // Waveform Generation Mode + TCCR2A_COM2A = 0x30 // Compare Output Mode bits + TCCR2A_WGM21 = 0x8 // Waveform Generation Mode + TCCR2A_CS2 = 0x7 // Clock Select bits + + // TIMSK2: Timer/Counter2 Interrupt Mask register + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter2 Interrupt Flag Register + TIFR2_OCF2A = 0x2 // Timer/Counter2 Output Compare Flag 2 + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x10 // Enable External Clock Interrupt + ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for LCD: Liquid Crystal Display +const ( + // LCDCRA: LCD Control Register A + LCDCRA_LCDEN = 0x80 // LCD Enable + LCDCRA_LCDAB = 0x40 // LCD A or B waveform + LCDCRA_LCDIF = 0x10 // LCD Interrupt Flag + LCDCRA_LCDIE = 0x8 // LCD Interrupt Enable + LCDCRA_LCDBD = 0x4 // LCD Buffer Disable + LCDCRA_LCDCCD = 0x2 // LCD Contrast Control Disable + LCDCRA_LCDBL = 0x1 // LCD Blanking + + // LCDCRB: LCD Control and Status Register B + LCDCRB_LCDCS = 0x80 // LCD CLock Select + LCDCRB_LCD2B = 0x40 // LCD 1/2 Bias Select + LCDCRB_LCDMUX = 0x30 // LCD Mux Selects + LCDCRB_LCDPM = 0x7 // LCD Port Masks + + // LCDFRR: LCD Frame Rate Register + LCDFRR_LCDPS = 0x70 // LCD Prescaler Selects + LCDFRR_LCDCD = 0x7 // LCD Clock Dividers + + // LCDCCR: LCD Contrast Control Register + LCDCCR_LCDDC = 0xe0 // LCD Display Configuration Bits + LCDCCR_LCDMDT = 0x10 // LCD Maximum Drive Time + LCDCCR_LCDCC = 0xf // LCD Contrast Controls +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register + EICRA_ISC01 = 0x2 // External Interrupt Sense Control 0 Bit 1 + EICRA_ISC00 = 0x1 // External Interrupt Sense Control 0 Bit 0 + + // EIMSK: External Interrupt Mask Register + EIMSK_PCIE = 0xc0 // Pin Change Interrupt Enables + EIMSK_INT0 = 0x1 // External Interrupt Request 0 Enable + + // EIFR: External Interrupt Flag Register + EIFR_PCIF = 0xc0 // Pin Change Interrupt Flags + EIFR_INTF0 = 0x1 // External Interrupt Flag 0 + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks +) + +// Bitfields for USI: Universal Serial Interface +const ( + // USISR: USI Status Register + USISR_USISIF = 0x80 // Start Condition Interrupt Flag + USISR_USIOIF = 0x40 // Counter Overflow Interrupt Flag + USISR_USIPF = 0x20 // Stop Condition Flag + USISR_USIDC = 0x10 // Data Output Collision + USISR_USICNT = 0xf // USI Counter Value Bits + + // USICR: USI Control Register + USICR_USISIE = 0x80 // Start Condition Interrupt Enable + USICR_USIOIE = 0x40 // Counter Overflow Interrupt Enable + USICR_USIWM = 0x30 // USI Wire Mode Bits + USICR_USICS = 0xc // USI Clock Source Select Bits + USICR_USICLK = 0x2 // Clock Strobe + USICR_USITC = 0x1 // Toggle Clock Port Pin +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmit Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data OverRun + UCSR0A_UPE0 = 0x4 // USART Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART Transmission Speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data Register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0x40 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // PRR: Power Reduction Register + PRR_PRLCD = 0x10 // Power Reduction LCD + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable +) diff --git a/src/device/avr/atmega169p.ld b/src/device/avr/atmega169p.ld new file mode 100644 index 00000000..16ffe79d --- /dev/null +++ b/src/device/avr/atmega169p.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega169P.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_size = 0x400; +__num_isrs = 23; diff --git a/src/device/avr/atmega169pa.go b/src/device/avr/atmega169pa.go new file mode 100644 index 00000000..43ba7c2e --- /dev/null +++ b/src/device/avr/atmega169pa.go @@ -0,0 +1,747 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega169PA.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega169pa + +// Device information for the ATmega169PA. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega169PA" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_PCINT0 = 2 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 3 // Pin Change Interrupt Request 1 + IRQ_TIMER2_COMP = 4 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 5 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 6 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 7 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 8 // Timer/Counter Compare Match B + IRQ_TIMER1_OVF = 9 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 10 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 11 // Timer/Counter0 Overflow + IRQ_SPI_STC = 12 // SPI Serial Transfer Complete + IRQ_USART0_RX = 13 // USART0, Rx Complete + IRQ_USART0_UDRE = 14 // USART0 Data register Empty + IRQ_USART0_TX = 15 // USART0, Tx Complete + IRQ_USI_START = 16 // USI Start Condition + IRQ_USI_OVERFLOW = 17 // USI Overflow + IRQ_ANALOG_COMP = 18 // Analog Comparator + IRQ_ADC = 19 // ADC Conversion Complete + IRQ_EE_READY = 20 // EEPROM Ready + IRQ_SPM_READY = 21 // Store Program Memory Read + IRQ_LCD = 22 // LCD Start of Frame + IRQ_max = 22 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0A __reg + TCNT0 __reg + OCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR0A: 0x44, // Timer/Counter0 Control Register + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2A __reg + TCNT2 __reg + OCR2A __reg + TIMSK2 __reg + TIFR2 __reg + ASSR __reg + }{ + TCCR2A: 0xb0, // Timer/Counter2 Control Register + TCNT2: 0xb2, // Timer/Counter2 + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register + TIMSK2: 0x70, // Timer/Counter2 Interrupt Mask register + TIFR2: 0x37, // Timer/Counter2 Interrupt Flag Register + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x60, // Watchdog Timer Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Bytes + EEARH: 0x41, // EEPROM Address Register Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + PORTG: 0x34, // Port G Data Register + DDRG: 0x33, // Port G Data Direction Register + PING: 0x32, // Port G Input Pins + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // Liquid Crystal Display + LCD = struct { + LCDCRA __reg + LCDCRB __reg + LCDFRR __reg + LCDCCR __reg + LCDDR18 __reg + LCDDR17 __reg + LCDDR16 __reg + LCDDR15 __reg + LCDDR13 __reg + LCDDR12 __reg + LCDDR11 __reg + LCDDR10 __reg + LCDDR8 __reg + LCDDR7 __reg + LCDDR6 __reg + LCDDR5 __reg + LCDDR3 __reg + LCDDR2 __reg + LCDDR1 __reg + LCDDR0 __reg + }{ + LCDCRA: 0xe4, // LCD Control Register A + LCDCRB: 0xe5, // LCD Control and Status Register B + LCDFRR: 0xe6, // LCD Frame Rate Register + LCDCCR: 0xe7, // LCD Contrast Control Register + LCDDR18: 0xfe, // LCD Data Register 18 + LCDDR17: 0xfd, // LCD Data Register 17 + LCDDR16: 0xfc, // LCD Data Register 16 + LCDDR15: 0xfb, // LCD Data Register 15 + LCDDR13: 0xf9, // LCD Data Register 13 + LCDDR12: 0xf8, // LCD Data Register 12 + LCDDR11: 0xf7, // LCD Data Register 11 + LCDDR10: 0xf6, // LCD Data Register 10 + LCDDR8: 0xf4, // LCD Data Register 8 + LCDDR7: 0xf3, // LCD Data Register 7 + LCDDR6: 0xf2, // LCD Data Register 6 + LCDDR5: 0xf1, // LCD Data Register 5 + LCDDR3: 0xef, // LCD Data Register 3 + LCDDR2: 0xee, // LCD Data Register 2 + LCDDR1: 0xed, // LCD Data Register 1 + LCDDR0: 0xec, // LCD Data Register 0 + } + + // Universal Serial Interface + USI = struct { + USIDR __reg + USISR __reg + USICR __reg + }{ + USIDR: 0xba, // USI Data Register + USISR: 0xb9, // USI Status Register + USICR: 0xb8, // USI Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 0 + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK1 __reg + PCMSK0 __reg + }{ + EICRA: 0x69, // External Interrupt Control Register + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + PRR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + PRR: 0x64, // Power Reduction Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0xe // Brown-out Detector trigger level + EXTENDED_RSTDISBL = 0x1 // Disable external reset + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0A: Timer/Counter0 Control Register + TCCR0A_FOC0A = 0x80 // Force Output Compare + TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0A_COM0A = 0x30 // Compare Match Output Modes + TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0A_CS0 = 0x7 // Clock Selects + + // TCNT0: Timer/Counter0 + TCNT0_TCNT0 = 0xff // Timer/Counter0 bits + + // OCR0A: Timer/Counter0 Output Compare Register + OCR0A_OCR0A = 0xff // Timer/Counter0 Output Compare A + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0 + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + + // TCNT1L: Timer/Counter1 Bytes + + // TCNT1H: Timer/Counter1 Bytes + TCNT1_TCNT1 = 0xffff // Timer/Counter1 bits + + // OCR1AL: Timer/Counter1 Output Compare Register A Bytes + + // OCR1AH: Timer/Counter1 Output Compare Register A Bytes + OCR1A_OCR1A = 0xffff // Timer/Counter1 Output Compare A + + // OCR1BL: Timer/Counter1 Output Compare Register B Bytes + + // OCR1BH: Timer/Counter1 Output Compare Register B Bytes + OCR1B_OCR1B = 0xffff // Timer/Counter1 Output Compare B + + // ICR1L: Timer/Counter1 Input Capture Register Bytes + + // ICR1H: Timer/Counter1 Input Capture Register Bytes + ICR1_ICR1 = 0xffff // Timer/Counter1 Input Capture + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2A: Timer/Counter2 Control Register + TCCR2A_FOC2A = 0x80 // Force Output Compare A + TCCR2A_WGM20 = 0x40 // Waveform Generation Mode + TCCR2A_COM2A = 0x30 // Compare Output Mode bits + TCCR2A_WGM21 = 0x8 // Waveform Generation Mode + TCCR2A_CS2 = 0x7 // Clock Select bits + + // TCNT2: Timer/Counter2 + TCNT2_TCNT2 = 0xff // Timer/Counter2 bits + + // OCR2A: Timer/Counter2 Output Compare Register + OCR2A_OCR2A = 0xff // Timer/Counter2 Output Compare A + + // TIMSK2: Timer/Counter2 Interrupt Mask register + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter2 Interrupt Flag Register + TIFR2_OCF2A = 0x2 // Timer/Counter2 Output Compare Flag 2 + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x10 // Enable External Clock Interrupt + ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for EEPROM: EEPROM +const ( + // EEARL: EEPROM Address Register Bytes + + // EEARH: EEPROM Address Register Bytes + EEAR_EEAR = 0x1ff // EEPROM Address Bits + + // EEDR: EEPROM Data Register + EEDR_EEDR = 0xff // EEPROM Data Bits + + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPDR: SPI Data Register + SPDR_SPDR = 0xff // SPI Data bits +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for LCD: Liquid Crystal Display +const ( + // LCDCRA: LCD Control Register A + LCDCRA_LCDEN = 0x80 // LCD Enable + LCDCRA_LCDAB = 0x40 // LCD A or B waveform + LCDCRA_LCDIF = 0x10 // LCD Interrupt Flag + LCDCRA_LCDIE = 0x8 // LCD Interrupt Enable + LCDCRA_LCDBD = 0x4 // LCD Buffer Disable + LCDCRA_LCDCCD = 0x2 // LCD Contrast Control Disable + LCDCRA_LCDBL = 0x1 // LCD Blanking + + // LCDCRB: LCD Control and Status Register B + LCDCRB_LCDCS = 0x80 // LCD CLock Select + LCDCRB_LCD2B = 0x40 // LCD 1/2 Bias Select + LCDCRB_LCDMUX = 0x30 // LCD Mux Selects + LCDCRB_LCDPM = 0x7 // LCD Port Masks + + // LCDFRR: LCD Frame Rate Register + LCDFRR_LCDPS = 0x70 // LCD Prescaler Selects + LCDFRR_LCDCD = 0x7 // LCD Clock Dividers + + // LCDCCR: LCD Contrast Control Register + LCDCCR_LCDDC = 0xe0 // LCD Display Configuration Bits + LCDCCR_LCDMDT = 0x10 // LCD Maximum Drive Time + LCDCCR_LCDCC = 0xf // LCD Contrast Controls +) + +// Bitfields for USI: Universal Serial Interface +const ( + // USIDR: USI Data Register + USIDR_USIDR = 0xff // USI Data bits + + // USISR: USI Status Register + USISR_USISIF = 0x80 // Start Condition Interrupt Flag + USISR_USIOIF = 0x40 // Counter Overflow Interrupt Flag + USISR_USIPF = 0x20 // Stop Condition Flag + USISR_USIDC = 0x10 // Data Output Collision + USISR_USICNT = 0xf // USI Counter Value Bits + + // USICR: USI Control Register + USICR_USISIE = 0x80 // Start Condition Interrupt Enable + USICR_USIOIE = 0x40 // Counter Overflow Interrupt Enable + USICR_USIWM = 0x30 // USI Wire Mode Bits + USICR_USICS = 0xc // USI Clock Source Select Bits + USICR_USICLK = 0x2 // Clock Strobe + USICR_USITC = 0x1 // Toggle Clock Port Pin +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCL: ADC Data Register Bytes + + // ADCH: ADC Data Register Bytes + ADC_ADC = 0x3ff // ADC Data Bits + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for USART: USART +const ( + // UDR0: USART I/O Data Register + UDR0_UDR0 = 0xff // USART I/O Data bits + + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmit Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data OverRun + UCSR0A_UPE0 = 0x4 // USART Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART Transmission Speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data Register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0x40 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity + + // UBRR0L: USART Baud Rate Register Bytes + + // UBRR0H: USART Baud Rate Register Bytes + UBRR0_UBRR0 = 0xfff // USART Baud Rate bits +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register + EICRA_ISC01 = 0x2 // External Interrupt Sense Control 0 Bit 1 + EICRA_ISC00 = 0x1 // External Interrupt Sense Control 0 Bit 0 + + // EIMSK: External Interrupt Mask Register + EIMSK_PCIE = 0x30 // Pin Change Interrupt Enables + EIMSK_INT0 = 0x1 // External Interrupt Request 0 Enable + + // EIFR: External Interrupt Flag Register + EIFR_PCIF = 0x30 // Pin Change Interrupt Flags + EIFR_INTF0 = 0x1 // External Interrupt Flag 0 + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // PRR: Power Reduction Register + PRR_PRLCD = 0x10 // Power Reduction LCD + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR2 = 0xff // General Purpose Bits + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR1 = 0xff // General Purpose Bits + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR0 = 0xff // General Purpose Bits +) diff --git a/src/device/avr/atmega169pa.ld b/src/device/avr/atmega169pa.ld new file mode 100644 index 00000000..86aab480 --- /dev/null +++ b/src/device/avr/atmega169pa.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega169PA.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_size = 0x400; +__num_isrs = 23; diff --git a/src/device/avr/atmega16a.go b/src/device/avr/atmega16a.go new file mode 100644 index 00000000..8ff760db --- /dev/null +++ b/src/device/avr/atmega16a.go @@ -0,0 +1,553 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega16A.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega16a + +// Device information for the ATmega16A. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega16A" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_TIMER2_COMP = 3 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 4 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 5 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 6 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 7 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 8 // Timer/Counter1 Overflow + IRQ_TIMER0_OVF = 9 // Timer/Counter0 Overflow + IRQ_SPI_STC = 10 // Serial Transfer Complete + IRQ_USART_RXC = 11 // USART, Rx Complete + IRQ_USART_UDRE = 12 // USART Data Register Empty + IRQ_USART_TXC = 13 // USART, Tx Complete + IRQ_ADC = 14 // ADC Conversion Complete + IRQ_EE_RDY = 15 // EEPROM Ready + IRQ_ANA_COMP = 16 // Analog Comparator + IRQ_TWI = 17 // 2-wire Serial Interface + IRQ_INT2 = 18 // External Interrupt Request 2 + IRQ_TIMER0_COMP = 19 // Timer/Counter0 Compare Match + IRQ_SPM_RDY = 20 // Store Program Memory Ready + IRQ_max = 20 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + HIGH __reg + LOW __reg + }{ + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0 __reg + TCNT0 __reg + OCR0 __reg + }{ + TCCR0: 0x53, // Timer/Counter Control Register + TCNT0: 0x52, // Timer/Counter 0 Register + OCR0: 0x5c, // Output Compare 0 Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TCCR1A: 0x4f, // Timer/Counter1 Control Register A + TCCR1B: 0x4e, // Timer/Counter1 Control Register B + TCNT1L: 0x4c, // Timer/Counter1 Bytes + TCNT1H: 0x4c, // Timer/Counter1 Bytes + OCR1AL: 0x4a, // Timer/Counter1 Output Compare Register Bytes + OCR1AH: 0x4a, // Timer/Counter1 Output Compare Register Bytes + OCR1BL: 0x48, // Timer/Counter1 Output Compare Register Bytes + OCR1BH: 0x48, // Timer/Counter1 Output Compare Register Bytes + ICR1L: 0x46, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x46, // Timer/Counter1 Input Capture Register Bytes + } + + // External Interrupts + EXINT = struct { + GICR __reg + GIFR __reg + }{ + GICR: 0x5b, // General Interrupt Control Register + GIFR: 0x5a, // General Interrupt Flag Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x3e, // EEPROM Address Register Bytes + EEARH: 0x3e, // EEPROM Address Register Bytes + EEDR: 0x3d, // EEPROM Data Register + EECR: 0x3c, // EEPROM Control Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x51, // Oscillator Calibration Value + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2 __reg + TCNT2 __reg + OCR2 __reg + ASSR __reg + }{ + TCCR2: 0x45, // Timer/Counter2 Control Register + TCNT2: 0x44, // Timer/Counter2 + OCR2: 0x43, // Timer/Counter2 Output Compare Register + ASSR: 0x42, // Asynchronous Status Register + } + + // Serial Peripheral Interface + SPI = struct { + SPDR __reg + SPSR __reg + SPCR __reg + }{ + SPDR: 0x2f, // SPI Data Register + SPSR: 0x2e, // SPI Status Register + SPCR: 0x2d, // SPI Control Register + } + + // USART + USART = struct { + UDR __reg + UCSRA __reg + UCSRB __reg + UCSRC __reg + UBRRL __reg + UBRRH __reg + }{ + UDR: 0x2c, // USART I/O Data Register + UCSRA: 0x2b, // USART Control and Status Register A + UCSRB: 0x2a, // USART Control and Status Register B + UCSRC: 0x40, // USART Control and Status Register C + UBRRL: 0x3f, // USART Baud Rate Register + UBRRH: 0x3f, // USART Baud Rate Register + } + + // Two Wire Serial Interface + TWI = struct { + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWBR: 0x20, // TWI Bit Rate register + TWCR: 0x56, // TWI Control Register + TWSR: 0x21, // TWI Status Register + TWDR: 0x23, // TWI Data register + TWAR: 0x22, // TWI (Slave) Address register + } + + // Analog Comparator + AC = struct { + ACSR __reg + }{ + ACSR: 0x28, // Analog Comparator Control And Status Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + }{ + ADMUX: 0x27, // The ADC multiplexer Selection Register + ADCSRA: 0x26, // The ADC Control and Status register + ADCL: 0x24, // ADC Data Register Bytes + ADCH: 0x24, // ADC Data Register Bytes + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + }{ + PORTA: 0x3b, // Port A Data Register + DDRA: 0x3a, // Port A Data Direction Register + PINA: 0x39, // Port A Input Pins + PORTB: 0x38, // Port B Data Register + DDRB: 0x37, // Port B Data Direction Register + PINB: 0x36, // Port B Input Pins + PORTC: 0x35, // Port C Data Register + DDRC: 0x34, // Port C Data Direction Register + PINC: 0x33, // Port C Input Pins + PORTD: 0x32, // Port D Data Register + DDRD: 0x31, // Port D Data Direction Register + PIND: 0x30, // Port D Input Pins + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x41, // Watchdog Timer Control Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + HIGH_CKOPT = 0x10 // CKOPT fuse (operation dependent of CKSEL fuses) + + // LOW + LOW_BODLEVEL = 0x80 // Brownout detector trigger level + LOW_BODEN = 0x40 // Brown-out detection enabled + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0: Timer/Counter Control Register + TCCR0_FOC0 = 0x80 // Force Output Compare + TCCR0_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0_COM0 = 0x30 // Compare Match Output Modes + TCCR0_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0_CS0 = 0x7 // Clock Selects + + // TCNT0: Timer/Counter 0 Register + TCNT0_TCNT0 = 0xff // Timer/Counter 0 bits + + // OCR0: Output Compare 0 Register + OCR0_OCR0 = 0xff // Output Compare bits +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_FOC1A = 0x8 // Force Output Compare 1A + TCCR1A_FOC1B = 0x4 // Force Output Compare 1B + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCNT1L: Timer/Counter1 Bytes + + // TCNT1H: Timer/Counter1 Bytes + TCNT1_TCNT1 = 0xffff // Timer/Counter1 bits + + // OCR1AL: Timer/Counter1 Output Compare Register Bytes + + // OCR1AH: Timer/Counter1 Output Compare Register Bytes + OCR1A_OCR1A = 0xffff // Timer/Counter1 Output Compare A bits + + // OCR1BL: Timer/Counter1 Output Compare Register Bytes + + // OCR1BH: Timer/Counter1 Output Compare Register Bytes + OCR1B_OCR1B = 0xffff // Timer/Counter1 Output Compare B bits + + // ICR1L: Timer/Counter1 Input Capture Register Bytes + + // ICR1H: Timer/Counter1 Input Capture Register Bytes + ICR1_ICR1 = 0xffff // Timer/Counter1 Input Capture bits +) + +// Bitfields for EXINT: External Interrupts +const ( + // GICR: General Interrupt Control Register + GICR_INT0 = 0x40 // External Interrupt Request 0 Enable + GICR_INT1 = 0x80 // External Interrupt Request 1 Enable + GICR_INT2 = 0x20 // External Interrupt Request 2 Enable + GICR_IVSEL = 0x2 // Interrupt Vector Select + GICR_IVCE = 0x1 // Interrupt Vector Change Enable + + // GIFR: General Interrupt Flag Register + GIFR_INTF = 0xc0 // External Interrupt Flags + GIFR_INTF2 = 0x20 // External Interrupt Flag 2 +) + +// Bitfields for EEPROM: EEPROM +const ( + // EEARL: EEPROM Address Register Bytes + + // EEARH: EEPROM Address Register Bytes + EEAR_EEAR = 0x1ff // EEPROM Address bits + + // EEDR: EEPROM Data Register + EEDR_EEDR = 0xff // EEPROM Data bits + + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2: Timer/Counter2 Control Register + TCCR2_FOC2 = 0x80 // Force Output Compare + TCCR2_WGM20 = 0x40 // Waveform Genration Mode + TCCR2_COM2 = 0x30 // Compare Output Mode bits + TCCR2_WGM21 = 0x8 // Waveform Generation Mode + TCCR2_CS2 = 0x7 // Clock Select bits + + // TCNT2: Timer/Counter2 + TCNT2_TCNT2 = 0xff // Timer/Counter2 + + // OCR2: Timer/Counter2 Output Compare Register + OCR2_OCR2 = 0xff // Timer/Counter2 Output Compare bits + + // ASSR: Asynchronous Status Register + ASSR_AS2 = 0x8 // Asynchronous Timer/counter2 + ASSR_TCN2UB = 0x4 // Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // Timer/counter Control Register2 Update Busy +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPDR: SPI Data Register + SPDR_SPDR = 0xff // SPI Data bits + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects +) + +// Bitfields for USART: USART +const ( + // UDR: USART I/O Data Register + UDR_UDR = 0xff // USART I/O Data bits + + // UCSRA: USART Control and Status Register A + UCSRA_RXC = 0x80 // USART Receive Complete + UCSRA_TXC = 0x40 // USART Transmitt Complete + UCSRA_UDRE = 0x20 // USART Data Register Empty + UCSRA_FE = 0x10 // Framing Error + UCSRA_DOR = 0x8 // Data overRun + UCSRA_UPE = 0x4 // Parity Error + UCSRA_U2X = 0x2 // Double the USART transmission speed + UCSRA_MPCM = 0x1 // Multi-processor Communication Mode + + // UCSRB: USART Control and Status Register B + UCSRB_RXCIE = 0x80 // RX Complete Interrupt Enable + UCSRB_TXCIE = 0x40 // TX Complete Interrupt Enable + UCSRB_UDRIE = 0x20 // USART Data register Empty Interrupt Enable + UCSRB_RXEN = 0x10 // Receiver Enable + UCSRB_TXEN = 0x8 // Transmitter Enable + UCSRB_UCSZ2 = 0x4 // Character Size + UCSRB_RXB8 = 0x2 // Receive Data Bit 8 + UCSRB_TXB8 = 0x1 // Transmit Data Bit 8 + + // UCSRC: USART Control and Status Register C + UCSRC_URSEL = 0x80 // Register Select + UCSRC_UMSEL = 0x40 // USART Mode Select + UCSRC_UPM = 0x30 // Parity Mode Bits + UCSRC_USBS = 0x8 // Stop Bit Select + UCSRC_UCSZ = 0x6 // Character Size + UCSRC_UCPOL = 0x1 // Clock Polarity + + // UBRRL: USART Baud Rate Register + + // UBRRH: USART Baud Rate Register + UBRR_UBRR = 0xfff // USART Baud Rate bits +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWBR: TWI Bit Rate register + TWBR_TWBR = 0xff // TWI Bit Rate bits + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWDR: TWI Data register + TWDR_TWD = 0xff // TWI Data bits + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCL: ADC Data Register Bytes + + // ADCH: ADC Data Register Bytes + ADC_ADC = 0x3ff // ADC Data Bits +) + +// Bitfields for JTAG: JTAG Interface +const ( + // OCDR: On-Chip Debug Related Register in I/O Memory + OCDR_OCDR = 0xff // On-Chip Debug Register Bits +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDTOE = 0x10 // RW + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) diff --git a/src/device/avr/atmega16a.ld b/src/device/avr/atmega16a.ld new file mode 100644 index 00000000..c6cb3bf0 --- /dev/null +++ b/src/device/avr/atmega16a.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega16A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_size = 0x400; +__num_isrs = 21; diff --git a/src/device/avr/atmega16hva.go b/src/device/avr/atmega16hva.go new file mode 100644 index 00000000..74d80e42 --- /dev/null +++ b/src/device/avr/atmega16hva.go @@ -0,0 +1,560 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega16HVA.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega16hva + +// Device information for the ATmega16HVA. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega16HVA" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset + IRQ_BPINT = 1 // Battery Protection Interrupt + IRQ_VREGMON = 2 // Voltage regulator monitor interrupt + IRQ_INT0 = 3 // External Interrupt Request 0 + IRQ_INT1 = 4 // External Interrupt Request 1 + IRQ_INT2 = 5 // External Interrupt Request 2 + IRQ_WDT = 6 // Watchdog Timeout Interrupt + IRQ_TIMER1_IC = 7 // Timer 1 Input capture + IRQ_TIMER1_COMPA = 8 // Timer 1 Compare Match A + IRQ_TIMER1_COMPB = 9 // Timer 1 Compare Match B + IRQ_TIMER1_OVF = 10 // Timer 1 overflow + IRQ_TIMER0_IC = 11 // Timer 0 Input Capture + IRQ_TIMER0_COMPA = 12 // Timer 0 Comapre Match A + IRQ_TIMER0_COMPB = 13 // Timer 0 Compare Match B + IRQ_TIMER0_OVF = 14 // Timer 0 Overflow + IRQ_SPI_STC = 15 // SPI Serial transfer complete + IRQ_VADC = 16 // Voltage ADC Conversion Complete + IRQ_CCADC_CONV = 17 // Coulomb Counter ADC Conversion Complete + IRQ_CCADC_REG_CUR = 18 // Coloumb Counter ADC Regular Current + IRQ_CCADC_ACC = 19 // Coloumb Counter ADC Accumulator + IRQ_EE_READY = 20 // EEPROM Ready + IRQ_max = 20 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + LOW __reg + }{ + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog-to-Digital Converter + ADC = struct { + VADMUX __reg + VADCL __reg + VADCH __reg + VADCSR __reg + }{ + VADMUX: 0x7c, // The VADC multiplexer Selection Register + VADCL: 0x78, // VADC Data Register Bytes + VADCH: 0x78, // VADC Data Register Bytes + VADCSR: 0x7a, // The VADC Control and Status register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // Bandgap + BANDGAP = struct { + BGCRR __reg + BGCCR __reg + }{ + BGCRR: 0xd1, // Bandgap Calibration of Resistor Ladder + BGCCR: 0xd0, // Bandgap Calibration Register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + } + + // I/O Port + PORT = struct { + PORTC __reg + PINC __reg + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + }{ + PORTC: 0x28, // Port C Data Register + PINC: 0x26, // Port C Input Pins + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Data Register, Port B + DDRB: 0x24, // Data Direction Register, Port B + PINB: 0x23, // Input Pins, Port B + } + + // FET Control + FET = struct { + FCSR __reg + }{ + FCSR: 0xf0, // FET Control and Status Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control and Status Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + MCUCR __reg + MCUSR __reg + FOSCCAL __reg + OSICSR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + DIDR0 __reg + PRR0 __reg + CLKPR __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + FOSCCAL: 0x66, // Fast Oscillator Calibration Value + OSICSR: 0x37, // Oscillator Sampling Interface Control and Status Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + DIDR0: 0x7e, // Digital Input Disable Register + PRR0: 0x64, // Power Reduction Register 0 + CLKPR: 0x61, // Clock Prescale Register + } + + // Battery Protection + BATTERY_PROTECTION = struct { + BPPLR __reg + BPCR __reg + BPHCTR __reg + BPOCTR __reg + BPSCTR __reg + BPCHCD __reg + BPDHCD __reg + BPCOCD __reg + BPDOCD __reg + BPSCD __reg + BPIFR __reg + BPIMSK __reg + }{ + BPPLR: 0xfe, // Battery Protection Parameter Lock Register + BPCR: 0xfd, // Battery Protection Control Register + BPHCTR: 0xfc, // Battery Protection Short-current Timing Register + BPOCTR: 0xfb, // Battery Protection Over-current Timing Register + BPSCTR: 0xfa, // Battery Protection Short-current Timing Register + BPCHCD: 0xf9, // Battery Protection Charge-High-current Detection Level Register + BPDHCD: 0xf8, // Battery Protection Discharge-High-current Detection Level Register + BPCOCD: 0xf7, // Battery Protection Charge-Over-current Detection Level Register + BPDOCD: 0xf6, // Battery Protection Discharge-Over-current Detection Level Register + BPSCD: 0xf5, // Battery Protection Short-Circuit Detection Level Register + BPIFR: 0xf3, // Battery Protection Interrupt Flag Register + BPIMSK: 0xf2, // Battery Protection Interrupt Mask Register + } + + // EEPROM + EEPROM = struct { + EEAR __reg + EEDR __reg + EECR __reg + }{ + EEAR: 0x41, // EEPROM Read/Write Access + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1B __reg + TCCR1A __reg + TCNT1L __reg + TCNT1H __reg + OCR1A __reg + OCR1B __reg + TIMSK1 __reg + TIFR1 __reg + GTCCR __reg + TCCR0A __reg + TCCR0B __reg + TCNT0L __reg + TCNT0H __reg + OCR0A __reg + OCR0B __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1A: 0x80, // Timer/Counter 1 Control Register A + TCNT1L: 0x84, // Timer Counter 1 Bytes + TCNT1H: 0x84, // Timer Counter 1 Bytes + OCR1A: 0x88, // Output Compare Register 1A + OCR1B: 0x89, // Output Compare Register B + TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + GTCCR: 0x43, // General Timer/Counter Control Register + TCCR0A: 0x44, // Timer/Counter0 Control Register + TCCR0B: 0x45, // Timer/Counter0 Control Register + TCNT0L: 0x46, // Timer Counter 0 Bytes + TCNT0H: 0x46, // Timer Counter 0 Bytes + OCR0A: 0x48, // Output compare Register A + OCR0B: 0x49, // Output compare Register B + TIMSK0: 0x6e, // Timer/Counter Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter Interrupt Flag register + } + + // Coulomb Counter + COULOMB_COUNTER = struct { + CADCSRA __reg + CADCSRB __reg + CADICL __reg + CADICH __reg + CADAC3 __reg + CADAC2 __reg + CADAC1 __reg + CADAC0 __reg + CADRC __reg + }{ + CADCSRA: 0xe4, // CC-ADC Control and Status Register A + CADCSRB: 0xe5, // CC-ADC Control and Status Register B + CADICL: 0xe8, // CC-ADC Instantaneous Current + CADICH: 0xe8, // CC-ADC Instantaneous Current + CADAC3: 0xe3, // ADC Accumulate Current + CADAC2: 0xe2, // ADC Accumulate Current + CADAC1: 0xe1, // ADC Accumulate Current + CADAC0: 0xe0, // ADC Accumulate Current + CADRC: 0xe6, // CC-ADC Regular Current + } + + // Voltage Regulator + VOLTAGE_REGULATOR = struct { + ROCR __reg + }{ + ROCR: 0xc8, // Regulator Operating Condition Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // LOW + LOW_WDTON = 0x80 // Watch-dog Timer always on + LOW_EESAVE = 0x40 // Preserve EEPROM through the Chip Erase cycle + LOW_SPIEN = 0x20 // Serial program downloading (SPI) enabled + LOW_DWEN = 0x10 // Debug Wire enable + LOW_SELFPRGEN = 0x8 // Self Programming enable + LOW_SUT = 0x7 // Select start-up time +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // VADMUX: The VADC multiplexer Selection Register + VADMUX_VADMUX = 0xf // Analog Channel and Gain Selection Bits + + // VADCSR: The VADC Control and Status register + VADCSR_VADEN = 0x8 // VADC Enable + VADCSR_VADSC = 0x4 // VADC Satrt Conversion + VADCSR_VADCCIF = 0x2 // VADC Conversion Complete Interrupt Flag + VADCSR_VADCCIE = 0x1 // VADC Conversion Complete Interrupt Enable +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for BANDGAP: Bandgap +const ( + // BGCRR: Bandgap Calibration of Resistor Ladder + BGCRR_BGCR = 0xff // Bandgap calibration bits + + // BGCCR: Bandgap Calibration Register + BGCCR_BGD = 0x80 // Setting the BGD bit to one will disable the bandgap voltage reference. This bit must be cleared before enabling CC-ADC or V-ADC, and must remain unset while either ADC is enabled. + BGCCR_BGCC = 0x3f // BG Calibration of PTAT Current Bits +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register + EICRA_ISC2 = 0x30 // External Interrupt Sense Control 2 Bits + EICRA_ISC1 = 0xc // External Interrupt Sense Control 1 Bits + EICRA_ISC0 = 0x3 // External Interrupt Sense Control 0 Bits + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0x7 // External Interrupt Request 2 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0x7 // External Interrupt Flags +) + +// Bitfields for FET: FET Control +const ( + // FCSR: FET Control and Status Register + FCSR_DUVRD = 0x8 // Deep Under-Voltage Recovery Disable + FCSR_CPS = 0x4 // Current Protection Status + FCSR_DFE = 0x2 // Discharge FET Enable + FCSR_CFE = 0x1 // Charge FET Enable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control and Status Register + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_CTPB = 0x10 // Clear Temporary Page Buffer + SPMCSR_RFLB = 0x8 // Read Fuse and Lock Bits + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // MCUCR: MCU Control Register + MCUCR_CKOE = 0x20 // Clock Output Enable + MCUCR_PUD = 0x10 // Pull-up disable + + // MCUSR: MCU Status Register + MCUSR_OCDRF = 0x10 // OCD Reset Flag + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BODRF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // OSICSR: Oscillator Sampling Interface Control and Status Register + OSICSR_OSISEL0 = 0x10 // Oscillator Sampling Interface Select 0 + OSICSR_OSIST = 0x2 // Oscillator Sampling Interface Status + OSICSR_OSIEN = 0x1 // Oscillator Sampling Interface Enable + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // DIDR0: Digital Input Disable Register + DIDR0_PA1DID = 0x2 // When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled. + DIDR0_PA0DID = 0x1 // When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled. + + // PRR0: Power Reduction Register 0 + PRR0_PRVRM = 0x20 // Power Reduction Voltage Regulator Monitor + PRR0_PRSPI = 0x8 // Power reduction SPI + PRR0_PRTIM1 = 0x4 // Power Reduction Timer/Counter1 + PRR0_PRTIM0 = 0x2 // Power Reduction Timer/Counter0 + PRR0_PRVADC = 0x1 // Power Reduction V-ADC + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0x3 // Clock Prescaler Select Bits +) + +// Bitfields for BATTERY_PROTECTION: Battery Protection +const ( + // BPPLR: Battery Protection Parameter Lock Register + BPPLR_BPPLE = 0x2 // Battery Protection Parameter Lock Enable + BPPLR_BPPL = 0x1 // Battery Protection Parameter Lock + + // BPCR: Battery Protection Control Register + BPCR_SCD = 0x10 // Short Circuit Protection Disabled + BPCR_DOCD = 0x8 // Discharge Over-current Protection Disabled + BPCR_COCD = 0x4 // Charge Over-current Protection Disabled + BPCR_DHCD = 0x2 // Discharge High-current Protection Disable + BPCR_CHCD = 0x1 // Charge High-current Protection Disable + + // BPIFR: Battery Protection Interrupt Flag Register + BPIFR_SCIF = 0x10 // Short-circuit Protection Activated Interrupt Flag + BPIFR_DOCIF = 0x8 // Discharge Over-current Protection Activated Interrupt Flag + BPIFR_COCIF = 0x4 // Charge Over-current Protection Activated Interrupt Flag + BPIFR_DHCIF = 0x2 // Disharge High-current Protection Activated Interrupt + BPIFR_CHCIF = 0x1 // Charge High-current Protection Activated Interrupt + + // BPIMSK: Battery Protection Interrupt Mask Register + BPIMSK_SCIE = 0x10 // Short-circuit Protection Activated Interrupt Enable + BPIMSK_DOCIE = 0x8 // Discharge Over-current Protection Activated Interrupt Enable + BPIMSK_COCIE = 0x4 // Charge Over-current Protection Activated Interrupt Enable + BPIMSK_DHCIE = 0x2 // Discharger High-current Protection Activated Interrupt + BPIMSK_CHCIE = 0x1 // Charger High-current Protection Activated Interrupt +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 + EECR_EERIE = 0x8 // EEProm Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_CS = 0x7 // Clock Select1 bis + + // TCCR1A: Timer/Counter 1 Control Register A + TCCR1A_TCW1 = 0x80 // Timer/Counter Width + TCCR1A_ICEN1 = 0x40 // Input Capture Mode Enable + TCCR1A_ICNC1 = 0x20 // Input Capture Noise Canceler + TCCR1A_ICES1 = 0x10 // Input Capture Edge Select + TCCR1A_ICS1 = 0x8 // Input Capture Select + TCCR1A_WGM10 = 0x1 // Waveform Generation Mode + + // TIMSK1: Timer/Counter Interrupt Mask Register + TIMSK1_ICIE1 = 0x8 // Timer/Counter n Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x8 // Timer/Counter 1 Input Capture Flag + TIFR1_OCF1B = 0x4 // Timer/Counter1 Output Compare Flag B + TIFR1_OCF1A = 0x2 // Timer/Counter1 Output Compare Flag A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // GTCCR: General Timer/Counter Control Register + GTCCR_TSM = 0x80 // Timer/Counter Synchronization Mode + GTCCR_PSRSYNC = 0x1 // Prescaler Reset + + // TCCR0A: Timer/Counter0 Control Register + TCCR0A_TCW0 = 0x80 // Timer/Counter Width + TCCR0A_ICEN0 = 0x40 // Input Capture Mode Enable + TCCR0A_ICNC0 = 0x20 // Input Capture Noise Canceler + TCCR0A_ICES0 = 0x10 // Input Capture Edge Select + TCCR0A_ICS0 = 0x8 // Input Capture Select + TCCR0A_WGM00 = 0x1 // Clock Select0 bit 0 + + // TCCR0B: Timer/Counter0 Control Register + TCCR0B_CS02 = 0x4 // Clock Select0 bit 2 + TCCR0B_CS01 = 0x2 // Clock Select0 bit 1 + TCCR0B_CS00 = 0x1 // Clock Select0 bit 0 + + // TIMSK0: Timer/Counter Interrupt Mask Register + TIMSK0_ICIE0 = 0x8 // Timer/Counter n Input Capture Interrupt Enable + TIMSK0_OCIE0B = 0x4 // Output Compare Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Output Compare Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Overflow Interrupt Enable + + // TIFR0: Timer/Counter Interrupt Flag register + TIFR0_ICF0 = 0x8 // Timer/Counter Interrupt Flag Register + TIFR0_OCF0B = 0x4 // Output Compare Flag + TIFR0_OCF0A = 0x2 // Output Compare Flag + TIFR0_TOV0 = 0x1 // Overflow Flag +) + +// Bitfields for COULOMB_COUNTER: Coulomb Counter +const ( + // CADCSRA: CC-ADC Control and Status Register A + CADCSRA_CADEN = 0x80 // When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled. + CADCSRA_CADPOL = 0x40 + CADCSRA_CADUB = 0x20 // CC_ADC Update Busy + CADCSRA_CADAS = 0x18 // CC_ADC Accumulate Current Select Bits + CADCSRA_CADSI = 0x6 // The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. + CADCSRA_CADSE = 0x1 // When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode. + + // CADCSRB: CC-ADC Control and Status Register B + CADCSRB_CADACIE = 0x40 + CADCSRB_CADRCIE = 0x20 // Regular Current Interrupt Enable + CADCSRB_CADICIE = 0x10 // CAD Instantenous Current Interrupt Enable + CADCSRB_CADACIF = 0x4 // CC-ADC Accumulate Current Interrupt Flag + CADCSRB_CADRCIF = 0x2 // CC-ADC Accumulate Current Interrupt Flag + CADCSRB_CADICIF = 0x1 // CC-ADC Instantaneous Current Interrupt Flag +) + +// Bitfields for VOLTAGE_REGULATOR: Voltage Regulator +const ( + // ROCR: Regulator Operating Condition Register + ROCR_ROCS = 0x80 // ROC Status + ROCR_ROCWIF = 0x2 // ROC Warning Interrupt Flag + ROCR_ROCWIE = 0x1 // ROC Warning Interrupt Enable +) diff --git a/src/device/avr/atmega16hva.ld b/src/device/avr/atmega16hva.ld new file mode 100644 index 00000000..666a915e --- /dev/null +++ b/src/device/avr/atmega16hva.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega16HVA.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_size = 0x200; +__num_isrs = 21; diff --git a/src/device/avr/atmega16hvb.go b/src/device/avr/atmega16hvb.go new file mode 100644 index 00000000..bbdf4593 --- /dev/null +++ b/src/device/avr/atmega16hvb.go @@ -0,0 +1,796 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega16HVB.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega16hvb + +// Device information for the ATmega16HVB. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega16HVB" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset + IRQ_BPINT = 1 // Battery Protection Interrupt + IRQ_VREGMON = 2 // Voltage regulator monitor interrupt + IRQ_INT0 = 3 // External Interrupt Request 0 + IRQ_INT1 = 4 // External Interrupt Request 1 + IRQ_INT2 = 5 // External Interrupt Request 2 + IRQ_INT3 = 6 // External Interrupt Request 3 + IRQ_PCINT0 = 7 // Pin Change Interrupt 0 + IRQ_PCINT1 = 8 // Pin Change Interrupt 1 + IRQ_WDT = 9 // Watchdog Timeout Interrupt + IRQ_BGSCD = 10 // Bandgap Buffer Short Circuit Detected + IRQ_CHDET = 11 // Charger Detect + IRQ_TIMER1_IC = 12 // Timer 1 Input capture + IRQ_TIMER1_COMPA = 13 // Timer 1 Compare Match A + IRQ_TIMER1_COMPB = 14 // Timer 1 Compare Match B + IRQ_TIMER1_OVF = 15 // Timer 1 overflow + IRQ_TIMER0_IC = 16 // Timer 0 Input Capture + IRQ_TIMER0_COMPA = 17 // Timer 0 Comapre Match A + IRQ_TIMER0_COMPB = 18 // Timer 0 Compare Match B + IRQ_TIMER0_OVF = 19 // Timer 0 Overflow + IRQ_TWIBUSCD = 20 // Two-Wire Bus Connect/Disconnect + IRQ_TWI = 21 // Two-Wire Serial Interface + IRQ_SPI_STC = 22 // SPI Serial transfer complete + IRQ_VADC = 23 // Voltage ADC Conversion Complete + IRQ_CCADC_CONV = 24 // Coulomb Counter ADC Conversion Complete + IRQ_CCADC_REG_CUR = 25 // Coloumb Counter ADC Regular Current + IRQ_CCADC_ACC = 26 // Coloumb Counter ADC Accumulator + IRQ_EE_READY = 27 // EEPROM Ready + IRQ_SPM = 28 // SPM Ready + IRQ_max = 28 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + LOW __reg + HIGH __reg + }{ + LOW: 0x0, + HIGH: 0x1, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog-to-Digital Converter + ADC = struct { + VADMUX __reg + VADCL __reg + VADCH __reg + VADCSR __reg + }{ + VADMUX: 0x7c, // The VADC multiplexer Selection Register + VADCL: 0x78, // VADC Data Register Bytes + VADCH: 0x78, // VADC Data Register Bytes + VADCSR: 0x7a, // The VADC Control and Status register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // FET Control + FET = struct { + FCSR __reg + }{ + FCSR: 0xf0, // FET Control and Status Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access + EEARH: 0x41, // EEPROM Read/Write Access + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Coulomb Counter + COULOMB_COUNTER = struct { + CADCSRA __reg + CADCSRB __reg + CADCSRC __reg + CADICL __reg + CADICH __reg + CADAC3 __reg + CADAC2 __reg + CADAC1 __reg + CADAC0 __reg + CADRCC __reg + CADRDC __reg + }{ + CADCSRA: 0xe6, // CC-ADC Control and Status Register A + CADCSRB: 0xe7, // CC-ADC Control and Status Register B + CADCSRC: 0xe8, // CC-ADC Control and Status Register C + CADICL: 0xe4, // CC-ADC Instantaneous Current + CADICH: 0xe4, // CC-ADC Instantaneous Current + CADAC3: 0xe3, // ADC Accumulate Current + CADAC2: 0xe2, // ADC Accumulate Current + CADAC1: 0xe1, // ADC Accumulate Current + CADAC0: 0xe0, // ADC Accumulate Current + CADRCC: 0xe9, // CC-ADC Regular Charge Current + CADRDC: 0xea, // CC-ADC Regular Discharge Current + } + + // Two Wire Serial Interface + TWI = struct { + TWBCSR __reg + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWBCSR: 0xbe, // TWI Bus Control and Status Register + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCICR __reg + PCIFR __reg + PCMSK1 __reg + PCMSK0 __reg + }{ + EICRA: 0x69, // External Interrupt Control Register + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + PCMSK1: 0x6c, // Pin Change Enable Mask Register 1 + PCMSK0: 0x6b, // Pin Change Enable Mask Register 0 + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1B __reg + TCCR1A __reg + TCNT1L __reg + TCNT1H __reg + OCR1A __reg + OCR1B __reg + TIMSK1 __reg + TIFR1 __reg + TCCR0B __reg + TCCR0A __reg + TCNT0L __reg + TCNT0H __reg + OCR0A __reg + OCR0B __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1A: 0x80, // Timer/Counter 1 Control Register A + TCNT1L: 0x84, // Timer Counter 1 Bytes + TCNT1H: 0x84, // Timer Counter 1 Bytes + OCR1A: 0x88, // Output Compare Register 1A + OCR1B: 0x89, // Output Compare Register B + TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR0B: 0x45, // Timer/Counter0 Control Register B + TCCR0A: 0x44, // Timer/Counter 0 Control Register A + TCNT0L: 0x46, // Timer Counter 0 Bytes + TCNT0H: 0x46, // Timer Counter 0 Bytes + OCR0A: 0x48, // Output Compare Register A + OCR0B: 0x49, // Output Compare Register B + TIMSK0: 0x6e, // Timer/Counter Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter Interrupt Flag register + } + + // Cell Balancing + CELL_BALANCING = struct { + CBCR __reg + }{ + CBCR: 0xf1, // Cell Balancing Control Register + } + + // Battery Protection + BATTERY_PROTECTION = struct { + BPPLR __reg + BPCR __reg + BPHCTR __reg + BPOCTR __reg + BPSCTR __reg + BPCHCD __reg + BPDHCD __reg + BPCOCD __reg + BPDOCD __reg + BPSCD __reg + BPIFR __reg + BPIMSK __reg + }{ + BPPLR: 0xfe, // Battery Protection Parameter Lock Register + BPCR: 0xfd, // Battery Protection Control Register + BPHCTR: 0xfc, // Battery Protection Short-current Timing Register + BPOCTR: 0xfb, // Battery Protection Over-current Timing Register + BPSCTR: 0xfa, // Battery Protection Short-current Timing Register + BPCHCD: 0xf9, // Battery Protection Charge-High-current Detection Level Register + BPDHCD: 0xf8, // Battery Protection Discharge-High-current Detection Level Register + BPCOCD: 0xf7, // Battery Protection Charge-Over-current Detection Level Register + BPDOCD: 0xf6, // Battery Protection Discharge-Over-current Detection Level Register + BPSCD: 0xf5, // Battery Protection Short-Circuit Detection Level Register + BPIFR: 0xf3, // Battery Protection Interrupt Flag Register + BPIMSK: 0xf2, // Battery Protection Interrupt Mask Register + } + + // Charger Detect + CHARGER_DETECT = struct { + CHGDCSR __reg + }{ + CHGDCSR: 0xd4, // Charger Detect Control and Status Register + } + + // Voltage Regulator + VOLTAGE_REGULATOR = struct { + ROCR __reg + }{ + ROCR: 0xc8, // Regulator Operating Condition Register + } + + // Bandgap + BANDGAP = struct { + BGCSR __reg + BGCRR __reg + BGCCR __reg + }{ + BGCSR: 0xd2, // Bandgap Control and Status Register + BGCRR: 0xd1, // Bandgap Calibration of Resistor Ladder + BGCCR: 0xd0, // Bandgap Calibration Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + MCUCR __reg + MCUSR __reg + FOSCCAL __reg + OSICSR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + DIDR0 __reg + PRR0 __reg + CLKPR __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + FOSCCAL: 0x66, // Fast Oscillator Calibration Value + OSICSR: 0x37, // Oscillator Sampling Interface Control and Status Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + DIDR0: 0x7e, // Digital Input Disable Register + PRR0: 0x64, // Power Reduction Register 0 + CLKPR: 0x61, // Clock Prescale Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + PINC __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + PINC: 0x26, // Port C Input Pins + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control and Status Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // LOW + LOW_WDTON = 0x80 // Watch-dog Timer always on + LOW_EESAVE = 0x40 // Preserve EEPROM through the Chip Erase cycle + LOW_SPIEN = 0x20 // Serial program downloading (SPI) enabled + LOW_SUT = 0x1c // Select start-up time + LOW_OSCSEL = 0x3 // Oscillator select + + // HIGH + HIGH_CKDIV8 = 0x10 // Clock Divide mode + HIGH_DWEN = 0x8 // Debug Wire enable + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // VADMUX: The VADC multiplexer Selection Register + VADMUX_VADMUX = 0xf // Analog Channel and Gain Selection Bits + + // VADCL: VADC Data Register Bytes + + // VADCH: VADC Data Register Bytes + VADC_VADC = 0xfff // VADC Data bits + + // VADCSR: The VADC Control and Status register + VADCSR_VADEN = 0x8 // VADC Enable + VADCSR_VADSC = 0x4 // VADC Satrt Conversion + VADCSR_VADCCIF = 0x2 // VADC Conversion Complete Interrupt Flag + VADCSR_VADCCIE = 0x1 // VADC Conversion Complete Interrupt Enable +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for FET: FET Control +const ( + // FCSR: FET Control and Status Register + FCSR_DUVRD = 0x8 // Deep Under-Voltage Recovery Disable + FCSR_CPS = 0x4 // Current Protection Status + FCSR_DFE = 0x2 // Discharge FET Enable + FCSR_CFE = 0x1 // Charge FET Enable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPDR: SPI Data Register + SPDR_SPDR = 0xff // SPI Data bits +) + +// Bitfields for EEPROM: EEPROM +const ( + // EEARL: EEPROM Read/Write Access + + // EEARH: EEPROM Read/Write Access + EEAR_EEAR = 0x3ff // EEPROM Address bits + + // EEDR: EEPROM Data Register + EEDR_EEDR = 0xff // EEPROM Data bits + + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 + EECR_EERIE = 0x8 // EEProm Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for COULOMB_COUNTER: Coulomb Counter +const ( + // CADCSRA: CC-ADC Control and Status Register A + CADCSRA_CADEN = 0x80 // When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled. + CADCSRA_CADPOL = 0x40 + CADCSRA_CADUB = 0x20 // CC_ADC Update Busy + CADCSRA_CADAS = 0x18 // CC_ADC Accumulate Current Select Bits + CADCSRA_CADSI = 0x6 // The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. + CADCSRA_CADSE = 0x1 // When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode. + + // CADCSRB: CC-ADC Control and Status Register B + CADCSRB_CADACIE = 0x40 + CADCSRB_CADRCIE = 0x20 // Regular Current Interrupt Enable + CADCSRB_CADICIE = 0x10 // CAD Instantenous Current Interrupt Enable + CADCSRB_CADACIF = 0x4 // CC-ADC Accumulate Current Interrupt Flag + CADCSRB_CADRCIF = 0x2 // CC-ADC Accumulate Current Interrupt Flag + CADCSRB_CADICIF = 0x1 // CC-ADC Instantaneous Current Interrupt Flag + + // CADCSRC: CC-ADC Control and Status Register C + CADCSRC_CADVSE = 0x1 // CC-ADC Voltage Scaling Enable + + // CADICL: CC-ADC Instantaneous Current + + // CADICH: CC-ADC Instantaneous Current + CADIC_CADIC = 0xffff // CC-ADC Instantaneous Current + + // CADAC3: ADC Accumulate Current + CADAC3_CADAC = 0xff // ADC accumulate current bits + + // CADAC2: ADC Accumulate Current + CADAC2_CADAC = 0xff // ADC accumulate current bits + + // CADAC1: ADC Accumulate Current + CADAC1_CADAC = 0xfc // ADC accumulate current bits + CADAC1_CADAC0 = 0x3 // ADC accumulate current bits + + // CADAC0: ADC Accumulate Current + CADAC0_CADAC0 = 0xff // ADC accumulate current bits + + // CADRCC: CC-ADC Regular Charge Current + CADRCC_CADRCC = 0xff // CC-ADC Regular Charge Current + + // CADRDC: CC-ADC Regular Discharge Current + CADRDC_CADRDC = 0xff // CC-ADC Regular Discharge Current +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWBCSR: TWI Bus Control and Status Register + TWBCSR_TWBCIF = 0x80 // TWI Bus Connect/Disconnect Interrupt Flag + TWBCSR_TWBCIE = 0x40 // TWI Bus Connect/Disconnect Interrupt Enable + TWBCSR_TWBDT = 0x6 // TWI Bus Disconnect Time-out Period + TWBCSR_TWBCIP = 0x1 // TWI Bus Connect/Disconnect Interrupt Polarity + + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWBR: TWI Bit Rate register + TWBR_TWBR = 0xff // TWI Bit Rate bits + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWDR: TWI Data register + TWDR_TWD = 0xff // TWI Data Bits + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register + EICRA_ISC3 = 0xc0 // External Interrupt Sense Control 3 Bits + EICRA_ISC2 = 0x30 // External Interrupt Sense Control 2 Bits + EICRA_ISC1 = 0xc // External Interrupt Sense Control 1 Bits + EICRA_ISC0 = 0x3 // External Interrupt Sense Control 0 Bits + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xf // External Interrupt Request 3 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xf // External Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0x3 // Pin Change Interrupt Enables + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0x3 // Pin Change Interrupt Flags + + // PCMSK1: Pin Change Enable Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Enable Mask + + // PCMSK0: Pin Change Enable Mask Register 0 + PCMSK0_PCINT = 0xf // Pin Change Enable Mask +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_CS = 0x7 // Clock Select1 bis + + // TCCR1A: Timer/Counter 1 Control Register A + TCCR1A_TCW1 = 0x80 // Timer/Counter Width + TCCR1A_ICEN1 = 0x40 // Input Capture Mode Enable + TCCR1A_ICNC1 = 0x20 // Input Capture Noise Canceler + TCCR1A_ICES1 = 0x10 // Input Capture Edge Select + TCCR1A_ICS1 = 0x8 // Input Capture Select + TCCR1A_WGM10 = 0x1 // Waveform Generation Mode + + // TCNT1L: Timer Counter 1 Bytes + + // TCNT1H: Timer Counter 1 Bytes + TCNT1_TCNT1 = 0xffff // Timer Counter 1 bits + + // OCR1A: Output Compare Register 1A + OCR1A_OCR1A = 0xff // Output Compare 1 A bits + + // OCR1B: Output Compare Register B + OCR1B_OCR1B = 0xff // Output Compare 1 B bits + + // TIMSK1: Timer/Counter Interrupt Mask Register + TIMSK1_ICIE1 = 0x8 // Timer/Counter n Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x8 // Timer/Counter 1 Input Capture Flag + TIFR1_OCF1B = 0x4 // Timer/Counter1 Output Compare Flag B + TIFR1_OCF1A = 0x2 // Timer/Counter1 Output Compare Flag A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR0B: Timer/Counter0 Control Register B + TCCR0B_CS02 = 0x4 // Clock Select0 bit 2 + TCCR0B_CS01 = 0x2 // Clock Select0 bit 1 + TCCR0B_CS00 = 0x1 // Clock Select0 bit 0 + + // TCCR0A: Timer/Counter 0 Control Register A + TCCR0A_TCW0 = 0x80 // Timer/Counter Width + TCCR0A_ICEN0 = 0x40 // Input Capture Mode Enable + TCCR0A_ICNC0 = 0x20 // Input Capture Noise Canceler + TCCR0A_ICES0 = 0x10 // Input Capture Edge Select + TCCR0A_ICS0 = 0x8 // Input Capture Select + TCCR0A_WGM00 = 0x1 // Waveform Generation Mode + + // TCNT0L: Timer Counter 0 Bytes + + // TCNT0H: Timer Counter 0 Bytes + TCNT0_TCNT0 = 0xffff // Timer Counter 0 bits + + // OCR0A: Output Compare Register A + OCR0A_OCR0A = 0xff // Output Compare 0 A bits + + // OCR0B: Output Compare Register B + OCR0B_OCR0B = 0xff // Output Compare 0 B bits + + // TIMSK0: Timer/Counter Interrupt Mask Register + TIMSK0_ICIE0 = 0x8 // Timer/Counter n Input Capture Interrupt Enable + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter Interrupt Flag register + TIFR0_ICF0 = 0x8 // Timer/Counter 0 Input Capture Flag + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for CELL_BALANCING: Cell Balancing +const ( + // CBCR: Cell Balancing Control Register + CBCR_CBE = 0xf // Cell Balancing Enables +) + +// Bitfields for BATTERY_PROTECTION: Battery Protection +const ( + // BPPLR: Battery Protection Parameter Lock Register + BPPLR_BPPLE = 0x2 // Battery Protection Parameter Lock Enable + BPPLR_BPPL = 0x1 // Battery Protection Parameter Lock + + // BPCR: Battery Protection Control Register + BPCR_EPID = 0x20 // External Protection Input Disable + BPCR_SCD = 0x10 // Short Circuit Protection Disabled + BPCR_DOCD = 0x8 // Discharge Over-current Protection Disabled + BPCR_COCD = 0x4 // Charge Over-current Protection Disabled + BPCR_DHCD = 0x2 // Discharge High-current Protection Disable + BPCR_CHCD = 0x1 // Charge High-current Protection Disable + + // BPHCTR: Battery Protection Short-current Timing Register + BPHCTR_HCPT = 0x3f // Battery Protection Short-current Timing bits + + // BPOCTR: Battery Protection Over-current Timing Register + BPOCTR_OCPT = 0x3f // Battery Protection Over-current Timing bits + + // BPSCTR: Battery Protection Short-current Timing Register + BPSCTR_SCPT = 0x7f // Battery Protection Short-current Timing bits + + // BPCHCD: Battery Protection Charge-High-current Detection Level Register + BPCHCD_CHCDL = 0xff // Battery Protection Charge-High-current Detection Level bits + + // BPDHCD: Battery Protection Discharge-High-current Detection Level Register + BPDHCD_DHCDL = 0xff // Battery Protection Discharge-High-current Detection Level bits + + // BPCOCD: Battery Protection Charge-Over-current Detection Level Register + BPCOCD_COCDL = 0xff // Battery Protection Charge-Over-current Detection Level bits + + // BPDOCD: Battery Protection Discharge-Over-current Detection Level Register + BPDOCD_DOCDL = 0xff // Battery Protection Discharge-Over-current Detection Level bits + + // BPSCD: Battery Protection Short-Circuit Detection Level Register + BPSCD_SCDL = 0xff // Battery Protection Short-Circuit Detection Level Register bits + + // BPIFR: Battery Protection Interrupt Flag Register + BPIFR_SCIF = 0x10 // Short-circuit Protection Activated Interrupt Flag + BPIFR_DOCIF = 0x8 // Discharge Over-current Protection Activated Interrupt Flag + BPIFR_COCIF = 0x4 // Charge Over-current Protection Activated Interrupt Flag + BPIFR_DHCIF = 0x2 // Disharge High-current Protection Activated Interrupt + BPIFR_CHCIF = 0x1 // Charge High-current Protection Activated Interrupt + + // BPIMSK: Battery Protection Interrupt Mask Register + BPIMSK_SCIE = 0x10 // Short-circuit Protection Activated Interrupt Enable + BPIMSK_DOCIE = 0x8 // Discharge Over-current Protection Activated Interrupt Enable + BPIMSK_COCIE = 0x4 // Charge Over-current Protection Activated Interrupt Enable + BPIMSK_DHCIE = 0x2 // Discharger High-current Protection Activated Interrupt + BPIMSK_CHCIE = 0x1 // Charger High-current Protection Activated Interrupt +) + +// Bitfields for CHARGER_DETECT: Charger Detect +const ( + // CHGDCSR: Charger Detect Control and Status Register + CHGDCSR_BATTPVL = 0x10 // BATT Pin Voltage Level + CHGDCSR_CHGDISC = 0xc // Charger Detect Interrupt Sense Control + CHGDCSR_CHGDIF = 0x2 // Charger Detect Interrupt Flag + CHGDCSR_CHGDIE = 0x1 // Charger Detect Interrupt Enable +) + +// Bitfields for VOLTAGE_REGULATOR: Voltage Regulator +const ( + // ROCR: Regulator Operating Condition Register + ROCR_ROCS = 0x80 // ROC Status + ROCR_ROCD = 0x10 // ROC Disable + ROCR_ROCWIF = 0x2 // ROC Warning Interrupt Flag + ROCR_ROCWIE = 0x1 // ROC Warning Interrupt Enable +) + +// Bitfields for BANDGAP: Bandgap +const ( + // BGCSR: Bandgap Control and Status Register + BGCSR_BGD = 0x20 // Bandgap Disable + BGCSR_BGSCDE = 0x10 // Bandgap Short Circuit Detection Enabled + BGCSR_BGSCDIF = 0x2 // Bandgap Short Circuit Detection Interrupt Flag + BGCSR_BGSCDIE = 0x1 // Bandgap Short Circuit Detection Interrupt Enable + + // BGCRR: Bandgap Calibration of Resistor Ladder + BGCRR_BGCR = 0xff // Bandgap Calibration of Resistor Ladder Bits + + // BGCCR: Bandgap Calibration Register + BGCCR_BGCC = 0x3f // BG Calibration of PTAT Current Bits +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // MCUCR: MCU Control Register + MCUCR_CKOE = 0x20 // Clock Output Enable + MCUCR_PUD = 0x10 // Pull-up disable + MCUCR_IVSEL = 0x2 // Interrupt Vector Select + MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable + + // MCUSR: MCU Status Register + MCUSR_OCDRF = 0x10 // OCD Reset Flag + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BODRF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // FOSCCAL: Fast Oscillator Calibration Value + FOSCCAL_FCAL = 0xff // Fast Oscillator Calibration Value + + // OSICSR: Oscillator Sampling Interface Control and Status Register + OSICSR_OSISEL0 = 0x10 // Oscillator Sampling Interface Select 0 + OSICSR_OSIST = 0x2 // Oscillator Sampling Interface Status + OSICSR_OSIEN = 0x1 // Oscillator Sampling Interface Enable + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR2 = 0xff // General Purpose IO bits + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR1 = 0xff // General Purpose IO bits + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR0 = 0xff // General Purpose IO bits + + // DIDR0: Digital Input Disable Register + DIDR0_PA1DID = 0x2 // When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled. + DIDR0_PA0DID = 0x1 // When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled. + + // PRR0: Power Reduction Register 0 + PRR0_PRTWI = 0x40 // Power Reduction TWI + PRR0_PRVRM = 0x20 // Power Reduction Voltage Regulator Monitor + PRR0_PRSPI = 0x8 // Power reduction SPI + PRR0_PRTIM1 = 0x4 // Power Reduction Timer/Counter1 + PRR0_PRTIM0 = 0x2 // Power Reduction Timer/Counter0 + PRR0_PRVADC = 0x1 // Power Reduction V-ADC + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0x3 // Clock Prescaler Select Bits +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control and Status Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read-While-Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read-While-Write Section Read Enable + SPMCSR_LBSET = 0x8 // Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) diff --git a/src/device/avr/atmega16hvb.ld b/src/device/avr/atmega16hvb.ld new file mode 100644 index 00000000..d451651f --- /dev/null +++ b/src/device/avr/atmega16hvb.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega16HVB.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_size = 0x400; +__num_isrs = 29; diff --git a/src/device/avr/atmega16hvbrevb.go b/src/device/avr/atmega16hvbrevb.go new file mode 100644 index 00000000..37371486 --- /dev/null +++ b/src/device/avr/atmega16hvbrevb.go @@ -0,0 +1,796 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega16HVBrevB.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega16hvbrevb + +// Device information for the ATmega16HVBrevB. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega16HVBrevB" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset + IRQ_BPINT = 1 // Battery Protection Interrupt + IRQ_VREGMON = 2 // Voltage regulator monitor interrupt + IRQ_INT0 = 3 // External Interrupt Request 0 + IRQ_INT1 = 4 // External Interrupt Request 1 + IRQ_INT2 = 5 // External Interrupt Request 2 + IRQ_INT3 = 6 // External Interrupt Request 3 + IRQ_PCINT0 = 7 // Pin Change Interrupt 0 + IRQ_PCINT1 = 8 // Pin Change Interrupt 1 + IRQ_WDT = 9 // Watchdog Timeout Interrupt + IRQ_BGSCD = 10 // Bandgap Buffer Short Circuit Detected + IRQ_CHDET = 11 // Charger Detect + IRQ_TIMER1_IC = 12 // Timer 1 Input capture + IRQ_TIMER1_COMPA = 13 // Timer 1 Compare Match A + IRQ_TIMER1_COMPB = 14 // Timer 1 Compare Match B + IRQ_TIMER1_OVF = 15 // Timer 1 overflow + IRQ_TIMER0_IC = 16 // Timer 0 Input Capture + IRQ_TIMER0_COMPA = 17 // Timer 0 Comapre Match A + IRQ_TIMER0_COMPB = 18 // Timer 0 Compare Match B + IRQ_TIMER0_OVF = 19 // Timer 0 Overflow + IRQ_TWIBUSCD = 20 // Two-Wire Bus Connect/Disconnect + IRQ_TWI = 21 // Two-Wire Serial Interface + IRQ_SPI_STC = 22 // SPI Serial transfer complete + IRQ_VADC = 23 // Voltage ADC Conversion Complete + IRQ_CCADC_CONV = 24 // Coulomb Counter ADC Conversion Complete + IRQ_CCADC_REG_CUR = 25 // Coloumb Counter ADC Regular Current + IRQ_CCADC_ACC = 26 // Coloumb Counter ADC Accumulator + IRQ_EE_READY = 27 // EEPROM Ready + IRQ_SPM = 28 // SPM Ready + IRQ_max = 28 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + LOW __reg + HIGH __reg + }{ + LOW: 0x0, + HIGH: 0x1, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog-to-Digital Converter + ADC = struct { + VADMUX __reg + VADCL __reg + VADCH __reg + VADCSR __reg + }{ + VADMUX: 0x7c, // The VADC multiplexer Selection Register + VADCL: 0x78, // VADC Data Register Bytes + VADCH: 0x78, // VADC Data Register Bytes + VADCSR: 0x7a, // The VADC Control and Status register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // FET Control + FET = struct { + FCSR __reg + }{ + FCSR: 0xf0, // FET Control and Status Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access + EEARH: 0x41, // EEPROM Read/Write Access + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Coulomb Counter + COULOMB_COUNTER = struct { + CADCSRA __reg + CADCSRB __reg + CADCSRC __reg + CADICL __reg + CADICH __reg + CADAC3 __reg + CADAC2 __reg + CADAC1 __reg + CADAC0 __reg + CADRCC __reg + CADRDC __reg + }{ + CADCSRA: 0xe6, // CC-ADC Control and Status Register A + CADCSRB: 0xe7, // CC-ADC Control and Status Register B + CADCSRC: 0xe8, // CC-ADC Control and Status Register C + CADICL: 0xe4, // CC-ADC Instantaneous Current + CADICH: 0xe4, // CC-ADC Instantaneous Current + CADAC3: 0xe3, // ADC Accumulate Current + CADAC2: 0xe2, // ADC Accumulate Current + CADAC1: 0xe1, // ADC Accumulate Current + CADAC0: 0xe0, // ADC Accumulate Current + CADRCC: 0xe9, // CC-ADC Regular Charge Current + CADRDC: 0xea, // CC-ADC Regular Discharge Current + } + + // Two Wire Serial Interface + TWI = struct { + TWBCSR __reg + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWBCSR: 0xbe, // TWI Bus Control and Status Register + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCICR __reg + PCIFR __reg + PCMSK1 __reg + PCMSK0 __reg + }{ + EICRA: 0x69, // External Interrupt Control Register + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + PCMSK1: 0x6c, // Pin Change Enable Mask Register 1 + PCMSK0: 0x6b, // Pin Change Enable Mask Register 0 + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1B __reg + TCCR1A __reg + TCNT1L __reg + TCNT1H __reg + OCR1A __reg + OCR1B __reg + TIMSK1 __reg + TIFR1 __reg + TCCR0B __reg + TCCR0A __reg + TCNT0L __reg + TCNT0H __reg + OCR0A __reg + OCR0B __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1A: 0x80, // Timer/Counter 1 Control Register A + TCNT1L: 0x84, // Timer Counter 1 Bytes + TCNT1H: 0x84, // Timer Counter 1 Bytes + OCR1A: 0x88, // Output Compare Register 1A + OCR1B: 0x89, // Output Compare Register B + TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR0B: 0x45, // Timer/Counter0 Control Register B + TCCR0A: 0x44, // Timer/Counter 0 Control Register A + TCNT0L: 0x46, // Timer Counter 0 Bytes + TCNT0H: 0x46, // Timer Counter 0 Bytes + OCR0A: 0x48, // Output Compare Register 0A + OCR0B: 0x49, // Output Compare Register B + TIMSK0: 0x6e, // Timer/Counter Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter Interrupt Flag register + } + + // Cell Balancing + CELL_BALANCING = struct { + CBCR __reg + }{ + CBCR: 0xf1, // Cell Balancing Control Register + } + + // Battery Protection + BATTERY_PROTECTION = struct { + BPPLR __reg + BPCR __reg + BPHCTR __reg + BPOCTR __reg + BPSCTR __reg + BPCHCD __reg + BPDHCD __reg + BPCOCD __reg + BPDOCD __reg + BPSCD __reg + BPIFR __reg + BPIMSK __reg + }{ + BPPLR: 0xfe, // Battery Protection Parameter Lock Register + BPCR: 0xfd, // Battery Protection Control Register + BPHCTR: 0xfc, // Battery Protection Short-current Timing Register + BPOCTR: 0xfb, // Battery Protection Over-current Timing Register + BPSCTR: 0xfa, // Battery Protection Short-current Timing Register + BPCHCD: 0xf9, // Battery Protection Charge-High-current Detection Level Register + BPDHCD: 0xf8, // Battery Protection Discharge-High-current Detection Level Register + BPCOCD: 0xf7, // Battery Protection Charge-Over-current Detection Level Register + BPDOCD: 0xf6, // Battery Protection Discharge-Over-current Detection Level Register + BPSCD: 0xf5, // Battery Protection Short-Circuit Detection Level Register + BPIFR: 0xf3, // Battery Protection Interrupt Flag Register + BPIMSK: 0xf2, // Battery Protection Interrupt Mask Register + } + + // Charger Detect + CHARGER_DETECT = struct { + CHGDCSR __reg + }{ + CHGDCSR: 0xd4, // Charger Detect Control and Status Register + } + + // Voltage Regulator + VOLTAGE_REGULATOR = struct { + ROCR __reg + }{ + ROCR: 0xc8, // Regulator Operating Condition Register + } + + // Bandgap + BANDGAP = struct { + BGCSR __reg + BGCRR __reg + BGCCR __reg + }{ + BGCSR: 0xd2, // Bandgap Control and Status Register + BGCRR: 0xd1, // Bandgap Calibration of Resistor Ladder + BGCCR: 0xd0, // Bandgap Calibration Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + MCUCR __reg + MCUSR __reg + FOSCCAL __reg + OSICSR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + DIDR0 __reg + PRR0 __reg + CLKPR __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + FOSCCAL: 0x66, // Fast Oscillator Calibration Value + OSICSR: 0x37, // Oscillator Sampling Interface Control and Status Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + DIDR0: 0x7e, // Digital Input Disable Register + PRR0: 0x64, // Power Reduction Register 0 + CLKPR: 0x61, // Clock Prescale Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + PINC __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + PINC: 0x26, // Port C Input Pins + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control and Status Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // LOW + LOW_WDTON = 0x80 // Watch-dog Timer always on + LOW_EESAVE = 0x40 // Preserve EEPROM through the Chip Erase cycle + LOW_SPIEN = 0x20 // Serial program downloading (SPI) enabled + LOW_SUT = 0x1c // Select start-up time + LOW_OSCSEL = 0x3 // Oscillator select + + // HIGH + HIGH_DUVRDINIT = 0x10 // DUVR mode on + HIGH_DWEN = 0x8 // Debug Wire enable + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // VADMUX: The VADC multiplexer Selection Register + VADMUX_VADMUX = 0xf // Analog Channel and Gain Selection Bits + + // VADCL: VADC Data Register Bytes + + // VADCH: VADC Data Register Bytes + VADC_VADC = 0xfff // VADC Data bits + + // VADCSR: The VADC Control and Status register + VADCSR_VADEN = 0x8 // VADC Enable + VADCSR_VADSC = 0x4 // VADC Satrt Conversion + VADCSR_VADCCIF = 0x2 // VADC Conversion Complete Interrupt Flag + VADCSR_VADCCIE = 0x1 // VADC Conversion Complete Interrupt Enable +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for FET: FET Control +const ( + // FCSR: FET Control and Status Register + FCSR_DUVRD = 0x8 // Deep Under-Voltage Recovery Disable + FCSR_CPS = 0x4 // Current Protection Status + FCSR_DFE = 0x2 // Discharge FET Enable + FCSR_CFE = 0x1 // Charge FET Enable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPDR: SPI Data Register + SPDR_SPDR = 0xff // SPI Data bits +) + +// Bitfields for EEPROM: EEPROM +const ( + // EEARL: EEPROM Read/Write Access + + // EEARH: EEPROM Read/Write Access + EEAR_EEAR = 0x3ff // EEPROM Address bits + + // EEDR: EEPROM Data Register + EEDR_EEDR = 0xff // EEPROM Data bits + + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 + EECR_EERIE = 0x8 // EEProm Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for COULOMB_COUNTER: Coulomb Counter +const ( + // CADCSRA: CC-ADC Control and Status Register A + CADCSRA_CADEN = 0x80 // When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled. + CADCSRA_CADPOL = 0x40 + CADCSRA_CADUB = 0x20 // CC_ADC Update Busy + CADCSRA_CADAS = 0x18 // CC_ADC Accumulate Current Select Bits + CADCSRA_CADSI = 0x6 // The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. + CADCSRA_CADSE = 0x1 // When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode. + + // CADCSRB: CC-ADC Control and Status Register B + CADCSRB_CADACIE = 0x40 + CADCSRB_CADRCIE = 0x20 // Regular Current Interrupt Enable + CADCSRB_CADICIE = 0x10 // CAD Instantenous Current Interrupt Enable + CADCSRB_CADACIF = 0x4 // CC-ADC Accumulate Current Interrupt Flag + CADCSRB_CADRCIF = 0x2 // CC-ADC Accumulate Current Interrupt Flag + CADCSRB_CADICIF = 0x1 // CC-ADC Instantaneous Current Interrupt Flag + + // CADCSRC: CC-ADC Control and Status Register C + CADCSRC_CADVSE = 0x1 // CC-ADC Voltage Scaling Enable + + // CADICL: CC-ADC Instantaneous Current + + // CADICH: CC-ADC Instantaneous Current + CADIC_CADIC = 0xffff // CC-ADC Instantaneous Current + + // CADAC3: ADC Accumulate Current + CADAC3_CADAC = 0xff // ADC accumulate current bits + + // CADAC2: ADC Accumulate Current + CADAC2_CADAC = 0xff // ADC accumulate current bits + + // CADAC1: ADC Accumulate Current + CADAC1_CADAC = 0xfc // ADC accumulate current bits + CADAC1_CADAC0 = 0x3 // ADC accumulate current bits + + // CADAC0: ADC Accumulate Current + CADAC0_CADAC0 = 0xff // ADC accumulate current bits + + // CADRCC: CC-ADC Regular Charge Current + CADRCC_CADRCC = 0xff // CC-ADC Regular Charge Current + + // CADRDC: CC-ADC Regular Discharge Current + CADRDC_CADRDC = 0xff // CC-ADC Regular Discharge Current +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWBCSR: TWI Bus Control and Status Register + TWBCSR_TWBCIF = 0x80 // TWI Bus Connect/Disconnect Interrupt Flag + TWBCSR_TWBCIE = 0x40 // TWI Bus Connect/Disconnect Interrupt Enable + TWBCSR_TWBDT = 0x6 // TWI Bus Disconnect Time-out Period + TWBCSR_TWBCIP = 0x1 // TWI Bus Connect/Disconnect Interrupt Polarity + + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWBR: TWI Bit Rate register + TWBR_TWBR = 0xff // TWI Bit Rate bits + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWDR: TWI Data register + TWDR_TWD = 0xff // TWI Data Bits + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register + EICRA_ISC3 = 0xc0 // External Interrupt Sense Control 3 Bits + EICRA_ISC2 = 0x30 // External Interrupt Sense Control 2 Bits + EICRA_ISC1 = 0xc // External Interrupt Sense Control 1 Bits + EICRA_ISC0 = 0x3 // External Interrupt Sense Control 0 Bits + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xf // External Interrupt Request 3 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xf // External Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0x3 // Pin Change Interrupt Enables + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0x3 // Pin Change Interrupt Flags + + // PCMSK1: Pin Change Enable Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Enable Mask + + // PCMSK0: Pin Change Enable Mask Register 0 + PCMSK0_PCINT = 0xf // Pin Change Enable Mask +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_CS = 0x7 // Clock Select1 bis + + // TCCR1A: Timer/Counter 1 Control Register A + TCCR1A_TCW1 = 0x80 // Timer/Counter Width + TCCR1A_ICEN1 = 0x40 // Input Capture Mode Enable + TCCR1A_ICNC1 = 0x20 // Input Capture Noise Canceler + TCCR1A_ICES1 = 0x10 // Input Capture Edge Select + TCCR1A_ICS1 = 0x8 // Input Capture Select + TCCR1A_WGM10 = 0x1 // Waveform Generation Mode + + // TCNT1L: Timer Counter 1 Bytes + + // TCNT1H: Timer Counter 1 Bytes + TCNT1_TCNT1 = 0xffff // Timer Counter 1 bits + + // OCR1A: Output Compare Register 1A + OCR1A_OCR1A = 0xff // Output Compare 1 A bits + + // OCR1B: Output Compare Register B + OCR1B_OCR1B = 0xff // Output Compare 1 B bits + + // TIMSK1: Timer/Counter Interrupt Mask Register + TIMSK1_ICIE1 = 0x8 // Timer/Counter n Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x8 // Timer/Counter 1 Input Capture Flag + TIFR1_OCF1B = 0x4 // Timer/Counter1 Output Compare Flag B + TIFR1_OCF1A = 0x2 // Timer/Counter1 Output Compare Flag A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR0B: Timer/Counter0 Control Register B + TCCR0B_CS02 = 0x4 // Clock Select0 bit 2 + TCCR0B_CS01 = 0x2 // Clock Select0 bit 1 + TCCR0B_CS00 = 0x1 // Clock Select0 bit 0 + + // TCCR0A: Timer/Counter 0 Control Register A + TCCR0A_TCW0 = 0x80 // Timer/Counter Width + TCCR0A_ICEN0 = 0x40 // Input Capture Mode Enable + TCCR0A_ICNC0 = 0x20 // Input Capture Noise Canceler + TCCR0A_ICES0 = 0x10 // Input Capture Edge Select + TCCR0A_ICS0 = 0x8 // Input Capture Select + TCCR0A_WGM00 = 0x1 // Waveform Generation Mode + + // TCNT0L: Timer Counter 0 Bytes + + // TCNT0H: Timer Counter 0 Bytes + TCNT0_TCNT0 = 0xffff // Timer Counter 0 bits + + // OCR0A: Output Compare Register 0A + OCR0A_OCR0A = 0xff // Output Compare 0 A bits + + // OCR0B: Output Compare Register B + OCR0B_OCR0B = 0xff // Output Compare 0 B bits + + // TIMSK0: Timer/Counter Interrupt Mask Register + TIMSK0_ICIE0 = 0x8 // Timer/Counter n Input Capture Interrupt Enable + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter Interrupt Flag register + TIFR0_ICF0 = 0x8 // Timer/Counter 0 Input Capture Flag + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for CELL_BALANCING: Cell Balancing +const ( + // CBCR: Cell Balancing Control Register + CBCR_CBE = 0xf // Cell Balancing Enables +) + +// Bitfields for BATTERY_PROTECTION: Battery Protection +const ( + // BPPLR: Battery Protection Parameter Lock Register + BPPLR_BPPLE = 0x2 // Battery Protection Parameter Lock Enable + BPPLR_BPPL = 0x1 // Battery Protection Parameter Lock + + // BPCR: Battery Protection Control Register + BPCR_EPID = 0x20 // External Protection Input Disable + BPCR_SCD = 0x10 // Short Circuit Protection Disabled + BPCR_DOCD = 0x8 // Discharge Over-current Protection Disabled + BPCR_COCD = 0x4 // Charge Over-current Protection Disabled + BPCR_DHCD = 0x2 // Discharge High-current Protection Disable + BPCR_CHCD = 0x1 // Charge High-current Protection Disable + + // BPHCTR: Battery Protection Short-current Timing Register + BPHCTR_HCPT = 0x3f // Battery Protection Short-current Timing bits + + // BPOCTR: Battery Protection Over-current Timing Register + BPOCTR_OCPT = 0x3f // Battery Protection Over-current Timing bits + + // BPSCTR: Battery Protection Short-current Timing Register + BPSCTR_SCPT = 0x7f // Battery Protection Short-current Timing bits + + // BPCHCD: Battery Protection Charge-High-current Detection Level Register + BPCHCD_CHCDL = 0xff // Battery Protection Charge-High-current Detection Level bits + + // BPDHCD: Battery Protection Discharge-High-current Detection Level Register + BPDHCD_DHCDL = 0xff // Battery Protection Discharge-High-current Detection Level bits + + // BPCOCD: Battery Protection Charge-Over-current Detection Level Register + BPCOCD_COCDL = 0xff // Battery Protection Charge-Over-current Detection Level bits + + // BPDOCD: Battery Protection Discharge-Over-current Detection Level Register + BPDOCD_DOCDL = 0xff // Battery Protection Discharge-Over-current Detection Level bits + + // BPSCD: Battery Protection Short-Circuit Detection Level Register + BPSCD_SCDL = 0xff // Battery Protection Short-Circuit Detection Level Register bits + + // BPIFR: Battery Protection Interrupt Flag Register + BPIFR_SCIF = 0x10 // Short-circuit Protection Activated Interrupt Flag + BPIFR_DOCIF = 0x8 // Discharge Over-current Protection Activated Interrupt Flag + BPIFR_COCIF = 0x4 // Charge Over-current Protection Activated Interrupt Flag + BPIFR_DHCIF = 0x2 // Disharge High-current Protection Activated Interrupt + BPIFR_CHCIF = 0x1 // Charge High-current Protection Activated Interrupt + + // BPIMSK: Battery Protection Interrupt Mask Register + BPIMSK_SCIE = 0x10 // Short-circuit Protection Activated Interrupt Enable + BPIMSK_DOCIE = 0x8 // Discharge Over-current Protection Activated Interrupt Enable + BPIMSK_COCIE = 0x4 // Charge Over-current Protection Activated Interrupt Enable + BPIMSK_DHCIE = 0x2 // Discharger High-current Protection Activated Interrupt + BPIMSK_CHCIE = 0x1 // Charger High-current Protection Activated Interrupt +) + +// Bitfields for CHARGER_DETECT: Charger Detect +const ( + // CHGDCSR: Charger Detect Control and Status Register + CHGDCSR_BATTPVL = 0x10 // BATT Pin Voltage Level + CHGDCSR_CHGDISC = 0xc // Charger Detect Interrupt Sense Control + CHGDCSR_CHGDIF = 0x2 // Charger Detect Interrupt Flag + CHGDCSR_CHGDIE = 0x1 // Charger Detect Interrupt Enable +) + +// Bitfields for VOLTAGE_REGULATOR: Voltage Regulator +const ( + // ROCR: Regulator Operating Condition Register + ROCR_ROCS = 0x80 // ROC Status + ROCR_ROCD = 0x10 // ROC Disable + ROCR_ROCWIF = 0x2 // ROC Warning Interrupt Flag + ROCR_ROCWIE = 0x1 // ROC Warning Interrupt Enable +) + +// Bitfields for BANDGAP: Bandgap +const ( + // BGCSR: Bandgap Control and Status Register + BGCSR_BGD = 0x20 // Bandgap Disable + BGCSR_BGSCDE = 0x10 // Bandgap Short Circuit Detection Enabled + BGCSR_BGSCDIF = 0x2 // Bandgap Short Circuit Detection Interrupt Flag + BGCSR_BGSCDIE = 0x1 // Bandgap Short Circuit Detection Interrupt Enable + + // BGCRR: Bandgap Calibration of Resistor Ladder + BGCRR_BGCR = 0xff // Bandgap Calibration of Resistor Ladder Bits + + // BGCCR: Bandgap Calibration Register + BGCCR_BGCC = 0x3f // BG Calibration of PTAT Current Bits +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // MCUCR: MCU Control Register + MCUCR_CKOE = 0x20 // Clock Output Enable + MCUCR_PUD = 0x10 // Pull-up disable + MCUCR_IVSEL = 0x2 // Interrupt Vector Select + MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable + + // MCUSR: MCU Status Register + MCUSR_OCDRF = 0x10 // OCD Reset Flag + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BODRF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // FOSCCAL: Fast Oscillator Calibration Value + FOSCCAL_FCAL = 0xff // Fast Oscillator Calibration Value + + // OSICSR: Oscillator Sampling Interface Control and Status Register + OSICSR_OSISEL0 = 0x10 // Oscillator Sampling Interface Select 0 + OSICSR_OSIST = 0x2 // Oscillator Sampling Interface Status + OSICSR_OSIEN = 0x1 // Oscillator Sampling Interface Enable + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR2 = 0xff // General Purpose IO bits + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR1 = 0xff // General Purpose IO bits + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR0 = 0xff // General Purpose IO bits + + // DIDR0: Digital Input Disable Register + DIDR0_PA1DID = 0x2 // When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled. + DIDR0_PA0DID = 0x1 // When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled. + + // PRR0: Power Reduction Register 0 + PRR0_PRTWI = 0x40 // Power Reduction TWI + PRR0_PRVRM = 0x20 // Power Reduction Voltage Regulator Monitor + PRR0_PRSPI = 0x8 // Power reduction SPI + PRR0_PRTIM1 = 0x4 // Power Reduction Timer/Counter1 + PRR0_PRTIM0 = 0x2 // Power Reduction Timer/Counter0 + PRR0_PRVADC = 0x1 // Power Reduction V-ADC + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0x3 // Clock Prescaler Select Bits +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control and Status Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read-While-Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read-While-Write Section Read Enable + SPMCSR_LBSET = 0x8 // Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) diff --git a/src/device/avr/atmega16hvbrevb.ld b/src/device/avr/atmega16hvbrevb.ld new file mode 100644 index 00000000..7a40ac28 --- /dev/null +++ b/src/device/avr/atmega16hvbrevb.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega16HVBrevB.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_size = 0x400; +__num_isrs = 29; diff --git a/src/device/avr/atmega16m1.go b/src/device/avr/atmega16m1.go new file mode 100644 index 00000000..13db09bd --- /dev/null +++ b/src/device/avr/atmega16m1.go @@ -0,0 +1,1163 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega16M1.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega16m1 + +// Device information for the ATmega16M1. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega16M1" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset + IRQ_ANACOMP0 = 1 // Analog Comparator 0 + IRQ_ANACOMP1 = 2 // Analog Comparator 1 + IRQ_ANACOMP2 = 3 // Analog Comparator 2 + IRQ_ANACOMP3 = 4 // Analog Comparator 3 + IRQ_PSC_FAULT = 5 // PSC Fault + IRQ_PSC_EC = 6 // PSC End of Cycle + IRQ_INT0 = 7 // External Interrupt Request 0 + IRQ_INT1 = 8 // External Interrupt Request 1 + IRQ_INT2 = 9 // External Interrupt Request 2 + IRQ_INT3 = 10 // External Interrupt Request 3 + IRQ_TIMER1_CAPT = 11 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 12 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 13 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 14 // Timer1/Counter1 Overflow + IRQ_TIMER0_COMPA = 15 // Timer/Counter0 Compare Match A + IRQ_TIMER0_COMPB = 16 // Timer/Counter0 Compare Match B + IRQ_TIMER0_OVF = 17 // Timer/Counter0 Overflow + IRQ_CAN_INT = 18 // CAN MOB, Burst, General Errors + IRQ_CAN_TOVF = 19 // CAN Timer Overflow + IRQ_LIN_TC = 20 // LIN Transfer Complete + IRQ_LIN_ERR = 21 // LIN Error + IRQ_PCINT0 = 22 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 23 // Pin Change Interrupt Request 1 + IRQ_PCINT2 = 24 // Pin Change Interrupt Request 2 + IRQ_PCINT3 = 25 // Pin Change Interrupt Request 3 + IRQ_SPI_STC = 26 // SPI Serial Transfer Complete + IRQ_ADC = 27 // ADC Conversion Complete + IRQ_WDT = 28 // Watchdog Time-Out Interrupt + IRQ_EE_READY = 29 // EEPROM Ready + IRQ_SPM_READY = 30 // Store Program Memory Read + IRQ_max = 30 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // I/O Port + PORT = struct { + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + }{ + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Port E Data Register + DDRE: 0x2d, // Port E Data Direction Register + PINE: 0x2c, // Port E Input Pins + } + + // Controller Area Network + CAN = struct { + CANGCON __reg + CANGSTA __reg + CANGIT __reg + CANGIE __reg + CANEN2 __reg + CANEN1 __reg + CANIE2 __reg + CANIE1 __reg + CANSIT2 __reg + CANSIT1 __reg + CANBT1 __reg + CANBT2 __reg + CANBT3 __reg + CANTCON __reg + CANTIML __reg + CANTIMH __reg + CANTTCL __reg + CANTTCH __reg + CANTEC __reg + CANREC __reg + CANHPMOB __reg + CANPAGE __reg + CANSTMOB __reg + CANCDMOB __reg + CANIDT4 __reg + CANIDT3 __reg + CANIDT2 __reg + CANIDT1 __reg + CANIDM4 __reg + CANIDM3 __reg + CANIDM2 __reg + CANIDM1 __reg + CANSTML __reg + CANSTMH __reg + CANMSG __reg + }{ + CANGCON: 0xd8, // CAN General Control Register + CANGSTA: 0xd9, // CAN General Status Register + CANGIT: 0xda, // CAN General Interrupt Register Flags + CANGIE: 0xdb, // CAN General Interrupt Enable Register + CANEN2: 0xdc, // Enable MOb Register 2 + CANEN1: 0xdd, // Enable MOb Register 1(empty) + CANIE2: 0xde, // Enable Interrupt MOb Register 2 + CANIE1: 0xdf, // Enable Interrupt MOb Register 1 (empty) + CANSIT2: 0xe0, // CAN Status Interrupt MOb Register 2 + CANSIT1: 0xe1, // CAN Status Interrupt MOb Register 1 (empty) + CANBT1: 0xe2, // CAN Bit Timing Register 1 + CANBT2: 0xe3, // CAN Bit Timing Register 2 + CANBT3: 0xe4, // CAN Bit Timing Register 3 + CANTCON: 0xe5, // Timer Control Register + CANTIML: 0xe6, // Timer Register + CANTIMH: 0xe6, // Timer Register + CANTTCL: 0xe8, // TTC Timer Register + CANTTCH: 0xe8, // TTC Timer Register + CANTEC: 0xea, // Transmit Error Counter Register + CANREC: 0xeb, // Receive Error Counter Register + CANHPMOB: 0xec, // Highest Priority MOb Register + CANPAGE: 0xed, // Page MOb Register + CANSTMOB: 0xee, // MOb Status Register + CANCDMOB: 0xef, // MOb Control and DLC Register + CANIDT4: 0xf0, // Identifier Tag Register 4 + CANIDT3: 0xf1, // Identifier Tag Register 3 + CANIDT2: 0xf2, // Identifier Tag Register 2 + CANIDT1: 0xf3, // Identifier Tag Register 1 + CANIDM4: 0xf4, // Identifier Mask Register 4 + CANIDM3: 0xf5, // Identifier Mask Register 3 + CANIDM2: 0xf6, // Identifier Mask Register 2 + CANIDM1: 0xf7, // Identifier Mask Register 1 + CANSTML: 0xf8, // Time Stamp Register + CANSTMH: 0xf8, // Time Stamp Register + CANMSG: 0xfa, // Message Data Register + } + + // Analog Comparator + AC = struct { + AC0CON __reg + AC1CON __reg + AC2CON __reg + AC3CON __reg + ACSR __reg + }{ + AC0CON: 0x94, // Analog Comparator 0 Control Register + AC1CON: 0x95, // Analog Comparator 1 Control Register + AC2CON: 0x96, // Analog Comparator 2 Control Register + AC3CON: 0x97, // Analog Comparator 3 Control Register + ACSR: 0x50, // Analog Comparator Status Register + } + + // Digital-to-Analog Converter + DAC = struct { + DACL __reg + DACH __reg + DACON __reg + }{ + DACL: 0x91, // DAC Data Register + DACH: 0x91, // DAC Data Register + DACON: 0x90, // DAC Control Register + } + + // CPU Registers + CPU = struct { + SPMCSR __reg + SREG __reg + SPL __reg + SPH __reg + MCUCR __reg + MCUSR __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PLLCSR __reg + PRR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x3a, // General Purpose IO Register 2 + GPIOR1: 0x39, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PLLCSR: 0x49, // PLL Control And Status Register + PRR: 0x64, // Power Reduction Register + } + + // Timer/Counter, 8-bit + TC8 = struct { + TIMSK0 __reg + TIFR0 __reg + TCCR0A __reg + TCCR0B __reg + TCNT0 __reg + OCR0A __reg + OCR0B __reg + }{ + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + TCCR0A: 0x44, // Timer/Counter Control Register A + TCCR0B: 0x45, // Timer/Counter Control Register B + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + ADCSRB __reg + DIDR0 __reg + DIDR1 __reg + AMP0CSR __reg + AMP1CSR __reg + AMP2CSR __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRB: 0x7b, // ADC Control and Status Register B + DIDR0: 0x7e, // Digital Input Disable Register 0 + DIDR1: 0x7f, // Digital Input Disable Register 0 + AMP0CSR: 0x75, + AMP1CSR: 0x76, + AMP2CSR: 0x77, + } + + // Local Interconnect Network + LINUART = struct { + LINCR __reg + LINSIR __reg + LINENIR __reg + LINERR __reg + LINBTR __reg + LINBRRL __reg + LINBRRH __reg + LINDLR __reg + LINIDR __reg + LINSEL __reg + LINDAT __reg + }{ + LINCR: 0xc8, // LIN Control Register + LINSIR: 0xc9, // LIN Status and Interrupt Register + LINENIR: 0xca, // LIN Enable Interrupt Register + LINERR: 0xcb, // LIN Error Register + LINBTR: 0xcc, // LIN Bit Timing Register + LINBRRL: 0xcd, // LIN Baud Rate Register + LINBRRH: 0xcd, // LIN Baud Rate Register + LINDLR: 0xcf, // LIN Data Length Register + LINIDR: 0xd0, // LIN Identifier Register + LINSEL: 0xd1, // LIN Data Buffer Selection Register + LINDAT: 0xd2, // LIN Data Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCICR __reg + PCMSK3 __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + PCMSK3: 0x6d, // Pin Change Mask Register 3 + PCMSK2: 0x6c, // Pin Change Mask Register 2 + PCMSK1: 0x6b, // Pin Change Mask Register 1 + PCMSK0: 0x6a, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access + EEARH: 0x41, // EEPROM Read/Write Access + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Power Stage Controller + PSC = struct { + PIFR __reg + PIM __reg + PMIC2 __reg + PMIC1 __reg + PMIC0 __reg + PCTL __reg + POC __reg + PCNF __reg + PSYNC __reg + POCR_RBL __reg + POCR_RBH __reg + POCR2SBL __reg + POCR2SBH __reg + POCR2RAL __reg + POCR2RAH __reg + POCR2SAL __reg + POCR2SAH __reg + POCR1SBL __reg + POCR1SBH __reg + POCR1RAL __reg + POCR1RAH __reg + POCR1SAL __reg + POCR1SAH __reg + POCR0SBL __reg + POCR0SBH __reg + POCR0RAL __reg + POCR0RAH __reg + POCR0SAL __reg + POCR0SAH __reg + }{ + PIFR: 0xbc, // PSC Interrupt Flag Register + PIM: 0xbb, // PSC Interrupt Mask Register + PMIC2: 0xba, // PSC Module 2 Input Control Register + PMIC1: 0xb9, // PSC Module 1 Input Control Register + PMIC0: 0xb8, // PSC Module 0 Input Control Register + PCTL: 0xb7, // PSC Control Register + POC: 0xb6, // PSC Output Configuration + PCNF: 0xb5, // PSC Configuration Register + PSYNC: 0xb4, // PSC Synchro Configuration + POCR_RBL: 0xb2, // PSC Output Compare RB Register + POCR_RBH: 0xb2, // PSC Output Compare RB Register + POCR2SBL: 0xb0, // PSC Module 2 Output Compare SB Register + POCR2SBH: 0xb0, // PSC Module 2 Output Compare SB Register + POCR2RAL: 0xae, // PSC Module 2 Output Compare RA Register + POCR2RAH: 0xae, // PSC Module 2 Output Compare RA Register + POCR2SAL: 0xac, // PSC Module 2 Output Compare SA Register + POCR2SAH: 0xac, // PSC Module 2 Output Compare SA Register + POCR1SBL: 0xaa, // PSC Module 1 Output Compare SB Register + POCR1SBH: 0xaa, // PSC Module 1 Output Compare SB Register + POCR1RAL: 0xa8, // PSC Module 1 Output Compare RA Register + POCR1RAH: 0xa8, // PSC Module 1 Output Compare RA Register + POCR1SAL: 0xa6, // PSC Module 1 Output Compare SA Register + POCR1SAH: 0xa6, // PSC Module 1 Output Compare SA Register + POCR0SBL: 0xa4, // PSC Module 0 Output Compare SB Register + POCR0SBH: 0xa4, // PSC Module 0 Output Compare SB Register + POCR0RAL: 0xa2, // PSC Module 0 Output Compare RA Register + POCR0RAH: 0xa2, // PSC Module 0 Output Compare RA Register + POCR0SAL: 0xa0, // PSC Module 0 Output Compare SA Register + POCR0SAH: 0xa0, // PSC Module 0 Output Compare SA Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_PSCRB = 0x20 // PSC Reset Behavior + EXTENDED_PSCRVA = 0x10 // PSCOUTnA Reset Value + EXTENDED_PSCRVB = 0x8 // PSC0UTnB Reset Value + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector Trigger Level + + // HIGH + HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PC6 as i/o pin) + HIGH_DWEN = 0x40 // Debug Wire enable + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watch-dog Timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Select Reset Vector + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTD1 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for CAN: Controller Area Network +const ( + // CANGCON: CAN General Control Register + CANGCON_ABRQ = 0x80 // Abort Request + CANGCON_OVRQ = 0x40 // Overload Frame Request + CANGCON_TTC = 0x20 // Time Trigger Communication + CANGCON_SYNTTC = 0x10 // Synchronization of TTC + CANGCON_LISTEN = 0x8 // Listening Mode + CANGCON_TEST = 0x4 // Test Mode + CANGCON_ENASTB = 0x2 // Enable / Standby + CANGCON_SWRES = 0x1 // Software Reset Request + + // CANGSTA: CAN General Status Register + CANGSTA_OVFG = 0x40 // Overload Frame Flag + CANGSTA_TXBSY = 0x10 // Transmitter Busy + CANGSTA_RXBSY = 0x8 // Receiver Busy + CANGSTA_ENFG = 0x4 // Enable Flag + CANGSTA_BOFF = 0x2 // Bus Off Mode + CANGSTA_ERRP = 0x1 // Error Passive Mode + + // CANGIT: CAN General Interrupt Register Flags + CANGIT_CANIT = 0x80 // General Interrupt Flag + CANGIT_BOFFIT = 0x40 // Bus Off Interrupt Flag + CANGIT_OVRTIM = 0x20 // Overrun CAN Timer Flag + CANGIT_BXOK = 0x10 // Burst Receive Interrupt Flag + CANGIT_SERG = 0x8 // Stuff Error General Flag + CANGIT_CERG = 0x4 // CRC Error General Flag + CANGIT_FERG = 0x2 // Form Error General Flag + CANGIT_AERG = 0x1 // Ackknowledgement Error General Flag + + // CANGIE: CAN General Interrupt Enable Register + CANGIE_ENIT = 0x80 // Enable all Interrupts + CANGIE_ENBOFF = 0x40 // Enable Bus Off Interrupt + CANGIE_ENRX = 0x20 // Enable Receive Interrupt + CANGIE_ENTX = 0x10 // Enable Transmitt Interrupt + CANGIE_ENERR = 0x8 // Enable MOb Error Interrupt + CANGIE_ENBX = 0x4 // Enable Burst Receive Interrupt + CANGIE_ENERG = 0x2 // Enable General Error Interrupt + CANGIE_ENOVRT = 0x1 // Enable CAN Timer Overrun Interrupt + + // CANEN2: Enable MOb Register 2 + CANEN2_ENMOB = 0x3f // Enable MObs + + // CANIE2: Enable Interrupt MOb Register 2 + CANIE2_IEMOB = 0x3f // Interrupt Enable MObs + + // CANSIT2: CAN Status Interrupt MOb Register 2 + CANSIT2_SIT = 0x3f // Status of Interrupt MObs + + // CANBT1: CAN Bit Timing Register 1 + CANBT1_BRP = 0x7e // Baud Rate Prescaler bits + + // CANBT2: CAN Bit Timing Register 2 + CANBT2_SJW = 0x60 // Re-Sync Jump Width bits + CANBT2_PRS = 0xe // Propagation Time Segment bits + + // CANBT3: CAN Bit Timing Register 3 + CANBT3_PHS2 = 0x70 // Phase Segment 2 bits + CANBT3_PHS1 = 0xe // Phase Segment 1 bits + CANBT3_SMP = 0x1 // Sample Type + + // CANTCON: Timer Control Register + CANTCON_TPRSC = 0xff // Timer Control bits + + // CANTIML: Timer Register + + // CANTIMH: Timer Register + CANTIM_CANTIM = 0xffff // Timer bits + + // CANTTCL: TTC Timer Register + + // CANTTCH: TTC Timer Register + CANTTC_TIMTTC = 0xffff // TTC Timer Count + + // CANTEC: Transmit Error Counter Register + CANTEC_TEC = 0xff // Transmit Error Counter bits + + // CANREC: Receive Error Counter Register + CANREC_REC = 0xff // Receive Error Counter bits + + // CANHPMOB: Highest Priority MOb Register + CANHPMOB_HPMOB = 0xf0 // Highest Priority MOb Number bits + CANHPMOB_CGP = 0xf // CAN General Purpose bits + + // CANPAGE: Page MOb Register + CANPAGE_MOBNB = 0xf0 // MOb Number bits + CANPAGE_AINC = 0x8 // MOb Data Buffer Auto Increment (Active Low) + CANPAGE_INDX = 0x7 // Data Buffer Index bits + + // CANSTMOB: MOb Status Register + CANSTMOB_DLCW = 0x80 // Data Length Code Warning on MOb + CANSTMOB_TXOK = 0x40 // Transmit OK on MOb + CANSTMOB_RXOK = 0x20 // Receive OK on MOb + CANSTMOB_BERR = 0x10 // Bit Error on MOb + CANSTMOB_SERR = 0x8 // Stuff Error on MOb + CANSTMOB_CERR = 0x4 // CRC Error on MOb + CANSTMOB_FERR = 0x2 // Form Error on MOb + CANSTMOB_AERR = 0x1 // Ackknowledgement Error on MOb + + // CANCDMOB: MOb Control and DLC Register + CANCDMOB_CONMOB = 0xc0 // MOb Config bits + CANCDMOB_RPLV = 0x20 // Reply Valid + CANCDMOB_IDE = 0x10 // Identifier Extension + CANCDMOB_DLC = 0xf // Data Length Code bits + + // CANIDT4: Identifier Tag Register 4 + CANIDT4_IDT = 0xf8 // Identifier Tag + CANIDT4_RTRTAG = 0x4 // Remote Transmission Request Tag + CANIDT4_RB1TAG = 0x2 // Reserved Bit 1 Tag + CANIDT4_RB0TAG = 0x1 // Reserved Bit 0 Tag + + // CANIDT3: Identifier Tag Register 3 + CANIDT3_IDT = 0xff // Identifier Tag + + // CANIDT2: Identifier Tag Register 2 + CANIDT2_IDT = 0xff // Identifier Tag + + // CANIDT1: Identifier Tag Register 1 + CANIDT1_IDT = 0xff // Identifier Tag + + // CANIDM4: Identifier Mask Register 4 + CANIDM4_IDEMSK = 0x1 // Identifier Extension Mask + CANIDM4_RTRMSK = 0x4 // Remote Transmission Request Mask + CANIDM4_IDMSK = 0xf8 // Identifier Mask + + // CANIDM3: Identifier Mask Register 3 + CANIDM3_IDMSK = 0xff // Identifier Mask + + // CANIDM2: Identifier Mask Register 2 + CANIDM2_IDMSK = 0xff // Identifier Mask + + // CANIDM1: Identifier Mask Register 1 + CANIDM1_IDMSK = 0xff // Identifier Mask + + // CANSTML: Time Stamp Register + + // CANSTMH: Time Stamp Register + CANSTM_TIMSTM = 0xffff // TIMSTM + + // CANMSG: Message Data Register + CANMSG_MSG = 0xff // Message Data bits +) + +// Bitfields for AC: Analog Comparator +const ( + // AC0CON: Analog Comparator 0 Control Register + AC0CON_AC0EN = 0x80 // Analog Comparator 0 Enable Bit + AC0CON_AC0IE = 0x40 // Analog Comparator 0 Interrupt Enable Bit + AC0CON_AC0IS = 0x30 // Analog Comparator 0 Interrupt Select Bits + AC0CON_ACCKSEL = 0x8 // Analog Comparator Clock Select + AC0CON_AC0M = 0x7 // Analog Comparator 0 Multiplexer Register + + // AC1CON: Analog Comparator 1 Control Register + AC1CON_AC1EN = 0x80 // Analog Comparator 1 Enable Bit + AC1CON_AC1IE = 0x40 // Analog Comparator 1 Interrupt Enable Bit + AC1CON_AC1IS = 0x30 // Analog Comparator 1 Interrupt Select Bit + AC1CON_AC1ICE = 0x8 // Analog Comparator 1 Interrupt Capture Enable Bit + AC1CON_AC1M = 0x7 // Analog Comparator 1 Multiplexer Register + + // AC2CON: Analog Comparator 2 Control Register + AC2CON_AC2EN = 0x80 // Analog Comparator 2 Enable Bit + AC2CON_AC2IE = 0x40 // Analog Comparator 2 Interrupt Enable Bit + AC2CON_AC2IS = 0x30 // Analog Comparator 2 Interrupt Select Bit + AC2CON_AC2M = 0x7 // Analog Comparator 2 Multiplexer Register + + // AC3CON: Analog Comparator 3 Control Register + AC3CON_AC3EN = 0x80 // Analog Comparator 3 Enable Bit + AC3CON_AC3IE = 0x40 // Analog Comparator 3 Interrupt Enable Bit + AC3CON_AC3IS = 0x30 // Analog Comparator 3 Interrupt Select Bit + AC3CON_AC3M = 0x7 // Analog Comparator 3 Multiplexer Register + + // ACSR: Analog Comparator Status Register + ACSR_AC3IF = 0x80 // Analog Comparator 3 Interrupt Flag Bit + ACSR_AC2IF = 0x40 // Analog Comparator 2 Interrupt Flag Bit + ACSR_AC1IF = 0x20 // Analog Comparator 1 Interrupt Flag Bit + ACSR_AC0IF = 0x10 // Analog Comparator 0 Interrupt Flag Bit + ACSR_AC3O = 0x8 // Analog Comparator 3 Output Bit + ACSR_AC2O = 0x4 // Analog Comparator 2 Output Bit + ACSR_AC1O = 0x2 // Analog Comparator 1 Output Bit + ACSR_AC0O = 0x1 // Analog Comparator 0 Output Bit +) + +// Bitfields for DAC: Digital-to-Analog Converter +const ( + // DACL: DAC Data Register + + // DACH: DAC Data Register + DAC_DAC = 0xffff // DAC Data Register Bits + + // DACON: DAC Control Register + DACON_DAATE = 0x80 // DAC Auto Trigger Enable Bit + DACON_DATS = 0x70 // DAC Trigger Selection Bits + DACON_DALA = 0x4 // DAC Left Adjust + DACON_DAOE = 0x2 // DAC Output Enable + DACON_DAEN = 0x1 // DAC Enable Bit +) + +// Bitfields for CPU: CPU Registers +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable + + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // MCUCR: MCU Control Register + MCUCR_SPIPS = 0x80 // SPI Pin Select + MCUCR_PUD = 0x10 // Pull-up disable + MCUCR_IVSEL = 0x2 // Interrupt Vector Select + MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable + + // MCUSR: MCU Status Register + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BORF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 + + // PLLCSR: PLL Control And Status Register + PLLCSR_PLLF = 0x4 // PLL Factor + PLLCSR_PLLE = 0x2 // PLL Enable + PLLCSR_PLOCK = 0x1 // PLL Lock Detector + + // PRR: Power Reduction Register + PRR_PRCAN = 0x40 // Power Reduction CAN + PRR_PRPSC = 0x20 // Power Reduction PSC + PRR_PRTIM1 = 0x10 // Power Reduction Timer/Counter1 + PRR_PRTIM0 = 0x8 // Power Reduction Timer/Counter0 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRLIN = 0x2 // Power Reduction LIN UART + PRR_PRADC = 0x1 // Power Reduction ADC +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCNT0: Timer/Counter0 + TCNT0_TCNT0 = 0xff // Timer/Counter0 bits + + // OCR0A: Timer/Counter0 Output Compare Register + OCR0A_OCR0A = 0xff // Timer/Counter0 Output Compare bits + + // OCR0B: Timer/Counter0 Output Compare Register + OCR0B_OCR0B = 0xff // Timer/Counter0 Output Compare bits +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TIMSK1: Timer/Counter Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output CompareB Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output CompareA Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 + TCCR1C_FOC1B = 0x40 + + // TCNT1L: Timer/Counter1 Bytes + + // TCNT1H: Timer/Counter1 Bytes + TCNT1_TCNT1 = 0xffff // Timer/Counter1 bits + + // OCR1AL: Timer/Counter1 Output Compare Register Bytes + + // OCR1AH: Timer/Counter1 Output Compare Register Bytes + OCR1A_OCR1A = 0xffff // Timer/Counter1 Output Compare bits + + // OCR1BL: Timer/Counter1 Output Compare Register Bytes + + // OCR1BH: Timer/Counter1 Output Compare Register Bytes + OCR1B_OCR1B = 0xffff // Timer/Counter1 Output Compare bits + + // ICR1L: Timer/Counter1 Input Capture Register Bytes + + // ICR1H: Timer/Counter1 Input Capture Register Bytes + ICR1_ICR1 = 0xffff // Timer/Counter1 Input Capture bits +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCL: ADC Data Register Bytes + + // ADCH: ADC Data Register Bytes + ADC_ADC = 0xffff // ADC Data bits + + // ADCSRB: ADC Control and Status Register B + ADCSRB_ADHSM = 0x80 // ADC High Speed Mode + ADCSRB_ISRCEN = 0x40 // Current Source Enable + ADCSRB_AREFEN = 0x20 // Analog Reference pin Enable + ADCSRB_ADTS = 0xf // ADC Auto Trigger Sources + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable + + // DIDR1: Digital Input Disable Register 0 + DIDR1_AMP2PD = 0x40 // AMP2P Pin Digital input Disable + DIDR1_ACMP0D = 0x20 // ACMP0 Pin Digital input Disable + DIDR1_AMP0PD = 0x10 // AMP0P Pin Digital input Disable + DIDR1_AMP0ND = 0x8 // AMP0N Pin Digital input Disable + DIDR1_ADC10D = 0x4 // ADC10 Pin Digital input Disable + DIDR1_ADC9D = 0x2 // ADC9 Pin Digital input Disable + DIDR1_ADC8D = 0x1 // ADC8 Pin Digital input Disable + + // AMP0CSR + AMP0CSR_AMP0EN = 0x80 + AMP0CSR_AMP0IS = 0x40 + AMP0CSR_AMP0G = 0x30 + AMP0CSR_AMPCMP0 = 0x8 // Amplifier 0 - Comparator 0 Connection + AMP0CSR_AMP0TS = 0x7 + + // AMP1CSR + AMP1CSR_AMP1EN = 0x80 + AMP1CSR_AMP1IS = 0x40 + AMP1CSR_AMP1G = 0x30 + AMP1CSR_AMPCMP1 = 0x8 // Amplifier 1 - Comparator 1 Connection + AMP1CSR_AMP1TS = 0x7 + + // AMP2CSR + AMP2CSR_AMP2EN = 0x80 + AMP2CSR_AMP2IS = 0x40 + AMP2CSR_AMP2G = 0x30 + AMP2CSR_AMPCMP2 = 0x8 // Amplifier 2 - Comparator 2 Connection + AMP2CSR_AMP2TS = 0x7 +) + +// Bitfields for LINUART: Local Interconnect Network +const ( + // LINCR: LIN Control Register + LINCR_LSWRES = 0x80 // Software Reset + LINCR_LIN13 = 0x40 // LIN Standard + LINCR_LCONF = 0x30 // LIN Configuration bits + LINCR_LENA = 0x8 // LIN or UART Enable + LINCR_LCMD = 0x7 // LIN Command and Mode bits + + // LINSIR: LIN Status and Interrupt Register + LINSIR_LIDST = 0xe0 // Identifier Status bits + LINSIR_LBUSY = 0x10 // Busy Signal + LINSIR_LERR = 0x8 // Error Interrupt + LINSIR_LIDOK = 0x4 // Identifier Interrupt + LINSIR_LTXOK = 0x2 // Transmit Performed Interrupt + LINSIR_LRXOK = 0x1 // Receive Performed Interrupt + + // LINENIR: LIN Enable Interrupt Register + LINENIR_LENERR = 0x8 // Enable Error Interrupt + LINENIR_LENIDOK = 0x4 // Enable Identifier Interrupt + LINENIR_LENTXOK = 0x2 // Enable Transmit Performed Interrupt + LINENIR_LENRXOK = 0x1 // Enable Receive Performed Interrupt + + // LINERR: LIN Error Register + LINERR_LABORT = 0x80 // Abort Flag + LINERR_LTOERR = 0x40 // Frame Time Out Error Flag + LINERR_LOVERR = 0x20 // Overrun Error Flag + LINERR_LFERR = 0x10 // Framing Error Flag + LINERR_LSERR = 0x8 // Synchronization Error Flag + LINERR_LPERR = 0x4 // Parity Error Flag + LINERR_LCERR = 0x2 // Checksum Error Flag + LINERR_LBERR = 0x1 // Bit Error Flag + + // LINBTR: LIN Bit Timing Register + LINBTR_LDISR = 0x80 // Disable Bit Timing Resynchronization + LINBTR_LBT = 0x3f // LIN Bit Timing bits + + // LINBRRL: LIN Baud Rate Register + + // LINBRRH: LIN Baud Rate Register + LINBRR_LDIV = 0xfff + + // LINDLR: LIN Data Length Register + LINDLR_LTXDL = 0xf0 // LIN Transmit Data Length bits + LINDLR_LRXDL = 0xf // LIN Receive Data Length bits + + // LINIDR: LIN Identifier Register + LINIDR_LP = 0xc0 // Parity bits + LINIDR_LID = 0x3f // Identifier bit 5 or Data Length bits + + // LINSEL: LIN Data Buffer Selection Register + LINSEL_LAINC = 0x8 // Auto Increment of Data Buffer Index (Active Low) + LINSEL_LINDX = 0x7 // FIFO LIN Data Buffer Index bits + + // LINDAT: LIN Data Register + LINDAT_LDATA = 0xff +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPDR: SPI Data Register + SPDR_SPDR = 0xff // SPI Data bits +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register + EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control 1 Bits + EICRA_ISC0 = 0x3 // External Interrupt Sense Control 0 Bits + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xf // External Interrupt Request 3 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xf // External Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0xf // Pin Change Interrupt Enables + + // PCMSK3: Pin Change Mask Register 3 + PCMSK3_PCINT = 0x7 // Pin Change Enable Masks + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0xf // Pin Change Interrupt Flags +) + +// Bitfields for EEPROM: EEPROM +const ( + // EEARL: EEPROM Read/Write Access + + // EEARH: EEPROM Read/Write Access + EEAR_EEAR = 0x3ff // EEPROM Address bits + + // EEDR: EEPROM Data Register + EEDR_EEDR = 0xff // EEPROM Data bits + + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming mode + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for PSC: Power Stage Controller +const ( + // PIFR: PSC Interrupt Flag Register + PIFR_PEV = 0xe // PSC External Event 2 Interrupt + PIFR_PEOP = 0x1 // PSC End of Cycle Interrupt + + // PIM: PSC Interrupt Mask Register + PIM_PEVE = 0xe // External Event 2 Interrupt Enable + PIM_PEOPE = 0x1 // PSC End of Cycle Interrupt Enable + + // PMIC2: PSC Module 2 Input Control Register + PMIC2_POVEN2 = 0x80 // PSC Module 2 Overlap Enable + PMIC2_PISEL2 = 0x40 // PSC Module 2 Input Select + PMIC2_PELEV2 = 0x20 // PSC Module 2 Input Level Selector + PMIC2_PFLTE2 = 0x10 // PSC Module 2 Input Filter Enable + PMIC2_PAOC2 = 0x8 // PSC Module 2 Asynchronous Output Control + PMIC2_PRFM2 = 0x7 // PSC Module 2 Input Mode bits + + // PMIC1: PSC Module 1 Input Control Register + PMIC1_POVEN1 = 0x80 // PSC Module 1 Overlap Enable + PMIC1_PISEL1 = 0x40 // PSC Module 1 Input Select + PMIC1_PELEV1 = 0x20 // PSC Module 1 Input Level Selector + PMIC1_PFLTE1 = 0x10 // PSC Module 1 Input Filter Enable + PMIC1_PAOC1 = 0x8 // PSC Module 1 Asynchronous Output Control + PMIC1_PRFM1 = 0x7 // PSC Module 1 Input Mode bits + + // PMIC0: PSC Module 0 Input Control Register + PMIC0_POVEN0 = 0x80 // PSC Module 0 Overlap Enable + PMIC0_PISEL0 = 0x40 // PSC Module 0 Input Select + PMIC0_PELEV0 = 0x20 // PSC Module 0 Input Level Selector + PMIC0_PFLTE0 = 0x10 // PSC Module 0 Input Filter Enable + PMIC0_PAOC0 = 0x8 // PSC Module 0 Asynchronous Output Control + PMIC0_PRFM0 = 0x7 // PSC Module 0 Input Mode bits + + // PCTL: PSC Control Register + PCTL_PPRE = 0xc0 // PSC Prescaler Select bits + PCTL_PCLKSEL = 0x20 // PSC Input Clock Select + PCTL_PCCYC = 0x2 // PSC Complete Cycle + PCTL_PRUN = 0x1 // PSC Run + + // POC: PSC Output Configuration + POC_POEN2B = 0x20 // PSC Output 2B Enable + POC_POEN2A = 0x10 // PSC Output 2A Enable + POC_POEN1B = 0x8 // PSC Output 1B Enable + POC_POEN1A = 0x4 // PSC Output 1A Enable + POC_POEN0B = 0x2 // PSC Output 0B Enable + POC_POEN0A = 0x1 // PSC Output 0A Enable + + // PCNF: PSC Configuration Register + PCNF_PULOCK = 0x20 // PSC Update Lock + PCNF_PMODE = 0x10 // PSC Mode + PCNF_POPB = 0x8 // PSC Output B Polarity + PCNF_POPA = 0x4 // PSC Output A Polarity + + // PSYNC: PSC Synchro Configuration + PSYNC_PSYNC2 = 0x30 // Selection of Synchronization Out for ADC + PSYNC_PSYNC1 = 0xc // Selection of Synchronization Out for ADC + PSYNC_PSYNC0 = 0x3 // Selection of Synchronization Out for ADC + + // POCR_RBL: PSC Output Compare RB Register + + // POCR_RBH: PSC Output Compare RB Register + POCR_RB_POCR_RB = 0xfff // PSC Output Compare RB bits + + // POCR2SBL: PSC Module 2 Output Compare SB Register + + // POCR2SBH: PSC Module 2 Output Compare SB Register + POCR2SB_POCR2SB = 0xfff // PSC Output Compare SB bits + + // POCR2RAL: PSC Module 2 Output Compare RA Register + + // POCR2RAH: PSC Module 2 Output Compare RA Register + POCR2RA_POCR2RA = 0xfff // PSC Output Compare RA bits + + // POCR2SAL: PSC Module 2 Output Compare SA Register + + // POCR2SAH: PSC Module 2 Output Compare SA Register + POCR2SA_POCR2SA = 0xfff // PSC Output Compare SA bits + + // POCR1SBL: PSC Module 1 Output Compare SB Register + + // POCR1SBH: PSC Module 1 Output Compare SB Register + POCR1SB_POCR1SB = 0xfff // PSC Output Compare SB bits + + // POCR1RAL: PSC Module 1 Output Compare RA Register + + // POCR1RAH: PSC Module 1 Output Compare RA Register + POCR1RA_POCR1RA = 0xfff // PSC Output Compare RA bits + + // POCR1SAL: PSC Module 1 Output Compare SA Register + + // POCR1SAH: PSC Module 1 Output Compare SA Register + POCR1SA_POCR1SA = 0xfff // PSC Output Compare SA bits + + // POCR0SBL: PSC Module 0 Output Compare SB Register + + // POCR0SBH: PSC Module 0 Output Compare SB Register + POCR0SB_POCR0SB = 0xfff // PSC Output Compare SB bits + + // POCR0RAL: PSC Module 0 Output Compare RA Register + + // POCR0RAH: PSC Module 0 Output Compare RA Register + POCR0RA_POCR0RA = 0xfff // PSC Output Compare RA bits + + // POCR0SAL: PSC Module 0 Output Compare SA Register + + // POCR0SAH: PSC Module 0 Output Compare SA Register + POCR0SA_POCR0SA = 0xfff // PSC Output Compare SA bits +) diff --git a/src/device/avr/atmega16m1.ld b/src/device/avr/atmega16m1.ld new file mode 100644 index 00000000..e0cf6d53 --- /dev/null +++ b/src/device/avr/atmega16m1.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega16M1.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_size = 0x400; +__num_isrs = 31; diff --git a/src/device/avr/atmega16u2.go b/src/device/avr/atmega16u2.go new file mode 100644 index 00000000..cf1301e5 --- /dev/null +++ b/src/device/avr/atmega16u2.go @@ -0,0 +1,842 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega16U2.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega16u2 + +// Device information for the ATmega16U2. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega16U2" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_INT3 = 4 // External Interrupt Request 3 + IRQ_INT4 = 5 // External Interrupt Request 4 + IRQ_INT5 = 6 // External Interrupt Request 5 + IRQ_INT6 = 7 // External Interrupt Request 6 + IRQ_INT7 = 8 // External Interrupt Request 7 + IRQ_PCINT0 = 9 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 10 // Pin Change Interrupt Request 1 + IRQ_USB_GEN = 11 // USB General Interrupt Request + IRQ_USB_COM = 12 // USB Endpoint/Pipe Interrupt Communication Request + IRQ_WDT = 13 // Watchdog Time-out Interrupt + IRQ_TIMER1_CAPT = 14 // Timer/Counter2 Capture Event + IRQ_TIMER1_COMPA = 15 // Timer/Counter2 Compare Match B + IRQ_TIMER1_COMPB = 16 // Timer/Counter2 Compare Match B + IRQ_TIMER1_COMPC = 17 // Timer/Counter2 Compare Match C + IRQ_TIMER1_OVF = 18 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 19 // Timer/Counter0 Compare Match A + IRQ_TIMER0_COMPB = 20 // Timer/Counter0 Compare Match B + IRQ_TIMER0_OVF = 21 // Timer/Counter0 Overflow + IRQ_SPI_STC = 22 // SPI Serial Transfer Complete + IRQ_USART1_RX = 23 // USART1, Rx Complete + IRQ_USART1_UDRE = 24 // USART1 Data register Empty + IRQ_USART1_TX = 25 // USART1, Tx Complete + IRQ_ANALOG_COMP = 26 // Analog Comparator + IRQ_EE_READY = 27 // EEPROM Ready + IRQ_SPM_READY = 28 // Store Program Memory Read + IRQ_max = 28 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // I/O Port + PORT = struct { + PORTB __reg + DDRB __reg + PINB __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTC __reg + DDRC __reg + PINC __reg + }{ + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Low Bytes + EEARH: 0x41, // EEPROM Address Register Low Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + GTCCR __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + GTCCR: 0x43, // General Timer/Counter Control Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + OCR1CL __reg + OCR1CH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1CL: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + OCR1CH: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // Phase Locked Loop + PLL = struct { + PLLCSR __reg + }{ + PLLCSR: 0x49, // PLL Status and Control register + } + + // USB Device Registers + USB_DEVICE = struct { + UPOE __reg + UEINT __reg + UEBCLX __reg + UEDATX __reg + UEIENX __reg + UESTA1X __reg + UESTA0X __reg + UECFG1X __reg + UECFG0X __reg + UECONX __reg + UERST __reg + UENUM __reg + UEINTX __reg + UDMFN __reg + UDFNUML __reg + UDFNUMH __reg + UDADDR __reg + UDIEN __reg + UDINT __reg + UDCON __reg + USBCON __reg + REGCR __reg + }{ + UPOE: 0xfb, // USB Software Output Enable register + UEINT: 0xf4, // USB Endpoint Number Interrupt Register + UEBCLX: 0xf2, // USB Endpoint Byte Count Register + UEDATX: 0xf1, // USB Data Endpoint + UEIENX: 0xf0, // USB Endpoint Interrupt Enable Register + UESTA1X: 0xef, // USB Endpoint Status 1 Register + UESTA0X: 0xee, // USB Endpoint Status 0 Register + UECFG1X: 0xed, // USB Endpoint Configuration 1 Register + UECFG0X: 0xec, // USB Endpoint Configuration 0 Register + UECONX: 0xeb, // USB Endpoint Control Register + UERST: 0xea, // USB Endpoint Reset Register + UENUM: 0xe9, // USB Endpoint Number + UEINTX: 0xe8, // USB Endpoint Interrupt Register + UDMFN: 0xe6, // USB Device Micro Frame Number + UDFNUML: 0xe4, // USB Device Frame Number High Register + UDFNUMH: 0xe4, // USB Device Frame Number High Register + UDADDR: 0xe3, // USB Device Address Register + UDIEN: 0xe2, // USB Device Interrupt Enable Register + UDINT: 0xe1, // USB Device Interrupt Register + UDCON: 0xe0, // USB Device Control Registers + USBCON: 0xd8, // USB General Control Register + REGCR: 0x63, // Regulator Control Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + MCUCR __reg + MCUSR __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + EIND __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PRR1 __reg + PRR0 __reg + CLKSTA __reg + CLKSEL1 __reg + CLKSEL0 __reg + DWDR __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, + SMCR: 0x53, // Sleep Mode Control Register + EIND: 0x5c, // Extended Indirect Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PRR1: 0x65, // Power Reduction Register1 + PRR0: 0x64, // Power Reduction Register0 + CLKSTA: 0xd2, + CLKSEL1: 0xd1, + CLKSEL0: 0xd0, + DWDR: 0x51, // debugWire communication register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EICRB __reg + EIMSK __reg + EIFR __reg + PCMSK0 __reg + PCMSK1 __reg + PCIFR __reg + PCICR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EICRB: 0x6a, // External Interrupt Control Register B + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + } + + // USART + USART = struct { + UDR1 __reg + UCSR1A __reg + UCSR1B __reg + UCSR1C __reg + UCSR1D __reg + UBRR1L __reg + UBRR1H __reg + }{ + UDR1: 0xce, // USART I/O Data Register + UCSR1A: 0xc8, // USART Control and Status Register A + UCSR1B: 0xc9, // USART Control and Status Register B + UCSR1C: 0xca, // USART Control and Status Register C + UCSR1D: 0xcb, // USART Control and Status Register D + UBRR1L: 0xcc, // USART Baud Rate Register Bytes + UBRR1H: 0xcc, // USART Baud Rate Register Bytes + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + WDTCKD __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + WDTCKD: 0x62, // Watchdog Timer Clock Divider + } + + // Analog Comparator + AC = struct { + ACSR __reg + ACMUX __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + ACMUX: 0x7d, // Analog Comparator Input Multiplexer + DIDR1: 0x7f, + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level + EXTENDED_HWBE = 0x8 // Hardware Boot Enable + + // HIGH + HIGH_DWEN = 0x80 // Debug Wire enable + HIGH_RSTDISBL = 0x40 // Reset Disabled (Enable PC6 as i/o pin) + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTC7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for PORT: I/O Port +const ( + // PORTC: Port C Data Register + PORTC_PORTC = 0xf0 // Port C Data Register bits + PORTC_PORTC = 0x7 // Port C Data Register bits + + // DDRC: Port C Data Direction Register + DDRC_DDC = 0xf0 // Port C Data Direction Register bits + DDRC_DDC = 0x7 // Port C Data Direction Register bits + + // PINC: Port C Input Pins + PINC_PINC = 0xf0 // Port C Input Pins bits + PINC_PINC = 0x7 // Port C Input Pins bits +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPDR: SPI Data Register + SPDR_SPDR = 0xff // SPI Data bits +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for EEPROM: EEPROM +const ( + // EEARL: EEPROM Address Register Low Bytes + + // EEARH: EEPROM Address Register Low Bytes + EEAR_EEAR = 0xfff // EEPROM Address bits + + // EEDR: EEPROM Data Register + EEDR_EEDR = 0xff // EEPROM Data bits + + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // OCR0B: Timer/Counter0 Output Compare Register + OCR0B_OCR0B = 0xff // Timer/Counter0 Output Compare B bits + + // OCR0A: Timer/Counter0 Output Compare Register + OCR0A_OCR0A = 0xff // Timer/Counter0 Output Compare A bits + + // TCNT0: Timer/Counter0 + TCNT0_TCNT0 = 0xff // Timer/Counter0 bits + + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag + + // GTCCR: General Timer/Counter Control Register + GTCCR_TSM = 0x80 // Timer/Counter Synchronization Mode + GTCCR_PSRSYNC = 0x1 // Prescaler Reset Timer/Counter1 and Timer/Counter0 +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_COM1C = 0xc // Compare Output Mode 1C, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + TCCR1C_FOC1C = 0x20 // Force Output Compare 1C + + // TCNT1L: Timer/Counter1 Bytes + + // TCNT1H: Timer/Counter1 Bytes + TCNT1_TCNT1 = 0xffff // Timer/Counter1 bits + + // OCR1AL: Timer/Counter1 Output Compare Register A Bytes + + // OCR1AH: Timer/Counter1 Output Compare Register A Bytes + OCR1A_OCR1A = 0xffff // Timer/Counter1 Output Compare A bits + + // OCR1BL: Timer/Counter1 Output Compare Register B Bytes + + // OCR1BH: Timer/Counter1 Output Compare Register B Bytes + OCR1B_OCR1B = 0xffff // Timer/Counter1 Output Compare B bits + + // OCR1CL: Timer/Counter1 Output Compare Register C Bytes + + // OCR1CH: Timer/Counter1 Output Compare Register C Bytes + OCR1C_OCR1C = 0xffff // Timer/Counter1 Output Compare C bits + + // ICR1L: Timer/Counter1 Input Capture Register Bytes + + // ICR1H: Timer/Counter1 Input Capture Register Bytes + ICR1_ICR1 = 0xffff // Timer/Counter1 Input Capture bits + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1C = 0x8 // Timer/Counter1 Output Compare C Match Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1C = 0x8 // Output Compare Flag 1C + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for PLL: Phase Locked Loop +const ( + // PLLCSR: PLL Status and Control register + PLLCSR_PLLP = 0x1c // PLL prescaler Bits + PLLCSR_PLLE = 0x2 // PLL Enable Bit + PLLCSR_PLOCK = 0x1 // PLL Lock Status Bit +) + +// Bitfields for USB_DEVICE: USB Device Registers +const ( + // UPOE: USB Software Output Enable register + UPOE_UPWE = 0xc0 // USB Buffers Direct Drive enable configuration + UPOE_UPDRV = 0x30 // USB direct drive values + UPOE_DPI = 0x2 // D+ Input value + UPOE_DMI = 0x1 // D- Input value + + // UEINT: USB Endpoint Number Interrupt Register + UEINT_EPINT = 0x1f // Byte Count bits + + // UEBCLX: USB Endpoint Byte Count Register + UEBCLX_BYCT = 0xff // Byte Count bits + + // UEDATX: USB Data Endpoint + UEDATX_DAT = 0xff // Data bits + + // UEIENX: USB Endpoint Interrupt Enable Register + UEIENX_FLERRE = 0x80 // Flow Error Interrupt Enable Flag + UEIENX_NAKINE = 0x40 // NAK IN Interrupt Enable Bit + UEIENX_NAKOUTE = 0x10 // NAK OUT Interrupt Enable Bit + UEIENX_RXSTPE = 0x8 // Received SETUP Interrupt Enable Flag + UEIENX_RXOUTE = 0x4 // Received OUT Data Interrupt Enable Flag + UEIENX_STALLEDE = 0x2 // Stalled Interrupt Enable Flag + UEIENX_TXINE = 0x1 // Transmitter Ready Interrupt Enable Flag + + // UESTA1X: USB Endpoint Status 1 Register + UESTA1X_CTRLDIR = 0x4 // Control Direction + UESTA1X_CURRBK = 0x3 // Current Bank + + // UESTA0X: USB Endpoint Status 0 Register + UESTA0X_CFGOK = 0x80 // Configuration Status Flag + UESTA0X_OVERFI = 0x40 // Overflow Error Interrupt Flag + UESTA0X_UNDERFI = 0x20 // Underflow Error Interrupt Flag + UESTA0X_DTSEQ = 0xc // Data Toggle Sequencing Flag + UESTA0X_NBUSYBK = 0x3 // Busy Bank Flag + + // UECFG1X: USB Endpoint Configuration 1 Register + UECFG1X_EPSIZE = 0x70 // Endpoint Size Bits + UECFG1X_EPBK = 0xc // Endpoint Bank Bits + UECFG1X_ALLOC = 0x2 // Endpoint Allocation Bit + + // UECFG0X: USB Endpoint Configuration 0 Register + UECFG0X_EPTYPE = 0xc0 // Endpoint Type Bits + UECFG0X_EPDIR = 0x1 // Endpoint Direction Bit + + // UECONX: USB Endpoint Control Register + UECONX_STALLRQ = 0x20 // STALL Request Handshake Bit + UECONX_STALLRQC = 0x10 // STALL Request Clear Handshake Bit + UECONX_RSTDT = 0x8 // Reset Data Toggle Bit + UECONX_EPEN = 0x1 // Endpoint Enable Bit + + // UERST: USB Endpoint Reset Register + UERST_EPRST = 0x1f // Endpoint FIFO Reset Bits + + // UENUM: USB Endpoint Number + UENUM_EPNUM = 0x7 // Endpoint Number bits + + // UEINTX: USB Endpoint Interrupt Register + UEINTX_FIFOCON = 0x80 // FIFO Control Bit + UEINTX_NAKINI = 0x40 // NAK IN Received Interrupt Flag + UEINTX_RWAL = 0x20 // Read/Write Allowed Flag + UEINTX_NAKOUTI = 0x10 // NAK OUT Received Interrupt Flag + UEINTX_RXSTPI = 0x8 // Received SETUP Interrupt Flag + UEINTX_RXOUTI = 0x4 // Received OUT Data Interrupt Flag + UEINTX_STALLEDI = 0x2 // STALLEDI Interrupt Flag + UEINTX_TXINI = 0x1 // Transmitter Ready Interrupt Flag + + // UDMFN: USB Device Micro Frame Number + UDMFN_FNCERR = 0x10 // Frame Number CRC Error Flag + + // UDFNUML: USB Device Frame Number High Register + + // UDFNUMH: USB Device Frame Number High Register + UDFNUM_FNUM = 0x7ff // Frame Number Upper Flag + + // UDADDR: USB Device Address Register + UDADDR_ADDEN = 0x80 // Address Enable Bit + UDADDR_UADD = 0x7f // USB Address Bits + + // UDIEN: USB Device Interrupt Enable Register + UDIEN_UPRSME = 0x40 // Upstream Resume Interrupt Enable Bit + UDIEN_EORSME = 0x20 // End Of Resume Interrupt Enable Bit + UDIEN_WAKEUPE = 0x10 // Wake-up CPU Interrupt Enable Bit + UDIEN_EORSTE = 0x8 // End Of Reset Interrupt Enable Bit + UDIEN_SOFE = 0x4 // Start Of Frame Interrupt Enable Bit + UDIEN_SUSPE = 0x1 // Suspend Interrupt Enable Bit + + // UDINT: USB Device Interrupt Register + UDINT_UPRSMI = 0x40 // Upstream Resume Interrupt Flag + UDINT_EORSMI = 0x20 // End Of Resume Interrupt Flag + UDINT_WAKEUPI = 0x10 // Wake-up CPU Interrupt Flag + UDINT_EORSTI = 0x8 // End Of Reset Interrupt Flag + UDINT_SOFI = 0x4 // Start Of Frame Interrupt Flag + UDINT_SUSPI = 0x1 // Suspend Interrupt Flag + + // UDCON: USB Device Control Registers + UDCON_RSTCPU = 0x4 // USB Reset CPU Bit + UDCON_RMWKUP = 0x2 // Remote Wake-up Bit + UDCON_DETACH = 0x1 // Detach Bit + + // USBCON: USB General Control Register + USBCON_USBE = 0x80 // USB macro Enable Bit + USBCON_FRZCLK = 0x20 // Freeze USB Clock Bit + + // REGCR: Regulator Control Register + REGCR_REGDIS = 0x1 // Regulator Disable +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // MCUCR: MCU Control Register + MCUCR_PUD = 0x10 // Pull-up disable + MCUCR_IVSEL = 0x2 // Interrupt Vector Select + MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable + + // MCUSR: MCU Status Register + MCUSR_USBRF = 0x20 // USB reset flag + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BORF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 + + // PRR1: Power Reduction Register1 + PRR1_PRUSB = 0x80 // Power Reduction USB + PRR1_PRUSART1 = 0x1 // Power Reduction USART1 + + // PRR0: Power Reduction Register0 + PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + + // CLKSTA + CLKSTA_RCON = 0x2 + CLKSTA_EXTON = 0x1 + + // CLKSEL1 + CLKSEL1_RCCKSEL = 0xf0 + CLKSEL1_EXCKSEL = 0xf + + // CLKSEL0 + CLKSEL0_RCSUT = 0xc0 + CLKSEL0_EXSUT = 0x30 + CLKSEL0_RCE = 0x8 + CLKSEL0_EXTE = 0x4 + CLKSEL0_CLKS = 0x1 +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EICRB: External Interrupt Control Register B + EICRB_ISC7 = 0xc0 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC6 = 0x30 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC5 = 0xc // External Interrupt 7-4 Sense Control Bit + EICRB_ISC4 = 0x3 // External Interrupt 7-4 Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xff // External Interrupt Request 7 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xff // External Interrupt Flags + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0x1f + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0x3 // Pin Change Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0x3 // Pin Change Interrupt Enables +) + +// Bitfields for USART: USART +const ( + // UDR1: USART I/O Data Register + UDR1_UDR1 = 0xff // USART I/O Data bits + + // UCSR1A: USART Control and Status Register A + UCSR1A_RXC1 = 0x80 // USART Receive Complete + UCSR1A_TXC1 = 0x40 // USART Transmitt Complete + UCSR1A_UDRE1 = 0x20 // USART Data Register Empty + UCSR1A_FE1 = 0x10 // Framing Error + UCSR1A_DOR1 = 0x8 // Data overRun + UCSR1A_UPE1 = 0x4 // Parity Error + UCSR1A_U2X1 = 0x2 // Double the USART transmission speed + UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode + + // UCSR1B: USART Control and Status Register B + UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable + UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable + UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable + UCSR1B_RXEN1 = 0x10 // Receiver Enable + UCSR1B_TXEN1 = 0x8 // Transmitter Enable + UCSR1B_UCSZ12 = 0x4 // Character Size + UCSR1B_RXB81 = 0x2 // Receive Data Bit 8 + UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8 + + // UCSR1C: USART Control and Status Register C + UCSR1C_UMSEL1 = 0xc0 // USART Mode Select + UCSR1C_UPM1 = 0x30 // Parity Mode Bits + UCSR1C_USBS1 = 0x8 // Stop Bit Select + UCSR1C_UCSZ1 = 0x6 // Character Size + UCSR1C_UCPOL1 = 0x1 // Clock Polarity + + // UCSR1D: USART Control and Status Register D + UCSR1D_CTSEN = 0x2 // CTS Enable + UCSR1D_RTSEN = 0x1 // RTS Enable + + // UBRR1L: USART Baud Rate Register Bytes + + // UBRR1H: USART Baud Rate Register Bytes + UBRR1_UBRR1 = 0xfff // USART Baud Rate bits +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable + + // WDTCKD: Watchdog Timer Clock Divider + WDTCKD_WDEWIF = 0x8 // Watchdog Early Warning Interrupt Flag + WDTCKD_WDEWIE = 0x4 // Watchdog Early Warning Interrupt Enable + WDTCKD_WCLKD = 0x3 // Watchdog Timer Clock Dividers +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // ACMUX: Analog Comparator Input Multiplexer + ACMUX_CMUX = 0x7 // Analog Comparator Selection Bits + + // DIDR1 + DIDR1_AIN7D = 0x80 // AIN7 Digital Input Disable + DIDR1_AIN6D = 0x40 // AIN6 Digital Input Disable + DIDR1_AIN5D = 0x20 // AIN5 Digital Input Disable + DIDR1_AIN4D = 0x10 // AIN4 Digital Input Disable + DIDR1_AIN3D = 0x8 // AIN3 Digital Input Disable + DIDR1_AIN2D = 0x4 // AIN2 Digital Input Disable + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) diff --git a/src/device/avr/atmega16u2.ld b/src/device/avr/atmega16u2.ld new file mode 100644 index 00000000..a66ab1a9 --- /dev/null +++ b/src/device/avr/atmega16u2.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega16U2.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_size = 0x200; +__num_isrs = 29; diff --git a/src/device/avr/atmega16u4.go b/src/device/avr/atmega16u4.go new file mode 100644 index 00000000..39891f9c --- /dev/null +++ b/src/device/avr/atmega16u4.go @@ -0,0 +1,1137 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega16U4.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega16u4 + +// Device information for the ATmega16U4. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega16U4" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_INT3 = 4 // External Interrupt Request 3 + IRQ_Reserved1 = 5 // Reserved1 + IRQ_Reserved2 = 6 // Reserved2 + IRQ_INT6 = 7 // External Interrupt Request 6 + IRQ_Reserved3 = 8 // Reserved3 + IRQ_PCINT0 = 9 // Pin Change Interrupt Request 0 + IRQ_USB_GEN = 10 // USB General Interrupt Request + IRQ_USB_COM = 11 // USB Endpoint/Pipe Interrupt Communication Request + IRQ_WDT = 12 // Watchdog Time-out Interrupt + IRQ_Reserved4 = 13 // Reserved4 + IRQ_Reserved5 = 14 // Reserved5 + IRQ_Reserved6 = 15 // Reserved6 + IRQ_TIMER1_CAPT = 16 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 17 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 18 // Timer/Counter1 Compare Match B + IRQ_TIMER1_COMPC = 19 // Timer/Counter1 Compare Match C + IRQ_TIMER1_OVF = 20 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 21 // Timer/Counter0 Compare Match A + IRQ_TIMER0_COMPB = 22 // Timer/Counter0 Compare Match B + IRQ_TIMER0_OVF = 23 // Timer/Counter0 Overflow + IRQ_SPI_STC = 24 // SPI Serial Transfer Complete + IRQ_USART1_RX = 25 // USART1, Rx Complete + IRQ_USART1_UDRE = 26 // USART1 Data register Empty + IRQ_USART1_TX = 27 // USART1, Tx Complete + IRQ_ANALOG_COMP = 28 // Analog Comparator + IRQ_ADC = 29 // ADC Conversion Complete + IRQ_EE_READY = 30 // EEPROM Ready + IRQ_TIMER3_CAPT = 31 // Timer/Counter3 Capture Event + IRQ_TIMER3_COMPA = 32 // Timer/Counter3 Compare Match A + IRQ_TIMER3_COMPB = 33 // Timer/Counter3 Compare Match B + IRQ_TIMER3_COMPC = 34 // Timer/Counter3 Compare Match C + IRQ_TIMER3_OVF = 35 // Timer/Counter3 Overflow + IRQ_TWI = 36 // 2-wire Serial Interface + IRQ_SPM_READY = 37 // Store Program Memory Read + IRQ_TIMER4_COMPA = 38 // Timer/Counter4 Compare Match A + IRQ_TIMER4_COMPB = 39 // Timer/Counter4 Compare Match B + IRQ_TIMER4_COMPD = 40 // Timer/Counter4 Compare Match D + IRQ_TIMER4_OVF = 41 // Timer/Counter4 Overflow + IRQ_TIMER4_FPF = 42 // Timer/Counter4 Fault Protection Interrupt + IRQ_max = 42 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // I/O Port + PORT = struct { + PORTD __reg + DDRD __reg + PIND __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + }{ + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // USART + USART = struct { + UDR1 __reg + UCSR1A __reg + UCSR1B __reg + UCSR1C __reg + UCSR1D __reg + UBRR1L __reg + UBRR1H __reg + }{ + UDR1: 0xce, // USART I/O Data Register + UCSR1A: 0xc8, // USART Control and Status Register A + UCSR1B: 0xc9, // USART Control and Status Register B + UCSR1C: 0xca, // USART Control and Status Register C + UCSR1D: 0xcb, // USART Control and Status Register D + UBRR1L: 0xcc, // USART Baud Rate Register Bytes + UBRR1H: 0xcc, // USART Baud Rate Register Bytes + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Low Bytes + EEARH: 0x41, // EEPROM Address Register Low Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + GTCCR __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + GTCCR: 0x43, // General Timer/Counter Control Register + } + + // Timer/Counter, 10-bit + TC10 = struct { + TCCR4A __reg + TCCR4B __reg + TCCR4C __reg + TCCR4D __reg + TCCR4E __reg + TCNT4 __reg + TC4H __reg + OCR4A __reg + OCR4B __reg + OCR4C __reg + OCR4D __reg + TIMSK4 __reg + TIFR4 __reg + DT4 __reg + }{ + TCCR4A: 0xc0, // Timer/Counter4 Control Register A + TCCR4B: 0xc1, // Timer/Counter4 Control Register B + TCCR4C: 0xc2, // Timer/Counter 4 Control Register C + TCCR4D: 0xc3, // Timer/Counter 4 Control Register D + TCCR4E: 0xc4, // Timer/Counter 4 Control Register E + TCNT4: 0xbe, // Timer/Counter4 Low Bytes + TC4H: 0xbf, // Timer/Counter4 + OCR4A: 0xcf, // Timer/Counter4 Output Compare Register A + OCR4B: 0xd0, // Timer/Counter4 Output Compare Register B + OCR4C: 0xd1, // Timer/Counter4 Output Compare Register C + OCR4D: 0xd2, // Timer/Counter4 Output Compare Register D + TIMSK4: 0x72, // Timer/Counter4 Interrupt Mask Register + TIFR4: 0x39, // Timer/Counter4 Interrupt Flag register + DT4: 0xd4, // Timer/Counter 4 Dead Time Value + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR3A __reg + TCCR3B __reg + TCCR3C __reg + TCNT3L __reg + TCNT3H __reg + OCR3AL __reg + OCR3AH __reg + OCR3BL __reg + OCR3BH __reg + OCR3CL __reg + OCR3CH __reg + ICR3L __reg + ICR3H __reg + TIMSK3 __reg + TIFR3 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + OCR1CL __reg + OCR1CH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR3A: 0x90, // Timer/Counter3 Control Register A + TCCR3B: 0x91, // Timer/Counter3 Control Register B + TCCR3C: 0x92, // Timer/Counter 3 Control Register C + TCNT3L: 0x94, // Timer/Counter3 Bytes + TCNT3H: 0x94, // Timer/Counter3 Bytes + OCR3AL: 0x98, // Timer/Counter3 Output Compare Register A Bytes + OCR3AH: 0x98, // Timer/Counter3 Output Compare Register A Bytes + OCR3BL: 0x9a, // Timer/Counter3 Output Compare Register B Bytes + OCR3BH: 0x9a, // Timer/Counter3 Output Compare Register B Bytes + OCR3CL: 0x9c, // Timer/Counter3 Output Compare Register C Bytes + OCR3CH: 0x9c, // Timer/Counter3 Output Compare Register C Bytes + ICR3L: 0x96, // Timer/Counter3 Input Capture Register Bytes + ICR3H: 0x96, // Timer/Counter3 Input Capture Register Bytes + TIMSK3: 0x71, // Timer/Counter3 Interrupt Mask Register + TIFR3: 0x38, // Timer/Counter3 Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1CL: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + OCR1CH: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EICRB __reg + EIMSK __reg + EIFR __reg + PCMSK0 __reg + PCIFR __reg + PCICR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EICRB: 0x6a, // External Interrupt Control Register B + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + DIDR2 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 1 + DIDR2: 0x7d, // Digital Input Disable Register 1 + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + RCCTRL __reg + CLKPR __reg + SMCR __reg + EIND __reg + RAMPZ __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PRR1 __reg + PRR0 __reg + CLKSTA __reg + CLKSEL1 __reg + CLKSEL0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + RCCTRL: 0x67, // Oscillator Control Register + CLKPR: 0x61, + SMCR: 0x53, // Sleep Mode Control Register + EIND: 0x5c, // Extended Indirect Register + RAMPZ: 0x5b, // Extended Z-pointer Register for ELPM/SPM + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PRR1: 0x65, // Power Reduction Register1 + PRR0: 0x64, // Power Reduction Register0 + CLKSTA: 0xc7, + CLKSEL1: 0xc6, + CLKSEL0: 0xc5, + } + + // Phase Locked Loop + PLL = struct { + PLLCSR __reg + PLLFRQ __reg + }{ + PLLCSR: 0x49, // PLL Status and Control register + PLLFRQ: 0x52, // PLL Frequency Control Register + } + + // USB Device Registers + USB_DEVICE = struct { + UEINT __reg + UEBCHX __reg + UEBCLX __reg + UEDATX __reg + UEIENX __reg + UESTA1X __reg + UESTA0X __reg + UECFG1X __reg + UECFG0X __reg + UECONX __reg + UERST __reg + UENUM __reg + UEINTX __reg + UDMFN __reg + UDFNUML __reg + UDFNUMH __reg + UDADDR __reg + UDIEN __reg + UDINT __reg + UDCON __reg + USBCON __reg + USBINT __reg + USBSTA __reg + UHWCON __reg + }{ + UEINT: 0xf4, + UEBCHX: 0xf3, + UEBCLX: 0xf2, + UEDATX: 0xf1, + UEIENX: 0xf0, + UESTA1X: 0xef, + UESTA0X: 0xee, + UECFG1X: 0xed, + UECFG0X: 0xec, + UECONX: 0xeb, + UERST: 0xea, + UENUM: 0xe9, + UEINTX: 0xe8, + UDMFN: 0xe6, + UDFNUML: 0xe4, + UDFNUMH: 0xe4, + UDADDR: 0xe3, + UDIEN: 0xe2, + UDINT: 0xe1, + UDCON: 0xe0, + USBCON: 0xd8, // USB General Control Register + USBINT: 0xda, + USBSTA: 0xd9, + UHWCON: 0xd7, + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level + EXTENDED_HWBE = 0x8 // Hardware Boot Enable + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTC7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPDR: SPI Data Register + SPDR_SPDR = 0xff // SPI Data bits +) + +// Bitfields for USART: USART +const ( + // UDR1: USART I/O Data Register + UDR1_UDR1 = 0xff // USART I/O Data bits + + // UCSR1A: USART Control and Status Register A + UCSR1A_RXC1 = 0x80 // USART Receive Complete + UCSR1A_TXC1 = 0x40 // USART Transmitt Complete + UCSR1A_UDRE1 = 0x20 // USART Data Register Empty + UCSR1A_FE1 = 0x10 // Framing Error + UCSR1A_DOR1 = 0x8 // Data overRun + UCSR1A_UPE1 = 0x4 // Parity Error + UCSR1A_U2X1 = 0x2 // Double the USART transmission speed + UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode + + // UCSR1B: USART Control and Status Register B + UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable + UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable + UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable + UCSR1B_RXEN1 = 0x10 // Receiver Enable + UCSR1B_TXEN1 = 0x8 // Transmitter Enable + UCSR1B_UCSZ12 = 0x4 // Character Size + UCSR1B_RXB81 = 0x2 // Receive Data Bit 8 + UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8 + + // UCSR1C: USART Control and Status Register C + UCSR1C_UMSEL1 = 0xc0 // USART Mode Select + UCSR1C_UPM1 = 0x30 // Parity Mode Bits + UCSR1C_USBS1 = 0x8 // Stop Bit Select + UCSR1C_UCSZ1 = 0x6 // Character Size + UCSR1C_UCPOL1 = 0x1 // Clock Polarity + + // UCSR1D: USART Control and Status Register D + UCSR1D_CTSEN = 0x2 // CTS Enable + UCSR1D_RTSEN = 0x1 // RTS Enable +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for EEPROM: EEPROM +const ( + // EEARL: EEPROM Address Register Low Bytes + + // EEARH: EEPROM Address Register Low Bytes + EEAR_EEAR = 0xfff // EEPROM Address Bits + + // EEDR: EEPROM Data Register + EEDR_EEDR = 0xff // EEPROM Data Bits + + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // OCR0B: Timer/Counter0 Output Compare Register + OCR0B_OCR0B = 0xff // Timer/Counter0 Output Compare B bits + + // OCR0A: Timer/Counter0 Output Compare Register + OCR0A_OCR0A = 0xff // Timer/Counter0 Output Compare A bits + + // TCNT0: Timer/Counter0 + TCNT0_TCNT0 = 0xff // Timer/Counter0 bits + + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag + + // GTCCR: General Timer/Counter Control Register + GTCCR_TSM = 0x80 // Timer/Counter Synchronization Mode + GTCCR_PSRSYNC = 0x1 // Prescaler Reset Timer/Counter1 and Timer/Counter0 +) + +// Bitfields for TC10: Timer/Counter, 10-bit +const ( + // TCCR4A: Timer/Counter4 Control Register A + TCCR4A_COM4A = 0xc0 // Compare Output Mode 1A, bits + TCCR4A_COM4B = 0x30 // Compare Output Mode 4B, bits + TCCR4A_FOC4A = 0x8 // Force Output Compare Match 4A + TCCR4A_FOC4B = 0x4 // Force Output Compare Match 4B + TCCR4A_PWM4A = 0x2 + TCCR4A_PWM4B = 0x1 + + // TCCR4B: Timer/Counter4 Control Register B + TCCR4B_PWM4X = 0x80 // PWM Inversion Mode + TCCR4B_PSR4 = 0x40 // Prescaler Reset Timer/Counter 4 + TCCR4B_DTPS4 = 0x30 // Dead Time Prescaler Bits + TCCR4B_CS4 = 0xf // Clock Select Bits + + // TCCR4C: Timer/Counter 4 Control Register C + TCCR4C_COM4A1S = 0x80 // Comparator A Output Mode + TCCR4C_COM4A0S = 0x40 // Comparator A Output Mode + TCCR4C_COM4B1S = 0x20 // Comparator B Output Mode + TCCR4C_COM4B0S = 0x10 // Comparator B Output Mode + TCCR4C_COM4D = 0xc // Comparator D Output Mode + TCCR4C_FOC4D = 0x2 // Force Output Compare Match 4D + TCCR4C_PWM4D = 0x1 // Pulse Width Modulator D Enable + + // TCCR4D: Timer/Counter 4 Control Register D + TCCR4D_FPIE4 = 0x80 // Fault Protection Interrupt Enable + TCCR4D_FPEN4 = 0x40 // Fault Protection Mode Enable + TCCR4D_FPNC4 = 0x20 // Fault Protection Noise Canceler + TCCR4D_FPES4 = 0x10 // Fault Protection Edge Select + TCCR4D_FPAC4 = 0x8 // Fault Protection Analog Comparator Enable + TCCR4D_FPF4 = 0x4 // Fault Protection Interrupt Flag + TCCR4D_WGM4 = 0x3 // Waveform Generation Mode bits + + // TCCR4E: Timer/Counter 4 Control Register E + TCCR4E_TLOCK4 = 0x80 // Register Update Lock + TCCR4E_ENHC4 = 0x40 // Enhanced Compare/PWM Mode + TCCR4E_OC4OE = 0x3f // Output Compare Override Enable bit + + // TCNT4: Timer/Counter4 Low Bytes + TCNT4_TC4 = 0xff // Timer/Counter4 bits + + // TC4H: Timer/Counter4 + TC4H_TC4 = 0x7 // Timer/Counter4 bits + + // OCR4A: Timer/Counter4 Output Compare Register A + OCR4A_OCR4A = 0xff // Timer/Counter4 Output Compare A bits + + // OCR4B: Timer/Counter4 Output Compare Register B + OCR4B_OCR4B = 0xff // Timer/Counter4 Output Compare B bits + + // OCR4C: Timer/Counter4 Output Compare Register C + OCR4C_OCR4C = 0xff // Timer/Counter4 Output Compare C bits + + // OCR4D: Timer/Counter4 Output Compare Register D + OCR4D_OCR4D = 0xff // Timer/Counter4 Output Compare D bits + + // TIMSK4: Timer/Counter4 Interrupt Mask Register + TIMSK4_OCIE4D = 0x80 // Timer/Counter4 Output Compare D Match Interrupt Enable + TIMSK4_OCIE4A = 0x40 // Timer/Counter4 Output Compare A Match Interrupt Enable + TIMSK4_OCIE4B = 0x20 // Timer/Counter4 Output Compare B Match Interrupt Enable + TIMSK4_TOIE4 = 0x4 // Timer/Counter4 Overflow Interrupt Enable + + // TIFR4: Timer/Counter4 Interrupt Flag register + TIFR4_OCF4D = 0x80 // Output Compare Flag 4D + TIFR4_OCF4A = 0x40 // Output Compare Flag 4A + TIFR4_OCF4B = 0x20 // Output Compare Flag 4B + TIFR4_TOV4 = 0x4 // Timer/Counter4 Overflow Flag + + // DT4: Timer/Counter 4 Dead Time Value + DT4_DT4L = 0xff // Timer/Counter 4 Dead Time Value Bits +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR3A: Timer/Counter3 Control Register A + TCCR3A_COM3A = 0xc0 // Compare Output Mode 1A, bits + TCCR3A_COM3B = 0x30 // Compare Output Mode 3B, bits + TCCR3A_COM3C = 0xc // Compare Output Mode 3C, bits + TCCR3A_WGM3 = 0x3 // Waveform Generation Mode + + // TCCR3B: Timer/Counter3 Control Register B + TCCR3B_ICNC3 = 0x80 // Input Capture 3 Noise Canceler + TCCR3B_ICES3 = 0x40 // Input Capture 3 Edge Select + TCCR3B_WGM3 = 0x18 // Waveform Generation Mode + TCCR3B_CS3 = 0x7 // Prescaler source of Timer/Counter 3 + + // TCCR3C: Timer/Counter 3 Control Register C + TCCR3C_FOC3A = 0x80 // Force Output Compare 3A + TCCR3C_FOC3B = 0x40 // Force Output Compare 3B + TCCR3C_FOC3C = 0x20 // Force Output Compare 3C + + // TCNT3L: Timer/Counter3 Bytes + + // TCNT3H: Timer/Counter3 Bytes + TCNT3_TCNT3 = 0xffff // Timer/Counter3 bits + + // OCR3AL: Timer/Counter3 Output Compare Register A Bytes + + // OCR3AH: Timer/Counter3 Output Compare Register A Bytes + OCR3A_OCR3A = 0xffff // Timer/Counter3 Output Compare A bits + + // OCR3BL: Timer/Counter3 Output Compare Register B Bytes + + // OCR3BH: Timer/Counter3 Output Compare Register B Bytes + OCR3B_OCR3B = 0xffff // Timer/Counter3 Output Compare B bits + + // OCR3CL: Timer/Counter3 Output Compare Register C Bytes + + // OCR3CH: Timer/Counter3 Output Compare Register C Bytes + OCR3C_OCR3C = 0xffff // Timer/Counter3 Output Compare C bits + + // ICR3L: Timer/Counter3 Input Capture Register Bytes + + // ICR3H: Timer/Counter3 Input Capture Register Bytes + ICR3_ICR3 = 0xffff // Timer/Counter3 Input Capture bits + + // TIMSK3: Timer/Counter3 Interrupt Mask Register + TIMSK3_ICIE3 = 0x20 // Timer/Counter3 Input Capture Interrupt Enable + TIMSK3_OCIE3C = 0x8 // Timer/Counter3 Output Compare C Match Interrupt Enable + TIMSK3_OCIE3B = 0x4 // Timer/Counter3 Output Compare B Match Interrupt Enable + TIMSK3_OCIE3A = 0x2 // Timer/Counter3 Output Compare A Match Interrupt Enable + TIMSK3_TOIE3 = 0x1 // Timer/Counter3 Overflow Interrupt Enable + + // TIFR3: Timer/Counter3 Interrupt Flag register + TIFR3_ICF3 = 0x20 // Input Capture Flag 3 + TIFR3_OCF3C = 0x8 // Output Compare Flag 3C + TIFR3_OCF3B = 0x4 // Output Compare Flag 3B + TIFR3_OCF3A = 0x2 // Output Compare Flag 3A + TIFR3_TOV3 = 0x1 // Timer/Counter3 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_COM1C = 0xc // Compare Output Mode 1C, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + TCCR1C_FOC1C = 0x20 // Force Output Compare 1C + + // TCNT1L: Timer/Counter1 Bytes + + // TCNT1H: Timer/Counter1 Bytes + TCNT1_TCNT1 = 0xffff // Timer/Counter1 bits + + // OCR1AL: Timer/Counter1 Output Compare Register A Bytes + + // OCR1AH: Timer/Counter1 Output Compare Register A Bytes + OCR1A_OCR1A = 0xffff // Timer/Counter1 Output Compare A bits + + // OCR1BL: Timer/Counter1 Output Compare Register B Bytes + + // OCR1BH: Timer/Counter1 Output Compare Register B Bytes + OCR1B_OCR1B = 0xffff // Timer/Counter1 Output Compare B bits + + // OCR1CL: Timer/Counter1 Output Compare Register C Bytes + + // OCR1CH: Timer/Counter1 Output Compare Register C Bytes + OCR1C_OCR1C = 0xffff // Timer/Counter1 Output Compare C bits + + // ICR1L: Timer/Counter1 Input Capture Register Bytes + + // ICR1H: Timer/Counter1 Input Capture Register Bytes + ICR1_ICR1 = 0xffff // Timer/Counter1 Input Capture bits + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1C = 0x8 // Timer/Counter1 Output Compare C Match Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1C = 0x8 // Output Compare Flag 1C + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EICRB: External Interrupt Control Register B + EICRB_ISC7 = 0xc0 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC6 = 0x30 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC5 = 0xc // External Interrupt 7-4 Sense Control Bit + EICRB_ISC4 = 0x3 // External Interrupt 7-4 Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xff // External Interrupt Request 7 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xff // External Interrupt Flags + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Mask 0 + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF0 = 0x1 // Pin Change Interrupt Flag 0 + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE0 = 0x1 // Pin Change Interrupt Enable 0 +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCL: ADC Data Register Bytes + + // ADCH: ADC Data Register Bytes + ADC_ADC = 0x3ff // ADC Data Bits + + // DIDR0: Digital Input Disable Register 1 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable + + // DIDR2: Digital Input Disable Register 1 + DIDR2_ADC13D = 0x20 // ADC13 Digital input Disable + DIDR2_ADC12D = 0x10 // ADC12 Digital input Disable + DIDR2_ADC11D = 0x8 // ADC11 Digital input Disable + DIDR2_ADC10D = 0x4 // ADC10 Digital input Disable + DIDR2_ADC9D = 0x2 // ADC9 Digital input Disable + DIDR2_ADC8D = 0x1 // ADC8 Digital input Disable +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // RCCTRL: Oscillator Control Register + RCCTRL_RCFREQ = 0x1 + + // CLKPR + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // RAMPZ: Extended Z-pointer Register for ELPM/SPM + RAMPZ_RAMPZ = 0x3 // Extended Z-Pointer Value + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 + + // PRR1: Power Reduction Register1 + PRR1_PRUSB = 0x80 // Power Reduction USB + PRR1_PRTIM4 = 0x10 // Power Reduction Timer/Counter4 + PRR1_PRTIM3 = 0x8 // Power Reduction Timer/Counter3 + PRR1_PRUSART1 = 0x1 // Power Reduction USART1 + + // PRR0: Power Reduction Register0 + PRR0_PRTWI = 0x80 // Power Reduction TWI + PRR0_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR0_PRUSART0 = 0x2 // Power Reduction USART + PRR0_PRADC = 0x1 // Power Reduction ADC + + // CLKSTA + CLKSTA_RCON = 0x2 + CLKSTA_EXTON = 0x1 + + // CLKSEL1 + CLKSEL1_RCCKSEL = 0xf0 + CLKSEL1_EXCKSEL = 0xf + + // CLKSEL0 + CLKSEL0_RCSUT = 0xc0 + CLKSEL0_EXSUT = 0x30 + CLKSEL0_RCE = 0x8 + CLKSEL0_EXTE = 0x4 + CLKSEL0_CLKS = 0x1 +) + +// Bitfields for PLL: Phase Locked Loop +const ( + // PLLCSR: PLL Status and Control register + PLLCSR_PINDIV = 0x10 // PLL prescaler Bit 2 + PLLCSR_PLLE = 0x2 // PLL Enable Bit + PLLCSR_PLOCK = 0x1 // PLL Lock Status Bit + + // PLLFRQ: PLL Frequency Control Register + PLLFRQ_PINMUX = 0x80 + PLLFRQ_PLLUSB = 0x40 + PLLFRQ_PLLTM = 0x30 + PLLFRQ_PDIV = 0xf +) + +// Bitfields for USB_DEVICE: USB Device Registers +const ( + // UEINT + UEINT_EPINT = 0x7f // Endpoint interrupt bits + + // UEBCHX + UEBCHX_BYCT = 0x7 // Byte count bits + + // UEBCLX + UEBCLX_BYCT = 0xff // Byte count bits + + // UEDATX + UEDATX_DAT = 0xff + + // UEIENX + UEIENX_FLERRE = 0x80 + UEIENX_NAKINE = 0x40 + UEIENX_NAKOUTE = 0x10 + UEIENX_RXSTPE = 0x8 + UEIENX_RXOUTE = 0x4 + UEIENX_STALLEDE = 0x2 + UEIENX_TXINE = 0x1 + + // UESTA1X + UESTA1X_CTRLDIR = 0x4 + UESTA1X_CURRBK = 0x3 + + // UESTA0X + UESTA0X_CFGOK = 0x80 + UESTA0X_OVERFI = 0x40 + UESTA0X_UNDERFI = 0x20 + UESTA0X_DTSEQ = 0xc + UESTA0X_NBUSYBK = 0x3 + + // UECFG1X + UECFG1X_EPSIZE = 0x70 + UECFG1X_EPBK = 0xc + UECFG1X_ALLOC = 0x2 + + // UECFG0X + UECFG0X_EPTYPE = 0xc0 + UECFG0X_EPDIR = 0x1 + + // UECONX + UECONX_STALLRQ = 0x20 + UECONX_STALLRQC = 0x10 + UECONX_RSTDT = 0x8 + UECONX_EPEN = 0x1 + + // UERST + UERST_EPRST = 0x7f + + // UENUM + UENUM_UENUM = 0x7 + + // UEINTX + UEINTX_FIFOCON = 0x80 + UEINTX_NAKINI = 0x40 + UEINTX_RWAL = 0x20 + UEINTX_NAKOUTI = 0x10 + UEINTX_RXSTPI = 0x8 + UEINTX_RXOUTI = 0x4 + UEINTX_STALLEDI = 0x2 + UEINTX_TXINI = 0x1 + + // UDMFN + UDMFN_FNCERR = 0x10 + + // UDFNUML + + // UDFNUMH + UDFNUM_FNUM = 0x7ff // Frame number value + + // UDADDR + UDADDR_ADDEN = 0x80 + UDADDR_UADD = 0x7f + + // UDIEN + UDIEN_UPRSME = 0x40 + UDIEN_EORSME = 0x20 + UDIEN_WAKEUPE = 0x10 + UDIEN_EORSTE = 0x8 + UDIEN_SOFE = 0x4 + UDIEN_SUSPE = 0x1 + + // UDINT + UDINT_UPRSMI = 0x40 + UDINT_EORSMI = 0x20 + UDINT_WAKEUPI = 0x10 + UDINT_EORSTI = 0x8 + UDINT_SOFI = 0x4 + UDINT_SUSPI = 0x1 + + // UDCON + UDCON_LSM = 0x4 // USB low speed mode + UDCON_RSTCPU = 0x8 + UDCON_RMWKUP = 0x2 + UDCON_DETACH = 0x1 + + // USBCON: USB General Control Register + USBCON_USBE = 0x80 + USBCON_FRZCLK = 0x20 + USBCON_OTGPADE = 0x10 + USBCON_VBUSTE = 0x1 + + // USBINT + USBINT_VBUSTI = 0x1 + + // USBSTA + USBSTA_SPEED = 0x8 + USBSTA_VBUS = 0x1 + + // UHWCON + UHWCON_UVREGE = 0x1 +) diff --git a/src/device/avr/atmega16u4.ld b/src/device/avr/atmega16u4.ld new file mode 100644 index 00000000..dfe34898 --- /dev/null +++ b/src/device/avr/atmega16u4.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega16U4.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x4000; +__ram_size = 0x500; +__num_isrs = 43; diff --git a/src/device/avr/atmega2560.go b/src/device/avr/atmega2560.go new file mode 100644 index 00000000..b75106a2 --- /dev/null +++ b/src/device/avr/atmega2560.go @@ -0,0 +1,1090 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega2560.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega2560 + +// Device information for the ATmega2560. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega2560" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_INT3 = 4 // External Interrupt Request 3 + IRQ_INT4 = 5 // External Interrupt Request 4 + IRQ_INT5 = 6 // External Interrupt Request 5 + IRQ_INT6 = 7 // External Interrupt Request 6 + IRQ_INT7 = 8 // External Interrupt Request 7 + IRQ_PCINT0 = 9 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 10 // Pin Change Interrupt Request 1 + IRQ_PCINT2 = 11 // Pin Change Interrupt Request 2 + IRQ_WDT = 12 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 13 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 14 // Timer/Counter2 Compare Match B + IRQ_TIMER2_OVF = 15 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 16 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 17 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 18 // Timer/Counter1 Compare Match B + IRQ_TIMER1_COMPC = 19 // Timer/Counter1 Compare Match C + IRQ_TIMER1_OVF = 20 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 21 // Timer/Counter0 Compare Match A + IRQ_TIMER0_COMPB = 22 // Timer/Counter0 Compare Match B + IRQ_TIMER0_OVF = 23 // Timer/Counter0 Overflow + IRQ_SPI_STC = 24 // SPI Serial Transfer Complete + IRQ_USART0_RX = 25 // USART0, Rx Complete + IRQ_USART0_UDRE = 26 // USART0 Data register Empty + IRQ_USART0_TX = 27 // USART0, Tx Complete + IRQ_ANALOG_COMP = 28 // Analog Comparator + IRQ_ADC = 29 // ADC Conversion Complete + IRQ_EE_READY = 30 // EEPROM Ready + IRQ_TIMER3_CAPT = 31 // Timer/Counter3 Capture Event + IRQ_TIMER3_COMPA = 32 // Timer/Counter3 Compare Match A + IRQ_TIMER3_COMPB = 33 // Timer/Counter3 Compare Match B + IRQ_TIMER3_COMPC = 34 // Timer/Counter3 Compare Match C + IRQ_TIMER3_OVF = 35 // Timer/Counter3 Overflow + IRQ_USART1_RX = 36 // USART1, Rx Complete + IRQ_USART1_UDRE = 37 // USART1 Data register Empty + IRQ_USART1_TX = 38 // USART1, Tx Complete + IRQ_TWI = 39 // 2-wire Serial Interface + IRQ_SPM_READY = 40 // Store Program Memory Read + IRQ_TIMER4_CAPT = 41 // Timer/Counter4 Capture Event + IRQ_TIMER4_COMPA = 42 // Timer/Counter4 Compare Match A + IRQ_TIMER4_COMPB = 43 // Timer/Counter4 Compare Match B + IRQ_TIMER4_COMPC = 44 // Timer/Counter4 Compare Match C + IRQ_TIMER4_OVF = 45 // Timer/Counter4 Overflow + IRQ_TIMER5_CAPT = 46 // Timer/Counter5 Capture Event + IRQ_TIMER5_COMPA = 47 // Timer/Counter5 Compare Match A + IRQ_TIMER5_COMPB = 48 // Timer/Counter5 Compare Match B + IRQ_TIMER5_COMPC = 49 // Timer/Counter5 Compare Match C + IRQ_TIMER5_OVF = 50 // Timer/Counter5 Overflow + IRQ_USART2_RX = 51 // USART2, Rx Complete + IRQ_USART2_UDRE = 52 // USART2 Data register Empty + IRQ_USART2_TX = 53 // USART2, Tx Complete + IRQ_USART3_RX = 54 // USART3, Rx Complete + IRQ_USART3_UDRE = 55 // USART3 Data register Empty + IRQ_USART3_TX = 56 // USART3, Tx Complete + IRQ_max = 56 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + UDR1 __reg + UCSR1A __reg + UCSR1B __reg + UCSR1C __reg + UBRR1L __reg + UBRR1H __reg + UDR2 __reg + UCSR2A __reg + UCSR2B __reg + UCSR2C __reg + UBRR2L __reg + UBRR2H __reg + UDR3 __reg + UCSR3A __reg + UCSR3B __reg + UCSR3C __reg + UBRR3L __reg + UBRR3H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + UDR1: 0xce, // USART I/O Data Register + UCSR1A: 0xc8, // USART Control and Status Register A + UCSR1B: 0xc9, // USART Control and Status Register B + UCSR1C: 0xca, // USART Control and Status Register C + UBRR1L: 0xcc, // USART Baud Rate Register Bytes + UBRR1H: 0xcc, // USART Baud Rate Register Bytes + UDR2: 0xd6, // USART I/O Data Register + UCSR2A: 0xd0, // USART Control and Status Register A + UCSR2B: 0xd1, // USART Control and Status Register B + UCSR2C: 0xd2, // USART Control and Status Register C + UBRR2L: 0xd4, // USART Baud Rate Register Bytes + UBRR2H: 0xd4, // USART Baud Rate Register Bytes + UDR3: 0x136, // USART I/O Data Register + UCSR3A: 0x130, // USART Control and Status Register A + UCSR3B: 0x131, // USART Control and Status Register B + UCSR3C: 0x132, // USART Control and Status Register C + UBRR3L: 0x134, // USART Baud Rate Register Bytes + UBRR3H: 0x134, // USART Baud Rate Register Bytes + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + PORTH __reg + DDRH __reg + PINH __reg + PORTJ __reg + DDRJ __reg + PINJ __reg + PORTK __reg + DDRK __reg + PINK __reg + PORTL __reg + DDRL __reg + PINL __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + PORTG: 0x34, // Data Register, Port G + DDRG: 0x33, // Data Direction Register, Port G + PING: 0x32, // Input Pins, Port G + PORTH: 0x102, // PORT H Data Register + DDRH: 0x101, // PORT H Data Direction Register + PINH: 0x100, // PORT H Input Pins + PORTJ: 0x105, // PORT J Data Register + DDRJ: 0x104, // PORT J Data Direction Register + PINJ: 0x103, // PORT J Input Pins + PORTK: 0x108, // PORT K Data Register + DDRK: 0x107, // PORT K Data Direction Register + PINK: 0x106, // PORT K Input Pins + PORTL: 0x10b, // PORT L Data Register + DDRL: 0x10a, // PORT L Data Direction Register + PINL: 0x109, // PORT L Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Low Bytes + EEARH: 0x41, // EEPROM Address Register Low Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR5A __reg + TCCR5B __reg + TCCR5C __reg + TCNT5L __reg + TCNT5H __reg + OCR5AL __reg + OCR5AH __reg + OCR5BL __reg + OCR5BH __reg + OCR5CL __reg + OCR5CH __reg + ICR5L __reg + ICR5H __reg + TIMSK5 __reg + TIFR5 __reg + TCCR4A __reg + TCCR4B __reg + TCCR4C __reg + TCNT4L __reg + TCNT4H __reg + OCR4AL __reg + OCR4AH __reg + OCR4BL __reg + OCR4BH __reg + OCR4CL __reg + OCR4CH __reg + ICR4L __reg + ICR4H __reg + TIMSK4 __reg + TIFR4 __reg + TCCR3A __reg + TCCR3B __reg + TCCR3C __reg + TCNT3L __reg + TCNT3H __reg + OCR3AL __reg + OCR3AH __reg + OCR3BL __reg + OCR3BH __reg + OCR3CL __reg + OCR3CH __reg + ICR3L __reg + ICR3H __reg + TIMSK3 __reg + TIFR3 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + OCR1CL __reg + OCR1CH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR5A: 0x120, // Timer/Counter5 Control Register A + TCCR5B: 0x121, // Timer/Counter5 Control Register B + TCCR5C: 0x122, // Timer/Counter 5 Control Register C + TCNT5L: 0x124, // Timer/Counter5 Bytes + TCNT5H: 0x124, // Timer/Counter5 Bytes + OCR5AL: 0x128, // Timer/Counter5 Output Compare Register A Bytes + OCR5AH: 0x128, // Timer/Counter5 Output Compare Register A Bytes + OCR5BL: 0x12a, // Timer/Counter5 Output Compare Register B Bytes + OCR5BH: 0x12a, // Timer/Counter5 Output Compare Register B Bytes + OCR5CL: 0x12c, // Timer/Counter5 Output Compare Register B Bytes + OCR5CH: 0x12c, // Timer/Counter5 Output Compare Register B Bytes + ICR5L: 0x126, // Timer/Counter5 Input Capture Register Bytes + ICR5H: 0x126, // Timer/Counter5 Input Capture Register Bytes + TIMSK5: 0x73, // Timer/Counter5 Interrupt Mask Register + TIFR5: 0x3a, // Timer/Counter5 Interrupt Flag register + TCCR4A: 0xa0, // Timer/Counter4 Control Register A + TCCR4B: 0xa1, // Timer/Counter4 Control Register B + TCCR4C: 0xa2, // Timer/Counter 4 Control Register C + TCNT4L: 0xa4, // Timer/Counter4 Bytes + TCNT4H: 0xa4, // Timer/Counter4 Bytes + OCR4AL: 0xa8, // Timer/Counter4 Output Compare Register A Bytes + OCR4AH: 0xa8, // Timer/Counter4 Output Compare Register A Bytes + OCR4BL: 0xaa, // Timer/Counter4 Output Compare Register B Bytes + OCR4BH: 0xaa, // Timer/Counter4 Output Compare Register B Bytes + OCR4CL: 0xac, // Timer/Counter4 Output Compare Register B Bytes + OCR4CH: 0xac, // Timer/Counter4 Output Compare Register B Bytes + ICR4L: 0xa6, // Timer/Counter4 Input Capture Register Bytes + ICR4H: 0xa6, // Timer/Counter4 Input Capture Register Bytes + TIMSK4: 0x72, // Timer/Counter4 Interrupt Mask Register + TIFR4: 0x39, // Timer/Counter4 Interrupt Flag register + TCCR3A: 0x90, // Timer/Counter3 Control Register A + TCCR3B: 0x91, // Timer/Counter3 Control Register B + TCCR3C: 0x92, // Timer/Counter 3 Control Register C + TCNT3L: 0x94, // Timer/Counter3 Bytes + TCNT3H: 0x94, // Timer/Counter3 Bytes + OCR3AL: 0x98, // Timer/Counter3 Output Compare Register A Bytes + OCR3AH: 0x98, // Timer/Counter3 Output Compare Register A Bytes + OCR3BL: 0x9a, // Timer/Counter3 Output Compare Register B Bytes + OCR3BH: 0x9a, // Timer/Counter3 Output Compare Register B Bytes + OCR3CL: 0x9c, // Timer/Counter3 Output Compare Register B Bytes + OCR3CH: 0x9c, // Timer/Counter3 Output Compare Register B Bytes + ICR3L: 0x96, // Timer/Counter3 Input Capture Register Bytes + ICR3H: 0x96, // Timer/Counter3 Input Capture Register Bytes + TIMSK3: 0x71, // Timer/Counter3 Interrupt Mask Register + TIFR3: 0x38, // Timer/Counter3 Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1CL: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + OCR1CH: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EICRB __reg + EIMSK __reg + EIFR __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + PCICR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EICRB: 0x6a, // External Interrupt Control Register B + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + XMCRA __reg + XMCRB __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + EIND __reg + RAMPZ __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PRR1 __reg + PRR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + XMCRA: 0x74, // External Memory Control Register A + XMCRB: 0x75, // External Memory Control Register B + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, + SMCR: 0x53, // Sleep Mode Control Register + EIND: 0x5c, // Extended Indirect Register + RAMPZ: 0x5b, // RAM Page Z Select Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PRR1: 0x65, // Power Reduction Register1 + PRR0: 0x64, // Power Reduction Register0 + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + DIDR2 __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // The ADC Control and Status register A + DIDR2: 0x7d, // Digital Input Disable Register + DIDR0: 0x7e, // Digital Input Disable Register + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0xc0 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity + + // UCSR1A: USART Control and Status Register A + UCSR1A_RXC1 = 0x80 // USART Receive Complete + UCSR1A_TXC1 = 0x40 // USART Transmitt Complete + UCSR1A_UDRE1 = 0x20 // USART Data Register Empty + UCSR1A_FE1 = 0x10 // Framing Error + UCSR1A_DOR1 = 0x8 // Data overRun + UCSR1A_UPE1 = 0x4 // Parity Error + UCSR1A_U2X1 = 0x2 // Double the USART transmission speed + UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode + + // UCSR1B: USART Control and Status Register B + UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable + UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable + UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable + UCSR1B_RXEN1 = 0x10 // Receiver Enable + UCSR1B_TXEN1 = 0x8 // Transmitter Enable + UCSR1B_UCSZ12 = 0x4 // Character Size + UCSR1B_RXB81 = 0x2 // Receive Data Bit 8 + UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8 + + // UCSR1C: USART Control and Status Register C + UCSR1C_UMSEL1 = 0xc0 // USART Mode Select + UCSR1C_UPM1 = 0x30 // Parity Mode Bits + UCSR1C_USBS1 = 0x8 // Stop Bit Select + UCSR1C_UCSZ1 = 0x6 // Character Size + UCSR1C_UCPOL1 = 0x1 // Clock Polarity + + // UCSR2A: USART Control and Status Register A + UCSR2A_RXC2 = 0x80 // USART Receive Complete + UCSR2A_TXC2 = 0x40 // USART Transmitt Complete + UCSR2A_UDRE2 = 0x20 // USART Data Register Empty + UCSR2A_FE2 = 0x10 // Framing Error + UCSR2A_DOR2 = 0x8 // Data overRun + UCSR2A_UPE2 = 0x4 // Parity Error + UCSR2A_U2X2 = 0x2 // Double the USART transmission speed + UCSR2A_MPCM2 = 0x1 // Multi-processor Communication Mode + + // UCSR2B: USART Control and Status Register B + UCSR2B_RXCIE2 = 0x80 // RX Complete Interrupt Enable + UCSR2B_TXCIE2 = 0x40 // TX Complete Interrupt Enable + UCSR2B_UDRIE2 = 0x20 // USART Data register Empty Interrupt Enable + UCSR2B_RXEN2 = 0x10 // Receiver Enable + UCSR2B_TXEN2 = 0x8 // Transmitter Enable + UCSR2B_UCSZ22 = 0x4 // Character Size + UCSR2B_RXB82 = 0x2 // Receive Data Bit 8 + UCSR2B_TXB82 = 0x1 // Transmit Data Bit 8 + + // UCSR2C: USART Control and Status Register C + UCSR2C_UMSEL2 = 0xc0 // USART Mode Select + UCSR2C_UPM2 = 0x30 // Parity Mode Bits + UCSR2C_USBS2 = 0x8 // Stop Bit Select + UCSR2C_UCSZ2 = 0x6 // Character Size + UCSR2C_UCPOL2 = 0x1 // Clock Polarity + + // UCSR3A: USART Control and Status Register A + UCSR3A_RXC3 = 0x80 // USART Receive Complete + UCSR3A_TXC3 = 0x40 // USART Transmitt Complete + UCSR3A_UDRE3 = 0x20 // USART Data Register Empty + UCSR3A_FE3 = 0x10 // Framing Error + UCSR3A_DOR3 = 0x8 // Data overRun + UCSR3A_UPE3 = 0x4 // Parity Error + UCSR3A_U2X3 = 0x2 // Double the USART transmission speed + UCSR3A_MPCM3 = 0x1 // Multi-processor Communication Mode + + // UCSR3B: USART Control and Status Register B + UCSR3B_RXCIE3 = 0x80 // RX Complete Interrupt Enable + UCSR3B_TXCIE3 = 0x40 // TX Complete Interrupt Enable + UCSR3B_UDRIE3 = 0x20 // USART Data register Empty Interrupt Enable + UCSR3B_RXEN3 = 0x10 // Receiver Enable + UCSR3B_TXEN3 = 0x8 // Transmitter Enable + UCSR3B_UCSZ32 = 0x4 // Character Size + UCSR3B_RXB83 = 0x2 // Receive Data Bit 8 + UCSR3B_TXB83 = 0x1 // Transmit Data Bit 8 + + // UCSR3C: USART Control and Status Register C + UCSR3C_UMSEL3 = 0xc0 // USART Mode Select + UCSR3C_UPM3 = 0x30 // Parity Mode Bits + UCSR3C_USBS3 = 0x8 // Stop Bit Select + UCSR3C_UCSZ3 = 0x6 // Character Size + UCSR3C_UCPOL3 = 0x1 // Clock Polarity +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2B = 0x4 // Output Compare Flag 2B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Output Mode bits + TCCR2A_COM2B = 0x30 // Compare Output Mode bits + TCCR2A_WGM2 = 0x3 // Waveform Genration Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy + ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR5A: Timer/Counter5 Control Register A + TCCR5A_COM5A = 0xc0 // Compare Output Mode 1A, bits + TCCR5A_COM5B = 0x30 // Compare Output Mode 5B, bits + TCCR5A_COM5C = 0xc // Compare Output Mode 5C, bits + TCCR5A_WGM5 = 0x3 // Waveform Generation Mode + + // TCCR5B: Timer/Counter5 Control Register B + TCCR5B_ICNC5 = 0x80 // Input Capture 5 Noise Canceler + TCCR5B_ICES5 = 0x40 // Input Capture 5 Edge Select + TCCR5B_WGM5 = 0x18 // Waveform Generation Mode + TCCR5B_CS5 = 0x7 // Prescaler source of Timer/Counter 5 + + // TCCR5C: Timer/Counter 5 Control Register C + TCCR5C_FOC5A = 0x80 // Force Output Compare 5A + TCCR5C_FOC5B = 0x40 // Force Output Compare 5B + TCCR5C_FOC5C = 0x20 // Force Output Compare 5C + + // TIMSK5: Timer/Counter5 Interrupt Mask Register + TIMSK5_ICIE5 = 0x20 // Timer/Counter5 Input Capture Interrupt Enable + TIMSK5_OCIE5C = 0x8 // Timer/Counter5 Output Compare C Match Interrupt Enable + TIMSK5_OCIE5B = 0x4 // Timer/Counter5 Output Compare B Match Interrupt Enable + TIMSK5_OCIE5A = 0x2 // Timer/Counter5 Output Compare A Match Interrupt Enable + TIMSK5_TOIE5 = 0x1 // Timer/Counter5 Overflow Interrupt Enable + + // TIFR5: Timer/Counter5 Interrupt Flag register + TIFR5_ICF5 = 0x20 // Input Capture Flag 5 + TIFR5_OCF5C = 0x8 // Output Compare Flag 5C + TIFR5_OCF5B = 0x4 // Output Compare Flag 5B + TIFR5_OCF5A = 0x2 // Output Compare Flag 5A + TIFR5_TOV5 = 0x1 // Timer/Counter5 Overflow Flag + + // TCCR4A: Timer/Counter4 Control Register A + TCCR4A_COM4A = 0xc0 // Compare Output Mode 1A, bits + TCCR4A_COM4B = 0x30 // Compare Output Mode 4B, bits + TCCR4A_COM4C = 0xc // Compare Output Mode 4C, bits + TCCR4A_WGM4 = 0x3 // Waveform Generation Mode + + // TCCR4B: Timer/Counter4 Control Register B + TCCR4B_ICNC4 = 0x80 // Input Capture 4 Noise Canceler + TCCR4B_ICES4 = 0x40 // Input Capture 4 Edge Select + TCCR4B_WGM4 = 0x18 // Waveform Generation Mode + TCCR4B_CS4 = 0x7 // Prescaler source of Timer/Counter 4 + + // TCCR4C: Timer/Counter 4 Control Register C + TCCR4C_FOC4A = 0x80 // Force Output Compare 4A + TCCR4C_FOC4B = 0x40 // Force Output Compare 4B + TCCR4C_FOC4C = 0x20 // Force Output Compare 4C + + // TIMSK4: Timer/Counter4 Interrupt Mask Register + TIMSK4_ICIE4 = 0x20 // Timer/Counter4 Input Capture Interrupt Enable + TIMSK4_OCIE4C = 0x8 // Timer/Counter4 Output Compare C Match Interrupt Enable + TIMSK4_OCIE4B = 0x4 // Timer/Counter4 Output Compare B Match Interrupt Enable + TIMSK4_OCIE4A = 0x2 // Timer/Counter4 Output Compare A Match Interrupt Enable + TIMSK4_TOIE4 = 0x1 // Timer/Counter4 Overflow Interrupt Enable + + // TIFR4: Timer/Counter4 Interrupt Flag register + TIFR4_ICF4 = 0x20 // Input Capture Flag 4 + TIFR4_OCF4C = 0x8 // Output Compare Flag 4C + TIFR4_OCF4B = 0x4 // Output Compare Flag 4B + TIFR4_OCF4A = 0x2 // Output Compare Flag 4A + TIFR4_TOV4 = 0x1 // Timer/Counter4 Overflow Flag + + // TCCR3A: Timer/Counter3 Control Register A + TCCR3A_COM3A = 0xc0 // Compare Output Mode 1A, bits + TCCR3A_COM3B = 0x30 // Compare Output Mode 3B, bits + TCCR3A_COM3C = 0xc // Compare Output Mode 3C, bits + TCCR3A_WGM3 = 0x3 // Waveform Generation Mode + + // TCCR3B: Timer/Counter3 Control Register B + TCCR3B_ICNC3 = 0x80 // Input Capture 3 Noise Canceler + TCCR3B_ICES3 = 0x40 // Input Capture 3 Edge Select + TCCR3B_WGM3 = 0x18 // Waveform Generation Mode + TCCR3B_CS3 = 0x7 // Prescaler source of Timer/Counter 3 + + // TCCR3C: Timer/Counter 3 Control Register C + TCCR3C_FOC3A = 0x80 // Force Output Compare 3A + TCCR3C_FOC3B = 0x40 // Force Output Compare 3B + TCCR3C_FOC3C = 0x20 // Force Output Compare 3C + + // TIMSK3: Timer/Counter3 Interrupt Mask Register + TIMSK3_ICIE3 = 0x20 // Timer/Counter3 Input Capture Interrupt Enable + TIMSK3_OCIE3C = 0x8 // Timer/Counter3 Output Compare C Match Interrupt Enable + TIMSK3_OCIE3B = 0x4 // Timer/Counter3 Output Compare B Match Interrupt Enable + TIMSK3_OCIE3A = 0x2 // Timer/Counter3 Output Compare A Match Interrupt Enable + TIMSK3_TOIE3 = 0x1 // Timer/Counter3 Overflow Interrupt Enable + + // TIFR3: Timer/Counter3 Interrupt Flag register + TIFR3_ICF3 = 0x20 // Input Capture Flag 3 + TIFR3_OCF3C = 0x8 // Output Compare Flag 3C + TIFR3_OCF3B = 0x4 // Output Compare Flag 3B + TIFR3_OCF3A = 0x2 // Output Compare Flag 3A + TIFR3_TOV3 = 0x1 // Timer/Counter3 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_COM1C = 0xc // Compare Output Mode 1C, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + TCCR1C_FOC1C = 0x20 // Force Output Compare 1C + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1C = 0x8 // Timer/Counter1 Output Compare C Match Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1C = 0x8 // Output Compare Flag 1C + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EICRB: External Interrupt Control Register B + EICRB_ISC7 = 0xc0 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC6 = 0x30 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC5 = 0xc // External Interrupt 7-4 Sense Control Bit + EICRB_ISC4 = 0x3 // External Interrupt 7-4 Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xff // External Interrupt Request 7 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xff // External Interrupt Flags + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Mask interrupt + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Mask interrupt + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Mask interrupt + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0x7 // Pin Change Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0x7 // Pin Change Interrupt Enables +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // XMCRA: External Memory Control Register A + XMCRA_SRE = 0x80 // External SRAM Enable + XMCRA_SRL = 0x70 // Wait state page limit + XMCRA_SRW1 = 0xc // Wait state select bit upper page + XMCRA_SRW0 = 0x3 // Wait state select bit lower page + + // XMCRB: External Memory Control Register B + XMCRB_XMBK = 0x80 // External Memory Bus Keeper Enable + XMCRB_XMM = 0x7 // External Memory High Mask + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 + + // PRR1: Power Reduction Register1 + PRR1_PRTIM5 = 0x20 // Power Reduction Timer/Counter5 + PRR1_PRTIM4 = 0x10 // Power Reduction Timer/Counter4 + PRR1_PRTIM3 = 0x8 // Power Reduction Timer/Counter3 + PRR1_PRUSART3 = 0x4 // Power Reduction USART3 + PRR1_PRUSART2 = 0x2 // Power Reduction USART2 + PRR1_PRUSART1 = 0x1 // Power Reduction USART1 + + // PRR0: Power Reduction Register0 + PRR0_PRTWI = 0x80 // Power Reduction TWI + PRR0_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR0_PRUSART0 = 0x2 // Power Reduction USART0 + PRR0_PRADC = 0x1 // Power Reduction ADC +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR2: Digital Input Disable Register + DIDR2_ADC15D = 0x80 + DIDR2_ADC14D = 0x40 + DIDR2_ADC13D = 0x20 + DIDR2_ADC12D = 0x10 + DIDR2_ADC11D = 0x8 + DIDR2_ADC10D = 0x4 + DIDR2_ADC9D = 0x2 + DIDR2_ADC8D = 0x1 + + // DIDR0: Digital Input Disable Register + DIDR0_ADC7D = 0x80 + DIDR0_ADC6D = 0x40 + DIDR0_ADC5D = 0x20 + DIDR0_ADC4D = 0x10 + DIDR0_ADC3D = 0x8 + DIDR0_ADC2D = 0x4 + DIDR0_ADC1D = 0x2 + DIDR0_ADC0D = 0x1 +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) diff --git a/src/device/avr/atmega2560.ld b/src/device/avr/atmega2560.ld new file mode 100644 index 00000000..b0136af2 --- /dev/null +++ b/src/device/avr/atmega2560.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega2560.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x40000; +__ram_size = 0x2000; +__num_isrs = 57; diff --git a/src/device/avr/atmega2561.go b/src/device/avr/atmega2561.go new file mode 100644 index 00000000..2904a7c6 --- /dev/null +++ b/src/device/avr/atmega2561.go @@ -0,0 +1,988 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega2561.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega2561 + +// Device information for the ATmega2561. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega2561" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_INT3 = 4 // External Interrupt Request 3 + IRQ_INT4 = 5 // External Interrupt Request 4 + IRQ_INT5 = 6 // External Interrupt Request 5 + IRQ_INT6 = 7 // External Interrupt Request 6 + IRQ_INT7 = 8 // External Interrupt Request 7 + IRQ_PCINT0 = 9 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 10 // Pin Change Interrupt Request 1 + IRQ_PCINT2 = 11 // Pin Change Interrupt Request 2 + IRQ_WDT = 12 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 13 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 14 // Timer/Counter2 Compare Match B + IRQ_TIMER2_OVF = 15 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 16 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 17 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 18 // Timer/Counter1 Compare Match B + IRQ_TIMER1_COMPC = 19 // Timer/Counter1 Compare Match C + IRQ_TIMER1_OVF = 20 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 21 // Timer/Counter0 Compare Match A + IRQ_TIMER0_COMPB = 22 // Timer/Counter0 Compare Match B + IRQ_TIMER0_OVF = 23 // Timer/Counter0 Overflow + IRQ_SPI_STC = 24 // SPI Serial Transfer Complete + IRQ_USART0_RX = 25 // USART0, Rx Complete + IRQ_USART0_UDRE = 26 // USART0 Data register Empty + IRQ_USART0_TX = 27 // USART0, Tx Complete + IRQ_ANALOG_COMP = 28 // Analog Comparator + IRQ_ADC = 29 // ADC Conversion Complete + IRQ_EE_READY = 30 // EEPROM Ready + IRQ_TIMER3_CAPT = 31 // Timer/Counter3 Capture Event + IRQ_TIMER3_COMPA = 32 // Timer/Counter3 Compare Match A + IRQ_TIMER3_COMPB = 33 // Timer/Counter3 Compare Match B + IRQ_TIMER3_COMPC = 34 // Timer/Counter3 Compare Match C + IRQ_TIMER3_OVF = 35 // Timer/Counter3 Overflow + IRQ_USART1_RX = 36 // USART1, Rx Complete + IRQ_USART1_UDRE = 37 // USART1 Data register Empty + IRQ_USART1_TX = 38 // USART1, Tx Complete + IRQ_TWI = 39 // 2-wire Serial Interface + IRQ_SPM_READY = 40 // Store Program Memory Read + IRQ_TIMER4_CAPT = 41 // Timer/Counter4 Capture Event + IRQ_TIMER4_COMPA = 42 // Timer/Counter4 Compare Match A + IRQ_TIMER4_COMPB = 43 // Timer/Counter4 Compare Match B + IRQ_TIMER4_COMPC = 44 // Timer/Counter4 Compare Match C + IRQ_TIMER4_OVF = 45 // Timer/Counter4 Overflow + IRQ_TIMER5_CAPT = 46 // Timer/Counter5 Capture Event + IRQ_TIMER5_COMPA = 47 // Timer/Counter5 Compare Match A + IRQ_TIMER5_COMPB = 48 // Timer/Counter5 Compare Match B + IRQ_TIMER5_COMPC = 49 // Timer/Counter5 Compare Match C + IRQ_TIMER5_OVF = 50 // Timer/Counter5 Overflow + IRQ_USART2_RX = 51 // USART2, Rx Complete + IRQ_USART2_UDRE = 52 // USART2 Data register Empty + IRQ_USART2_TX = 53 // USART2, Tx Complete + IRQ_USART3_RX = 54 // USART3, Rx Complete + IRQ_USART3_UDRE = 55 // USART3 Data register Empty + IRQ_USART3_TX = 56 // USART3, Tx Complete + IRQ_max = 56 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + UDR1 __reg + UCSR1A __reg + UCSR1B __reg + UCSR1C __reg + UBRR1L __reg + UBRR1H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + UDR1: 0xce, // USART I/O Data Register + UCSR1A: 0xc8, // USART Control and Status Register A + UCSR1B: 0xc9, // USART Control and Status Register B + UCSR1C: 0xca, // USART Control and Status Register C + UBRR1L: 0xcc, // USART Baud Rate Register Bytes + UBRR1H: 0xcc, // USART Baud Rate Register Bytes + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + PORTG: 0x34, // Data Register, Port G + DDRG: 0x33, // Data Direction Register, Port G + PING: 0x32, // Input Pins, Port G + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Low Bytes + EEARH: 0x41, // EEPROM Address Register Low Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR5A __reg + TCCR5B __reg + TCCR5C __reg + TCNT5L __reg + TCNT5H __reg + OCR5AL __reg + OCR5AH __reg + OCR5BL __reg + OCR5BH __reg + OCR5CL __reg + OCR5CH __reg + ICR5L __reg + ICR5H __reg + TIMSK5 __reg + TIFR5 __reg + TCCR4A __reg + TCCR4B __reg + TCCR4C __reg + TCNT4L __reg + TCNT4H __reg + OCR4AL __reg + OCR4AH __reg + OCR4BL __reg + OCR4BH __reg + OCR4CL __reg + OCR4CH __reg + ICR4L __reg + ICR4H __reg + TIMSK4 __reg + TIFR4 __reg + TCCR3A __reg + TCCR3B __reg + TCCR3C __reg + TCNT3L __reg + TCNT3H __reg + OCR3AL __reg + OCR3AH __reg + OCR3BL __reg + OCR3BH __reg + OCR3CL __reg + OCR3CH __reg + ICR3L __reg + ICR3H __reg + TIMSK3 __reg + TIFR3 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + OCR1CL __reg + OCR1CH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR5A: 0x120, // Timer/Counter5 Control Register A + TCCR5B: 0x121, // Timer/Counter5 Control Register B + TCCR5C: 0x122, // Timer/Counter 5 Control Register C + TCNT5L: 0x124, // Timer/Counter5 Bytes + TCNT5H: 0x124, // Timer/Counter5 Bytes + OCR5AL: 0x128, // Timer/Counter5 Output Compare Register A Bytes + OCR5AH: 0x128, // Timer/Counter5 Output Compare Register A Bytes + OCR5BL: 0x12a, // Timer/Counter5 Output Compare Register B Bytes + OCR5BH: 0x12a, // Timer/Counter5 Output Compare Register B Bytes + OCR5CL: 0x12c, // Timer/Counter5 Output Compare Register B Bytes + OCR5CH: 0x12c, // Timer/Counter5 Output Compare Register B Bytes + ICR5L: 0x126, // Timer/Counter5 Input Capture Register Bytes + ICR5H: 0x126, // Timer/Counter5 Input Capture Register Bytes + TIMSK5: 0x73, // Timer/Counter5 Interrupt Mask Register + TIFR5: 0x3a, // Timer/Counter5 Interrupt Flag register + TCCR4A: 0xa0, // Timer/Counter4 Control Register A + TCCR4B: 0xa1, // Timer/Counter4 Control Register B + TCCR4C: 0xa2, // Timer/Counter 4 Control Register C + TCNT4L: 0xa4, // Timer/Counter4 Bytes + TCNT4H: 0xa4, // Timer/Counter4 Bytes + OCR4AL: 0xa8, // Timer/Counter4 Output Compare Register A Bytes + OCR4AH: 0xa8, // Timer/Counter4 Output Compare Register A Bytes + OCR4BL: 0xaa, // Timer/Counter4 Output Compare Register B Bytes + OCR4BH: 0xaa, // Timer/Counter4 Output Compare Register B Bytes + OCR4CL: 0xac, // Timer/Counter4 Output Compare Register B Bytes + OCR4CH: 0xac, // Timer/Counter4 Output Compare Register B Bytes + ICR4L: 0xa6, // Timer/Counter4 Input Capture Register Bytes + ICR4H: 0xa6, // Timer/Counter4 Input Capture Register Bytes + TIMSK4: 0x72, // Timer/Counter4 Interrupt Mask Register + TIFR4: 0x39, // Timer/Counter4 Interrupt Flag register + TCCR3A: 0x90, // Timer/Counter3 Control Register A + TCCR3B: 0x91, // Timer/Counter3 Control Register B + TCCR3C: 0x92, // Timer/Counter 3 Control Register C + TCNT3L: 0x94, // Timer/Counter3 Bytes + TCNT3H: 0x94, // Timer/Counter3 Bytes + OCR3AL: 0x98, // Timer/Counter3 Output Compare Register A Bytes + OCR3AH: 0x98, // Timer/Counter3 Output Compare Register A Bytes + OCR3BL: 0x9a, // Timer/Counter3 Output Compare Register B Bytes + OCR3BH: 0x9a, // Timer/Counter3 Output Compare Register B Bytes + OCR3CL: 0x9c, // Timer/Counter3 Output Compare Register B Bytes + OCR3CH: 0x9c, // Timer/Counter3 Output Compare Register B Bytes + ICR3L: 0x96, // Timer/Counter3 Input Capture Register Bytes + ICR3H: 0x96, // Timer/Counter3 Input Capture Register Bytes + TIMSK3: 0x71, // Timer/Counter3 Interrupt Mask Register + TIFR3: 0x38, // Timer/Counter3 Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1CL: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + OCR1CH: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EICRB __reg + EIMSK __reg + EIFR __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + PCICR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EICRB: 0x6a, // External Interrupt Control Register B + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + XMCRA __reg + XMCRB __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + EIND __reg + RAMPZ __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PRR1 __reg + PRR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + XMCRA: 0x74, // External Memory Control Register A + XMCRB: 0x75, // External Memory Control Register B + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, + SMCR: 0x53, // Sleep Mode Control Register + EIND: 0x5c, // Extended Indirect Register + RAMPZ: 0x5b, // RAM Page Z Select Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PRR1: 0x65, // Power Reduction Register1 + PRR0: 0x64, // Power Reduction Register0 + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + DIDR2 __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // The ADC Control and Status register A + DIDR2: 0x7d, // Digital Input Disable Register + DIDR0: 0x7e, // Digital Input Disable Register + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0xc0 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity + + // UCSR1A: USART Control and Status Register A + UCSR1A_RXC1 = 0x80 // USART Receive Complete + UCSR1A_TXC1 = 0x40 // USART Transmitt Complete + UCSR1A_UDRE1 = 0x20 // USART Data Register Empty + UCSR1A_FE1 = 0x10 // Framing Error + UCSR1A_DOR1 = 0x8 // Data overRun + UCSR1A_UPE1 = 0x4 // Parity Error + UCSR1A_U2X1 = 0x2 // Double the USART transmission speed + UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode + + // UCSR1B: USART Control and Status Register B + UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable + UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable + UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable + UCSR1B_RXEN1 = 0x10 // Receiver Enable + UCSR1B_TXEN1 = 0x8 // Transmitter Enable + UCSR1B_UCSZ12 = 0x4 // Character Size + UCSR1B_RXB81 = 0x2 // Receive Data Bit 8 + UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8 + + // UCSR1C: USART Control and Status Register C + UCSR1C_UMSEL1 = 0xc0 // USART Mode Select + UCSR1C_UPM1 = 0x30 // Parity Mode Bits + UCSR1C_USBS1 = 0x8 // Stop Bit Select + UCSR1C_UCSZ1 = 0x6 // Character Size + UCSR1C_UCPOL1 = 0x1 // Clock Polarity +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2B = 0x4 // Output Compare Flag 2B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Output Mode bits + TCCR2A_COM2B = 0x30 // Compare Output Mode bits + TCCR2A_WGM2 = 0x3 // Waveform Genration Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy + ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR5A: Timer/Counter5 Control Register A + TCCR5A_COM5A = 0xc0 // Compare Output Mode 1A, bits + TCCR5A_COM5B = 0x30 // Compare Output Mode 5B, bits + TCCR5A_COM5C = 0xc // Compare Output Mode 5C, bits + TCCR5A_WGM5 = 0x3 // Waveform Generation Mode + + // TCCR5B: Timer/Counter5 Control Register B + TCCR5B_ICNC5 = 0x80 // Input Capture 5 Noise Canceler + TCCR5B_ICES5 = 0x40 // Input Capture 5 Edge Select + TCCR5B_WGM5 = 0x18 // Waveform Generation Mode + TCCR5B_CS5 = 0x7 // Prescaler source of Timer/Counter 5 + + // TCCR5C: Timer/Counter 5 Control Register C + TCCR5C_FOC5A = 0x80 // Force Output Compare 5A + TCCR5C_FOC5B = 0x40 // Force Output Compare 5B + TCCR5C_FOC5C = 0x20 // Force Output Compare 5C + + // TIMSK5: Timer/Counter5 Interrupt Mask Register + TIMSK5_ICIE5 = 0x20 // Timer/Counter5 Input Capture Interrupt Enable + TIMSK5_OCIE5C = 0x8 // Timer/Counter5 Output Compare C Match Interrupt Enable + TIMSK5_OCIE5B = 0x4 // Timer/Counter5 Output Compare B Match Interrupt Enable + TIMSK5_OCIE5A = 0x2 // Timer/Counter5 Output Compare A Match Interrupt Enable + TIMSK5_TOIE5 = 0x1 // Timer/Counter5 Overflow Interrupt Enable + + // TIFR5: Timer/Counter5 Interrupt Flag register + TIFR5_ICF5 = 0x20 // Input Capture Flag 5 + TIFR5_OCF5C = 0x8 // Output Compare Flag 5C + TIFR5_OCF5B = 0x4 // Output Compare Flag 5B + TIFR5_OCF5A = 0x2 // Output Compare Flag 5A + TIFR5_TOV5 = 0x1 // Timer/Counter5 Overflow Flag + + // TCCR4A: Timer/Counter4 Control Register A + TCCR4A_COM4A = 0xc0 // Compare Output Mode 1A, bits + TCCR4A_COM4B = 0x30 // Compare Output Mode 4B, bits + TCCR4A_COM4C = 0xc // Compare Output Mode 4C, bits + TCCR4A_WGM4 = 0x3 // Waveform Generation Mode + + // TCCR4B: Timer/Counter4 Control Register B + TCCR4B_ICNC4 = 0x80 // Input Capture 4 Noise Canceler + TCCR4B_ICES4 = 0x40 // Input Capture 4 Edge Select + TCCR4B_WGM4 = 0x18 // Waveform Generation Mode + TCCR4B_CS4 = 0x7 // Prescaler source of Timer/Counter 4 + + // TCCR4C: Timer/Counter 4 Control Register C + TCCR4C_FOC4A = 0x80 // Force Output Compare 4A + TCCR4C_FOC4B = 0x40 // Force Output Compare 4B + TCCR4C_FOC4C = 0x20 // Force Output Compare 4C + + // TIMSK4: Timer/Counter4 Interrupt Mask Register + TIMSK4_ICIE4 = 0x20 // Timer/Counter4 Input Capture Interrupt Enable + TIMSK4_OCIE4C = 0x8 // Timer/Counter4 Output Compare C Match Interrupt Enable + TIMSK4_OCIE4B = 0x4 // Timer/Counter4 Output Compare B Match Interrupt Enable + TIMSK4_OCIE4A = 0x2 // Timer/Counter4 Output Compare A Match Interrupt Enable + TIMSK4_TOIE4 = 0x1 // Timer/Counter4 Overflow Interrupt Enable + + // TIFR4: Timer/Counter4 Interrupt Flag register + TIFR4_ICF4 = 0x20 // Input Capture Flag 4 + TIFR4_OCF4C = 0x8 // Output Compare Flag 4C + TIFR4_OCF4B = 0x4 // Output Compare Flag 4B + TIFR4_OCF4A = 0x2 // Output Compare Flag 4A + TIFR4_TOV4 = 0x1 // Timer/Counter4 Overflow Flag + + // TCCR3A: Timer/Counter3 Control Register A + TCCR3A_COM3A = 0xc0 // Compare Output Mode 1A, bits + TCCR3A_COM3B = 0x30 // Compare Output Mode 3B, bits + TCCR3A_COM3C = 0xc // Compare Output Mode 3C, bits + TCCR3A_WGM3 = 0x3 // Waveform Generation Mode + + // TCCR3B: Timer/Counter3 Control Register B + TCCR3B_ICNC3 = 0x80 // Input Capture 3 Noise Canceler + TCCR3B_ICES3 = 0x40 // Input Capture 3 Edge Select + TCCR3B_WGM3 = 0x18 // Waveform Generation Mode + TCCR3B_CS3 = 0x7 // Prescaler source of Timer/Counter 3 + + // TCCR3C: Timer/Counter 3 Control Register C + TCCR3C_FOC3A = 0x80 // Force Output Compare 3A + TCCR3C_FOC3B = 0x40 // Force Output Compare 3B + TCCR3C_FOC3C = 0x20 // Force Output Compare 3C + + // TIMSK3: Timer/Counter3 Interrupt Mask Register + TIMSK3_ICIE3 = 0x20 // Timer/Counter3 Input Capture Interrupt Enable + TIMSK3_OCIE3C = 0x8 // Timer/Counter3 Output Compare C Match Interrupt Enable + TIMSK3_OCIE3B = 0x4 // Timer/Counter3 Output Compare B Match Interrupt Enable + TIMSK3_OCIE3A = 0x2 // Timer/Counter3 Output Compare A Match Interrupt Enable + TIMSK3_TOIE3 = 0x1 // Timer/Counter3 Overflow Interrupt Enable + + // TIFR3: Timer/Counter3 Interrupt Flag register + TIFR3_ICF3 = 0x20 // Input Capture Flag 3 + TIFR3_OCF3C = 0x8 // Output Compare Flag 3C + TIFR3_OCF3B = 0x4 // Output Compare Flag 3B + TIFR3_OCF3A = 0x2 // Output Compare Flag 3A + TIFR3_TOV3 = 0x1 // Timer/Counter3 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_COM1C = 0xc // Compare Output Mode 1C, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + TCCR1C_FOC1C = 0x20 // Force Output Compare 1C + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1C = 0x8 // Timer/Counter1 Output Compare C Match Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1C = 0x8 // Output Compare Flag 1C + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EICRB: External Interrupt Control Register B + EICRB_ISC7 = 0xc0 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC6 = 0x30 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC5 = 0xc // External Interrupt 7-4 Sense Control Bit + EICRB_ISC4 = 0x3 // External Interrupt 7-4 Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xff // External Interrupt Request 7 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xff // External Interrupt Flags + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Mask interrupt + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Mask interrupt + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Mask interrupt + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0x7 // Pin Change Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0x7 // Pin Change Interrupt Enables +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // XMCRA: External Memory Control Register A + XMCRA_SRE = 0x80 // External SRAM Enable + XMCRA_SRL = 0x70 // Wait state page limit + XMCRA_SRW1 = 0xc // Wait state select bit upper page + XMCRA_SRW0 = 0x3 // Wait state select bit lower page + + // XMCRB: External Memory Control Register B + XMCRB_XMBK = 0x80 // External Memory Bus Keeper Enable + XMCRB_XMM = 0x7 // External Memory High Mask + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 + + // PRR1: Power Reduction Register1 + PRR1_PRTIM5 = 0x20 // Power Reduction Timer/Counter5 + PRR1_PRTIM4 = 0x10 // Power Reduction Timer/Counter4 + PRR1_PRTIM3 = 0x8 // Power Reduction Timer/Counter3 + PRR1_PRUSART3 = 0x4 // Power Reduction USART3 + PRR1_PRUSART2 = 0x2 // Power Reduction USART2 + PRR1_PRUSART1 = 0x1 // Power Reduction USART1 + + // PRR0: Power Reduction Register0 + PRR0_PRTWI = 0x80 // Power Reduction TWI + PRR0_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR0_PRUSART0 = 0x2 // Power Reduction USART0 + PRR0_PRADC = 0x1 // Power Reduction ADC +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR2: Digital Input Disable Register + DIDR2_ADC15D = 0x80 + DIDR2_ADC14D = 0x40 + DIDR2_ADC13D = 0x20 + DIDR2_ADC12D = 0x10 + DIDR2_ADC11D = 0x8 + DIDR2_ADC10D = 0x4 + DIDR2_ADC9D = 0x2 + DIDR2_ADC8D = 0x1 + + // DIDR0: Digital Input Disable Register + DIDR0_ADC7D = 0x80 + DIDR0_ADC6D = 0x40 + DIDR0_ADC5D = 0x20 + DIDR0_ADC4D = 0x10 + DIDR0_ADC3D = 0x8 + DIDR0_ADC2D = 0x4 + DIDR0_ADC1D = 0x2 + DIDR0_ADC0D = 0x1 +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) diff --git a/src/device/avr/atmega2561.ld b/src/device/avr/atmega2561.ld new file mode 100644 index 00000000..a3c09a06 --- /dev/null +++ b/src/device/avr/atmega2561.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega2561.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x40000; +__ram_size = 0x2000; +__num_isrs = 57; diff --git a/src/device/avr/atmega2564rfr2.go b/src/device/avr/atmega2564rfr2.go new file mode 100644 index 00000000..a376d2f1 --- /dev/null +++ b/src/device/avr/atmega2564rfr2.go @@ -0,0 +1,1768 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega2564RFR2.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega2564rfr2 + +// Device information for the ATmega2564RFR2. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega2564RFR2" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_INT3 = 4 // External Interrupt Request 3 + IRQ_INT4 = 5 // External Interrupt Request 4 + IRQ_INT5 = 6 // External Interrupt Request 5 + IRQ_INT6 = 7 // External Interrupt Request 6 + IRQ_INT7 = 8 // External Interrupt Request 7 + IRQ_PCINT0 = 9 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 10 // Pin Change Interrupt Request 1 + IRQ_PCINT2 = 11 // Pin Change Interrupt Request 2 + IRQ_WDT = 12 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 13 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 14 // Timer/Counter2 Compare Match B + IRQ_TIMER2_OVF = 15 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 16 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 17 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 18 // Timer/Counter1 Compare Match B + IRQ_TIMER1_COMPC = 19 // Timer/Counter1 Compare Match C + IRQ_TIMER1_OVF = 20 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 21 // Timer/Counter0 Compare Match A + IRQ_TIMER0_COMPB = 22 // Timer/Counter0 Compare Match B + IRQ_TIMER0_OVF = 23 // Timer/Counter0 Overflow + IRQ_SPI_STC = 24 // SPI Serial Transfer Complete + IRQ_USART0_RX = 25 // USART0, Rx Complete + IRQ_USART0_UDRE = 26 // USART0 Data register Empty + IRQ_USART0_TX = 27 // USART0, Tx Complete + IRQ_ANALOG_COMP = 28 // Analog Comparator + IRQ_ADC = 29 // ADC Conversion Complete + IRQ_EE_READY = 30 // EEPROM Ready + IRQ_TIMER3_CAPT = 31 // Timer/Counter3 Capture Event + IRQ_TIMER3_COMPA = 32 // Timer/Counter3 Compare Match A + IRQ_TIMER3_COMPB = 33 // Timer/Counter3 Compare Match B + IRQ_TIMER3_COMPC = 34 // Timer/Counter3 Compare Match C + IRQ_TIMER3_OVF = 35 // Timer/Counter3 Overflow + IRQ_USART1_RX = 36 // USART1, Rx Complete + IRQ_USART1_UDRE = 37 // USART1 Data register Empty + IRQ_USART1_TX = 38 // USART1, Tx Complete + IRQ_TWI = 39 // 2-wire Serial Interface + IRQ_SPM_READY = 40 // Store Program Memory Read + IRQ_TIMER4_CAPT = 41 // Timer/Counter4 Capture Event + IRQ_TIMER4_COMPA = 42 // Timer/Counter4 Compare Match A + IRQ_TIMER4_COMPB = 43 // Timer/Counter4 Compare Match B + IRQ_TIMER4_COMPC = 44 // Timer/Counter4 Compare Match C + IRQ_TIMER4_OVF = 45 // Timer/Counter4 Overflow + IRQ_TIMER5_CAPT = 46 // Timer/Counter5 Capture Event + IRQ_TIMER5_COMPA = 47 // Timer/Counter5 Compare Match A + IRQ_TIMER5_COMPB = 48 // Timer/Counter5 Compare Match B + IRQ_TIMER5_COMPC = 49 // Timer/Counter5 Compare Match C + IRQ_TIMER5_OVF = 50 // Timer/Counter5 Overflow + IRQ_TRX24_PLL_LOCK = 57 // TRX24 - PLL lock interrupt + IRQ_TRX24_PLL_UNLOCK = 58 // TRX24 - PLL unlock interrupt + IRQ_TRX24_RX_START = 59 // TRX24 - Receive start interrupt + IRQ_TRX24_RX_END = 60 // TRX24 - RX_END interrupt + IRQ_TRX24_CCA_ED_DONE = 61 // TRX24 - CCA/ED done interrupt + IRQ_TRX24_XAH_AMI = 62 // TRX24 - XAH - AMI + IRQ_TRX24_TX_END = 63 // TRX24 - TX_END interrupt + IRQ_TRX24_AWAKE = 64 // TRX24 AWAKE - tranceiver is reaching state TRX_OFF + IRQ_SCNT_CMP1 = 65 // Symbol counter - compare match 1 interrupt + IRQ_SCNT_CMP2 = 66 // Symbol counter - compare match 2 interrupt + IRQ_SCNT_CMP3 = 67 // Symbol counter - compare match 3 interrupt + IRQ_SCNT_OVFL = 68 // Symbol counter - overflow interrupt + IRQ_SCNT_BACKOFF = 69 // Symbol counter - backoff interrupt + IRQ_AES_READY = 70 // AES engine ready interrupt + IRQ_BAT_LOW = 71 // Battery monitor indicates supply voltage below threshold + IRQ_TRX24_TX_START = 72 // TRX24 TX start interrupt + IRQ_TRX24_AMI0 = 73 // Address match interrupt of address filter 0 + IRQ_TRX24_AMI1 = 74 // Address match interrupt of address filter 1 + IRQ_TRX24_AMI2 = 75 // Address match interrupt of address filter 2 + IRQ_TRX24_AMI3 = 76 // Address match interrupt of address filter 3 + IRQ_max = 76 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // USART + USART = struct { + UDR0 __reg + UBRR0L __reg + UBRR0H __reg + UDR1 __reg + UBRR1L __reg + UBRR1H __reg + }{ + UDR0: 0xc6, // USART0 I/O Data Register + UBRR0L: 0xc4, // USART0 Baud Rate Register Bytes + UBRR0H: 0xc4, // USART0 Baud Rate Register Bytes + UDR1: 0xce, // USART1 I/O Data Register + UBRR1L: 0xcc, // USART1 Baud Rate Register Bytes + UBRR1H: 0xcc, // USART1 Baud Rate Register Bytes + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate Register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data Register + TWAR: 0xba, // TWI (Slave) Address Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins Address + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins Address + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins Address + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins Address + PORTE: 0x2e, // Port E Data Register + DDRE: 0x2d, // Port E Data Direction Register + PINE: 0x2c, // Port E Input Pins Address + PORTF: 0x31, // Port F Data Register + DDRF: 0x30, // Port F Data Direction Register + PINF: 0x2f, // Port F Input Pins Address + PORTG: 0x34, // Port G Data Register + DDRG: 0x33, // Port G Data Direction Register + PING: 0x32, // Port G Input Pins Address + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register B + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 Register + TCCR0B: 0x45, // Timer/Counter0 Control Register B + TCCR0A: 0x44, // Timer/Counter0 Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag Register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR5A __reg + TCCR5B __reg + TCCR5C __reg + TCNT5L __reg + TCNT5H __reg + OCR5AL __reg + OCR5AH __reg + OCR5BL __reg + OCR5BH __reg + OCR5CL __reg + OCR5CH __reg + ICR5L __reg + ICR5H __reg + TIMSK5 __reg + TIFR5 __reg + TCCR4A __reg + TCCR4B __reg + TCCR4C __reg + TCNT4L __reg + TCNT4H __reg + OCR4AL __reg + OCR4AH __reg + OCR4BL __reg + OCR4BH __reg + OCR4CL __reg + OCR4CH __reg + ICR4L __reg + ICR4H __reg + TIMSK4 __reg + TIFR4 __reg + TCCR3A __reg + TCCR3B __reg + TCCR3C __reg + TCNT3L __reg + TCNT3H __reg + OCR3AL __reg + OCR3AH __reg + OCR3BL __reg + OCR3BH __reg + OCR3CL __reg + OCR3CH __reg + ICR3L __reg + ICR3H __reg + TIMSK3 __reg + TIFR3 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + OCR1CL __reg + OCR1CH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR5A: 0x120, // Timer/Counter5 Control Register A + TCCR5B: 0x121, // Timer/Counter5 Control Register B + TCCR5C: 0x122, // Timer/Counter5 Control Register C + TCNT5L: 0x124, // Timer/Counter5 Bytes + TCNT5H: 0x124, // Timer/Counter5 Bytes + OCR5AL: 0x128, // Timer/Counter5 Output Compare Register A Bytes + OCR5AH: 0x128, // Timer/Counter5 Output Compare Register A Bytes + OCR5BL: 0x12a, // Timer/Counter5 Output Compare Register B Bytes + OCR5BH: 0x12a, // Timer/Counter5 Output Compare Register B Bytes + OCR5CL: 0x12c, // Timer/Counter5 Output Compare Register C Bytes + OCR5CH: 0x12c, // Timer/Counter5 Output Compare Register C Bytes + ICR5L: 0x126, // Timer/Counter5 Input Capture Register Bytes + ICR5H: 0x126, // Timer/Counter5 Input Capture Register Bytes + TIMSK5: 0x73, // Timer/Counter5 Interrupt Mask Register + TIFR5: 0x3a, // Timer/Counter5 Interrupt Flag Register + TCCR4A: 0xa0, // Timer/Counter4 Control Register A + TCCR4B: 0xa1, // Timer/Counter4 Control Register B + TCCR4C: 0xa2, // Timer/Counter4 Control Register C + TCNT4L: 0xa4, // Timer/Counter4 Bytes + TCNT4H: 0xa4, // Timer/Counter4 Bytes + OCR4AL: 0xa8, // Timer/Counter4 Output Compare Register A Bytes + OCR4AH: 0xa8, // Timer/Counter4 Output Compare Register A Bytes + OCR4BL: 0xaa, // Timer/Counter4 Output Compare Register B Bytes + OCR4BH: 0xaa, // Timer/Counter4 Output Compare Register B Bytes + OCR4CL: 0xac, // Timer/Counter4 Output Compare Register C Bytes + OCR4CH: 0xac, // Timer/Counter4 Output Compare Register C Bytes + ICR4L: 0xa6, // Timer/Counter4 Input Capture Register Bytes + ICR4H: 0xa6, // Timer/Counter4 Input Capture Register Bytes + TIMSK4: 0x72, // Timer/Counter4 Interrupt Mask Register + TIFR4: 0x39, // Timer/Counter4 Interrupt Flag Register + TCCR3A: 0x90, // Timer/Counter3 Control Register A + TCCR3B: 0x91, // Timer/Counter3 Control Register B + TCCR3C: 0x92, // Timer/Counter3 Control Register C + TCNT3L: 0x94, // Timer/Counter3 Bytes + TCNT3H: 0x94, // Timer/Counter3 Bytes + OCR3AL: 0x98, // Timer/Counter3 Output Compare Register A Bytes + OCR3AH: 0x98, // Timer/Counter3 Output Compare Register A Bytes + OCR3BL: 0x9a, // Timer/Counter3 Output Compare Register B Bytes + OCR3BH: 0x9a, // Timer/Counter3 Output Compare Register B Bytes + OCR3CL: 0x9c, // Timer/Counter3 Output Compare Register C Bytes + OCR3CH: 0x9c, // Timer/Counter3 Output Compare Register C Bytes + ICR3L: 0x96, // Timer/Counter3 Input Capture Register Bytes + ICR3H: 0x96, // Timer/Counter3 Input Capture Register Bytes + TIMSK3: 0x71, // Timer/Counter3 Interrupt Mask Register + TIFR3: 0x38, // Timer/Counter3 Interrupt Flag Register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1CL: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + OCR1CH: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag Register + } + + // Low-Power 2.4 GHz Transceiver + TRX24 = struct { + PARCR __reg + MAFSA0L __reg + MAFSA0H __reg + MAFPA0L __reg + MAFPA0H __reg + MAFSA1L __reg + MAFSA1H __reg + MAFPA1L __reg + MAFPA1H __reg + MAFSA2L __reg + MAFSA2H __reg + MAFPA2L __reg + MAFPA2H __reg + MAFSA3L __reg + MAFSA3H __reg + MAFPA3L __reg + MAFPA3H __reg + MAFCR0 __reg + MAFCR1 __reg + AES_CTRL __reg + AES_STATUS __reg + AES_STATE __reg + AES_KEY __reg + TRX_STATUS __reg + TRX_STATE __reg + TRX_CTRL_0 __reg + TRX_CTRL_1 __reg + PHY_TX_PWR __reg + PHY_RSSI __reg + PHY_ED_LEVEL __reg + PHY_CC_CCA __reg + CCA_THRES __reg + RX_CTRL __reg + SFD_VALUE __reg + TRX_CTRL_2 __reg + ANT_DIV __reg + IRQ_MASK __reg + IRQ_STATUS __reg + IRQ_MASK1 __reg + IRQ_STATUS1 __reg + VREG_CTRL __reg + BATMON __reg + XOSC_CTRL __reg + CC_CTRL_0 __reg + CC_CTRL_1 __reg + RX_SYN __reg + TRX_RPC __reg + XAH_CTRL_1 __reg + FTN_CTRL __reg + PLL_CF __reg + PLL_DCU __reg + PART_NUM __reg + VERSION_NUM __reg + MAN_ID_0 __reg + MAN_ID_1 __reg + SHORT_ADDR_0 __reg + SHORT_ADDR_1 __reg + PAN_ID_0 __reg + PAN_ID_1 __reg + IEEE_ADDR_0 __reg + IEEE_ADDR_1 __reg + IEEE_ADDR_2 __reg + IEEE_ADDR_3 __reg + IEEE_ADDR_4 __reg + IEEE_ADDR_5 __reg + IEEE_ADDR_6 __reg + IEEE_ADDR_7 __reg + XAH_CTRL_0 __reg + CSMA_SEED_0 __reg + CSMA_SEED_1 __reg + CSMA_BE __reg + TST_CTRL_DIGI __reg + TST_RX_LENGTH __reg + TRXFBST __reg + TRXFBEND __reg + }{ + PARCR: 0x138, // Power Amplifier Ramp up/down Control Register + MAFSA0L: 0x10e, // Transceiver MAC Short Address Register for Frame Filter 0 (Low Byte) + MAFSA0H: 0x10f, // Transceiver MAC Short Address Register for Frame Filter 0 (High Byte) + MAFPA0L: 0x110, // Transceiver Personal Area Network ID Register for Frame Filter 0 (Low Byte) + MAFPA0H: 0x111, // Transceiver Personal Area Network ID Register for Frame Filter 0 (High Byte) + MAFSA1L: 0x112, // Transceiver MAC Short Address Register for Frame Filter 1 (Low Byte) + MAFSA1H: 0x113, // Transceiver MAC Short Address Register for Frame Filter 1 (High Byte) + MAFPA1L: 0x114, // Transceiver Personal Area Network ID Register for Frame Filter 1 (Low Byte) + MAFPA1H: 0x115, // Transceiver Personal Area Network ID Register for Frame Filter 1 (High Byte) + MAFSA2L: 0x116, // Transceiver MAC Short Address Register for Frame Filter 2 (Low Byte) + MAFSA2H: 0x117, // Transceiver MAC Short Address Register for Frame Filter 2 (High Byte) + MAFPA2L: 0x118, // Transceiver Personal Area Network ID Register for Frame Filter 2 (Low Byte) + MAFPA2H: 0x119, // Transceiver Personal Area Network ID Register for Frame Filter 2 (High Byte) + MAFSA3L: 0x11a, // Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte) + MAFSA3H: 0x11b, // Transceiver MAC Short Address Register for Frame Filter 3 (High Byte) + MAFPA3L: 0x11c, // Transceiver Personal Area Network ID Register for Frame Filter 3 (Low Byte) + MAFPA3H: 0x11d, // Transceiver Personal Area Network ID Register for Frame Filter 3 (High Byte) + MAFCR0: 0x10c, // Multiple Address Filter Configuration Register 0 + MAFCR1: 0x10d, // Multiple Address Filter Configuration Register 1 + AES_CTRL: 0x13c, // AES Control Register + AES_STATUS: 0x13d, // AES Status Register + AES_STATE: 0x13e, // AES Plain and Cipher Text Buffer Register + AES_KEY: 0x13f, // AES Encryption and Decryption Key Buffer Register + TRX_STATUS: 0x141, // Transceiver Status Register + TRX_STATE: 0x142, // Transceiver State Control Register + TRX_CTRL_0: 0x143, // Reserved + TRX_CTRL_1: 0x144, // Transceiver Control Register 1 + PHY_TX_PWR: 0x145, // Transceiver Transmit Power Control Register + PHY_RSSI: 0x146, // Receiver Signal Strength Indicator Register + PHY_ED_LEVEL: 0x147, // Transceiver Energy Detection Level Register + PHY_CC_CCA: 0x148, // Transceiver Clear Channel Assessment (CCA) Control Register + CCA_THRES: 0x149, // Transceiver CCA Threshold Setting Register + RX_CTRL: 0x14a, // Transceiver Receive Control Register + SFD_VALUE: 0x14b, // Start of Frame Delimiter Value Register + TRX_CTRL_2: 0x14c, // Transceiver Control Register 2 + ANT_DIV: 0x14d, // Antenna Diversity Control Register + IRQ_MASK: 0x14e, // Transceiver Interrupt Enable Register + IRQ_STATUS: 0x14f, // Transceiver Interrupt Status Register + IRQ_MASK1: 0xbe, // Transceiver Interrupt Enable Register 1 + IRQ_STATUS1: 0xbf, // Transceiver Interrupt Status Register 1 + VREG_CTRL: 0x150, // Voltage Regulator Control and Status Register + BATMON: 0x151, // Battery Monitor Control and Status Register + XOSC_CTRL: 0x152, // Crystal Oscillator Control Register + CC_CTRL_0: 0x153, // Channel Control Register 0 + CC_CTRL_1: 0x154, // Channel Control Register 1 + RX_SYN: 0x155, // Transceiver Receiver Sensitivity Control Register + TRX_RPC: 0x156, // Transceiver Reduced Power Consumption Control + XAH_CTRL_1: 0x157, // Transceiver Acknowledgment Frame Control Register 1 + FTN_CTRL: 0x158, // Transceiver Filter Tuning Control Register + PLL_CF: 0x15a, // Transceiver Center Frequency Calibration Control Register + PLL_DCU: 0x15b, // Transceiver Delay Cell Calibration Control Register + PART_NUM: 0x15c, // Device Identification Register (Part Number) + VERSION_NUM: 0x15d, // Device Identification Register (Version Number) + MAN_ID_0: 0x15e, // Device Identification Register (Manufacture ID Low Byte) + MAN_ID_1: 0x15f, // Device Identification Register (Manufacture ID High Byte) + SHORT_ADDR_0: 0x160, // Transceiver MAC Short Address Register (Low Byte) + SHORT_ADDR_1: 0x161, // Transceiver MAC Short Address Register (High Byte) + PAN_ID_0: 0x162, // Transceiver Personal Area Network ID Register (Low Byte) + PAN_ID_1: 0x163, // Transceiver Personal Area Network ID Register (High Byte) + IEEE_ADDR_0: 0x164, // Transceiver MAC IEEE Address Register 0 + IEEE_ADDR_1: 0x165, // Transceiver MAC IEEE Address Register 1 + IEEE_ADDR_2: 0x166, // Transceiver MAC IEEE Address Register 2 + IEEE_ADDR_3: 0x167, // Transceiver MAC IEEE Address Register 3 + IEEE_ADDR_4: 0x168, // Transceiver MAC IEEE Address Register 4 + IEEE_ADDR_5: 0x169, // Transceiver MAC IEEE Address Register 5 + IEEE_ADDR_6: 0x16a, // Transceiver MAC IEEE Address Register 6 + IEEE_ADDR_7: 0x16b, // Transceiver MAC IEEE Address Register 7 + XAH_CTRL_0: 0x16c, // Transceiver Extended Operating Mode Control Register + CSMA_SEED_0: 0x16d, // Transceiver CSMA-CA Random Number Generator Seed Register + CSMA_SEED_1: 0x16e, // Transceiver Acknowledgment Frame Control Register 2 + CSMA_BE: 0x16f, // Transceiver CSMA-CA Back-off Exponent Control Register + TST_CTRL_DIGI: 0x176, // Transceiver Digital Test Control Register + TST_RX_LENGTH: 0x17b, // Transceiver Received Frame Length Register + TRXFBST: 0x180, // Start of frame buffer + TRXFBEND: 0x1ff, // End of frame buffer + } + + // MAC Symbol Counter + SYMCNT = struct { + SCTSTRHH __reg + SCTSTRHL __reg + SCTSTRLH __reg + SCTSTRLL __reg + SCOCR1HH __reg + SCOCR1HL __reg + SCOCR1LH __reg + SCOCR1LL __reg + SCOCR2HH __reg + SCOCR2HL __reg + SCOCR2LH __reg + SCOCR2LL __reg + SCOCR3HH __reg + SCOCR3HL __reg + SCOCR3LH __reg + SCOCR3LL __reg + SCTSRHH __reg + SCTSRHL __reg + SCTSRLH __reg + SCTSRLL __reg + SCBTSRHH __reg + SCBTSRHL __reg + SCBTSRLH __reg + SCBTSRLL __reg + SCCNTHH __reg + SCCNTHL __reg + SCCNTLH __reg + SCCNTLL __reg + SCIRQS __reg + SCIRQM __reg + SCSR __reg + SCCR1 __reg + SCCR0 __reg + SCCSR __reg + SCRSTRHH __reg + SCRSTRHL __reg + SCRSTRLH __reg + SCRSTRLL __reg + }{ + SCTSTRHH: 0xfc, // Symbol Counter Transmit Frame Timestamp Register HH-Byte + SCTSTRHL: 0xfb, // Symbol Counter Transmit Frame Timestamp Register HL-Byte + SCTSTRLH: 0xfa, // Symbol Counter Transmit Frame Timestamp Register LH-Byte + SCTSTRLL: 0xf9, // Symbol Counter Transmit Frame Timestamp Register LL-Byte + SCOCR1HH: 0xf8, // Symbol Counter Output Compare Register 1 HH-Byte + SCOCR1HL: 0xf7, // Symbol Counter Output Compare Register 1 HL-Byte + SCOCR1LH: 0xf6, // Symbol Counter Output Compare Register 1 LH-Byte + SCOCR1LL: 0xf5, // Symbol Counter Output Compare Register 1 LL-Byte + SCOCR2HH: 0xf4, // Symbol Counter Output Compare Register 2 HH-Byte + SCOCR2HL: 0xf3, // Symbol Counter Output Compare Register 2 HL-Byte + SCOCR2LH: 0xf2, // Symbol Counter Output Compare Register 2 LH-Byte + SCOCR2LL: 0xf1, // Symbol Counter Output Compare Register 2 LL-Byte + SCOCR3HH: 0xf0, // Symbol Counter Output Compare Register 3 HH-Byte + SCOCR3HL: 0xef, // Symbol Counter Output Compare Register 3 HL-Byte + SCOCR3LH: 0xee, // Symbol Counter Output Compare Register 3 LH-Byte + SCOCR3LL: 0xed, // Symbol Counter Output Compare Register 3 LL-Byte + SCTSRHH: 0xec, // Symbol Counter Frame Timestamp Register HH-Byte + SCTSRHL: 0xeb, // Symbol Counter Frame Timestamp Register HL-Byte + SCTSRLH: 0xea, // Symbol Counter Frame Timestamp Register LH-Byte + SCTSRLL: 0xe9, // Symbol Counter Frame Timestamp Register LL-Byte + SCBTSRHH: 0xe8, // Symbol Counter Beacon Timestamp Register HH-Byte + SCBTSRHL: 0xe7, // Symbol Counter Beacon Timestamp Register HL-Byte + SCBTSRLH: 0xe6, // Symbol Counter Beacon Timestamp Register LH-Byte + SCBTSRLL: 0xe5, // Symbol Counter Beacon Timestamp Register LL-Byte + SCCNTHH: 0xe4, // Symbol Counter Register HH-Byte + SCCNTHL: 0xe3, // Symbol Counter Register HL-Byte + SCCNTLH: 0xe2, // Symbol Counter Register LH-Byte + SCCNTLL: 0xe1, // Symbol Counter Register LL-Byte + SCIRQS: 0xe0, // Symbol Counter Interrupt Status Register + SCIRQM: 0xdf, // Symbol Counter Interrupt Mask Register + SCSR: 0xde, // Symbol Counter Status Register + SCCR1: 0xdd, // Symbol Counter Control Register 1 + SCCR0: 0xdc, // Symbol Counter Control Register 0 + SCCSR: 0xdb, // Symbol Counter Compare Source Register + SCRSTRHH: 0xda, // Symbol Counter Received Frame Timestamp Register HH-Byte + SCRSTRHL: 0xd9, // Symbol Counter Received Frame Timestamp Register HL-Byte + SCRSTRLH: 0xd8, // Symbol Counter Received Frame Timestamp Register LH-Byte + SCRSTRLL: 0xd7, // Symbol Counter Received Frame Timestamp Register LL-Byte + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Bytes + EEARH: 0x41, // EEPROM Address Register Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EICRB __reg + EIMSK __reg + EIFR __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + PCICR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EICRB: 0x6a, // External Interrupt Control Register B + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + ADCSRC __reg + DIDR2 __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC Multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // The ADC Control and Status Register A + ADCSRC: 0x77, // The ADC Control and Status Register C + DIDR2: 0x7d, // Digital Input Disable Register 2 + DIDR0: 0x7e, // Digital Input Disable Register 0 + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + EIND __reg + RAMPZ __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PRR2 __reg + PRR1 __reg + PRR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + SMCR: 0x53, // Sleep Mode Control Register + EIND: 0x5c, // Extended Indirect Register + RAMPZ: 0x5b, // Extended Z-pointer Register for ELPM/SPM + GPIOR2: 0x4b, // General Purpose I/O Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PRR2: 0x63, // Power Reduction Register 2 + PRR1: 0x65, // Power Reduction Register 1 + PRR0: 0x64, // Power Reduction Register0 + } + + // FLASH Controller + FLASH = struct { + NEMCR __reg + BGCR __reg + }{ + NEMCR: 0x75, // Flash Extended-Mode Control-Register + BGCR: 0x67, // Reference Voltage Calibration Register + } + + // Power Controller + PWRCTRL = struct { + TRXPR __reg + DRTRAM0 __reg + DRTRAM1 __reg + DRTRAM2 __reg + DRTRAM3 __reg + LLDRL __reg + LLDRH __reg + LLCR __reg + DPDS0 __reg + DPDS1 __reg + }{ + TRXPR: 0x139, // Transceiver Pin Register + DRTRAM0: 0x135, // Data Retention Configuration Register #0 + DRTRAM1: 0x134, // Data Retention Configuration Register #1 + DRTRAM2: 0x133, // Data Retention Configuration Register #2 + DRTRAM3: 0x132, // Data Retention Configuration Register #3 + LLDRL: 0x130, // Low Leakage Voltage Regulator Data Register (Low-Byte) + LLDRH: 0x131, // Low Leakage Voltage Regulator Data Register (High-Byte) + LLCR: 0x12f, // Low Leakage Voltage Regulator Control Register + DPDS0: 0x136, // Port Driver Strength Register 0 + DPDS1: 0x137, // Port Driver Strength Register 1 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_CKSEL_SUT = 0x3f // Select Clock Source : Start-up time +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe // TWI Address Mask + TWAMR_Res = 0x1 // Reserved Bit + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI START Condition Bit + TWCR_TWSTO = 0x10 // TWI STOP Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collision Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_Res = 0x2 // Reserved Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_Res = 0x4 // Reserved Bit + TWSR_TWPS = 0x3 // TWI Prescaler Bits + + // TWAR: TWI (Slave) Address Register + TWAR_TWA = 0xfe // TWI (Slave) Address + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Select 1 and 0 + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter0 Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_Res = 0x30 // Reserved Bit + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter0 Control Register A + TCCR0A_COM0A = 0xc0 // Compare Match Output A Mode + TCCR0A_COM0B = 0x30 // Compare Match Output B Mode + TCCR0A_Res = 0xc // Reserved Bit + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag Register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare B Match Flag + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare A Match Flag + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_Res = 0xf8 // Reserved Bit + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_Res = 0xf8 // Reserved Bit + TIFR2_OCF2B = 0x4 // Output Compare Flag 2 B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2 A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Match Output A Mode + TCCR2A_COM2B = 0x30 // Compare Match Output B Mode + TCCR2A_WGM2 = 0x3 // Waveform Generation Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select + + // ASSR: Asynchronous Status Register + ASSR_EXCLKAMR = 0x80 // Enable External Clock Input for AMR + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Timer/Counter2 Asynchronous Mode + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Timer/Counter2 Output Compare Register A Update Busy + ASSR_OCR2BUB = 0x4 // Timer/Counter2 Output Compare Register B Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter2 Control Register A Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter2 Control Register B Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR5A: Timer/Counter5 Control Register A + TCCR5A_COM5A = 0xc0 // Compare Output Mode for Channel A + TCCR5A_COM5B = 0x30 // Compare Output Mode for Channel B + TCCR5A_COM5C = 0xc // Compare Output Mode for Channel C + TCCR5A_WGM5 = 0x3 // Waveform Generation Mode + + // TCCR5B: Timer/Counter5 Control Register B + TCCR5B_ICNC5 = 0x80 // Input Capture 5 Noise Canceller + TCCR5B_ICES5 = 0x40 // Input Capture 5 Edge Select + TCCR5B_Res = 0x20 // Reserved Bit + TCCR5B_WGM5 = 0x18 // Waveform Generation Mode + TCCR5B_CS5 = 0x7 // Clock Select + + // TCCR5C: Timer/Counter5 Control Register C + TCCR5C_FOC5A = 0x80 // Force Output Compare for Channel A + TCCR5C_FOC5B = 0x40 // Force Output Compare for Channel B + TCCR5C_FOC5C = 0x20 // Force Output Compare for Channel C + + // TIMSK5: Timer/Counter5 Interrupt Mask Register + TIMSK5_ICIE5 = 0x20 // Timer/Counter5 Input Capture Interrupt Enable + TIMSK5_OCIE5C = 0x8 // Timer/Counter5 Output Compare C Match Interrupt Enable + TIMSK5_OCIE5B = 0x4 // Timer/Counter5 Output Compare B Match Interrupt Enable + TIMSK5_OCIE5A = 0x2 // Timer/Counter5 Output Compare A Match Interrupt Enable + TIMSK5_TOIE5 = 0x1 // Timer/Counter5 Overflow Interrupt Enable + + // TIFR5: Timer/Counter5 Interrupt Flag Register + TIFR5_ICF5 = 0x20 // Timer/Counter5 Input Capture Flag + TIFR5_OCF5C = 0x8 // Timer/Counter5 Output Compare C Match Flag + TIFR5_OCF5B = 0x4 // Timer/Counter5 Output Compare B Match Flag + TIFR5_OCF5A = 0x2 // Timer/Counter5 Output Compare A Match Flag + TIFR5_TOV5 = 0x1 // Timer/Counter5 Overflow Flag + + // TCCR4A: Timer/Counter4 Control Register A + TCCR4A_COM4A = 0xc0 // Compare Output Mode for Channel A + TCCR4A_COM4B = 0x30 // Compare Output Mode for Channel B + TCCR4A_COM4C = 0xc // Compare Output Mode for Channel C + TCCR4A_WGM4 = 0x3 // Waveform Generation Mode + + // TCCR4B: Timer/Counter4 Control Register B + TCCR4B_ICNC4 = 0x80 // Input Capture 4 Noise Canceller + TCCR4B_ICES4 = 0x40 // Input Capture 4 Edge Select + TCCR4B_Res = 0x20 // Reserved Bit + TCCR4B_WGM4 = 0x18 // Waveform Generation Mode + TCCR4B_CS4 = 0x7 // Clock Select + + // TCCR4C: Timer/Counter4 Control Register C + TCCR4C_FOC4A = 0x80 // Force Output Compare for Channel A + TCCR4C_FOC4B = 0x40 // Force Output Compare for Channel B + TCCR4C_FOC4C = 0x20 // Force Output Compare for Channel C + + // TIMSK4: Timer/Counter4 Interrupt Mask Register + TIMSK4_ICIE4 = 0x20 // Timer/Counter4 Input Capture Interrupt Enable + TIMSK4_OCIE4C = 0x8 // Timer/Counter4 Output Compare C Match Interrupt Enable + TIMSK4_OCIE4B = 0x4 // Timer/Counter4 Output Compare B Match Interrupt Enable + TIMSK4_OCIE4A = 0x2 // Timer/Counter4 Output Compare A Match Interrupt Enable + TIMSK4_TOIE4 = 0x1 // Timer/Counter4 Overflow Interrupt Enable + + // TIFR4: Timer/Counter4 Interrupt Flag Register + TIFR4_ICF4 = 0x20 // Timer/Counter4 Input Capture Flag + TIFR4_OCF4C = 0x8 // Timer/Counter4 Output Compare C Match Flag + TIFR4_OCF4B = 0x4 // Timer/Counter4 Output Compare B Match Flag + TIFR4_OCF4A = 0x2 // Timer/Counter4 Output Compare A Match Flag + TIFR4_TOV4 = 0x1 // Timer/Counter4 Overflow Flag + + // TCCR3A: Timer/Counter3 Control Register A + TCCR3A_COM3A = 0xc0 // Compare Output Mode for Channel A + TCCR3A_COM3B = 0x30 // Compare Output Mode for Channel B + TCCR3A_COM3C = 0xc // Compare Output Mode for Channel C + TCCR3A_WGM3 = 0x3 // Waveform Generation Mode + + // TCCR3B: Timer/Counter3 Control Register B + TCCR3B_ICNC3 = 0x80 // Input Capture 3 Noise Canceller + TCCR3B_ICES3 = 0x40 // Input Capture 3 Edge Select + TCCR3B_Res = 0x20 // Reserved Bit + TCCR3B_WGM3 = 0x18 // Waveform Generation Mode + TCCR3B_CS3 = 0x7 // Clock Select + + // TCCR3C: Timer/Counter3 Control Register C + TCCR3C_FOC3A = 0x80 // Force Output Compare for Channel A + TCCR3C_FOC3B = 0x40 // Force Output Compare for Channel B + TCCR3C_FOC3C = 0x20 // Force Output Compare for Channel C + + // TIMSK3: Timer/Counter3 Interrupt Mask Register + TIMSK3_ICIE3 = 0x20 // Timer/Counter3 Input Capture Interrupt Enable + TIMSK3_OCIE3C = 0x8 // Timer/Counter3 Output Compare C Match Interrupt Enable + TIMSK3_OCIE3B = 0x4 // Timer/Counter3 Output Compare B Match Interrupt Enable + TIMSK3_OCIE3A = 0x2 // Timer/Counter3 Output Compare A Match Interrupt Enable + TIMSK3_TOIE3 = 0x1 // Timer/Counter3 Overflow Interrupt Enable + + // TIFR3: Timer/Counter3 Interrupt Flag Register + TIFR3_ICF3 = 0x20 // Timer/Counter3 Input Capture Flag + TIFR3_OCF3C = 0x8 // Timer/Counter3 Output Compare C Match Flag + TIFR3_OCF3B = 0x4 // Timer/Counter3 Output Compare B Match Flag + TIFR3_OCF3A = 0x2 // Timer/Counter3 Output Compare A Match Flag + TIFR3_TOV3 = 0x1 // Timer/Counter3 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode for Channel A + TCCR1A_COM1B = 0x30 // Compare Output Mode for Channel B + TCCR1A_COM1C = 0xc // Compare Output Mode for Channel C + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceller + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_Res = 0x20 // Reserved Bit + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Clock Select + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare for Channel A + TCCR1C_FOC1B = 0x40 // Force Output Compare for Channel B + TCCR1C_FOC1C = 0x20 // Force Output Compare for Channel C + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1C = 0x8 // Timer/Counter1 Output Compare C Match Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag Register + TIFR1_ICF1 = 0x20 // Timer/Counter1 Input Capture Flag + TIFR1_OCF1C = 0x8 // Timer/Counter1 Output Compare C Match Flag + TIFR1_OCF1B = 0x4 // Timer/Counter1 Output Compare B Match Flag + TIFR1_OCF1A = 0x2 // Timer/Counter1 Output Compare A Match Flag + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for TRX24: Low-Power 2.4 GHz Transceiver +const ( + // PARCR: Power Amplifier Ramp up/down Control Register + PARCR_PALTD = 0xe0 // ext. PA Ramp Down Lead Time + PARCR_PALTU = 0x1c // ext. PA Ramp Up Lead Time + PARCR_PARDFI = 0x2 // Power Amplifier Ramp Down Frequency Inversion + PARCR_PARUFI = 0x1 // Power Amplifier Ramp Up Frequency Inversion + + // MAFSA0L: Transceiver MAC Short Address Register for Frame Filter 0 (Low Byte) + MAFSA0L_MAFSA0L = 0xff // MAC Short Address low Byte for Frame Filter 0 + + // MAFSA0H: Transceiver MAC Short Address Register for Frame Filter 0 (High Byte) + MAFSA0H_MAFSA0H = 0xff // MAC Short Address high Byte for Frame Filter 0 + + // MAFPA0L: Transceiver Personal Area Network ID Register for Frame Filter 0 (Low Byte) + MAFPA0L_MAFPA0L = 0xff // MAC Personal Area Network ID low Byte for Frame Filter 0 + + // MAFPA0H: Transceiver Personal Area Network ID Register for Frame Filter 0 (High Byte) + MAFPA0H_MAFPA0H = 0xff // MAC Personal Area Network ID high Byte for Frame Filter 0 + + // MAFSA1L: Transceiver MAC Short Address Register for Frame Filter 1 (Low Byte) + MAFSA1L_MAFSA1L = 0xff // MAC Short Address low Byte for Frame Filter 1 + + // MAFSA1H: Transceiver MAC Short Address Register for Frame Filter 1 (High Byte) + MAFSA1H_MAFSA1H = 0xff // MAC Short Address high Byte for Frame Filter 1 + + // MAFPA1L: Transceiver Personal Area Network ID Register for Frame Filter 1 (Low Byte) + MAFPA1L_MAFPA1L = 0xff // MAC Personal Area Network ID low Byte for Frame Filter 1 + + // MAFPA1H: Transceiver Personal Area Network ID Register for Frame Filter 1 (High Byte) + MAFPA1H_MAFPA1H = 0xff // MAC Personal Area Network ID high Byte for Frame Filter 1 + + // MAFSA2L: Transceiver MAC Short Address Register for Frame Filter 2 (Low Byte) + MAFSA2L_MAFSA2L = 0xff // MAC Short Address low Byte for Frame Filter 2 + + // MAFSA2H: Transceiver MAC Short Address Register for Frame Filter 2 (High Byte) + MAFSA2H_MAFSA2H = 0xff // MAC Short Address high Byte for Frame Filter 2 + + // MAFPA2L: Transceiver Personal Area Network ID Register for Frame Filter 2 (Low Byte) + MAFPA2L_MAFPA2L = 0xff // MAC Personal Area Network ID low Byte for Frame Filter 2 + + // MAFPA2H: Transceiver Personal Area Network ID Register for Frame Filter 2 (High Byte) + MAFPA2H_MAFPA2H = 0xff // MAC Personal Area Network ID high Byte for Frame Filter 2 + + // MAFSA3L: Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte) + MAFSA3L_MAFSA3L = 0xff // MAC Short Address low Byte for Frame Filter 3 + + // MAFSA3H: Transceiver MAC Short Address Register for Frame Filter 3 (High Byte) + MAFSA3H_MAFSA3H = 0xff // MAC Short Address high Byte for Frame Filter 3 + + // MAFPA3L: Transceiver Personal Area Network ID Register for Frame Filter 3 (Low Byte) + MAFPA3L_MAFPA3L = 0xff // MAC Personal Area Network ID low Byte for Frame Filter 3 + + // MAFPA3H: Transceiver Personal Area Network ID Register for Frame Filter 3 (High Byte) + MAFPA3H_MAFPA3H = 0xff // MAC Personal Area Network ID high Byte for Frame Filter 3 + + // MAFCR0: Multiple Address Filter Configuration Register 0 + MAFCR0_Res = 0xf0 // Reserved Bit + MAFCR0_MAF3EN = 0x8 // Multiple Address Filter 3 Enable + MAFCR0_MAF2EN = 0x4 // Multiple Address Filter 2 Enable + MAFCR0_MAF1EN = 0x2 // Multiple Address Filter 1 Enable + MAFCR0_MAF0EN = 0x1 // Multiple Address Filter 0 Enable + + // MAFCR1: Multiple Address Filter Configuration Register 1 + MAFCR1_AACK_3_SET_PD = 0x80 // Set Data Pending bit for address filter 3. + MAFCR1_AACK_3_I_AM_COORD = 0x40 // Enable PAN Coordinator mode for address filter 3. + MAFCR1_AACK_2_SET_PD = 0x20 // Set Data Pending bit for address filter 2. + MAFCR1_AACK_2_I_AM_COORD = 0x10 // Enable PAN Coordinator mode for address filter 2. + MAFCR1_AACK_1_SET_PD = 0x8 // Set Data Pending bit for address filter 1. + MAFCR1_AACK_1_I_AM_COORD = 0x4 // Enable PAN Coordinator mode for address filter 1. + MAFCR1_AACK_0_SET_PD = 0x2 // Set Data Pending bit for address filter 0. + MAFCR1_AACK_0_I_AM_COORD = 0x1 // Enable PAN Coordinator mode for address filter 0. + + // AES_CTRL: AES Control Register + AES_CTRL_AES_REQUEST = 0x80 // Request AES Operation. + AES_CTRL_AES_MODE = 0x20 // Set AES Operation Mode + AES_CTRL_AES_DIR = 0x8 // Set AES Operation Direction + AES_CTRL_AES_IM = 0x4 // AES Interrupt Enable + + // AES_STATUS: AES Status Register + AES_STATUS_AES_ER = 0x80 // AES Operation Finished with Error + AES_STATUS_AES_DONE = 0x1 // AES Operation Finished with Success + + // AES_STATE: AES Plain and Cipher Text Buffer Register + AES_STATE_AES_STATE = 0xff // AES Plain and Cipher Text Buffer + + // AES_KEY: AES Encryption and Decryption Key Buffer Register + AES_KEY_AES_KEY = 0xff // AES Encryption/Decryption Key Buffer + + // TRX_STATUS: Transceiver Status Register + TRX_STATUS_CCA_DONE = 0x80 // CCA Algorithm Status + TRX_STATUS_CCA_STATUS = 0x40 // CCA Status Result + TRX_STATUS_TST_STATUS = 0x20 // Test mode status + TRX_STATUS_TRX_STATUS = 0x1f // Transceiver Main Status + + // TRX_STATE: Transceiver State Control Register + TRX_STATE_TRAC_STATUS = 0xe0 // Transaction Status + TRX_STATE_TRX_CMD = 0x1f // State Control Command + + // TRX_CTRL_0: Reserved + TRX_CTRL_0_Res7 = 0x80 // Reserved + TRX_CTRL_0_PMU_EN = 0x40 // Enable Phase Measurement Unit + TRX_CTRL_0_PMU_START = 0x20 // Start of Phase Measurement Unit + TRX_CTRL_0_PMU_IF_INV = 0x10 // PMU IF Inverse + + // TRX_CTRL_1: Transceiver Control Register 1 + TRX_CTRL_1_PA_EXT_EN = 0x80 // External PA support enable + TRX_CTRL_1_IRQ_2_EXT_EN = 0x40 // Connect Frame Start IRQ to TC1 + TRX_CTRL_1_TX_AUTO_CRC_ON = 0x20 // Enable Automatic CRC Calculation + TRX_CTRL_1_PLL_TX_FLT = 0x10 // Enable PLL TX filter + + // PHY_TX_PWR: Transceiver Transmit Power Control Register + PHY_TX_PWR_TX_PWR = 0xf // Transmit Power Setting + + // PHY_RSSI: Receiver Signal Strength Indicator Register + PHY_RSSI_RX_CRC_VALID = 0x80 // Received Frame CRC Status + PHY_RSSI_RND_VALUE = 0x60 // Random Value + PHY_RSSI_RSSI = 0x1f // Receiver Signal Strength Indicator + + // PHY_ED_LEVEL: Transceiver Energy Detection Level Register + PHY_ED_LEVEL_ED_LEVEL = 0xff // Energy Detection Level + + // PHY_CC_CCA: Transceiver Clear Channel Assessment (CCA) Control Register + PHY_CC_CCA_CCA_REQUEST = 0x80 // Manual CCA Measurement Request + PHY_CC_CCA_CCA_MODE = 0x60 // Select CCA Measurement Mode + PHY_CC_CCA_CHANNEL = 0x1f // RX/TX Channel Selection + + // CCA_THRES: Transceiver CCA Threshold Setting Register + CCA_THRES_CCA_CS_THRES = 0xf0 // CS Threshold Level for CCA Measurement + CCA_THRES_CCA_ED_THRES = 0xf // ED Threshold Level for CCA Measurement + + // RX_CTRL: Transceiver Receive Control Register + RX_CTRL_PDT_THRES = 0xf // Receiver Sensitivity Control + + // SFD_VALUE: Start of Frame Delimiter Value Register + SFD_VALUE_SFD_VALUE = 0xff // Start of Frame Delimiter Value + + // TRX_CTRL_2: Transceiver Control Register 2 + TRX_CTRL_2_RX_SAFE_MODE = 0x80 // RX Safe Mode + TRX_CTRL_2_OQPSK_DATA_RATE = 0x3 // Data Rate Selection + + // ANT_DIV: Antenna Diversity Control Register + ANT_DIV_ANT_SEL = 0x80 // Antenna Diversity Antenna Status + ANT_DIV_ANT_DIV_EN = 0x8 // Enable Antenna Diversity + ANT_DIV_ANT_EXT_SW_EN = 0x4 // Enable External Antenna Switch Control + ANT_DIV_ANT_CTRL = 0x3 // Static Antenna Diversity Switch Control + + // IRQ_MASK: Transceiver Interrupt Enable Register + IRQ_MASK_AWAKE_EN = 0x80 // Awake Interrupt Enable + IRQ_MASK_TX_END_EN = 0x40 // TX_END Interrupt Enable + IRQ_MASK_AMI_EN = 0x20 // Address Match Interrupt Enable + IRQ_MASK_CCA_ED_DONE_EN = 0x10 // End of ED Measurement Interrupt Enable + IRQ_MASK_RX_END_EN = 0x8 // RX_END Interrupt Enable + IRQ_MASK_RX_START_EN = 0x4 // RX_START Interrupt Enable + IRQ_MASK_PLL_UNLOCK_EN = 0x2 // PLL Unlock Interrupt Enable + IRQ_MASK_PLL_LOCK_EN = 0x1 // PLL Lock Interrupt Enable + + // IRQ_STATUS: Transceiver Interrupt Status Register + IRQ_STATUS_AWAKE = 0x80 // Awake Interrupt Status + IRQ_STATUS_TX_END = 0x40 // TX_END Interrupt Status + IRQ_STATUS_AMI = 0x20 // Address Match Interrupt Status + IRQ_STATUS_CCA_ED_DONE = 0x10 // End of ED Measurement Interrupt Status + IRQ_STATUS_RX_END = 0x8 // RX_END Interrupt Status + IRQ_STATUS_RX_START = 0x4 // RX_START Interrupt Status + IRQ_STATUS_PLL_UNLOCK = 0x2 // PLL Unlock Interrupt Status + IRQ_STATUS_PLL_LOCK = 0x1 // PLL Lock Interrupt Status + + // IRQ_MASK1: Transceiver Interrupt Enable Register 1 + IRQ_MASK1_Res = 0xe0 // Reserved Bit + IRQ_MASK1_MAF_3_AMI_EN = 0x10 // Address Match Interrupt enable Address filter 3 + IRQ_MASK1_MAF_2_AMI_EN = 0x8 // Address Match Interrupt enable Address filter 2 + IRQ_MASK1_MAF_1_AMI_EN = 0x4 // Address Match Interrupt enable Address filter 1 + IRQ_MASK1_MAF_0_AMI_EN = 0x2 // Address Match Interrupt enable Address filter 0 + IRQ_MASK1_TX_START_EN = 0x1 // Transmit Start Interrupt enable + + // IRQ_STATUS1: Transceiver Interrupt Status Register 1 + IRQ_STATUS1_Res = 0xe0 // Reserved Bit + IRQ_STATUS1_MAF_3_AMI = 0x10 // Address Match Interrupt Status Address filter 3 + IRQ_STATUS1_MAF_2_AMI = 0x8 // Address Match Interrupt Status Address filter 2 + IRQ_STATUS1_MAF_1_AMI = 0x4 // Address Match Interrupt Status Address filter 1 + IRQ_STATUS1_MAF_0_AMI = 0x2 // Address Match Interrupt Status Address filter 0 + IRQ_STATUS1_TX_START = 0x1 // Transmit Start Interrupt Status + + // VREG_CTRL: Voltage Regulator Control and Status Register + VREG_CTRL_AVREG_EXT = 0x80 // Use External AVDD Regulator + VREG_CTRL_AVDD_OK = 0x40 // AVDD Supply Voltage Valid + VREG_CTRL_DVREG_EXT = 0x8 // Use External DVDD Regulator + VREG_CTRL_DVDD_OK = 0x4 // DVDD Supply Voltage Valid + + // BATMON: Battery Monitor Control and Status Register + BATMON_BAT_LOW = 0x80 // Battery Monitor Interrupt Status + BATMON_BAT_LOW_EN = 0x40 // Battery Monitor Interrupt Enable + BATMON_BATMON_OK = 0x20 // Battery Monitor Status + BATMON_BATMON_HR = 0x10 // Battery Monitor Voltage Range + BATMON_BATMON_VTH = 0xf // Battery Monitor Threshold Voltage + + // XOSC_CTRL: Crystal Oscillator Control Register + XOSC_CTRL_XTAL_MODE = 0xf0 // Crystal Oscillator Operating Mode + XOSC_CTRL_XTAL_TRIM = 0xf // Crystal Oscillator Load Capacitance Trimming + + // CC_CTRL_0: Channel Control Register 0 + CC_CTRL_0_CC_NUMBER = 0xff // Channel Number + + // CC_CTRL_1: Channel Control Register 1 + CC_CTRL_1_CC_BAND = 0xf // Channel Band + + // RX_SYN: Transceiver Receiver Sensitivity Control Register + RX_SYN_RX_PDT_DIS = 0x80 // Prevent Frame Reception + RX_SYN_RX_OVERRIDE = 0x40 // Receiver Override Function + RX_SYN_RX_PDT_LEVEL = 0xf // Reduce Receiver Sensitivity + + // TRX_RPC: Transceiver Reduced Power Consumption Control + TRX_RPC_RX_RPC_CTRL = 0xc0 // Smart Receiving Mode Timing + TRX_RPC_RX_RPC_EN = 0x20 // Reciver Smart Receiving Mode Enable + TRX_RPC_PDT_RPC_EN = 0x10 // Smart Receiving Mode Reduced Sensitivity Enable + TRX_RPC_PLL_RPC_EN = 0x8 // PLL Smart Receiving Mode Enable + TRX_RPC_Res0 = 0x4 // Reserved + TRX_RPC_IPAN_RPC_EN = 0x2 // Smart Receiving Mode IPAN Handling Enable + TRX_RPC_XAH_RPC_EN = 0x1 // Smart Receiving in Extended Operating Modes Enable + + // XAH_CTRL_1: Transceiver Acknowledgment Frame Control Register 1 + XAH_CTRL_1_AACK_FLTR_RES_FT = 0x20 // Filter Reserved Frames + XAH_CTRL_1_AACK_UPLD_RES_FT = 0x10 // Process Reserved Frames + XAH_CTRL_1_AACK_ACK_TIME = 0x4 // Reduce Acknowledgment Time + XAH_CTRL_1_AACK_PROM_MODE = 0x2 // Enable Promiscuous Mode + + // FTN_CTRL: Transceiver Filter Tuning Control Register + FTN_CTRL_FTN_START = 0x80 // Start Calibration Loop of Filter Tuning Network + + // PLL_CF: Transceiver Center Frequency Calibration Control Register + PLL_CF_PLL_CF_START = 0x80 // Start Center Frequency Calibration + + // PLL_DCU: Transceiver Delay Cell Calibration Control Register + PLL_DCU_PLL_DCU_START = 0x80 // Start Delay Cell Calibration + + // PART_NUM: Device Identification Register (Part Number) + PART_NUM_PART_NUM = 0xff // Part Number + + // VERSION_NUM: Device Identification Register (Version Number) + VERSION_NUM_VERSION_NUM = 0xff // Version Number + + // MAN_ID_0: Device Identification Register (Manufacture ID Low Byte) + MAN_ID_0_MAN_ID_07 = 0x80 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_06 = 0x40 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_05 = 0x20 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_04 = 0x10 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_03 = 0x8 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_02 = 0x4 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_01 = 0x2 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_00 = 0x1 // Manufacturer ID (Low Byte) + + // MAN_ID_1: Device Identification Register (Manufacture ID High Byte) + MAN_ID_1_MAN_ID_ = 0xff // Manufacturer ID (High Byte) + + // SHORT_ADDR_0: Transceiver MAC Short Address Register (Low Byte) + SHORT_ADDR_0_SHORT_ADDR_07 = 0x80 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_06 = 0x40 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_05 = 0x20 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_04 = 0x10 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_03 = 0x8 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_02 = 0x4 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_01 = 0x2 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_00 = 0x1 // MAC Short Address + + // SHORT_ADDR_1: Transceiver MAC Short Address Register (High Byte) + SHORT_ADDR_1_SHORT_ADDR_ = 0xff // MAC Short Address + + // PAN_ID_0: Transceiver Personal Area Network ID Register (Low Byte) + PAN_ID_0_PAN_ID_07 = 0x80 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_06 = 0x40 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_05 = 0x20 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_04 = 0x10 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_03 = 0x8 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_02 = 0x4 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_01 = 0x2 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_00 = 0x1 // MAC Personal Area Network ID + + // PAN_ID_1: Transceiver Personal Area Network ID Register (High Byte) + PAN_ID_1_PAN_ID_ = 0xff // MAC Personal Area Network ID + + // IEEE_ADDR_0: Transceiver MAC IEEE Address Register 0 + IEEE_ADDR_0_IEEE_ADDR_07 = 0x80 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_06 = 0x40 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_05 = 0x20 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_04 = 0x10 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_03 = 0x8 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_02 = 0x4 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_01 = 0x2 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_00 = 0x1 // MAC IEEE Address + + // IEEE_ADDR_1: Transceiver MAC IEEE Address Register 1 + IEEE_ADDR_1_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // IEEE_ADDR_2: Transceiver MAC IEEE Address Register 2 + IEEE_ADDR_2_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // IEEE_ADDR_3: Transceiver MAC IEEE Address Register 3 + IEEE_ADDR_3_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // IEEE_ADDR_4: Transceiver MAC IEEE Address Register 4 + IEEE_ADDR_4_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // IEEE_ADDR_5: Transceiver MAC IEEE Address Register 5 + IEEE_ADDR_5_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // IEEE_ADDR_6: Transceiver MAC IEEE Address Register 6 + IEEE_ADDR_6_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // IEEE_ADDR_7: Transceiver MAC IEEE Address Register 7 + IEEE_ADDR_7_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // XAH_CTRL_0: Transceiver Extended Operating Mode Control Register + XAH_CTRL_0_MAX_FRAME_RETRIES = 0xf0 // Maximum Number of Frame Re-transmission Attempts + XAH_CTRL_0_MAX_CSMA_RETRIES = 0xe // Maximum Number of CSMA-CA Procedure Repetition Attempts + XAH_CTRL_0_SLOTTED_OPERATION = 0x1 // Set Slotted Acknowledgment + + // CSMA_SEED_0: Transceiver CSMA-CA Random Number Generator Seed Register + CSMA_SEED_0_CSMA_SEED_07 = 0x80 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_06 = 0x40 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_05 = 0x20 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_04 = 0x10 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_03 = 0x8 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_02 = 0x4 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_01 = 0x2 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_00 = 0x1 // Seed Value for CSMA Random Number Generator + + // CSMA_SEED_1: Transceiver Acknowledgment Frame Control Register 2 + CSMA_SEED_1_AACK_FVN_MODE = 0xc0 // Acknowledgment Frame Filter Mode + CSMA_SEED_1_AACK_SET_PD = 0x20 // Set Frame Pending Sub-field + CSMA_SEED_1_AACK_DIS_ACK = 0x10 // Disable Acknowledgment Frame Transmission + CSMA_SEED_1_AACK_I_AM_COORD = 0x8 // Set Personal Area Network Coordinator + CSMA_SEED_1_CSMA_SEED_1 = 0x7 // Seed Value for CSMA Random Number Generator + + // CSMA_BE: Transceiver CSMA-CA Back-off Exponent Control Register + CSMA_BE_MAX_BE = 0xf0 // Maximum Back-off Exponent + CSMA_BE_MIN_BE = 0xf // Minimum Back-off Exponent + + // TST_CTRL_DIGI: Transceiver Digital Test Control Register + TST_CTRL_DIGI_TST_CTRL_DIG = 0xf // Digital Test Controller Register + + // TST_RX_LENGTH: Transceiver Received Frame Length Register + TST_RX_LENGTH_RX_LENGTH = 0xff // Received Frame Length +) + +// Bitfields for SYMCNT: MAC Symbol Counter +const ( + // SCTSTRHH: Symbol Counter Transmit Frame Timestamp Register HH-Byte + SCTSTRHH_SCTSTRHH = 0xff // Symbol Counter Transmit Frame Timestamp Register HH-Byte + + // SCTSTRHL: Symbol Counter Transmit Frame Timestamp Register HL-Byte + SCTSTRHL_SCTSTRHL = 0xff // Symbol Counter Transmit Frame Timestamp Register HL-Byte + + // SCTSTRLH: Symbol Counter Transmit Frame Timestamp Register LH-Byte + SCTSTRLH_SCTSTRLH = 0xff // Symbol Counter Transmit Frame Timestamp Register LH-Byte + + // SCTSTRLL: Symbol Counter Transmit Frame Timestamp Register LL-Byte + SCTSTRLL_SCTSTRLL = 0xff // Symbol Counter Transmit Frame Timestamp Register LL-Byte + + // SCOCR1HH: Symbol Counter Output Compare Register 1 HH-Byte + SCOCR1HH_SCOCR1HH = 0xff // Symbol Counter Output Compare Register 1 HH-Byte + + // SCOCR1HL: Symbol Counter Output Compare Register 1 HL-Byte + SCOCR1HL_SCOCR1HL = 0xff // Symbol Counter Output Compare Register 1 HL-Byte + + // SCOCR1LH: Symbol Counter Output Compare Register 1 LH-Byte + SCOCR1LH_SCOCR1LH = 0xff // Symbol Counter Output Compare Register 1 LH-Byte + + // SCOCR1LL: Symbol Counter Output Compare Register 1 LL-Byte + SCOCR1LL_SCOCR1LL = 0xff // Symbol Counter Output Compare Register 1 LL-Byte + + // SCOCR2HH: Symbol Counter Output Compare Register 2 HH-Byte + SCOCR2HH_SCOCR2HH = 0xff // Symbol Counter Output Compare Register 2 HH-Byte + + // SCOCR2HL: Symbol Counter Output Compare Register 2 HL-Byte + SCOCR2HL_SCOCR2HL = 0xff // Symbol Counter Output Compare Register 2 HL-Byte + + // SCOCR2LH: Symbol Counter Output Compare Register 2 LH-Byte + SCOCR2LH_SCOCR2LH = 0xff // Symbol Counter Output Compare Register 2 LH-Byte + + // SCOCR2LL: Symbol Counter Output Compare Register 2 LL-Byte + SCOCR2LL_SCOCR2LL = 0xff // Symbol Counter Output Compare Register 2 LL-Byte + + // SCOCR3HH: Symbol Counter Output Compare Register 3 HH-Byte + SCOCR3HH_SCOCR3HH = 0xff // Symbol Counter Output Compare Register 3 HH-Byte + + // SCOCR3HL: Symbol Counter Output Compare Register 3 HL-Byte + SCOCR3HL_SCOCR3HL = 0xff // Symbol Counter Output Compare Register 3 HL-Byte + + // SCOCR3LH: Symbol Counter Output Compare Register 3 LH-Byte + SCOCR3LH_SCOCR3LH = 0xff // Symbol Counter Output Compare Register 3 LH-Byte + + // SCOCR3LL: Symbol Counter Output Compare Register 3 LL-Byte + SCOCR3LL_SCOCR3LL = 0xff // Symbol Counter Output Compare Register 3 LL-Byte + + // SCTSRHH: Symbol Counter Frame Timestamp Register HH-Byte + SCTSRHH_SCTSRHH = 0xff // Symbol Counter Frame Timestamp Register HH-Byte + + // SCTSRHL: Symbol Counter Frame Timestamp Register HL-Byte + SCTSRHL_SCTSRHL = 0xff // Symbol Counter Frame Timestamp Register HL-Byte + + // SCTSRLH: Symbol Counter Frame Timestamp Register LH-Byte + SCTSRLH_SCTSRLH = 0xff // Symbol Counter Frame Timestamp Register LH-Byte + + // SCTSRLL: Symbol Counter Frame Timestamp Register LL-Byte + SCTSRLL_SCTSRLL = 0xff // Symbol Counter Frame Timestamp Register LL-Byte + + // SCBTSRHH: Symbol Counter Beacon Timestamp Register HH-Byte + SCBTSRHH_SCBTSRHH = 0xff // Symbol Counter Beacon Timestamp Register HH-Byte + + // SCBTSRHL: Symbol Counter Beacon Timestamp Register HL-Byte + SCBTSRHL_SCBTSRHL = 0xff // Symbol Counter Beacon Timestamp Register HL-Byte + + // SCBTSRLH: Symbol Counter Beacon Timestamp Register LH-Byte + SCBTSRLH_SCBTSRLH = 0xff // Symbol Counter Beacon Timestamp Register LH-Byte + + // SCBTSRLL: Symbol Counter Beacon Timestamp Register LL-Byte + SCBTSRLL_SCBTSRLL = 0xff // Symbol Counter Beacon Timestamp Register LL-Byte + + // SCCNTHH: Symbol Counter Register HH-Byte + SCCNTHH_SCCNTHH = 0xff // Symbol Counter Register HH-Byte + + // SCCNTHL: Symbol Counter Register HL-Byte + SCCNTHL_SCCNTHL = 0xff // Symbol Counter Register HL-Byte + + // SCCNTLH: Symbol Counter Register LH-Byte + SCCNTLH_SCCNTLH = 0xff // Symbol Counter Register LH-Byte + + // SCCNTLL: Symbol Counter Register LL-Byte + SCCNTLL_SCCNTLL = 0xff // Symbol Counter Register LL-Byte + + // SCIRQS: Symbol Counter Interrupt Status Register + SCIRQS_Res = 0xe0 // Reserved Bit + SCIRQS_IRQSBO = 0x10 // Backoff Slot Counter IRQ + SCIRQS_IRQSOF = 0x8 // Symbol Counter Overflow IRQ + SCIRQS_IRQSCP = 0x7 // Compare Unit 3 Compare Match IRQ + + // SCIRQM: Symbol Counter Interrupt Mask Register + SCIRQM_Res = 0xe0 // Reserved Bit + SCIRQM_IRQMBO = 0x10 // Backoff Slot Counter IRQ enable + SCIRQM_IRQMOF = 0x8 // Symbol Counter Overflow IRQ enable + SCIRQM_IRQMCP = 0x7 // Symbol Counter Compare Match 3 IRQ enable + + // SCSR: Symbol Counter Status Register + SCSR_Res = 0xfe // Reserved Bit + SCSR_SCBSY = 0x1 // Symbol Counter busy + + // SCCR1: Symbol Counter Control Register 1 + SCCR1_Res = 0xc0 // Reserved Bit + SCCR1_SCBTSM = 0x20 // Symbol Counter Beacon Timestamp Mask Register + SCCR1_SCCKDIV = 0x1c // Clock divider for synchronous clock source (16MHz Transceiver Clock) + SCCR1_SCEECLK = 0x2 // Enable External Clock Source on PG2 + SCCR1_SCENBO = 0x1 // Backoff Slot Counter enable + + // SCCR0: Symbol Counter Control Register 0 + SCCR0_SCRES = 0x80 // Symbol Counter Synchronization + SCCR0_SCMBTS = 0x40 // Manual Beacon Timestamp + SCCR0_SCEN = 0x20 // Symbol Counter enable + SCCR0_SCCKSEL = 0x10 // Symbol Counter Clock Source select + SCCR0_SCTSE = 0x8 // Symbol Counter Automatic Timestamping enable + SCCR0_SCCMP = 0x7 // Symbol Counter Compare Unit 3 Mode select + + // SCCSR: Symbol Counter Compare Source Register + SCCSR_Res = 0xc0 // Reserved Bit + SCCSR_SCCS3 = 0x30 // Symbol Counter Compare Source select register for Compare Unit 3 + SCCSR_SCCS2 = 0xc // Symbol Counter Compare Source select register for Compare Unit 2 + SCCSR_SCCS1 = 0x3 // Symbol Counter Compare Source select register for Compare Units + + // SCRSTRHH: Symbol Counter Received Frame Timestamp Register HH-Byte + SCRSTRHH_SCRSTRHH = 0xff // Symbol Counter Received Frame Timestamp Register HH-Byte + + // SCRSTRHL: Symbol Counter Received Frame Timestamp Register HL-Byte + SCRSTRHL_SCRSTRHL = 0xff // Symbol Counter Received Frame Timestamp Register HL-Byte + + // SCRSTRLH: Symbol Counter Received Frame Timestamp Register LH-Byte + SCRSTRLH_SCRSTRLH = 0xff // Symbol Counter Received Frame Timestamp Register LH-Byte + + // SCRSTRLL: Symbol Counter Received Frame Timestamp Register LL-Byte + SCRSTRLL_SCRSTRLL = 0xff // Symbol Counter Received Frame Timestamp Register LL-Byte +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Programming Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for JTAG: JTAG Interface +const ( + // OCDR: On-Chip Debug Register + OCDR_OCDR = 0xff // On-Chip Debug Register Data +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC3 = 0xc0 // External Interrupt 3 Sense Control Bit + EICRA_ISC2 = 0x30 // External Interrupt 2 Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt 1 Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt 0 Sense Control Bit + + // EICRB: External Interrupt Control Register B + EICRB_ISC7 = 0xc0 // External Interrupt 7 Sense Control Bit + EICRB_ISC6 = 0x30 // External Interrupt 6 Sense Control Bit + EICRB_ISC5 = 0xc // External Interrupt 5 Sense Control Bit + EICRB_ISC4 = 0x3 // External Interrupt 4 Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xff // External Interrupt Request Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xff // External Interrupt Flag + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Mask + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Enable Mask + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Mask + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_Res = 0xf8 // Reserved Bit + PCIFR_PCIF = 0x7 // Pin Change Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_Res = 0xf8 // Reserved Bit + PCICR_PCIE = 0x7 // Pin Change Interrupt Enables +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC Multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // ADC Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status Register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCSRC: The ADC Control and Status Register C + ADCSRC_ADTHT = 0xc0 // ADC Track-and-Hold Time + ADCSRC_Res0 = 0x20 // Reserved + ADCSRC_ADSUT = 0x1f // ADC Start-up Time + + // DIDR2: Digital Input Disable Register 2 + DIDR2_ADC15D = 0x80 // Reserved Bits + DIDR2_ADC14D = 0x40 // Reserved Bits + DIDR2_ADC13D = 0x20 // Reserved Bits + DIDR2_ADC12D = 0x10 // Reserved Bits + DIDR2_ADC11D = 0x8 // Reserved Bits + DIDR2_ADC10D = 0x4 // Reserved Bits + DIDR2_ADC9D = 0x2 // Reserved Bits + DIDR2_ADC8D = 0x1 // Reserved Bits + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // Disable ADC7:0 Digital Input + DIDR0_ADC6D = 0x40 // Disable ADC7:0 Digital Input + DIDR0_ADC5D = 0x20 // Disable ADC7:0 Digital Input + DIDR0_ADC4D = 0x10 // Disable ADC7:0 Digital Input + DIDR0_ADC3D = 0x8 // Disable ADC7:0 Digital Input + DIDR0_ADC2D = 0x4 // Disable ADC7:0 Digital Input + DIDR0_ADC1D = 0x2 // Disable ADC7:0 Digital Input + DIDR0_ADC0D = 0x1 // Disable ADC7:0 Digital Input +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write Section Read Enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_CAL = 0xff // Oscillator Calibration Tuning Value + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // RAMPZ: Extended Z-pointer Register for ELPM/SPM + RAMPZ_RAMPZ = 0x3 // Extended Z-Pointer Value + + // GPIOR2: General Purpose I/O Register 2 + GPIOR2_GPIOR = 0xff // General Purpose I/O Register 2 Value + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose I/O Register 1 Value + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR06 = 0x40 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR05 = 0x20 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR04 = 0x10 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR03 = 0x8 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR02 = 0x4 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR01 = 0x2 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR00 = 0x1 // General Purpose I/O Register 0 Value + + // PRR2: Power Reduction Register 2 + PRR2_PRRAM3 = 0x8 // Power Reduction SRAM3 + PRR2_PRRAM2 = 0x4 // Power Reduction SRAM2 + PRR2_PRRAM1 = 0x2 // Power Reduction SRAM1 + PRR2_PRRAM0 = 0x1 // Power Reduction SRAM0 + + // PRR1: Power Reduction Register 1 + PRR1_Res = 0x80 // Reserved Bit + PRR1_PRTRX24 = 0x40 // Power Reduction Transceiver + PRR1_PRTIM5 = 0x20 // Power Reduction Timer/Counter5 + PRR1_PRTIM4 = 0x10 // Power Reduction Timer/Counter4 + PRR1_PRTIM3 = 0x8 // Power Reduction Timer/Counter3 + PRR1_PRUSART1 = 0x1 // Power Reduction USART1 + + // PRR0: Power Reduction Register0 + PRR0_PRTWI = 0x80 // Power Reduction TWI + PRR0_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR0_PRPGA = 0x10 // Power Reduction PGA + PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR0_PRUSART0 = 0x2 // Power Reduction USART + PRR0_PRADC = 0x1 // Power Reduction ADC +) + +// Bitfields for FLASH: FLASH Controller +const ( + // NEMCR: Flash Extended-Mode Control-Register + NEMCR_ENEAM = 0x40 // Enable Extended Address Mode for Extra Rows + NEMCR_AEAM = 0x30 // Address for Extended Address Mode of Extra Rows + + // BGCR: Reference Voltage Calibration Register + BGCR_Res = 0x80 // Reserved Bit + BGCR_BGCAL_FINE = 0x78 // Fine Calibration Bits + BGCR_BGCAL = 0x7 // Coarse Calibration Bits +) + +// Bitfields for PWRCTRL: Power Controller +const ( + // TRXPR: Transceiver Pin Register + TRXPR_SLPTR = 0x2 // Multi-purpose Transceiver Control Bit + TRXPR_TRXRST = 0x1 // Force Transceiver Reset + + // DRTRAM0: Data Retention Configuration Register #0 + DRTRAM0_DRTSWOK = 0x20 // DRT Switch OK + DRTRAM0_ENDRT = 0x10 // Enable SRAM Data Retention + + // DRTRAM1: Data Retention Configuration Register #1 + DRTRAM1_DRTSWOK = 0x20 // DRT Switch OK + DRTRAM1_ENDRT = 0x10 // Enable SRAM Data Retention + + // DRTRAM2: Data Retention Configuration Register #2 + DRTRAM2_Res = 0x40 // Reserved Bit + DRTRAM2_DRTSWOK = 0x20 // DRT Switch OK + DRTRAM2_ENDRT = 0x10 // Enable SRAM Data Retention + + // DRTRAM3: Data Retention Configuration Register #3 + DRTRAM3_DRTSWOK = 0x20 // DRT Switch OK + DRTRAM3_ENDRT = 0x10 // Enable SRAM Data Retention + + // LLDRL: Low Leakage Voltage Regulator Data Register (Low-Byte) + LLDRL_LLDRL = 0xf // Low-Byte Data Register Bits + + // LLDRH: Low Leakage Voltage Regulator Data Register (High-Byte) + LLDRH_LLDRH = 0x1f // High-Byte Data Register Bits + + // LLCR: Low Leakage Voltage Regulator Control Register + LLCR_Res = 0xc0 // Reserved Bit + LLCR_LLDONE = 0x20 // Calibration Done + LLCR_LLCOMP = 0x10 // Comparator Output + LLCR_LLCAL = 0x8 // Calibration Active + LLCR_LLTCO = 0x4 // Temperature Coefficient of Current Source + LLCR_LLSHORT = 0x2 // Short Lower Calibration Circuit + LLCR_LLENCAL = 0x1 // Enable Automatic Calibration + + // DPDS0: Port Driver Strength Register 0 + DPDS0_PFDRV = 0xc0 // Driver Strength Port F + DPDS0_PEDRV = 0x30 // Driver Strength Port E + DPDS0_PDDRV = 0xc // Driver Strength Port D + DPDS0_PBDRV = 0x3 // Driver Strength Port B + + // DPDS1: Port Driver Strength Register 1 + DPDS1_PGDRV = 0x3 // Driver Strength Port G +) diff --git a/src/device/avr/atmega2564rfr2.ld b/src/device/avr/atmega2564rfr2.ld new file mode 100644 index 00000000..1e08f44a --- /dev/null +++ b/src/device/avr/atmega2564rfr2.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega2564RFR2.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x40000; +__ram_size = 0x8000; +__num_isrs = 71; diff --git a/src/device/avr/atmega256rfr2.go b/src/device/avr/atmega256rfr2.go new file mode 100644 index 00000000..b21dd5ba --- /dev/null +++ b/src/device/avr/atmega256rfr2.go @@ -0,0 +1,1769 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega256RFR2.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega256rfr2 + +// Device information for the ATmega256RFR2. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega256RFR2" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_INT3 = 4 // External Interrupt Request 3 + IRQ_INT4 = 5 // External Interrupt Request 4 + IRQ_INT5 = 6 // External Interrupt Request 5 + IRQ_INT6 = 7 // External Interrupt Request 6 + IRQ_INT7 = 8 // External Interrupt Request 7 + IRQ_PCINT0 = 9 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 10 // Pin Change Interrupt Request 1 + IRQ_PCINT2 = 11 // Pin Change Interrupt Request 2 + IRQ_WDT = 12 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 13 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 14 // Timer/Counter2 Compare Match B + IRQ_TIMER2_OVF = 15 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 16 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 17 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 18 // Timer/Counter1 Compare Match B + IRQ_TIMER1_COMPC = 19 // Timer/Counter1 Compare Match C + IRQ_TIMER1_OVF = 20 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 21 // Timer/Counter0 Compare Match A + IRQ_TIMER0_COMPB = 22 // Timer/Counter0 Compare Match B + IRQ_TIMER0_OVF = 23 // Timer/Counter0 Overflow + IRQ_SPI_STC = 24 // SPI Serial Transfer Complete + IRQ_USART0_RX = 25 // USART0, Rx Complete + IRQ_USART0_UDRE = 26 // USART0 Data register Empty + IRQ_USART0_TX = 27 // USART0, Tx Complete + IRQ_ANALOG_COMP = 28 // Analog Comparator + IRQ_ADC = 29 // ADC Conversion Complete + IRQ_EE_READY = 30 // EEPROM Ready + IRQ_TIMER3_CAPT = 31 // Timer/Counter3 Capture Event + IRQ_TIMER3_COMPA = 32 // Timer/Counter3 Compare Match A + IRQ_TIMER3_COMPB = 33 // Timer/Counter3 Compare Match B + IRQ_TIMER3_COMPC = 34 // Timer/Counter3 Compare Match C + IRQ_TIMER3_OVF = 35 // Timer/Counter3 Overflow + IRQ_USART1_RX = 36 // USART1, Rx Complete + IRQ_USART1_UDRE = 37 // USART1 Data register Empty + IRQ_USART1_TX = 38 // USART1, Tx Complete + IRQ_TWI = 39 // 2-wire Serial Interface + IRQ_SPM_READY = 40 // Store Program Memory Read + IRQ_TIMER4_CAPT = 41 // Timer/Counter4 Capture Event + IRQ_TIMER4_COMPA = 42 // Timer/Counter4 Compare Match A + IRQ_TIMER4_COMPB = 43 // Timer/Counter4 Compare Match B + IRQ_TIMER4_COMPC = 44 // Timer/Counter4 Compare Match C + IRQ_TIMER4_OVF = 45 // Timer/Counter4 Overflow + IRQ_TIMER5_CAPT = 46 // Timer/Counter5 Capture Event + IRQ_TIMER5_COMPA = 47 // Timer/Counter5 Compare Match A + IRQ_TIMER5_COMPB = 48 // Timer/Counter5 Compare Match B + IRQ_TIMER5_COMPC = 49 // Timer/Counter5 Compare Match C + IRQ_TIMER5_OVF = 50 // Timer/Counter5 Overflow + IRQ_TRX24_PLL_LOCK = 57 // TRX24 - PLL lock interrupt + IRQ_TRX24_PLL_UNLOCK = 58 // TRX24 - PLL unlock interrupt + IRQ_TRX24_RX_START = 59 // TRX24 - Receive start interrupt + IRQ_TRX24_RX_END = 60 // TRX24 - RX_END interrupt + IRQ_TRX24_CCA_ED_DONE = 61 // TRX24 - CCA/ED done interrupt + IRQ_TRX24_XAH_AMI = 62 // TRX24 - XAH - AMI + IRQ_TRX24_TX_END = 63 // TRX24 - TX_END interrupt + IRQ_TRX24_AWAKE = 64 // TRX24 AWAKE - tranceiver is reaching state TRX_OFF + IRQ_SCNT_CMP1 = 65 // Symbol counter - compare match 1 interrupt + IRQ_SCNT_CMP2 = 66 // Symbol counter - compare match 2 interrupt + IRQ_SCNT_CMP3 = 67 // Symbol counter - compare match 3 interrupt + IRQ_SCNT_OVFL = 68 // Symbol counter - overflow interrupt + IRQ_SCNT_BACKOFF = 69 // Symbol counter - backoff interrupt + IRQ_AES_READY = 70 // AES engine ready interrupt + IRQ_BAT_LOW = 71 // Battery monitor indicates supply voltage below threshold + IRQ_TRX24_TX_START = 72 // TRX24 TX start interrupt + IRQ_TRX24_AMI0 = 73 // Address match interrupt of address filter 0 + IRQ_TRX24_AMI1 = 74 // Address match interrupt of address filter 1 + IRQ_TRX24_AMI2 = 75 // Address match interrupt of address filter 2 + IRQ_TRX24_AMI3 = 76 // Address match interrupt of address filter 3 + IRQ_max = 76 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // USART + USART = struct { + UDR0 __reg + UBRR0L __reg + UBRR0H __reg + UDR1 __reg + UBRR1L __reg + UBRR1H __reg + }{ + UDR0: 0xc6, // USART0 I/O Data Register + UBRR0L: 0xc4, // USART0 Baud Rate Register Bytes + UBRR0H: 0xc4, // USART0 Baud Rate Register Bytes + UDR1: 0xce, // USART1 I/O Data Register + UBRR1L: 0xcc, // USART1 Baud Rate Register Bytes + UBRR1H: 0xcc, // USART1 Baud Rate Register Bytes + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate Register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data Register + TWAR: 0xba, // TWI (Slave) Address Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins Address + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins Address + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins Address + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins Address + PORTE: 0x2e, // Port E Data Register + DDRE: 0x2d, // Port E Data Direction Register + PINE: 0x2c, // Port E Input Pins Address + PORTF: 0x31, // Port F Data Register + DDRF: 0x30, // Port F Data Direction Register + PINF: 0x2f, // Port F Input Pins Address + PORTG: 0x34, // Port G Data Register + DDRG: 0x33, // Port G Data Direction Register + PING: 0x32, // Port G Input Pins Address + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register B + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 Register + TCCR0B: 0x45, // Timer/Counter0 Control Register B + TCCR0A: 0x44, // Timer/Counter0 Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag Register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR5A __reg + TCCR5B __reg + TCCR5C __reg + TCNT5L __reg + TCNT5H __reg + OCR5AL __reg + OCR5AH __reg + OCR5BL __reg + OCR5BH __reg + OCR5CL __reg + OCR5CH __reg + ICR5L __reg + ICR5H __reg + TIMSK5 __reg + TIFR5 __reg + TCCR4A __reg + TCCR4B __reg + TCCR4C __reg + TCNT4L __reg + TCNT4H __reg + OCR4AL __reg + OCR4AH __reg + OCR4BL __reg + OCR4BH __reg + OCR4CL __reg + OCR4CH __reg + ICR4L __reg + ICR4H __reg + TIMSK4 __reg + TIFR4 __reg + TCCR3A __reg + TCCR3B __reg + TCCR3C __reg + TCNT3L __reg + TCNT3H __reg + OCR3AL __reg + OCR3AH __reg + OCR3BL __reg + OCR3BH __reg + OCR3CL __reg + OCR3CH __reg + ICR3L __reg + ICR3H __reg + TIMSK3 __reg + TIFR3 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + OCR1CL __reg + OCR1CH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR5A: 0x120, // Timer/Counter5 Control Register A + TCCR5B: 0x121, // Timer/Counter5 Control Register B + TCCR5C: 0x122, // Timer/Counter5 Control Register C + TCNT5L: 0x124, // Timer/Counter5 Bytes + TCNT5H: 0x124, // Timer/Counter5 Bytes + OCR5AL: 0x128, // Timer/Counter5 Output Compare Register A Bytes + OCR5AH: 0x128, // Timer/Counter5 Output Compare Register A Bytes + OCR5BL: 0x12a, // Timer/Counter5 Output Compare Register B Bytes + OCR5BH: 0x12a, // Timer/Counter5 Output Compare Register B Bytes + OCR5CL: 0x12c, // Timer/Counter5 Output Compare Register C Bytes + OCR5CH: 0x12c, // Timer/Counter5 Output Compare Register C Bytes + ICR5L: 0x126, // Timer/Counter5 Input Capture Register Bytes + ICR5H: 0x126, // Timer/Counter5 Input Capture Register Bytes + TIMSK5: 0x73, // Timer/Counter5 Interrupt Mask Register + TIFR5: 0x3a, // Timer/Counter5 Interrupt Flag Register + TCCR4A: 0xa0, // Timer/Counter4 Control Register A + TCCR4B: 0xa1, // Timer/Counter4 Control Register B + TCCR4C: 0xa2, // Timer/Counter4 Control Register C + TCNT4L: 0xa4, // Timer/Counter4 Bytes + TCNT4H: 0xa4, // Timer/Counter4 Bytes + OCR4AL: 0xa8, // Timer/Counter4 Output Compare Register A Bytes + OCR4AH: 0xa8, // Timer/Counter4 Output Compare Register A Bytes + OCR4BL: 0xaa, // Timer/Counter4 Output Compare Register B Bytes + OCR4BH: 0xaa, // Timer/Counter4 Output Compare Register B Bytes + OCR4CL: 0xac, // Timer/Counter4 Output Compare Register C Bytes + OCR4CH: 0xac, // Timer/Counter4 Output Compare Register C Bytes + ICR4L: 0xa6, // Timer/Counter4 Input Capture Register Bytes + ICR4H: 0xa6, // Timer/Counter4 Input Capture Register Bytes + TIMSK4: 0x72, // Timer/Counter4 Interrupt Mask Register + TIFR4: 0x39, // Timer/Counter4 Interrupt Flag Register + TCCR3A: 0x90, // Timer/Counter3 Control Register A + TCCR3B: 0x91, // Timer/Counter3 Control Register B + TCCR3C: 0x92, // Timer/Counter3 Control Register C + TCNT3L: 0x94, // Timer/Counter3 Bytes + TCNT3H: 0x94, // Timer/Counter3 Bytes + OCR3AL: 0x98, // Timer/Counter3 Output Compare Register A Bytes + OCR3AH: 0x98, // Timer/Counter3 Output Compare Register A Bytes + OCR3BL: 0x9a, // Timer/Counter3 Output Compare Register B Bytes + OCR3BH: 0x9a, // Timer/Counter3 Output Compare Register B Bytes + OCR3CL: 0x9c, // Timer/Counter3 Output Compare Register C Bytes + OCR3CH: 0x9c, // Timer/Counter3 Output Compare Register C Bytes + ICR3L: 0x96, // Timer/Counter3 Input Capture Register Bytes + ICR3H: 0x96, // Timer/Counter3 Input Capture Register Bytes + TIMSK3: 0x71, // Timer/Counter3 Interrupt Mask Register + TIFR3: 0x38, // Timer/Counter3 Interrupt Flag Register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1CL: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + OCR1CH: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag Register + } + + // Low-Power 2.4 GHz Transceiver + TRX24 = struct { + PARCR __reg + MAFSA0L __reg + MAFSA0H __reg + MAFPA0L __reg + MAFPA0H __reg + MAFSA1L __reg + MAFSA1H __reg + MAFPA1L __reg + MAFPA1H __reg + MAFSA2L __reg + MAFSA2H __reg + MAFPA2L __reg + MAFPA2H __reg + MAFSA3L __reg + MAFSA3H __reg + MAFPA3L __reg + MAFPA3H __reg + MAFCR0 __reg + MAFCR1 __reg + AES_CTRL __reg + AES_STATUS __reg + AES_STATE __reg + AES_KEY __reg + TRX_STATUS __reg + TRX_STATE __reg + TRX_CTRL_0 __reg + TRX_CTRL_1 __reg + PHY_TX_PWR __reg + PHY_RSSI __reg + PHY_ED_LEVEL __reg + PHY_CC_CCA __reg + CCA_THRES __reg + RX_CTRL __reg + SFD_VALUE __reg + TRX_CTRL_2 __reg + ANT_DIV __reg + IRQ_MASK __reg + IRQ_STATUS __reg + IRQ_MASK1 __reg + IRQ_STATUS1 __reg + VREG_CTRL __reg + BATMON __reg + XOSC_CTRL __reg + CC_CTRL_0 __reg + CC_CTRL_1 __reg + RX_SYN __reg + TRX_RPC __reg + XAH_CTRL_1 __reg + FTN_CTRL __reg + PLL_CF __reg + PLL_DCU __reg + PART_NUM __reg + VERSION_NUM __reg + MAN_ID_0 __reg + MAN_ID_1 __reg + SHORT_ADDR_0 __reg + SHORT_ADDR_1 __reg + PAN_ID_0 __reg + PAN_ID_1 __reg + IEEE_ADDR_0 __reg + IEEE_ADDR_1 __reg + IEEE_ADDR_2 __reg + IEEE_ADDR_3 __reg + IEEE_ADDR_4 __reg + IEEE_ADDR_5 __reg + IEEE_ADDR_6 __reg + IEEE_ADDR_7 __reg + XAH_CTRL_0 __reg + CSMA_SEED_0 __reg + CSMA_SEED_1 __reg + CSMA_BE __reg + TST_CTRL_DIGI __reg + TST_RX_LENGTH __reg + TRXFBST __reg + TRXFBEND __reg + }{ + PARCR: 0x138, // Power Amplifier Ramp up/down Control Register + MAFSA0L: 0x10e, // Transceiver MAC Short Address Register for Frame Filter 0 (Low Byte) + MAFSA0H: 0x10f, // Transceiver MAC Short Address Register for Frame Filter 0 (High Byte) + MAFPA0L: 0x110, // Transceiver Personal Area Network ID Register for Frame Filter 0 (Low Byte) + MAFPA0H: 0x111, // Transceiver Personal Area Network ID Register for Frame Filter 0 (High Byte) + MAFSA1L: 0x112, // Transceiver MAC Short Address Register for Frame Filter 1 (Low Byte) + MAFSA1H: 0x113, // Transceiver MAC Short Address Register for Frame Filter 1 (High Byte) + MAFPA1L: 0x114, // Transceiver Personal Area Network ID Register for Frame Filter 1 (Low Byte) + MAFPA1H: 0x115, // Transceiver Personal Area Network ID Register for Frame Filter 1 (High Byte) + MAFSA2L: 0x116, // Transceiver MAC Short Address Register for Frame Filter 2 (Low Byte) + MAFSA2H: 0x117, // Transceiver MAC Short Address Register for Frame Filter 2 (High Byte) + MAFPA2L: 0x118, // Transceiver Personal Area Network ID Register for Frame Filter 2 (Low Byte) + MAFPA2H: 0x119, // Transceiver Personal Area Network ID Register for Frame Filter 2 (High Byte) + MAFSA3L: 0x11a, // Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte) + MAFSA3H: 0x11b, // Transceiver MAC Short Address Register for Frame Filter 3 (High Byte) + MAFPA3L: 0x11c, // Transceiver Personal Area Network ID Register for Frame Filter 3 (Low Byte) + MAFPA3H: 0x11d, // Transceiver Personal Area Network ID Register for Frame Filter 3 (High Byte) + MAFCR0: 0x10c, // Multiple Address Filter Configuration Register 0 + MAFCR1: 0x10d, // Multiple Address Filter Configuration Register 1 + AES_CTRL: 0x13c, // AES Control Register + AES_STATUS: 0x13d, // AES Status Register + AES_STATE: 0x13e, // AES Plain and Cipher Text Buffer Register + AES_KEY: 0x13f, // AES Encryption and Decryption Key Buffer Register + TRX_STATUS: 0x141, // Transceiver Status Register + TRX_STATE: 0x142, // Transceiver State Control Register + TRX_CTRL_0: 0x143, // Reserved + TRX_CTRL_1: 0x144, // Transceiver Control Register 1 + PHY_TX_PWR: 0x145, // Transceiver Transmit Power Control Register + PHY_RSSI: 0x146, // Receiver Signal Strength Indicator Register + PHY_ED_LEVEL: 0x147, // Transceiver Energy Detection Level Register + PHY_CC_CCA: 0x148, // Transceiver Clear Channel Assessment (CCA) Control Register + CCA_THRES: 0x149, // Transceiver CCA Threshold Setting Register + RX_CTRL: 0x14a, // Transceiver Receive Control Register + SFD_VALUE: 0x14b, // Start of Frame Delimiter Value Register + TRX_CTRL_2: 0x14c, // Transceiver Control Register 2 + ANT_DIV: 0x14d, // Antenna Diversity Control Register + IRQ_MASK: 0x14e, // Transceiver Interrupt Enable Register + IRQ_STATUS: 0x14f, // Transceiver Interrupt Status Register + IRQ_MASK1: 0xbe, // Transceiver Interrupt Enable Register 1 + IRQ_STATUS1: 0xbf, // Transceiver Interrupt Status Register 1 + VREG_CTRL: 0x150, // Voltage Regulator Control and Status Register + BATMON: 0x151, // Battery Monitor Control and Status Register + XOSC_CTRL: 0x152, // Crystal Oscillator Control Register + CC_CTRL_0: 0x153, // Channel Control Register 0 + CC_CTRL_1: 0x154, // Channel Control Register 1 + RX_SYN: 0x155, // Transceiver Receiver Sensitivity Control Register + TRX_RPC: 0x156, // Transceiver Reduced Power Consumption Control + XAH_CTRL_1: 0x157, // Transceiver Acknowledgment Frame Control Register 1 + FTN_CTRL: 0x158, // Transceiver Filter Tuning Control Register + PLL_CF: 0x15a, // Transceiver Center Frequency Calibration Control Register + PLL_DCU: 0x15b, // Transceiver Delay Cell Calibration Control Register + PART_NUM: 0x15c, // Device Identification Register (Part Number) + VERSION_NUM: 0x15d, // Device Identification Register (Version Number) + MAN_ID_0: 0x15e, // Device Identification Register (Manufacture ID Low Byte) + MAN_ID_1: 0x15f, // Device Identification Register (Manufacture ID High Byte) + SHORT_ADDR_0: 0x160, // Transceiver MAC Short Address Register (Low Byte) + SHORT_ADDR_1: 0x161, // Transceiver MAC Short Address Register (High Byte) + PAN_ID_0: 0x162, // Transceiver Personal Area Network ID Register (Low Byte) + PAN_ID_1: 0x163, // Transceiver Personal Area Network ID Register (High Byte) + IEEE_ADDR_0: 0x164, // Transceiver MAC IEEE Address Register 0 + IEEE_ADDR_1: 0x165, // Transceiver MAC IEEE Address Register 1 + IEEE_ADDR_2: 0x166, // Transceiver MAC IEEE Address Register 2 + IEEE_ADDR_3: 0x167, // Transceiver MAC IEEE Address Register 3 + IEEE_ADDR_4: 0x168, // Transceiver MAC IEEE Address Register 4 + IEEE_ADDR_5: 0x169, // Transceiver MAC IEEE Address Register 5 + IEEE_ADDR_6: 0x16a, // Transceiver MAC IEEE Address Register 6 + IEEE_ADDR_7: 0x16b, // Transceiver MAC IEEE Address Register 7 + XAH_CTRL_0: 0x16c, // Transceiver Extended Operating Mode Control Register + CSMA_SEED_0: 0x16d, // Transceiver CSMA-CA Random Number Generator Seed Register + CSMA_SEED_1: 0x16e, // Transceiver Acknowledgment Frame Control Register 2 + CSMA_BE: 0x16f, // Transceiver CSMA-CA Back-off Exponent Control Register + TST_CTRL_DIGI: 0x176, // Transceiver Digital Test Control Register + TST_RX_LENGTH: 0x17b, // Transceiver Received Frame Length Register + TRXFBST: 0x180, // Start of frame buffer + TRXFBEND: 0x1ff, // End of frame buffer + } + + // MAC Symbol Counter + SYMCNT = struct { + SCTSTRHH __reg + SCTSTRHL __reg + SCTSTRLH __reg + SCTSTRLL __reg + SCOCR1HH __reg + SCOCR1HL __reg + SCOCR1LH __reg + SCOCR1LL __reg + SCOCR2HH __reg + SCOCR2HL __reg + SCOCR2LH __reg + SCOCR2LL __reg + SCOCR3HH __reg + SCOCR3HL __reg + SCOCR3LH __reg + SCOCR3LL __reg + SCTSRHH __reg + SCTSRHL __reg + SCTSRLH __reg + SCTSRLL __reg + SCBTSRHH __reg + SCBTSRHL __reg + SCBTSRLH __reg + SCBTSRLL __reg + SCCNTHH __reg + SCCNTHL __reg + SCCNTLH __reg + SCCNTLL __reg + SCIRQS __reg + SCIRQM __reg + SCSR __reg + SCCR1 __reg + SCCR0 __reg + SCCSR __reg + SCRSTRHH __reg + SCRSTRHL __reg + SCRSTRLH __reg + SCRSTRLL __reg + }{ + SCTSTRHH: 0xfc, // Symbol Counter Transmit Frame Timestamp Register HH-Byte + SCTSTRHL: 0xfb, // Symbol Counter Transmit Frame Timestamp Register HL-Byte + SCTSTRLH: 0xfa, // Symbol Counter Transmit Frame Timestamp Register LH-Byte + SCTSTRLL: 0xf9, // Symbol Counter Transmit Frame Timestamp Register LL-Byte + SCOCR1HH: 0xf8, // Symbol Counter Output Compare Register 1 HH-Byte + SCOCR1HL: 0xf7, // Symbol Counter Output Compare Register 1 HL-Byte + SCOCR1LH: 0xf6, // Symbol Counter Output Compare Register 1 LH-Byte + SCOCR1LL: 0xf5, // Symbol Counter Output Compare Register 1 LL-Byte + SCOCR2HH: 0xf4, // Symbol Counter Output Compare Register 2 HH-Byte + SCOCR2HL: 0xf3, // Symbol Counter Output Compare Register 2 HL-Byte + SCOCR2LH: 0xf2, // Symbol Counter Output Compare Register 2 LH-Byte + SCOCR2LL: 0xf1, // Symbol Counter Output Compare Register 2 LL-Byte + SCOCR3HH: 0xf0, // Symbol Counter Output Compare Register 3 HH-Byte + SCOCR3HL: 0xef, // Symbol Counter Output Compare Register 3 HL-Byte + SCOCR3LH: 0xee, // Symbol Counter Output Compare Register 3 LH-Byte + SCOCR3LL: 0xed, // Symbol Counter Output Compare Register 3 LL-Byte + SCTSRHH: 0xec, // Symbol Counter Frame Timestamp Register HH-Byte + SCTSRHL: 0xeb, // Symbol Counter Frame Timestamp Register HL-Byte + SCTSRLH: 0xea, // Symbol Counter Frame Timestamp Register LH-Byte + SCTSRLL: 0xe9, // Symbol Counter Frame Timestamp Register LL-Byte + SCBTSRHH: 0xe8, // Symbol Counter Beacon Timestamp Register HH-Byte + SCBTSRHL: 0xe7, // Symbol Counter Beacon Timestamp Register HL-Byte + SCBTSRLH: 0xe6, // Symbol Counter Beacon Timestamp Register LH-Byte + SCBTSRLL: 0xe5, // Symbol Counter Beacon Timestamp Register LL-Byte + SCCNTHH: 0xe4, // Symbol Counter Register HH-Byte + SCCNTHL: 0xe3, // Symbol Counter Register HL-Byte + SCCNTLH: 0xe2, // Symbol Counter Register LH-Byte + SCCNTLL: 0xe1, // Symbol Counter Register LL-Byte + SCIRQS: 0xe0, // Symbol Counter Interrupt Status Register + SCIRQM: 0xdf, // Symbol Counter Interrupt Mask Register + SCSR: 0xde, // Symbol Counter Status Register + SCCR1: 0xdd, // Symbol Counter Control Register 1 + SCCR0: 0xdc, // Symbol Counter Control Register 0 + SCCSR: 0xdb, // Symbol Counter Compare Source Register + SCRSTRHH: 0xda, // Symbol Counter Received Frame Timestamp Register HH-Byte + SCRSTRHL: 0xd9, // Symbol Counter Received Frame Timestamp Register HL-Byte + SCRSTRLH: 0xd8, // Symbol Counter Received Frame Timestamp Register LH-Byte + SCRSTRLL: 0xd7, // Symbol Counter Received Frame Timestamp Register LL-Byte + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Bytes + EEARH: 0x41, // EEPROM Address Register Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EICRB __reg + EIMSK __reg + EIFR __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + PCICR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EICRB: 0x6a, // External Interrupt Control Register B + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + ADCSRC __reg + DIDR2 __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC Multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // The ADC Control and Status Register A + ADCSRC: 0x77, // The ADC Control and Status Register C + DIDR2: 0x7d, // Digital Input Disable Register 2 + DIDR0: 0x7e, // Digital Input Disable Register 0 + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + EIND __reg + RAMPZ __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PRR2 __reg + PRR1 __reg + PRR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + SMCR: 0x53, // Sleep Mode Control Register + EIND: 0x5c, // Extended Indirect Register + RAMPZ: 0x5b, // Extended Z-pointer Register for ELPM/SPM + GPIOR2: 0x4b, // General Purpose I/O Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PRR2: 0x63, // Power Reduction Register 2 + PRR1: 0x65, // Power Reduction Register 1 + PRR0: 0x64, // Power Reduction Register0 + } + + // FLASH Controller + FLASH = struct { + NEMCR __reg + BGCR __reg + }{ + NEMCR: 0x75, // Flash Extended-Mode Control-Register + BGCR: 0x67, // Reference Voltage Calibration Register + } + + // Power Controller + PWRCTRL = struct { + TRXPR __reg + DRTRAM0 __reg + DRTRAM1 __reg + DRTRAM2 __reg + DRTRAM3 __reg + LLDRL __reg + LLDRH __reg + LLCR __reg + DPDS0 __reg + DPDS1 __reg + }{ + TRXPR: 0x139, // Transceiver Pin Register + DRTRAM0: 0x135, // Data Retention Configuration Register #0 + DRTRAM1: 0x134, // Data Retention Configuration Register #1 + DRTRAM2: 0x133, // Data Retention Configuration Register #2 + DRTRAM3: 0x132, // Data Retention Configuration Register #3 + LLDRL: 0x130, // Low Leakage Voltage Regulator Data Register (Low-Byte) + LLDRH: 0x131, // Low Leakage Voltage Regulator Data Register (High-Byte) + LLCR: 0x12f, // Low Leakage Voltage Regulator Control Register + DPDS0: 0x136, // Port Driver Strength Register 0 + DPDS1: 0x137, // Port Driver Strength Register 1 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_CKSEL_SUT = 0x3f // Select Clock Source : Start-up time +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe // TWI Address Mask + TWAMR_Res = 0x1 // Reserved Bit + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI START Condition Bit + TWCR_TWSTO = 0x10 // TWI STOP Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collision Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_Res = 0x2 // Reserved Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_Res = 0x4 // Reserved Bit + TWSR_TWPS = 0x3 // TWI Prescaler Bits + + // TWAR: TWI (Slave) Address Register + TWAR_TWA = 0xfe // TWI (Slave) Address + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Select 1 and 0 + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter0 Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_Res = 0x30 // Reserved Bit + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter0 Control Register A + TCCR0A_COM0A = 0xc0 // Compare Match Output A Mode + TCCR0A_COM0B = 0x30 // Compare Match Output B Mode + TCCR0A_Res = 0xc // Reserved Bit + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag Register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare B Match Flag + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare A Match Flag + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_Res = 0xf8 // Reserved Bit + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_Res = 0xf8 // Reserved Bit + TIFR2_OCF2B = 0x4 // Output Compare Flag 2 B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2 A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Match Output A Mode + TCCR2A_COM2B = 0x30 // Compare Match Output B Mode + TCCR2A_WGM2 = 0x3 // Waveform Generation Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select + + // ASSR: Asynchronous Status Register + ASSR_EXCLKAMR = 0x80 // Enable External Clock Input for AMR + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Timer/Counter2 Asynchronous Mode + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Timer/Counter2 Output Compare Register A Update Busy + ASSR_OCR2BUB = 0x4 // Timer/Counter2 Output Compare Register B Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter2 Control Register A Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter2 Control Register B Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR5A: Timer/Counter5 Control Register A + TCCR5A_COM5A = 0xc0 // Compare Output Mode for Channel A + TCCR5A_COM5B = 0x30 // Compare Output Mode for Channel B + TCCR5A_COM5C = 0xc // Compare Output Mode for Channel C + TCCR5A_WGM5 = 0x3 // Waveform Generation Mode + + // TCCR5B: Timer/Counter5 Control Register B + TCCR5B_ICNC5 = 0x80 // Input Capture 5 Noise Canceller + TCCR5B_ICES5 = 0x40 // Input Capture 5 Edge Select + TCCR5B_Res = 0x20 // Reserved Bit + TCCR5B_WGM5 = 0x18 // Waveform Generation Mode + TCCR5B_CS5 = 0x7 // Clock Select + + // TCCR5C: Timer/Counter5 Control Register C + TCCR5C_FOC5A = 0x80 // Force Output Compare for Channel A + TCCR5C_FOC5B = 0x40 // Force Output Compare for Channel B + TCCR5C_FOC5C = 0x20 // Force Output Compare for Channel C + + // TIMSK5: Timer/Counter5 Interrupt Mask Register + TIMSK5_ICIE5 = 0x20 // Timer/Counter5 Input Capture Interrupt Enable + TIMSK5_OCIE5C = 0x8 // Timer/Counter5 Output Compare C Match Interrupt Enable + TIMSK5_OCIE5B = 0x4 // Timer/Counter5 Output Compare B Match Interrupt Enable + TIMSK5_OCIE5A = 0x2 // Timer/Counter5 Output Compare A Match Interrupt Enable + TIMSK5_TOIE5 = 0x1 // Timer/Counter5 Overflow Interrupt Enable + + // TIFR5: Timer/Counter5 Interrupt Flag Register + TIFR5_ICF5 = 0x20 // Timer/Counter5 Input Capture Flag + TIFR5_OCF5C = 0x8 // Timer/Counter5 Output Compare C Match Flag + TIFR5_OCF5B = 0x4 // Timer/Counter5 Output Compare B Match Flag + TIFR5_OCF5A = 0x2 // Timer/Counter5 Output Compare A Match Flag + TIFR5_TOV5 = 0x1 // Timer/Counter5 Overflow Flag + + // TCCR4A: Timer/Counter4 Control Register A + TCCR4A_COM4A = 0xc0 // Compare Output Mode for Channel A + TCCR4A_COM4B = 0x30 // Compare Output Mode for Channel B + TCCR4A_COM4C = 0xc // Compare Output Mode for Channel C + TCCR4A_WGM4 = 0x3 // Waveform Generation Mode + + // TCCR4B: Timer/Counter4 Control Register B + TCCR4B_ICNC4 = 0x80 // Input Capture 4 Noise Canceller + TCCR4B_ICES4 = 0x40 // Input Capture 4 Edge Select + TCCR4B_Res = 0x20 // Reserved Bit + TCCR4B_WGM4 = 0x18 // Waveform Generation Mode + TCCR4B_CS4 = 0x7 // Clock Select + + // TCCR4C: Timer/Counter4 Control Register C + TCCR4C_FOC4A = 0x80 // Force Output Compare for Channel A + TCCR4C_FOC4B = 0x40 // Force Output Compare for Channel B + TCCR4C_FOC4C = 0x20 // Force Output Compare for Channel C + + // TIMSK4: Timer/Counter4 Interrupt Mask Register + TIMSK4_ICIE4 = 0x20 // Timer/Counter4 Input Capture Interrupt Enable + TIMSK4_OCIE4C = 0x8 // Timer/Counter4 Output Compare C Match Interrupt Enable + TIMSK4_OCIE4B = 0x4 // Timer/Counter4 Output Compare B Match Interrupt Enable + TIMSK4_OCIE4A = 0x2 // Timer/Counter4 Output Compare A Match Interrupt Enable + TIMSK4_TOIE4 = 0x1 // Timer/Counter4 Overflow Interrupt Enable + + // TIFR4: Timer/Counter4 Interrupt Flag Register + TIFR4_ICF4 = 0x20 // Timer/Counter4 Input Capture Flag + TIFR4_OCF4C = 0x8 // Timer/Counter4 Output Compare C Match Flag + TIFR4_OCF4B = 0x4 // Timer/Counter4 Output Compare B Match Flag + TIFR4_OCF4A = 0x2 // Timer/Counter4 Output Compare A Match Flag + TIFR4_TOV4 = 0x1 // Timer/Counter4 Overflow Flag + + // TCCR3A: Timer/Counter3 Control Register A + TCCR3A_COM3A = 0xc0 // Compare Output Mode for Channel A + TCCR3A_COM3B = 0x30 // Compare Output Mode for Channel B + TCCR3A_COM3C = 0xc // Compare Output Mode for Channel C + TCCR3A_WGM3 = 0x3 // Waveform Generation Mode + + // TCCR3B: Timer/Counter3 Control Register B + TCCR3B_ICNC3 = 0x80 // Input Capture 3 Noise Canceller + TCCR3B_ICES3 = 0x40 // Input Capture 3 Edge Select + TCCR3B_Res = 0x20 // Reserved Bit + TCCR3B_WGM3 = 0x18 // Waveform Generation Mode + TCCR3B_CS3 = 0x7 // Clock Select + + // TCCR3C: Timer/Counter3 Control Register C + TCCR3C_FOC3A = 0x80 // Force Output Compare for Channel A + TCCR3C_FOC3B = 0x40 // Force Output Compare for Channel B + TCCR3C_FOC3C = 0x20 // Force Output Compare for Channel C + + // TIMSK3: Timer/Counter3 Interrupt Mask Register + TIMSK3_ICIE3 = 0x20 // Timer/Counter3 Input Capture Interrupt Enable + TIMSK3_OCIE3C = 0x8 // Timer/Counter3 Output Compare C Match Interrupt Enable + TIMSK3_OCIE3B = 0x4 // Timer/Counter3 Output Compare B Match Interrupt Enable + TIMSK3_OCIE3A = 0x2 // Timer/Counter3 Output Compare A Match Interrupt Enable + TIMSK3_TOIE3 = 0x1 // Timer/Counter3 Overflow Interrupt Enable + + // TIFR3: Timer/Counter3 Interrupt Flag Register + TIFR3_ICF3 = 0x20 // Timer/Counter3 Input Capture Flag + TIFR3_OCF3C = 0x8 // Timer/Counter3 Output Compare C Match Flag + TIFR3_OCF3B = 0x4 // Timer/Counter3 Output Compare B Match Flag + TIFR3_OCF3A = 0x2 // Timer/Counter3 Output Compare A Match Flag + TIFR3_TOV3 = 0x1 // Timer/Counter3 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode for Channel A + TCCR1A_COM1B = 0x30 // Compare Output Mode for Channel B + TCCR1A_COM1C = 0xc // Compare Output Mode for Channel C + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceller + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_Res = 0x20 // Reserved Bit + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Clock Select + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare for Channel A + TCCR1C_FOC1B = 0x40 // Force Output Compare for Channel B + TCCR1C_FOC1C = 0x20 // Force Output Compare for Channel C + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1C = 0x8 // Timer/Counter1 Output Compare C Match Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag Register + TIFR1_ICF1 = 0x20 // Timer/Counter1 Input Capture Flag + TIFR1_OCF1C = 0x8 // Timer/Counter1 Output Compare C Match Flag + TIFR1_OCF1B = 0x4 // Timer/Counter1 Output Compare B Match Flag + TIFR1_OCF1A = 0x2 // Timer/Counter1 Output Compare A Match Flag + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for TRX24: Low-Power 2.4 GHz Transceiver +const ( + // PARCR: Power Amplifier Ramp up/down Control Register + PARCR_PALTD = 0xe0 // ext. PA Ramp Down Lead Time + PARCR_PALTU = 0x1c // ext. PA Ramp Up Lead Time + PARCR_PARDFI = 0x2 // Power Amplifier Ramp Down Frequency Inversion + PARCR_PARUFI = 0x1 // Power Amplifier Ramp Up Frequency Inversion + + // MAFSA0L: Transceiver MAC Short Address Register for Frame Filter 0 (Low Byte) + MAFSA0L_MAFSA0L = 0xff // MAC Short Address low Byte for Frame Filter 0 + + // MAFSA0H: Transceiver MAC Short Address Register for Frame Filter 0 (High Byte) + MAFSA0H_MAFSA0H = 0xff // MAC Short Address high Byte for Frame Filter 0 + + // MAFPA0L: Transceiver Personal Area Network ID Register for Frame Filter 0 (Low Byte) + MAFPA0L_MAFPA0L = 0xff // MAC Personal Area Network ID low Byte for Frame Filter 0 + + // MAFPA0H: Transceiver Personal Area Network ID Register for Frame Filter 0 (High Byte) + MAFPA0H_MAFPA0H = 0xff // MAC Personal Area Network ID high Byte for Frame Filter 0 + + // MAFSA1L: Transceiver MAC Short Address Register for Frame Filter 1 (Low Byte) + MAFSA1L_MAFSA1L = 0xff // MAC Short Address low Byte for Frame Filter 1 + + // MAFSA1H: Transceiver MAC Short Address Register for Frame Filter 1 (High Byte) + MAFSA1H_MAFSA1H = 0xff // MAC Short Address high Byte for Frame Filter 1 + + // MAFPA1L: Transceiver Personal Area Network ID Register for Frame Filter 1 (Low Byte) + MAFPA1L_MAFPA1L = 0xff // MAC Personal Area Network ID low Byte for Frame Filter 1 + + // MAFPA1H: Transceiver Personal Area Network ID Register for Frame Filter 1 (High Byte) + MAFPA1H_MAFPA1H = 0xff // MAC Personal Area Network ID high Byte for Frame Filter 1 + + // MAFSA2L: Transceiver MAC Short Address Register for Frame Filter 2 (Low Byte) + MAFSA2L_MAFSA2L = 0xff // MAC Short Address low Byte for Frame Filter 2 + + // MAFSA2H: Transceiver MAC Short Address Register for Frame Filter 2 (High Byte) + MAFSA2H_MAFSA2H = 0xff // MAC Short Address high Byte for Frame Filter 2 + + // MAFPA2L: Transceiver Personal Area Network ID Register for Frame Filter 2 (Low Byte) + MAFPA2L_MAFPA2L = 0xff // MAC Personal Area Network ID low Byte for Frame Filter 2 + + // MAFPA2H: Transceiver Personal Area Network ID Register for Frame Filter 2 (High Byte) + MAFPA2H_MAFPA2H = 0xff // MAC Personal Area Network ID high Byte for Frame Filter 2 + + // MAFSA3L: Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte) + MAFSA3L_MAFSA3L = 0xff // MAC Short Address low Byte for Frame Filter 3 + + // MAFSA3H: Transceiver MAC Short Address Register for Frame Filter 3 (High Byte) + MAFSA3H_MAFSA3H = 0xff // MAC Short Address high Byte for Frame Filter 3 + + // MAFPA3L: Transceiver Personal Area Network ID Register for Frame Filter 3 (Low Byte) + MAFPA3L_MAFPA3L = 0xff // MAC Personal Area Network ID low Byte for Frame Filter 3 + + // MAFPA3H: Transceiver Personal Area Network ID Register for Frame Filter 3 (High Byte) + MAFPA3H_MAFPA3H = 0xff // MAC Personal Area Network ID high Byte for Frame Filter 3 + + // MAFCR0: Multiple Address Filter Configuration Register 0 + MAFCR0_Res = 0xf0 // Reserved Bit + MAFCR0_MAF3EN = 0x8 // Multiple Address Filter 3 Enable + MAFCR0_MAF2EN = 0x4 // Multiple Address Filter 2 Enable + MAFCR0_MAF1EN = 0x2 // Multiple Address Filter 1 Enable + MAFCR0_MAF0EN = 0x1 // Multiple Address Filter 0 Enable + + // MAFCR1: Multiple Address Filter Configuration Register 1 + MAFCR1_AACK_3_SET_PD = 0x80 // Set Data Pending bit for address filter 3. + MAFCR1_AACK_3_I_AM_COORD = 0x40 // Enable PAN Coordinator mode for address filter 3. + MAFCR1_AACK_2_SET_PD = 0x20 // Set Data Pending bit for address filter 2. + MAFCR1_AACK_2_I_AM_COORD = 0x10 // Enable PAN Coordinator mode for address filter 2. + MAFCR1_AACK_1_SET_PD = 0x8 // Set Data Pending bit for address filter 1. + MAFCR1_AACK_1_I_AM_COORD = 0x4 // Enable PAN Coordinator mode for address filter 1. + MAFCR1_AACK_0_SET_PD = 0x2 // Set Data Pending bit for address filter 0. + MAFCR1_AACK_0_I_AM_COORD = 0x1 // Enable PAN Coordinator mode for address filter 0. + + // AES_CTRL: AES Control Register + AES_CTRL_AES_REQUEST = 0x80 // Request AES Operation. + AES_CTRL_AES_MODE = 0x20 // Set AES Operation Mode + AES_CTRL_AES_DIR = 0x8 // Set AES Operation Direction + AES_CTRL_AES_IM = 0x4 // AES Interrupt Enable + + // AES_STATUS: AES Status Register + AES_STATUS_AES_ER = 0x80 // AES Operation Finished with Error + AES_STATUS_AES_DONE = 0x1 // AES Operation Finished with Success + + // AES_STATE: AES Plain and Cipher Text Buffer Register + AES_STATE_AES_STATE = 0xff // AES Plain and Cipher Text Buffer + + // AES_KEY: AES Encryption and Decryption Key Buffer Register + AES_KEY_AES_KEY = 0xff // AES Encryption/Decryption Key Buffer + + // TRX_STATUS: Transceiver Status Register + TRX_STATUS_CCA_DONE = 0x80 // CCA Algorithm Status + TRX_STATUS_CCA_STATUS = 0x40 // CCA Status Result + TRX_STATUS_TST_STATUS = 0x20 // Test mode status + TRX_STATUS_TRX_STATUS = 0x1f // Transceiver Main Status + + // TRX_STATE: Transceiver State Control Register + TRX_STATE_TRAC_STATUS = 0xe0 // Transaction Status + TRX_STATE_TRX_CMD = 0x1f // State Control Command + + // TRX_CTRL_0: Reserved + TRX_CTRL_0_Res7 = 0x80 // Reserved + TRX_CTRL_0_PMU_EN = 0x40 // Enable Phase Measurement Unit + TRX_CTRL_0_PMU_START = 0x20 // Start of Phase Measurement Unit + TRX_CTRL_0_PMU_IF_INV = 0x10 // PMU IF Inverse + + // TRX_CTRL_1: Transceiver Control Register 1 + TRX_CTRL_1_PA_EXT_EN = 0x80 // External PA support enable + TRX_CTRL_1_IRQ_2_EXT_EN = 0x40 // Connect Frame Start IRQ to TC1 + TRX_CTRL_1_TX_AUTO_CRC_ON = 0x20 // Enable Automatic CRC Calculation + TRX_CTRL_1_PLL_TX_FLT = 0x10 // Enable PLL TX filter + + // PHY_TX_PWR: Transceiver Transmit Power Control Register + PHY_TX_PWR_TX_PWR = 0xf // Transmit Power Setting + + // PHY_RSSI: Receiver Signal Strength Indicator Register + PHY_RSSI_RX_CRC_VALID = 0x80 // Received Frame CRC Status + PHY_RSSI_RND_VALUE = 0x60 // Random Value + PHY_RSSI_RSSI = 0x1f // Receiver Signal Strength Indicator + + // PHY_ED_LEVEL: Transceiver Energy Detection Level Register + PHY_ED_LEVEL_ED_LEVEL = 0xff // Energy Detection Level + + // PHY_CC_CCA: Transceiver Clear Channel Assessment (CCA) Control Register + PHY_CC_CCA_CCA_REQUEST = 0x80 // Manual CCA Measurement Request + PHY_CC_CCA_CCA_MODE = 0x60 // Select CCA Measurement Mode + PHY_CC_CCA_CHANNEL = 0x1f // RX/TX Channel Selection + + // CCA_THRES: Transceiver CCA Threshold Setting Register + CCA_THRES_CCA_CS_THRES = 0xf0 // CS Threshold Level for CCA Measurement + CCA_THRES_CCA_ED_THRES = 0xf // ED Threshold Level for CCA Measurement + + // RX_CTRL: Transceiver Receive Control Register + RX_CTRL_PDT_THRES = 0xf // Receiver Sensitivity Control + + // SFD_VALUE: Start of Frame Delimiter Value Register + SFD_VALUE_SFD_VALUE = 0xff // Start of Frame Delimiter Value + + // TRX_CTRL_2: Transceiver Control Register 2 + TRX_CTRL_2_RX_SAFE_MODE = 0x80 // RX Safe Mode + TRX_CTRL_2_OQPSK_DATA_RATE = 0x3 // Data Rate Selection + + // ANT_DIV: Antenna Diversity Control Register + ANT_DIV_ANT_SEL = 0x80 // Antenna Diversity Antenna Status + ANT_DIV_ANT_DIV_EN = 0x8 // Enable Antenna Diversity + ANT_DIV_ANT_EXT_SW_EN = 0x4 // Enable External Antenna Switch Control + ANT_DIV_ANT_CTRL = 0x3 // Static Antenna Diversity Switch Control + + // IRQ_MASK: Transceiver Interrupt Enable Register + IRQ_MASK_AWAKE_EN = 0x80 // Awake Interrupt Enable + IRQ_MASK_TX_END_EN = 0x40 // TX_END Interrupt Enable + IRQ_MASK_AMI_EN = 0x20 // Address Match Interrupt Enable + IRQ_MASK_CCA_ED_DONE_EN = 0x10 // End of ED Measurement Interrupt Enable + IRQ_MASK_RX_END_EN = 0x8 // RX_END Interrupt Enable + IRQ_MASK_RX_START_EN = 0x4 // RX_START Interrupt Enable + IRQ_MASK_PLL_UNLOCK_EN = 0x2 // PLL Unlock Interrupt Enable + IRQ_MASK_PLL_LOCK_EN = 0x1 // PLL Lock Interrupt Enable + + // IRQ_STATUS: Transceiver Interrupt Status Register + IRQ_STATUS_AWAKE = 0x80 // Awake Interrupt Status + IRQ_STATUS_TX_END = 0x40 // TX_END Interrupt Status + IRQ_STATUS_AMI = 0x20 // Address Match Interrupt Status + IRQ_STATUS_CCA_ED_DONE = 0x10 // End of ED Measurement Interrupt Status + IRQ_STATUS_RX_END = 0x8 // RX_END Interrupt Status + IRQ_STATUS_RX_START = 0x4 // RX_START Interrupt Status + IRQ_STATUS_PLL_UNLOCK = 0x2 // PLL Unlock Interrupt Status + IRQ_STATUS_PLL_LOCK = 0x1 // PLL Lock Interrupt Status + + // IRQ_MASK1: Transceiver Interrupt Enable Register 1 + IRQ_MASK1_Res = 0xe0 // Reserved Bit + IRQ_MASK1_MAF_3_AMI_EN = 0x10 // Address Match Interrupt enable Address filter 3 + IRQ_MASK1_MAF_2_AMI_EN = 0x8 // Address Match Interrupt enable Address filter 2 + IRQ_MASK1_MAF_1_AMI_EN = 0x4 // Address Match Interrupt enable Address filter 1 + IRQ_MASK1_MAF_0_AMI_EN = 0x2 // Address Match Interrupt enable Address filter 0 + IRQ_MASK1_TX_START_EN = 0x1 // Transmit Start Interrupt enable + + // IRQ_STATUS1: Transceiver Interrupt Status Register 1 + IRQ_STATUS1_Res = 0xe0 // Reserved Bit + IRQ_STATUS1_MAF_3_AMI = 0x10 // Address Match Interrupt Status Address filter 3 + IRQ_STATUS1_MAF_2_AMI = 0x8 // Address Match Interrupt Status Address filter 2 + IRQ_STATUS1_MAF_1_AMI = 0x4 // Address Match Interrupt Status Address filter 1 + IRQ_STATUS1_MAF_0_AMI = 0x2 // Address Match Interrupt Status Address filter 0 + IRQ_STATUS1_TX_START = 0x1 // Transmit Start Interrupt Status + + // VREG_CTRL: Voltage Regulator Control and Status Register + VREG_CTRL_AVREG_EXT = 0x80 // Use External AVDD Regulator + VREG_CTRL_AVDD_OK = 0x40 // AVDD Supply Voltage Valid + VREG_CTRL_DVREG_EXT = 0x8 // Use External DVDD Regulator + VREG_CTRL_DVDD_OK = 0x4 // DVDD Supply Voltage Valid + + // BATMON: Battery Monitor Control and Status Register + BATMON_BAT_LOW = 0x80 // Battery Monitor Interrupt Status + BATMON_BAT_LOW_EN = 0x40 // Battery Monitor Interrupt Enable + BATMON_BATMON_OK = 0x20 // Battery Monitor Status + BATMON_BATMON_HR = 0x10 // Battery Monitor Voltage Range + BATMON_BATMON_VTH = 0xf // Battery Monitor Threshold Voltage + + // XOSC_CTRL: Crystal Oscillator Control Register + XOSC_CTRL_XTAL_MODE = 0xf0 // Crystal Oscillator Operating Mode + XOSC_CTRL_XTAL_TRIM = 0xf // Crystal Oscillator Load Capacitance Trimming + + // CC_CTRL_0: Channel Control Register 0 + CC_CTRL_0_CC_NUMBER = 0xff // Channel Number + + // CC_CTRL_1: Channel Control Register 1 + CC_CTRL_1_CC_BAND = 0xf // Channel Band + + // RX_SYN: Transceiver Receiver Sensitivity Control Register + RX_SYN_RX_PDT_DIS = 0x80 // Prevent Frame Reception + RX_SYN_RX_OVERRIDE = 0x40 // Receiver Override Function + RX_SYN_RX_PDT_LEVEL = 0xf // Reduce Receiver Sensitivity + + // TRX_RPC: Transceiver Reduced Power Consumption Control + TRX_RPC_RX_RPC_CTRL = 0xc0 // Smart Receiving Mode Timing + TRX_RPC_RX_RPC_EN = 0x20 // Reciver Smart Receiving Mode Enable + TRX_RPC_PDT_RPC_EN = 0x10 // Smart Receiving Mode Reduced Sensitivity Enable + TRX_RPC_PLL_RPC_EN = 0x8 // PLL Smart Receiving Mode Enable + TRX_RPC_Res0 = 0x4 // Reserved + TRX_RPC_IPAN_RPC_EN = 0x2 // Smart Receiving Mode IPAN Handling Enable + TRX_RPC_XAH_RPC_EN = 0x1 // Smart Receiving in Extended Operating Modes Enable + + // XAH_CTRL_1: Transceiver Acknowledgment Frame Control Register 1 + XAH_CTRL_1_AACK_FLTR_RES_FT = 0x20 // Filter Reserved Frames + XAH_CTRL_1_AACK_UPLD_RES_FT = 0x10 // Process Reserved Frames + XAH_CTRL_1_AACK_ACK_TIME = 0x4 // Reduce Acknowledgment Time + XAH_CTRL_1_AACK_PROM_MODE = 0x2 // Enable Promiscuous Mode + + // FTN_CTRL: Transceiver Filter Tuning Control Register + FTN_CTRL_FTN_START = 0x80 // Start Calibration Loop of Filter Tuning Network + + // PLL_CF: Transceiver Center Frequency Calibration Control Register + PLL_CF_PLL_CF_START = 0x80 // Start Center Frequency Calibration + + // PLL_DCU: Transceiver Delay Cell Calibration Control Register + PLL_DCU_PLL_DCU_START = 0x80 // Start Delay Cell Calibration + + // PART_NUM: Device Identification Register (Part Number) + PART_NUM_PART_NUM = 0xff // Part Number + + // VERSION_NUM: Device Identification Register (Version Number) + VERSION_NUM_VERSION_NUM = 0xff // Version Number + + // MAN_ID_0: Device Identification Register (Manufacture ID Low Byte) + MAN_ID_0_MAN_ID_07 = 0x80 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_06 = 0x40 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_05 = 0x20 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_04 = 0x10 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_03 = 0x8 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_02 = 0x4 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_01 = 0x2 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_00 = 0x1 // Manufacturer ID (Low Byte) + + // MAN_ID_1: Device Identification Register (Manufacture ID High Byte) + MAN_ID_1_MAN_ID_ = 0xff // Manufacturer ID (High Byte) + + // SHORT_ADDR_0: Transceiver MAC Short Address Register (Low Byte) + SHORT_ADDR_0_SHORT_ADDR_07 = 0x80 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_06 = 0x40 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_05 = 0x20 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_04 = 0x10 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_03 = 0x8 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_02 = 0x4 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_01 = 0x2 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_00 = 0x1 // MAC Short Address + + // SHORT_ADDR_1: Transceiver MAC Short Address Register (High Byte) + SHORT_ADDR_1_SHORT_ADDR_ = 0xff // MAC Short Address + + // PAN_ID_0: Transceiver Personal Area Network ID Register (Low Byte) + PAN_ID_0_PAN_ID_07 = 0x80 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_06 = 0x40 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_05 = 0x20 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_04 = 0x10 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_03 = 0x8 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_02 = 0x4 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_01 = 0x2 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_00 = 0x1 // MAC Personal Area Network ID + + // PAN_ID_1: Transceiver Personal Area Network ID Register (High Byte) + PAN_ID_1_PAN_ID_ = 0xff // MAC Personal Area Network ID + + // IEEE_ADDR_0: Transceiver MAC IEEE Address Register 0 + IEEE_ADDR_0_IEEE_ADDR_07 = 0x80 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_06 = 0x40 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_05 = 0x20 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_04 = 0x10 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_03 = 0x8 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_02 = 0x4 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_01 = 0x2 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_00 = 0x1 // MAC IEEE Address + + // IEEE_ADDR_1: Transceiver MAC IEEE Address Register 1 + IEEE_ADDR_1_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // IEEE_ADDR_2: Transceiver MAC IEEE Address Register 2 + IEEE_ADDR_2_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // IEEE_ADDR_3: Transceiver MAC IEEE Address Register 3 + IEEE_ADDR_3_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // IEEE_ADDR_4: Transceiver MAC IEEE Address Register 4 + IEEE_ADDR_4_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // IEEE_ADDR_5: Transceiver MAC IEEE Address Register 5 + IEEE_ADDR_5_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // IEEE_ADDR_6: Transceiver MAC IEEE Address Register 6 + IEEE_ADDR_6_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // IEEE_ADDR_7: Transceiver MAC IEEE Address Register 7 + IEEE_ADDR_7_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // XAH_CTRL_0: Transceiver Extended Operating Mode Control Register + XAH_CTRL_0_MAX_FRAME_RETRIES = 0xf0 // Maximum Number of Frame Re-transmission Attempts + XAH_CTRL_0_MAX_CSMA_RETRIES = 0xe // Maximum Number of CSMA-CA Procedure Repetition Attempts + XAH_CTRL_0_SLOTTED_OPERATION = 0x1 // Set Slotted Acknowledgment + + // CSMA_SEED_0: Transceiver CSMA-CA Random Number Generator Seed Register + CSMA_SEED_0_CSMA_SEED_07 = 0x80 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_06 = 0x40 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_05 = 0x20 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_04 = 0x10 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_03 = 0x8 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_02 = 0x4 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_01 = 0x2 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_00 = 0x1 // Seed Value for CSMA Random Number Generator + + // CSMA_SEED_1: Transceiver Acknowledgment Frame Control Register 2 + CSMA_SEED_1_AACK_FVN_MODE = 0xc0 // Acknowledgment Frame Filter Mode + CSMA_SEED_1_AACK_SET_PD = 0x20 // Set Frame Pending Sub-field + CSMA_SEED_1_AACK_DIS_ACK = 0x10 // Disable Acknowledgment Frame Transmission + CSMA_SEED_1_AACK_I_AM_COORD = 0x8 // Set Personal Area Network Coordinator + CSMA_SEED_1_CSMA_SEED_1 = 0x7 // Seed Value for CSMA Random Number Generator + + // CSMA_BE: Transceiver CSMA-CA Back-off Exponent Control Register + CSMA_BE_MAX_BE = 0xf0 // Maximum Back-off Exponent + CSMA_BE_MIN_BE = 0xf // Minimum Back-off Exponent + + // TST_CTRL_DIGI: Transceiver Digital Test Control Register + TST_CTRL_DIGI_TST_CTRL_DIG = 0xf // Digital Test Controller Register + + // TST_RX_LENGTH: Transceiver Received Frame Length Register + TST_RX_LENGTH_RX_LENGTH = 0xff // Received Frame Length +) + +// Bitfields for SYMCNT: MAC Symbol Counter +const ( + // SCTSTRHH: Symbol Counter Transmit Frame Timestamp Register HH-Byte + SCTSTRHH_SCTSTRHH = 0xff // Symbol Counter Transmit Frame Timestamp Register HH-Byte + + // SCTSTRHL: Symbol Counter Transmit Frame Timestamp Register HL-Byte + SCTSTRHL_SCTSTRHL = 0xff // Symbol Counter Transmit Frame Timestamp Register HL-Byte + + // SCTSTRLH: Symbol Counter Transmit Frame Timestamp Register LH-Byte + SCTSTRLH_SCTSTRLH = 0xff // Symbol Counter Transmit Frame Timestamp Register LH-Byte + + // SCTSTRLL: Symbol Counter Transmit Frame Timestamp Register LL-Byte + SCTSTRLL_SCTSTRLL = 0xff // Symbol Counter Transmit Frame Timestamp Register LL-Byte + + // SCOCR1HH: Symbol Counter Output Compare Register 1 HH-Byte + SCOCR1HH_SCOCR1HH = 0xff // Symbol Counter Output Compare Register 1 HH-Byte + + // SCOCR1HL: Symbol Counter Output Compare Register 1 HL-Byte + SCOCR1HL_SCOCR1HL = 0xff // Symbol Counter Output Compare Register 1 HL-Byte + + // SCOCR1LH: Symbol Counter Output Compare Register 1 LH-Byte + SCOCR1LH_SCOCR1LH = 0xff // Symbol Counter Output Compare Register 1 LH-Byte + + // SCOCR1LL: Symbol Counter Output Compare Register 1 LL-Byte + SCOCR1LL_SCOCR1LL = 0xff // Symbol Counter Output Compare Register 1 LL-Byte + + // SCOCR2HH: Symbol Counter Output Compare Register 2 HH-Byte + SCOCR2HH_SCOCR2HH = 0xff // Symbol Counter Output Compare Register 2 HH-Byte + + // SCOCR2HL: Symbol Counter Output Compare Register 2 HL-Byte + SCOCR2HL_SCOCR2HL = 0xff // Symbol Counter Output Compare Register 2 HL-Byte + + // SCOCR2LH: Symbol Counter Output Compare Register 2 LH-Byte + SCOCR2LH_SCOCR2LH = 0xff // Symbol Counter Output Compare Register 2 LH-Byte + + // SCOCR2LL: Symbol Counter Output Compare Register 2 LL-Byte + SCOCR2LL_SCOCR2LL = 0xff // Symbol Counter Output Compare Register 2 LL-Byte + + // SCOCR3HH: Symbol Counter Output Compare Register 3 HH-Byte + SCOCR3HH_SCOCR3HH = 0xff // Symbol Counter Output Compare Register 3 HH-Byte + + // SCOCR3HL: Symbol Counter Output Compare Register 3 HL-Byte + SCOCR3HL_SCOCR3HL = 0xff // Symbol Counter Output Compare Register 3 HL-Byte + + // SCOCR3LH: Symbol Counter Output Compare Register 3 LH-Byte + SCOCR3LH_SCOCR3LH = 0xff // Symbol Counter Output Compare Register 3 LH-Byte + + // SCOCR3LL: Symbol Counter Output Compare Register 3 LL-Byte + SCOCR3LL_SCOCR3LL = 0xff // Symbol Counter Output Compare Register 3 LL-Byte + + // SCTSRHH: Symbol Counter Frame Timestamp Register HH-Byte + SCTSRHH_SCTSRHH = 0xff // Symbol Counter Frame Timestamp Register HH-Byte + + // SCTSRHL: Symbol Counter Frame Timestamp Register HL-Byte + SCTSRHL_SCTSRHL = 0xff // Symbol Counter Frame Timestamp Register HL-Byte + + // SCTSRLH: Symbol Counter Frame Timestamp Register LH-Byte + SCTSRLH_SCTSRLH = 0xff // Symbol Counter Frame Timestamp Register LH-Byte + + // SCTSRLL: Symbol Counter Frame Timestamp Register LL-Byte + SCTSRLL_SCTSRLL = 0xff // Symbol Counter Frame Timestamp Register LL-Byte + + // SCBTSRHH: Symbol Counter Beacon Timestamp Register HH-Byte + SCBTSRHH_SCBTSRHH = 0xff // Symbol Counter Beacon Timestamp Register HH-Byte + + // SCBTSRHL: Symbol Counter Beacon Timestamp Register HL-Byte + SCBTSRHL_SCBTSRHL = 0xff // Symbol Counter Beacon Timestamp Register HL-Byte + + // SCBTSRLH: Symbol Counter Beacon Timestamp Register LH-Byte + SCBTSRLH_SCBTSRLH = 0xff // Symbol Counter Beacon Timestamp Register LH-Byte + + // SCBTSRLL: Symbol Counter Beacon Timestamp Register LL-Byte + SCBTSRLL_SCBTSRLL = 0xff // Symbol Counter Beacon Timestamp Register LL-Byte + + // SCCNTHH: Symbol Counter Register HH-Byte + SCCNTHH_SCCNTHH = 0xff // Symbol Counter Register HH-Byte + + // SCCNTHL: Symbol Counter Register HL-Byte + SCCNTHL_SCCNTHL = 0xff // Symbol Counter Register HL-Byte + + // SCCNTLH: Symbol Counter Register LH-Byte + SCCNTLH_SCCNTLH = 0xff // Symbol Counter Register LH-Byte + + // SCCNTLL: Symbol Counter Register LL-Byte + SCCNTLL_SCCNTLL = 0xff // Symbol Counter Register LL-Byte + + // SCIRQS: Symbol Counter Interrupt Status Register + SCIRQS_Res = 0xe0 // Reserved Bit + SCIRQS_IRQSBO = 0x10 // Backoff Slot Counter IRQ + SCIRQS_IRQSOF = 0x8 // Symbol Counter Overflow IRQ + SCIRQS_IRQSCP = 0x7 // Compare Unit 3 Compare Match IRQ + + // SCIRQM: Symbol Counter Interrupt Mask Register + SCIRQM_Res = 0xe0 // Reserved Bit + SCIRQM_IRQMBO = 0x10 // Backoff Slot Counter IRQ enable + SCIRQM_IRQMOF = 0x8 // Symbol Counter Overflow IRQ enable + SCIRQM_IRQMCP = 0x7 // Symbol Counter Compare Match 3 IRQ enable + + // SCSR: Symbol Counter Status Register + SCSR_Res = 0xfe // Reserved Bit + SCSR_SCBSY = 0x1 // Symbol Counter busy + + // SCCR1: Symbol Counter Control Register 1 + SCCR1_Res = 0xc0 // Reserved Bit + SCCR1_SCBTSM = 0x20 // Symbol Counter Beacon Timestamp Mask Register + SCCR1_SCCKDIV = 0x1c // Clock divider for synchronous clock source (16MHz Transceiver Clock) + SCCR1_SCEECLK = 0x2 // Enable External Clock Source on PG2 + SCCR1_SCENBO = 0x1 // Backoff Slot Counter enable + + // SCCR0: Symbol Counter Control Register 0 + SCCR0_SCRES = 0x80 // Symbol Counter Synchronization + SCCR0_SCMBTS = 0x40 // Manual Beacon Timestamp + SCCR0_SCEN = 0x20 // Symbol Counter enable + SCCR0_SCCKSEL = 0x10 // Symbol Counter Clock Source select + SCCR0_SCTSE = 0x8 // Symbol Counter Automatic Timestamping enable + SCCR0_SCCMP = 0x7 // Symbol Counter Compare Unit 3 Mode select + + // SCCSR: Symbol Counter Compare Source Register + SCCSR_Res = 0xc0 // Reserved Bit + SCCSR_SCCS3 = 0x30 // Symbol Counter Compare Source select register for Compare Unit 3 + SCCSR_SCCS2 = 0xc // Symbol Counter Compare Source select register for Compare Unit 2 + SCCSR_SCCS1 = 0x3 // Symbol Counter Compare Source select register for Compare Units + + // SCRSTRHH: Symbol Counter Received Frame Timestamp Register HH-Byte + SCRSTRHH_SCRSTRHH = 0xff // Symbol Counter Received Frame Timestamp Register HH-Byte + + // SCRSTRHL: Symbol Counter Received Frame Timestamp Register HL-Byte + SCRSTRHL_SCRSTRHL = 0xff // Symbol Counter Received Frame Timestamp Register HL-Byte + + // SCRSTRLH: Symbol Counter Received Frame Timestamp Register LH-Byte + SCRSTRLH_SCRSTRLH = 0xff // Symbol Counter Received Frame Timestamp Register LH-Byte + + // SCRSTRLL: Symbol Counter Received Frame Timestamp Register LL-Byte + SCRSTRLL_SCRSTRLL = 0xff // Symbol Counter Received Frame Timestamp Register LL-Byte +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Programming Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for JTAG: JTAG Interface +const ( + // OCDR: On-Chip Debug Register + OCDR_OCDR = 0xff // On-Chip Debug Register Data +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC3 = 0xc0 // External Interrupt 3 Sense Control Bit + EICRA_ISC2 = 0x30 // External Interrupt 2 Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt 1 Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt 0 Sense Control Bit + + // EICRB: External Interrupt Control Register B + EICRB_ISC7 = 0xc0 // External Interrupt 7 Sense Control Bit + EICRB_ISC6 = 0x30 // External Interrupt 6 Sense Control Bit + EICRB_ISC5 = 0xc // External Interrupt 5 Sense Control Bit + EICRB_ISC4 = 0x3 // External Interrupt 4 Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xff // External Interrupt Request Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xff // External Interrupt Flag + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Mask + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Enable Mask + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Mask + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_Res = 0xf8 // Reserved Bit + PCIFR_PCIF = 0x7 // Pin Change Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_Res = 0xf8 // Reserved Bit + PCICR_PCIE = 0x7 // Pin Change Interrupt Enables +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC Multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // ADC Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status Register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCSRC: The ADC Control and Status Register C + ADCSRC_ADTHT = 0xc0 // ADC Track-and-Hold Time + ADCSRC_Res0 = 0x20 // Reserved + ADCSRC_ADSUT = 0x1f // ADC Start-up Time + + // DIDR2: Digital Input Disable Register 2 + DIDR2_ADC15D = 0x80 // Reserved Bits + DIDR2_ADC14D = 0x40 // Reserved Bits + DIDR2_ADC13D = 0x20 // Reserved Bits + DIDR2_ADC12D = 0x10 // Reserved Bits + DIDR2_ADC11D = 0x8 // Reserved Bits + DIDR2_ADC10D = 0x4 // Reserved Bits + DIDR2_ADC9D = 0x2 // Reserved Bits + DIDR2_ADC8D = 0x1 // Reserved Bits + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // Disable ADC7:0 Digital Input + DIDR0_ADC6D = 0x40 // Disable ADC7:0 Digital Input + DIDR0_ADC5D = 0x20 // Disable ADC7:0 Digital Input + DIDR0_ADC4D = 0x10 // Disable ADC7:0 Digital Input + DIDR0_ADC3D = 0x8 // Disable ADC7:0 Digital Input + DIDR0_ADC2D = 0x4 // Disable ADC7:0 Digital Input + DIDR0_ADC1D = 0x2 // Disable ADC7:0 Digital Input + DIDR0_ADC0D = 0x1 // Disable ADC7:0 Digital Input +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write Section Read Enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_CAL = 0xff // Oscillator Calibration Tuning Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // RAMPZ: Extended Z-pointer Register for ELPM/SPM + RAMPZ_RAMPZ = 0x3 // Extended Z-Pointer Value + + // GPIOR2: General Purpose I/O Register 2 + GPIOR2_GPIOR = 0xff // General Purpose I/O Register 2 Value + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose I/O Register 1 Value + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR06 = 0x40 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR05 = 0x20 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR04 = 0x10 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR03 = 0x8 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR02 = 0x4 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR01 = 0x2 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR00 = 0x1 // General Purpose I/O Register 0 Value + + // PRR2: Power Reduction Register 2 + PRR2_PRRAM3 = 0x8 // Power Reduction SRAM3 + PRR2_PRRAM2 = 0x4 // Power Reduction SRAM2 + PRR2_PRRAM1 = 0x2 // Power Reduction SRAM1 + PRR2_PRRAM0 = 0x1 // Power Reduction SRAM0 + + // PRR1: Power Reduction Register 1 + PRR1_Res = 0x80 // Reserved Bit + PRR1_PRTRX24 = 0x40 // Power Reduction Transceiver + PRR1_PRTIM5 = 0x20 // Power Reduction Timer/Counter5 + PRR1_PRTIM4 = 0x10 // Power Reduction Timer/Counter4 + PRR1_PRTIM3 = 0x8 // Power Reduction Timer/Counter3 + PRR1_PRUSART1 = 0x1 // Power Reduction USART1 + + // PRR0: Power Reduction Register0 + PRR0_PRTWI = 0x80 // Power Reduction TWI + PRR0_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR0_PRPGA = 0x10 // Power Reduction PGA + PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR0_PRUSART0 = 0x2 // Power Reduction USART + PRR0_PRADC = 0x1 // Power Reduction ADC +) + +// Bitfields for FLASH: FLASH Controller +const ( + // NEMCR: Flash Extended-Mode Control-Register + NEMCR_ENEAM = 0x40 // Enable Extended Address Mode for Extra Rows + NEMCR_AEAM = 0x30 // Address for Extended Address Mode of Extra Rows + + // BGCR: Reference Voltage Calibration Register + BGCR_Res = 0x80 // Reserved Bit + BGCR_BGCAL_FINE = 0x78 // Fine Calibration Bits + BGCR_BGCAL = 0x7 // Coarse Calibration Bits +) + +// Bitfields for PWRCTRL: Power Controller +const ( + // TRXPR: Transceiver Pin Register + TRXPR_SLPTR = 0x2 // Multi-purpose Transceiver Control Bit + TRXPR_TRXRST = 0x1 // Force Transceiver Reset + + // DRTRAM0: Data Retention Configuration Register #0 + DRTRAM0_DRTSWOK = 0x20 // DRT Switch OK + DRTRAM0_ENDRT = 0x10 // Enable SRAM Data Retention + + // DRTRAM1: Data Retention Configuration Register #1 + DRTRAM1_DRTSWOK = 0x20 // DRT Switch OK + DRTRAM1_ENDRT = 0x10 // Enable SRAM Data Retention + + // DRTRAM2: Data Retention Configuration Register #2 + DRTRAM2_Res = 0x40 // Reserved Bit + DRTRAM2_DRTSWOK = 0x20 // DRT Switch OK + DRTRAM2_ENDRT = 0x10 // Enable SRAM Data Retention + + // DRTRAM3: Data Retention Configuration Register #3 + DRTRAM3_DRTSWOK = 0x20 // DRT Switch OK + DRTRAM3_ENDRT = 0x10 // Enable SRAM Data Retention + + // LLDRL: Low Leakage Voltage Regulator Data Register (Low-Byte) + LLDRL_LLDRL = 0xf // Low-Byte Data Register Bits + + // LLDRH: Low Leakage Voltage Regulator Data Register (High-Byte) + LLDRH_LLDRH = 0x1f // High-Byte Data Register Bits + + // LLCR: Low Leakage Voltage Regulator Control Register + LLCR_Res = 0xc0 // Reserved Bit + LLCR_LLDONE = 0x20 // Calibration Done + LLCR_LLCOMP = 0x10 // Comparator Output + LLCR_LLCAL = 0x8 // Calibration Active + LLCR_LLTCO = 0x4 // Temperature Coefficient of Current Source + LLCR_LLSHORT = 0x2 // Short Lower Calibration Circuit + LLCR_LLENCAL = 0x1 // Enable Automatic Calibration + + // DPDS0: Port Driver Strength Register 0 + DPDS0_PFDRV = 0xc0 // Driver Strength Port F + DPDS0_PEDRV = 0x30 // Driver Strength Port E + DPDS0_PDDRV = 0xc // Driver Strength Port D + DPDS0_PBDRV = 0x3 // Driver Strength Port B + + // DPDS1: Port Driver Strength Register 1 + DPDS1_PGDRV = 0x3 // Driver Strength Port G +) diff --git a/src/device/avr/atmega256rfr2.ld b/src/device/avr/atmega256rfr2.ld new file mode 100644 index 00000000..0ffd3b86 --- /dev/null +++ b/src/device/avr/atmega256rfr2.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega256RFR2.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x40000; +__ram_size = 0x8000; +__num_isrs = 71; diff --git a/src/device/avr/atmega32.go b/src/device/avr/atmega32.go new file mode 100644 index 00000000..757c72dd --- /dev/null +++ b/src/device/avr/atmega32.go @@ -0,0 +1,491 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega32.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega32 + +// Device information for the ATmega32. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega32" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_TIMER2_COMP = 4 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 5 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 6 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 7 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 8 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 9 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 10 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 11 // Timer/Counter0 Overflow + IRQ_SPI_STC = 12 // Serial Transfer Complete + IRQ_USART_RXC = 13 // USART, Rx Complete + IRQ_USART_UDRE = 14 // USART Data Register Empty + IRQ_USART_TXC = 15 // USART, Tx Complete + IRQ_ADC = 16 // ADC Conversion Complete + IRQ_EE_RDY = 17 // EEPROM Ready + IRQ_ANA_COMP = 18 // Analog Comparator + IRQ_TWI = 19 // 2-wire Serial Interface + IRQ_SPM_RDY = 20 // Store Program Memory Ready + IRQ_max = 20 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + HIGH __reg + LOW __reg + }{ + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x42, // On-Chip Debug Related Register in I/O Memory + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x3e, // EEPROM Read/Write Access Bytes + EEARH: 0x3e, // EEPROM Read/Write Access Bytes + EEDR: 0x3d, // EEPROM Data Register + EECR: 0x3c, // EEPROM Control Register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x41, // Watchdog Timer Control Register + } + + // External Interrupts + EXINT = struct { + GICR __reg + GIFR __reg + }{ + GICR: 0x5b, // General Interrupt Control Register + GIFR: 0x5a, // General Interrupt Flag Register + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0 __reg + TCNT0 __reg + OCR0 __reg + }{ + TCCR0: 0x53, // Timer/Counter Control Register + TCNT0: 0x52, // Timer/Counter Register + OCR0: 0x5c, // Output Compare Register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2 __reg + TCNT2 __reg + OCR2 __reg + ASSR __reg + }{ + TCCR2: 0x45, // Timer/Counter2 Control Register + TCNT2: 0x44, // Timer/Counter2 + OCR2: 0x43, // Timer/Counter2 Output Compare Register + ASSR: 0x42, // Asynchronous Status Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TCCR1A: 0x4f, // Timer/Counter1 Control Register A + TCCR1B: 0x4e, // Timer/Counter1 Control Register B + TCNT1L: 0x4c, // Timer/Counter1 Bytes + TCNT1H: 0x4c, // Timer/Counter1 Bytes + OCR1AL: 0x4a, // Timer/Counter1 Output Compare Register Bytes + OCR1AH: 0x4a, // Timer/Counter1 Output Compare Register Bytes + OCR1BL: 0x48, // Timer/Counter1 Output Compare Register Bytes + OCR1BH: 0x48, // Timer/Counter1 Output Compare Register Bytes + ICR1L: 0x46, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x46, // Timer/Counter1 Input Capture Register Bytes + } + + // Serial Peripheral Interface + SPI = struct { + SPDR __reg + SPSR __reg + SPCR __reg + }{ + SPDR: 0x2f, // SPI Data Register + SPSR: 0x2e, // SPI Status Register + SPCR: 0x2d, // SPI Control Register + } + + // USART + USART = struct { + UDR __reg + UCSRA __reg + UCSRB __reg + UCSRC __reg + UBRRH __reg + UBRRL __reg + }{ + UDR: 0x2c, // USART I/O Data Register + UCSRA: 0x2b, // USART Control and Status Register A + UCSRB: 0x2a, // USART Control and Status Register B + UCSRC: 0x40, // USART Control and Status Register C + UBRRH: 0x40, // USART Baud Rate Register Hight Byte + UBRRL: 0x29, // USART Baud Rate Register Low Byte + } + + // Analog Comparator + AC = struct { + ACSR __reg + }{ + ACSR: 0x28, // Analog Comparator Control And Status Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + }{ + ADMUX: 0x27, // The ADC multiplexer Selection Register + ADCSRA: 0x26, // The ADC Control and Status register + ADCL: 0x24, // ADC Data Register Bytes + ADCH: 0x24, // ADC Data Register Bytes + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + }{ + PORTA: 0x3b, // Port A Data Register + DDRA: 0x3a, // Port A Data Direction Register + PINA: 0x39, // Port A Input Pins + PORTB: 0x38, // Port B Data Register + DDRB: 0x37, // Port B Data Direction Register + PINB: 0x36, // Port B Input Pins + PORTC: 0x35, // Port C Data Register + DDRC: 0x34, // Port C Data Direction Register + PINC: 0x33, // Port C Input Pins + PORTD: 0x32, // Port D Data Register + DDRD: 0x31, // Port D Data Direction Register + PIND: 0x30, // Port D Input Pins + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x51, // Oscillator Calibration Value + } + + // Bootloader + BOOT_LOAD = struct { + SPMCR __reg + }{ + SPMCR: 0x57, // Store Program Memory Control Register + } + + // Two Wire Serial Interface + TWI = struct { + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWBR: 0x20, // TWI Bit Rate register + TWCR: 0x56, // TWI Control Register + TWSR: 0x21, // TWI Status Register + TWDR: 0x23, // TWI Data register + TWAR: 0x22, // TWI (Slave) Address register + } +) + +// Bitfields for FUSE: Fuses +const ( + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_CKOPT = 0x10 // Oscillator options + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_BODLEVEL = 0x80 // Brownout detector trigger level + LOW_BODEN = 0x40 // Brown-out detection enabled + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for JTAG: JTAG Interface +const ( + // OCDR: On-Chip Debug Related Register in I/O Memory + OCDR_OCDR = 0xff // On-Chip Debug Register Bits +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDTOE = 0x10 // RW + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for EXINT: External Interrupts +const ( + // GICR: General Interrupt Control Register + GICR_INT0 = 0x40 // External Interrupt Request 0 Enable + GICR_INT1 = 0x80 // External Interrupt Request 1 Enable + GICR_INT2 = 0x20 // External Interrupt Request 2 Enable + GICR_IVSEL = 0x2 // Interrupt Vector Select + GICR_IVCE = 0x1 // Interrupt Vector Change Enable + + // GIFR: General Interrupt Flag Register + GIFR_INTF = 0xc0 // External Interrupt Flags + GIFR_INTF2 = 0x20 // External Interrupt Flag 2 +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0: Timer/Counter Control Register + TCCR0_FOC0 = 0x80 // Force Output Compare + TCCR0_WGM00 = 0x40 // Waveform Generation Mode + TCCR0_COM0 = 0x30 // Compare Match Output Modes + TCCR0_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0_CS0 = 0x7 // Clock Selects +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2: Timer/Counter2 Control Register + TCCR2_FOC2 = 0x80 // Force Output Compare + TCCR2_WGM20 = 0x40 // Pulse Width Modulator Enable + TCCR2_COM2 = 0x30 // Compare Output Mode bits + TCCR2_WGM21 = 0x8 // Clear Timer/Counter2 on Compare Match + TCCR2_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_AS2 = 0x8 // Asynchronous Timer/counter2 + ASSR_TCN2UB = 0x4 // Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // Timer/counter Control Register2 Update Busy +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_FOC1A = 0x8 // Force Output Compare 1A + TCCR1A_FOC1B = 0x4 // Force Output Compare 1B + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects +) + +// Bitfields for USART: USART +const ( + // UCSRA: USART Control and Status Register A + UCSRA_RXC = 0x80 // USART Receive Complete + UCSRA_TXC = 0x40 // USART Transmitt Complete + UCSRA_UDRE = 0x20 // USART Data Register Empty + UCSRA_FE = 0x10 // Framing Error + UCSRA_DOR = 0x8 // Data overRun + UCSRA_UPE = 0x4 // Parity Error + UCSRA_U2X = 0x2 // Double the USART transmission speed + UCSRA_MPCM = 0x1 // Multi-processor Communication Mode + + // UCSRB: USART Control and Status Register B + UCSRB_RXCIE = 0x80 // RX Complete Interrupt Enable + UCSRB_TXCIE = 0x40 // TX Complete Interrupt Enable + UCSRB_UDRIE = 0x20 // USART Data register Empty Interrupt Enable + UCSRB_RXEN = 0x10 // Receiver Enable + UCSRB_TXEN = 0x8 // Transmitter Enable + UCSRB_UCSZ2 = 0x4 // Character Size + UCSRB_RXB8 = 0x2 // Receive Data Bit 8 + UCSRB_TXB8 = 0x1 // Transmit Data Bit 8 + + // UCSRC: USART Control and Status Register C + UCSRC_URSEL = 0x80 // Register Select + UCSRC_UMSEL = 0x40 // USART Mode Select + UCSRC_UPM = 0x30 // Parity Mode Bits + UCSRC_USBS = 0x8 // Stop Bit Select + UCSRC_UCSZ = 0x6 // Character Size + UCSRC_UCPOL = 0x1 // Clock Polarity +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCR: Store Program Memory Control Register + SPMCR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCR_RWWSB = 0x40 // Read While Write Section Busy + SPMCR_RWWSRE = 0x10 // Read While Write secion read enable + SPMCR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCR_PGWRT = 0x4 // Page Write + SPMCR_PGERS = 0x2 // Page Erase + SPMCR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler bits + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI address bits + TWAR_TWGCE = 0x1 // TWI general call recognition enable bit +) diff --git a/src/device/avr/atmega32.ld b/src/device/avr/atmega32.ld new file mode 100644 index 00000000..18b69bc0 --- /dev/null +++ b/src/device/avr/atmega32.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega32.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_size = 0x800; +__num_isrs = 21; diff --git a/src/device/avr/atmega3208.go b/src/device/avr/atmega3208.go new file mode 100644 index 00000000..8b3edc13 --- /dev/null +++ b/src/device/avr/atmega3208.go @@ -0,0 +1,1291 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega3208.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega3208 + +// Device information for the ATmega3208. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega3208" + ARCH = "AVR8X" + FAMILY = "AVR MEGA" +) + +// Interrupts +const ( + IRQ_NMI = 1 // + IRQ_VLM = 2 // + IRQ_CNT = 3 // + IRQ_PIT = 4 // + IRQ_CCL = 5 // + IRQ_PORT = 6 // + IRQ_LUNF = 7 // + IRQ_OVF = 7 // + IRQ_HUNF = 8 // + IRQ_LCMP0 = 9 // + IRQ_CMP0 = 9 // + IRQ_CMP1 = 10 // + IRQ_LCMP1 = 10 // + IRQ_CMP2 = 11 // + IRQ_LCMP2 = 11 // + IRQ_INT = 12 // + IRQ_INT = 13 // + IRQ_TWIS = 14 // + IRQ_TWIM = 15 // + IRQ_INT = 16 // + IRQ_RXC = 17 // + IRQ_DRE = 18 // + IRQ_TXC = 19 // + IRQ_PORT = 20 // + IRQ_AC = 21 // + IRQ_RESRDY = 22 // + IRQ_WCOMP = 23 // + IRQ_PORT = 24 // + IRQ_INT = 25 // + IRQ_RXC = 26 // + IRQ_DRE = 27 // + IRQ_TXC = 28 // + IRQ_PORT = 29 // + IRQ_EE = 30 // + IRQ_RXC = 31 // + IRQ_DRE = 32 // + IRQ_TXC = 33 // + IRQ_PORT = 34 // + IRQ_PORT = 35 // + IRQ_max = 35 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Analog Comparator + AC = struct { + DACREF __reg + MUXCTRLA __reg + }{ + DACREF: 0x4, // Referance scale control + MUXCTRLA: 0x2, // Mux Control A + } + + // Analog to Digital Converter + ADC = struct { + COMMAND __reg + CTRLE __reg + MUXPOS __reg + RESL __reg + RESH __reg + SAMPCTRL __reg + WINHTL __reg + WINHTH __reg + WINLTL __reg + WINLTH __reg + }{ + COMMAND: 0x8, // Command + CTRLE: 0x4, // Control E + MUXPOS: 0x6, // Positive mux input + RESL: 0x10, // ADC Accumulator Result + RESH: 0x10, // ADC Accumulator Result + SAMPCTRL: 0x5, // Sample Control + WINHTL: 0x14, // Window comparator high threshold + WINHTH: 0x14, // Window comparator high threshold + WINLTL: 0x12, // Window comparator low threshold + WINLTH: 0x12, // Window comparator low threshold + } + + // Bod interface + BOD = struct { + VLMCTRLA __reg + }{ + VLMCTRLA: 0x8, // Voltage level monitor Control + } + + // Configurable Custom Logic + CCL = struct { + INTCTRL0 __reg + LUT0CTRLA __reg + LUT0CTRLB __reg + LUT0CTRLC __reg + LUT1CTRLA __reg + LUT1CTRLB __reg + LUT1CTRLC __reg + LUT2CTRLA __reg + LUT2CTRLB __reg + LUT2CTRLC __reg + LUT3CTRLA __reg + LUT3CTRLB __reg + LUT3CTRLC __reg + SEQCTRL0 __reg + TRUTH0 __reg + TRUTH1 __reg + TRUTH2 __reg + TRUTH3 __reg + }{ + INTCTRL0: 0x5, // Interrupt Control 0 + LUT0CTRLA: 0x8, // LUT Control 0 A + LUT0CTRLB: 0x9, // LUT Control 0 B + LUT0CTRLC: 0xa, // LUT Control 0 C + LUT1CTRLA: 0xc, // LUT Control 1 A + LUT1CTRLB: 0xd, // LUT Control 1 B + LUT1CTRLC: 0xe, // LUT Control 1 C + LUT2CTRLA: 0x10, // LUT Control 2 A + LUT2CTRLB: 0x11, // LUT Control 2 B + LUT2CTRLC: 0x12, // LUT Control 2 C + LUT3CTRLA: 0x14, // LUT Control 3 A + LUT3CTRLB: 0x15, // LUT Control 3 B + LUT3CTRLC: 0x16, // LUT Control 3 C + SEQCTRL0: 0x1, // Sequential Control 0 + TRUTH0: 0xb, // Truth 0 + TRUTH1: 0xf, // Truth 1 + TRUTH2: 0x13, // Truth 2 + TRUTH3: 0x17, // Truth 3 + } + + // Clock controller + CLKCTRL = struct { + MCLKCTRLA __reg + MCLKCTRLB __reg + MCLKLOCK __reg + MCLKSTATUS __reg + OSC20MCALIBA __reg + OSC20MCALIBB __reg + OSC20MCTRLA __reg + OSC32KCALIB __reg + OSC32KCTRLA __reg + XOSC32KCTRLA __reg + }{ + MCLKCTRLA: 0x0, // MCLK Control A + MCLKCTRLB: 0x1, // MCLK Control B + MCLKLOCK: 0x2, // MCLK Lock + MCLKSTATUS: 0x3, // MCLK Status + OSC20MCALIBA: 0x11, // OSC20M Calibration A + OSC20MCALIBB: 0x12, // OSC20M Calibration B + OSC20MCTRLA: 0x10, // OSC20M Control A + OSC32KCALIB: 0x19, // OSC32K Calibration + OSC32KCTRLA: 0x18, // OSC32K Control A + XOSC32KCTRLA: 0x1c, // XOSC32K Control A + } + + // CPU + CPU = struct { + CCP __reg + RAMPZ __reg + SPH __reg + SPL __reg + SREG __reg + }{ + CCP: 0x4, // Configuration Change Protection + RAMPZ: 0xb, // Extended Z-pointer Register + SPH: 0xe, // Stack Pointer High + SPL: 0xd, // Stack Pointer Low + SREG: 0xf, // Status Register + } + + // Interrupt Controller + CPUINT = struct { + LVL0PRI __reg + LVL1VEC __reg + }{ + LVL0PRI: 0x2, // Interrupt Level 0 Priority + LVL1VEC: 0x3, // Interrupt Level 1 Priority Vector + } + + // CRCSCAN + CRCSCAN = struct { + }{} + + // Event System + EVSYS = struct { + CHANNEL0 __reg + CHANNEL1 __reg + CHANNEL2 __reg + CHANNEL3 __reg + CHANNEL4 __reg + CHANNEL5 __reg + STROBE __reg + USERADC0 __reg + USERCCLLUT0A __reg + USERCCLLUT0B __reg + USERCCLLUT1A __reg + USERCCLLUT1B __reg + USERCCLLUT2A __reg + USERCCLLUT2B __reg + USERCCLLUT3A __reg + USERCCLLUT3B __reg + USEREVOUTA __reg + USEREVOUTB __reg + USEREVOUTC __reg + USEREVOUTD __reg + USEREVOUTE __reg + USEREVOUTF __reg + USERTCA0 __reg + USERTCB0 __reg + USERTCB1 __reg + USERTCB2 __reg + USERTCB3 __reg + USERUSART0 __reg + USERUSART1 __reg + USERUSART2 __reg + USERUSART3 __reg + }{ + CHANNEL0: 0x10, // Multiplexer Channel 0 + CHANNEL1: 0x11, // Multiplexer Channel 1 + CHANNEL2: 0x12, // Multiplexer Channel 2 + CHANNEL3: 0x13, // Multiplexer Channel 3 + CHANNEL4: 0x14, // Multiplexer Channel 4 + CHANNEL5: 0x15, // Multiplexer Channel 5 + STROBE: 0x0, // Channel Strobe + USERADC0: 0x28, // User ADC0 + USERCCLLUT0A: 0x20, // User CCL LUT0 Event A + USERCCLLUT0B: 0x21, // User CCL LUT0 Event B + USERCCLLUT1A: 0x22, // User CCL LUT1 Event A + USERCCLLUT1B: 0x23, // User CCL LUT1 Event B + USERCCLLUT2A: 0x24, // User CCL LUT2 Event A + USERCCLLUT2B: 0x25, // User CCL LUT2 Event B + USERCCLLUT3A: 0x26, // User CCL LUT3 Event A + USERCCLLUT3B: 0x27, // User CCL LUT3 Event B + USEREVOUTA: 0x29, // User EVOUT Port A + USEREVOUTB: 0x2a, // User EVOUT Port B + USEREVOUTC: 0x2b, // User EVOUT Port C + USEREVOUTD: 0x2c, // User EVOUT Port D + USEREVOUTE: 0x2d, // User EVOUT Port E + USEREVOUTF: 0x2e, // User EVOUT Port F + USERTCA0: 0x33, // User TCA0 + USERTCB0: 0x34, // User TCB0 + USERTCB1: 0x35, // User TCB1 + USERTCB2: 0x36, // User TCB2 + USERTCB3: 0x37, // User TCB3 + USERUSART0: 0x2f, // User USART0 + USERUSART1: 0x30, // User USART1 + USERUSART2: 0x31, // User USART2 + USERUSART3: 0x32, // User USART3 + } + + // Fuses + FUSE = struct { + APPEND __reg + BODCFG __reg + BOOTEND __reg + OSCCFG __reg + SYSCFG0 __reg + SYSCFG1 __reg + TCD0CFG __reg + WDTCFG __reg + }{ + APPEND: 0x7, // Application Code Section End + BODCFG: 0x1, // BOD Configuration + BOOTEND: 0x8, // Boot Section End + OSCCFG: 0x2, // Oscillator Configuration + SYSCFG0: 0x5, // System Configuration 0 + SYSCFG1: 0x6, // System Configuration 1 + TCD0CFG: 0x4, // TCD0 Configuration + WDTCFG: 0x0, // Watchdog Configuration + } + + // General Purpose IO + GPIO = struct { + GPIOR0 __reg + GPIOR1 __reg + GPIOR2 __reg + GPIOR3 __reg + }{ + GPIOR0: 0x0, // General Purpose IO Register 0 + GPIOR1: 0x1, // General Purpose IO Register 1 + GPIOR2: 0x2, // General Purpose IO Register 2 + GPIOR3: 0x3, // General Purpose IO Register 3 + } + + // Lockbit + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, // Lock Bits + } + + // BIST in the NVMCTRL module + NVMBIST = struct { + ADDRPAT __reg + DATAPAT __reg + }{ + ADDRPAT: 0x1, // Address pattern + DATAPAT: 0x2, // Data pattern + } + + // Non-volatile Memory Controller + NVMCTRL = struct { + ADDRL __reg + ADDRH __reg + }{ + ADDRL: 0x8, // Address + ADDRH: 0x8, // Address + } + + // I/O Ports + PORT = struct { + DIRCLR __reg + DIRSET __reg + DIRTGL __reg + OUTCLR __reg + OUTSET __reg + OUTTGL __reg + PIN0CTRL __reg + PIN1CTRL __reg + PIN2CTRL __reg + PIN3CTRL __reg + PIN4CTRL __reg + PIN5CTRL __reg + PIN6CTRL __reg + PIN7CTRL __reg + PORTCTRL __reg + }{ + DIRCLR: 0x2, // Data Direction Clear + DIRSET: 0x1, // Data Direction Set + DIRTGL: 0x3, // Data Direction Toggle + OUTCLR: 0x6, // Output Value Clear + OUTSET: 0x5, // Output Value Set + OUTTGL: 0x7, // Output Value Toggle + PIN0CTRL: 0x10, // Pin 0 Control + PIN1CTRL: 0x11, // Pin 1 Control + PIN2CTRL: 0x12, // Pin 2 Control + PIN3CTRL: 0x13, // Pin 3 Control + PIN4CTRL: 0x14, // Pin 4 Control + PIN5CTRL: 0x15, // Pin 5 Control + PIN6CTRL: 0x16, // Pin 6 Control + PIN7CTRL: 0x17, // Pin 7 Control + PORTCTRL: 0xa, // Port Control + } + + // Port Multiplexer + PORTMUX = struct { + CCLROUTEA __reg + EVSYSROUTEA __reg + TCAROUTEA __reg + TCBROUTEA __reg + TWISPIROUTEA __reg + USARTROUTEA __reg + }{ + CCLROUTEA: 0x1, // Port Multiplexer CCL + EVSYSROUTEA: 0x0, // Port Multiplexer EVSYS + TCAROUTEA: 0x4, // Port Multiplexer TCA + TCBROUTEA: 0x5, // Port Multiplexer TCB + TWISPIROUTEA: 0x3, // Port Multiplexer TWI and SPI + USARTROUTEA: 0x2, // Port Multiplexer USART register A + } + + // Reset controller + RSTCTRL = struct { + RSTFR __reg + SWRR __reg + }{ + RSTFR: 0x0, // Reset Flags + SWRR: 0x1, // Software Reset + } + + // Real-Time Counter + RTC = struct { + CLKSEL __reg + CMPL __reg + CMPH __reg + PITCTRLA __reg + PITDBGCTRL __reg + PITINTCTRL __reg + PITINTFLAGS __reg + PITSTATUS __reg + }{ + CLKSEL: 0x7, // Clock Select + CMPL: 0xc, // Compare + CMPH: 0xc, // Compare + PITCTRLA: 0x10, // PIT Control A + PITDBGCTRL: 0x15, // PIT Debug control + PITINTCTRL: 0x12, // PIT Interrupt Control + PITINTFLAGS: 0x13, // PIT Interrupt Flags + PITSTATUS: 0x11, // PIT Status + } + + // Signature row + SIGROW = struct { + CHECKSUM1 __reg + DEVICEID0 __reg + DEVICEID1 __reg + DEVICEID2 __reg + OSCCAL16M0 __reg + OSCCAL16M1 __reg + OSCCAL20M0 __reg + OSCCAL20M1 __reg + OSCCAL32K __reg + OSC16ERR3V __reg + OSC16ERR5V __reg + OSC20ERR3V __reg + OSC20ERR5V __reg + SERNUM0 __reg + SERNUM1 __reg + SERNUM2 __reg + SERNUM3 __reg + SERNUM4 __reg + SERNUM5 __reg + SERNUM6 __reg + SERNUM7 __reg + SERNUM8 __reg + SERNUM9 __reg + TEMPSENSE0 __reg + TEMPSENSE1 __reg + }{ + CHECKSUM1: 0x2f, // CRC Checksum Byte 1 + DEVICEID0: 0x0, // Device ID Byte 0 + DEVICEID1: 0x1, // Device ID Byte 1 + DEVICEID2: 0x2, // Device ID Byte 2 + OSCCAL16M0: 0x18, // Oscillator Calibration 16 MHz Byte 0 + OSCCAL16M1: 0x19, // Oscillator Calibration 16 MHz Byte 1 + OSCCAL20M0: 0x1a, // Oscillator Calibration 20 MHz Byte 0 + OSCCAL20M1: 0x1b, // Oscillator Calibration 20 MHz Byte 1 + OSCCAL32K: 0x14, // Oscillator Calibration for 32kHz ULP + OSC16ERR3V: 0x22, // OSC16 error at 3V + OSC16ERR5V: 0x23, // OSC16 error at 5V + OSC20ERR3V: 0x24, // OSC20 error at 3V + OSC20ERR5V: 0x25, // OSC20 error at 5V + SERNUM0: 0x3, // Serial Number Byte 0 + SERNUM1: 0x4, // Serial Number Byte 1 + SERNUM2: 0x5, // Serial Number Byte 2 + SERNUM3: 0x6, // Serial Number Byte 3 + SERNUM4: 0x7, // Serial Number Byte 4 + SERNUM5: 0x8, // Serial Number Byte 5 + SERNUM6: 0x9, // Serial Number Byte 6 + SERNUM7: 0xa, // Serial Number Byte 7 + SERNUM8: 0xb, // Serial Number Byte 8 + SERNUM9: 0xc, // Serial Number Byte 9 + TEMPSENSE0: 0x20, // Temperature Sensor Calibration Byte 0 + TEMPSENSE1: 0x21, // Temperature Sensor Calibration Byte 1 + } + + // Sleep Controller + SLPCTRL = struct { + }{} + + // Serial Peripheral Interface + SPI = struct { + }{} + + // System Configuration Registers + SYSCFG = struct { + EXTBRK __reg + OCDM __reg + OCDMS __reg + REVID __reg + }{ + EXTBRK: 0x2, // External Break + OCDM: 0x18, // OCD Message Register + OCDMS: 0x19, // OCD Message Status + REVID: 0x1, // Revision ID + } + + // 16-bit Timer/Counter Type A + TCA = struct { + CMP0L __reg + CMP0H __reg + CMP0BUFL __reg + CMP0BUFH __reg + CMP1L __reg + CMP1H __reg + CMP1BUFL __reg + CMP1BUFH __reg + CMP2L __reg + CMP2H __reg + CMP2BUFL __reg + CMP2BUFH __reg + CTRLFCLR __reg + CTRLFSET __reg + PERBUFL __reg + PERBUFH __reg + HCMP0 __reg + HCMP1 __reg + HCMP2 __reg + HCNT __reg + HPER __reg + LCMP0 __reg + LCMP1 __reg + LCMP2 __reg + LCNT __reg + LPER __reg + }{ + CMP0L: 0x28, // Compare 0 + CMP0H: 0x28, // Compare 0 + CMP0BUFL: 0x38, // Compare 0 Buffer + CMP0BUFH: 0x38, // Compare 0 Buffer + CMP1L: 0x2a, // Compare 1 + CMP1H: 0x2a, // Compare 1 + CMP1BUFL: 0x3a, // Compare 1 Buffer + CMP1BUFH: 0x3a, // Compare 1 Buffer + CMP2L: 0x2c, // Compare 2 + CMP2H: 0x2c, // Compare 2 + CMP2BUFL: 0x3c, // Compare 2 Buffer + CMP2BUFH: 0x3c, // Compare 2 Buffer + CTRLFCLR: 0x6, // Control F Clear + CTRLFSET: 0x7, // Control F Set + PERBUFL: 0x36, // Period Buffer + PERBUFH: 0x36, // Period Buffer + HCMP0: 0x29, // High Compare + HCMP1: 0x2b, // High Compare + HCMP2: 0x2d, // High Compare + HCNT: 0x21, // High Count + HPER: 0x27, // High Period + LCMP0: 0x28, // Low Compare + LCMP1: 0x2a, // Low Compare + LCMP2: 0x2c, // Low Compare + LCNT: 0x20, // Low Count + LPER: 0x26, // Low Period + } + + // 16-bit Timer Type B + TCB = struct { + CCMPL __reg + CCMPH __reg + }{ + CCMPL: 0xc, // Compare or Capture + CCMPH: 0xc, // Compare or Capture + } + + // Two-Wire Interface + TWI = struct { + BRIDGECTRL __reg + MADDR __reg + MBAUD __reg + MCTRLA __reg + MCTRLB __reg + MDATA __reg + MSTATUS __reg + SADDR __reg + SADDRMASK __reg + SCTRLA __reg + SCTRLB __reg + SDATA __reg + SSTATUS __reg + }{ + BRIDGECTRL: 0x1, // Bridge Control + MADDR: 0x7, // Master Address + MBAUD: 0x6, // Master Baurd Rate Control + MCTRLA: 0x3, // Master Control A + MCTRLB: 0x4, // Master Control B + MDATA: 0x8, // Master Data + MSTATUS: 0x5, // Master Status + SADDR: 0xc, // Slave Address + SADDRMASK: 0xe, // Slave Address Mask + SCTRLA: 0x9, // Slave Control A + SCTRLB: 0xa, // Slave Control B + SDATA: 0xd, // Slave Data + SSTATUS: 0xb, // Slave Status + } + + // Universal Synchronous and Asynchronous Receiver and Transmitter + USART = struct { + BAUDL __reg + BAUDH __reg + RXDATAH __reg + RXDATAL __reg + RXPLCTRL __reg + TXDATAH __reg + TXDATAL __reg + TXPLCTRL __reg + }{ + BAUDL: 0x8, // Baud Rate + BAUDH: 0x8, // Baud Rate + RXDATAH: 0x1, // Receive Data High Byte + RXDATAL: 0x0, // Receive Data Low Byte + RXPLCTRL: 0xe, // IRCOM Receiver Pulse Length Control + TXDATAH: 0x3, // Transmit Data High Byte + TXDATAL: 0x2, // Transmit Data Low Byte + TXPLCTRL: 0xd, // IRCOM Transmitter Pulse Length Control + } + + // User Row + USERROW = struct { + USERROW0 __reg + USERROW1 __reg + USERROW2 __reg + USERROW3 __reg + USERROW4 __reg + USERROW5 __reg + USERROW6 __reg + USERROW7 __reg + USERROW8 __reg + USERROW9 __reg + USERROW10 __reg + USERROW11 __reg + USERROW12 __reg + USERROW13 __reg + USERROW14 __reg + USERROW15 __reg + USERROW16 __reg + USERROW17 __reg + USERROW18 __reg + USERROW19 __reg + USERROW20 __reg + USERROW21 __reg + USERROW22 __reg + USERROW23 __reg + USERROW24 __reg + USERROW25 __reg + USERROW26 __reg + USERROW27 __reg + USERROW28 __reg + USERROW29 __reg + USERROW30 __reg + USERROW31 __reg + USERROW32 __reg + USERROW33 __reg + USERROW34 __reg + USERROW35 __reg + USERROW36 __reg + USERROW37 __reg + USERROW38 __reg + USERROW39 __reg + USERROW40 __reg + USERROW41 __reg + USERROW42 __reg + USERROW43 __reg + USERROW44 __reg + USERROW45 __reg + USERROW46 __reg + USERROW47 __reg + USERROW48 __reg + USERROW49 __reg + USERROW50 __reg + USERROW51 __reg + USERROW52 __reg + USERROW53 __reg + USERROW54 __reg + USERROW55 __reg + USERROW56 __reg + USERROW57 __reg + USERROW58 __reg + USERROW59 __reg + USERROW60 __reg + USERROW61 __reg + USERROW62 __reg + USERROW63 __reg + }{ + USERROW0: 0x0, // User Row Byte 0 + USERROW1: 0x1, // User Row Byte 1 + USERROW2: 0x2, // User Row Byte 2 + USERROW3: 0x3, // User Row Byte 3 + USERROW4: 0x4, // User Row Byte 4 + USERROW5: 0x5, // User Row Byte 5 + USERROW6: 0x6, // User Row Byte 6 + USERROW7: 0x7, // User Row Byte 7 + USERROW8: 0x8, // User Row Byte 8 + USERROW9: 0x9, // User Row Byte 9 + USERROW10: 0xa, // User Row Byte 10 + USERROW11: 0xb, // User Row Byte 11 + USERROW12: 0xc, // User Row Byte 12 + USERROW13: 0xd, // User Row Byte 13 + USERROW14: 0xe, // User Row Byte 14 + USERROW15: 0xf, // User Row Byte 15 + USERROW16: 0x10, // User Row Byte 16 + USERROW17: 0x11, // User Row Byte 17 + USERROW18: 0x12, // User Row Byte 18 + USERROW19: 0x13, // User Row Byte 19 + USERROW20: 0x14, // User Row Byte 20 + USERROW21: 0x15, // User Row Byte 21 + USERROW22: 0x16, // User Row Byte 22 + USERROW23: 0x17, // User Row Byte 23 + USERROW24: 0x18, // User Row Byte 24 + USERROW25: 0x19, // User Row Byte 25 + USERROW26: 0x1a, // User Row Byte 26 + USERROW27: 0x1b, // User Row Byte 27 + USERROW28: 0x1c, // User Row Byte 28 + USERROW29: 0x1d, // User Row Byte 29 + USERROW30: 0x1e, // User Row Byte 30 + USERROW31: 0x1f, // User Row Byte 31 + USERROW32: 0x20, // User Row Byte 32 + USERROW33: 0x21, // User Row Byte 33 + USERROW34: 0x22, // User Row Byte 34 + USERROW35: 0x23, // User Row Byte 35 + USERROW36: 0x24, // User Row Byte 36 + USERROW37: 0x25, // User Row Byte 37 + USERROW38: 0x26, // User Row Byte 38 + USERROW39: 0x27, // User Row Byte 39 + USERROW40: 0x28, // User Row Byte 40 + USERROW41: 0x29, // User Row Byte 41 + USERROW42: 0x2a, // User Row Byte 42 + USERROW43: 0x2b, // User Row Byte 43 + USERROW44: 0x2c, // User Row Byte 44 + USERROW45: 0x2d, // User Row Byte 45 + USERROW46: 0x2e, // User Row Byte 46 + USERROW47: 0x2f, // User Row Byte 47 + USERROW48: 0x30, // User Row Byte 48 + USERROW49: 0x31, // User Row Byte 49 + USERROW50: 0x32, // User Row Byte 50 + USERROW51: 0x33, // User Row Byte 51 + USERROW52: 0x34, // User Row Byte 52 + USERROW53: 0x35, // User Row Byte 53 + USERROW54: 0x36, // User Row Byte 54 + USERROW55: 0x37, // User Row Byte 55 + USERROW56: 0x38, // User Row Byte 56 + USERROW57: 0x39, // User Row Byte 57 + USERROW58: 0x3a, // User Row Byte 58 + USERROW59: 0x3b, // User Row Byte 59 + USERROW60: 0x3c, // User Row Byte 60 + USERROW61: 0x3d, // User Row Byte 61 + USERROW62: 0x3e, // User Row Byte 62 + USERROW63: 0x3f, // User Row Byte 63 + } + + // Virtual Ports + VPORT = struct { + }{} + + // Voltage reference + VREF = struct { + }{} + + // Watch-Dog Timer + WDT = struct { + }{} +) + +// Bitfields for AC: Analog Comparator +const ( + // DACREF: Referance scale control + DACREF_DATA = 0xff // DAC voltage reference + + // MUXCTRLA: Mux Control A + MUXCTRLA_INVERT = 0x80 // Invert AC Output + MUXCTRLA_MUXNEG = 0x3 // Negative Input MUX Selection + MUXCTRLA_MUXPOS = 0x18 // Positive Input MUX Selection +) + +// Bitfields for ADC: Analog to Digital Converter +const ( + // COMMAND: Command + COMMAND_STCONV = 0x1 // Start Conversion Operation + + // CTRLE: Control E + CTRLE_WINCM = 0x7 // Window Comparator Mode + + // MUXPOS: Positive mux input + MUXPOS_MUXPOS = 0x1f // Analog Channel Selection Bits + + // SAMPCTRL: Sample Control + SAMPCTRL_SAMPLEN = 0x1f // Sample lenght +) + +// Bitfields for BOD: Bod interface +const ( + // VLMCTRLA: Voltage level monitor Control + VLMCTRLA_VLMLVL = 0x3 // voltage level monitor level +) + +// Bitfields for CCL: Configurable Custom Logic +const ( + // INTCTRL0: Interrupt Control 0 + INTCTRL0_INTMODE0 = 0x3 // Interrupt Mode for LUT0 + INTCTRL0_INTMODE1 = 0xc // Interrupt Mode for LUT1 + INTCTRL0_INTMODE2 = 0x30 // Interrupt Mode for LUT2 + INTCTRL0_INTMODE3 = 0xc0 // Interrupt Mode for LUT3 + + // LUT0CTRLA: LUT Control 0 A + LUT0CTRLA_CLKSRC = 0xe // Clock Source Selection + LUT0CTRLA_EDGEDET = 0x80 // Edge Detection Enable + LUT0CTRLA_ENABLE = 0x1 // LUT Enable + LUT0CTRLA_FILTSEL = 0x30 // Filter Selection + LUT0CTRLA_OUTEN = 0x40 // Output Enable + + // LUT0CTRLB: LUT Control 0 B + LUT0CTRLB_INSEL0 = 0xf // LUT Input 0 Source Selection + LUT0CTRLB_INSEL1 = 0xf0 // LUT Input 1 Source Selection + + // LUT0CTRLC: LUT Control 0 C + LUT0CTRLC_INSEL2 = 0xf // LUT Input 2 Source Selection + + // LUT1CTRLA: LUT Control 1 A + LUT1CTRLA_CLKSRC = 0xe // Clock Source Selection + LUT1CTRLA_EDGEDET = 0x80 // Edge Detection Enable + LUT1CTRLA_ENABLE = 0x1 // LUT Enable + LUT1CTRLA_FILTSEL = 0x30 // Filter Selection + LUT1CTRLA_OUTEN = 0x40 // Output Enable + + // LUT1CTRLB: LUT Control 1 B + LUT1CTRLB_INSEL0 = 0xf // LUT Input 0 Source Selection + LUT1CTRLB_INSEL1 = 0xf0 // LUT Input 1 Source Selection + + // LUT1CTRLC: LUT Control 1 C + LUT1CTRLC_INSEL2 = 0xf // LUT Input 2 Source Selection + + // LUT2CTRLA: LUT Control 2 A + LUT2CTRLA_CLKSRC = 0xe // Clock Source Selection + LUT2CTRLA_EDGEDET = 0x80 // Edge Detection Enable + LUT2CTRLA_ENABLE = 0x1 // LUT Enable + LUT2CTRLA_FILTSEL = 0x30 // Filter Selection + LUT2CTRLA_OUTEN = 0x40 // Output Enable + + // LUT2CTRLB: LUT Control 2 B + LUT2CTRLB_INSEL0 = 0xf // LUT Input 0 Source Selection + LUT2CTRLB_INSEL1 = 0xf0 // LUT Input 1 Source Selection + + // LUT2CTRLC: LUT Control 2 C + LUT2CTRLC_INSEL2 = 0xf // LUT Input 2 Source Selection + + // LUT3CTRLA: LUT Control 3 A + LUT3CTRLA_CLKSRC = 0xe // Clock Source Selection + LUT3CTRLA_EDGEDET = 0x80 // Edge Detection Enable + LUT3CTRLA_ENABLE = 0x1 // LUT Enable + LUT3CTRLA_FILTSEL = 0x30 // Filter Selection + LUT3CTRLA_OUTEN = 0x40 // Output Enable + + // LUT3CTRLB: LUT Control 3 B + LUT3CTRLB_INSEL0 = 0xf // LUT Input 0 Source Selection + LUT3CTRLB_INSEL1 = 0xf0 // LUT Input 1 Source Selection + + // LUT3CTRLC: LUT Control 3 C + LUT3CTRLC_INSEL2 = 0xf // LUT Input 2 Source Selection + + // SEQCTRL0: Sequential Control 0 + SEQCTRL0_SEQSEL = 0x7 // Sequential Selection +) + +// Bitfields for CLKCTRL: Clock controller +const ( + // MCLKCTRLA: MCLK Control A + MCLKCTRLA_CLKOUT = 0x80 // System clock out + MCLKCTRLA_CLKSEL = 0x3 // clock select + + // MCLKCTRLB: MCLK Control B + MCLKCTRLB_PDIV = 0x1e // Prescaler division + MCLKCTRLB_PEN = 0x1 // Prescaler enable + + // MCLKLOCK: MCLK Lock + MCLKLOCK_LOCKEN = 0x1 // lock ebable + + // MCLKSTATUS: MCLK Status + MCLKSTATUS_EXTS = 0x80 // External Clock status + MCLKSTATUS_OSC20MS = 0x10 // 20MHz oscillator status + MCLKSTATUS_OSC32KS = 0x20 // 32KHz oscillator status + MCLKSTATUS_SOSC = 0x1 // System Oscillator changing + MCLKSTATUS_XOSC32KS = 0x40 // 32.768 kHz Crystal Oscillator status + + // OSC20MCALIBA: OSC20M Calibration A + OSC20MCALIBA_CALSEL20M = 0x80 // Calibration freq select + OSC20MCALIBA_CAL20M = 0x7f // Calibration + + // OSC20MCALIBB: OSC20M Calibration B + OSC20MCALIBB_LOCK = 0x80 // Lock + OSC20MCALIBB_TEMPCAL20M = 0xf // Oscillator temperature coefficient + + // OSC20MCTRLA: OSC20M Control A + OSC20MCTRLA_RUNSTDBY = 0x2 // Run standby + + // OSC32KCALIB: OSC32K Calibration + OSC32KCALIB_CAL32K = 0x3f // Calibration + + // OSC32KCTRLA: OSC32K Control A + OSC32KCTRLA_RUNSTDBY = 0x2 // Run standby + + // XOSC32KCTRLA: XOSC32K Control A + XOSC32KCTRLA_CSUT = 0x30 // Crystal startup time + XOSC32KCTRLA_ENABLE = 0x1 // Enable + XOSC32KCTRLA_RUNSTDBY = 0x2 // Run standby + XOSC32KCTRLA_SEL = 0x4 // Select +) + +// Bitfields for CPU: CPU +const ( + // CCP: Configuration Change Protection + CCP_CCP = 0xff // CCP signature + + // SREG: Status Register + SREG_C = 0x1 // Carry Flag + SREG_H = 0x20 // Half Carry Flag + SREG_I = 0x80 // Global Interrupt Enable Flag + SREG_N = 0x4 // Negative Flag + SREG_S = 0x10 // N Exclusive Or V Flag + SREG_T = 0x40 // Transfer Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_Z = 0x2 // Zero Flag +) + +// Bitfields for CPUINT: Interrupt Controller +const ( + // LVL0PRI: Interrupt Level 0 Priority + LVL0PRI_LVL0PRI = 0xff // Interrupt Level Priority + + // LVL1VEC: Interrupt Level 1 Priority Vector + LVL1VEC_LVL1VEC = 0xff // Interrupt Vector with High Priority +) + +// Bitfields for EVSYS: Event System +const ( + // CHANNEL0: Multiplexer Channel 0 + CHANNEL0_GENERATOR = 0xff // Generator selector + + // CHANNEL1: Multiplexer Channel 1 + CHANNEL1_GENERATOR = 0xff // Generator selector + + // CHANNEL2: Multiplexer Channel 2 + CHANNEL2_GENERATOR = 0xff // Generator selector + + // CHANNEL3: Multiplexer Channel 3 + CHANNEL3_GENERATOR = 0xff // Generator selector + + // CHANNEL4: Multiplexer Channel 4 + CHANNEL4_GENERATOR = 0xff // Generator selector + + // CHANNEL5: Multiplexer Channel 5 + CHANNEL5_GENERATOR = 0xff // Generator selector + + // STROBE: Channel Strobe + STROBE_STROBE0 = 0xff // Software event on channels + + // USERADC0: User ADC0 + USERADC0_CHANNEL = 0xff // Channel selector + + // USERCCLLUT0A: User CCL LUT0 Event A + USERCCLLUT0A_CHANNEL = 0xff // Channel selector + + // USERCCLLUT0B: User CCL LUT0 Event B + USERCCLLUT0B_CHANNEL = 0xff // Channel selector + + // USERCCLLUT1A: User CCL LUT1 Event A + USERCCLLUT1A_CHANNEL = 0xff // Channel selector + + // USERCCLLUT1B: User CCL LUT1 Event B + USERCCLLUT1B_CHANNEL = 0xff // Channel selector + + // USERCCLLUT2A: User CCL LUT2 Event A + USERCCLLUT2A_CHANNEL = 0xff // Channel selector + + // USERCCLLUT2B: User CCL LUT2 Event B + USERCCLLUT2B_CHANNEL = 0xff // Channel selector + + // USERCCLLUT3A: User CCL LUT3 Event A + USERCCLLUT3A_CHANNEL = 0xff // Channel selector + + // USERCCLLUT3B: User CCL LUT3 Event B + USERCCLLUT3B_CHANNEL = 0xff // Channel selector + + // USEREVOUTA: User EVOUT Port A + USEREVOUTA_CHANNEL = 0xff // Channel selector + + // USEREVOUTB: User EVOUT Port B + USEREVOUTB_CHANNEL = 0xff // Channel selector + + // USEREVOUTC: User EVOUT Port C + USEREVOUTC_CHANNEL = 0xff // Channel selector + + // USEREVOUTD: User EVOUT Port D + USEREVOUTD_CHANNEL = 0xff // Channel selector + + // USEREVOUTE: User EVOUT Port E + USEREVOUTE_CHANNEL = 0xff // Channel selector + + // USEREVOUTF: User EVOUT Port F + USEREVOUTF_CHANNEL = 0xff // Channel selector + + // USERTCA0: User TCA0 + USERTCA0_CHANNEL = 0xff // Channel selector + + // USERTCB0: User TCB0 + USERTCB0_CHANNEL = 0xff // Channel selector + + // USERTCB1: User TCB1 + USERTCB1_CHANNEL = 0xff // Channel selector + + // USERTCB2: User TCB2 + USERTCB2_CHANNEL = 0xff // Channel selector + + // USERTCB3: User TCB3 + USERTCB3_CHANNEL = 0xff // Channel selector + + // USERUSART0: User USART0 + USERUSART0_CHANNEL = 0xff // Channel selector + + // USERUSART1: User USART1 + USERUSART1_CHANNEL = 0xff // Channel selector + + // USERUSART2: User USART2 + USERUSART2_CHANNEL = 0xff // Channel selector + + // USERUSART3: User USART3 + USERUSART3_CHANNEL = 0xff // Channel selector +) + +// Bitfields for FUSE: Fuses +const ( + // BODCFG: BOD Configuration + BODCFG_ACTIVE = 0xc // BOD Operation in Active Mode + BODCFG_LVL = 0xe0 // BOD Level + BODCFG_SAMPFREQ = 0x10 // BOD Sample Frequency + BODCFG_SLEEP = 0x3 // BOD Operation in Sleep Mode + + // OSCCFG: Oscillator Configuration + OSCCFG_FREQSEL = 0x3 // Frequency Select + OSCCFG_OSCLOCK = 0x80 // Oscillator Lock + + // SYSCFG0: System Configuration 0 + SYSCFG0_CRCSRC = 0xc0 // CRC Source + SYSCFG0_EESAVE = 0x1 // EEPROM Save + SYSCFG0_RSTPINCFG = 0x8 // Reset Pin Configuration + + // SYSCFG1: System Configuration 1 + SYSCFG1_SUT = 0x7 // Startup Time + + // TCD0CFG: TCD0 Configuration + TCD0CFG_CMPA = 0x1 // Compare A Default Output Value + TCD0CFG_CMPAEN = 0x10 // Compare A Output Enable + TCD0CFG_CMPB = 0x2 // Compare B Default Output Value + TCD0CFG_CMPBEN = 0x20 // Compare B Output Enable + TCD0CFG_CMPC = 0x4 // Compare C Default Output Value + TCD0CFG_CMPCEN = 0x40 // Compare C Output Enable + TCD0CFG_CMPD = 0x8 // Compare D Default Output Value + TCD0CFG_CMPDEN = 0x80 // Compare D Output Enable + + // WDTCFG: Watchdog Configuration + WDTCFG_PERIOD = 0xf // Watchdog Timeout Period + WDTCFG_WINDOW = 0xf0 // Watchdog Window Timeout Period +) + +// Bitfields for LOCKBIT: Lockbit +const ( + // LOCKBIT: Lock Bits + LOCKBIT_LB = 0xff // Lock Bits +) + +// Bitfields for NVMBIST: BIST in the NVMCTRL module +const ( + // ADDRPAT: Address pattern + ADDRPAT_AMODE = 0x70 // Address mode + ADDRPAT_XMODE = 0x3 // X address mode + ADDRPAT_YMODE = 0xc // Y address mode + + // DATAPAT: Data pattern + DATAPAT_PATTERN = 0x3 // Data check pattern + END_END = 0xffffff +) + +// Bitfields for PORT: I/O Ports +const ( + // PIN0CTRL: Pin 0 Control + PIN0CTRL_INVEN = 0x80 // Inverted I/O Enable + PIN0CTRL_ISC = 0x7 // Input/Sense Configuration + PIN0CTRL_PULLUPEN = 0x8 // Pullup enable + + // PIN1CTRL: Pin 1 Control + PIN1CTRL_INVEN = 0x80 // Inverted I/O Enable + PIN1CTRL_ISC = 0x7 // Input/Sense Configuration + PIN1CTRL_PULLUPEN = 0x8 // Pullup enable + + // PIN2CTRL: Pin 2 Control + PIN2CTRL_INVEN = 0x80 // Inverted I/O Enable + PIN2CTRL_ISC = 0x7 // Input/Sense Configuration + PIN2CTRL_PULLUPEN = 0x8 // Pullup enable + + // PIN3CTRL: Pin 3 Control + PIN3CTRL_INVEN = 0x80 // Inverted I/O Enable + PIN3CTRL_ISC = 0x7 // Input/Sense Configuration + PIN3CTRL_PULLUPEN = 0x8 // Pullup enable + + // PIN4CTRL: Pin 4 Control + PIN4CTRL_INVEN = 0x80 // Inverted I/O Enable + PIN4CTRL_ISC = 0x7 // Input/Sense Configuration + PIN4CTRL_PULLUPEN = 0x8 // Pullup enable + + // PIN5CTRL: Pin 5 Control + PIN5CTRL_INVEN = 0x80 // Inverted I/O Enable + PIN5CTRL_ISC = 0x7 // Input/Sense Configuration + PIN5CTRL_PULLUPEN = 0x8 // Pullup enable + + // PIN6CTRL: Pin 6 Control + PIN6CTRL_INVEN = 0x80 // Inverted I/O Enable + PIN6CTRL_ISC = 0x7 // Input/Sense Configuration + PIN6CTRL_PULLUPEN = 0x8 // Pullup enable + + // PIN7CTRL: Pin 7 Control + PIN7CTRL_INVEN = 0x80 // Inverted I/O Enable + PIN7CTRL_ISC = 0x7 // Input/Sense Configuration + PIN7CTRL_PULLUPEN = 0x8 // Pullup enable + + // PORTCTRL: Port Control + PORTCTRL_SRL = 0x1 // Slew Rate Limit Enable +) + +// Bitfields for PORTMUX: Port Multiplexer +const ( + // CCLROUTEA: Port Multiplexer CCL + CCLROUTEA_LUT0 = 0x1 // CCL LUT0 + CCLROUTEA_LUT1 = 0x2 // CCL LUT1 + CCLROUTEA_LUT2 = 0x4 // CCL LUT2 + CCLROUTEA_LUT3 = 0x8 // CCL LUT3 + + // EVSYSROUTEA: Port Multiplexer EVSYS + EVSYSROUTEA_EVOUT0 = 0x1 // Event Output 0 + EVSYSROUTEA_EVOUT1 = 0x2 // Event Output 1 + EVSYSROUTEA_EVOUT2 = 0x4 // Event Output 2 + EVSYSROUTEA_EVOUT3 = 0x8 // Event Output 3 + EVSYSROUTEA_EVOUT4 = 0x10 // Event Output 4 + EVSYSROUTEA_EVOUT5 = 0x20 // Event Output 5 + + // TCAROUTEA: Port Multiplexer TCA + TCAROUTEA_TCA0 = 0x7 // Port Multiplexer TCA0 + + // TCBROUTEA: Port Multiplexer TCB + TCBROUTEA_TCB0 = 0x1 // Port Multiplexer TCB0 + TCBROUTEA_TCB1 = 0x2 // Port Multiplexer TCB1 + TCBROUTEA_TCB2 = 0x4 // Port Multiplexer TCB2 + TCBROUTEA_TCB3 = 0x8 // Port Multiplexer TCB3 + + // TWISPIROUTEA: Port Multiplexer TWI and SPI + TWISPIROUTEA_SPI0 = 0x3 // Port Multiplexer SPI0 + TWISPIROUTEA_TWI0 = 0x30 // Port Multiplexer TWI0 + + // USARTROUTEA: Port Multiplexer USART register A + USARTROUTEA_USART0 = 0x3 // Port Multiplexer USART0 + USARTROUTEA_USART1 = 0xc // Port Multiplexer USART1 + USARTROUTEA_USART2 = 0x30 // Port Multiplexer USART2 + USARTROUTEA_USART3 = 0xc0 // Port Multiplexer USART3 +) + +// Bitfields for RSTCTRL: Reset controller +const ( + // RSTFR: Reset Flags + RSTFR_BORF = 0x2 // Brown out detector Reset flag + RSTFR_EXTRF = 0x4 // External Reset flag + RSTFR_PORF = 0x1 // Power on Reset flag + RSTFR_SWRF = 0x10 // Software Reset flag + RSTFR_UPDIRF = 0x20 // UPDI Reset flag + RSTFR_WDRF = 0x8 // Watch dog Reset flag + + // SWRR: Software Reset + SWRR_SWRE = 0x1 // Software reset enable +) + +// Bitfields for RTC: Real-Time Counter +const ( + // CLKSEL: Clock Select + CLKSEL_CLKSEL = 0x3 // Clock Select + + // PITCTRLA: PIT Control A + PITCTRLA_PERIOD = 0x78 // Period + PITCTRLA_PITEN = 0x1 // Enable + + // PITDBGCTRL: PIT Debug control + PITDBGCTRL_DBGRUN = 0x1 // Run in debug + + // PITINTCTRL: PIT Interrupt Control + PITINTCTRL_PI = 0x1 // Periodic Interrupt + + // PITINTFLAGS: PIT Interrupt Flags + PITINTFLAGS_PI = 0x1 // Periodic Interrupt + + // PITSTATUS: PIT Status + PITSTATUS_CTRLBUSY = 0x1 // CTRLA Synchronization Busy Flag +) + +// Bitfields for SYSCFG: System Configuration Registers +const ( + // EXTBRK: External Break + EXTBRK_ENEXTBRK = 0x1 // External break enable + + // OCDMS: OCD Message Status + OCDMS_OCDMR = 0x1 // OCD Message Read +) + +// Bitfields for TCA: 16-bit Timer/Counter Type A +const ( + // CTRLFCLR: Control F Clear + CTRLFCLR_CMP0BV = 0x2 // Compare 0 Buffer Valid + CTRLFCLR_CMP1BV = 0x4 // Compare 1 Buffer Valid + CTRLFCLR_CMP2BV = 0x8 // Compare 2 Buffer Valid + CTRLFCLR_PERBV = 0x1 // Period Buffer Valid + + // CTRLFSET: Control F Set + CTRLFSET_CMP0BV = 0x2 // Compare 0 Buffer Valid + CTRLFSET_CMP1BV = 0x4 // Compare 1 Buffer Valid + CTRLFSET_CMP2BV = 0x8 // Compare 2 Buffer Valid + CTRLFSET_PERBV = 0x1 // Period Buffer Valid +) + +// Bitfields for TWI: Two-Wire Interface +const ( + // BRIDGECTRL: Bridge Control + BRIDGECTRL_ENABLE = 0x1 // Bridge Enable + BRIDGECTRL_FMPEN = 0x2 // FM Plus Enable + BRIDGECTRL_SDAHOLD = 0xc // SDA Hold Time + + // MCTRLA: Master Control A + MCTRLA_ENABLE = 0x1 // Enable TWI Master + MCTRLA_QCEN = 0x10 // Quick Command Enable + MCTRLA_RIEN = 0x80 // Read Interrupt Enable + MCTRLA_SMEN = 0x2 // Smart Mode Enable + MCTRLA_TIMEOUT = 0xc // Inactive Bus Timeout + MCTRLA_WIEN = 0x40 // Write Interrupt Enable + + // MCTRLB: Master Control B + MCTRLB_ACKACT = 0x4 // Acknowledge Action + MCTRLB_FLUSH = 0x8 // Flush + MCTRLB_MCMD = 0x3 // Command + + // MSTATUS: Master Status + MSTATUS_ARBLOST = 0x8 // Arbitration Lost + MSTATUS_BUSERR = 0x4 // Bus Error + MSTATUS_BUSSTATE = 0x3 // Bus State + MSTATUS_CLKHOLD = 0x20 // Clock Hold + MSTATUS_RIF = 0x80 // Read Interrupt Flag + MSTATUS_RXACK = 0x10 // Received Acknowledge + MSTATUS_WIF = 0x40 // Write Interrupt Flag + + // SADDRMASK: Slave Address Mask + SADDRMASK_ADDREN = 0x1 // Address Enable + SADDRMASK_ADDRMASK = 0xfe // Address Mask + + // SCTRLA: Slave Control A + SCTRLA_APIEN = 0x40 // Address/Stop Interrupt Enable + SCTRLA_DIEN = 0x80 // Data Interrupt Enable + SCTRLA_ENABLE = 0x1 // Enable TWI Slave + SCTRLA_PIEN = 0x20 // Stop Interrupt Enable + SCTRLA_PMEN = 0x4 // Promiscuous Mode Enable + SCTRLA_SMEN = 0x2 // Smart Mode Enable + + // SCTRLB: Slave Control B + SCTRLB_ACKACT = 0x4 // Acknowledge Action + SCTRLB_SCMD = 0x3 // Command + + // SSTATUS: Slave Status + SSTATUS_AP = 0x1 // Slave Address or Stop + SSTATUS_APIF = 0x40 // Address/Stop Interrupt Flag + SSTATUS_BUSERR = 0x4 // Bus Error + SSTATUS_CLKHOLD = 0x20 // Clock Hold + SSTATUS_COLL = 0x8 // Collision + SSTATUS_DIF = 0x80 // Data Interrupt Flag + SSTATUS_DIR = 0x2 // Read/Write Direction + SSTATUS_RXACK = 0x10 // Received Acknowledge +) + +// Bitfields for USART: Universal Synchronous and Asynchronous Receiver and Transmitter +const ( + // RXDATAH: Receive Data High Byte + RXDATAH_BUFOVF = 0x40 // Buffer Overflow + RXDATAH_DATA8 = 0x1 // Receiver Data Register + RXDATAH_FERR = 0x4 // Frame Error + RXDATAH_PERR = 0x2 // Parity Error + RXDATAH_RXCIF = 0x80 // Receive Complete Interrupt Flag + + // RXDATAL: Receive Data Low Byte + RXDATAL_DATA = 0xff // RX Data + + // RXPLCTRL: IRCOM Receiver Pulse Length Control + RXPLCTRL_RXPL = 0x7f // Receiver Pulse Lenght + + // TXDATAH: Transmit Data High Byte + TXDATAH_DATA8 = 0x1 // Transmit Data Register (CHSIZE=9bit) + + // TXDATAL: Transmit Data Low Byte + TXDATAL_DATA = 0xff // Transmit Data Register + + // TXPLCTRL: IRCOM Transmitter Pulse Length Control + TXPLCTRL_TXPL = 0xff // Transmit pulse length +) diff --git a/src/device/avr/atmega3208.ld b/src/device/avr/atmega3208.ld new file mode 100644 index 00000000..518175ee --- /dev/null +++ b/src/device/avr/atmega3208.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega3208.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_size = 0x1000; +__num_isrs = 39; diff --git a/src/device/avr/atmega3209.go b/src/device/avr/atmega3209.go new file mode 100644 index 00000000..27b1e50c --- /dev/null +++ b/src/device/avr/atmega3209.go @@ -0,0 +1,1305 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega3209.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega3209 + +// Device information for the ATmega3209. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega3209" + ARCH = "AVR8X" + FAMILY = "AVR MEGA" +) + +// Interrupts +const ( + IRQ_NMI = 1 // + IRQ_VLM = 2 // + IRQ_CNT = 3 // + IRQ_PIT = 4 // + IRQ_CCL = 5 // + IRQ_PORT = 6 // + IRQ_LUNF = 7 // + IRQ_OVF = 7 // + IRQ_HUNF = 8 // + IRQ_LCMP0 = 9 // + IRQ_CMP0 = 9 // + IRQ_CMP1 = 10 // + IRQ_LCMP1 = 10 // + IRQ_CMP2 = 11 // + IRQ_LCMP2 = 11 // + IRQ_INT = 12 // + IRQ_INT = 13 // + IRQ_TWIS = 14 // + IRQ_TWIM = 15 // + IRQ_INT = 16 // + IRQ_RXC = 17 // + IRQ_DRE = 18 // + IRQ_TXC = 19 // + IRQ_PORT = 20 // + IRQ_AC = 21 // + IRQ_RESRDY = 22 // + IRQ_WCOMP = 23 // + IRQ_PORT = 24 // + IRQ_INT = 25 // + IRQ_RXC = 26 // + IRQ_DRE = 27 // + IRQ_TXC = 28 // + IRQ_PORT = 29 // + IRQ_EE = 30 // + IRQ_RXC = 31 // + IRQ_DRE = 32 // + IRQ_TXC = 33 // + IRQ_PORT = 34 // + IRQ_PORT = 35 // + IRQ_INT = 36 // + IRQ_RXC = 37 // + IRQ_DRE = 38 // + IRQ_TXC = 39 // + IRQ_max = 39 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Analog Comparator + AC = struct { + DACREF __reg + MUXCTRLA __reg + }{ + DACREF: 0x4, // Referance scale control + MUXCTRLA: 0x2, // Mux Control A + } + + // Analog to Digital Converter + ADC = struct { + COMMAND __reg + CTRLE __reg + MUXPOS __reg + RESL __reg + RESH __reg + SAMPCTRL __reg + WINHTL __reg + WINHTH __reg + WINLTL __reg + WINLTH __reg + }{ + COMMAND: 0x8, // Command + CTRLE: 0x4, // Control E + MUXPOS: 0x6, // Positive mux input + RESL: 0x10, // ADC Accumulator Result + RESH: 0x10, // ADC Accumulator Result + SAMPCTRL: 0x5, // Sample Control + WINHTL: 0x14, // Window comparator high threshold + WINHTH: 0x14, // Window comparator high threshold + WINLTL: 0x12, // Window comparator low threshold + WINLTH: 0x12, // Window comparator low threshold + } + + // Bod interface + BOD = struct { + VLMCTRLA __reg + }{ + VLMCTRLA: 0x8, // Voltage level monitor Control + } + + // Configurable Custom Logic + CCL = struct { + INTCTRL0 __reg + LUT0CTRLA __reg + LUT0CTRLB __reg + LUT0CTRLC __reg + LUT1CTRLA __reg + LUT1CTRLB __reg + LUT1CTRLC __reg + LUT2CTRLA __reg + LUT2CTRLB __reg + LUT2CTRLC __reg + LUT3CTRLA __reg + LUT3CTRLB __reg + LUT3CTRLC __reg + SEQCTRL0 __reg + TRUTH0 __reg + TRUTH1 __reg + TRUTH2 __reg + TRUTH3 __reg + }{ + INTCTRL0: 0x5, // Interrupt Control 0 + LUT0CTRLA: 0x8, // LUT Control 0 A + LUT0CTRLB: 0x9, // LUT Control 0 B + LUT0CTRLC: 0xa, // LUT Control 0 C + LUT1CTRLA: 0xc, // LUT Control 1 A + LUT1CTRLB: 0xd, // LUT Control 1 B + LUT1CTRLC: 0xe, // LUT Control 1 C + LUT2CTRLA: 0x10, // LUT Control 2 A + LUT2CTRLB: 0x11, // LUT Control 2 B + LUT2CTRLC: 0x12, // LUT Control 2 C + LUT3CTRLA: 0x14, // LUT Control 3 A + LUT3CTRLB: 0x15, // LUT Control 3 B + LUT3CTRLC: 0x16, // LUT Control 3 C + SEQCTRL0: 0x1, // Sequential Control 0 + TRUTH0: 0xb, // Truth 0 + TRUTH1: 0xf, // Truth 1 + TRUTH2: 0x13, // Truth 2 + TRUTH3: 0x17, // Truth 3 + } + + // Clock controller + CLKCTRL = struct { + MCLKCTRLA __reg + MCLKCTRLB __reg + MCLKLOCK __reg + MCLKSTATUS __reg + OSC20MCALIBA __reg + OSC20MCALIBB __reg + OSC20MCTRLA __reg + OSC32KCALIB __reg + OSC32KCTRLA __reg + XOSC32KCTRLA __reg + }{ + MCLKCTRLA: 0x0, // MCLK Control A + MCLKCTRLB: 0x1, // MCLK Control B + MCLKLOCK: 0x2, // MCLK Lock + MCLKSTATUS: 0x3, // MCLK Status + OSC20MCALIBA: 0x11, // OSC20M Calibration A + OSC20MCALIBB: 0x12, // OSC20M Calibration B + OSC20MCTRLA: 0x10, // OSC20M Control A + OSC32KCALIB: 0x19, // OSC32K Calibration + OSC32KCTRLA: 0x18, // OSC32K Control A + XOSC32KCTRLA: 0x1c, // XOSC32K Control A + } + + // CPU + CPU = struct { + CCP __reg + RAMPZ __reg + SPH __reg + SPL __reg + SREG __reg + }{ + CCP: 0x4, // Configuration Change Protection + RAMPZ: 0xb, // Extended Z-pointer Register + SPH: 0xe, // Stack Pointer High + SPL: 0xd, // Stack Pointer Low + SREG: 0xf, // Status Register + } + + // Interrupt Controller + CPUINT = struct { + LVL0PRI __reg + LVL1VEC __reg + }{ + LVL0PRI: 0x2, // Interrupt Level 0 Priority + LVL1VEC: 0x3, // Interrupt Level 1 Priority Vector + } + + // CRCSCAN + CRCSCAN = struct { + }{} + + // Event System + EVSYS = struct { + CHANNEL0 __reg + CHANNEL1 __reg + CHANNEL2 __reg + CHANNEL3 __reg + CHANNEL4 __reg + CHANNEL5 __reg + CHANNEL6 __reg + CHANNEL7 __reg + STROBE __reg + USERADC0 __reg + USERCCLLUT0A __reg + USERCCLLUT0B __reg + USERCCLLUT1A __reg + USERCCLLUT1B __reg + USERCCLLUT2A __reg + USERCCLLUT2B __reg + USERCCLLUT3A __reg + USERCCLLUT3B __reg + USEREVOUTA __reg + USEREVOUTB __reg + USEREVOUTC __reg + USEREVOUTD __reg + USEREVOUTE __reg + USEREVOUTF __reg + USERTCA0 __reg + USERTCB0 __reg + USERTCB1 __reg + USERTCB2 __reg + USERTCB3 __reg + USERUSART0 __reg + USERUSART1 __reg + USERUSART2 __reg + USERUSART3 __reg + }{ + CHANNEL0: 0x10, // Multiplexer Channel 0 + CHANNEL1: 0x11, // Multiplexer Channel 1 + CHANNEL2: 0x12, // Multiplexer Channel 2 + CHANNEL3: 0x13, // Multiplexer Channel 3 + CHANNEL4: 0x14, // Multiplexer Channel 4 + CHANNEL5: 0x15, // Multiplexer Channel 5 + CHANNEL6: 0x16, // Multiplexer Channel 6 + CHANNEL7: 0x17, // Multiplexer Channel 7 + STROBE: 0x0, // Channel Strobe + USERADC0: 0x28, // User ADC0 + USERCCLLUT0A: 0x20, // User CCL LUT0 Event A + USERCCLLUT0B: 0x21, // User CCL LUT0 Event B + USERCCLLUT1A: 0x22, // User CCL LUT1 Event A + USERCCLLUT1B: 0x23, // User CCL LUT1 Event B + USERCCLLUT2A: 0x24, // User CCL LUT2 Event A + USERCCLLUT2B: 0x25, // User CCL LUT2 Event B + USERCCLLUT3A: 0x26, // User CCL LUT3 Event A + USERCCLLUT3B: 0x27, // User CCL LUT3 Event B + USEREVOUTA: 0x29, // User EVOUT Port A + USEREVOUTB: 0x2a, // User EVOUT Port B + USEREVOUTC: 0x2b, // User EVOUT Port C + USEREVOUTD: 0x2c, // User EVOUT Port D + USEREVOUTE: 0x2d, // User EVOUT Port E + USEREVOUTF: 0x2e, // User EVOUT Port F + USERTCA0: 0x33, // User TCA0 + USERTCB0: 0x34, // User TCB0 + USERTCB1: 0x35, // User TCB1 + USERTCB2: 0x36, // User TCB2 + USERTCB3: 0x37, // User TCB3 + USERUSART0: 0x2f, // User USART0 + USERUSART1: 0x30, // User USART1 + USERUSART2: 0x31, // User USART2 + USERUSART3: 0x32, // User USART3 + } + + // Fuses + FUSE = struct { + APPEND __reg + BODCFG __reg + BOOTEND __reg + OSCCFG __reg + SYSCFG0 __reg + SYSCFG1 __reg + TCD0CFG __reg + WDTCFG __reg + }{ + APPEND: 0x7, // Application Code Section End + BODCFG: 0x1, // BOD Configuration + BOOTEND: 0x8, // Boot Section End + OSCCFG: 0x2, // Oscillator Configuration + SYSCFG0: 0x5, // System Configuration 0 + SYSCFG1: 0x6, // System Configuration 1 + TCD0CFG: 0x4, // TCD0 Configuration + WDTCFG: 0x0, // Watchdog Configuration + } + + // General Purpose IO + GPIO = struct { + GPIOR0 __reg + GPIOR1 __reg + GPIOR2 __reg + GPIOR3 __reg + }{ + GPIOR0: 0x0, // General Purpose IO Register 0 + GPIOR1: 0x1, // General Purpose IO Register 1 + GPIOR2: 0x2, // General Purpose IO Register 2 + GPIOR3: 0x3, // General Purpose IO Register 3 + } + + // Lockbit + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, // Lock Bits + } + + // BIST in the NVMCTRL module + NVMBIST = struct { + ADDRPAT __reg + DATAPAT __reg + }{ + ADDRPAT: 0x1, // Address pattern + DATAPAT: 0x2, // Data pattern + } + + // Non-volatile Memory Controller + NVMCTRL = struct { + ADDRL __reg + ADDRH __reg + }{ + ADDRL: 0x8, // Address + ADDRH: 0x8, // Address + } + + // I/O Ports + PORT = struct { + DIRCLR __reg + DIRSET __reg + DIRTGL __reg + OUTCLR __reg + OUTSET __reg + OUTTGL __reg + PIN0CTRL __reg + PIN1CTRL __reg + PIN2CTRL __reg + PIN3CTRL __reg + PIN4CTRL __reg + PIN5CTRL __reg + PIN6CTRL __reg + PIN7CTRL __reg + PORTCTRL __reg + }{ + DIRCLR: 0x2, // Data Direction Clear + DIRSET: 0x1, // Data Direction Set + DIRTGL: 0x3, // Data Direction Toggle + OUTCLR: 0x6, // Output Value Clear + OUTSET: 0x5, // Output Value Set + OUTTGL: 0x7, // Output Value Toggle + PIN0CTRL: 0x10, // Pin 0 Control + PIN1CTRL: 0x11, // Pin 1 Control + PIN2CTRL: 0x12, // Pin 2 Control + PIN3CTRL: 0x13, // Pin 3 Control + PIN4CTRL: 0x14, // Pin 4 Control + PIN5CTRL: 0x15, // Pin 5 Control + PIN6CTRL: 0x16, // Pin 6 Control + PIN7CTRL: 0x17, // Pin 7 Control + PORTCTRL: 0xa, // Port Control + } + + // Port Multiplexer + PORTMUX = struct { + CCLROUTEA __reg + EVSYSROUTEA __reg + TCAROUTEA __reg + TCBROUTEA __reg + TWISPIROUTEA __reg + USARTROUTEA __reg + }{ + CCLROUTEA: 0x1, // Port Multiplexer CCL + EVSYSROUTEA: 0x0, // Port Multiplexer EVSYS + TCAROUTEA: 0x4, // Port Multiplexer TCA + TCBROUTEA: 0x5, // Port Multiplexer TCB + TWISPIROUTEA: 0x3, // Port Multiplexer TWI and SPI + USARTROUTEA: 0x2, // Port Multiplexer USART register A + } + + // Reset controller + RSTCTRL = struct { + RSTFR __reg + SWRR __reg + }{ + RSTFR: 0x0, // Reset Flags + SWRR: 0x1, // Software Reset + } + + // Real-Time Counter + RTC = struct { + CLKSEL __reg + CMPL __reg + CMPH __reg + PITCTRLA __reg + PITDBGCTRL __reg + PITINTCTRL __reg + PITINTFLAGS __reg + PITSTATUS __reg + }{ + CLKSEL: 0x7, // Clock Select + CMPL: 0xc, // Compare + CMPH: 0xc, // Compare + PITCTRLA: 0x10, // PIT Control A + PITDBGCTRL: 0x15, // PIT Debug control + PITINTCTRL: 0x12, // PIT Interrupt Control + PITINTFLAGS: 0x13, // PIT Interrupt Flags + PITSTATUS: 0x11, // PIT Status + } + + // Signature row + SIGROW = struct { + CHECKSUM1 __reg + DEVICEID0 __reg + DEVICEID1 __reg + DEVICEID2 __reg + OSCCAL16M0 __reg + OSCCAL16M1 __reg + OSCCAL20M0 __reg + OSCCAL20M1 __reg + OSCCAL32K __reg + OSC16ERR3V __reg + OSC16ERR5V __reg + OSC20ERR3V __reg + OSC20ERR5V __reg + SERNUM0 __reg + SERNUM1 __reg + SERNUM2 __reg + SERNUM3 __reg + SERNUM4 __reg + SERNUM5 __reg + SERNUM6 __reg + SERNUM7 __reg + SERNUM8 __reg + SERNUM9 __reg + TEMPSENSE0 __reg + TEMPSENSE1 __reg + }{ + CHECKSUM1: 0x2f, // CRC Checksum Byte 1 + DEVICEID0: 0x0, // Device ID Byte 0 + DEVICEID1: 0x1, // Device ID Byte 1 + DEVICEID2: 0x2, // Device ID Byte 2 + OSCCAL16M0: 0x18, // Oscillator Calibration 16 MHz Byte 0 + OSCCAL16M1: 0x19, // Oscillator Calibration 16 MHz Byte 1 + OSCCAL20M0: 0x1a, // Oscillator Calibration 20 MHz Byte 0 + OSCCAL20M1: 0x1b, // Oscillator Calibration 20 MHz Byte 1 + OSCCAL32K: 0x14, // Oscillator Calibration for 32kHz ULP + OSC16ERR3V: 0x22, // OSC16 error at 3V + OSC16ERR5V: 0x23, // OSC16 error at 5V + OSC20ERR3V: 0x24, // OSC20 error at 3V + OSC20ERR5V: 0x25, // OSC20 error at 5V + SERNUM0: 0x3, // Serial Number Byte 0 + SERNUM1: 0x4, // Serial Number Byte 1 + SERNUM2: 0x5, // Serial Number Byte 2 + SERNUM3: 0x6, // Serial Number Byte 3 + SERNUM4: 0x7, // Serial Number Byte 4 + SERNUM5: 0x8, // Serial Number Byte 5 + SERNUM6: 0x9, // Serial Number Byte 6 + SERNUM7: 0xa, // Serial Number Byte 7 + SERNUM8: 0xb, // Serial Number Byte 8 + SERNUM9: 0xc, // Serial Number Byte 9 + TEMPSENSE0: 0x20, // Temperature Sensor Calibration Byte 0 + TEMPSENSE1: 0x21, // Temperature Sensor Calibration Byte 1 + } + + // Sleep Controller + SLPCTRL = struct { + }{} + + // Serial Peripheral Interface + SPI = struct { + }{} + + // System Configuration Registers + SYSCFG = struct { + EXTBRK __reg + OCDM __reg + OCDMS __reg + REVID __reg + }{ + EXTBRK: 0x2, // External Break + OCDM: 0x18, // OCD Message Register + OCDMS: 0x19, // OCD Message Status + REVID: 0x1, // Revision ID + } + + // 16-bit Timer/Counter Type A + TCA = struct { + CMP0L __reg + CMP0H __reg + CMP0BUFL __reg + CMP0BUFH __reg + CMP1L __reg + CMP1H __reg + CMP1BUFL __reg + CMP1BUFH __reg + CMP2L __reg + CMP2H __reg + CMP2BUFL __reg + CMP2BUFH __reg + CTRLFCLR __reg + CTRLFSET __reg + PERBUFL __reg + PERBUFH __reg + HCMP0 __reg + HCMP1 __reg + HCMP2 __reg + HCNT __reg + HPER __reg + LCMP0 __reg + LCMP1 __reg + LCMP2 __reg + LCNT __reg + LPER __reg + }{ + CMP0L: 0x28, // Compare 0 + CMP0H: 0x28, // Compare 0 + CMP0BUFL: 0x38, // Compare 0 Buffer + CMP0BUFH: 0x38, // Compare 0 Buffer + CMP1L: 0x2a, // Compare 1 + CMP1H: 0x2a, // Compare 1 + CMP1BUFL: 0x3a, // Compare 1 Buffer + CMP1BUFH: 0x3a, // Compare 1 Buffer + CMP2L: 0x2c, // Compare 2 + CMP2H: 0x2c, // Compare 2 + CMP2BUFL: 0x3c, // Compare 2 Buffer + CMP2BUFH: 0x3c, // Compare 2 Buffer + CTRLFCLR: 0x6, // Control F Clear + CTRLFSET: 0x7, // Control F Set + PERBUFL: 0x36, // Period Buffer + PERBUFH: 0x36, // Period Buffer + HCMP0: 0x29, // High Compare + HCMP1: 0x2b, // High Compare + HCMP2: 0x2d, // High Compare + HCNT: 0x21, // High Count + HPER: 0x27, // High Period + LCMP0: 0x28, // Low Compare + LCMP1: 0x2a, // Low Compare + LCMP2: 0x2c, // Low Compare + LCNT: 0x20, // Low Count + LPER: 0x26, // Low Period + } + + // 16-bit Timer Type B + TCB = struct { + CCMPL __reg + CCMPH __reg + }{ + CCMPL: 0xc, // Compare or Capture + CCMPH: 0xc, // Compare or Capture + } + + // Two-Wire Interface + TWI = struct { + BRIDGECTRL __reg + MADDR __reg + MBAUD __reg + MCTRLA __reg + MCTRLB __reg + MDATA __reg + MSTATUS __reg + SADDR __reg + SADDRMASK __reg + SCTRLA __reg + SCTRLB __reg + SDATA __reg + SSTATUS __reg + }{ + BRIDGECTRL: 0x1, // Bridge Control + MADDR: 0x7, // Master Address + MBAUD: 0x6, // Master Baurd Rate Control + MCTRLA: 0x3, // Master Control A + MCTRLB: 0x4, // Master Control B + MDATA: 0x8, // Master Data + MSTATUS: 0x5, // Master Status + SADDR: 0xc, // Slave Address + SADDRMASK: 0xe, // Slave Address Mask + SCTRLA: 0x9, // Slave Control A + SCTRLB: 0xa, // Slave Control B + SDATA: 0xd, // Slave Data + SSTATUS: 0xb, // Slave Status + } + + // Universal Synchronous and Asynchronous Receiver and Transmitter + USART = struct { + BAUDL __reg + BAUDH __reg + RXDATAH __reg + RXDATAL __reg + RXPLCTRL __reg + TXDATAH __reg + TXDATAL __reg + TXPLCTRL __reg + }{ + BAUDL: 0x8, // Baud Rate + BAUDH: 0x8, // Baud Rate + RXDATAH: 0x1, // Receive Data High Byte + RXDATAL: 0x0, // Receive Data Low Byte + RXPLCTRL: 0xe, // IRCOM Receiver Pulse Length Control + TXDATAH: 0x3, // Transmit Data High Byte + TXDATAL: 0x2, // Transmit Data Low Byte + TXPLCTRL: 0xd, // IRCOM Transmitter Pulse Length Control + } + + // User Row + USERROW = struct { + USERROW0 __reg + USERROW1 __reg + USERROW2 __reg + USERROW3 __reg + USERROW4 __reg + USERROW5 __reg + USERROW6 __reg + USERROW7 __reg + USERROW8 __reg + USERROW9 __reg + USERROW10 __reg + USERROW11 __reg + USERROW12 __reg + USERROW13 __reg + USERROW14 __reg + USERROW15 __reg + USERROW16 __reg + USERROW17 __reg + USERROW18 __reg + USERROW19 __reg + USERROW20 __reg + USERROW21 __reg + USERROW22 __reg + USERROW23 __reg + USERROW24 __reg + USERROW25 __reg + USERROW26 __reg + USERROW27 __reg + USERROW28 __reg + USERROW29 __reg + USERROW30 __reg + USERROW31 __reg + USERROW32 __reg + USERROW33 __reg + USERROW34 __reg + USERROW35 __reg + USERROW36 __reg + USERROW37 __reg + USERROW38 __reg + USERROW39 __reg + USERROW40 __reg + USERROW41 __reg + USERROW42 __reg + USERROW43 __reg + USERROW44 __reg + USERROW45 __reg + USERROW46 __reg + USERROW47 __reg + USERROW48 __reg + USERROW49 __reg + USERROW50 __reg + USERROW51 __reg + USERROW52 __reg + USERROW53 __reg + USERROW54 __reg + USERROW55 __reg + USERROW56 __reg + USERROW57 __reg + USERROW58 __reg + USERROW59 __reg + USERROW60 __reg + USERROW61 __reg + USERROW62 __reg + USERROW63 __reg + }{ + USERROW0: 0x0, // User Row Byte 0 + USERROW1: 0x1, // User Row Byte 1 + USERROW2: 0x2, // User Row Byte 2 + USERROW3: 0x3, // User Row Byte 3 + USERROW4: 0x4, // User Row Byte 4 + USERROW5: 0x5, // User Row Byte 5 + USERROW6: 0x6, // User Row Byte 6 + USERROW7: 0x7, // User Row Byte 7 + USERROW8: 0x8, // User Row Byte 8 + USERROW9: 0x9, // User Row Byte 9 + USERROW10: 0xa, // User Row Byte 10 + USERROW11: 0xb, // User Row Byte 11 + USERROW12: 0xc, // User Row Byte 12 + USERROW13: 0xd, // User Row Byte 13 + USERROW14: 0xe, // User Row Byte 14 + USERROW15: 0xf, // User Row Byte 15 + USERROW16: 0x10, // User Row Byte 16 + USERROW17: 0x11, // User Row Byte 17 + USERROW18: 0x12, // User Row Byte 18 + USERROW19: 0x13, // User Row Byte 19 + USERROW20: 0x14, // User Row Byte 20 + USERROW21: 0x15, // User Row Byte 21 + USERROW22: 0x16, // User Row Byte 22 + USERROW23: 0x17, // User Row Byte 23 + USERROW24: 0x18, // User Row Byte 24 + USERROW25: 0x19, // User Row Byte 25 + USERROW26: 0x1a, // User Row Byte 26 + USERROW27: 0x1b, // User Row Byte 27 + USERROW28: 0x1c, // User Row Byte 28 + USERROW29: 0x1d, // User Row Byte 29 + USERROW30: 0x1e, // User Row Byte 30 + USERROW31: 0x1f, // User Row Byte 31 + USERROW32: 0x20, // User Row Byte 32 + USERROW33: 0x21, // User Row Byte 33 + USERROW34: 0x22, // User Row Byte 34 + USERROW35: 0x23, // User Row Byte 35 + USERROW36: 0x24, // User Row Byte 36 + USERROW37: 0x25, // User Row Byte 37 + USERROW38: 0x26, // User Row Byte 38 + USERROW39: 0x27, // User Row Byte 39 + USERROW40: 0x28, // User Row Byte 40 + USERROW41: 0x29, // User Row Byte 41 + USERROW42: 0x2a, // User Row Byte 42 + USERROW43: 0x2b, // User Row Byte 43 + USERROW44: 0x2c, // User Row Byte 44 + USERROW45: 0x2d, // User Row Byte 45 + USERROW46: 0x2e, // User Row Byte 46 + USERROW47: 0x2f, // User Row Byte 47 + USERROW48: 0x30, // User Row Byte 48 + USERROW49: 0x31, // User Row Byte 49 + USERROW50: 0x32, // User Row Byte 50 + USERROW51: 0x33, // User Row Byte 51 + USERROW52: 0x34, // User Row Byte 52 + USERROW53: 0x35, // User Row Byte 53 + USERROW54: 0x36, // User Row Byte 54 + USERROW55: 0x37, // User Row Byte 55 + USERROW56: 0x38, // User Row Byte 56 + USERROW57: 0x39, // User Row Byte 57 + USERROW58: 0x3a, // User Row Byte 58 + USERROW59: 0x3b, // User Row Byte 59 + USERROW60: 0x3c, // User Row Byte 60 + USERROW61: 0x3d, // User Row Byte 61 + USERROW62: 0x3e, // User Row Byte 62 + USERROW63: 0x3f, // User Row Byte 63 + } + + // Virtual Ports + VPORT = struct { + }{} + + // Voltage reference + VREF = struct { + }{} + + // Watch-Dog Timer + WDT = struct { + }{} +) + +// Bitfields for AC: Analog Comparator +const ( + // DACREF: Referance scale control + DACREF_DATA = 0xff // DAC voltage reference + + // MUXCTRLA: Mux Control A + MUXCTRLA_INVERT = 0x80 // Invert AC Output + MUXCTRLA_MUXNEG = 0x3 // Negative Input MUX Selection + MUXCTRLA_MUXPOS = 0x18 // Positive Input MUX Selection +) + +// Bitfields for ADC: Analog to Digital Converter +const ( + // COMMAND: Command + COMMAND_STCONV = 0x1 // Start Conversion Operation + + // CTRLE: Control E + CTRLE_WINCM = 0x7 // Window Comparator Mode + + // MUXPOS: Positive mux input + MUXPOS_MUXPOS = 0x1f // Analog Channel Selection Bits + + // SAMPCTRL: Sample Control + SAMPCTRL_SAMPLEN = 0x1f // Sample lenght +) + +// Bitfields for BOD: Bod interface +const ( + // VLMCTRLA: Voltage level monitor Control + VLMCTRLA_VLMLVL = 0x3 // voltage level monitor level +) + +// Bitfields for CCL: Configurable Custom Logic +const ( + // INTCTRL0: Interrupt Control 0 + INTCTRL0_INTMODE0 = 0x3 // Interrupt Mode for LUT0 + INTCTRL0_INTMODE1 = 0xc // Interrupt Mode for LUT1 + INTCTRL0_INTMODE2 = 0x30 // Interrupt Mode for LUT2 + INTCTRL0_INTMODE3 = 0xc0 // Interrupt Mode for LUT3 + + // LUT0CTRLA: LUT Control 0 A + LUT0CTRLA_CLKSRC = 0xe // Clock Source Selection + LUT0CTRLA_EDGEDET = 0x80 // Edge Detection Enable + LUT0CTRLA_ENABLE = 0x1 // LUT Enable + LUT0CTRLA_FILTSEL = 0x30 // Filter Selection + LUT0CTRLA_OUTEN = 0x40 // Output Enable + + // LUT0CTRLB: LUT Control 0 B + LUT0CTRLB_INSEL0 = 0xf // LUT Input 0 Source Selection + LUT0CTRLB_INSEL1 = 0xf0 // LUT Input 1 Source Selection + + // LUT0CTRLC: LUT Control 0 C + LUT0CTRLC_INSEL2 = 0xf // LUT Input 2 Source Selection + + // LUT1CTRLA: LUT Control 1 A + LUT1CTRLA_CLKSRC = 0xe // Clock Source Selection + LUT1CTRLA_EDGEDET = 0x80 // Edge Detection Enable + LUT1CTRLA_ENABLE = 0x1 // LUT Enable + LUT1CTRLA_FILTSEL = 0x30 // Filter Selection + LUT1CTRLA_OUTEN = 0x40 // Output Enable + + // LUT1CTRLB: LUT Control 1 B + LUT1CTRLB_INSEL0 = 0xf // LUT Input 0 Source Selection + LUT1CTRLB_INSEL1 = 0xf0 // LUT Input 1 Source Selection + + // LUT1CTRLC: LUT Control 1 C + LUT1CTRLC_INSEL2 = 0xf // LUT Input 2 Source Selection + + // LUT2CTRLA: LUT Control 2 A + LUT2CTRLA_CLKSRC = 0xe // Clock Source Selection + LUT2CTRLA_EDGEDET = 0x80 // Edge Detection Enable + LUT2CTRLA_ENABLE = 0x1 // LUT Enable + LUT2CTRLA_FILTSEL = 0x30 // Filter Selection + LUT2CTRLA_OUTEN = 0x40 // Output Enable + + // LUT2CTRLB: LUT Control 2 B + LUT2CTRLB_INSEL0 = 0xf // LUT Input 0 Source Selection + LUT2CTRLB_INSEL1 = 0xf0 // LUT Input 1 Source Selection + + // LUT2CTRLC: LUT Control 2 C + LUT2CTRLC_INSEL2 = 0xf // LUT Input 2 Source Selection + + // LUT3CTRLA: LUT Control 3 A + LUT3CTRLA_CLKSRC = 0xe // Clock Source Selection + LUT3CTRLA_EDGEDET = 0x80 // Edge Detection Enable + LUT3CTRLA_ENABLE = 0x1 // LUT Enable + LUT3CTRLA_FILTSEL = 0x30 // Filter Selection + LUT3CTRLA_OUTEN = 0x40 // Output Enable + + // LUT3CTRLB: LUT Control 3 B + LUT3CTRLB_INSEL0 = 0xf // LUT Input 0 Source Selection + LUT3CTRLB_INSEL1 = 0xf0 // LUT Input 1 Source Selection + + // LUT3CTRLC: LUT Control 3 C + LUT3CTRLC_INSEL2 = 0xf // LUT Input 2 Source Selection + + // SEQCTRL0: Sequential Control 0 + SEQCTRL0_SEQSEL = 0x7 // Sequential Selection +) + +// Bitfields for CLKCTRL: Clock controller +const ( + // MCLKCTRLA: MCLK Control A + MCLKCTRLA_CLKOUT = 0x80 // System clock out + MCLKCTRLA_CLKSEL = 0x3 // clock select + + // MCLKCTRLB: MCLK Control B + MCLKCTRLB_PDIV = 0x1e // Prescaler division + MCLKCTRLB_PEN = 0x1 // Prescaler enable + + // MCLKLOCK: MCLK Lock + MCLKLOCK_LOCKEN = 0x1 // lock ebable + + // MCLKSTATUS: MCLK Status + MCLKSTATUS_EXTS = 0x80 // External Clock status + MCLKSTATUS_OSC20MS = 0x10 // 20MHz oscillator status + MCLKSTATUS_OSC32KS = 0x20 // 32KHz oscillator status + MCLKSTATUS_SOSC = 0x1 // System Oscillator changing + MCLKSTATUS_XOSC32KS = 0x40 // 32.768 kHz Crystal Oscillator status + + // OSC20MCALIBA: OSC20M Calibration A + OSC20MCALIBA_CALSEL20M = 0x80 // Calibration freq select + OSC20MCALIBA_CAL20M = 0x7f // Calibration + + // OSC20MCALIBB: OSC20M Calibration B + OSC20MCALIBB_LOCK = 0x80 // Lock + OSC20MCALIBB_TEMPCAL20M = 0xf // Oscillator temperature coefficient + + // OSC20MCTRLA: OSC20M Control A + OSC20MCTRLA_RUNSTDBY = 0x2 // Run standby + + // OSC32KCALIB: OSC32K Calibration + OSC32KCALIB_CAL32K = 0x3f // Calibration + + // OSC32KCTRLA: OSC32K Control A + OSC32KCTRLA_RUNSTDBY = 0x2 // Run standby + + // XOSC32KCTRLA: XOSC32K Control A + XOSC32KCTRLA_CSUT = 0x30 // Crystal startup time + XOSC32KCTRLA_ENABLE = 0x1 // Enable + XOSC32KCTRLA_RUNSTDBY = 0x2 // Run standby + XOSC32KCTRLA_SEL = 0x4 // Select +) + +// Bitfields for CPU: CPU +const ( + // CCP: Configuration Change Protection + CCP_CCP = 0xff // CCP signature + + // SREG: Status Register + SREG_C = 0x1 // Carry Flag + SREG_H = 0x20 // Half Carry Flag + SREG_I = 0x80 // Global Interrupt Enable Flag + SREG_N = 0x4 // Negative Flag + SREG_S = 0x10 // N Exclusive Or V Flag + SREG_T = 0x40 // Transfer Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_Z = 0x2 // Zero Flag +) + +// Bitfields for CPUINT: Interrupt Controller +const ( + // LVL0PRI: Interrupt Level 0 Priority + LVL0PRI_LVL0PRI = 0xff // Interrupt Level Priority + + // LVL1VEC: Interrupt Level 1 Priority Vector + LVL1VEC_LVL1VEC = 0xff // Interrupt Vector with High Priority +) + +// Bitfields for EVSYS: Event System +const ( + // CHANNEL0: Multiplexer Channel 0 + CHANNEL0_GENERATOR = 0xff // Generator selector + + // CHANNEL1: Multiplexer Channel 1 + CHANNEL1_GENERATOR = 0xff // Generator selector + + // CHANNEL2: Multiplexer Channel 2 + CHANNEL2_GENERATOR = 0xff // Generator selector + + // CHANNEL3: Multiplexer Channel 3 + CHANNEL3_GENERATOR = 0xff // Generator selector + + // CHANNEL4: Multiplexer Channel 4 + CHANNEL4_GENERATOR = 0xff // Generator selector + + // CHANNEL5: Multiplexer Channel 5 + CHANNEL5_GENERATOR = 0xff // Generator selector + + // CHANNEL6: Multiplexer Channel 6 + CHANNEL6_GENERATOR = 0xff // Generator selector + + // CHANNEL7: Multiplexer Channel 7 + CHANNEL7_GENERATOR = 0xff // Generator selector + + // STROBE: Channel Strobe + STROBE_STROBE0 = 0xff // Software event on channels + + // USERADC0: User ADC0 + USERADC0_CHANNEL = 0xff // Channel selector + + // USERCCLLUT0A: User CCL LUT0 Event A + USERCCLLUT0A_CHANNEL = 0xff // Channel selector + + // USERCCLLUT0B: User CCL LUT0 Event B + USERCCLLUT0B_CHANNEL = 0xff // Channel selector + + // USERCCLLUT1A: User CCL LUT1 Event A + USERCCLLUT1A_CHANNEL = 0xff // Channel selector + + // USERCCLLUT1B: User CCL LUT1 Event B + USERCCLLUT1B_CHANNEL = 0xff // Channel selector + + // USERCCLLUT2A: User CCL LUT2 Event A + USERCCLLUT2A_CHANNEL = 0xff // Channel selector + + // USERCCLLUT2B: User CCL LUT2 Event B + USERCCLLUT2B_CHANNEL = 0xff // Channel selector + + // USERCCLLUT3A: User CCL LUT3 Event A + USERCCLLUT3A_CHANNEL = 0xff // Channel selector + + // USERCCLLUT3B: User CCL LUT3 Event B + USERCCLLUT3B_CHANNEL = 0xff // Channel selector + + // USEREVOUTA: User EVOUT Port A + USEREVOUTA_CHANNEL = 0xff // Channel selector + + // USEREVOUTB: User EVOUT Port B + USEREVOUTB_CHANNEL = 0xff // Channel selector + + // USEREVOUTC: User EVOUT Port C + USEREVOUTC_CHANNEL = 0xff // Channel selector + + // USEREVOUTD: User EVOUT Port D + USEREVOUTD_CHANNEL = 0xff // Channel selector + + // USEREVOUTE: User EVOUT Port E + USEREVOUTE_CHANNEL = 0xff // Channel selector + + // USEREVOUTF: User EVOUT Port F + USEREVOUTF_CHANNEL = 0xff // Channel selector + + // USERTCA0: User TCA0 + USERTCA0_CHANNEL = 0xff // Channel selector + + // USERTCB0: User TCB0 + USERTCB0_CHANNEL = 0xff // Channel selector + + // USERTCB1: User TCB1 + USERTCB1_CHANNEL = 0xff // Channel selector + + // USERTCB2: User TCB2 + USERTCB2_CHANNEL = 0xff // Channel selector + + // USERTCB3: User TCB3 + USERTCB3_CHANNEL = 0xff // Channel selector + + // USERUSART0: User USART0 + USERUSART0_CHANNEL = 0xff // Channel selector + + // USERUSART1: User USART1 + USERUSART1_CHANNEL = 0xff // Channel selector + + // USERUSART2: User USART2 + USERUSART2_CHANNEL = 0xff // Channel selector + + // USERUSART3: User USART3 + USERUSART3_CHANNEL = 0xff // Channel selector +) + +// Bitfields for FUSE: Fuses +const ( + // BODCFG: BOD Configuration + BODCFG_ACTIVE = 0xc // BOD Operation in Active Mode + BODCFG_LVL = 0xe0 // BOD Level + BODCFG_SAMPFREQ = 0x10 // BOD Sample Frequency + BODCFG_SLEEP = 0x3 // BOD Operation in Sleep Mode + + // OSCCFG: Oscillator Configuration + OSCCFG_FREQSEL = 0x3 // Frequency Select + OSCCFG_OSCLOCK = 0x80 // Oscillator Lock + + // SYSCFG0: System Configuration 0 + SYSCFG0_CRCSRC = 0xc0 // CRC Source + SYSCFG0_EESAVE = 0x1 // EEPROM Save + SYSCFG0_RSTPINCFG = 0x8 // Reset Pin Configuration + + // SYSCFG1: System Configuration 1 + SYSCFG1_SUT = 0x7 // Startup Time + + // TCD0CFG: TCD0 Configuration + TCD0CFG_CMPA = 0x1 // Compare A Default Output Value + TCD0CFG_CMPAEN = 0x10 // Compare A Output Enable + TCD0CFG_CMPB = 0x2 // Compare B Default Output Value + TCD0CFG_CMPBEN = 0x20 // Compare B Output Enable + TCD0CFG_CMPC = 0x4 // Compare C Default Output Value + TCD0CFG_CMPCEN = 0x40 // Compare C Output Enable + TCD0CFG_CMPD = 0x8 // Compare D Default Output Value + TCD0CFG_CMPDEN = 0x80 // Compare D Output Enable + + // WDTCFG: Watchdog Configuration + WDTCFG_PERIOD = 0xf // Watchdog Timeout Period + WDTCFG_WINDOW = 0xf0 // Watchdog Window Timeout Period +) + +// Bitfields for LOCKBIT: Lockbit +const ( + // LOCKBIT: Lock Bits + LOCKBIT_LB = 0xff // Lock Bits +) + +// Bitfields for NVMBIST: BIST in the NVMCTRL module +const ( + // ADDRPAT: Address pattern + ADDRPAT_AMODE = 0x70 // Address mode + ADDRPAT_XMODE = 0x3 // X address mode + ADDRPAT_YMODE = 0xc // Y address mode + + // DATAPAT: Data pattern + DATAPAT_PATTERN = 0x3 // Data check pattern + END_END = 0xffffff +) + +// Bitfields for PORT: I/O Ports +const ( + // PIN0CTRL: Pin 0 Control + PIN0CTRL_INVEN = 0x80 // Inverted I/O Enable + PIN0CTRL_ISC = 0x7 // Input/Sense Configuration + PIN0CTRL_PULLUPEN = 0x8 // Pullup enable + + // PIN1CTRL: Pin 1 Control + PIN1CTRL_INVEN = 0x80 // Inverted I/O Enable + PIN1CTRL_ISC = 0x7 // Input/Sense Configuration + PIN1CTRL_PULLUPEN = 0x8 // Pullup enable + + // PIN2CTRL: Pin 2 Control + PIN2CTRL_INVEN = 0x80 // Inverted I/O Enable + PIN2CTRL_ISC = 0x7 // Input/Sense Configuration + PIN2CTRL_PULLUPEN = 0x8 // Pullup enable + + // PIN3CTRL: Pin 3 Control + PIN3CTRL_INVEN = 0x80 // Inverted I/O Enable + PIN3CTRL_ISC = 0x7 // Input/Sense Configuration + PIN3CTRL_PULLUPEN = 0x8 // Pullup enable + + // PIN4CTRL: Pin 4 Control + PIN4CTRL_INVEN = 0x80 // Inverted I/O Enable + PIN4CTRL_ISC = 0x7 // Input/Sense Configuration + PIN4CTRL_PULLUPEN = 0x8 // Pullup enable + + // PIN5CTRL: Pin 5 Control + PIN5CTRL_INVEN = 0x80 // Inverted I/O Enable + PIN5CTRL_ISC = 0x7 // Input/Sense Configuration + PIN5CTRL_PULLUPEN = 0x8 // Pullup enable + + // PIN6CTRL: Pin 6 Control + PIN6CTRL_INVEN = 0x80 // Inverted I/O Enable + PIN6CTRL_ISC = 0x7 // Input/Sense Configuration + PIN6CTRL_PULLUPEN = 0x8 // Pullup enable + + // PIN7CTRL: Pin 7 Control + PIN7CTRL_INVEN = 0x80 // Inverted I/O Enable + PIN7CTRL_ISC = 0x7 // Input/Sense Configuration + PIN7CTRL_PULLUPEN = 0x8 // Pullup enable + + // PORTCTRL: Port Control + PORTCTRL_SRL = 0x1 // Slew Rate Limit Enable +) + +// Bitfields for PORTMUX: Port Multiplexer +const ( + // CCLROUTEA: Port Multiplexer CCL + CCLROUTEA_LUT0 = 0x1 // CCL LUT0 + CCLROUTEA_LUT1 = 0x2 // CCL LUT1 + CCLROUTEA_LUT2 = 0x4 // CCL LUT2 + CCLROUTEA_LUT3 = 0x8 // CCL LUT3 + + // EVSYSROUTEA: Port Multiplexer EVSYS + EVSYSROUTEA_EVOUT0 = 0x1 // Event Output 0 + EVSYSROUTEA_EVOUT1 = 0x2 // Event Output 1 + EVSYSROUTEA_EVOUT2 = 0x4 // Event Output 2 + EVSYSROUTEA_EVOUT3 = 0x8 // Event Output 3 + EVSYSROUTEA_EVOUT4 = 0x10 // Event Output 4 + EVSYSROUTEA_EVOUT5 = 0x20 // Event Output 5 + + // TCAROUTEA: Port Multiplexer TCA + TCAROUTEA_TCA0 = 0x7 // Port Multiplexer TCA0 + + // TCBROUTEA: Port Multiplexer TCB + TCBROUTEA_TCB0 = 0x1 // Port Multiplexer TCB0 + TCBROUTEA_TCB1 = 0x2 // Port Multiplexer TCB1 + TCBROUTEA_TCB2 = 0x4 // Port Multiplexer TCB2 + TCBROUTEA_TCB3 = 0x8 // Port Multiplexer TCB3 + + // TWISPIROUTEA: Port Multiplexer TWI and SPI + TWISPIROUTEA_SPI0 = 0x3 // Port Multiplexer SPI0 + TWISPIROUTEA_TWI0 = 0x30 // Port Multiplexer TWI0 + + // USARTROUTEA: Port Multiplexer USART register A + USARTROUTEA_USART0 = 0x3 // Port Multiplexer USART0 + USARTROUTEA_USART1 = 0xc // Port Multiplexer USART1 + USARTROUTEA_USART2 = 0x30 // Port Multiplexer USART2 + USARTROUTEA_USART3 = 0xc0 // Port Multiplexer USART3 +) + +// Bitfields for RSTCTRL: Reset controller +const ( + // RSTFR: Reset Flags + RSTFR_BORF = 0x2 // Brown out detector Reset flag + RSTFR_EXTRF = 0x4 // External Reset flag + RSTFR_PORF = 0x1 // Power on Reset flag + RSTFR_SWRF = 0x10 // Software Reset flag + RSTFR_UPDIRF = 0x20 // UPDI Reset flag + RSTFR_WDRF = 0x8 // Watch dog Reset flag + + // SWRR: Software Reset + SWRR_SWRE = 0x1 // Software reset enable +) + +// Bitfields for RTC: Real-Time Counter +const ( + // CLKSEL: Clock Select + CLKSEL_CLKSEL = 0x3 // Clock Select + + // PITCTRLA: PIT Control A + PITCTRLA_PERIOD = 0x78 // Period + PITCTRLA_PITEN = 0x1 // Enable + + // PITDBGCTRL: PIT Debug control + PITDBGCTRL_DBGRUN = 0x1 // Run in debug + + // PITINTCTRL: PIT Interrupt Control + PITINTCTRL_PI = 0x1 // Periodic Interrupt + + // PITINTFLAGS: PIT Interrupt Flags + PITINTFLAGS_PI = 0x1 // Periodic Interrupt + + // PITSTATUS: PIT Status + PITSTATUS_CTRLBUSY = 0x1 // CTRLA Synchronization Busy Flag +) + +// Bitfields for SYSCFG: System Configuration Registers +const ( + // EXTBRK: External Break + EXTBRK_ENEXTBRK = 0x1 // External break enable + + // OCDMS: OCD Message Status + OCDMS_OCDMR = 0x1 // OCD Message Read +) + +// Bitfields for TCA: 16-bit Timer/Counter Type A +const ( + // CTRLFCLR: Control F Clear + CTRLFCLR_CMP0BV = 0x2 // Compare 0 Buffer Valid + CTRLFCLR_CMP1BV = 0x4 // Compare 1 Buffer Valid + CTRLFCLR_CMP2BV = 0x8 // Compare 2 Buffer Valid + CTRLFCLR_PERBV = 0x1 // Period Buffer Valid + + // CTRLFSET: Control F Set + CTRLFSET_CMP0BV = 0x2 // Compare 0 Buffer Valid + CTRLFSET_CMP1BV = 0x4 // Compare 1 Buffer Valid + CTRLFSET_CMP2BV = 0x8 // Compare 2 Buffer Valid + CTRLFSET_PERBV = 0x1 // Period Buffer Valid +) + +// Bitfields for TWI: Two-Wire Interface +const ( + // BRIDGECTRL: Bridge Control + BRIDGECTRL_ENABLE = 0x1 // Bridge Enable + BRIDGECTRL_FMPEN = 0x2 // FM Plus Enable + BRIDGECTRL_SDAHOLD = 0xc // SDA Hold Time + + // MCTRLA: Master Control A + MCTRLA_ENABLE = 0x1 // Enable TWI Master + MCTRLA_QCEN = 0x10 // Quick Command Enable + MCTRLA_RIEN = 0x80 // Read Interrupt Enable + MCTRLA_SMEN = 0x2 // Smart Mode Enable + MCTRLA_TIMEOUT = 0xc // Inactive Bus Timeout + MCTRLA_WIEN = 0x40 // Write Interrupt Enable + + // MCTRLB: Master Control B + MCTRLB_ACKACT = 0x4 // Acknowledge Action + MCTRLB_FLUSH = 0x8 // Flush + MCTRLB_MCMD = 0x3 // Command + + // MSTATUS: Master Status + MSTATUS_ARBLOST = 0x8 // Arbitration Lost + MSTATUS_BUSERR = 0x4 // Bus Error + MSTATUS_BUSSTATE = 0x3 // Bus State + MSTATUS_CLKHOLD = 0x20 // Clock Hold + MSTATUS_RIF = 0x80 // Read Interrupt Flag + MSTATUS_RXACK = 0x10 // Received Acknowledge + MSTATUS_WIF = 0x40 // Write Interrupt Flag + + // SADDRMASK: Slave Address Mask + SADDRMASK_ADDREN = 0x1 // Address Enable + SADDRMASK_ADDRMASK = 0xfe // Address Mask + + // SCTRLA: Slave Control A + SCTRLA_APIEN = 0x40 // Address/Stop Interrupt Enable + SCTRLA_DIEN = 0x80 // Data Interrupt Enable + SCTRLA_ENABLE = 0x1 // Enable TWI Slave + SCTRLA_PIEN = 0x20 // Stop Interrupt Enable + SCTRLA_PMEN = 0x4 // Promiscuous Mode Enable + SCTRLA_SMEN = 0x2 // Smart Mode Enable + + // SCTRLB: Slave Control B + SCTRLB_ACKACT = 0x4 // Acknowledge Action + SCTRLB_SCMD = 0x3 // Command + + // SSTATUS: Slave Status + SSTATUS_AP = 0x1 // Slave Address or Stop + SSTATUS_APIF = 0x40 // Address/Stop Interrupt Flag + SSTATUS_BUSERR = 0x4 // Bus Error + SSTATUS_CLKHOLD = 0x20 // Clock Hold + SSTATUS_COLL = 0x8 // Collision + SSTATUS_DIF = 0x80 // Data Interrupt Flag + SSTATUS_DIR = 0x2 // Read/Write Direction + SSTATUS_RXACK = 0x10 // Received Acknowledge +) + +// Bitfields for USART: Universal Synchronous and Asynchronous Receiver and Transmitter +const ( + // RXDATAH: Receive Data High Byte + RXDATAH_BUFOVF = 0x40 // Buffer Overflow + RXDATAH_DATA8 = 0x1 // Receiver Data Register + RXDATAH_FERR = 0x4 // Frame Error + RXDATAH_PERR = 0x2 // Parity Error + RXDATAH_RXCIF = 0x80 // Receive Complete Interrupt Flag + + // RXDATAL: Receive Data Low Byte + RXDATAL_DATA = 0xff // RX Data + + // RXPLCTRL: IRCOM Receiver Pulse Length Control + RXPLCTRL_RXPL = 0x7f // Receiver Pulse Lenght + + // TXDATAH: Transmit Data High Byte + TXDATAH_DATA8 = 0x1 // Transmit Data Register (CHSIZE=9bit) + + // TXDATAL: Transmit Data Low Byte + TXDATAL_DATA = 0xff // Transmit Data Register + + // TXPLCTRL: IRCOM Transmitter Pulse Length Control + TXPLCTRL_TXPL = 0xff // Transmit pulse length +) diff --git a/src/device/avr/atmega3209.ld b/src/device/avr/atmega3209.ld new file mode 100644 index 00000000..4376fd40 --- /dev/null +++ b/src/device/avr/atmega3209.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega3209.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_size = 0x1000; +__num_isrs = 43; diff --git a/src/device/avr/atmega324a.go b/src/device/avr/atmega324a.go new file mode 100644 index 00000000..9941f124 --- /dev/null +++ b/src/device/avr/atmega324a.go @@ -0,0 +1,711 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega324A.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega324a + +// Device information for the ATmega324A. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega324A" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_PCINT0 = 4 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 5 // Pin Change Interrupt Request 1 + IRQ_PCINT2 = 6 // Pin Change Interrupt Request 2 + IRQ_PCINT3 = 7 // Pin Change Interrupt Request 3 + IRQ_WDT = 8 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 9 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 10 // Timer/Counter2 Compare Match B + IRQ_TIMER2_OVF = 11 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 12 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 13 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 14 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 15 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 16 // Timer/Counter0 Compare Match A + IRQ_TIMER0_COMPB = 17 // Timer/Counter0 Compare Match B + IRQ_TIMER0_OVF = 18 // Timer/Counter0 Overflow + IRQ_SPI_STC = 19 // SPI Serial Transfer Complete + IRQ_USART0_RX = 20 // USART0, Rx Complete + IRQ_USART0_UDRE = 21 // USART0 Data register Empty + IRQ_USART0_TX = 22 // USART0, Tx Complete + IRQ_ANALOG_COMP = 23 // Analog Comparator + IRQ_ADC = 24 // ADC Conversion Complete + IRQ_EE_READY = 25 // EEPROM Ready + IRQ_TWI = 26 // 2-wire Serial Interface + IRQ_SPM_READY = 27 // Store Program Memory Read + IRQ_USART1_RX = 28 // USART1 RX complete + IRQ_USART1_UDRE = 29 // USART1 Data Register Empty + IRQ_USART1_TX = 30 // USART1 TX complete + IRQ_max = 30 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + UDR1 __reg + UCSR1A __reg + UCSR1B __reg + UCSR1C __reg + UBRR1L __reg + UBRR1H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + UDR1: 0xce, // USART I/O Data Register + UCSR1A: 0xc8, // USART Control and Status Register A + UCSR1B: 0xc9, // USART Control and Status Register B + UCSR1C: 0xca, // USART Control and Status Register C + UBRR1L: 0xcc, // USART Baud Rate Register Bytes + UBRR1H: 0xcc, // USART Baud Rate Register Bytes + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK3 __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + PCICR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK3: 0x73, // Pin Change Mask Register 3 + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // The ADC Control and Status register A + DIDR0: 0x7e, // Digital Input Disable Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Low Bytes + EEARH: 0x41, // EEPROM Address Register Low Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Serial Peripheral Interface + SPI = struct { + SPDR0 __reg + SPSR0 __reg + SPCR0 __reg + }{ + SPDR0: 0x4e, // SPI Data Register + SPSR0: 0x4d, // SPI Status Register + SPCR0: 0x4c, // SPI Control Register + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PRR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PRR0: 0x64, // Power Reduction Register0 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTB1 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0xc0 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity + + // UCSR1A: USART Control and Status Register A + UCSR1A_RXC1 = 0x80 // USART Receive Complete + UCSR1A_TXC1 = 0x40 // USART Transmitt Complete + UCSR1A_UDRE1 = 0x20 // USART Data Register Empty + UCSR1A_FE1 = 0x10 // Framing Error + UCSR1A_DOR1 = 0x8 // Data overRun + UCSR1A_UPE1 = 0x4 // Parity Error + UCSR1A_U2X1 = 0x2 // Double the USART transmission speed + UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode + + // UCSR1B: USART Control and Status Register B + UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable + UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable + UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable + UCSR1B_RXEN1 = 0x10 // Receiver Enable + UCSR1B_TXEN1 = 0x8 // Transmitter Enable + UCSR1B_UCSZ12 = 0x4 // Character Size + UCSR1B_RXB81 = 0x2 // Receive Data Bit 8 + UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8 + + // UCSR1C: USART Control and Status Register C + UCSR1C_UMSEL1 = 0xc0 // USART Mode Select + UCSR1C_UPM1 = 0x30 // Parity Mode Bits + UCSR1C_USBS1 = 0x8 // Stop Bit Select + UCSR1C_UCSZ1 = 0x6 // Character Size + UCSR1C_UCPOL1 = 0x1 // Clock Polarity +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2B = 0x4 // Output Compare Flag 2B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Output Mode bits + TCCR2A_COM2B = 0x30 // Compare Output Mode bits + TCCR2A_WGM2 = 0x3 // Waveform Genration Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy + ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0x7 // External Interrupt Request 2 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0x7 // External Interrupt Flags + + // PCMSK3: Pin Change Mask Register 3 + PCMSK3_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0xf // Pin Change Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0xf // Pin Change Interrupt Enables +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register + DIDR0_ADC7D = 0x80 + DIDR0_ADC6D = 0x40 + DIDR0_ADC5D = 0x20 + DIDR0_ADC4D = 0x10 + DIDR0_ADC3D = 0x8 + DIDR0_ADC2D = 0x4 + DIDR0_ADC1D = 0x2 + DIDR0_ADC0D = 0x1 +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Timer/Counter1 Input Capture Flag + TIFR1_OCF1B = 0x4 // Timer/Counter1 Output Compare B Match Flag + TIFR1_OCF1A = 0x2 // Timer/Counter1 Output Compare A Match Flag + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Pulse Width Modulator Select Bits + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode Bits + TCCR1B_CS1 = 0x7 // Clock Select1 bits + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare for Channel A + TCCR1C_FOC1B = 0x40 // Force Output Compare for Channel B +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPSR0: SPI Status Register + SPSR0_SPIF0 = 0x80 // SPI Interrupt Flag + SPSR0_WCOL0 = 0x40 // Write Collision Flag + SPSR0_SPI2X0 = 0x1 // Double SPI Speed Bit + + // SPCR0: SPI Control Register + SPCR0_SPIE0 = 0x80 // SPI Interrupt Enable + SPCR0_SPE0 = 0x40 // SPI Enable + SPCR0_DORD0 = 0x20 // Data Order + SPCR0_MSTR0 = 0x10 // Master/Slave Select + SPCR0_CPOL0 = 0x8 // Clock polarity + SPCR0_CPHA0 = 0x4 // Clock Phase + SPCR0_SPR10 = 0x2 // SPI Clock Rate Select 1 + SPCR0_SPR00 = 0x1 // SPI Clock Rate Select 0 +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 + + // PRR0: Power Reduction Register0 + PRR0_PRTWI = 0x80 // Power Reduction TWI + PRR0_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR0_PRUSART1 = 0x10 // Power Reduction USARTs + PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR0_PRUSART0 = 0x2 // Power Reduction USARTs + PRR0_PRADC = 0x1 // Power Reduction ADC +) diff --git a/src/device/avr/atmega324a.ld b/src/device/avr/atmega324a.ld new file mode 100644 index 00000000..4d713dc1 --- /dev/null +++ b/src/device/avr/atmega324a.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega324A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_size = 0x800; +__num_isrs = 31; diff --git a/src/device/avr/atmega324p.go b/src/device/avr/atmega324p.go new file mode 100644 index 00000000..8d50d2c6 --- /dev/null +++ b/src/device/avr/atmega324p.go @@ -0,0 +1,711 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega324P.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega324p + +// Device information for the ATmega324P. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega324P" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_PCINT0 = 4 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 5 // Pin Change Interrupt Request 1 + IRQ_PCINT2 = 6 // Pin Change Interrupt Request 2 + IRQ_PCINT3 = 7 // Pin Change Interrupt Request 3 + IRQ_WDT = 8 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 9 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 10 // Timer/Counter2 Compare Match B + IRQ_TIMER2_OVF = 11 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 12 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 13 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 14 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 15 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 16 // Timer/Counter0 Compare Match A + IRQ_TIMER0_COMPB = 17 // Timer/Counter0 Compare Match B + IRQ_TIMER0_OVF = 18 // Timer/Counter0 Overflow + IRQ_SPI_STC = 19 // SPI Serial Transfer Complete + IRQ_USART0_RX = 20 // USART0, Rx Complete + IRQ_USART0_UDRE = 21 // USART0 Data register Empty + IRQ_USART0_TX = 22 // USART0, Tx Complete + IRQ_ANALOG_COMP = 23 // Analog Comparator + IRQ_ADC = 24 // ADC Conversion Complete + IRQ_EE_READY = 25 // EEPROM Ready + IRQ_TWI = 26 // 2-wire Serial Interface + IRQ_SPM_READY = 27 // Store Program Memory Read + IRQ_USART1_RX = 28 // USART1 RX complete + IRQ_USART1_UDRE = 29 // USART1 Data Register Empty + IRQ_USART1_TX = 30 // USART1 TX complete + IRQ_max = 30 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + UDR1 __reg + UCSR1A __reg + UCSR1B __reg + UCSR1C __reg + UBRR1L __reg + UBRR1H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + UDR1: 0xce, // USART I/O Data Register + UCSR1A: 0xc8, // USART Control and Status Register A + UCSR1B: 0xc9, // USART Control and Status Register B + UCSR1C: 0xca, // USART Control and Status Register C + UBRR1L: 0xcc, // USART Baud Rate Register Bytes + UBRR1H: 0xcc, // USART Baud Rate Register Bytes + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK3 __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + PCICR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK3: 0x73, // Pin Change Mask Register 3 + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // The ADC Control and Status register A + DIDR0: 0x7e, // Digital Input Disable Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Low Bytes + EEARH: 0x41, // EEPROM Address Register Low Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Serial Peripheral Interface + SPI = struct { + SPDR0 __reg + SPSR0 __reg + SPCR0 __reg + }{ + SPDR0: 0x4e, // SPI Data Register + SPSR0: 0x4d, // SPI Status Register + SPCR0: 0x4c, // SPI Control Register + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PRR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PRR0: 0x64, // Power Reduction Register0 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTB1 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0xc0 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity + + // UCSR1A: USART Control and Status Register A + UCSR1A_RXC1 = 0x80 // USART Receive Complete + UCSR1A_TXC1 = 0x40 // USART Transmitt Complete + UCSR1A_UDRE1 = 0x20 // USART Data Register Empty + UCSR1A_FE1 = 0x10 // Framing Error + UCSR1A_DOR1 = 0x8 // Data overRun + UCSR1A_UPE1 = 0x4 // Parity Error + UCSR1A_U2X1 = 0x2 // Double the USART transmission speed + UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode + + // UCSR1B: USART Control and Status Register B + UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable + UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable + UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable + UCSR1B_RXEN1 = 0x10 // Receiver Enable + UCSR1B_TXEN1 = 0x8 // Transmitter Enable + UCSR1B_UCSZ12 = 0x4 // Character Size + UCSR1B_RXB81 = 0x2 // Receive Data Bit 8 + UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8 + + // UCSR1C: USART Control and Status Register C + UCSR1C_UMSEL1 = 0xc0 // USART Mode Select + UCSR1C_UPM1 = 0x30 // Parity Mode Bits + UCSR1C_USBS1 = 0x8 // Stop Bit Select + UCSR1C_UCSZ1 = 0x6 // Character Size + UCSR1C_UCPOL1 = 0x1 // Clock Polarity +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2B = 0x4 // Output Compare Flag 2B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Output Mode bits + TCCR2A_COM2B = 0x30 // Compare Output Mode bits + TCCR2A_WGM2 = 0x3 // Waveform Genration Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy + ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0x7 // External Interrupt Request 2 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0x7 // External Interrupt Flags + + // PCMSK3: Pin Change Mask Register 3 + PCMSK3_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0xf // Pin Change Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0xf // Pin Change Interrupt Enables +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register + DIDR0_ADC7D = 0x80 + DIDR0_ADC6D = 0x40 + DIDR0_ADC5D = 0x20 + DIDR0_ADC4D = 0x10 + DIDR0_ADC3D = 0x8 + DIDR0_ADC2D = 0x4 + DIDR0_ADC1D = 0x2 + DIDR0_ADC0D = 0x1 +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Timer/Counter1 Input Capture Flag + TIFR1_OCF1B = 0x4 // Timer/Counter1 Output Compare B Match Flag + TIFR1_OCF1A = 0x2 // Timer/Counter1 Output Compare A Match Flag + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Pulse Width Modulator Select Bits + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode Bits + TCCR1B_CS1 = 0x7 // Clock Select1 bits + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare for Channel A + TCCR1C_FOC1B = 0x40 // Force Output Compare for Channel B +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPSR0: SPI Status Register + SPSR0_SPIF0 = 0x80 // SPI Interrupt Flag + SPSR0_WCOL0 = 0x40 // Write Collision Flag + SPSR0_SPI2X0 = 0x1 // Double SPI Speed Bit + + // SPCR0: SPI Control Register + SPCR0_SPIE0 = 0x80 // SPI Interrupt Enable + SPCR0_SPE0 = 0x40 // SPI Enable + SPCR0_DORD0 = 0x20 // Data Order + SPCR0_MSTR0 = 0x10 // Master/Slave Select + SPCR0_CPOL0 = 0x8 // Clock polarity + SPCR0_CPHA0 = 0x4 // Clock Phase + SPCR0_SPR10 = 0x2 // SPI Clock Rate Select 1 + SPCR0_SPR00 = 0x1 // SPI Clock Rate Select 0 +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 + + // PRR0: Power Reduction Register0 + PRR0_PRTWI = 0x80 // Power Reduction TWI + PRR0_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR0_PRUSART1 = 0x10 // Power Reduction USARTs + PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR0_PRUSART0 = 0x2 // Power Reduction USARTs + PRR0_PRADC = 0x1 // Power Reduction ADC +) diff --git a/src/device/avr/atmega324p.ld b/src/device/avr/atmega324p.ld new file mode 100644 index 00000000..356093b2 --- /dev/null +++ b/src/device/avr/atmega324p.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega324P.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_size = 0x800; +__num_isrs = 31; diff --git a/src/device/avr/atmega324pa.go b/src/device/avr/atmega324pa.go new file mode 100644 index 00000000..b51ecc34 --- /dev/null +++ b/src/device/avr/atmega324pa.go @@ -0,0 +1,782 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega324PA.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega324pa + +// Device information for the ATmega324PA. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega324PA" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_PCINT0 = 4 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 5 // Pin Change Interrupt Request 1 + IRQ_PCINT2 = 6 // Pin Change Interrupt Request 2 + IRQ_PCINT3 = 7 // Pin Change Interrupt Request 3 + IRQ_WDT = 8 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 9 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 10 // Timer/Counter2 Compare Match B + IRQ_TIMER2_OVF = 11 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 12 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 13 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 14 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 15 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 16 // Timer/Counter0 Compare Match A + IRQ_TIMER0_COMPB = 17 // Timer/Counter0 Compare Match B + IRQ_TIMER0_OVF = 18 // Timer/Counter0 Overflow + IRQ_SPI_STC = 19 // SPI Serial Transfer Complete + IRQ_USART0_RX = 20 // USART0, Rx Complete + IRQ_USART0_UDRE = 21 // USART0 Data register Empty + IRQ_USART0_TX = 22 // USART0, Tx Complete + IRQ_ANALOG_COMP = 23 // Analog Comparator + IRQ_ADC = 24 // ADC Conversion Complete + IRQ_EE_READY = 25 // EEPROM Ready + IRQ_TWI = 26 // 2-wire Serial Interface + IRQ_SPM_READY = 27 // Store Program Memory Read + IRQ_USART1_RX = 28 // USART1 RX complete + IRQ_USART1_UDRE = 29 // USART1 Data Register Empty + IRQ_USART1_TX = 30 // USART1 TX complete + IRQ_max = 30 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + UDR1 __reg + UCSR1A __reg + UCSR1B __reg + UCSR1C __reg + UBRR1L __reg + UBRR1H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + UDR1: 0xce, // USART I/O Data Register + UCSR1A: 0xc8, // USART Control and Status Register A + UCSR1B: 0xc9, // USART Control and Status Register B + UCSR1C: 0xca, // USART Control and Status Register C + UBRR1L: 0xcc, // USART Baud Rate Register Bytes + UBRR1H: 0xcc, // USART Baud Rate Register Bytes + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK3 __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + PCICR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK3: 0x73, // Pin Change Mask Register 3 + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // The ADC Control and Status register A + DIDR0: 0x7e, // Digital Input Disable Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Low Bytes + EEARH: 0x41, // EEPROM Address Register Low Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Serial Peripheral Interface + SPI = struct { + SPDR0 __reg + SPSR0 __reg + SPCR0 __reg + }{ + SPDR0: 0x4e, // SPI Data Register + SPSR0: 0x4d, // SPI Status Register + SPCR0: 0x4c, // SPI Control Register + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PRR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PRR0: 0x64, // Power Reduction Register0 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTB1 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for USART: USART +const ( + // UDR0: USART I/O Data Register + UDR0_UDR0 = 0xff // USART I/O Data bits + + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0xc0 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity + + // UDR1: USART I/O Data Register + UDR1_UDR1 = 0xff // USART I/O Data bits + + // UCSR1A: USART Control and Status Register A + UCSR1A_RXC1 = 0x80 // USART Receive Complete + UCSR1A_TXC1 = 0x40 // USART Transmitt Complete + UCSR1A_UDRE1 = 0x20 // USART Data Register Empty + UCSR1A_FE1 = 0x10 // Framing Error + UCSR1A_DOR1 = 0x8 // Data overRun + UCSR1A_UPE1 = 0x4 // Parity Error + UCSR1A_U2X1 = 0x2 // Double the USART transmission speed + UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode + + // UCSR1B: USART Control and Status Register B + UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable + UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable + UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable + UCSR1B_RXEN1 = 0x10 // Receiver Enable + UCSR1B_TXEN1 = 0x8 // Transmitter Enable + UCSR1B_UCSZ12 = 0x4 // Character Size + UCSR1B_RXB81 = 0x2 // Receive Data Bit 8 + UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8 + + // UCSR1C: USART Control and Status Register C + UCSR1C_UMSEL1 = 0xc0 // USART Mode Select + UCSR1C_UPM1 = 0x30 // Parity Mode Bits + UCSR1C_USBS1 = 0x8 // Stop Bit Select + UCSR1C_UCSZ1 = 0x6 // Character Size + UCSR1C_UCPOL1 = 0x1 // Clock Polarity + + // UBRR1L: USART Baud Rate Register Bytes + + // UBRR1H: USART Baud Rate Register Bytes + UBRR1_UBRR1 = 0xfff // USART Baud Rate bits +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // OCR0B: Timer/Counter0 Output Compare Register + OCR0B_OCR0B = 0xff // Timer/Counter0 Output Compare B bits + + // OCR0A: Timer/Counter0 Output Compare Register + OCR0A_OCR0A = 0xff // Timer/Counter0 Output Compare A bits + + // TCNT0: Timer/Counter0 + TCNT0_TCNT0 = 0xff // Timer/Counter0 bits + + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2B = 0x4 // Output Compare Flag 2B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Output Mode bits + TCCR2A_COM2B = 0x30 // Compare Output Mode bits + TCCR2A_WGM2 = 0x3 // Waveform Genration Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select bits + + // TCNT2: Timer/Counter2 + TCNT2_TCNT2 = 0xff // Timer/Counter2 bits + + // OCR2B: Timer/Counter2 Output Compare Register B + OCR2B_OCR2B = 0xff // Timer/Counter2 Output Compare B bits + + // OCR2A: Timer/Counter2 Output Compare Register A + OCR2A_OCR2A = 0xff // Timer/Counter0 Output Compare A bits + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy + ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0x7 // External Interrupt Request 2 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0x7 // External Interrupt Flags + + // PCMSK3: Pin Change Mask Register 3 + PCMSK3_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0xf // Pin Change Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0xf // Pin Change Interrupt Enables +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCL: ADC Data Register Bytes + + // ADCH: ADC Data Register Bytes + ADC_ADC = 0x3ff // ADC Data bits + + // ADCSRA: The ADC Control and Status register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register + DIDR0_ADC7D = 0x80 + DIDR0_ADC6D = 0x40 + DIDR0_ADC5D = 0x20 + DIDR0_ADC4D = 0x10 + DIDR0_ADC3D = 0x8 + DIDR0_ADC2D = 0x4 + DIDR0_ADC1D = 0x2 + DIDR0_ADC0D = 0x1 +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Timer/Counter1 Input Capture Flag + TIFR1_OCF1B = 0x4 // Timer/Counter1 Output Compare B Match Flag + TIFR1_OCF1A = 0x2 // Timer/Counter1 Output Compare A Match Flag + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Pulse Width Modulator Select Bits + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode Bits + TCCR1B_CS1 = 0x7 // Clock Select1 bits + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare for Channel A + TCCR1C_FOC1B = 0x40 // Force Output Compare for Channel B + + // TCNT1L: Timer/Counter1 Bytes + + // TCNT1H: Timer/Counter1 Bytes + TCNT1_TCNT1 = 0xffff // Timer/Counter1 bits + + // OCR1AL: Timer/Counter1 Output Compare Register A Bytes + + // OCR1AH: Timer/Counter1 Output Compare Register A Bytes + OCR1A_OCR1A = 0xffff // Timer/Counter1 Output Compare A bits + + // OCR1BL: Timer/Counter1 Output Compare Register B Bytes + + // OCR1BH: Timer/Counter1 Output Compare Register B Bytes + OCR1B_OCR1B = 0xff // Timer/Counter1 Output Compare B bits + + // ICR1L: Timer/Counter1 Input Capture Register Bytes + + // ICR1H: Timer/Counter1 Input Capture Register Bytes + ICR1_ICR1 = 0xffff // Timer/Counter1 Input Capture bits +) + +// Bitfields for EEPROM: EEPROM +const ( + // EEARL: EEPROM Address Register Low Bytes + + // EEARH: EEPROM Address Register Low Bytes + EEAR_EEAR = 0xfff // EEPROM Address Bits + + // EEDR: EEPROM Data Register + EEDR_EEDR = 0xff // EEPROM Data Bits + + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPDR0: SPI Data Register + SPDR0_SPDR0 = 0xff // SPI Data bits + + // SPSR0: SPI Status Register + SPSR0_SPIF0 = 0x80 // SPI Interrupt Flag + SPSR0_WCOL0 = 0x40 // Write Collision Flag + SPSR0_SPI2X0 = 0x1 // Double SPI Speed Bit + + // SPCR0: SPI Control Register + SPCR0_SPIE0 = 0x80 // SPI Interrupt Enable + SPCR0_SPE0 = 0x40 // SPI Enable + SPCR0_DORD0 = 0x20 // Data Order + SPCR0_MSTR0 = 0x10 // Master/Slave Select + SPCR0_CPOL0 = 0x8 // Clock polarity + SPCR0_CPHA0 = 0x4 // Clock Phase + SPCR0_SPR10 = 0x2 // SPI Clock Rate Select 1 + SPCR0_SPR00 = 0x1 // SPI Clock Rate Select 0 +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWBR: TWI Bit Rate register + TWBR_TWBR = 0xff // TWI bit rate bits + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWDR: TWI Data register + TWDR_TWD = 0xff // TWI data bits + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 + + // PRR0: Power Reduction Register0 + PRR0_PRTWI = 0x80 // Power Reduction TWI + PRR0_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR0_PRUSART1 = 0x10 // Power Reduction USART1 + PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR0_PRUSART0 = 0x2 // Power Reduction USART0 + PRR0_PRADC = 0x1 // Power Reduction ADC +) diff --git a/src/device/avr/atmega324pa.ld b/src/device/avr/atmega324pa.ld new file mode 100644 index 00000000..954934b6 --- /dev/null +++ b/src/device/avr/atmega324pa.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega324PA.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_size = 0x800; +__num_isrs = 31; diff --git a/src/device/avr/atmega324pb.go b/src/device/avr/atmega324pb.go new file mode 100644 index 00000000..f2444ec4 --- /dev/null +++ b/src/device/avr/atmega324pb.go @@ -0,0 +1,990 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega324PB.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega324pb + +// Device information for the ATmega324PB. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega324PB" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_PCINT0 = 4 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 5 // Pin Change Interrupt Request 1 + IRQ_PCINT2 = 6 // Pin Change Interrupt Request 2 + IRQ_PCINT3 = 7 // Pin Change Interrupt Request 3 + IRQ_WDT = 8 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 9 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 10 // Timer/Counter2 Compare Match B + IRQ_TIMER2_OVF = 11 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 12 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 13 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 14 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 15 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 16 // Timer/Counter0 Compare Match A + IRQ_TIMER0_COMPB = 17 // Timer/Counter0 Compare Match B + IRQ_TIMER0_OVF = 18 // Timer/Counter0 Overflow + IRQ_SPI0_STC = 19 // SPI0 Serial Transfer Complete + IRQ_USART0_RX = 20 // USART0 Rx Complete + IRQ_USART0_UDRE = 21 // USART0 Data register Empty + IRQ_USART0_TX = 22 // USART0 Tx Complete + IRQ_ANALOG_COMP = 23 // Analog Comparator + IRQ_ADC = 24 // ADC Conversion Complete + IRQ_EE_READY = 25 // EEPROM Ready + IRQ_TWI0 = 26 // 2-wire Serial Interface 0 + IRQ_SPM_READY = 27 // Store Program Memory Read + IRQ_USART1_RX = 28 // USART1 RX complete + IRQ_USART1_UDRE = 29 // USART1 Data Register Empty + IRQ_USART1_TX = 30 // USART1 TX complete + IRQ_TIMER3_CAPT = 31 // Timer/Counter3 Capture Event + IRQ_TIMER3_COMPA = 32 // Timer/Counter3 Compare Match A + IRQ_TIMER3_COMPB = 33 // Timer/Counter3 Compare Match B + IRQ_TIMER3_OVF = 34 // Timer/Counter3 Overflow + IRQ_USART0_RXS = 35 // USART0 RX start edge detect + IRQ_USART0_START = 35 // USART0 RX start edge detect + IRQ_USART1_RXS = 36 // USART1 RX start edge detect + IRQ_USART1_START = 36 // USART1 RX start edge detect + IRQ_PCINT4 = 37 // Pin Change Interrupt Request 4 + IRQ_XOSCFD = 38 // Crystal failure detect + IRQ_PTC_EOC = 39 // PTC end of conversion + IRQ_PTC_WCOMP = 40 // PTC window comparator interrupt + IRQ_SPI1_STC = 41 // SPI1 Serial Transfer Complete + IRQ_TWI1 = 42 // 2-wire Serial Interface 1 + IRQ_TIMER4_CAPT = 43 // Timer/Counter4 Capture Event + IRQ_TIMER4_COMPA = 44 // Timer/Counter4 Compare Match A + IRQ_TIMER4_COMPB = 45 // Timer/Counter4 Compare Match B + IRQ_TIMER4_OVF = 46 // Timer/Counter4 Overflow + IRQ_USART2_RX = 47 // USART2 Rx Complete + IRQ_USART2_UDRE = 48 // USART2 Data register Empty + IRQ_USART2_TX = 49 // USART2 Tx Complete + IRQ_USART2_RXS = 50 // USART2 RX start edge detect + IRQ_USART2_START = 50 // USART2 RX start edge detect + IRQ_max = 50 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog Comparator + AC = struct { + ACSR __reg + ACSRB __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + ACSRB: 0x4f, // Analog Comparator Control And Status Register B + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UCSR0D __reg + UBRR0L __reg + UBRR0H __reg + UDR1 __reg + UCSR1A __reg + UCSR1B __reg + UCSR1C __reg + UCSR1D __reg + UBRR1L __reg + UBRR1H __reg + UDR2 __reg + UCSR2A __reg + UCSR2B __reg + UCSR2C __reg + UCSR2D __reg + UBRR2L __reg + UBRR2H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UCSR0D: 0xc3, // USART Control and Status Register D + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + UDR1: 0xce, // USART I/O Data Register + UCSR1A: 0xc8, // USART Control and Status Register A + UCSR1B: 0xc9, // USART Control and Status Register B + UCSR1C: 0xca, // USART Control and Status Register C + UCSR1D: 0xcb, // USART Control and Status Register D + UBRR1L: 0xcc, // USART Baud Rate Register Bytes + UBRR1H: 0xcc, // USART Baud Rate Register Bytes + UDR2: 0xd6, // USART I/O Data Register + UCSR2A: 0xd0, // USART Control and Status Register A + UCSR2B: 0xd1, // USART Control and Status Register B + UCSR2C: 0xd2, // USART Control and Status Register C + UCSR2D: 0xd3, // USART Control and Status Register D + UBRR2L: 0xd4, // USART Baud Rate Register Bytes + UBRR2H: 0xd4, // USART Baud Rate Register Bytes + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Port E Data Register + DDRE: 0x2d, // Port E Data Direction Register + PINE: 0x2c, // Port E Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + GTCCR __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter0 Control Register B + TCCR0A: 0x44, // Timer/Counter0 Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + GTCCR: 0x43, // General Timer/Counter Control Register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK4 __reg + PCMSK3 __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + PCICR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK4: 0x75, // Pin Change Mask Register 4 + PCMSK3: 0x73, // Pin Change Mask Register 3 + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + ADCSRB __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // ADC multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // ADC Control and Status register A + ADCSRB: 0x7b, // ADC Control and Status register B + DIDR0: 0x7e, // Digital Input Disable Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + TIMSK3 __reg + TIFR3 __reg + TCCR3A __reg + TCCR3B __reg + TCCR3C __reg + TCNT3L __reg + TCNT3H __reg + OCR3AL __reg + OCR3AH __reg + OCR3BL __reg + OCR3BH __reg + ICR3L __reg + ICR3H __reg + TIMSK4 __reg + TIFR4 __reg + TCCR4A __reg + TCCR4B __reg + TCCR4C __reg + TCNT4L __reg + TCNT4H __reg + OCR4AL __reg + OCR4AH __reg + OCR4BL __reg + OCR4BH __reg + ICR4L __reg + ICR4H __reg + }{ + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK3: 0x71, // Timer/Counter3 Interrupt Mask Register + TIFR3: 0x38, // Timer/Counter Interrupt Flag register + TCCR3A: 0x90, // Timer/Counter3 Control Register A + TCCR3B: 0x91, // Timer/Counter3 Control Register B + TCCR3C: 0x92, // Timer/Counter3 Control Register C + TCNT3L: 0x94, // Timer/Counter3 Bytes + TCNT3H: 0x94, // Timer/Counter3 Bytes + OCR3AL: 0x98, // Timer/Counter3 Output Compare Register A Bytes + OCR3AH: 0x98, // Timer/Counter3 Output Compare Register A Bytes + OCR3BL: 0x9a, // Timer/Counter3 Output Compare Register B Bytes + OCR3BH: 0x9a, // Timer/Counter3 Output Compare Register B Bytes + ICR3L: 0x96, // Timer/Counter3 Input Capture Register Bytes + ICR3H: 0x96, // Timer/Counter3 Input Capture Register Bytes + TIMSK4: 0x72, // Timer/Counter4 Interrupt Mask Register + TIFR4: 0x39, // Timer/Counter Interrupt Flag register + TCCR4A: 0xa0, // Timer/Counter4 Control Register A + TCCR4B: 0xa1, // Timer/Counter4 Control Register B + TCCR4C: 0xa2, // Timer/Counter4 Control Register C + TCNT4L: 0xa4, // Timer/Counter4 Bytes + TCNT4H: 0xa4, // Timer/Counter4 Bytes + OCR4AL: 0xa8, // Timer/Counter4 Output Compare Register A Bytes + OCR4AH: 0xa8, // Timer/Counter4 Output Compare Register A Bytes + OCR4BL: 0xaa, // Timer/Counter4 Output Compare Register B Bytes + OCR4BH: 0xaa, // Timer/Counter4 Output Compare Register B Bytes + ICR4L: 0xa6, // Timer/Counter4 Input Capture Register Bytes + ICR4H: 0xa6, // Timer/Counter4 Input Capture Register Bytes + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Low Bytes + EEARH: 0x41, // EEPROM Address Register Low Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Serial Peripheral Interface + SPI = struct { + SPDR0 __reg + SPSR0 __reg + SPCR0 __reg + SPDR1 __reg + SPSR1 __reg + SPCR1 __reg + }{ + SPDR0: 0x4e, // SPI Data Register + SPSR0: 0x4d, // SPI Status Register + SPCR0: 0x4c, // SPI Control Register + SPDR1: 0xae, // SPI Data Register + SPSR1: 0xad, // SPI Status Register + SPCR1: 0xac, // SPI Control Register + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR0 __reg + TWBR0 __reg + TWCR0 __reg + TWSR0 __reg + TWDR0 __reg + TWAR0 __reg + TWAMR1 __reg + TWBR1 __reg + TWCR1 __reg + TWSR1 __reg + TWDR1 __reg + TWAR1 __reg + }{ + TWAMR0: 0xbd, // TWI (Slave) Address Mask Register + TWBR0: 0xb8, // TWI Bit Rate register + TWCR0: 0xbc, // TWI Control Register + TWSR0: 0xb9, // TWI Status Register + TWDR0: 0xbb, // TWI Data register + TWAR0: 0xba, // TWI (Slave) Address register + TWAMR1: 0xdd, // TWI (Slave) Address Mask Register + TWBR1: 0xd8, // TWI Bit Rate register + TWCR1: 0xdc, // TWI Control Register + TWSR1: 0xd9, // TWI Status Register + TWDR1: 0xdb, // TWI Data register + TWAR1: 0xda, // TWI (Slave) Address register + } + + // Clock Failure Detection + CFD = struct { + XFDCSR __reg + }{ + XFDCSR: 0x62, // XOSC Failure Detection Control and Status Register + } + + // Peripheral Touch Controller + PTC = struct { + }{} + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PRR0 __reg + PRR1 __reg + PRR2 __reg + SPMCSR __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PRR0: 0x64, // Power Reduction Register0 + PRR1: 0x65, // Power Reduction Register1 + PRR2: 0x63, // Power Reduction Register2 + SPMCSR: 0x57, // Store Program Memory Control Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_CFD = 0x8 // Clock Failure Detection + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTB1 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // ACSRB: Analog Comparator Control And Status Register B + ACSRB_ACOE = 0x1 // Analog Comparator Output enable + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC = 0x80 // USART Receive Complete + UCSR0A_TXC = 0x40 // USART Transmitt Complete + UCSR0A_UDRE = 0x20 // USART Data Register Empty + UCSR0A_FE = 0x10 // Framing Error + UCSR0A_DOR = 0x8 // Data overRun + UCSR0A_UPE = 0x4 // Parity Error + UCSR0A_U2X = 0x2 // Double the USART transmission speed + UCSR0A_MPCM = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN = 0x10 // Receiver Enable + UCSR0B_TXEN = 0x8 // Transmitter Enable + UCSR0B_UCSZ2 = 0x4 // Character Size + UCSR0B_RXB8 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB8 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL = 0xc0 // USART Mode Select + UCSR0C_UPM = 0x30 // Parity Mode Bits + UCSR0C_USBS = 0x8 // Stop Bit Select + UCSR0C_UCSZ = 0x6 // Character Size + UCSR0C_UCPOL = 0x1 // Clock Polarity + + // UCSR0D: USART Control and Status Register D + UCSR0D_RXSIE = 0x80 // RX Start Frame Interrupt Enable + UCSR0D_RXS = 0x40 // Start Frame Detect Flag + UCSR0D_SFDE = 0x20 // Start Frame Detection Enable + + // UCSR1A: USART Control and Status Register A + UCSR1A_RXC = 0x80 // USART Receive Complete + UCSR1A_TXC = 0x40 // USART Transmitt Complete + UCSR1A_UDRE = 0x20 // USART Data Register Empty + UCSR1A_FE = 0x10 // Framing Error + UCSR1A_DOR = 0x8 // Data overRun + UCSR1A_UPE = 0x4 // Parity Error + UCSR1A_U2X = 0x2 // Double the USART transmission speed + UCSR1A_MPCM = 0x1 // Multi-processor Communication Mode + + // UCSR1B: USART Control and Status Register B + UCSR1B_RXCIE = 0x80 // RX Complete Interrupt Enable + UCSR1B_TXCIE = 0x40 // TX Complete Interrupt Enable + UCSR1B_UDRIE = 0x20 // USART Data register Empty Interrupt Enable + UCSR1B_RXEN = 0x10 // Receiver Enable + UCSR1B_TXEN = 0x8 // Transmitter Enable + UCSR1B_UCSZ2 = 0x4 // Character Size + UCSR1B_RXB8 = 0x2 // Receive Data Bit 8 + UCSR1B_TXB8 = 0x1 // Transmit Data Bit 8 + + // UCSR1C: USART Control and Status Register C + UCSR1C_UMSEL = 0xc0 // USART Mode Select + UCSR1C_UPM = 0x30 // Parity Mode Bits + UCSR1C_USBS = 0x8 // Stop Bit Select + UCSR1C_UCSZ = 0x6 // Character Size + UCSR1C_UCPOL = 0x1 // Clock Polarity + + // UCSR1D: USART Control and Status Register D + UCSR1D_RXSIE = 0x80 // RX Start Frame Interrupt Enable + UCSR1D_RXS = 0x40 // Start Frame Detect Flag + UCSR1D_SFDE = 0x20 // Start Frame Detection Enable + + // UCSR2A: USART Control and Status Register A + UCSR2A_RXC = 0x80 // USART Receive Complete + UCSR2A_TXC = 0x40 // USART Transmitt Complete + UCSR2A_UDRE = 0x20 // USART Data Register Empty + UCSR2A_FE = 0x10 // Framing Error + UCSR2A_DOR = 0x8 // Data overRun + UCSR2A_UPE = 0x4 // Parity Error + UCSR2A_U2X = 0x2 // Double the USART transmission speed + UCSR2A_MPCM = 0x1 // Multi-processor Communication Mode + + // UCSR2B: USART Control and Status Register B + UCSR2B_RXCIE = 0x80 // RX Complete Interrupt Enable + UCSR2B_TXCIE = 0x40 // TX Complete Interrupt Enable + UCSR2B_UDRIE = 0x20 // USART Data register Empty Interrupt Enable + UCSR2B_RXEN = 0x10 // Receiver Enable + UCSR2B_TXEN = 0x8 // Transmitter Enable + UCSR2B_UCSZ2 = 0x4 // Character Size + UCSR2B_RXB8 = 0x2 // Receive Data Bit 8 + UCSR2B_TXB8 = 0x1 // Transmit Data Bit 8 + + // UCSR2C: USART Control and Status Register C + UCSR2C_UMSEL = 0xc0 // USART Mode Select + UCSR2C_UPM = 0x30 // Parity Mode Bits + UCSR2C_USBS = 0x8 // Stop Bit Select + UCSR2C_UCSZ = 0x6 // Character Size + UCSR2C_UCPOL = 0x1 // Clock Polarity + + // UCSR2D: USART Control and Status Register D + UCSR2D_RXSIE = 0x80 // RX Start Frame Interrupt Enable + UCSR2D_RXS = 0x40 // Start Frame Detect Flag + UCSR2D_SFDE = 0x20 // Start Frame Detection Enable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter0 Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 // Waveform Generation Mode + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter0 Control Register A + TCCR0A_COM0A = 0xc0 // Compare Match Output A Mode + TCCR0A_COM0B = 0x30 // Compare Match Output B Mode + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag + + // GTCCR: General Timer/Counter Control Register + GTCCR_TSM = 0x80 // Timer/Counter Synchronization Mode + GTCCR_PSRASY = 0x2 // Prescaler Reset Timer/Counter2 + GTCCR_PSRSYNC = 0x1 // Prescaler Reset Timer/Counter1 and Timer/Counter0 +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2B = 0x4 // Output Compare Flag 2B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Output Mode 2A bits + TCCR2A_COM2B = 0x30 // Compare Output Mode 2B bits + TCCR2A_WGM2 = 0x3 // Waveform Genration Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy + ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0x7 // External Interrupt Request Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0x7 // External Interrupt Flags + + // PCMSK4: Pin Change Mask Register 4 + PCMSK4_PCINT = 0x7f // Pin Change Enable Masks + + // PCMSK3: Pin Change Mask Register 3 + PCMSK3_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0x1f // Pin Change Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0x1f // Pin Change Interrupt Enables +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: ADC Control and Status register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCSRB: ADC Control and Status register B + ADCSRB_GPIOEN = 0x80 // Enable GPIO function of PE4 + ADCSRB_ACME = 0x40 // Analog Comparator Multiplexer Enable + ADCSRB_ADTS = 0x7 // ADC Auto Trigger Source bits + + // DIDR0: Digital Input Disable Register + DIDR0_ADC7D = 0x80 + DIDR0_ADC6D = 0x40 + DIDR0_ADC5D = 0x20 + DIDR0_ADC4D = 0x10 + DIDR0_ADC3D = 0x8 + DIDR0_ADC2D = 0x4 + DIDR0_ADC1D = 0x2 + DIDR0_ADC0D = 0x1 +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Timer/Counter1 Input Capture Flag + TIFR1_OCF1B = 0x4 // Timer/Counter1 Output Compare B Match Flag + TIFR1_OCF1A = 0x2 // Timer/Counter1 Output Compare A Match Flag + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Pulse Width Modulator Select Bits + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode Bits + TCCR1B_CS1 = 0x7 // Clock Select1 bits + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare for Channel A + TCCR1C_FOC1B = 0x40 // Force Output Compare for Channel B + + // TIMSK3: Timer/Counter3 Interrupt Mask Register + TIMSK3_ICIE3 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK3_OCIE3B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK3_OCIE3A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK3_TOIE3 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR3: Timer/Counter Interrupt Flag register + TIFR3_ICF3 = 0x20 // Timer/Counter1 Input Capture Flag + TIFR3_OCF3B = 0x4 // Timer/Counter1 Output Compare B Match Flag + TIFR3_OCF3A = 0x2 // Timer/Counter1 Output Compare A Match Flag + TIFR3_TOV3 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR3A: Timer/Counter3 Control Register A + TCCR3A_COM3A = 0xc0 // Compare Output Mode 1A, bits + TCCR3A_COM3B = 0x30 // Compare Output Mode 1B, bits + TCCR3A_WGM3 = 0x3 // Pulse Width Modulator Select Bits + + // TCCR3B: Timer/Counter3 Control Register B + TCCR3B_ICNC3 = 0x80 // Input Capture 1 Noise Canceler + TCCR3B_ICES3 = 0x40 // Input Capture 1 Edge Select + TCCR3B_WGM3 = 0x18 // Waveform Generation Mode Bits + TCCR3B_CS3 = 0x7 // Clock Select1 bits + + // TCCR3C: Timer/Counter3 Control Register C + TCCR3C_FOC3A = 0x80 // Force Output Compare for Channel A + TCCR3C_FOC3B = 0x40 // Force Output Compare for Channel B + + // TIMSK4: Timer/Counter4 Interrupt Mask Register + TIMSK4_ICIE4 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK4_OCIE4B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK4_OCIE4A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK4_TOIE4 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR4: Timer/Counter Interrupt Flag register + TIFR4_ICF4 = 0x20 // Timer/Counter1 Input Capture Flag + TIFR4_OCF4B = 0x4 // Timer/Counter1 Output Compare B Match Flag + TIFR4_OCF4A = 0x2 // Timer/Counter1 Output Compare A Match Flag + TIFR4_TOV4 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR4A: Timer/Counter4 Control Register A + TCCR4A_COM4A = 0xc0 // Compare Output Mode 1A, bits + TCCR4A_COM4B = 0x30 // Compare Output Mode 1B, bits + TCCR4A_WGM4 = 0x3 // Pulse Width Modulator Select Bits + + // TCCR4B: Timer/Counter4 Control Register B + TCCR4B_ICNC4 = 0x80 // Input Capture 1 Noise Canceler + TCCR4B_ICES4 = 0x40 // Input Capture 1 Edge Select + TCCR4B_WGM4 = 0x18 // Waveform Generation Mode Bits + TCCR4B_CS4 = 0x7 // Clock Select1 bits + + // TCCR4C: Timer/Counter4 Control Register C + TCCR4C_FOC4A = 0x80 // Force Output Compare for Channel A + TCCR4C_FOC4B = 0x40 // Force Output Compare for Channel B +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Programming Enable + EECR_EEPE = 0x2 // EEPROM Programming Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPSR0: SPI Status Register + SPSR0_SPIF = 0x80 // SPI Interrupt Flag + SPSR0_WCOL = 0x40 // Write Collision Flag + SPSR0_SPI2X = 0x1 // Double SPI Speed Bit + + // SPCR0: SPI Control Register + SPCR0_SPIE = 0x80 // SPI Interrupt Enable + SPCR0_SPE = 0x40 // SPI Enable + SPCR0_DORD = 0x20 // Data Order + SPCR0_MSTR = 0x10 // Master/Slave Select + SPCR0_CPOL = 0x8 // Clock polarity + SPCR0_CPHA = 0x4 // Clock Phase + SPCR0_SPR = 0x3 // SPI Clock Rate Select + + // SPSR1: SPI Status Register + SPSR1_SPIF = 0x80 // SPI Interrupt Flag + SPSR1_WCOL = 0x40 // Write Collision Flag + SPSR1_SPI2X = 0x1 // Double SPI Speed Bit + + // SPCR1: SPI Control Register + SPCR1_SPIE = 0x80 // SPI Interrupt Enable + SPCR1_SPE = 0x40 // SPI Enable + SPCR1_DORD = 0x20 // Data Order + SPCR1_MSTR = 0x10 // Master/Slave Select + SPCR1_CPOL = 0x8 // Clock polarity + SPCR1_CPHA = 0x4 // Clock Phase + SPCR1_SPR = 0x3 // SPI Clock Rate Select +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR0: TWI (Slave) Address Mask Register + TWAMR0_TWAM0 = 0xfe + + // TWCR0: TWI Control Register + TWCR0_TWINT = 0x80 // TWI Interrupt Flag + TWCR0_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR0_TWSTA = 0x20 // TWI Start Condition Bit + TWCR0_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR0_TWWC = 0x8 // TWI Write Collition Flag + TWCR0_TWEN = 0x4 // TWI Enable Bit + TWCR0_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR0: TWI Status Register + TWSR0_TWS0 = 0xf8 // TWI Status + TWSR0_TWPS = 0x3 // TWI Prescaler + + // TWAR0: TWI (Slave) Address register + TWAR0_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR0_TWGCE = 0x1 // TWI General Call Recognition Enable Bit + + // TWAMR1: TWI (Slave) Address Mask Register + TWAMR1_TWAM1 = 0xfe + + // TWCR1: TWI Control Register + TWCR1_TWINT = 0x80 // TWI Interrupt Flag + TWCR1_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR1_TWSTA = 0x20 // TWI Start Condition Bit + TWCR1_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR1_TWWC = 0x8 // TWI Write Collition Flag + TWCR1_TWEN = 0x4 // TWI Enable Bit + TWCR1_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR1: TWI Status Register + TWSR1_TWS0 = 0xf8 // TWI Status + TWSR1_TWPS = 0x3 // TWI Prescaler + + // TWAR1: TWI (Slave) Address register + TWAR1_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR1_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for CFD: Clock Failure Detection +const ( + // XFDCSR: XOSC Failure Detection Control and Status Register + XFDCSR_XFDIF = 0x2 // Failure Detection Interrupt Flag + XFDCSR_XFDIE = 0x1 // Failure Detection Interrupt Enable +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // PRR0: Power Reduction Register0 + PRR0_PRTWI0 = 0x80 // Power Reduction TWI0 + PRR0_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR0_PRUSART1 = 0x10 // Power Reduction USART1 + PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR0_PRSPI0 = 0x4 // Power Reduction Serial Peripheral Interface 0 + PRR0_PRUSART0 = 0x2 // Power Reduction USART0 + PRR0_PRADC = 0x1 // Power Reduction ADC + + // PRR1: Power Reduction Register1 + PRR1_PRTIM4 = 0x2 // Power Reduction Timer/Counter4 + PRR1_PRTIM3 = 0x1 // Power Reduction Timer/Counter3 + + // PRR2: Power Reduction Register2 + PRR2_PRPTC = 0x8 // Power Reduction Peripheral Touch Controller + PRR2_PRUSART2 = 0x4 // Power Reduction USART2 + PRR2_PRSPI1 = 0x2 // Power Reduction Serial Peripheral Interface 1 + PRR2_PRTWI1 = 0x1 // Power Reduction TWI1 + + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) diff --git a/src/device/avr/atmega324pb.ld b/src/device/avr/atmega324pb.ld new file mode 100644 index 00000000..cf5ed84f --- /dev/null +++ b/src/device/avr/atmega324pb.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega324PB.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_size = 0x800; +__num_isrs = 54; diff --git a/src/device/avr/atmega325.go b/src/device/avr/atmega325.go new file mode 100644 index 00000000..e010fa70 --- /dev/null +++ b/src/device/avr/atmega325.go @@ -0,0 +1,605 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega325.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega325 + +// Device information for the ATmega325. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega325" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_PCINT0 = 2 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 3 // Pin Change Interrupt Request 1 + IRQ_TIMER2_COMP = 4 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 5 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 6 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 7 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 8 // Timer/Counter Compare Match B + IRQ_TIMER1_OVF = 9 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 10 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 11 // Timer/Counter0 Overflow + IRQ_SPI_STC = 12 // SPI Serial Transfer Complete + IRQ_USART0_RX = 13 // USART0, Rx Complete + IRQ_USART0_UDRE = 14 // USART0 Data register Empty + IRQ_USART0_TX = 15 // USART0, Tx Complete + IRQ_USI_START = 16 // USI Start Condition + IRQ_USI_OVERFLOW = 17 // USI Overflow + IRQ_ANALOG_COMP = 18 // Analog Comparator + IRQ_ADC = 19 // ADC Conversion Complete + IRQ_EE_READY = 20 // EEPROM Ready + IRQ_SPM_READY = 21 // Store Program Memory Read + IRQ_max = 21 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 0 + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } + + // Universal Serial Interface + USI = struct { + USIDR __reg + USISR __reg + USICR __reg + }{ + USIDR: 0xba, // USI Data Register + USISR: 0xb9, // USI Status Register + USICR: 0xb8, // USI Control Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK1 __reg + PCMSK0 __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access Bytes + EEARH: 0x41, // EEPROM Read/Write Access Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + PORTG: 0x34, // Port G Data Register + DDRG: 0x33, // Port G Data Direction Register + PING: 0x32, // Port G Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0A __reg + TCNT0 __reg + OCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR0A: 0x44, // Timer/Counter0 Control Register + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2A __reg + TCNT2 __reg + OCR2A __reg + TIMSK2 __reg + TIFR2 __reg + ASSR __reg + }{ + TCCR2A: 0xb0, // Timer/Counter2 Control Register + TCNT2: 0xb2, // Timer/Counter2 + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register + TIMSK2: 0x70, // Timer/Counter2 Interrupt Mask register + TIFR2: 0x37, // Timer/Counter2 Interrupt Flag Register + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x60, // Watchdog Timer Control Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + PRR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + PRR: 0x64, // Power Reduction Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x6 // Brown-out Detector trigger level + EXTENDED_RSTDISBL = 0x1 // External Reset Disable + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM memory through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmit Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data OverRun + UCSR0A_UPE0 = 0x4 // USART Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART Transmission Speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data Register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0x40 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) + +// Bitfields for USI: Universal Serial Interface +const ( + // USISR: USI Status Register + USISR_USISIF = 0x80 // Start Condition Interrupt Flag + USISR_USIOIF = 0x40 // Counter Overflow Interrupt Flag + USISR_USIPF = 0x20 // Stop Condition Flag + USISR_USIDC = 0x10 // Data Output Collision + USISR_USICNT = 0xf // USI Counter Value Bits + + // USICR: USI Control Register + USICR_USISIE = 0x80 // Start Condition Interrupt Enable + USICR_USIOIE = 0x40 // Counter Overflow Interrupt Enable + USICR_USIWM = 0x30 // USI Wire Mode Bits + USICR_USICS = 0xc // USI Clock Source Select Bits + USICR_USICLK = 0x2 // Clock Strobe + USICR_USITC = 0x1 // Toggle Clock Port Pin +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC01 = 0x2 // External Interrupt Sense Control 0 Bit 1 + EICRA_ISC00 = 0x1 // External Interrupt Sense Control 0 Bit 0 + + // EIMSK: External Interrupt Mask Register + EIMSK_PCIE = 0xf0 // Pin Change Interrupt Enables + EIMSK_INT0 = 0x1 // External Interrupt Request 0 Enable + + // EIFR: External Interrupt Flag Register + EIFR_PCIF = 0xf0 // Pin Change Interrupt Flags + EIFR_INTF0 = 0x1 // External Interrupt Flag 0 + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Mask bits + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Mask bits +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0A: Timer/Counter0 Control Register + TCCR0A_FOC0A = 0x80 // Force Output Compare + TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0A_COM0A = 0x30 // Compare Match Output Modes + TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0A_CS0 = 0x7 // Clock Selects + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0 + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2A: Timer/Counter2 Control Register + TCCR2A_FOC2A = 0x80 // Force Output Compare A + TCCR2A_WGM20 = 0x40 // Waveform Generation Mode + TCCR2A_COM2A = 0x30 // Compare Output Mode bits + TCCR2A_WGM21 = 0x8 // Waveform Generation Mode + TCCR2A_CS2 = 0x7 // Clock Select bits + + // TIMSK2: Timer/Counter2 Interrupt Mask register + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter2 Interrupt Flag Register + TIFR2_OCF2A = 0x2 // Timer/Counter2 Output Compare Flag 2 + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x10 // Enable External Clock Interrupt + ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // PRR: Power Reduction Register + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable +) diff --git a/src/device/avr/atmega325.ld b/src/device/avr/atmega325.ld new file mode 100644 index 00000000..9ea3887e --- /dev/null +++ b/src/device/avr/atmega325.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega325.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_size = 0x800; +__num_isrs = 22; diff --git a/src/device/avr/atmega3250.go b/src/device/avr/atmega3250.go new file mode 100644 index 00000000..20ba850b --- /dev/null +++ b/src/device/avr/atmega3250.go @@ -0,0 +1,630 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega3250.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega3250 + +// Device information for the ATmega3250. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega3250" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_PCINT0 = 2 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 3 // Pin Change Interrupt Request 1 + IRQ_TIMER2_COMP = 4 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 5 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 6 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 7 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 8 // Timer/Counter Compare Match B + IRQ_TIMER1_OVF = 9 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 10 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 11 // Timer/Counter0 Overflow + IRQ_SPI_STC = 12 // SPI Serial Transfer Complete + IRQ_USART_RX = 13 // USART, Rx Complete + IRQ_USART_UDRE = 14 // USART Data register Empty + IRQ_USART0_TX = 15 // USART0, Tx Complete + IRQ_USI_START = 16 // USI Start Condition + IRQ_USI_OVERFLOW = 17 // USI Overflow + IRQ_ANALOG_COMP = 18 // Analog Comparator + IRQ_ADC = 19 // ADC Conversion Complete + IRQ_EE_READY = 20 // EEPROM Ready + IRQ_SPM_READY = 21 // Store Program Memory Read + IRQ_NOT_USED = 22 // RESERVED + IRQ_PCINT2 = 23 // Pin Change Interrupt Request 2 + IRQ_PCINT3 = 24 // Pin Change Interrupt Request 3 + IRQ_max = 24 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0A __reg + TCNT0 __reg + OCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR0A: 0x44, // Timer/Counter0 Control Register + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2A __reg + TCNT2 __reg + OCR2A __reg + TIMSK2 __reg + TIFR2 __reg + ASSR __reg + }{ + TCCR2A: 0xb0, // Timer/Counter2 Control Register + TCNT2: 0xb2, // Timer/Counter2 + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register + TIMSK2: 0x70, // Timer/Counter2 Interrupt Mask register + TIFR2: 0x37, // Timer/Counter2 Interrupt Flag Register + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x60, // Watchdog Timer Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access Bytes + EEARH: 0x41, // EEPROM Read/Write Access Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + PORTH __reg + DDRH __reg + PINH __reg + PORTJ __reg + DDRJ __reg + PINJ __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + PORTG: 0x34, // Port G Data Register + DDRG: 0x33, // Port G Data Direction Register + PING: 0x32, // Port G Input Pins + PORTH: 0xda, // PORT H Data Register + DDRH: 0xd9, // PORT H Data Direction Register + PINH: 0xd8, // PORT H Input Pins + PORTJ: 0xdd, // PORT J Data Register + DDRJ: 0xdc, // PORT J Data Direction Register + PINJ: 0xdb, // PORT J Input Pins + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK3 __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK3: 0x73, // Pin Change Mask Register 3 + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + PRR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + PRR: 0x64, // Power Reduction Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + } + + // Universal Serial Interface + USI = struct { + USIDR __reg + USISR __reg + USICR __reg + }{ + USIDR: 0xba, // USI Data Register + USISR: 0xb9, // USI Status Register + USICR: 0xb8, // USI Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 0 + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x6 // Brown-out Detector trigger level + EXTENDED_RSTDISBL = 0x1 // External Reset Disable + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM memory through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0A: Timer/Counter0 Control Register + TCCR0A_FOC0A = 0x80 // Force Output Compare + TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0A_COM0A = 0x30 // Compare Match Output Modes + TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0A_CS0 = 0x7 // Clock Selects + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0 + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2A: Timer/Counter2 Control Register + TCCR2A_FOC2A = 0x80 // Force Output Compare A + TCCR2A_WGM20 = 0x40 // Waveform Generation Mode + TCCR2A_COM2A = 0x30 // Compare Output Mode bits + TCCR2A_WGM21 = 0x8 // Waveform Generation Mode + TCCR2A_CS2 = 0x7 // Clock Select bits + + // TIMSK2: Timer/Counter2 Interrupt Mask register + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter2 Interrupt Flag Register + TIFR2_OCF2A = 0x2 // Timer/Counter2 Output Compare Flag 2 + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x10 // Enable External Clock Interrupt + ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC01 = 0x2 // External Interrupt Sense Control 0 Bit 1 + EICRA_ISC00 = 0x1 // External Interrupt Sense Control 0 Bit 0 + + // EIMSK: External Interrupt Mask Register + EIMSK_PCIE = 0xf0 // Pin Change Interrupt Enables + EIMSK_INT0 = 0x1 // External Interrupt Request 0 Enable + + // EIFR: External Interrupt Flag Register + EIFR_PCIF = 0xf0 // Pin Change Interrupt Flags + EIFR_INTF0 = 0x1 // External Interrupt Flag 0 + + // PCMSK3: Pin Change Mask Register 3 + PCMSK3_PCINT = 0x7f // Pin Change Mask bits + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Mask bits + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Mask bits + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Mask bits +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // PRR: Power Reduction Register + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable +) + +// Bitfields for USI: Universal Serial Interface +const ( + // USISR: USI Status Register + USISR_USISIF = 0x80 // Start Condition Interrupt Flag + USISR_USIOIF = 0x40 // Counter Overflow Interrupt Flag + USISR_USIPF = 0x20 // Stop Condition Flag + USISR_USIDC = 0x10 // Data Output Collision + USISR_USICNT = 0xf // USI Counter Value Bits + + // USICR: USI Control Register + USICR_USISIE = 0x80 // Start Condition Interrupt Enable + USICR_USIOIE = 0x40 // Counter Overflow Interrupt Enable + USICR_USIWM = 0x30 // USI Wire Mode Bits + USICR_USICS = 0xc // USI Clock Source Select Bits + USICR_USICLK = 0x2 // Clock Strobe + USICR_USITC = 0x1 // Toggle Clock Port Pin +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmit Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data OverRun + UCSR0A_UPE0 = 0x4 // USART Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART Transmission Speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data Register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0x40 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) diff --git a/src/device/avr/atmega3250.ld b/src/device/avr/atmega3250.ld new file mode 100644 index 00000000..ff1410c6 --- /dev/null +++ b/src/device/avr/atmega3250.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega3250.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_size = 0x800; +__num_isrs = 25; diff --git a/src/device/avr/atmega3250a.go b/src/device/avr/atmega3250a.go new file mode 100644 index 00000000..068d1b7e --- /dev/null +++ b/src/device/avr/atmega3250a.go @@ -0,0 +1,630 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega3250A.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega3250a + +// Device information for the ATmega3250A. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega3250A" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_PCINT0 = 2 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 3 // Pin Change Interrupt Request 1 + IRQ_TIMER2_COMP = 4 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 5 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 6 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 7 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 8 // Timer/Counter Compare Match B + IRQ_TIMER1_OVF = 9 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 10 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 11 // Timer/Counter0 Overflow + IRQ_SPI_STC = 12 // SPI Serial Transfer Complete + IRQ_USART_RX = 13 // USART, Rx Complete + IRQ_USART_UDRE = 14 // USART Data register Empty + IRQ_USART0_TX = 15 // USART0, Tx Complete + IRQ_USI_START = 16 // USI Start Condition + IRQ_USI_OVERFLOW = 17 // USI Overflow + IRQ_ANALOG_COMP = 18 // Analog Comparator + IRQ_ADC = 19 // ADC Conversion Complete + IRQ_EE_READY = 20 // EEPROM Ready + IRQ_SPM_READY = 21 // Store Program Memory Read + IRQ_NOT_USED = 22 // RESERVED + IRQ_PCINT2 = 23 // Pin Change Interrupt Request 2 + IRQ_PCINT3 = 24 // Pin Change Interrupt Request 3 + IRQ_max = 24 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0A __reg + TCNT0 __reg + OCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR0A: 0x44, // Timer/Counter0 Control Register + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2A __reg + TCNT2 __reg + OCR2A __reg + TIMSK2 __reg + TIFR2 __reg + ASSR __reg + }{ + TCCR2A: 0xb0, // Timer/Counter2 Control Register + TCNT2: 0xb2, // Timer/Counter2 + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register + TIMSK2: 0x70, // Timer/Counter2 Interrupt Mask register + TIFR2: 0x37, // Timer/Counter2 Interrupt Flag Register + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x60, // Watchdog Timer Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access Bytes + EEARH: 0x41, // EEPROM Read/Write Access Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + PORTH __reg + DDRH __reg + PINH __reg + PORTJ __reg + DDRJ __reg + PINJ __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + PORTG: 0x34, // Port G Data Register + DDRG: 0x33, // Port G Data Direction Register + PING: 0x32, // Port G Input Pins + PORTH: 0xda, // PORT H Data Register + DDRH: 0xd9, // PORT H Data Direction Register + PINH: 0xd8, // PORT H Input Pins + PORTJ: 0xdd, // PORT J Data Register + DDRJ: 0xdc, // PORT J Data Direction Register + PINJ: 0xdb, // PORT J Input Pins + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK3 __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK3: 0x73, // Pin Change Mask Register 3 + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + PRR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + PRR: 0x64, // Power Reduction Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + } + + // Universal Serial Interface + USI = struct { + USIDR __reg + USISR __reg + USICR __reg + }{ + USIDR: 0xba, // USI Data Register + USISR: 0xb9, // USI Status Register + USICR: 0xb8, // USI Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 0 + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x6 // Brown-out Detector trigger level + EXTENDED_RSTDISBL = 0x1 // External Reset Disable + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM memory through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0A: Timer/Counter0 Control Register + TCCR0A_FOC0A = 0x80 // Force Output Compare + TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0A_COM0A = 0x30 // Compare Match Output Modes + TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0A_CS0 = 0x7 // Clock Selects + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0 + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2A: Timer/Counter2 Control Register + TCCR2A_FOC2A = 0x80 // Force Output Compare A + TCCR2A_WGM20 = 0x40 // Waveform Generation Mode + TCCR2A_COM2A = 0x30 // Compare Output Mode bits + TCCR2A_WGM21 = 0x8 // Waveform Generation Mode + TCCR2A_CS2 = 0x7 // Clock Select bits + + // TIMSK2: Timer/Counter2 Interrupt Mask register + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter2 Interrupt Flag Register + TIFR2_OCF2A = 0x2 // Timer/Counter2 Output Compare Flag 2 + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x10 // Enable External Clock Interrupt + ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC01 = 0x2 // External Interrupt Sense Control 0 Bit 1 + EICRA_ISC00 = 0x1 // External Interrupt Sense Control 0 Bit 0 + + // EIMSK: External Interrupt Mask Register + EIMSK_PCIE = 0xf0 // Pin Change Interrupt Enables + EIMSK_INT0 = 0x1 // External Interrupt Request 0 Enable + + // EIFR: External Interrupt Flag Register + EIFR_PCIF = 0xf0 // Pin Change Interrupt Flags + EIFR_INTF0 = 0x1 // External Interrupt Flag 0 + + // PCMSK3: Pin Change Mask Register 3 + PCMSK3_PCINT = 0x7f // Pin Change Mask bits + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Mask bits + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Mask bits + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Mask bits +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // PRR: Power Reduction Register + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable +) + +// Bitfields for USI: Universal Serial Interface +const ( + // USISR: USI Status Register + USISR_USISIF = 0x80 // Start Condition Interrupt Flag + USISR_USIOIF = 0x40 // Counter Overflow Interrupt Flag + USISR_USIPF = 0x20 // Stop Condition Flag + USISR_USIDC = 0x10 // Data Output Collision + USISR_USICNT = 0xf // USI Counter Value Bits + + // USICR: USI Control Register + USICR_USISIE = 0x80 // Start Condition Interrupt Enable + USICR_USIOIE = 0x40 // Counter Overflow Interrupt Enable + USICR_USIWM = 0x30 // USI Wire Mode Bits + USICR_USICS = 0xc // USI Clock Source Select Bits + USICR_USICLK = 0x2 // Clock Strobe + USICR_USITC = 0x1 // Toggle Clock Port Pin +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmit Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data OverRun + UCSR0A_UPE0 = 0x4 // USART Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART Transmission Speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data Register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0x40 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) diff --git a/src/device/avr/atmega3250a.ld b/src/device/avr/atmega3250a.ld new file mode 100644 index 00000000..fbdcf279 --- /dev/null +++ b/src/device/avr/atmega3250a.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega3250A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_size = 0x800; +__num_isrs = 25; diff --git a/src/device/avr/atmega3250p.go b/src/device/avr/atmega3250p.go new file mode 100644 index 00000000..d0df5c52 --- /dev/null +++ b/src/device/avr/atmega3250p.go @@ -0,0 +1,630 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega3250P.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega3250p + +// Device information for the ATmega3250P. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega3250P" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_PCINT0 = 2 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 3 // Pin Change Interrupt Request 1 + IRQ_TIMER2_COMP = 4 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 5 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 6 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 7 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 8 // Timer/Counter Compare Match B + IRQ_TIMER1_OVF = 9 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 10 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 11 // Timer/Counter0 Overflow + IRQ_SPI_STC = 12 // SPI Serial Transfer Complete + IRQ_USART_RX = 13 // USART, Rx Complete + IRQ_USART_UDRE = 14 // USART Data register Empty + IRQ_USART0_TX = 15 // USART0, Tx Complete + IRQ_USI_START = 16 // USI Start Condition + IRQ_USI_OVERFLOW = 17 // USI Overflow + IRQ_ANALOG_COMP = 18 // Analog Comparator + IRQ_ADC = 19 // ADC Conversion Complete + IRQ_EE_READY = 20 // EEPROM Ready + IRQ_SPM_READY = 21 // Store Program Memory Read + IRQ_NOT_USED = 22 // RESERVED + IRQ_PCINT2 = 23 // Pin Change Interrupt Request 2 + IRQ_PCINT3 = 24 // Pin Change Interrupt Request 3 + IRQ_max = 24 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0A __reg + TCNT0 __reg + OCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR0A: 0x44, // Timer/Counter0 Control Register + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2A __reg + TCNT2 __reg + OCR2A __reg + TIMSK2 __reg + TIFR2 __reg + ASSR __reg + }{ + TCCR2A: 0xb0, // Timer/Counter2 Control Register + TCNT2: 0xb2, // Timer/Counter2 + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register + TIMSK2: 0x70, // Timer/Counter2 Interrupt Mask register + TIFR2: 0x37, // Timer/Counter2 Interrupt Flag Register + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x60, // Watchdog Timer Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access Bytes + EEARH: 0x41, // EEPROM Read/Write Access Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + PORTH __reg + DDRH __reg + PINH __reg + PORTJ __reg + DDRJ __reg + PINJ __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + PORTG: 0x34, // Port G Data Register + DDRG: 0x33, // Port G Data Direction Register + PING: 0x32, // Port G Input Pins + PORTH: 0xda, // PORT H Data Register + DDRH: 0xd9, // PORT H Data Direction Register + PINH: 0xd8, // PORT H Input Pins + PORTJ: 0xdd, // PORT J Data Register + DDRJ: 0xdc, // PORT J Data Direction Register + PINJ: 0xdb, // PORT J Input Pins + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK3 __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK3: 0x73, // Pin Change Mask Register 3 + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + PRR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + PRR: 0x64, // Power Reduction Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + } + + // Universal Serial Interface + USI = struct { + USIDR __reg + USISR __reg + USICR __reg + }{ + USIDR: 0xba, // USI Data Register + USISR: 0xb9, // USI Status Register + USICR: 0xb8, // USI Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 0 + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x6 // Brown-out Detector trigger level + EXTENDED_RSTDISBL = 0x1 // External Reset Disable + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM memory through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0A: Timer/Counter0 Control Register + TCCR0A_FOC0A = 0x80 // Force Output Compare + TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0A_COM0A = 0x30 // Compare Match Output Modes + TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0A_CS0 = 0x7 // Clock Selects + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0 + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2A: Timer/Counter2 Control Register + TCCR2A_FOC2A = 0x80 // Force Output Compare A + TCCR2A_WGM20 = 0x40 // Waveform Generation Mode + TCCR2A_COM2A = 0x30 // Compare Output Mode bits + TCCR2A_WGM21 = 0x8 // Waveform Generation Mode + TCCR2A_CS2 = 0x7 // Clock Select bits + + // TIMSK2: Timer/Counter2 Interrupt Mask register + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter2 Interrupt Flag Register + TIFR2_OCF2A = 0x2 // Timer/Counter2 Output Compare Flag 2 + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x10 // Enable External Clock Interrupt + ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC01 = 0x2 // External Interrupt Sense Control 0 Bit 1 + EICRA_ISC00 = 0x1 // External Interrupt Sense Control 0 Bit 0 + + // EIMSK: External Interrupt Mask Register + EIMSK_PCIE = 0xf0 // Pin Change Interrupt Enables + EIMSK_INT0 = 0x1 // External Interrupt Request 0 Enable + + // EIFR: External Interrupt Flag Register + EIFR_PCIF = 0xf0 // Pin Change Interrupt Flags + EIFR_INTF0 = 0x1 // External Interrupt Flag 0 + + // PCMSK3: Pin Change Mask Register 3 + PCMSK3_PCINT = 0x7f // Pin Change Mask bits + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Mask bits + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Mask bits + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Mask bits +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // PRR: Power Reduction Register + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable +) + +// Bitfields for USI: Universal Serial Interface +const ( + // USISR: USI Status Register + USISR_USISIF = 0x80 // Start Condition Interrupt Flag + USISR_USIOIF = 0x40 // Counter Overflow Interrupt Flag + USISR_USIPF = 0x20 // Stop Condition Flag + USISR_USIDC = 0x10 // Data Output Collision + USISR_USICNT = 0xf // USI Counter Value Bits + + // USICR: USI Control Register + USICR_USISIE = 0x80 // Start Condition Interrupt Enable + USICR_USIOIE = 0x40 // Counter Overflow Interrupt Enable + USICR_USIWM = 0x30 // USI Wire Mode Bits + USICR_USICS = 0xc // USI Clock Source Select Bits + USICR_USICLK = 0x2 // Clock Strobe + USICR_USITC = 0x1 // Toggle Clock Port Pin +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmit Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data OverRun + UCSR0A_UPE0 = 0x4 // USART Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART Transmission Speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data Register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0x40 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) diff --git a/src/device/avr/atmega3250p.ld b/src/device/avr/atmega3250p.ld new file mode 100644 index 00000000..9b510e7f --- /dev/null +++ b/src/device/avr/atmega3250p.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega3250P.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_size = 0x800; +__num_isrs = 25; diff --git a/src/device/avr/atmega3250pa.go b/src/device/avr/atmega3250pa.go new file mode 100644 index 00000000..3b789916 --- /dev/null +++ b/src/device/avr/atmega3250pa.go @@ -0,0 +1,619 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega3250PA.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega3250pa + +// Device information for the ATmega3250PA. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega3250PA" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_PCINT0 = 2 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 3 // Pin Change Interrupt Request 1 + IRQ_TIMER2_COMP = 4 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 5 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 6 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 7 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 8 // Timer/Counter Compare Match B + IRQ_TIMER1_OVF = 9 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 10 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 11 // Timer/Counter0 Overflow + IRQ_SPI_STC = 12 // SPI Serial Transfer Complete + IRQ_USART_RX = 13 // USART, Rx Complete + IRQ_USART_UDRE = 14 // USART Data register Empty + IRQ_USART0_TX = 15 // USART0, Tx Complete + IRQ_USI_START = 16 // USI Start Condition + IRQ_USI_OVERFLOW = 17 // USI Overflow + IRQ_ANALOG_COMP = 18 // Analog Comparator + IRQ_ADC = 19 // ADC Conversion Complete + IRQ_EE_READY = 20 // EEPROM Ready + IRQ_SPM_READY = 21 // Store Program Memory Read + IRQ_NOT_USED = 22 // RESERVED + IRQ_PCINT2 = 23 // Pin Change Interrupt Request 2 + IRQ_PCINT3 = 24 // Pin Change Interrupt Request 3 + IRQ_max = 24 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0A __reg + TCNT0 __reg + OCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR0A: 0x44, // Timer/Counter0 Control Register + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2A __reg + TCNT2 __reg + OCR2A __reg + TIMSK2 __reg + TIFR2 __reg + ASSR __reg + }{ + TCCR2A: 0xb0, // Timer/Counter2 Control Register + TCNT2: 0xb2, // Timer/Counter2 + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register + TIMSK2: 0x70, // Timer/Counter2 Interrupt Mask register + TIFR2: 0x37, // Timer/Counter2 Interrupt Flag Register + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x60, // Watchdog Timer Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access Bytes + EEARH: 0x41, // EEPROM Read/Write Access Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + PORTH __reg + DDRH __reg + PINH __reg + PORTJ __reg + DDRJ __reg + PINJ __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + PORTG: 0x34, // Port G Data Register + DDRG: 0x33, // Port G Data Direction Register + PING: 0x32, // Port G Input Pins + PORTH: 0xda, // PORT H Data Register + DDRH: 0xd9, // PORT H Data Direction Register + PINH: 0xd8, // PORT H Input Pins + PORTJ: 0xdd, // PORT J Data Register + DDRJ: 0xdc, // PORT J Data Direction Register + PINJ: 0xdb, // PORT J Input Pins + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK3 __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK3: 0x73, // Pin Change Mask Register 3 + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + } + + // Universal Serial Interface + USI = struct { + USIDR __reg + USISR __reg + USICR __reg + }{ + USIDR: 0xba, // USI Data Register + USISR: 0xb9, // USI Status Register + USICR: 0xb8, // USI Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 0 + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + PRR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + PRR: 0x64, // Power Reduction Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x6 // Brown-out Detector trigger level + EXTENDED_RSTDISBL = 0x1 // External Reset Disable + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM memory through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0A: Timer/Counter0 Control Register + TCCR0A_FOC0A = 0x80 // Force Output Compare + TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0A_COM0A = 0x30 // Compare Match Output Modes + TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0A_CS0 = 0x7 // Clock Selects + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0 + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2A: Timer/Counter2 Control Register + TCCR2A_FOC2A = 0x80 // Force Output Compare A + TCCR2A_WGM20 = 0x40 // Waveform Generation Mode + TCCR2A_COM2A = 0x30 // Compare Output Mode bits + TCCR2A_WGM21 = 0x8 // Waveform Generation Mode + TCCR2A_CS2 = 0x7 // Clock Select bits + + // TIMSK2: Timer/Counter2 Interrupt Mask register + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter2 Interrupt Flag Register + TIFR2_OCF2A = 0x2 // Timer/Counter2 Output Compare Flag 2 + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x10 // Enable External Clock Interrupt + ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC01 = 0x2 // External Interrupt Sense Control 0 Bit 1 + EICRA_ISC00 = 0x1 // External Interrupt Sense Control 0 Bit 0 + + // EIMSK: External Interrupt Mask Register + EIMSK_PCIE = 0xf0 // Pin Change Interrupt Enables + EIMSK_INT0 = 0x1 // External Interrupt Request 0 Enable + + // EIFR: External Interrupt Flag Register + EIFR_PCIF = 0xf0 // Pin Change Interrupt Flags + EIFR_INTF0 = 0x1 // External Interrupt Flag 0 +) + +// Bitfields for USI: Universal Serial Interface +const ( + // USISR: USI Status Register + USISR_USISIF = 0x80 // Start Condition Interrupt Flag + USISR_USIOIF = 0x40 // Counter Overflow Interrupt Flag + USISR_USIPF = 0x20 // Stop Condition Flag + USISR_USIDC = 0x10 // Data Output Collision + USISR_USICNT = 0xf // USI Counter Value Bits + + // USICR: USI Control Register + USICR_USISIE = 0x80 // Start Condition Interrupt Enable + USICR_USIOIE = 0x40 // Counter Overflow Interrupt Enable + USICR_USIWM = 0x30 // USI Wire Mode Bits + USICR_USICS = 0xc // USI Clock Source Select Bits + USICR_USICLK = 0x2 // Clock Strobe + USICR_USITC = 0x1 // Toggle Clock Port Pin +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmit Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data OverRun + UCSR0A_UPE0 = 0x4 // USART Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART Transmission Speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data Register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0x40 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // PRR: Power Reduction Register + PRR_PRLCD = 0x10 // Power Reduction LCD + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable +) diff --git a/src/device/avr/atmega3250pa.ld b/src/device/avr/atmega3250pa.ld new file mode 100644 index 00000000..182b6ba0 --- /dev/null +++ b/src/device/avr/atmega3250pa.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega3250PA.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_size = 0x800; +__num_isrs = 25; diff --git a/src/device/avr/atmega325a.go b/src/device/avr/atmega325a.go new file mode 100644 index 00000000..bf27e988 --- /dev/null +++ b/src/device/avr/atmega325a.go @@ -0,0 +1,606 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega325A.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega325a + +// Device information for the ATmega325A. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega325A" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_PCINT0 = 2 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 3 // Pin Change Interrupt Request 1 + IRQ_TIMER2_COMP = 4 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 5 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 6 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 7 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 8 // Timer/Counter Compare Match B + IRQ_TIMER1_OVF = 9 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 10 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 11 // Timer/Counter0 Overflow + IRQ_SPI_STC = 12 // SPI Serial Transfer Complete + IRQ_USART0_RX = 13 // USART0, Rx Complete + IRQ_USART0_UDRE = 14 // USART0 Data register Empty + IRQ_USART0_TX = 15 // USART0, Tx Complete + IRQ_USI_START = 16 // USI Start Condition + IRQ_USI_OVERFLOW = 17 // USI Overflow + IRQ_ANALOG_COMP = 18 // Analog Comparator + IRQ_ADC = 19 // ADC Conversion Complete + IRQ_EE_READY = 20 // EEPROM Ready + IRQ_SPM_READY = 21 // Store Program Memory Read + IRQ_max = 21 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 0 + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } + + // Universal Serial Interface + USI = struct { + USIDR __reg + USISR __reg + USICR __reg + }{ + USIDR: 0xba, // USI Data Register + USISR: 0xb9, // USI Status Register + USICR: 0xb8, // USI Control Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK1 __reg + PCMSK0 __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access Bytes + EEARH: 0x41, // EEPROM Read/Write Access Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + PORTG: 0x34, // Port G Data Register + DDRG: 0x33, // Port G Data Direction Register + PING: 0x32, // Port G Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0A __reg + TCNT0 __reg + OCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR0A: 0x44, // Timer/Counter0 Control Register + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2A __reg + TCNT2 __reg + OCR2A __reg + TIMSK2 __reg + TIFR2 __reg + ASSR __reg + }{ + TCCR2A: 0xb0, // Timer/Counter2 Control Register + TCNT2: 0xb2, // Timer/Counter2 + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register + TIMSK2: 0x70, // Timer/Counter2 Interrupt Mask register + TIFR2: 0x37, // Timer/Counter2 Interrupt Flag Register + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x60, // Watchdog Timer Control Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + PRR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + PRR: 0x64, // Power Reduction Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x6 // Brown-out Detector trigger level + EXTENDED_RSTDISBL = 0x1 // External Reset Disable + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM memory through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmit Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data OverRun + UCSR0A_UPE0 = 0x4 // USART Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART Transmission Speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data Register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0x40 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) + +// Bitfields for USI: Universal Serial Interface +const ( + // USISR: USI Status Register + USISR_USISIF = 0x80 // Start Condition Interrupt Flag + USISR_USIOIF = 0x40 // Counter Overflow Interrupt Flag + USISR_USIPF = 0x20 // Stop Condition Flag + USISR_USIDC = 0x10 // Data Output Collision + USISR_USICNT = 0xf // USI Counter Value Bits + + // USICR: USI Control Register + USICR_USISIE = 0x80 // Start Condition Interrupt Enable + USICR_USIOIE = 0x40 // Counter Overflow Interrupt Enable + USICR_USIWM = 0x30 // USI Wire Mode Bits + USICR_USICS = 0xc // USI Clock Source Select Bits + USICR_USICLK = 0x2 // Clock Strobe + USICR_USITC = 0x1 // Toggle Clock Port Pin +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC01 = 0x2 // External Interrupt Sense Control 0 Bit 1 + EICRA_ISC00 = 0x1 // External Interrupt Sense Control 0 Bit 0 + + // EIMSK: External Interrupt Mask Register + EIMSK_PCIE = 0xf0 // Pin Change Interrupt Enables + EIMSK_INT0 = 0x1 // External Interrupt Request 0 Enable + + // EIFR: External Interrupt Flag Register + EIFR_PCIF = 0xf0 // Pin Change Interrupt Flags + EIFR_INTF0 = 0x1 // External Interrupt Flag 0 + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Mask bits + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Mask bits +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0A: Timer/Counter0 Control Register + TCCR0A_FOC0A = 0x80 // Force Output Compare + TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0A_COM0A = 0x30 // Compare Match Output Modes + TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0A_CS0 = 0x7 // Clock Selects + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0 + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2A: Timer/Counter2 Control Register + TCCR2A_FOC2A = 0x80 // Force Output Compare A + TCCR2A_WGM20 = 0x40 // Waveform Generation Mode + TCCR2A_COM2A = 0x30 // Compare Output Mode bits + TCCR2A_WGM21 = 0x8 // Waveform Generation Mode + TCCR2A_CS2 = 0x7 // Clock Select bits + + // TIMSK2: Timer/Counter2 Interrupt Mask register + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter2 Interrupt Flag Register + TIFR2_OCF2A = 0x2 // Timer/Counter2 Output Compare Flag 2 + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x10 // Enable External Clock Interrupt + ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // PRR: Power Reduction Register + PRR_PRLCD = 0x10 // Power Reduction LCD + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable +) diff --git a/src/device/avr/atmega325a.ld b/src/device/avr/atmega325a.ld new file mode 100644 index 00000000..1bb9e1c6 --- /dev/null +++ b/src/device/avr/atmega325a.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega325A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_size = 0x800; +__num_isrs = 22; diff --git a/src/device/avr/atmega325p.go b/src/device/avr/atmega325p.go new file mode 100644 index 00000000..8ede519f --- /dev/null +++ b/src/device/avr/atmega325p.go @@ -0,0 +1,606 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega325P.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega325p + +// Device information for the ATmega325P. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega325P" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_PCINT0 = 2 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 3 // Pin Change Interrupt Request 1 + IRQ_TIMER2_COMP = 4 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 5 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 6 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 7 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 8 // Timer/Counter Compare Match B + IRQ_TIMER1_OVF = 9 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 10 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 11 // Timer/Counter0 Overflow + IRQ_SPI_STC = 12 // SPI Serial Transfer Complete + IRQ_USART0_RX = 13 // USART0, Rx Complete + IRQ_USART0_UDRE = 14 // USART0 Data register Empty + IRQ_USART0_TX = 15 // USART0, Tx Complete + IRQ_USI_START = 16 // USI Start Condition + IRQ_USI_OVERFLOW = 17 // USI Overflow + IRQ_ANALOG_COMP = 18 // Analog Comparator + IRQ_ADC = 19 // ADC Conversion Complete + IRQ_EE_READY = 20 // EEPROM Ready + IRQ_SPM_READY = 21 // Store Program Memory Read + IRQ_max = 21 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 0 + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } + + // Universal Serial Interface + USI = struct { + USIDR __reg + USISR __reg + USICR __reg + }{ + USIDR: 0xba, // USI Data Register + USISR: 0xb9, // USI Status Register + USICR: 0xb8, // USI Control Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK1 __reg + PCMSK0 __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access Bytes + EEARH: 0x41, // EEPROM Read/Write Access Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + PORTG: 0x34, // Port G Data Register + DDRG: 0x33, // Port G Data Direction Register + PING: 0x32, // Port G Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0A __reg + TCNT0 __reg + OCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR0A: 0x44, // Timer/Counter0 Control Register + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2A __reg + TCNT2 __reg + OCR2A __reg + TIMSK2 __reg + TIFR2 __reg + ASSR __reg + }{ + TCCR2A: 0xb0, // Timer/Counter2 Control Register + TCNT2: 0xb2, // Timer/Counter2 + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register + TIMSK2: 0x70, // Timer/Counter2 Interrupt Mask register + TIFR2: 0x37, // Timer/Counter2 Interrupt Flag Register + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x60, // Watchdog Timer Control Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + PRR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + PRR: 0x64, // Power Reduction Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x6 // Brown-out Detector trigger level + EXTENDED_RSTDISBL = 0x1 // External Reset Disable + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM memory through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmit Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data OverRun + UCSR0A_UPE0 = 0x4 // USART Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART Transmission Speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data Register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0x40 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) + +// Bitfields for USI: Universal Serial Interface +const ( + // USISR: USI Status Register + USISR_USISIF = 0x80 // Start Condition Interrupt Flag + USISR_USIOIF = 0x40 // Counter Overflow Interrupt Flag + USISR_USIPF = 0x20 // Stop Condition Flag + USISR_USIDC = 0x10 // Data Output Collision + USISR_USICNT = 0xf // USI Counter Value Bits + + // USICR: USI Control Register + USICR_USISIE = 0x80 // Start Condition Interrupt Enable + USICR_USIOIE = 0x40 // Counter Overflow Interrupt Enable + USICR_USIWM = 0x30 // USI Wire Mode Bits + USICR_USICS = 0xc // USI Clock Source Select Bits + USICR_USICLK = 0x2 // Clock Strobe + USICR_USITC = 0x1 // Toggle Clock Port Pin +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC01 = 0x2 // External Interrupt Sense Control 0 Bit 1 + EICRA_ISC00 = 0x1 // External Interrupt Sense Control 0 Bit 0 + + // EIMSK: External Interrupt Mask Register + EIMSK_PCIE = 0xf0 // Pin Change Interrupt Enables + EIMSK_INT0 = 0x1 // External Interrupt Request 0 Enable + + // EIFR: External Interrupt Flag Register + EIFR_PCIF = 0xf0 // Pin Change Interrupt Flags + EIFR_INTF0 = 0x1 // External Interrupt Flag 0 + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Mask bits + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Mask bits +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0A: Timer/Counter0 Control Register + TCCR0A_FOC0A = 0x80 // Force Output Compare + TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0A_COM0A = 0x30 // Compare Match Output Modes + TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0A_CS0 = 0x7 // Clock Selects + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0 + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2A: Timer/Counter2 Control Register + TCCR2A_FOC2A = 0x80 // Force Output Compare A + TCCR2A_WGM20 = 0x40 // Waveform Generation Mode + TCCR2A_COM2A = 0x30 // Compare Output Mode bits + TCCR2A_WGM21 = 0x8 // Waveform Generation Mode + TCCR2A_CS2 = 0x7 // Clock Select bits + + // TIMSK2: Timer/Counter2 Interrupt Mask register + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter2 Interrupt Flag Register + TIFR2_OCF2A = 0x2 // Timer/Counter2 Output Compare Flag 2 + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x10 // Enable External Clock Interrupt + ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // PRR: Power Reduction Register + PRR_PRLCD = 0x10 // Power Reduction LCD + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable +) diff --git a/src/device/avr/atmega325p.ld b/src/device/avr/atmega325p.ld new file mode 100644 index 00000000..176f312e --- /dev/null +++ b/src/device/avr/atmega325p.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega325P.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_size = 0x800; +__num_isrs = 22; diff --git a/src/device/avr/atmega325pa.go b/src/device/avr/atmega325pa.go new file mode 100644 index 00000000..36f9468d --- /dev/null +++ b/src/device/avr/atmega325pa.go @@ -0,0 +1,600 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega325PA.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega325pa + +// Device information for the ATmega325PA. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega325PA" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_PCINT0 = 2 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 3 // Pin Change Interrupt Request 1 + IRQ_TIMER2_COMP = 4 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 5 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 6 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 7 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 8 // Timer/Counter Compare Match B + IRQ_TIMER1_OVF = 9 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 10 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 11 // Timer/Counter0 Overflow + IRQ_SPI_STC = 12 // SPI Serial Transfer Complete + IRQ_USART0_RX = 13 // USART0, Rx Complete + IRQ_USART0_UDRE = 14 // USART0 Data register Empty + IRQ_USART0_TX = 15 // USART0, Tx Complete + IRQ_USI_START = 16 // USI Start Condition + IRQ_USI_OVERFLOW = 17 // USI Overflow + IRQ_ANALOG_COMP = 18 // Analog Comparator + IRQ_ADC = 19 // ADC Conversion Complete + IRQ_EE_READY = 20 // EEPROM Ready + IRQ_SPM_READY = 21 // Store Program Memory Read + IRQ_max = 21 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 0 + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } + + // Universal Serial Interface + USI = struct { + USIDR __reg + USISR __reg + USICR __reg + }{ + USIDR: 0xba, // USI Data Register + USISR: 0xb9, // USI Status Register + USICR: 0xb8, // USI Control Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK1 __reg + PCMSK0 __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access Bytes + EEARH: 0x41, // EEPROM Read/Write Access Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + PORTG: 0x34, // Port G Data Register + DDRG: 0x33, // Port G Data Direction Register + PING: 0x32, // Port G Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0A __reg + TCNT0 __reg + OCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR0A: 0x44, // Timer/Counter0 Control Register + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2A __reg + TCNT2 __reg + OCR2A __reg + TIMSK2 __reg + TIFR2 __reg + ASSR __reg + }{ + TCCR2A: 0xb0, // Timer/Counter2 Control Register + TCNT2: 0xb2, // Timer/Counter2 + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register + TIMSK2: 0x70, // Timer/Counter2 Interrupt Mask register + TIFR2: 0x37, // Timer/Counter2 Interrupt Flag Register + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x60, // Watchdog Timer Control Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + PRR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + PRR: 0x64, // Power Reduction Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x6 // Brown-out Detector trigger level + EXTENDED_RSTDISBL = 0x1 // External Reset Disable + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM memory through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmit Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data OverRun + UCSR0A_UPE0 = 0x4 // USART Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART Transmission Speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data Register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0x40 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) + +// Bitfields for USI: Universal Serial Interface +const ( + // USISR: USI Status Register + USISR_USISIF = 0x80 // Start Condition Interrupt Flag + USISR_USIOIF = 0x40 // Counter Overflow Interrupt Flag + USISR_USIPF = 0x20 // Stop Condition Flag + USISR_USIDC = 0x10 // Data Output Collision + USISR_USICNT = 0xf // USI Counter Value Bits + + // USICR: USI Control Register + USICR_USISIE = 0x80 // Start Condition Interrupt Enable + USICR_USIOIE = 0x40 // Counter Overflow Interrupt Enable + USICR_USIWM = 0x30 // USI Wire Mode Bits + USICR_USICS = 0xc // USI Clock Source Select Bits + USICR_USICLK = 0x2 // Clock Strobe + USICR_USITC = 0x1 // Toggle Clock Port Pin +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC01 = 0x2 // External Interrupt Sense Control 0 Bit 1 + EICRA_ISC00 = 0x1 // External Interrupt Sense Control 0 Bit 0 + + // EIMSK: External Interrupt Mask Register + EIMSK_PCIE = 0xf0 // Pin Change Interrupt Enables + EIMSK_INT0 = 0x1 // External Interrupt Request 0 Enable + + // EIFR: External Interrupt Flag Register + EIFR_PCIF = 0xf0 // Pin Change Interrupt Flags + EIFR_INTF0 = 0x1 // External Interrupt Flag 0 +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0A: Timer/Counter0 Control Register + TCCR0A_FOC0A = 0x80 // Force Output Compare + TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0A_COM0A = 0x30 // Compare Match Output Modes + TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0A_CS0 = 0x7 // Clock Selects + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0 + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2A: Timer/Counter2 Control Register + TCCR2A_FOC2A = 0x80 // Force Output Compare A + TCCR2A_WGM20 = 0x40 // Waveform Generation Mode + TCCR2A_COM2A = 0x30 // Compare Output Mode bits + TCCR2A_WGM21 = 0x8 // Waveform Generation Mode + TCCR2A_CS2 = 0x7 // Clock Select bits + + // TIMSK2: Timer/Counter2 Interrupt Mask register + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter2 Interrupt Flag Register + TIFR2_OCF2A = 0x2 // Timer/Counter2 Output Compare Flag 2 + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x10 // Enable External Clock Interrupt + ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // PRR: Power Reduction Register + PRR_PRLCD = 0x10 // Power Reduction LCD + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable +) diff --git a/src/device/avr/atmega325pa.ld b/src/device/avr/atmega325pa.ld new file mode 100644 index 00000000..67141aa3 --- /dev/null +++ b/src/device/avr/atmega325pa.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega325PA.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_size = 0x800; +__num_isrs = 22; diff --git a/src/device/avr/atmega328.go b/src/device/avr/atmega328.go new file mode 100644 index 00000000..38c45114 --- /dev/null +++ b/src/device/avr/atmega328.go @@ -0,0 +1,718 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega328.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega328 + +// Device information for the ATmega328. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega328" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_PCINT0 = 3 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 4 // Pin Change Interrupt Request 1 + IRQ_PCINT2 = 5 // Pin Change Interrupt Request 2 + IRQ_WDT = 6 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 7 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 8 // Timer/Counter2 Compare Match B + IRQ_TIMER2_OVF = 9 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 10 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 11 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 12 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 13 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 14 // TimerCounter0 Compare Match A + IRQ_TIMER0_COMPB = 15 // TimerCounter0 Compare Match B + IRQ_TIMER0_OVF = 16 // Timer/Couner0 Overflow + IRQ_SPI_STC = 17 // SPI Serial Transfer Complete + IRQ_USART_RX = 18 // USART Rx Complete + IRQ_USART_UDRE = 19 // USART, Data Register Empty + IRQ_USART_TX = 20 // USART Tx Complete + IRQ_ADC = 21 // ADC Conversion Complete + IRQ_EE_READY = 22 // EEPROM Ready + IRQ_ANALOG_COMP = 23 // Analog Comparator + IRQ_TWI = 24 // Two-wire Serial Interface + IRQ_SPM_READY = 25 // Store Program Memory Read + IRQ_max = 25 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + ADCSRB __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // The ADC Control and Status register A + ADCSRB: 0x7b, // The ADC Control and Status register B + DIDR0: 0x7e, // Digital Input Disable Register + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // I/O Port + PORT = struct { + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + }{ + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCICR __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + } + + // Serial Peripheral Interface + SPI = struct { + SPDR __reg + SPSR __reg + SPCR __reg + }{ + SPDR: 0x4e, // SPI Data Register + SPSR: 0x4d, // SPI Status Register + SPCR: 0x4c, // SPI Control Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Bytes + EEARH: 0x41, // EEPROM Address Register Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // CPU Registers + CPU = struct { + PRR __reg + OSCCAL __reg + CLKPR __reg + SREG __reg + SPL __reg + SPH __reg + SPMCSR __reg + MCUCR __reg + MCUSR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + PRR: 0x64, // Power Reduction Register + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + SPMCSR: 0x57, // Store Program Memory Control and Status Register + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose I/O Register 2 + GPIOR1: 0x4a, // General Purpose I/O Register 1 + GPIOR0: 0x3e, // General Purpose I/O Register 0 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // HIGH + HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PC6 as i/o pin) + HIGH_DWEN = 0x40 // Debug Wire enable + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watch-dog Timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select boot size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTB0 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for USART: USART +const ( + // UDR0: USART I/O Data Register + UDR0_UDR0 = 0xff // USART I/O Data bits + + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0xc0 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity + + // UBRR0L: USART Baud Rate Register Bytes + + // UBRR0H: USART Baud Rate Register Bytes + UBRR0_UBRR0 = 0xfff // USART Baud rate bits +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWBR: TWI Bit Rate register + TWBR_TWBR = 0xff // TWI Bit rate bits + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWDR: TWI Data register + TWDR_TWDR = 0xff // TWI Data bits + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TIMSK1: Timer/Counter Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output CompareB Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output CompareA Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 + TCCR1C_FOC1B = 0x40 + + // TCNT1L: Timer/Counter1 Bytes + + // TCNT1H: Timer/Counter1 Bytes + TCNT1_TCNT1 = 0xffff // Timer/Counter1 bits + + // OCR1AL: Timer/Counter1 Output Compare Register Bytes + + // OCR1AH: Timer/Counter1 Output Compare Register Bytes + OCR1A_OCR1A = 0xffff // Timer/Counter1 Output Compare A bits + + // OCR1BL: Timer/Counter1 Output Compare Register Bytes + + // OCR1BH: Timer/Counter1 Output Compare Register Bytes + OCR1B_OCR1B = 0xffff // Timer/Counter1 Output Compare B bits + + // ICR1L: Timer/Counter1 Input Capture Register Bytes + + // ICR1H: Timer/Counter1 Input Capture Register Bytes + ICR1_ICR1 = 0xffff // Timer/Counter1 Input Capture bits +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2B = 0x4 // Output Compare Flag 2B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Output Mode bits + TCCR2A_COM2B = 0x30 // Compare Output Mode bits + TCCR2A_WGM2 = 0x3 // Waveform Genration Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select bits + + // TCNT2: Timer/Counter2 + TCNT2_TCNT2 = 0xff // Timer/Counter2 bits + + // OCR2B: Timer/Counter2 Output Compare Register B + OCR2B_OCR2B = 0xff // Timer/Counter2 Output Compare B bits + + // OCR2A: Timer/Counter2 Output Compare Register A + OCR2A_OCR2A = 0xff // Timer/Counter2 Output Compare A bits + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy + ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0xf // Analog Channel Selection Bits + + // ADCL: ADC Data Register Bytes + + // ADCH: ADC Data Register Bytes + ADC_ADC = 0x3ff // ADC Data bits + + // ADCSRA: The ADC Control and Status register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCSRB: The ADC Control and Status register B + ADCSRB_ACME = 0x40 + ADCSRB_ADTS = 0x7 // ADC Auto Trigger Source bits + + // DIDR0: Digital Input Disable Register + DIDR0_ADC5D = 0x20 + DIDR0_ADC4D = 0x10 + DIDR0_ADC3D = 0x8 + DIDR0_ADC2D = 0x4 + DIDR0_ADC1D = 0x2 + DIDR0_ADC0D = 0x1 +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // OCR0B: Timer/Counter0 Output Compare Register + OCR0B_OCR0B = 0xff // Timer/Counter0 Output Compare B bits + + // OCR0A: Timer/Counter0 Output Compare Register + OCR0A_OCR0A = 0xff // Timer/Counter0 Output Compare A bits + + // TCNT0: Timer/Counter0 + TCNT0_TCNT0 = 0xff // Timer/Counter0 bits + + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register + EICRA_ISC1 = 0xc // External Interrupt Sense Control 1 Bits + EICRA_ISC0 = 0x3 // External Interrupt Sense Control 0 Bits + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0x3 // External Interrupt Request 1 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0x3 // External Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0x7 // Pin Change Interrupt Enables + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0x7f // Pin Change Enable Masks + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0x7 // Pin Change Interrupt Flags +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPDR: SPI Data Register + SPDR_SPDR = 0xff // SPI Data bits + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for EEPROM: EEPROM +const ( + // EEARL: EEPROM Address Register Bytes + + // EEARH: EEPROM Address Register Bytes + EEAR_EEAR = 0x3ff // EEPROM Address Bits + + // EEDR: EEPROM Data Register + EEDR_EEDR = 0xff // EEPROM Data Bits + + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for CPU: CPU Registers +const ( + // PRR: Power Reduction Register + PRR_PRTWI = 0x80 // Power Reduction TWI + PRR_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // SPMCSR: Store Program Memory Control and Status Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read-While-Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read-While-Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory + + // MCUCR: MCU Control Register + MCUCR_PUD = 0x10 + MCUCR_IVSEL = 0x2 + MCUCR_IVCE = 0x1 + + // MCUSR: MCU Status Register + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BORF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select Bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR2: General Purpose I/O Register 2 + GPIOR2_GPIOR2 = 0xff // General Purpose I/O bits + + // GPIOR1: General Purpose I/O Register 1 + GPIOR1_GPIOR1 = 0xff // General Purpose I/O bits + + // GPIOR0: General Purpose I/O Register 0 + GPIOR0_GPIOR0 = 0xff // General Purpose I/O bits +) diff --git a/src/device/avr/atmega328.ld b/src/device/avr/atmega328.ld new file mode 100644 index 00000000..257cc1bc --- /dev/null +++ b/src/device/avr/atmega328.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega328.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_size = 0x800; +__num_isrs = 26; diff --git a/src/device/avr/atmega328p.go b/src/device/avr/atmega328p.go new file mode 100644 index 00000000..44870a57 --- /dev/null +++ b/src/device/avr/atmega328p.go @@ -0,0 +1,643 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega328P.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega328p + +// Device information for the ATmega328P. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega328P" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_PCINT0 = 3 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 4 // Pin Change Interrupt Request 1 + IRQ_PCINT2 = 5 // Pin Change Interrupt Request 2 + IRQ_WDT = 6 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 7 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 8 // Timer/Counter2 Compare Match B + IRQ_TIMER2_OVF = 9 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 10 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 11 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 12 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 13 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 14 // TimerCounter0 Compare Match A + IRQ_TIMER0_COMPB = 15 // TimerCounter0 Compare Match B + IRQ_TIMER0_OVF = 16 // Timer/Couner0 Overflow + IRQ_SPI_STC = 17 // SPI Serial Transfer Complete + IRQ_USART_RX = 18 // USART Rx Complete + IRQ_USART_UDRE = 19 // USART, Data Register Empty + IRQ_USART_TX = 20 // USART Tx Complete + IRQ_ADC = 21 // ADC Conversion Complete + IRQ_EE_READY = 22 // EEPROM Ready + IRQ_ANALOG_COMP = 23 // Analog Comparator + IRQ_TWI = 24 // Two-wire Serial Interface + IRQ_SPM_Ready = 25 // Store Program Memory Read + IRQ_max = 25 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + ADCSRB __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // The ADC Control and Status register A + ADCSRB: 0x7b, // The ADC Control and Status register B + DIDR0: 0x7e, // Digital Input Disable Register + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // I/O Port + PORT = struct { + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + }{ + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCICR __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + } + + // Serial Peripheral Interface + SPI = struct { + SPDR __reg + SPSR __reg + SPCR __reg + }{ + SPDR: 0x4e, // SPI Data Register + SPSR: 0x4d, // SPI Status Register + SPCR: 0x4c, // SPI Control Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // CPU Registers + CPU = struct { + PRR __reg + OSCCAL __reg + CLKPR __reg + SREG __reg + SPL __reg + SPH __reg + SPMCSR __reg + MCUCR __reg + MCUSR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + PRR: 0x64, // Power Reduction Register + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + SPMCSR: 0x57, // Store Program Memory Control and Status Register + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose I/O Register 2 + GPIOR1: 0x4a, // General Purpose I/O Register 1 + GPIOR0: 0x3e, // General Purpose I/O Register 0 + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Bytes + EEARH: 0x41, // EEPROM Address Register Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // HIGH + HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PC6 as i/o pin) + HIGH_DWEN = 0x40 // Debug Wire enable + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watch-dog Timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select boot size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTB0 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0xc0 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TIMSK1: Timer/Counter Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output CompareB Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output CompareA Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 + TCCR1C_FOC1B = 0x40 +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2B = 0x4 // Output Compare Flag 2B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Output Mode bits + TCCR2A_COM2B = 0x30 // Compare Output Mode bits + TCCR2A_WGM2 = 0x3 // Waveform Genration Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy + ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0xf // Analog Channel Selection Bits + + // ADCSRA: The ADC Control and Status register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCSRB: The ADC Control and Status register B + ADCSRB_ACME = 0x40 + ADCSRB_ADTS = 0x7 // ADC Auto Trigger Source bits + + // DIDR0: Digital Input Disable Register + DIDR0_ADC5D = 0x20 + DIDR0_ADC4D = 0x10 + DIDR0_ADC3D = 0x8 + DIDR0_ADC2D = 0x4 + DIDR0_ADC1D = 0x2 + DIDR0_ADC0D = 0x1 +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register + EICRA_ISC1 = 0xc // External Interrupt Sense Control 1 Bits + EICRA_ISC0 = 0x3 // External Interrupt Sense Control 0 Bits + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0x3 // External Interrupt Request 1 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0x3 // External Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0x7 // Pin Change Interrupt Enables + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0x7f // Pin Change Enable Masks + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0x7 // Pin Change Interrupt Flags +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for CPU: CPU Registers +const ( + // PRR: Power Reduction Register + PRR_PRTWI = 0x80 // Power Reduction TWI + PRR_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // SPMCSR: Store Program Memory Control and Status Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read-While-Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read-While-Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory + + // MCUCR: MCU Control Register + MCUCR_BODS = 0x40 // BOD Sleep + MCUCR_BODSE = 0x20 // BOD Sleep Enable + MCUCR_PUD = 0x10 + MCUCR_IVSEL = 0x2 + MCUCR_IVCE = 0x1 + + // MCUSR: MCU Status Register + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BORF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select Bits + SMCR_SE = 0x1 // Sleep Enable +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) diff --git a/src/device/avr/atmega328p.ld b/src/device/avr/atmega328p.ld new file mode 100644 index 00000000..00e0bdd7 --- /dev/null +++ b/src/device/avr/atmega328p.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega328P.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_size = 0x800; +__num_isrs = 26; diff --git a/src/device/avr/atmega328pb.go b/src/device/avr/atmega328pb.go new file mode 100644 index 00000000..7d585d66 --- /dev/null +++ b/src/device/avr/atmega328pb.go @@ -0,0 +1,916 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega328PB.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega328pb + +// Device information for the ATmega328PB. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega328PB" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_PCINT0 = 3 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 4 // Pin Change Interrupt Request 1 + IRQ_PCINT2 = 5 // Pin Change Interrupt Request 2 + IRQ_WDT = 6 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 7 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 8 // Timer/Counter2 Compare Match B + IRQ_TIMER2_OVF = 9 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 10 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 11 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 12 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 13 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 14 // TimerCounter0 Compare Match A + IRQ_TIMER0_COMPB = 15 // TimerCounter0 Compare Match B + IRQ_TIMER0_OVF = 16 // Timer/Couner0 Overflow + IRQ_SPI0_STC = 17 // SPI Serial Transfer Complete + IRQ_USART0_RX = 18 // USART0 Rx Complete + IRQ_USART0_UDRE = 19 // USART0, Data Register Empty + IRQ_USART0_TX = 20 // USART0 Tx Complete + IRQ_ADC = 21 // ADC Conversion Complete + IRQ_EE_READY = 22 // EEPROM Ready + IRQ_ANALOG_COMP = 23 // Analog Comparator + IRQ_TWI0 = 24 // Two-wire Serial Interface + IRQ_SPM_Ready = 25 // Store Program Memory Read + IRQ_USART0_START = 26 // USART0 Start frame detection + IRQ_PCINT3 = 27 // Pin Change Interrupt Request 3 + IRQ_USART1_RX = 28 // USART1 Rx Complete + IRQ_USART1_UDRE = 29 // USART1, Data Register Empty + IRQ_USART1_TX = 30 // USART1 Tx Complete + IRQ_USART1_START = 31 // USART1 Start frame detection + IRQ_TIMER3_CAPT = 32 // Timer/Counter3 Capture Event + IRQ_TIMER3_COMPA = 33 // Timer/Counter3 Compare Match A + IRQ_TIMER3_COMPB = 34 // Timer/Counter3 Compare Match B + IRQ_TIMER3_OVF = 35 // Timer/Counter3 Overflow + IRQ_CFD = 36 // Clock failure detection interrupt + IRQ_PTC_EOC = 37 // PTC End of conversion + IRQ_PTC_WCOMP = 38 // PTC Window comparator mode + IRQ_SPI1_STC = 39 // SPI1 Serial Transfer Complete + IRQ_TWI1 = 40 // TWI Transfer Complete + IRQ_TIMER4_CAPT = 41 // Timer/Counter4 Capture Event + IRQ_TIMER4_COMPA = 42 // Timer/Counter4 Compare Match A + IRQ_TIMER4_COMPB = 43 // Timer/Counter4 Compare Match B + IRQ_TIMER4_OVF = 44 // Timer/Counter4 Overflow + IRQ_max = 44 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UCSR0D __reg + UBRR0L __reg + UBRR0H __reg + UDR1 __reg + UCSR1A __reg + UCSR1B __reg + UCSR1C __reg + UCSR1D __reg + UBRR1L __reg + UBRR1H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register 0 + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UCSR0D: 0xc3, // USART Control and Status Register D + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + UDR1: 0xce, // USART I/O Data Register + UCSR1A: 0xc8, // USART Control and Status Register A + UCSR1B: 0xc9, // USART Control and Status Register B + UCSR1C: 0xca, // USART Control and Status Register C + UCSR1D: 0xcb, // USART Control and Status Register D + UBRR1L: 0xcc, // USART Baud Rate Register Bytes + UBRR1H: 0xcc, // USART Baud Rate Register Bytes + } + + // + TWI = struct { + TWAMR0 __reg + TWBR0 __reg + TWCR0 __reg + TWSR0 __reg + TWDR0 __reg + TWAR0 __reg + TWAMR1 __reg + TWBR1 __reg + TWCR1 __reg + TWSR1 __reg + TWDR1 __reg + TWAR1 __reg + }{ + TWAMR0: 0xbd, // TWI (Slave) Address Mask Register + TWBR0: 0xb8, // TWI Bit Rate register + TWCR0: 0xbc, // TWI Control Register + TWSR0: 0xb9, // TWI Status Register + TWDR0: 0xbb, // TWI Data register + TWAR0: 0xba, // TWI (Slave) Address register + TWAMR1: 0xdd, // TWI (Slave) Address Mask Register + TWBR1: 0xd8, // TWI Bit Rate register + TWCR1: 0xdc, // TWI Control Register + TWSR1: 0xd9, // TWI Status Register + TWDR1: 0xdb, // TWI Data register + TWAR1: 0xda, // TWI (Slave) Address register + } + + // + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + TIMSK3 __reg + TIFR3 __reg + TCCR3A __reg + TCCR3B __reg + TCCR3C __reg + TCNT3L __reg + TCNT3H __reg + OCR3AL __reg + OCR3AH __reg + OCR3BL __reg + OCR3BH __reg + ICR3L __reg + ICR3H __reg + TIMSK4 __reg + TIFR4 __reg + TCCR4A __reg + TCCR4B __reg + TCCR4C __reg + TCNT4L __reg + TCNT4H __reg + OCR4AL __reg + OCR4AH __reg + OCR4BL __reg + OCR4BH __reg + ICR4L __reg + ICR4H __reg + }{ + TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK3: 0x71, // Timer/Counter Interrupt Mask Register + TIFR3: 0x38, // Timer/Counter3 Interrupt Flag register + TCCR3A: 0x90, // Timer/Counter3 Control Register A + TCCR3B: 0x91, // Timer/Counter3 Control Register B + TCCR3C: 0x92, // Timer/Counter3 Control Register C + TCNT3L: 0x94, // Timer/Counter3 Bytes + TCNT3H: 0x94, // Timer/Counter3 Bytes + OCR3AL: 0x98, // Timer/Counter3 Output Compare Register Bytes + OCR3AH: 0x98, // Timer/Counter3 Output Compare Register Bytes + OCR3BL: 0x9a, // Timer/Counter3 Output Compare Register Bytes + OCR3BH: 0x9a, // Timer/Counter3 Output Compare Register Bytes + ICR3L: 0x96, // Timer/Counter3 Input Capture Register Bytes + ICR3H: 0x96, // Timer/Counter3 Input Capture Register Bytes + TIMSK4: 0x72, // Timer/Counter4 Interrupt Mask Register + TIFR4: 0x39, // Timer/Counter4 Interrupt Flag register + TCCR4A: 0xa0, // Timer/Counter4 Control Register A + TCCR4B: 0xa1, // Timer/Counter4 Control Register B + TCCR4C: 0xa2, // Timer/Counter4 Control Register C + TCNT4L: 0xa4, // Timer/Counter4 Bytes + TCNT4H: 0xa4, // Timer/Counter4 Bytes + OCR4AL: 0xa8, // Timer/Counter4 Output Compare Register Bytes + OCR4AH: 0xa8, // Timer/Counter4 Output Compare Register Bytes + OCR4BL: 0xaa, // Timer/Counter4 Output Compare Register Bytes + OCR4BH: 0xaa, // Timer/Counter4 Output Compare Register Bytes + ICR4L: 0xa6, // Timer/Counter4 Input Capture Register Bytes + ICR4H: 0xa6, // Timer/Counter4 Input Capture Register Bytes + } + + // + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + ADCSRB __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // The ADC Control and Status register A + ADCSRB: 0x7b, // The ADC Control and Status register B + DIDR0: 0x7e, // Digital Input Disable Register + } + + // + AC = struct { + ACSRA __reg + ACSR __reg + ACSRB __reg + DIDR1 __reg + }{ + ACSRA: 0x50, // Analog Comparator Control And Status Register-A + ACSR: 0x50, // Analog Comparator Control And Status Register + ACSRB: 0x4f, // Analog Comparator Control And Status Register-B + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // + PORT = struct { + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + }{ + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Port E Data Register + DDRE: 0x2d, // Port E Data Direction Register + PINE: 0x2c, // Port E Input Pins + } + + // + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCICR __reg + PCMSK3 __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + PCMSK3: 0x73, // Pin Change Mask Register 3 + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + } + + // + SPI = struct { + SPDR0 __reg + SPSR0 __reg + SPCR0 __reg + SPDR1 __reg + SPSR1 __reg + SPCR1 __reg + }{ + SPDR0: 0x4e, // SPI Data Register + SPSR0: 0x4d, // SPI Status Register + SPCR0: 0x4c, // SPI Control Register + SPDR1: 0xae, // SPI Data Register + SPSR1: 0xad, // SPI Status Register + SPCR1: 0xac, // SPI Control Register + } + + // + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // + CFD = struct { + XFDCSR __reg + }{ + XFDCSR: 0x62, // XOSC Failure Detection Control and Status Register + } + + // + PTC = struct { + }{} + + // + CPU = struct { + PRR0 __reg + PRR1 __reg + OSCCAL __reg + CLKPR __reg + SREG __reg + SPL __reg + SPH __reg + SPMCSR __reg + MCUCR __reg + MCUSR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + PRR0: 0x64, // Power Reduction Register 0 + PRR1: 0x65, // Power Reduction Register 1 + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + SPMCSR: 0x57, // Store Program Memory Control and Status Register + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose I/O Register 2 + GPIOR1: 0x4a, // General Purpose I/O Register 1 + GPIOR0: 0x3e, // General Purpose I/O Register 0 + } + + // + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Bytes + EEARH: 0x41, // EEPROM Address Register Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } +) + +// Bitfields for FUSE: +const ( + // EXTENDED + EXTENDED_CFD = 0x8 // Clock Failure Detection + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // HIGH + HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PC6 as i/o pin) + HIGH_DWEN = 0x40 // Debug Wire enable + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watch-dog Timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select boot size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTB0 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for USART: +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0xc0 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity + + // UCSR0D: USART Control and Status Register D + UCSR0D_RXSIE = 0x80 // USART RX Start Interrupt Enable + UCSR0D_RXS = 0x40 // USART RX Start + UCSR0D_SFDE = 0x20 // Start frame detection enable + + // UCSR1A: USART Control and Status Register A + UCSR1A_RXC1 = 0x80 // USART Receive Complete + UCSR1A_TXC1 = 0x40 // USART Transmitt Complete + UCSR1A_UDRE1 = 0x20 // USART Data Register Empty + UCSR1A_FE1 = 0x10 // Framing Error + UCSR1A_DOR1 = 0x8 // Data overRun + UCSR1A_UPE1 = 0x4 // Parity Error + UCSR1A_U2X1 = 0x2 // Double the USART transmission speed + UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode + + // UCSR1B: USART Control and Status Register B + UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable + UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable + UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable + UCSR1B_RXEN1 = 0x10 // Receiver Enable + UCSR1B_TXEN1 = 0x8 // Transmitter Enable + UCSR1B_UCSZ12 = 0x4 // Character Size + UCSR1B_RXB81 = 0x2 // Receive Data Bit 8 + UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8 + + // UCSR1C: USART Control and Status Register C + UCSR1C_UMSEL1 = 0xc0 // USART Mode Select + UCSR1C_UPM1 = 0x30 // Parity Mode Bits + UCSR1C_USBS1 = 0x8 // Stop Bit Select + UCSR1C_UCSZ1 = 0x6 // Character Size + UCSR1C_UCPOL1 = 0x1 // Clock Polarity + + // UCSR1D: USART Control and Status Register D + UCSR1D_RXSIE1 = 0x80 // USART RX Start Interrupt Enable + UCSR1D_RXS1 = 0x40 // USART RX Start + UCSR1D_SFDE1 = 0x20 // Start frame detection enable +) + +// Bitfields for TWI: +const ( + // TWAMR0: TWI (Slave) Address Mask Register + TWAMR0_TWAM = 0xfe + + // TWCR0: TWI Control Register + TWCR0_TWINT = 0x80 // TWI Interrupt Flag + TWCR0_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR0_TWSTA = 0x20 // TWI Start Condition Bit + TWCR0_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR0_TWWC = 0x8 // TWI Write Collition Flag + TWCR0_TWEN = 0x4 // TWI Enable Bit + TWCR0_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR0: TWI Status Register + TWSR0_TWS = 0xf8 // TWI Status + TWSR0_TWPS = 0x3 // TWI Prescaler + + // TWAR0: TWI (Slave) Address register + TWAR0_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR0_TWGCE = 0x1 // TWI General Call Recognition Enable Bit + + // TWAMR1: TWI (Slave) Address Mask Register + TWAMR1_TWAM1 = 0xfe + + // TWCR1: TWI Control Register + TWCR1_TWINT1 = 0x80 // TWI Interrupt Flag + TWCR1_TWEA1 = 0x40 // TWI Enable Acknowledge Bit + TWCR1_TWSTA1 = 0x20 // TWI Start Condition Bit + TWCR1_TWSTO1 = 0x10 // TWI Stop Condition Bit + TWCR1_TWWC1 = 0x8 // TWI Write Collition Flag + TWCR1_TWEN1 = 0x4 // TWI Enable Bit + TWCR1_TWIE1 = 0x1 // TWI Interrupt Enable + + // TWSR1: TWI Status Register + TWSR1_TWS1 = 0xf8 // TWI Status + TWSR1_TWPS1 = 0x3 // TWI Prescaler +) + +// Bitfields for TC16: +const ( + // TIMSK1: Timer/Counter Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output CompareB Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output CompareA Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 + TCCR1C_FOC1B = 0x40 + + // TIMSK3: Timer/Counter Interrupt Mask Register + TIMSK3_ICIE3 = 0x20 // Timer/Counter3 Input Capture Interrupt Enable + TIMSK3_OCIE3B = 0x4 // Timer/Counter3 Output Compare Match B Interrupt Enable + TIMSK3_OCIE3A = 0x2 // Timer/Counter3 Output Compare Match A Interrupt Enable + TIMSK3_TOIE3 = 0x1 // Timer/Counter3 Overflow Interrupt Enable + + // TIFR3: Timer/Counter3 Interrupt Flag register + TIFR3_OCF3B = 0x4 // Output Compare Flag 3B + TIFR3_OCF3A = 0x2 // Output Compare Flag 3A + TIFR3_TOV3 = 0x1 // Timer/Counter3 Overflow Flag + + // TCCR3A: Timer/Counter3 Control Register A + TCCR3A_COM3A = 0xc0 // Compare Output Mode bits + TCCR3A_COM3B = 0x30 // Compare Output Mode bits + TCCR3A_WGM3 = 0x3 // Waveform Genration Mode + + // TCCR3B: Timer/Counter3 Control Register B + TCCR3B_ICNC3 = 0x80 // Input Capture Noise Canceler + TCCR3B_ICES3 = 0x40 // Input Capture Edge Select + TCCR3B_WGM33 = 0x10 // Waveform Generation Mode bit 3 + TCCR3B_WGM32 = 0x8 // Waveform Generation Mode bit 2 + TCCR3B_CS3 = 0x7 // Clock Select bits + + // TCCR3C: Timer/Counter3 Control Register C + TCCR3C_FOC3A = 0x80 // Force Output Compare for Channel A + TCCR3C_FOC3B = 0x40 // Force Output Compare for Channel B + + // TIMSK4: Timer/Counter4 Interrupt Mask Register + TIMSK4_ICIE4 = 0x20 // Timer/Counter4 Input Capture Interrupt Enable + TIMSK4_OCIE4B = 0x4 // Timer/Counter4 Output Compare Match B Interrupt Enable + TIMSK4_OCIE4A = 0x2 // Timer/Counter4 Output Compare Match A Interrupt Enable + TIMSK4_TOIE4 = 0x1 // Timer/Counter4 Overflow Interrupt Enable + + // TIFR4: Timer/Counter4 Interrupt Flag register + TIFR4_OCF4B = 0x4 // Output Compare Flag 4B + TIFR4_OCF4A = 0x2 // Output Compare Flag 4A + TIFR4_TOV4 = 0x1 // Timer/Counter4 Overflow Flag + + // TCCR4A: Timer/Counter4 Control Register A + TCCR4A_COM4A = 0xc0 // Compare Output Mode bits + TCCR4A_COM4B = 0x30 // Compare Output Mode bits + TCCR4A_WGM4 = 0x3 // Waveform Genration Mode + + // TCCR4B: Timer/Counter4 Control Register B + TCCR4B_ICNC4 = 0x80 // Input Capture Noise Canceler + TCCR4B_ICES4 = 0x40 // Input Capture Edge Select + TCCR4B_WGM43 = 0x10 // Waveform Generation Mode bit 3 + TCCR4B_WGM42 = 0x8 // Waveform Generation Mode bit 2 + TCCR4B_CS4 = 0x7 // Clock Select bits + + // TCCR4C: Timer/Counter4 Control Register C + TCCR4C_FOC4A = 0x80 // Force Output Compare for Channel A + TCCR4C_FOC4B = 0x40 // Force Output Compare for Channel B +) + +// Bitfields for TC8_ASYNC: +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2B = 0x4 // Output Compare Flag 2B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Output Mode bits + TCCR2A_COM2B = 0x30 // Compare Output Mode bits + TCCR2A_WGM2 = 0x3 // Waveform Genration Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy + ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy +) + +// Bitfields for ADC: +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0xf // Analog Channel Selection Bits + + // ADCSRA: The ADC Control and Status register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCSRB: The ADC Control and Status register B + ADCSRB_ACME = 0x40 + ADCSRB_ADTS = 0x7 // ADC Auto Trigger Source bits + + // DIDR0: Digital Input Disable Register + DIDR0_ADC5D = 0x20 + DIDR0_ADC4D = 0x10 + DIDR0_ADC3D = 0x8 + DIDR0_ADC2D = 0x4 + DIDR0_ADC1D = 0x2 + DIDR0_ADC0D = 0x1 +) + +// Bitfields for AC: +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // ACSRB: Analog Comparator Control And Status Register-B + ACSRB_ACOE = 0x1 // Analog Comparator Output Enable + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for TC8: +const ( + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWM + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for EXINT: +const ( + // EICRA: External Interrupt Control Register + EICRA_ISC1 = 0xc // External Interrupt Sense Control 1 Bits + EICRA_ISC0 = 0x3 // External Interrupt Sense Control 0 Bits + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0x3 // External Interrupt Request 1 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0x3 // External Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0xf // Pin Change Interrupt Enables + + // PCMSK3: Pin Change Mask Register 3 + PCMSK3_PCINT = 0xf // Pin Change Enable Masks + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0x7f // Pin Change Enable Masks + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0xf // Pin Change Interrupt Flags +) + +// Bitfields for SPI: +const ( + // SPSR0: SPI Status Register + SPSR0_SPIF = 0x80 // SPI Interrupt Flag + SPSR0_WCOL = 0x40 // Write Collision Flag + SPSR0_SPI2X = 0x1 // Double SPI Speed Bit + + // SPCR0: SPI Control Register + SPCR0_SPIE = 0x80 // SPI Interrupt Enable + SPCR0_SPE = 0x40 // SPI Enable + SPCR0_DORD = 0x20 // Data Order + SPCR0_MSTR = 0x10 // Master/Slave Select + SPCR0_CPOL = 0x8 // Clock polarity + SPCR0_CPHA = 0x4 // Clock Phase + SPCR0_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR1: SPI Status Register + SPSR1_SPIF1 = 0x80 // SPI Interrupt Flag + SPSR1_WCOL1 = 0x40 // Write Collision Flag + SPSR1_SPI2X1 = 0x1 // Double SPI Speed Bit + + // SPCR1: SPI Control Register + SPCR1_SPIE1 = 0x80 // SPI Interrupt Enable + SPCR1_SPE1 = 0x40 // SPI Enable + SPCR1_DORD1 = 0x20 // Data Order + SPCR1_MSTR1 = 0x10 // Master/Slave Select + SPCR1_CPOL1 = 0x8 // Clock polarity + SPCR1_CPHA1 = 0x4 // Clock Phase + SPCR1_SPR1 = 0x3 // SPI Clock Rate Selects +) + +// Bitfields for WDT: +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for CFD: +const ( + // XFDCSR: XOSC Failure Detection Control and Status Register + XFDCSR_XFDIF = 0x2 // Failure Detection Interrupt Flag + XFDCSR_XFDIE = 0x1 // Failure Detection Interrupt Enable +) + +// Bitfields for CPU: +const ( + // PRR0: Power Reduction Register 0 + PRR0_PRTWI0 = 0x80 // Power Reduction TWI0 + PRR0_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR0_PRUSART1 = 0x10 // Power Reduction USART1 + PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR0_PRSPI0 = 0x4 // Power Reduction Serial Peripheral Interface 1 + PRR0_PRUSART0 = 0x2 // Power Reduction USART0 + PRR0_PRADC = 0x1 // Power Reduction ADC + + // PRR1: Power Reduction Register 1 + PRR1_PRTWI1 = 0x20 // Power Reduction TWI1 + PRR1_PRPTC = 0x10 // Power Reduction Peripheral Touch Controller + PRR1_PRTIM4 = 0x8 // Power Reduction Timer/Counter4 + PRR1_PRSPI1 = 0x4 // Power Reduction Serial Peripheral Interface 1 + PRR1_PRTIM3 = 0x1 // Power Reduction Timer/Counter3 + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // SPMCSR: Store Program Memory Control and Status Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read-While-Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read-While-Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory + + // MCUCR: MCU Control Register + MCUCR_BODS = 0x40 // BOD Sleep + MCUCR_BODSE = 0x20 // BOD Sleep Enable + MCUCR_PUD = 0x10 + MCUCR_IVSEL = 0x2 + MCUCR_IVCE = 0x1 + + // MCUSR: MCU Status Register + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BORF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select Bits + SMCR_SE = 0x1 // Sleep Enable +) + +// Bitfields for EEPROM: +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) diff --git a/src/device/avr/atmega328pb.ld b/src/device/avr/atmega328pb.ld new file mode 100644 index 00000000..83a42f38 --- /dev/null +++ b/src/device/avr/atmega328pb.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega328PB.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_size = 0x800; +__num_isrs = 45; diff --git a/src/device/avr/atmega329.go b/src/device/avr/atmega329.go new file mode 100644 index 00000000..fe60da8a --- /dev/null +++ b/src/device/avr/atmega329.go @@ -0,0 +1,676 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega329.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega329 + +// Device information for the ATmega329. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega329" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_PCINT0 = 2 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 3 // Pin Change Interrupt Request 1 + IRQ_TIMER2_COMP = 4 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 5 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 6 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 7 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 8 // Timer/Counter Compare Match B + IRQ_TIMER1_OVF = 9 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 10 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 11 // Timer/Counter0 Overflow + IRQ_SPI_STC = 12 // SPI Serial Transfer Complete + IRQ_USART0_RX = 13 // USART0, Rx Complete + IRQ_USART0_UDRE = 14 // USART0 Data register Empty + IRQ_USART0_TX = 15 // USART0, Tx Complete + IRQ_USI_START = 16 // USI Start Condition + IRQ_USI_OVERFLOW = 17 // USI Overflow + IRQ_ANALOG_COMP = 18 // Analog Comparator + IRQ_ADC = 19 // ADC Conversion Complete + IRQ_EE_READY = 20 // EEPROM Ready + IRQ_SPM_READY = 21 // Store Program Memory Read + IRQ_LCD = 22 // LCD Start of Frame + IRQ_max = 22 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0A __reg + TCNT0 __reg + OCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR0A: 0x44, // Timer/Counter0 Control Register + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2A __reg + TCNT2 __reg + OCR2A __reg + TIMSK2 __reg + TIFR2 __reg + ASSR __reg + }{ + TCCR2A: 0xb0, // Timer/Counter2 Control Register + TCNT2: 0xb2, // Timer/Counter2 + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register + TIMSK2: 0x70, // Timer/Counter2 Interrupt Mask register + TIFR2: 0x37, // Timer/Counter2 Interrupt Flag Register + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x60, // Watchdog Timer Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access Bytes + EEARH: 0x41, // EEPROM Read/Write Access Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + PORTG: 0x34, // Port G Data Register + DDRG: 0x33, // Port G Data Direction Register + PING: 0x32, // Port G Input Pins + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // Liquid Crystal Display + LCD = struct { + LCDDR18 __reg + LCDDR17 __reg + LCDDR16 __reg + LCDDR15 __reg + LCDDR13 __reg + LCDDR12 __reg + LCDDR11 __reg + LCDDR10 __reg + LCDDR08 __reg + LCDDR07 __reg + LCDDR06 __reg + LCDDR05 __reg + LCDDR03 __reg + LCDDR02 __reg + LCDDR01 __reg + LCDDR00 __reg + LCDCCR __reg + LCDFRR __reg + LCDCRB __reg + LCDCRA __reg + }{ + LCDDR18: 0xfe, // LCD Data Register 18 + LCDDR17: 0xfd, // LCD Data Register 17 + LCDDR16: 0xfc, // LCD Data Register 16 + LCDDR15: 0xfb, // LCD Data Register 15 + LCDDR13: 0xf9, // LCD Data Register 13 + LCDDR12: 0xf8, // LCD Data Register 12 + LCDDR11: 0xf7, // LCD Data Register 11 + LCDDR10: 0xf6, // LCD Data Register 10 + LCDDR08: 0xf4, // LCD Data Register 8 + LCDDR07: 0xf3, // LCD Data Register 7 + LCDDR06: 0xf2, // LCD Data Register 6 + LCDDR05: 0xf1, // LCD Data Register 5 + LCDDR03: 0xef, // LCD Data Register 3 + LCDDR02: 0xee, // LCD Data Register 2 + LCDDR01: 0xed, // LCD Data Register 1 + LCDDR00: 0xec, // LCD Data Register 0 + LCDCCR: 0xe7, // LCD Contrast Control Register + LCDFRR: 0xe6, // LCD Frame Rate Register + LCDCRB: 0xe5, // LCD Control and Status Register B + LCDCRA: 0xe4, // LCD Control and Status Register A + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK1 __reg + PCMSK0 __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + PRR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + PRR: 0x64, // Power Reduction Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + } + + // Universal Serial Interface + USI = struct { + USIDR __reg + USISR __reg + USICR __reg + }{ + USIDR: 0xba, // USI Data Register + USISR: 0xb9, // USI Status Register + USICR: 0xb8, // USI Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 0 + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x6 // Brown-out Detector trigger level + EXTENDED_RSTDISBL = 0x1 // External Reset Disable + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM memory through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0A: Timer/Counter0 Control Register + TCCR0A_FOC0A = 0x80 // Force Output Compare + TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0A_COM0A = 0x30 // Compare Match Output Modes + TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0A_CS0 = 0x7 // Clock Selects + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0 + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2A: Timer/Counter2 Control Register + TCCR2A_FOC2A = 0x80 // Force Output Compare A + TCCR2A_WGM20 = 0x40 // Waveform Generation Mode + TCCR2A_COM2A = 0x30 // Compare Output Mode bits + TCCR2A_WGM21 = 0x8 // Waveform Generation Mode + TCCR2A_CS2 = 0x7 // Clock Select bits + + // TIMSK2: Timer/Counter2 Interrupt Mask register + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter2 Interrupt Flag Register + TIFR2_OCF2A = 0x2 // Timer/Counter2 Output Compare Flag 2 + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x10 // Enable External Clock Interrupt + ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for LCD: Liquid Crystal Display +const ( + // LCDCCR: LCD Contrast Control Register + LCDCCR_LCDDC = 0xe0 // LCD Display Configuration + LCDCCR_LCDCC = 0xf // LCD Contrast Control + + // LCDFRR: LCD Frame Rate Register + LCDFRR_LCDPS = 0x70 // LCD Prescaler Selects + LCDFRR_LCDCD = 0x7 // LCD Clock Dividers + + // LCDCRB: LCD Control and Status Register B + LCDCRB_LCDCS = 0x80 // LCD CLock Select + LCDCRB_LCD2B = 0x40 // LCD 1/2 Bias Select + LCDCRB_LCDMUX = 0x30 // LCD Mux Selects + LCDCRB_LCDPM = 0xf // LCD Port Masks + + // LCDCRA: LCD Control and Status Register A + LCDCRA_LCDEN = 0x80 // LCD Enable + LCDCRA_LCDAB = 0x40 // LCD A or B waveform + LCDCRA_LCDIF = 0x10 // LCD Interrupt Flag + LCDCRA_LCDIE = 0x8 // LCD Interrupt Enable + LCDCRA_LCDBL = 0x1 // LCD Blanking +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC01 = 0x2 // External Interrupt Sense Control 0 Bit 1 + EICRA_ISC00 = 0x1 // External Interrupt Sense Control 0 Bit 0 + + // EIMSK: External Interrupt Mask Register + EIMSK_PCIE = 0xf0 // Pin Change Interrupt Enables + EIMSK_INT0 = 0x1 // External Interrupt Request 0 Enable + + // EIFR: External Interrupt Flag Register + EIFR_PCIF = 0xf0 // Pin Change Interrupt Flags + EIFR_INTF0 = 0x1 // External Interrupt Flag 0 + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Mask + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Mask +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // PRR: Power Reduction Register + PRR_PRLCD = 0x10 // Power Reduction LCD + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable +) + +// Bitfields for USI: Universal Serial Interface +const ( + // USISR: USI Status Register + USISR_USISIF = 0x80 // Start Condition Interrupt Flag + USISR_USIOIF = 0x40 // Counter Overflow Interrupt Flag + USISR_USIPF = 0x20 // Stop Condition Flag + USISR_USIDC = 0x10 // Data Output Collision + USISR_USICNT = 0xf // USI Counter Value Bits + + // USICR: USI Control Register + USICR_USISIE = 0x80 // Start Condition Interrupt Enable + USICR_USIOIE = 0x40 // Counter Overflow Interrupt Enable + USICR_USIWM = 0x30 // USI Wire Mode Bits + USICR_USICS = 0xc // USI Clock Source Select Bits + USICR_USICLK = 0x2 // Clock Strobe + USICR_USITC = 0x1 // Toggle Clock Port Pin +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmit Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data OverRun + UCSR0A_UPE0 = 0x4 // USART Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART Transmission Speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data Register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0x40 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) diff --git a/src/device/avr/atmega329.ld b/src/device/avr/atmega329.ld new file mode 100644 index 00000000..f9c3895c --- /dev/null +++ b/src/device/avr/atmega329.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega329.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_size = 0x800; +__num_isrs = 23; diff --git a/src/device/avr/atmega3290.go b/src/device/avr/atmega3290.go new file mode 100644 index 00000000..03ec9b6c --- /dev/null +++ b/src/device/avr/atmega3290.go @@ -0,0 +1,708 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega3290.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega3290 + +// Device information for the ATmega3290. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega3290" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_PCINT0 = 2 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 3 // Pin Change Interrupt Request 1 + IRQ_TIMER2_COMP = 4 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 5 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 6 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 7 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 8 // Timer/Counter Compare Match B + IRQ_TIMER1_OVF = 9 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 10 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 11 // Timer/Counter0 Overflow + IRQ_SPI_STC = 12 // SPI Serial Transfer Complete + IRQ_USART_RX = 13 // USART, Rx Complete + IRQ_USART_UDRE = 14 // USART Data register Empty + IRQ_USART0_TX = 15 // USART0, Tx Complete + IRQ_USI_START = 16 // USI Start Condition + IRQ_USI_OVERFLOW = 17 // USI Overflow + IRQ_ANALOG_COMP = 18 // Analog Comparator + IRQ_ADC = 19 // ADC Conversion Complete + IRQ_EE_READY = 20 // EEPROM Ready + IRQ_SPM_READY = 21 // Store Program Memory Read + IRQ_LCD = 22 // LCD Start of Frame + IRQ_PCINT2 = 23 // Pin Change Interrupt Request 2 + IRQ_PCINT3 = 24 // Pin Change Interrupt Request 3 + IRQ_max = 24 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0A __reg + TCNT0 __reg + OCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR0A: 0x44, // Timer/Counter0 Control Register + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2A __reg + TCNT2 __reg + OCR2A __reg + TIMSK2 __reg + TIFR2 __reg + ASSR __reg + }{ + TCCR2A: 0xb0, // Timer/Counter2 Control Register + TCNT2: 0xb2, // Timer/Counter2 + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register + TIMSK2: 0x70, // Timer/Counter2 Interrupt Mask register + TIFR2: 0x37, // Timer/Counter2 Interrupt Flag Register + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x60, // Watchdog Timer Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access Bytes + EEARH: 0x41, // EEPROM Read/Write Access Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + PORTH __reg + DDRH __reg + PINH __reg + PORTJ __reg + DDRJ __reg + PINJ __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + PORTG: 0x34, // Port G Data Register + DDRG: 0x33, // Port G Data Direction Register + PING: 0x32, // Port G Input Pins + PORTH: 0xda, // PORT H Data Register + DDRH: 0xd9, // PORT H Data Direction Register + PINH: 0xd8, // PORT H Input Pins + PORTJ: 0xdd, // PORT J Data Register + DDRJ: 0xdc, // PORT J Data Direction Register + PINJ: 0xdb, // PORT J Input Pins + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // Liquid Crystal Display + LCD = struct { + LCDDR19 __reg + LCDDR18 __reg + LCDDR17 __reg + LCDDR16 __reg + LCDDR15 __reg + LCDDR14 __reg + LCDDR13 __reg + LCDDR12 __reg + LCDDR11 __reg + LCDDR10 __reg + LCDDR09 __reg + LCDDR08 __reg + LCDDR07 __reg + LCDDR06 __reg + LCDDR05 __reg + LCDDR04 __reg + LCDDR03 __reg + LCDDR02 __reg + LCDDR01 __reg + LCDDR00 __reg + LCDCCR __reg + LCDFRR __reg + LCDCRB __reg + LCDCRA __reg + }{ + LCDDR19: 0xff, // LCD Data Register 19 + LCDDR18: 0xfe, // LCD Data Register 18 + LCDDR17: 0xfd, // LCD Data Register 17 + LCDDR16: 0xfc, // LCD Data Register 16 + LCDDR15: 0xfb, // LCD Data Register 15 + LCDDR14: 0xfa, // LCD Data Register 14 + LCDDR13: 0xf9, // LCD Data Register 13 + LCDDR12: 0xf8, // LCD Data Register 12 + LCDDR11: 0xf7, // LCD Data Register 11 + LCDDR10: 0xf6, // LCD Data Register 10 + LCDDR09: 0xf5, // LCD Data Register 9 + LCDDR08: 0xf4, // LCD Data Register 8 + LCDDR07: 0xf3, // LCD Data Register 7 + LCDDR06: 0xf2, // LCD Data Register 6 + LCDDR05: 0xf1, // LCD Data Register 5 + LCDDR04: 0xf0, // LCD Data Register 4 + LCDDR03: 0xef, // LCD Data Register 3 + LCDDR02: 0xee, // LCD Data Register 2 + LCDDR01: 0xed, // LCD Data Register 1 + LCDDR00: 0xec, // LCD Data Register 0 + LCDCCR: 0xe7, // LCD Contrast Control Register + LCDFRR: 0xe6, // LCD Frame Rate Register + LCDCRB: 0xe5, // LCD Control and Status Register B + LCDCRA: 0xe4, // LCD Control and Status Register A + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK3 __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK3: 0x73, // Pin Change Mask Register 3 + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + PRR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + PRR: 0x64, // Power Reduction Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + } + + // Universal Serial Interface + USI = struct { + USIDR __reg + USISR __reg + USICR __reg + }{ + USIDR: 0xba, // USI Data Register + USISR: 0xb9, // USI Status Register + USICR: 0xb8, // USI Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 0 + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x6 // Brown-out Detector trigger level + EXTENDED_RSTDISBL = 0x1 // External Reset Disable + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM memory through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0A: Timer/Counter0 Control Register + TCCR0A_FOC0A = 0x80 // Force Output Compare + TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0A_COM0A = 0x30 // Compare Match Output Modes + TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0A_CS0 = 0x7 // Clock Selects + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0 + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2A: Timer/Counter2 Control Register + TCCR2A_FOC2A = 0x80 // Force Output Compare A + TCCR2A_WGM20 = 0x40 // Waveform Generation Mode + TCCR2A_COM2A = 0x30 // Compare Output Mode bits + TCCR2A_WGM21 = 0x8 // Waveform Generation Mode + TCCR2A_CS2 = 0x7 // Clock Select bits + + // TIMSK2: Timer/Counter2 Interrupt Mask register + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter2 Interrupt Flag Register + TIFR2_OCF2A = 0x2 // Timer/Counter2 Output Compare Flag 2 + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x10 // Enable External Clock Interrupt + ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for LCD: Liquid Crystal Display +const ( + // LCDCCR: LCD Contrast Control Register + LCDCCR_LCDDC = 0xe0 // LCD Display Configuration + LCDCCR_LCDCC = 0xf // LCD Contrast Control + + // LCDFRR: LCD Frame Rate Register + LCDFRR_LCDPS = 0x70 // LCD Prescaler Selects + LCDFRR_LCDCD = 0x7 // LCD Clock Dividers + + // LCDCRB: LCD Control and Status Register B + LCDCRB_LCDCS = 0x80 // LCD CLock Select + LCDCRB_LCD2B = 0x40 // LCD 1/2 Bias Select + LCDCRB_LCDMUX = 0x30 // LCD Mux Selects + LCDCRB_LCDPM = 0xf // LCD Port Masks + + // LCDCRA: LCD Control and Status Register A + LCDCRA_LCDEN = 0x80 // LCD Enable + LCDCRA_LCDAB = 0x40 // LCD A or B waveform + LCDCRA_LCDIF = 0x10 // LCD Interrupt Flag + LCDCRA_LCDIE = 0x8 // LCD Interrupt Enable + LCDCRA_LCDBL = 0x1 // LCD Blanking +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC01 = 0x2 // External Interrupt Sense Control 0 Bit 1 + EICRA_ISC00 = 0x1 // External Interrupt Sense Control 0 Bit 0 + + // EIMSK: External Interrupt Mask Register + EIMSK_PCIE = 0xf0 // Pin Change Interrupt Enables + EIMSK_INT0 = 0x1 // External Interrupt Request 0 Enable + + // EIFR: External Interrupt Flag Register + EIFR_PCIF = 0xf0 // Pin Change Interrupt Flags + EIFR_INTF0 = 0x1 // External Interrupt Flag 0 + + // PCMSK3: Pin Change Mask Register 3 + PCMSK3_PCINT = 0x7f // Pin Change Mask + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Mask + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Mask + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Mask +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // PRR: Power Reduction Register + PRR_PRLCD = 0x10 // Power Reduction LCD + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable +) + +// Bitfields for USI: Universal Serial Interface +const ( + // USISR: USI Status Register + USISR_USISIF = 0x80 // Start Condition Interrupt Flag + USISR_USIOIF = 0x40 // Counter Overflow Interrupt Flag + USISR_USIPF = 0x20 // Stop Condition Flag + USISR_USIDC = 0x10 // Data Output Collision + USISR_USICNT = 0xf // USI Counter Value Bits + + // USICR: USI Control Register + USICR_USISIE = 0x80 // Start Condition Interrupt Enable + USICR_USIOIE = 0x40 // Counter Overflow Interrupt Enable + USICR_USIWM = 0x30 // USI Wire Mode Bits + USICR_USICS = 0xc // USI Clock Source Select Bits + USICR_USICLK = 0x2 // Clock Strobe + USICR_USITC = 0x1 // Toggle Clock Port Pin +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmit Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data OverRun + UCSR0A_UPE0 = 0x4 // USART Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART Transmission Speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data Register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0x40 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) diff --git a/src/device/avr/atmega3290.ld b/src/device/avr/atmega3290.ld new file mode 100644 index 00000000..ec61385a --- /dev/null +++ b/src/device/avr/atmega3290.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega3290.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_size = 0x800; +__num_isrs = 25; diff --git a/src/device/avr/atmega3290a.go b/src/device/avr/atmega3290a.go new file mode 100644 index 00000000..e11d159a --- /dev/null +++ b/src/device/avr/atmega3290a.go @@ -0,0 +1,708 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega3290A.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega3290a + +// Device information for the ATmega3290A. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega3290A" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_PCINT0 = 2 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 3 // Pin Change Interrupt Request 1 + IRQ_TIMER2_COMP = 4 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 5 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 6 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 7 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 8 // Timer/Counter Compare Match B + IRQ_TIMER1_OVF = 9 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 10 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 11 // Timer/Counter0 Overflow + IRQ_SPI_STC = 12 // SPI Serial Transfer Complete + IRQ_USART_RX = 13 // USART, Rx Complete + IRQ_USART_UDRE = 14 // USART Data register Empty + IRQ_USART0_TX = 15 // USART0, Tx Complete + IRQ_USI_START = 16 // USI Start Condition + IRQ_USI_OVERFLOW = 17 // USI Overflow + IRQ_ANALOG_COMP = 18 // Analog Comparator + IRQ_ADC = 19 // ADC Conversion Complete + IRQ_EE_READY = 20 // EEPROM Ready + IRQ_SPM_READY = 21 // Store Program Memory Read + IRQ_LCD = 22 // LCD Start of Frame + IRQ_PCINT2 = 23 // Pin Change Interrupt Request 2 + IRQ_PCINT3 = 24 // Pin Change Interrupt Request 3 + IRQ_max = 24 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0A __reg + TCNT0 __reg + OCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR0A: 0x44, // Timer/Counter0 Control Register + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2A __reg + TCNT2 __reg + OCR2A __reg + TIMSK2 __reg + TIFR2 __reg + ASSR __reg + }{ + TCCR2A: 0xb0, // Timer/Counter2 Control Register + TCNT2: 0xb2, // Timer/Counter2 + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register + TIMSK2: 0x70, // Timer/Counter2 Interrupt Mask register + TIFR2: 0x37, // Timer/Counter2 Interrupt Flag Register + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x60, // Watchdog Timer Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access Bytes + EEARH: 0x41, // EEPROM Read/Write Access Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + PORTH __reg + DDRH __reg + PINH __reg + PORTJ __reg + DDRJ __reg + PINJ __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + PORTG: 0x34, // Port G Data Register + DDRG: 0x33, // Port G Data Direction Register + PING: 0x32, // Port G Input Pins + PORTH: 0xda, // PORT H Data Register + DDRH: 0xd9, // PORT H Data Direction Register + PINH: 0xd8, // PORT H Input Pins + PORTJ: 0xdd, // PORT J Data Register + DDRJ: 0xdc, // PORT J Data Direction Register + PINJ: 0xdb, // PORT J Input Pins + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // Liquid Crystal Display + LCD = struct { + LCDDR19 __reg + LCDDR18 __reg + LCDDR17 __reg + LCDDR16 __reg + LCDDR15 __reg + LCDDR14 __reg + LCDDR13 __reg + LCDDR12 __reg + LCDDR11 __reg + LCDDR10 __reg + LCDDR09 __reg + LCDDR08 __reg + LCDDR07 __reg + LCDDR06 __reg + LCDDR05 __reg + LCDDR04 __reg + LCDDR03 __reg + LCDDR02 __reg + LCDDR01 __reg + LCDDR00 __reg + LCDCCR __reg + LCDFRR __reg + LCDCRB __reg + LCDCRA __reg + }{ + LCDDR19: 0xff, // LCD Data Register 19 + LCDDR18: 0xfe, // LCD Data Register 18 + LCDDR17: 0xfd, // LCD Data Register 17 + LCDDR16: 0xfc, // LCD Data Register 16 + LCDDR15: 0xfb, // LCD Data Register 15 + LCDDR14: 0xfa, // LCD Data Register 14 + LCDDR13: 0xf9, // LCD Data Register 13 + LCDDR12: 0xf8, // LCD Data Register 12 + LCDDR11: 0xf7, // LCD Data Register 11 + LCDDR10: 0xf6, // LCD Data Register 10 + LCDDR09: 0xf5, // LCD Data Register 9 + LCDDR08: 0xf4, // LCD Data Register 8 + LCDDR07: 0xf3, // LCD Data Register 7 + LCDDR06: 0xf2, // LCD Data Register 6 + LCDDR05: 0xf1, // LCD Data Register 5 + LCDDR04: 0xf0, // LCD Data Register 4 + LCDDR03: 0xef, // LCD Data Register 3 + LCDDR02: 0xee, // LCD Data Register 2 + LCDDR01: 0xed, // LCD Data Register 1 + LCDDR00: 0xec, // LCD Data Register 0 + LCDCCR: 0xe7, // LCD Contrast Control Register + LCDFRR: 0xe6, // LCD Frame Rate Register + LCDCRB: 0xe5, // LCD Control and Status Register B + LCDCRA: 0xe4, // LCD Control and Status Register A + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK3 __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK3: 0x73, // Pin Change Mask Register 3 + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + PRR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + PRR: 0x64, // Power Reduction Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + } + + // Universal Serial Interface + USI = struct { + USIDR __reg + USISR __reg + USICR __reg + }{ + USIDR: 0xba, // USI Data Register + USISR: 0xb9, // USI Status Register + USICR: 0xb8, // USI Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 0 + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x6 // Brown-out Detector trigger level + EXTENDED_RSTDISBL = 0x1 // External Reset Disable + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM memory through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0A: Timer/Counter0 Control Register + TCCR0A_FOC0A = 0x80 // Force Output Compare + TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0A_COM0A = 0x30 // Compare Match Output Modes + TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0A_CS0 = 0x7 // Clock Selects + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0 + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2A: Timer/Counter2 Control Register + TCCR2A_FOC2A = 0x80 // Force Output Compare A + TCCR2A_WGM20 = 0x40 // Waveform Generation Mode + TCCR2A_COM2A = 0x30 // Compare Output Mode bits + TCCR2A_WGM21 = 0x8 // Waveform Generation Mode + TCCR2A_CS2 = 0x7 // Clock Select bits + + // TIMSK2: Timer/Counter2 Interrupt Mask register + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter2 Interrupt Flag Register + TIFR2_OCF2A = 0x2 // Timer/Counter2 Output Compare Flag 2 + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x10 // Enable External Clock Interrupt + ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for LCD: Liquid Crystal Display +const ( + // LCDCCR: LCD Contrast Control Register + LCDCCR_LCDDC = 0xe0 // LCD Display Configuration + LCDCCR_LCDCC = 0xf // LCD Contrast Control + + // LCDFRR: LCD Frame Rate Register + LCDFRR_LCDPS = 0x70 // LCD Prescaler Selects + LCDFRR_LCDCD = 0x7 // LCD Clock Dividers + + // LCDCRB: LCD Control and Status Register B + LCDCRB_LCDCS = 0x80 // LCD CLock Select + LCDCRB_LCD2B = 0x40 // LCD 1/2 Bias Select + LCDCRB_LCDMUX = 0x30 // LCD Mux Selects + LCDCRB_LCDPM = 0xf // LCD Port Masks + + // LCDCRA: LCD Control and Status Register A + LCDCRA_LCDEN = 0x80 // LCD Enable + LCDCRA_LCDAB = 0x40 // LCD A or B waveform + LCDCRA_LCDIF = 0x10 // LCD Interrupt Flag + LCDCRA_LCDIE = 0x8 // LCD Interrupt Enable + LCDCRA_LCDBL = 0x1 // LCD Blanking +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC01 = 0x2 // External Interrupt Sense Control 0 Bit 1 + EICRA_ISC00 = 0x1 // External Interrupt Sense Control 0 Bit 0 + + // EIMSK: External Interrupt Mask Register + EIMSK_PCIE = 0xf0 // Pin Change Interrupt Enables + EIMSK_INT0 = 0x1 // External Interrupt Request 0 Enable + + // EIFR: External Interrupt Flag Register + EIFR_PCIF = 0xf0 // Pin Change Interrupt Flags + EIFR_INTF0 = 0x1 // External Interrupt Flag 0 + + // PCMSK3: Pin Change Mask Register 3 + PCMSK3_PCINT = 0x7f // Pin Change Mask + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Mask + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Mask + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Mask +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // PRR: Power Reduction Register + PRR_PRLCD = 0x10 // Power Reduction LCD + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable +) + +// Bitfields for USI: Universal Serial Interface +const ( + // USISR: USI Status Register + USISR_USISIF = 0x80 // Start Condition Interrupt Flag + USISR_USIOIF = 0x40 // Counter Overflow Interrupt Flag + USISR_USIPF = 0x20 // Stop Condition Flag + USISR_USIDC = 0x10 // Data Output Collision + USISR_USICNT = 0xf // USI Counter Value Bits + + // USICR: USI Control Register + USICR_USISIE = 0x80 // Start Condition Interrupt Enable + USICR_USIOIE = 0x40 // Counter Overflow Interrupt Enable + USICR_USIWM = 0x30 // USI Wire Mode Bits + USICR_USICS = 0xc // USI Clock Source Select Bits + USICR_USICLK = 0x2 // Clock Strobe + USICR_USITC = 0x1 // Toggle Clock Port Pin +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmit Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data OverRun + UCSR0A_UPE0 = 0x4 // USART Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART Transmission Speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data Register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0x40 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) diff --git a/src/device/avr/atmega3290a.ld b/src/device/avr/atmega3290a.ld new file mode 100644 index 00000000..33cf88ac --- /dev/null +++ b/src/device/avr/atmega3290a.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega3290A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_size = 0x800; +__num_isrs = 25; diff --git a/src/device/avr/atmega3290p.go b/src/device/avr/atmega3290p.go new file mode 100644 index 00000000..7f7480a4 --- /dev/null +++ b/src/device/avr/atmega3290p.go @@ -0,0 +1,711 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega3290P.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega3290p + +// Device information for the ATmega3290P. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega3290P" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_PCINT0 = 2 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 3 // Pin Change Interrupt Request 1 + IRQ_TIMER2_COMP = 4 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 5 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 6 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 7 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 8 // Timer/Counter Compare Match B + IRQ_TIMER1_OVF = 9 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 10 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 11 // Timer/Counter0 Overflow + IRQ_SPI_STC = 12 // SPI Serial Transfer Complete + IRQ_USART_RX = 13 // USART, Rx Complete + IRQ_USART_UDRE = 14 // USART Data register Empty + IRQ_USART0_TX = 15 // USART0, Tx Complete + IRQ_USI_START = 16 // USI Start Condition + IRQ_USI_OVERFLOW = 17 // USI Overflow + IRQ_ANALOG_COMP = 18 // Analog Comparator + IRQ_ADC = 19 // ADC Conversion Complete + IRQ_EE_READY = 20 // EEPROM Ready + IRQ_SPM_READY = 21 // Store Program Memory Read + IRQ_LCD = 22 // LCD Start of Frame + IRQ_PCINT2 = 23 // Pin Change Interrupt Request 2 + IRQ_PCINT3 = 24 // Pin Change Interrupt Request 3 + IRQ_max = 24 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0A __reg + TCNT0 __reg + OCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR0A: 0x44, // Timer/Counter0 Control Register + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2A __reg + TCNT2 __reg + OCR2A __reg + TIMSK2 __reg + TIFR2 __reg + ASSR __reg + }{ + TCCR2A: 0xb0, // Timer/Counter2 Control Register + TCNT2: 0xb2, // Timer/Counter2 + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register + TIMSK2: 0x70, // Timer/Counter2 Interrupt Mask register + TIFR2: 0x37, // Timer/Counter2 Interrupt Flag Register + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x60, // Watchdog Timer Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access Bytes + EEARH: 0x41, // EEPROM Read/Write Access Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + PORTH __reg + DDRH __reg + PINH __reg + PORTJ __reg + DDRJ __reg + PINJ __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + PORTG: 0x34, // Port G Data Register + DDRG: 0x33, // Port G Data Direction Register + PING: 0x32, // Port G Input Pins + PORTH: 0xda, // PORT H Data Register + DDRH: 0xd9, // PORT H Data Direction Register + PINH: 0xd8, // PORT H Input Pins + PORTJ: 0xdd, // PORT J Data Register + DDRJ: 0xdc, // PORT J Data Direction Register + PINJ: 0xdb, // PORT J Input Pins + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // Liquid Crystal Display + LCD = struct { + LCDDR19 __reg + LCDDR18 __reg + LCDDR17 __reg + LCDDR16 __reg + LCDDR15 __reg + LCDDR14 __reg + LCDDR13 __reg + LCDDR12 __reg + LCDDR11 __reg + LCDDR10 __reg + LCDDR09 __reg + LCDDR08 __reg + LCDDR07 __reg + LCDDR06 __reg + LCDDR05 __reg + LCDDR04 __reg + LCDDR03 __reg + LCDDR02 __reg + LCDDR01 __reg + LCDDR00 __reg + LCDCCR __reg + LCDFRR __reg + LCDCRB __reg + LCDCRA __reg + }{ + LCDDR19: 0xff, // LCD Data Register 19 + LCDDR18: 0xfe, // LCD Data Register 18 + LCDDR17: 0xfd, // LCD Data Register 17 + LCDDR16: 0xfc, // LCD Data Register 16 + LCDDR15: 0xfb, // LCD Data Register 15 + LCDDR14: 0xfa, // LCD Data Register 14 + LCDDR13: 0xf9, // LCD Data Register 13 + LCDDR12: 0xf8, // LCD Data Register 12 + LCDDR11: 0xf7, // LCD Data Register 11 + LCDDR10: 0xf6, // LCD Data Register 10 + LCDDR09: 0xf5, // LCD Data Register 9 + LCDDR08: 0xf4, // LCD Data Register 8 + LCDDR07: 0xf3, // LCD Data Register 7 + LCDDR06: 0xf2, // LCD Data Register 6 + LCDDR05: 0xf1, // LCD Data Register 5 + LCDDR04: 0xf0, // LCD Data Register 4 + LCDDR03: 0xef, // LCD Data Register 3 + LCDDR02: 0xee, // LCD Data Register 2 + LCDDR01: 0xed, // LCD Data Register 1 + LCDDR00: 0xec, // LCD Data Register 0 + LCDCCR: 0xe7, // LCD Contrast Control Register + LCDFRR: 0xe6, // LCD Frame Rate Register + LCDCRB: 0xe5, // LCD Control and Status Register B + LCDCRA: 0xe4, // LCD Control and Status Register A + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK3 __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK3: 0x73, // Pin Change Mask Register 3 + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + PRR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + PRR: 0x64, // Power Reduction Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + } + + // Universal Serial Interface + USI = struct { + USIDR __reg + USISR __reg + USICR __reg + }{ + USIDR: 0xba, // USI Data Register + USISR: 0xb9, // USI Status Register + USICR: 0xb8, // USI Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 0 + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x6 // Brown-out Detector trigger level + EXTENDED_RSTDISBL = 0x1 // External Reset Disable + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM memory through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0A: Timer/Counter0 Control Register + TCCR0A_FOC0A = 0x80 // Force Output Compare + TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0A_COM0A = 0x30 // Compare Match Output Modes + TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0A_CS0 = 0x7 // Clock Selects + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0 + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2A: Timer/Counter2 Control Register + TCCR2A_FOC2A = 0x80 // Force Output Compare A + TCCR2A_WGM20 = 0x40 // Waveform Generation Mode + TCCR2A_COM2A = 0x30 // Compare Output Mode bits + TCCR2A_WGM21 = 0x8 // Waveform Generation Mode + TCCR2A_CS2 = 0x7 // Clock Select bits + + // TIMSK2: Timer/Counter2 Interrupt Mask register + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter2 Interrupt Flag Register + TIFR2_OCF2A = 0x2 // Timer/Counter2 Output Compare Flag 2 + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x10 // Enable External Clock Interrupt + ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for LCD: Liquid Crystal Display +const ( + // LCDCCR: LCD Contrast Control Register + LCDCCR_LCDDC = 0xe0 // LCD Display Configurations + LCDCCR_LCDMDT = 0x10 // LCD Maximum Drive Time + LCDCCR_LCDCC = 0xf // LCD Contrast Control + + // LCDFRR: LCD Frame Rate Register + LCDFRR_LCDPS = 0x70 // LCD Prescaler Selects + LCDFRR_LCDCD = 0x7 // LCD Clock Dividers + + // LCDCRB: LCD Control and Status Register B + LCDCRB_LCDCS = 0x80 // LCD CLock Select + LCDCRB_LCD2B = 0x40 // LCD 1/2 Bias Select + LCDCRB_LCDMUX = 0x30 // LCD Mux Selects + LCDCRB_LCDPM = 0xf // LCD Port Masks + + // LCDCRA: LCD Control and Status Register A + LCDCRA_LCDEN = 0x80 // LCD Enable + LCDCRA_LCDAB = 0x40 // LCD A or B waveform + LCDCRA_LCDIF = 0x10 // LCD Interrupt Flag + LCDCRA_LCDIE = 0x8 // LCD Interrupt Enable + LCDCRA_LCDBD = 0x4 // LCD Buffer Disable + LCDCRA_LCDCCD = 0x2 // LCD Contrast Control Disable + LCDCRA_LCDBL = 0x1 // LCD Blanking +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC01 = 0x2 // External Interrupt Sense Control 0 Bit 1 + EICRA_ISC00 = 0x1 // External Interrupt Sense Control 0 Bit 0 + + // EIMSK: External Interrupt Mask Register + EIMSK_PCIE = 0xf0 // Pin Change Interrupt Enables + EIMSK_INT0 = 0x1 // External Interrupt Request 0 Enable + + // EIFR: External Interrupt Flag Register + EIFR_PCIF = 0xf0 // Pin Change Interrupt Flags + EIFR_INTF0 = 0x1 // External Interrupt Flag 0 + + // PCMSK3: Pin Change Mask Register 3 + PCMSK3_PCINT = 0x7f // Pin Change Mask + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Mask + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Mask + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Mask +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // PRR: Power Reduction Register + PRR_PRLCD = 0x10 // Power Reduction LCD + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable +) + +// Bitfields for USI: Universal Serial Interface +const ( + // USISR: USI Status Register + USISR_USISIF = 0x80 // Start Condition Interrupt Flag + USISR_USIOIF = 0x40 // Counter Overflow Interrupt Flag + USISR_USIPF = 0x20 // Stop Condition Flag + USISR_USIDC = 0x10 // Data Output Collision + USISR_USICNT = 0xf // USI Counter Value Bits + + // USICR: USI Control Register + USICR_USISIE = 0x80 // Start Condition Interrupt Enable + USICR_USIOIE = 0x40 // Counter Overflow Interrupt Enable + USICR_USIWM = 0x30 // USI Wire Mode Bits + USICR_USICS = 0xc // USI Clock Source Select Bits + USICR_USICLK = 0x2 // Clock Strobe + USICR_USITC = 0x1 // Toggle Clock Port Pin +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmit Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data OverRun + UCSR0A_UPE0 = 0x4 // USART Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART Transmission Speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data Register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0x40 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) diff --git a/src/device/avr/atmega3290p.ld b/src/device/avr/atmega3290p.ld new file mode 100644 index 00000000..fb062d25 --- /dev/null +++ b/src/device/avr/atmega3290p.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega3290P.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_size = 0x800; +__num_isrs = 25; diff --git a/src/device/avr/atmega3290pa.go b/src/device/avr/atmega3290pa.go new file mode 100644 index 00000000..510ba9fd --- /dev/null +++ b/src/device/avr/atmega3290pa.go @@ -0,0 +1,699 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega3290PA.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega3290pa + +// Device information for the ATmega3290PA. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega3290PA" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_PCINT0 = 2 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 3 // Pin Change Interrupt Request 1 + IRQ_TIMER2_COMP = 4 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 5 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 6 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 7 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 8 // Timer/Counter Compare Match B + IRQ_TIMER1_OVF = 9 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 10 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 11 // Timer/Counter0 Overflow + IRQ_SPI_STC = 12 // SPI Serial Transfer Complete + IRQ_USART_RX = 13 // USART, Rx Complete + IRQ_USART_UDRE = 14 // USART Data register Empty + IRQ_USART0_TX = 15 // USART0, Tx Complete + IRQ_USI_START = 16 // USI Start Condition + IRQ_USI_OVERFLOW = 17 // USI Overflow + IRQ_ANALOG_COMP = 18 // Analog Comparator + IRQ_ADC = 19 // ADC Conversion Complete + IRQ_EE_READY = 20 // EEPROM Ready + IRQ_SPM_READY = 21 // Store Program Memory Read + IRQ_LCD = 22 // LCD Start of Frame + IRQ_PCINT2 = 23 // Pin Change Interrupt Request 2 + IRQ_PCINT3 = 24 // Pin Change Interrupt Request 3 + IRQ_max = 24 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0A __reg + TCNT0 __reg + OCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR0A: 0x44, // Timer/Counter0 Control Register + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2A __reg + TCNT2 __reg + OCR2A __reg + TIMSK2 __reg + TIFR2 __reg + ASSR __reg + }{ + TCCR2A: 0xb0, // Timer/Counter2 Control Register + TCNT2: 0xb2, // Timer/Counter2 + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register + TIMSK2: 0x70, // Timer/Counter2 Interrupt Mask register + TIFR2: 0x37, // Timer/Counter2 Interrupt Flag Register + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x60, // Watchdog Timer Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access Bytes + EEARH: 0x41, // EEPROM Read/Write Access Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + PORTH __reg + DDRH __reg + PINH __reg + PORTJ __reg + DDRJ __reg + PINJ __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + PORTG: 0x34, // Port G Data Register + DDRG: 0x33, // Port G Data Direction Register + PING: 0x32, // Port G Input Pins + PORTH: 0xda, // PORT H Data Register + DDRH: 0xd9, // PORT H Data Direction Register + PINH: 0xd8, // PORT H Input Pins + PORTJ: 0xdd, // PORT J Data Register + DDRJ: 0xdc, // PORT J Data Direction Register + PINJ: 0xdb, // PORT J Input Pins + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK3 __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK3: 0x73, // Pin Change Mask Register 3 + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + } + + // Universal Serial Interface + USI = struct { + USIDR __reg + USISR __reg + USICR __reg + }{ + USIDR: 0xba, // USI Data Register + USISR: 0xb9, // USI Status Register + USICR: 0xb8, // USI Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 0 + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } + + // Liquid Crystal Display + LCD = struct { + LCDDR19 __reg + LCDDR18 __reg + LCDDR17 __reg + LCDDR16 __reg + LCDDR15 __reg + LCDDR14 __reg + LCDDR13 __reg + LCDDR12 __reg + LCDDR11 __reg + LCDDR10 __reg + LCDDR9 __reg + LCDDR8 __reg + LCDDR7 __reg + LCDDR6 __reg + LCDDR5 __reg + LCDDR4 __reg + LCDDR3 __reg + LCDDR2 __reg + LCDDR1 __reg + LCDDR0 __reg + LCDCCR __reg + LCDFRR __reg + LCDCRB __reg + LCDCRA __reg + }{ + LCDDR19: 0xff, // LCD Data Register 19 + LCDDR18: 0xfe, // LCD Data Register 18 + LCDDR17: 0xfd, // LCD Data Register 17 + LCDDR16: 0xfc, // LCD Data Register 16 + LCDDR15: 0xfb, // LCD Data Register 15 + LCDDR14: 0xfa, // LCD Data Register 14 + LCDDR13: 0xf9, // LCD Data Register 13 + LCDDR12: 0xf8, // LCD Data Register 12 + LCDDR11: 0xf7, // LCD Data Register 11 + LCDDR10: 0xf6, // LCD Data Register 10 + LCDDR9: 0xf5, // LCD Data Register 9 + LCDDR8: 0xf4, // LCD Data Register 8 + LCDDR7: 0xf3, // LCD Data Register 7 + LCDDR6: 0xf2, // LCD Data Register 6 + LCDDR5: 0xf1, // LCD Data Register 5 + LCDDR4: 0xf0, // LCD Data Register 4 + LCDDR3: 0xef, // LCD Data Register 3 + LCDDR2: 0xee, // LCD Data Register 2 + LCDDR1: 0xed, // LCD Data Register 1 + LCDDR0: 0xec, // LCD Data Register 0 + LCDCCR: 0xe7, // LCD Contrast Control Register + LCDFRR: 0xe6, // LCD Frame Rate Register + LCDCRB: 0xe5, // LCD Control and Status Register B + LCDCRA: 0xe4, // LCD Control and Status Register A + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + PRR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + PRR: 0x64, // Power Reduction Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x6 // Brown-out Detector trigger level + EXTENDED_RSTDISBL = 0x1 // External Reset Disable + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM memory through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0A: Timer/Counter0 Control Register + TCCR0A_FOC0A = 0x80 // Force Output Compare + TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0A_COM0A = 0x30 // Compare Match Output Modes + TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0A_CS0 = 0x7 // Clock Selects + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0 + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2A: Timer/Counter2 Control Register + TCCR2A_FOC2A = 0x80 // Force Output Compare A + TCCR2A_WGM20 = 0x40 // Waveform Generation Mode + TCCR2A_COM2A = 0x30 // Compare Output Mode bits + TCCR2A_WGM21 = 0x8 // Waveform Generation Mode + TCCR2A_CS2 = 0x7 // Clock Select bits + + // TIMSK2: Timer/Counter2 Interrupt Mask register + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter2 Interrupt Flag Register + TIFR2_OCF2A = 0x2 // Timer/Counter2 Output Compare Flag 2 + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x10 // Enable External Clock Interrupt + ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC01 = 0x2 // External Interrupt Sense Control 0 Bit 1 + EICRA_ISC00 = 0x1 // External Interrupt Sense Control 0 Bit 0 + + // EIMSK: External Interrupt Mask Register + EIMSK_PCIE = 0xf0 // Pin Change Interrupt Enables + EIMSK_INT0 = 0x1 // External Interrupt Request 0 Enable + + // EIFR: External Interrupt Flag Register + EIFR_PCIF = 0xf0 // Pin Change Interrupt Flags + EIFR_INTF0 = 0x1 // External Interrupt Flag 0 +) + +// Bitfields for USI: Universal Serial Interface +const ( + // USISR: USI Status Register + USISR_USISIF = 0x80 // Start Condition Interrupt Flag + USISR_USIOIF = 0x40 // Counter Overflow Interrupt Flag + USISR_USIPF = 0x20 // Stop Condition Flag + USISR_USIDC = 0x10 // Data Output Collision + USISR_USICNT = 0xf // USI Counter Value Bits + + // USICR: USI Control Register + USICR_USISIE = 0x80 // Start Condition Interrupt Enable + USICR_USIOIE = 0x40 // Counter Overflow Interrupt Enable + USICR_USIWM = 0x30 // USI Wire Mode Bits + USICR_USICS = 0xc // USI Clock Source Select Bits + USICR_USICLK = 0x2 // Clock Strobe + USICR_USITC = 0x1 // Toggle Clock Port Pin +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmit Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data OverRun + UCSR0A_UPE0 = 0x4 // USART Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART Transmission Speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data Register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0x40 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) + +// Bitfields for LCD: Liquid Crystal Display +const ( + // LCDCCR: LCD Contrast Control Register + LCDCCR_LCDDC = 0xe0 // LCD Display Configurations + LCDCCR_LCDMDT = 0x10 // LCD Maximum Drive Time + LCDCCR_LCDCC = 0xf // LCD Contrast Controls + + // LCDFRR: LCD Frame Rate Register + LCDFRR_LCDPS = 0x70 // LCD Prescaler Selects + LCDFRR_LCDCD = 0x7 // LCD Clock Dividers + + // LCDCRB: LCD Control and Status Register B + LCDCRB_LCDCS = 0x80 // LCD CLock Select + LCDCRB_LCD2B = 0x40 // LCD 1/2 Bias Select + LCDCRB_LCDMUX = 0x30 // LCD Mux Selects + LCDCRB_LCDPM = 0xf // LCD Port Masks + + // LCDCRA: LCD Control and Status Register A + LCDCRA_LCDEN = 0x80 // LCD Enable + LCDCRA_LCDAB = 0x40 // LCD A or B waveform + LCDCRA_LCDIF = 0x10 // LCD Interrupt Flag + LCDCRA_LCDIE = 0x8 // LCD Interrupt Enable + LCDCRA_LCDBD = 0x4 // LCD Buffer Disable + LCDCRA_LCDCCD = 0x2 // LCD Contrast Control Disable + LCDCRA_LCDBL = 0x1 // LCD Blanking +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // PRR: Power Reduction Register + PRR_PRLCD = 0x10 // Power Reduction LCD + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable +) diff --git a/src/device/avr/atmega3290pa.ld b/src/device/avr/atmega3290pa.ld new file mode 100644 index 00000000..4d7a104f --- /dev/null +++ b/src/device/avr/atmega3290pa.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega3290PA.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_size = 0x800; +__num_isrs = 25; diff --git a/src/device/avr/atmega329a.go b/src/device/avr/atmega329a.go new file mode 100644 index 00000000..7687e8e4 --- /dev/null +++ b/src/device/avr/atmega329a.go @@ -0,0 +1,839 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega329A.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega329a + +// Device information for the ATmega329A. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega329A" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_PCINT0 = 2 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 3 // Pin Change Interrupt Request 1 + IRQ_TIMER2_COMP = 4 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 5 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 6 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 7 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 8 // Timer/Counter Compare Match B + IRQ_TIMER1_OVF = 9 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 10 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 11 // Timer/Counter0 Overflow + IRQ_SPI_STC = 12 // SPI Serial Transfer Complete + IRQ_USART0_RX = 13 // USART0, Rx Complete + IRQ_USART0_UDRE = 14 // USART0 Data register Empty + IRQ_USART0_TX = 15 // USART0, Tx Complete + IRQ_USI_START = 16 // USI Start Condition + IRQ_USI_OVERFLOW = 17 // USI Overflow + IRQ_ANALOG_COMP = 18 // Analog Comparator + IRQ_ADC = 19 // ADC Conversion Complete + IRQ_EE_READY = 20 // EEPROM Ready + IRQ_SPM_READY = 21 // Store Program Memory Read + IRQ_LCD = 22 // LCD Start of Frame + IRQ_max = 22 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0A __reg + TCNT0 __reg + OCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR0A: 0x44, // Timer/Counter0 Control Register + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2A __reg + TCNT2 __reg + OCR2A __reg + TIMSK2 __reg + TIFR2 __reg + ASSR __reg + }{ + TCCR2A: 0xb0, // Timer/Counter2 Control Register + TCNT2: 0xb2, // Timer/Counter2 + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register + TIMSK2: 0x70, // Timer/Counter2 Interrupt Mask register + TIFR2: 0x37, // Timer/Counter2 Interrupt Flag Register + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x60, // Watchdog Timer Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access Bytes + EEARH: 0x41, // EEPROM Read/Write Access Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + PORTG: 0x34, // Port G Data Register + DDRG: 0x33, // Port G Data Direction Register + PING: 0x32, // Port G Input Pins + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // Liquid Crystal Display + LCD = struct { + LCDDR18 __reg + LCDDR17 __reg + LCDDR16 __reg + LCDDR15 __reg + LCDDR13 __reg + LCDDR12 __reg + LCDDR11 __reg + LCDDR10 __reg + LCDDR08 __reg + LCDDR07 __reg + LCDDR06 __reg + LCDDR05 __reg + LCDDR03 __reg + LCDDR02 __reg + LCDDR01 __reg + LCDDR00 __reg + LCDCCR __reg + LCDFRR __reg + LCDCRB __reg + LCDCRA __reg + }{ + LCDDR18: 0xfe, // LCD Data Register 18 + LCDDR17: 0xfd, // LCD Data Register 17 + LCDDR16: 0xfc, // LCD Data Register 16 + LCDDR15: 0xfb, // LCD Data Register 15 + LCDDR13: 0xf9, // LCD Data Register 13 + LCDDR12: 0xf8, // LCD Data Register 12 + LCDDR11: 0xf7, // LCD Data Register 11 + LCDDR10: 0xf6, // LCD Data Register 10 + LCDDR08: 0xf4, // LCD Data Register 8 + LCDDR07: 0xf3, // LCD Data Register 7 + LCDDR06: 0xf2, // LCD Data Register 6 + LCDDR05: 0xf1, // LCD Data Register 5 + LCDDR03: 0xef, // LCD Data Register 3 + LCDDR02: 0xee, // LCD Data Register 2 + LCDDR01: 0xed, // LCD Data Register 1 + LCDDR00: 0xec, // LCD Data Register 0 + LCDCCR: 0xe7, // LCD Contrast Control Register + LCDFRR: 0xe6, // LCD Frame Rate Register + LCDCRB: 0xe5, // LCD Control and Status Register B + LCDCRA: 0xe4, // LCD Control Register A + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK1 __reg + PCMSK0 __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + PRR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + PRR: 0x64, // Power Reduction Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + } + + // Universal Serial Interface + USI = struct { + USIDR __reg + USISR __reg + USICR __reg + }{ + USIDR: 0xba, // USI Data Register + USISR: 0xb9, // USI Status Register + USICR: 0xb8, // USI Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 0 + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x6 // Brown-out Detector trigger level + EXTENDED_RSTDISBL = 0x1 // External Reset Disable + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM memory through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0A: Timer/Counter0 Control Register + TCCR0A_FOC0A = 0x80 // Force Output Compare + TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0A_COM0A = 0x30 // Compare Match Output Modes + TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0A_CS0 = 0x7 // Clock Selects + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0 + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2A: Timer/Counter2 Control Register + TCCR2A_FOC2A = 0x80 // Force Output Compare A + TCCR2A_WGM20 = 0x40 // Waveform Generation Mode + TCCR2A_COM2A = 0x30 // Compare Output Mode bits + TCCR2A_WGM21 = 0x8 // Waveform Generation Mode + TCCR2A_CS2 = 0x7 // Clock Select bits + + // TIMSK2: Timer/Counter2 Interrupt Mask register + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter2 Interrupt Flag Register + TIFR2_OCF2A = 0x2 // Timer/Counter2 Output Compare Flag 2 + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x10 // Enable External Clock Interrupt + ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for LCD: Liquid Crystal Display +const ( + // LCDDR18: LCD Data Register 18 + LCDDR18_SEG324 = 0x1 // LCD memory bit segment + LCDDR18_SEG325 = 0x2 // LCD memory bit segment + LCDDR18_SEG326 = 0x4 // LCD memory bit segment + LCDDR18_SEG327 = 0x8 // LCD memory bit segment + LCDDR18_SEG328 = 0x10 // LCD memory bit segment + LCDDR18_SEG329 = 0x20 // LCD memory bit segment + LCDDR18_SEG330 = 0x40 // LCD memory bit segment + LCDDR18_SEG331 = 0x80 // LCD memory bit segment + + // LCDDR17: LCD Data Register 17 + LCDDR17_SEG316 = 0x1 // LCD memory bit segment + LCDDR17_SEG317 = 0x2 // LCD memory bit segment + LCDDR17_SEG318 = 0x4 // LCD memory bit segment + LCDDR17_SEG319 = 0x8 // LCD memory bit segment + LCDDR17_SEG320 = 0x10 // LCD memory bit segment + LCDDR17_SEG321 = 0x20 // LCD memory bit segment + LCDDR17_SEG322 = 0x40 // LCD memory bit segment + LCDDR17_SEG323 = 0x80 // LCD memory bit segment + + // LCDDR16: LCD Data Register 16 + LCDDR16_SEG308 = 0x1 // LCD memory bit segment + LCDDR16_SEG309 = 0x2 // LCD memory bit segment + LCDDR16_SEG310 = 0x4 // LCD memory bit segment + LCDDR16_SEG311 = 0x8 // LCD memory bit segment + LCDDR16_SEG312 = 0x10 // LCD memory bit segment + LCDDR16_SEG313 = 0x20 // LCD memory bit segment + LCDDR16_SEG314 = 0x40 // LCD memory bit segment + LCDDR16_SEG315 = 0x80 // LCD memory bit segment + + // LCDDR15: LCD Data Register 15 + LCDDR15_SEG300 = 0x1 // LCD memory bit segment + LCDDR15_SEG301 = 0x2 // LCD memory bit segment + LCDDR15_SEG302 = 0x4 // LCD memory bit segment + LCDDR15_SEG303 = 0x8 // LCD memory bit segment + LCDDR15_SEG304 = 0x10 // LCD memory bit segment + LCDDR15_SEG305 = 0x20 // LCD memory bit segment + LCDDR15_SEG306 = 0x40 // LCD memory bit segment + LCDDR15_SEG307 = 0x80 // LCD memory bit segment + + // LCDDR13: LCD Data Register 13 + LCDDR13_SEG224 = 0x1 // LCD memory bit segment + LCDDR13_SEG225 = 0x2 // LCD memory bit segment + LCDDR13_SEG226 = 0x4 // LCD memory bit segment + LCDDR13_SEG227 = 0x8 // LCD memory bit segment + LCDDR13_SEG228 = 0x10 // LCD memory bit segment + LCDDR13_SEG229 = 0x20 // LCD memory bit segment + LCDDR13_SEG230 = 0x40 // LCD memory bit segment + LCDDR13_SEG231 = 0x80 // LCD memory bit segment + + // LCDDR12: LCD Data Register 12 + LCDDR12_SEG216 = 0x1 // LCD memory bit segment + LCDDR12_SEG217 = 0x2 // LCD memory bit segment + LCDDR12_SEG218 = 0x4 // LCD memory bit segment + LCDDR12_SEG219 = 0x8 // LCD memory bit segment + LCDDR12_SEG220 = 0x10 // LCD memory bit segment + LCDDR12_SEG221 = 0x20 // LCD memory bit segment + LCDDR12_SEG222 = 0x40 // LCD memory bit segment + LCDDR12_SEG223 = 0x80 // LCD memory bit segment + + // LCDDR11: LCD Data Register 11 + LCDDR11_SEG208 = 0x1 // LCD memory bit segment + LCDDR11_SEG209 = 0x2 // LCD memory bit segment + LCDDR11_SEG210 = 0x4 // LCD memory bit segment + LCDDR11_SEG211 = 0x8 // LCD memory bit segment + LCDDR11_SEG212 = 0x10 // LCD memory bit segment + LCDDR11_SEG213 = 0x20 // LCD memory bit segment + LCDDR11_SEG214 = 0x40 // LCD memory bit segment + LCDDR11_SEG215 = 0x80 // LCD memory bit segment + + // LCDDR10: LCD Data Register 10 + LCDDR10_SEG200 = 0x1 // LCD memory bit segment + LCDDR10_SEG201 = 0x2 // LCD memory bit segment + LCDDR10_SEG202 = 0x4 // LCD memory bit segment + LCDDR10_SEG203 = 0x8 // LCD memory bit segment + LCDDR10_SEG204 = 0x10 // LCD memory bit segment + LCDDR10_SEG205 = 0x20 // LCD memory bit segment + LCDDR10_SEG206 = 0x40 // LCD memory bit segment + LCDDR10_SEG207 = 0x80 // LCD memory bit segment + + // LCDDR08: LCD Data Register 8 + LCDDR08_SEG124 = 0x1 // LCD memory bit segment + LCDDR08_SEG125 = 0x2 // LCD memory bit segment + LCDDR08_SEG126 = 0x4 // LCD memory bit segment + LCDDR08_SEG127 = 0x8 // LCD memory bit segment + LCDDR08_SEG128 = 0x10 // LCD memory bit segment + LCDDR08_SEG129 = 0x20 // LCD memory bit segment + LCDDR08_SEG130 = 0x40 // LCD memory bit segment + LCDDR08_SEG131 = 0x80 // LCD memory bit segment + + // LCDDR07: LCD Data Register 7 + LCDDR07_SEG116 = 0x1 // LCD memory bit segment + LCDDR07_SEG117 = 0x2 // LCD memory bit segment + LCDDR07_SEG118 = 0x4 // LCD memory bit segment + LCDDR07_SEG119 = 0x8 // LCD memory bit segment + LCDDR07_SEG120 = 0x10 // LCD memory bit segment + LCDDR07_SEG121 = 0x20 // LCD memory bit segment + LCDDR07_SEG122 = 0x40 // LCD memory bit segment + LCDDR07_SEG123 = 0x80 // LCD memory bit segment + + // LCDDR06: LCD Data Register 6 + LCDDR06_SEG108 = 0x1 // LCD memory bit segment + LCDDR06_SEG109 = 0x2 // LCD memory bit segment + LCDDR06_SEG110 = 0x4 // LCD memory bit segment + LCDDR06_SEG111 = 0x8 // LCD memory bit segment + LCDDR06_SEG112 = 0x10 // LCD memory bit segment + LCDDR06_SEG113 = 0x20 // LCD memory bit segment + LCDDR06_SEG114 = 0x40 // LCD memory bit segment + LCDDR06_SEG115 = 0x80 // LCD memory bit segment + + // LCDDR05: LCD Data Register 5 + LCDDR05_SEG100 = 0x1 // LCD memory bit segment + LCDDR05_SEG101 = 0x2 // LCD memory bit segment + LCDDR05_SEG102 = 0x4 // LCD memory bit segment + LCDDR05_SEG103 = 0x8 // LCD memory bit segment + LCDDR05_SEG104 = 0x10 // LCD memory bit segment + LCDDR05_SEG105 = 0x20 // LCD memory bit segment + LCDDR05_SEG106 = 0x40 // LCD memory bit segment + LCDDR05_SEG107 = 0x80 // LCD memory bit segment + + // LCDDR03: LCD Data Register 3 + LCDDR03_SEG024 = 0x1 // LCD memory bit segment + LCDDR03_SEG025 = 0x2 // LCD memory bit segment + LCDDR03_SEG026 = 0x4 // LCD memory bit segment + LCDDR03_SEG027 = 0x8 // LCD memory bit segment + LCDDR03_SEG028 = 0x10 // LCD memory bit segment + LCDDR03_SEG029 = 0x20 // LCD memory bit segment + LCDDR03_SEG030 = 0x40 // LCD memory bit segment + LCDDR03_SEG031 = 0x80 // LCD memory bit segment + + // LCDDR02: LCD Data Register 2 + LCDDR02_SEG016 = 0x1 // LCD memory bit segment + LCDDR02_SEG017 = 0x2 // LCD memory bit segment + LCDDR02_SEG018 = 0x4 // LCD memory bit segment + LCDDR02_SEG019 = 0x8 // LCD memory bit segment + LCDDR02_SEG020 = 0x10 // LCD memory bit segment + LCDDR02_SEG021 = 0x20 // LCD memory bit segment + LCDDR02_SEG022 = 0x40 // LCD memory bit segment + LCDDR02_SEG023 = 0x80 // LCD memory bit segment + + // LCDDR01: LCD Data Register 1 + LCDDR01_SEG008 = 0x1 // LCD memory bit segment + LCDDR01_SEG009 = 0x2 // LCD memory bit segment + LCDDR01_SEG010 = 0x4 // LCD memory bit segment + LCDDR01_SEG011 = 0x8 // LCD memory bit segment + LCDDR01_SEG012 = 0x10 // LCD memory bit segment + LCDDR01_SEG013 = 0x20 // LCD memory bit segment + LCDDR01_SEG014 = 0x40 // LCD memory bit segment + LCDDR01_SEG015 = 0x80 // LCD memory bit segment + + // LCDDR00: LCD Data Register 0 + LCDDR00_SEG000 = 0x1 // LCD memory bit segment + LCDDR00_SEG001 = 0x2 // LCD memory bit segment + LCDDR00_SEG002 = 0x4 // LCD memory bit segment + LCDDR00_SEG003 = 0x8 // LCD memory bit segment + LCDDR00_SEG004 = 0x10 // LCD memory bit segment + LCDDR00_SEG005 = 0x20 // LCD memory bit segment + LCDDR00_SEG006 = 0x40 // LCD memory bit segment + LCDDR00_SEG007 = 0x80 // LCD memory bit segment + + // LCDCCR: LCD Contrast Control Register + LCDCCR_LCDDC = 0xe0 // LCD Display Configuration + LCDCCR_LCDMDT = 0x10 // LCD Maximum Drive Time + LCDCCR_LCDCC = 0xf // LCD Contrast Controls + + // LCDFRR: LCD Frame Rate Register + LCDFRR_LCDPS = 0x70 // LCD Prescaler Selects + LCDFRR_LCDCD = 0x7 // LCD Clock Dividers + + // LCDCRB: LCD Control and Status Register B + LCDCRB_LCDCS = 0x80 // LCD CLock Select + LCDCRB_LCD2B = 0x40 // LCD 1/2 Bias Select + LCDCRB_LCDMUX = 0x30 // LCD Mux Selects + LCDCRB_LCDPM = 0xf // LCD Port Masks + + // LCDCRA: LCD Control Register A + LCDCRA_LCDEN = 0x80 // LCD Enable + LCDCRA_LCDAB = 0x40 // LCD A or B waveform + LCDCRA_LCDIF = 0x10 // LCD Interrupt Flag + LCDCRA_LCDIE = 0x8 // LCD Interrupt Enable + LCDCRA_LCDBD = 0x4 // LCD Buffer Disable + LCDCRA_LCDCCD = 0x2 // LCD Contrast Control Disable + LCDCRA_LCDBL = 0x1 // LCD Blanking +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC01 = 0x2 // External Interrupt Sense Control 0 Bit 1 + EICRA_ISC00 = 0x1 // External Interrupt Sense Control 0 Bit 0 + + // EIMSK: External Interrupt Mask Register + EIMSK_PCIE = 0xf0 // Pin Change Interrupt Enables + EIMSK_INT0 = 0x1 // External Interrupt Request 0 Enable + + // EIFR: External Interrupt Flag Register + EIFR_PCIF = 0xf0 // Pin Change Interrupt Flags + EIFR_INTF0 = 0x1 // External Interrupt Flag 0 + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Mask + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Mask +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // PRR: Power Reduction Register + PRR_PRLCD = 0x10 // Power Reduction LCD + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable +) + +// Bitfields for USI: Universal Serial Interface +const ( + // USISR: USI Status Register + USISR_USISIF = 0x80 // Start Condition Interrupt Flag + USISR_USIOIF = 0x40 // Counter Overflow Interrupt Flag + USISR_USIPF = 0x20 // Stop Condition Flag + USISR_USIDC = 0x10 // Data Output Collision + USISR_USICNT = 0xf // USI Counter Value Bits + + // USICR: USI Control Register + USICR_USISIE = 0x80 // Start Condition Interrupt Enable + USICR_USIOIE = 0x40 // Counter Overflow Interrupt Enable + USICR_USIWM = 0x30 // USI Wire Mode Bits + USICR_USICS = 0xc // USI Clock Source Select Bits + USICR_USICLK = 0x2 // Clock Strobe + USICR_USITC = 0x1 // Toggle Clock Port Pin +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmit Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data OverRun + UCSR0A_UPE0 = 0x4 // USART Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART Transmission Speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data Register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0x40 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) diff --git a/src/device/avr/atmega329a.ld b/src/device/avr/atmega329a.ld new file mode 100644 index 00000000..99be0868 --- /dev/null +++ b/src/device/avr/atmega329a.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega329A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_size = 0x800; +__num_isrs = 23; diff --git a/src/device/avr/atmega329p.go b/src/device/avr/atmega329p.go new file mode 100644 index 00000000..f166f264 --- /dev/null +++ b/src/device/avr/atmega329p.go @@ -0,0 +1,853 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega329P.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega329p + +// Device information for the ATmega329P. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega329P" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_PCINT0 = 2 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 3 // Pin Change Interrupt Request 1 + IRQ_TIMER2_COMP = 4 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 5 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 6 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 7 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 8 // Timer/Counter Compare Match B + IRQ_TIMER1_OVF = 9 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 10 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 11 // Timer/Counter0 Overflow + IRQ_SPI_STC = 12 // SPI Serial Transfer Complete + IRQ_USART0_RX = 13 // USART0, Rx Complete + IRQ_USART0_UDRE = 14 // USART0 Data register Empty + IRQ_USART0_TX = 15 // USART0, Tx Complete + IRQ_USI_START = 16 // USI Start Condition + IRQ_USI_OVERFLOW = 17 // USI Overflow + IRQ_ANALOG_COMP = 18 // Analog Comparator + IRQ_ADC = 19 // ADC Conversion Complete + IRQ_EE_READY = 20 // EEPROM Ready + IRQ_SPM_READY = 21 // Store Program Memory Read + IRQ_LCD = 22 // LCD Start of Frame + IRQ_max = 22 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0A __reg + TCNT0 __reg + OCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR0A: 0x44, // Timer/Counter0 Control Register + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2A __reg + TCNT2 __reg + OCR2A __reg + TIMSK2 __reg + TIFR2 __reg + ASSR __reg + }{ + TCCR2A: 0xb0, // Timer/Counter2 Control Register + TCNT2: 0xb2, // Timer/Counter2 + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register + TIMSK2: 0x70, // Timer/Counter2 Interrupt Mask register + TIFR2: 0x37, // Timer/Counter2 Interrupt Flag Register + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x60, // Watchdog Timer Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access Bytes + EEARH: 0x41, // EEPROM Read/Write Access Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + PORTG: 0x34, // Port G Data Register + DDRG: 0x33, // Port G Data Direction Register + PING: 0x32, // Port G Input Pins + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK1 __reg + PCMSK0 __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + } + + // Universal Serial Interface + USI = struct { + USIDR __reg + USISR __reg + USICR __reg + }{ + USIDR: 0xba, // USI Data Register + USISR: 0xb9, // USI Status Register + USICR: 0xb8, // USI Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 0 + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } + + // Liquid Crystal Display + LCD = struct { + LCDDR18 __reg + LCDDR17 __reg + LCDDR16 __reg + LCDDR15 __reg + LCDDR13 __reg + LCDDR12 __reg + LCDDR11 __reg + LCDDR10 __reg + LCDDR8 __reg + LCDDR7 __reg + LCDDR6 __reg + LCDDR5 __reg + LCDDR3 __reg + LCDDR2 __reg + LCDDR1 __reg + LCDDR0 __reg + LCDCCR __reg + LCDFRR __reg + LCDCRB __reg + LCDCRA __reg + }{ + LCDDR18: 0xfe, // LCD Data Register 18 + LCDDR17: 0xfd, // LCD Data Register 17 + LCDDR16: 0xfc, // LCD Data Register 16 + LCDDR15: 0xfb, // LCD Data Register 15 + LCDDR13: 0xf9, // LCD Data Register 13 + LCDDR12: 0xf8, // LCD Data Register 12 + LCDDR11: 0xf7, // LCD Data Register 11 + LCDDR10: 0xf6, // LCD Data Register 10 + LCDDR8: 0xf4, // LCD Data Register 8 + LCDDR7: 0xf3, // LCD Data Register 7 + LCDDR6: 0xf2, // LCD Data Register 6 + LCDDR5: 0xf1, // LCD Data Register 5 + LCDDR3: 0xef, // LCD Data Register 3 + LCDDR2: 0xee, // LCD Data Register 2 + LCDDR1: 0xed, // LCD Data Register 1 + LCDDR0: 0xec, // LCD Data Register 0 + LCDCCR: 0xe7, // LCD Contrast Control Register + LCDFRR: 0xe6, // LCD Frame Rate Register + LCDCRB: 0xe5, // LCD Control and Status Register B + LCDCRA: 0xe4, // LCD Control Register A + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + PRR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + PRR: 0x64, // Power Reduction Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x6 // Brown-out Detector trigger level + EXTENDED_RSTDISBL = 0x1 // External Reset Disable + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM memory through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0A: Timer/Counter0 Control Register + TCCR0A_FOC0A = 0x80 // Force Output Compare + TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0A_COM0A = 0x30 // Compare Match Output Modes + TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0A_CS0 = 0x7 // Clock Selects + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0 + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2A: Timer/Counter2 Control Register + TCCR2A_FOC2A = 0x80 // Force Output Compare A + TCCR2A_WGM20 = 0x40 // Waveform Generation Mode + TCCR2A_COM2A = 0x30 // Compare Output Mode bits + TCCR2A_WGM21 = 0x8 // Waveform Generation Mode + TCCR2A_CS2 = 0x7 // Clock Select bits + + // TIMSK2: Timer/Counter2 Interrupt Mask register + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter2 Interrupt Flag Register + TIFR2_OCF2A = 0x2 // Timer/Counter2 Output Compare Flag 2 + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x10 // Enable External Clock Interrupt + ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC01 = 0x2 // External Interrupt Sense Control 0 Bit 1 + EICRA_ISC00 = 0x1 // External Interrupt Sense Control 0 Bit 0 + + // EIMSK: External Interrupt Mask Register + EIMSK_PCIE = 0xf0 // Pin Change Interrupt Enables + EIMSK_INT0 = 0x1 // External Interrupt Request 0 Enable + + // EIFR: External Interrupt Flag Register + EIFR_PCIF = 0xf0 // Pin Change Interrupt Flags + EIFR_INTF0 = 0x1 // External Interrupt Flag 0 + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT8 = 0x1 // Pin Change Mask Register pin 8 + PCMSK1_PCINT9 = 0x2 // Pin Change Mask Register pin 9 + PCMSK1_PCINT10 = 0x4 // Pin Change Mask Register pin 10 + PCMSK1_PCINT11 = 0x8 // Pin Change Mask Register pin 11 + PCMSK1_PCINT12 = 0x10 // Pin Change Mask Register pin 12 + PCMSK1_PCINT13 = 0x20 // Pin Change Mask Register pin 13 + PCMSK1_PCINT14 = 0x40 // Pin Change Mask Register pin 14 + PCMSK1_PCINT15 = 0x80 // Pin Change Mask Register pin 15 + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT0 = 0x1 // Pin Change Mask Register pin 0 + PCMSK0_PCINT1 = 0x2 // Pin Change Mask Register pin 1 + PCMSK0_PCINT2 = 0x4 // Pin Change Mask Register pin 2 + PCMSK0_PCINT3 = 0x8 // Pin Change Mask Register pin 3 + PCMSK0_PCINT4 = 0x10 // Pin Change Mask Register pin 4 + PCMSK0_PCINT5 = 0x20 // Pin Change Mask Register pin 5 + PCMSK0_PCINT6 = 0x40 // Pin Change Mask Register pin 6 + PCMSK0_PCINT7 = 0x80 // Pin Change Mask Register pin 7 +) + +// Bitfields for USI: Universal Serial Interface +const ( + // USISR: USI Status Register + USISR_USISIF = 0x80 // Start Condition Interrupt Flag + USISR_USIOIF = 0x40 // Counter Overflow Interrupt Flag + USISR_USIPF = 0x20 // Stop Condition Flag + USISR_USIDC = 0x10 // Data Output Collision + USISR_USICNT = 0xf // USI Counter Value Bits + + // USICR: USI Control Register + USICR_USISIE = 0x80 // Start Condition Interrupt Enable + USICR_USIOIE = 0x40 // Counter Overflow Interrupt Enable + USICR_USIWM = 0x30 // USI Wire Mode Bits + USICR_USICS = 0xc // USI Clock Source Select Bits + USICR_USICLK = 0x2 // Clock Strobe + USICR_USITC = 0x1 // Toggle Clock Port Pin +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmit Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data OverRun + UCSR0A_UPE0 = 0x4 // USART Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART Transmission Speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data Register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0x40 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) + +// Bitfields for LCD: Liquid Crystal Display +const ( + // LCDDR18: LCD Data Register 18 + LCDDR18_SEG324 = 0x1 // LCD memory bit segment + LCDDR18_SEG325 = 0x2 // LCD memory bit segment + LCDDR18_SEG326 = 0x4 // LCD memory bit segment + LCDDR18_SEG327 = 0x8 // LCD memory bit segment + LCDDR18_SEG328 = 0x10 // LCD memory bit segment + LCDDR18_SEG329 = 0x20 // LCD memory bit segment + LCDDR18_SEG330 = 0x40 // LCD memory bit segment + LCDDR18_SEG331 = 0x80 // LCD memory bit segment + + // LCDDR17: LCD Data Register 17 + LCDDR17_SEG316 = 0x1 // LCD memory bit segment + LCDDR17_SEG317 = 0x2 // LCD memory bit segment + LCDDR17_SEG318 = 0x4 // LCD memory bit segment + LCDDR17_SEG319 = 0x8 // LCD memory bit segment + LCDDR17_SEG320 = 0x10 // LCD memory bit segment + LCDDR17_SEG321 = 0x20 // LCD memory bit segment + LCDDR17_SEG322 = 0x40 // LCD memory bit segment + LCDDR17_SEG323 = 0x80 // LCD memory bit segment + + // LCDDR16: LCD Data Register 16 + LCDDR16_SEG308 = 0x1 // LCD memory bit segment + LCDDR16_SEG309 = 0x2 // LCD memory bit segment + LCDDR16_SEG310 = 0x4 // LCD memory bit segment + LCDDR16_SEG311 = 0x8 // LCD memory bit segment + LCDDR16_SEG312 = 0x10 // LCD memory bit segment + LCDDR16_SEG313 = 0x20 // LCD memory bit segment + LCDDR16_SEG314 = 0x40 // LCD memory bit segment + LCDDR16_SEG315 = 0x80 // LCD memory bit segment + + // LCDDR15: LCD Data Register 15 + LCDDR15_SEG300 = 0x1 // LCD memory bit segment + LCDDR15_SEG301 = 0x2 // LCD memory bit segment + LCDDR15_SEG302 = 0x4 // LCD memory bit segment + LCDDR15_SEG303 = 0x8 // LCD memory bit segment + LCDDR15_SEG304 = 0x10 // LCD memory bit segment + LCDDR15_SEG305 = 0x20 // LCD memory bit segment + LCDDR15_SEG306 = 0x40 // LCD memory bit segment + LCDDR15_SEG307 = 0x80 // LCD memory bit segment + + // LCDDR13: LCD Data Register 13 + LCDDR13_SEG224 = 0x1 // LCD memory bit segment + LCDDR13_SEG225 = 0x2 // LCD memory bit segment + LCDDR13_SEG226 = 0x4 // LCD memory bit segment + LCDDR13_SEG227 = 0x8 // LCD memory bit segment + LCDDR13_SEG228 = 0x10 // LCD memory bit segment + LCDDR13_SEG229 = 0x20 // LCD memory bit segment + LCDDR13_SEG230 = 0x40 // LCD memory bit segment + LCDDR13_SEG231 = 0x80 // LCD memory bit segment + + // LCDDR12: LCD Data Register 12 + LCDDR12_SEG216 = 0x1 // LCD memory bit segment + LCDDR12_SEG217 = 0x2 // LCD memory bit segment + LCDDR12_SEG218 = 0x4 // LCD memory bit segment + LCDDR12_SEG219 = 0x8 // LCD memory bit segment + LCDDR12_SEG220 = 0x10 // LCD memory bit segment + LCDDR12_SEG221 = 0x20 // LCD memory bit segment + LCDDR12_SEG222 = 0x40 // LCD memory bit segment + LCDDR12_SEG223 = 0x80 // LCD memory bit segment + + // LCDDR11: LCD Data Register 11 + LCDDR11_SEG208 = 0x1 // LCD memory bit segment + LCDDR11_SEG209 = 0x2 // LCD memory bit segment + LCDDR11_SEG210 = 0x4 // LCD memory bit segment + LCDDR11_SEG211 = 0x8 // LCD memory bit segment + LCDDR11_SEG212 = 0x10 // LCD memory bit segment + LCDDR11_SEG213 = 0x20 // LCD memory bit segment + LCDDR11_SEG214 = 0x40 // LCD memory bit segment + LCDDR11_SEG215 = 0x80 // LCD memory bit segment + + // LCDDR10: LCD Data Register 10 + LCDDR10_SEG200 = 0x1 // LCD memory bit segment + LCDDR10_SEG201 = 0x2 // LCD memory bit segment + LCDDR10_SEG202 = 0x4 // LCD memory bit segment + LCDDR10_SEG203 = 0x8 // LCD memory bit segment + LCDDR10_SEG204 = 0x10 // LCD memory bit segment + LCDDR10_SEG205 = 0x20 // LCD memory bit segment + LCDDR10_SEG206 = 0x40 // LCD memory bit segment + LCDDR10_SEG207 = 0x80 // LCD memory bit segment + + // LCDDR8: LCD Data Register 8 + LCDDR8_SEG124 = 0x1 // LCD memory bit segment + LCDDR8_SEG125 = 0x2 // LCD memory bit segment + LCDDR8_SEG126 = 0x4 // LCD memory bit segment + LCDDR8_SEG127 = 0x8 // LCD memory bit segment + LCDDR8_SEG128 = 0x10 // LCD memory bit segment + LCDDR8_SEG129 = 0x20 // LCD memory bit segment + LCDDR8_SEG130 = 0x40 // LCD memory bit segment + LCDDR8_SEG131 = 0x80 // LCD memory bit segment + + // LCDDR7: LCD Data Register 7 + LCDDR7_SEG116 = 0x1 // LCD memory bit segment + LCDDR7_SEG117 = 0x2 // LCD memory bit segment + LCDDR7_SEG118 = 0x4 // LCD memory bit segment + LCDDR7_SEG119 = 0x8 // LCD memory bit segment + LCDDR7_SEG120 = 0x10 // LCD memory bit segment + LCDDR7_SEG121 = 0x20 // LCD memory bit segment + LCDDR7_SEG122 = 0x40 // LCD memory bit segment + LCDDR7_SEG123 = 0x80 // LCD memory bit segment + + // LCDDR6: LCD Data Register 6 + LCDDR6_SEG108 = 0x1 // LCD memory bit segment + LCDDR6_SEG109 = 0x2 // LCD memory bit segment + LCDDR6_SEG110 = 0x4 // LCD memory bit segment + LCDDR6_SEG111 = 0x8 // LCD memory bit segment + LCDDR6_SEG112 = 0x10 // LCD memory bit segment + LCDDR6_SEG113 = 0x20 // LCD memory bit segment + LCDDR6_SEG114 = 0x40 // LCD memory bit segment + LCDDR6_SEG115 = 0x80 // LCD memory bit segment + + // LCDDR5: LCD Data Register 5 + LCDDR5_SEG100 = 0x1 // LCD memory bit segment + LCDDR5_SEG101 = 0x2 // LCD memory bit segment + LCDDR5_SEG102 = 0x4 // LCD memory bit segment + LCDDR5_SEG103 = 0x8 // LCD memory bit segment + LCDDR5_SEG104 = 0x10 // LCD memory bit segment + LCDDR5_SEG105 = 0x20 // LCD memory bit segment + LCDDR5_SEG106 = 0x40 // LCD memory bit segment + LCDDR5_SEG107 = 0x80 // LCD memory bit segment + + // LCDDR3: LCD Data Register 3 + LCDDR3_SEG024 = 0x1 // LCD memory bit segment + LCDDR3_SEG025 = 0x2 // LCD memory bit segment + LCDDR3_SEG026 = 0x4 // LCD memory bit segment + LCDDR3_SEG027 = 0x8 // LCD memory bit segment + LCDDR3_SEG028 = 0x10 // LCD memory bit segment + LCDDR3_SEG029 = 0x20 // LCD memory bit segment + LCDDR3_SEG030 = 0x40 // LCD memory bit segment + LCDDR3_SEG031 = 0x80 // LCD memory bit segment + + // LCDDR2: LCD Data Register 2 + LCDDR2_SEG016 = 0x1 // LCD memory bit segment + LCDDR2_SEG017 = 0x2 // LCD memory bit segment + LCDDR2_SEG018 = 0x4 // LCD memory bit segment + LCDDR2_SEG019 = 0x8 // LCD memory bit segment + LCDDR2_SEG020 = 0x10 // LCD memory bit segment + LCDDR2_SEG021 = 0x20 // LCD memory bit segment + LCDDR2_SEG022 = 0x40 // LCD memory bit segment + LCDDR2_SEG023 = 0x80 // LCD memory bit segment + + // LCDDR1: LCD Data Register 1 + LCDDR1_SEG008 = 0x1 // LCD memory bit segment + LCDDR1_SEG009 = 0x2 // LCD memory bit segment + LCDDR1_SEG010 = 0x4 // LCD memory bit segment + LCDDR1_SEG011 = 0x8 // LCD memory bit segment + LCDDR1_SEG012 = 0x10 // LCD memory bit segment + LCDDR1_SEG013 = 0x20 // LCD memory bit segment + LCDDR1_SEG014 = 0x40 // LCD memory bit segment + LCDDR1_SEG015 = 0x80 // LCD memory bit segment + + // LCDDR0: LCD Data Register 0 + LCDDR0_SEG000 = 0x1 // LCD memory bit segment + LCDDR0_SEG001 = 0x2 // LCD memory bit segment + LCDDR0_SEG002 = 0x4 // LCD memory bit segment + LCDDR0_SEG003 = 0x8 // LCD memory bit segment + LCDDR0_SEG004 = 0x10 // LCD memory bit segment + LCDDR0_SEG005 = 0x20 // LCD memory bit segment + LCDDR0_SEG006 = 0x40 // LCD memory bit segment + LCDDR0_SEG007 = 0x80 // LCD memory bit segment + + // LCDCCR: LCD Contrast Control Register + LCDCCR_LCDDC = 0xe0 + LCDCCR_LCDMDT = 0x10 // LCD Maximum Drive Time + LCDCCR_LCDCC = 0xf // LCD Contrast Controls + + // LCDFRR: LCD Frame Rate Register + LCDFRR_LCDPS = 0x70 // LCD Prescaler Selects + LCDFRR_LCDCD = 0x7 // LCD Clock Dividers + + // LCDCRB: LCD Control and Status Register B + LCDCRB_LCDCS = 0x80 // LCD CLock Select + LCDCRB_LCD2B = 0x40 // LCD 1/2 Bias Select + LCDCRB_LCDMUX = 0x30 // LCD Mux Selects + LCDCRB_LCDPM = 0xf // LCD Port Masks + + // LCDCRA: LCD Control Register A + LCDCRA_LCDEN = 0x80 // LCD Enable + LCDCRA_LCDAB = 0x40 // LCD A or B waveform + LCDCRA_LCDIF = 0x10 // LCD Interrupt Flag + LCDCRA_LCDIE = 0x8 // LCD Interrupt Enable + LCDCRA_LCDBD = 0x4 // LCD Buffer Disable + LCDCRA_LCDCCD = 0x2 // LCD Contrast Control Disable + LCDCRA_LCDBL = 0x1 // LCD Blanking +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // PRR: Power Reduction Register + PRR_PRLCD = 0x10 // Power Reduction LCD + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable +) diff --git a/src/device/avr/atmega329p.ld b/src/device/avr/atmega329p.ld new file mode 100644 index 00000000..72e9b93c --- /dev/null +++ b/src/device/avr/atmega329p.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega329P.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_size = 0x800; +__num_isrs = 23; diff --git a/src/device/avr/atmega329pa.go b/src/device/avr/atmega329pa.go new file mode 100644 index 00000000..f31a584c --- /dev/null +++ b/src/device/avr/atmega329pa.go @@ -0,0 +1,839 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega329PA.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega329pa + +// Device information for the ATmega329PA. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega329PA" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_PCINT0 = 2 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 3 // Pin Change Interrupt Request 1 + IRQ_TIMER2_COMP = 4 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 5 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 6 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 7 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 8 // Timer/Counter Compare Match B + IRQ_TIMER1_OVF = 9 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 10 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 11 // Timer/Counter0 Overflow + IRQ_SPI_STC = 12 // SPI Serial Transfer Complete + IRQ_USART0_RX = 13 // USART0, Rx Complete + IRQ_USART0_UDRE = 14 // USART0 Data register Empty + IRQ_USART0_TX = 15 // USART0, Tx Complete + IRQ_USI_START = 16 // USI Start Condition + IRQ_USI_OVERFLOW = 17 // USI Overflow + IRQ_ANALOG_COMP = 18 // Analog Comparator + IRQ_ADC = 19 // ADC Conversion Complete + IRQ_EE_READY = 20 // EEPROM Ready + IRQ_SPM_READY = 21 // Store Program Memory Read + IRQ_LCD = 22 // LCD Start of Frame + IRQ_max = 22 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0A __reg + TCNT0 __reg + OCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR0A: 0x44, // Timer/Counter0 Control Register + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2A __reg + TCNT2 __reg + OCR2A __reg + TIMSK2 __reg + TIFR2 __reg + ASSR __reg + }{ + TCCR2A: 0xb0, // Timer/Counter2 Control Register + TCNT2: 0xb2, // Timer/Counter2 + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register + TIMSK2: 0x70, // Timer/Counter2 Interrupt Mask register + TIFR2: 0x37, // Timer/Counter2 Interrupt Flag Register + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x60, // Watchdog Timer Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access Bytes + EEARH: 0x41, // EEPROM Read/Write Access Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + PORTG: 0x34, // Port G Data Register + DDRG: 0x33, // Port G Data Direction Register + PING: 0x32, // Port G Input Pins + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // Liquid Crystal Display + LCD = struct { + LCDDR18 __reg + LCDDR17 __reg + LCDDR16 __reg + LCDDR15 __reg + LCDDR13 __reg + LCDDR12 __reg + LCDDR11 __reg + LCDDR10 __reg + LCDDR08 __reg + LCDDR07 __reg + LCDDR06 __reg + LCDDR05 __reg + LCDDR03 __reg + LCDDR02 __reg + LCDDR01 __reg + LCDDR00 __reg + LCDCCR __reg + LCDFRR __reg + LCDCRB __reg + LCDCRA __reg + }{ + LCDDR18: 0xfe, // LCD Data Register 18 + LCDDR17: 0xfd, // LCD Data Register 17 + LCDDR16: 0xfc, // LCD Data Register 16 + LCDDR15: 0xfb, // LCD Data Register 15 + LCDDR13: 0xf9, // LCD Data Register 13 + LCDDR12: 0xf8, // LCD Data Register 12 + LCDDR11: 0xf7, // LCD Data Register 11 + LCDDR10: 0xf6, // LCD Data Register 10 + LCDDR08: 0xf4, // LCD Data Register 8 + LCDDR07: 0xf3, // LCD Data Register 7 + LCDDR06: 0xf2, // LCD Data Register 6 + LCDDR05: 0xf1, // LCD Data Register 5 + LCDDR03: 0xef, // LCD Data Register 3 + LCDDR02: 0xee, // LCD Data Register 2 + LCDDR01: 0xed, // LCD Data Register 1 + LCDDR00: 0xec, // LCD Data Register 0 + LCDCCR: 0xe7, // LCD Contrast Control Register + LCDFRR: 0xe6, // LCD Frame Rate Register + LCDCRB: 0xe5, // LCD Control and Status Register B + LCDCRA: 0xe4, // LCD Control Register A + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK1 __reg + PCMSK0 __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + PRR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + PRR: 0x64, // Power Reduction Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + } + + // Universal Serial Interface + USI = struct { + USIDR __reg + USISR __reg + USICR __reg + }{ + USIDR: 0xba, // USI Data Register + USISR: 0xb9, // USI Status Register + USICR: 0xb8, // USI Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 0 + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x6 // Brown-out Detector trigger level + EXTENDED_RSTDISBL = 0x1 // External Reset Disable + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM memory through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0A: Timer/Counter0 Control Register + TCCR0A_FOC0A = 0x80 // Force Output Compare + TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0A_COM0A = 0x30 // Compare Match Output Modes + TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0A_CS0 = 0x7 // Clock Selects + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0 + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2A: Timer/Counter2 Control Register + TCCR2A_FOC2A = 0x80 // Force Output Compare A + TCCR2A_WGM20 = 0x40 // Waveform Generation Mode + TCCR2A_COM2A = 0x30 // Compare Output Mode bits + TCCR2A_WGM21 = 0x8 // Waveform Generation Mode + TCCR2A_CS2 = 0x7 // Clock Select bits + + // TIMSK2: Timer/Counter2 Interrupt Mask register + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter2 Interrupt Flag Register + TIFR2_OCF2A = 0x2 // Timer/Counter2 Output Compare Flag 2 + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x10 // Enable External Clock Interrupt + ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for LCD: Liquid Crystal Display +const ( + // LCDDR18: LCD Data Register 18 + LCDDR18_SEG324 = 0x1 // LCD memory bit segment + LCDDR18_SEG325 = 0x2 // LCD memory bit segment + LCDDR18_SEG326 = 0x4 // LCD memory bit segment + LCDDR18_SEG327 = 0x8 // LCD memory bit segment + LCDDR18_SEG328 = 0x10 // LCD memory bit segment + LCDDR18_SEG329 = 0x20 // LCD memory bit segment + LCDDR18_SEG330 = 0x40 // LCD memory bit segment + LCDDR18_SEG331 = 0x80 // LCD memory bit segment + + // LCDDR17: LCD Data Register 17 + LCDDR17_SEG316 = 0x1 // LCD memory bit segment + LCDDR17_SEG317 = 0x2 // LCD memory bit segment + LCDDR17_SEG318 = 0x4 // LCD memory bit segment + LCDDR17_SEG319 = 0x8 // LCD memory bit segment + LCDDR17_SEG320 = 0x10 // LCD memory bit segment + LCDDR17_SEG321 = 0x20 // LCD memory bit segment + LCDDR17_SEG322 = 0x40 // LCD memory bit segment + LCDDR17_SEG323 = 0x80 // LCD memory bit segment + + // LCDDR16: LCD Data Register 16 + LCDDR16_SEG308 = 0x1 // LCD memory bit segment + LCDDR16_SEG309 = 0x2 // LCD memory bit segment + LCDDR16_SEG310 = 0x4 // LCD memory bit segment + LCDDR16_SEG311 = 0x8 // LCD memory bit segment + LCDDR16_SEG312 = 0x10 // LCD memory bit segment + LCDDR16_SEG313 = 0x20 // LCD memory bit segment + LCDDR16_SEG314 = 0x40 // LCD memory bit segment + LCDDR16_SEG315 = 0x80 // LCD memory bit segment + + // LCDDR15: LCD Data Register 15 + LCDDR15_SEG300 = 0x1 // LCD memory bit segment + LCDDR15_SEG301 = 0x2 // LCD memory bit segment + LCDDR15_SEG302 = 0x4 // LCD memory bit segment + LCDDR15_SEG303 = 0x8 // LCD memory bit segment + LCDDR15_SEG304 = 0x10 // LCD memory bit segment + LCDDR15_SEG305 = 0x20 // LCD memory bit segment + LCDDR15_SEG306 = 0x40 // LCD memory bit segment + LCDDR15_SEG307 = 0x80 // LCD memory bit segment + + // LCDDR13: LCD Data Register 13 + LCDDR13_SEG224 = 0x1 // LCD memory bit segment + LCDDR13_SEG225 = 0x2 // LCD memory bit segment + LCDDR13_SEG226 = 0x4 // LCD memory bit segment + LCDDR13_SEG227 = 0x8 // LCD memory bit segment + LCDDR13_SEG228 = 0x10 // LCD memory bit segment + LCDDR13_SEG229 = 0x20 // LCD memory bit segment + LCDDR13_SEG230 = 0x40 // LCD memory bit segment + LCDDR13_SEG231 = 0x80 // LCD memory bit segment + + // LCDDR12: LCD Data Register 12 + LCDDR12_SEG216 = 0x1 // LCD memory bit segment + LCDDR12_SEG217 = 0x2 // LCD memory bit segment + LCDDR12_SEG218 = 0x4 // LCD memory bit segment + LCDDR12_SEG219 = 0x8 // LCD memory bit segment + LCDDR12_SEG220 = 0x10 // LCD memory bit segment + LCDDR12_SEG221 = 0x20 // LCD memory bit segment + LCDDR12_SEG222 = 0x40 // LCD memory bit segment + LCDDR12_SEG223 = 0x80 // LCD memory bit segment + + // LCDDR11: LCD Data Register 11 + LCDDR11_SEG208 = 0x1 // LCD memory bit segment + LCDDR11_SEG209 = 0x2 // LCD memory bit segment + LCDDR11_SEG210 = 0x4 // LCD memory bit segment + LCDDR11_SEG211 = 0x8 // LCD memory bit segment + LCDDR11_SEG212 = 0x10 // LCD memory bit segment + LCDDR11_SEG213 = 0x20 // LCD memory bit segment + LCDDR11_SEG214 = 0x40 // LCD memory bit segment + LCDDR11_SEG215 = 0x80 // LCD memory bit segment + + // LCDDR10: LCD Data Register 10 + LCDDR10_SEG200 = 0x1 // LCD memory bit segment + LCDDR10_SEG201 = 0x2 // LCD memory bit segment + LCDDR10_SEG202 = 0x4 // LCD memory bit segment + LCDDR10_SEG203 = 0x8 // LCD memory bit segment + LCDDR10_SEG204 = 0x10 // LCD memory bit segment + LCDDR10_SEG205 = 0x20 // LCD memory bit segment + LCDDR10_SEG206 = 0x40 // LCD memory bit segment + LCDDR10_SEG207 = 0x80 // LCD memory bit segment + + // LCDDR08: LCD Data Register 8 + LCDDR08_SEG124 = 0x1 // LCD memory bit segment + LCDDR08_SEG125 = 0x2 // LCD memory bit segment + LCDDR08_SEG126 = 0x4 // LCD memory bit segment + LCDDR08_SEG127 = 0x8 // LCD memory bit segment + LCDDR08_SEG128 = 0x10 // LCD memory bit segment + LCDDR08_SEG129 = 0x20 // LCD memory bit segment + LCDDR08_SEG130 = 0x40 // LCD memory bit segment + LCDDR08_SEG131 = 0x80 // LCD memory bit segment + + // LCDDR07: LCD Data Register 7 + LCDDR07_SEG116 = 0x1 // LCD memory bit segment + LCDDR07_SEG117 = 0x2 // LCD memory bit segment + LCDDR07_SEG118 = 0x4 // LCD memory bit segment + LCDDR07_SEG119 = 0x8 // LCD memory bit segment + LCDDR07_SEG120 = 0x10 // LCD memory bit segment + LCDDR07_SEG121 = 0x20 // LCD memory bit segment + LCDDR07_SEG122 = 0x40 // LCD memory bit segment + LCDDR07_SEG123 = 0x80 // LCD memory bit segment + + // LCDDR06: LCD Data Register 6 + LCDDR06_SEG108 = 0x1 // LCD memory bit segment + LCDDR06_SEG109 = 0x2 // LCD memory bit segment + LCDDR06_SEG110 = 0x4 // LCD memory bit segment + LCDDR06_SEG111 = 0x8 // LCD memory bit segment + LCDDR06_SEG112 = 0x10 // LCD memory bit segment + LCDDR06_SEG113 = 0x20 // LCD memory bit segment + LCDDR06_SEG114 = 0x40 // LCD memory bit segment + LCDDR06_SEG115 = 0x80 // LCD memory bit segment + + // LCDDR05: LCD Data Register 5 + LCDDR05_SEG100 = 0x1 // LCD memory bit segment + LCDDR05_SEG101 = 0x2 // LCD memory bit segment + LCDDR05_SEG102 = 0x4 // LCD memory bit segment + LCDDR05_SEG103 = 0x8 // LCD memory bit segment + LCDDR05_SEG104 = 0x10 // LCD memory bit segment + LCDDR05_SEG105 = 0x20 // LCD memory bit segment + LCDDR05_SEG106 = 0x40 // LCD memory bit segment + LCDDR05_SEG107 = 0x80 // LCD memory bit segment + + // LCDDR03: LCD Data Register 3 + LCDDR03_SEG024 = 0x1 // LCD memory bit segment + LCDDR03_SEG025 = 0x2 // LCD memory bit segment + LCDDR03_SEG026 = 0x4 // LCD memory bit segment + LCDDR03_SEG027 = 0x8 // LCD memory bit segment + LCDDR03_SEG028 = 0x10 // LCD memory bit segment + LCDDR03_SEG029 = 0x20 // LCD memory bit segment + LCDDR03_SEG030 = 0x40 // LCD memory bit segment + LCDDR03_SEG031 = 0x80 // LCD memory bit segment + + // LCDDR02: LCD Data Register 2 + LCDDR02_SEG016 = 0x1 // LCD memory bit segment + LCDDR02_SEG017 = 0x2 // LCD memory bit segment + LCDDR02_SEG018 = 0x4 // LCD memory bit segment + LCDDR02_SEG019 = 0x8 // LCD memory bit segment + LCDDR02_SEG020 = 0x10 // LCD memory bit segment + LCDDR02_SEG021 = 0x20 // LCD memory bit segment + LCDDR02_SEG022 = 0x40 // LCD memory bit segment + LCDDR02_SEG023 = 0x80 // LCD memory bit segment + + // LCDDR01: LCD Data Register 1 + LCDDR01_SEG008 = 0x1 // LCD memory bit segment + LCDDR01_SEG009 = 0x2 // LCD memory bit segment + LCDDR01_SEG010 = 0x4 // LCD memory bit segment + LCDDR01_SEG011 = 0x8 // LCD memory bit segment + LCDDR01_SEG012 = 0x10 // LCD memory bit segment + LCDDR01_SEG013 = 0x20 // LCD memory bit segment + LCDDR01_SEG014 = 0x40 // LCD memory bit segment + LCDDR01_SEG015 = 0x80 // LCD memory bit segment + + // LCDDR00: LCD Data Register 0 + LCDDR00_SEG000 = 0x1 // LCD memory bit segment + LCDDR00_SEG001 = 0x2 // LCD memory bit segment + LCDDR00_SEG002 = 0x4 // LCD memory bit segment + LCDDR00_SEG003 = 0x8 // LCD memory bit segment + LCDDR00_SEG004 = 0x10 // LCD memory bit segment + LCDDR00_SEG005 = 0x20 // LCD memory bit segment + LCDDR00_SEG006 = 0x40 // LCD memory bit segment + LCDDR00_SEG007 = 0x80 // LCD memory bit segment + + // LCDCCR: LCD Contrast Control Register + LCDCCR_LCDDC = 0xe0 // LCD Display Configuration + LCDCCR_LCDMDT = 0x10 // LCD Maximum Drive Time + LCDCCR_LCDCC = 0xf // LCD Contrast Controls + + // LCDFRR: LCD Frame Rate Register + LCDFRR_LCDPS = 0x70 // LCD Prescaler Selects + LCDFRR_LCDCD = 0x7 // LCD Clock Dividers + + // LCDCRB: LCD Control and Status Register B + LCDCRB_LCDCS = 0x80 // LCD CLock Select + LCDCRB_LCD2B = 0x40 // LCD 1/2 Bias Select + LCDCRB_LCDMUX = 0x30 // LCD Mux Selects + LCDCRB_LCDPM = 0xf // LCD Port Masks + + // LCDCRA: LCD Control Register A + LCDCRA_LCDEN = 0x80 // LCD Enable + LCDCRA_LCDAB = 0x40 // LCD A or B waveform + LCDCRA_LCDIF = 0x10 // LCD Interrupt Flag + LCDCRA_LCDIE = 0x8 // LCD Interrupt Enable + LCDCRA_LCDBD = 0x4 // LCD Buffer Disable + LCDCRA_LCDCCD = 0x2 // LCD Contrast Control Disable + LCDCRA_LCDBL = 0x1 // LCD Blanking +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC01 = 0x2 // External Interrupt Sense Control 0 Bit 1 + EICRA_ISC00 = 0x1 // External Interrupt Sense Control 0 Bit 0 + + // EIMSK: External Interrupt Mask Register + EIMSK_PCIE = 0xf0 // Pin Change Interrupt Enables + EIMSK_INT0 = 0x1 // External Interrupt Request 0 Enable + + // EIFR: External Interrupt Flag Register + EIFR_PCIF = 0xf0 // Pin Change Interrupt Flags + EIFR_INTF0 = 0x1 // External Interrupt Flag 0 + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Mask + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Mask +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // PRR: Power Reduction Register + PRR_PRLCD = 0x10 // Power Reduction LCD + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable +) + +// Bitfields for USI: Universal Serial Interface +const ( + // USISR: USI Status Register + USISR_USISIF = 0x80 // Start Condition Interrupt Flag + USISR_USIOIF = 0x40 // Counter Overflow Interrupt Flag + USISR_USIPF = 0x20 // Stop Condition Flag + USISR_USIDC = 0x10 // Data Output Collision + USISR_USICNT = 0xf // USI Counter Value Bits + + // USICR: USI Control Register + USICR_USISIE = 0x80 // Start Condition Interrupt Enable + USICR_USIOIE = 0x40 // Counter Overflow Interrupt Enable + USICR_USIWM = 0x30 // USI Wire Mode Bits + USICR_USICS = 0xc // USI Clock Source Select Bits + USICR_USICLK = 0x2 // Clock Strobe + USICR_USITC = 0x1 // Toggle Clock Port Pin +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmit Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data OverRun + UCSR0A_UPE0 = 0x4 // USART Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART Transmission Speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data Register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0x40 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) diff --git a/src/device/avr/atmega329pa.ld b/src/device/avr/atmega329pa.ld new file mode 100644 index 00000000..c4b94fa9 --- /dev/null +++ b/src/device/avr/atmega329pa.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega329PA.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_size = 0x800; +__num_isrs = 23; diff --git a/src/device/avr/atmega32a.go b/src/device/avr/atmega32a.go new file mode 100644 index 00000000..7566b311 --- /dev/null +++ b/src/device/avr/atmega32a.go @@ -0,0 +1,474 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega32A.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega32a + +// Device information for the ATmega32A. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega32A" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_TIMER2_COMP = 4 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 5 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 6 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 7 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 8 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 9 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 10 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 11 // Timer/Counter0 Overflow + IRQ_SPI_STC = 12 // Serial Transfer Complete + IRQ_USART_RXC = 13 // USART, Rx Complete + IRQ_USART_UDRE = 14 // USART Data Register Empty + IRQ_USART_TXC = 15 // USART, Tx Complete + IRQ_ADC = 16 // ADC Conversion Complete + IRQ_EE_RDY = 17 // EEPROM Ready + IRQ_ANA_COMP = 18 // Analog Comparator + IRQ_TWI = 19 // 2-wire Serial Interface + IRQ_SPM_RDY = 20 // Store Program Memory Ready + IRQ_max = 20 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + HIGH __reg + LOW __reg + }{ + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x3e, // EEPROM Read/Write Access Bytes + EEARH: 0x3e, // EEPROM Read/Write Access Bytes + EEDR: 0x3d, // EEPROM Data Register + EECR: 0x3c, // EEPROM Control Register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x41, // Watchdog Timer Control Register + } + + // External Interrupts + EXINT = struct { + GICR __reg + GIFR __reg + }{ + GICR: 0x5b, // General Interrupt Control Register + GIFR: 0x5a, // General Interrupt Flag Register + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0 __reg + TCNT0 __reg + OCR0 __reg + }{ + TCCR0: 0x53, // Timer/Counter Control Register + TCNT0: 0x52, // Timer/Counter Register + OCR0: 0x5c, // Output Compare Register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2 __reg + TCNT2 __reg + OCR2 __reg + ASSR __reg + }{ + TCCR2: 0x45, // Timer/Counter2 Control Register + TCNT2: 0x44, // Timer/Counter2 + OCR2: 0x43, // Timer/Counter2 Output Compare Register + ASSR: 0x42, // Asynchronous Status Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TCCR1A: 0x4f, // Timer/Counter1 Control Register A + TCCR1B: 0x4e, // Timer/Counter1 Control Register B + TCNT1L: 0x4c, // Timer/Counter1 Bytes + TCNT1H: 0x4c, // Timer/Counter1 Bytes + OCR1AL: 0x4a, // Timer/Counter1 Output Compare Register Bytes + OCR1AH: 0x4a, // Timer/Counter1 Output Compare Register Bytes + OCR1BL: 0x48, // Timer/Counter1 Output Compare Register Bytes + OCR1BH: 0x48, // Timer/Counter1 Output Compare Register Bytes + ICR1L: 0x46, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x46, // Timer/Counter1 Input Capture Register Bytes + } + + // Serial Peripheral Interface + SPI = struct { + SPDR __reg + SPSR __reg + SPCR __reg + }{ + SPDR: 0x2f, // SPI Data Register + SPSR: 0x2e, // SPI Status Register + SPCR: 0x2d, // SPI Control Register + } + + // USART + USART = struct { + UDR __reg + UCSRA __reg + UCSRB __reg + UCSRC __reg + UBRRH __reg + UBRRL __reg + }{ + UDR: 0x2c, // USART I/O Data Register + UCSRA: 0x2b, // USART Control and Status Register A + UCSRB: 0x2a, // USART Control and Status Register B + UCSRC: 0x40, // USART Control and Status Register C + UBRRH: 0x40, // USART Baud Rate Register Hight Byte + UBRRL: 0x29, // USART Baud Rate Register Low Byte + } + + // Analog Comparator + AC = struct { + ACSR __reg + }{ + ACSR: 0x28, // Analog Comparator Control And Status Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + }{ + ADMUX: 0x27, // The ADC multiplexer Selection Register + ADCSRA: 0x26, // The ADC Control and Status register + ADCL: 0x24, // ADC Data Register Bytes + ADCH: 0x24, // ADC Data Register Bytes + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + }{ + PORTA: 0x3b, // Port A Data Register + DDRA: 0x3a, // Port A Data Direction Register + PINA: 0x39, // Port A Input Pins + PORTB: 0x38, // Port B Data Register + DDRB: 0x37, // Port B Data Direction Register + PINB: 0x36, // Port B Input Pins + PORTC: 0x35, // Port C Data Register + DDRC: 0x34, // Port C Data Direction Register + PINC: 0x33, // Port C Input Pins + PORTD: 0x32, // Port D Data Register + DDRD: 0x31, // Port D Data Direction Register + PIND: 0x30, // Port D Input Pins + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x51, // Oscillator Calibration Value + } + + // Bootloader + BOOT_LOAD = struct { + SPMCR __reg + }{ + SPMCR: 0x57, // Store Program Memory Control Register + } + + // Two Wire Serial Interface + TWI = struct { + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWBR: 0x20, // TWI Bit Rate register + TWCR: 0x56, // TWI Control Register + TWSR: 0x21, // TWI Status Register + TWDR: 0x23, // TWI Data register + TWAR: 0x22, // TWI (Slave) Address register + } +) + +// Bitfields for FUSE: Fuses +const ( + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_CKOPT = 0x10 // Oscillator options + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_BODLEVEL = 0x80 // Brownout detector trigger level + LOW_BODEN = 0x40 // Brown-out detection enabled + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDTOE = 0x10 // RW + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for EXINT: External Interrupts +const ( + // GICR: General Interrupt Control Register + GICR_INT0 = 0x40 // External Interrupt Request 0 Enable + GICR_INT1 = 0x80 // External Interrupt Request 1 Enable + GICR_INT2 = 0x20 // External Interrupt Request 2 Enable + GICR_IVSEL = 0x2 // Interrupt Vector Select + GICR_IVCE = 0x1 // Interrupt Vector Change Enable + + // GIFR: General Interrupt Flag Register + GIFR_INTF = 0xc0 // External Interrupt Flags + GIFR_INTF2 = 0x20 // External Interrupt Flag 2 +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0: Timer/Counter Control Register + TCCR0_FOC0 = 0x80 // Force Output Compare + TCCR0_WGM00 = 0x40 // Waveform Generation Mode + TCCR0_COM0 = 0x30 // Compare Match Output Modes + TCCR0_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0_CS0 = 0x7 // Clock Selects +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2: Timer/Counter2 Control Register + TCCR2_FOC2 = 0x80 // Force Output Compare + TCCR2_WGM20 = 0x40 // Pulse Width Modulator Enable + TCCR2_COM2 = 0x30 // Compare Output Mode bits + TCCR2_WGM21 = 0x8 // Clear Timer/Counter2 on Compare Match + TCCR2_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_AS2 = 0x8 // Asynchronous Timer/counter2 + ASSR_TCN2UB = 0x4 // Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // Timer/counter Control Register2 Update Busy +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_FOC1A = 0x8 // Force Output Compare 1A + TCCR1A_FOC1B = 0x4 // Force Output Compare 1B + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects +) + +// Bitfields for USART: USART +const ( + // UCSRA: USART Control and Status Register A + UCSRA_RXC = 0x80 // USART Receive Complete + UCSRA_TXC = 0x40 // USART Transmitt Complete + UCSRA_UDRE = 0x20 // USART Data Register Empty + UCSRA_FE = 0x10 // Framing Error + UCSRA_DOR = 0x8 // Data overRun + UCSRA_UPE = 0x4 // Parity Error + UCSRA_U2X = 0x2 // Double the USART transmission speed + UCSRA_MPCM = 0x1 // Multi-processor Communication Mode + + // UCSRB: USART Control and Status Register B + UCSRB_RXCIE = 0x80 // RX Complete Interrupt Enable + UCSRB_TXCIE = 0x40 // TX Complete Interrupt Enable + UCSRB_UDRIE = 0x20 // USART Data register Empty Interrupt Enable + UCSRB_RXEN = 0x10 // Receiver Enable + UCSRB_TXEN = 0x8 // Transmitter Enable + UCSRB_UCSZ2 = 0x4 // Character Size + UCSRB_RXB8 = 0x2 // Receive Data Bit 8 + UCSRB_TXB8 = 0x1 // Transmit Data Bit 8 + + // UCSRC: USART Control and Status Register C + UCSRC_URSEL = 0x80 // Register Select + UCSRC_UMSEL = 0x40 // USART Mode Select + UCSRC_UPM = 0x30 // Parity Mode Bits + UCSRC_USBS = 0x8 // Stop Bit Select + UCSRC_UCSZ = 0x6 // Character Size + UCSRC_UCPOL = 0x1 // Clock Polarity +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCR: Store Program Memory Control Register + SPMCR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCR_RWWSB = 0x40 // Read While Write Section Busy + SPMCR_RWWSRE = 0x10 // Read While Write secion read enable + SPMCR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCR_PGWRT = 0x4 // Page Write + SPMCR_PGERS = 0x2 // Page Erase + SPMCR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler bits +) diff --git a/src/device/avr/atmega32a.ld b/src/device/avr/atmega32a.ld new file mode 100644 index 00000000..a4ab191f --- /dev/null +++ b/src/device/avr/atmega32a.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega32A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_size = 0x800; +__num_isrs = 21; diff --git a/src/device/avr/atmega32c1.go b/src/device/avr/atmega32c1.go new file mode 100644 index 00000000..c8e7bef1 --- /dev/null +++ b/src/device/avr/atmega32c1.go @@ -0,0 +1,991 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega32C1.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega32c1 + +// Device information for the ATmega32C1. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega32C1" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset + IRQ_ANACOMP0 = 1 // Analog Comparator 0 + IRQ_ANACOMP1 = 2 // Analog Comparator 1 + IRQ_ANACOMP2 = 3 // Analog Comparator 2 + IRQ_ANACOMP3 = 4 // Analog Comparator 3 + IRQ_PSC_FAULT = 5 // PSC Fault + IRQ_PSC_EC = 6 // PSC End of Cycle + IRQ_INT0 = 7 // External Interrupt Request 0 + IRQ_INT1 = 8 // External Interrupt Request 1 + IRQ_INT2 = 9 // External Interrupt Request 2 + IRQ_INT3 = 10 // External Interrupt Request 3 + IRQ_TIMER1_CAPT = 11 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 12 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 13 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 14 // Timer1/Counter1 Overflow + IRQ_TIMER0_COMPA = 15 // Timer/Counter0 Compare Match A + IRQ_TIMER0_COMPB = 16 // Timer/Counter0 Compare Match B + IRQ_TIMER0_OVF = 17 // Timer/Counter0 Overflow + IRQ_CAN_INT = 18 // CAN MOB, Burst, General Errors + IRQ_CAN_TOVF = 19 // CAN Timer Overflow + IRQ_LIN_TC = 20 // LIN Transfer Complete + IRQ_LIN_ERR = 21 // LIN Error + IRQ_PCINT0 = 22 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 23 // Pin Change Interrupt Request 1 + IRQ_PCINT2 = 24 // Pin Change Interrupt Request 2 + IRQ_PCINT3 = 25 // Pin Change Interrupt Request 3 + IRQ_SPI_STC = 26 // SPI Serial Transfer Complete + IRQ_ADC = 27 // ADC Conversion Complete + IRQ_WDT = 28 // Watchdog Time-Out Interrupt + IRQ_EE_READY = 29 // EEPROM Ready + IRQ_SPM_READY = 30 // Store Program Memory Read + IRQ_max = 30 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // I/O Port + PORT = struct { + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + }{ + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Port E Data Register + DDRE: 0x2d, // Port E Data Direction Register + PINE: 0x2c, // Port E Input Pins + } + + // Controller Area Network + CAN = struct { + CANGCON __reg + CANGSTA __reg + CANGIT __reg + CANGIE __reg + CANEN2 __reg + CANEN1 __reg + CANIE2 __reg + CANIE1 __reg + CANSIT2 __reg + CANSIT1 __reg + CANBT1 __reg + CANBT2 __reg + CANBT3 __reg + CANTCON __reg + CANTIML __reg + CANTIMH __reg + CANTTCL __reg + CANTTCH __reg + CANTEC __reg + CANREC __reg + CANHPMOB __reg + CANPAGE __reg + CANSTMOB __reg + CANCDMOB __reg + CANIDT4 __reg + CANIDT3 __reg + CANIDT2 __reg + CANIDT1 __reg + CANIDM4 __reg + CANIDM3 __reg + CANIDM2 __reg + CANIDM1 __reg + CANSTML __reg + CANSTMH __reg + CANMSG __reg + }{ + CANGCON: 0xd8, // CAN General Control Register + CANGSTA: 0xd9, // CAN General Status Register + CANGIT: 0xda, // CAN General Interrupt Register Flags + CANGIE: 0xdb, // CAN General Interrupt Enable Register + CANEN2: 0xdc, // Enable MOb Register 2 + CANEN1: 0xdd, // Enable MOb Register 1(empty) + CANIE2: 0xde, // Enable Interrupt MOb Register 2 + CANIE1: 0xdf, // Enable Interrupt MOb Register 1 (empty) + CANSIT2: 0xe0, // CAN Status Interrupt MOb Register 2 + CANSIT1: 0xe1, // CAN Status Interrupt MOb Register 1 (empty) + CANBT1: 0xe2, // CAN Bit Timing Register 1 + CANBT2: 0xe3, // CAN Bit Timing Register 2 + CANBT3: 0xe4, // CAN Bit Timing Register 3 + CANTCON: 0xe5, // Timer Control Register + CANTIML: 0xe6, // Timer Register + CANTIMH: 0xe6, // Timer Register + CANTTCL: 0xe8, // TTC Timer Register + CANTTCH: 0xe8, // TTC Timer Register + CANTEC: 0xea, // Transmit Error Counter Register + CANREC: 0xeb, // Receive Error Counter Register + CANHPMOB: 0xec, // Highest Priority MOb Register + CANPAGE: 0xed, // Page MOb Register + CANSTMOB: 0xee, // MOb Status Register + CANCDMOB: 0xef, // MOb Control and DLC Register + CANIDT4: 0xf0, // Identifier Tag Register 4 + CANIDT3: 0xf1, // Identifier Tag Register 3 + CANIDT2: 0xf2, // Identifier Tag Register 2 + CANIDT1: 0xf3, // Identifier Tag Register 1 + CANIDM4: 0xf4, // Identifier Mask Register 4 + CANIDM3: 0xf5, // Identifier Mask Register 3 + CANIDM2: 0xf6, // Identifier Mask Register 2 + CANIDM1: 0xf7, // Identifier Mask Register 1 + CANSTML: 0xf8, // Time Stamp Register + CANSTMH: 0xf8, // Time Stamp Register + CANMSG: 0xfa, // Message Data Register + } + + // Analog Comparator + AC = struct { + AC0CON __reg + AC1CON __reg + AC2CON __reg + AC3CON __reg + ACSR __reg + }{ + AC0CON: 0x94, // Analog Comparator 0 Control Register + AC1CON: 0x95, // Analog Comparator 1 Control Register + AC2CON: 0x96, // Analog Comparator 2 Control Register + AC3CON: 0x97, // Analog Comparator 3 Control Register + ACSR: 0x50, // Analog Comparator Status Register + } + + // Digital-to-Analog Converter + DAC = struct { + DACL __reg + DACH __reg + DACON __reg + }{ + DACL: 0x91, // DAC Data Register + DACH: 0x91, // DAC Data Register + DACON: 0x90, // DAC Control Register + } + + // CPU Registers + CPU = struct { + SPMCSR __reg + SREG __reg + SPL __reg + SPH __reg + MCUCR __reg + MCUSR __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PLLCSR __reg + PRR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x3a, // General Purpose IO Register 2 + GPIOR1: 0x39, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PLLCSR: 0x49, // PLL Control And Status Register + PRR: 0x64, // Power Reduction Register + } + + // Timer/Counter, 8-bit + TC8 = struct { + TIMSK0 __reg + TIFR0 __reg + TCCR0A __reg + TCCR0B __reg + TCNT0 __reg + OCR0A __reg + OCR0B __reg + }{ + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + TCCR0A: 0x44, // Timer/Counter Control Register A + TCCR0B: 0x45, // Timer/Counter Control Register B + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + ADCSRB __reg + DIDR0 __reg + DIDR1 __reg + AMP0CSR __reg + AMP1CSR __reg + AMP2CSR __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRB: 0x7b, // ADC Control and Status Register B + DIDR0: 0x7e, // Digital Input Disable Register 0 + DIDR1: 0x7f, // Digital Input Disable Register 0 + AMP0CSR: 0x75, + AMP1CSR: 0x76, + AMP2CSR: 0x77, + } + + // Local Interconnect Network + LINUART = struct { + LINCR __reg + LINSIR __reg + LINENIR __reg + LINERR __reg + LINBTR __reg + LINBRRL __reg + LINBRRH __reg + LINDLR __reg + LINIDR __reg + LINSEL __reg + LINDAT __reg + }{ + LINCR: 0xc8, // LIN Control Register + LINSIR: 0xc9, // LIN Status and Interrupt Register + LINENIR: 0xca, // LIN Enable Interrupt Register + LINERR: 0xcb, // LIN Error Register + LINBTR: 0xcc, // LIN Bit Timing Register + LINBRRL: 0xcd, // LIN Baud Rate Register + LINBRRH: 0xcd, // LIN Baud Rate Register + LINDLR: 0xcf, // LIN Data Length Register + LINIDR: 0xd0, // LIN Identifier Register + LINSEL: 0xd1, // LIN Data Buffer Selection Register + LINDAT: 0xd2, // LIN Data Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCICR __reg + PCMSK3 __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + PCMSK3: 0x6d, // Pin Change Mask Register 3 + PCMSK2: 0x6c, // Pin Change Mask Register 2 + PCMSK1: 0x6b, // Pin Change Mask Register 1 + PCMSK0: 0x6a, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access + EEARH: 0x41, // EEPROM Read/Write Access + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_PSCRB = 0x20 // PSC Reset Behavior + EXTENDED_PSCRVA = 0x10 // PSCOUTnA Reset Value + EXTENDED_PSCRVB = 0x8 // PSC0UTnB Reset Value + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector Trigger Level + + // HIGH + HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PC6 as i/o pin) + HIGH_DWEN = 0x40 // Debug Wire enable + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watch-dog Timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Select Reset Vector + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTD1 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for CAN: Controller Area Network +const ( + // CANGCON: CAN General Control Register + CANGCON_ABRQ = 0x80 // Abort Request + CANGCON_OVRQ = 0x40 // Overload Frame Request + CANGCON_TTC = 0x20 // Time Trigger Communication + CANGCON_SYNTTC = 0x10 // Synchronization of TTC + CANGCON_LISTEN = 0x8 // Listening Mode + CANGCON_TEST = 0x4 // Test Mode + CANGCON_ENASTB = 0x2 // Enable / Standby + CANGCON_SWRES = 0x1 // Software Reset Request + + // CANGSTA: CAN General Status Register + CANGSTA_OVFG = 0x40 // Overload Frame Flag + CANGSTA_TXBSY = 0x10 // Transmitter Busy + CANGSTA_RXBSY = 0x8 // Receiver Busy + CANGSTA_ENFG = 0x4 // Enable Flag + CANGSTA_BOFF = 0x2 // Bus Off Mode + CANGSTA_ERRP = 0x1 // Error Passive Mode + + // CANGIT: CAN General Interrupt Register Flags + CANGIT_CANIT = 0x80 // General Interrupt Flag + CANGIT_BOFFIT = 0x40 // Bus Off Interrupt Flag + CANGIT_OVRTIM = 0x20 // Overrun CAN Timer Flag + CANGIT_BXOK = 0x10 // Burst Receive Interrupt Flag + CANGIT_SERG = 0x8 // Stuff Error General Flag + CANGIT_CERG = 0x4 // CRC Error General Flag + CANGIT_FERG = 0x2 // Form Error General Flag + CANGIT_AERG = 0x1 // Ackknowledgement Error General Flag + + // CANGIE: CAN General Interrupt Enable Register + CANGIE_ENIT = 0x80 // Enable all Interrupts + CANGIE_ENBOFF = 0x40 // Enable Bus Off Interrupt + CANGIE_ENRX = 0x20 // Enable Receive Interrupt + CANGIE_ENTX = 0x10 // Enable Transmitt Interrupt + CANGIE_ENERR = 0x8 // Enable MOb Error Interrupt + CANGIE_ENBX = 0x4 // Enable Burst Receive Interrupt + CANGIE_ENERG = 0x2 // Enable General Error Interrupt + CANGIE_ENOVRT = 0x1 // Enable CAN Timer Overrun Interrupt + + // CANEN2: Enable MOb Register 2 + CANEN2_ENMOB = 0x3f // Enable MObs + + // CANIE2: Enable Interrupt MOb Register 2 + CANIE2_IEMOB = 0x3f // Interrupt Enable MObs + + // CANSIT2: CAN Status Interrupt MOb Register 2 + CANSIT2_SIT = 0x3f // Status of Interrupt MObs + + // CANBT1: CAN Bit Timing Register 1 + CANBT1_BRP = 0x7e // Baud Rate Prescaler bits + + // CANBT2: CAN Bit Timing Register 2 + CANBT2_SJW = 0x60 // Re-Sync Jump Width bits + CANBT2_PRS = 0xe // Propagation Time Segment bits + + // CANBT3: CAN Bit Timing Register 3 + CANBT3_PHS2 = 0x70 // Phase Segment 2 bits + CANBT3_PHS1 = 0xe // Phase Segment 1 bits + CANBT3_SMP = 0x1 // Sample Type + + // CANTCON: Timer Control Register + CANTCON_TPRSC = 0xff // Timer Control bits + + // CANTIML: Timer Register + + // CANTIMH: Timer Register + CANTIM_CANTIM = 0xffff // CAN Timer bits + + // CANTTCL: TTC Timer Register + + // CANTTCH: TTC Timer Register + CANTTC_TIMTTC = 0xffff // TTC Timer Count + + // CANTEC: Transmit Error Counter Register + CANTEC_TEC = 0xff // Transmit Error Counter bits + + // CANREC: Receive Error Counter Register + CANREC_REC = 0xff // Receive Error Counter bits + + // CANHPMOB: Highest Priority MOb Register + CANHPMOB_HPMOB = 0xf0 // Highest Priority MOb Number bits + CANHPMOB_CGP = 0xf // CAN General Purpose bits + + // CANPAGE: Page MOb Register + CANPAGE_MOBNB = 0xf0 // MOb Number bits + CANPAGE_AINC = 0x8 // MOb Data Buffer Auto Increment (Active Low) + CANPAGE_INDX = 0x7 // Data Buffer Index bits + + // CANSTMOB: MOb Status Register + CANSTMOB_DLCW = 0x80 // Data Length Code Warning on MOb + CANSTMOB_TXOK = 0x40 // Transmit OK on MOb + CANSTMOB_RXOK = 0x20 // Receive OK on MOb + CANSTMOB_BERR = 0x10 // Bit Error on MOb + CANSTMOB_SERR = 0x8 // Stuff Error on MOb + CANSTMOB_CERR = 0x4 // CRC Error on MOb + CANSTMOB_FERR = 0x2 // Form Error on MOb + CANSTMOB_AERR = 0x1 // Ackknowledgement Error on MOb + + // CANCDMOB: MOb Control and DLC Register + CANCDMOB_CONMOB = 0xc0 // MOb Config bits + CANCDMOB_RPLV = 0x20 // Reply Valid + CANCDMOB_IDE = 0x10 // Identifier Extension + CANCDMOB_DLC = 0xf // Data Length Code bits + + // CANIDT4: Identifier Tag Register 4 + CANIDT4_IDT = 0xf8 // Identifier Tag + CANIDT4_RTRTAG = 0x4 // Remote Transmission Request Tag + CANIDT4_RB1TAG = 0x2 // Reserved Bit 1 Tag + CANIDT4_RB0TAG = 0x1 // Reserved Bit 0 Tag + + // CANIDT3: Identifier Tag Register 3 + CANIDT3_IDT = 0xff // Identifier Tag + + // CANIDT2: Identifier Tag Register 2 + CANIDT2_IDT = 0xff // Identifier Tag + + // CANIDT1: Identifier Tag Register 1 + CANIDT1_IDT = 0xff // Identifier Tag + + // CANIDM4: Identifier Mask Register 4 + CANIDM4_IDEMSK = 0x1 // Identifier Extension Mask + CANIDM4_RTRMSK = 0x4 // Remote Transmission Request Mask + CANIDM4_IDMSK = 0xf8 // Identifier Mask + + // CANIDM3: Identifier Mask Register 3 + CANIDM3_IDMSK = 0xff // Identifier Mask + + // CANIDM2: Identifier Mask Register 2 + CANIDM2_IDMSK = 0xff // Identifier Mask + + // CANIDM1: Identifier Mask Register 1 + CANIDM1_IDMSK = 0xff // Identifier Mask + + // CANSTML: Time Stamp Register + + // CANSTMH: Time Stamp Register + CANSTM_TIMSTM = 0xffff // TIMSTM + + // CANMSG: Message Data Register + CANMSG_MSG = 0xff // Message Data bits +) + +// Bitfields for AC: Analog Comparator +const ( + // AC0CON: Analog Comparator 0 Control Register + AC0CON_AC0EN = 0x80 // Analog Comparator 0 Enable Bit + AC0CON_AC0IE = 0x40 // Analog Comparator 0 Interrupt Enable Bit + AC0CON_AC0IS = 0x30 // Analog Comparator 0 Interrupt Select Bits + AC0CON_ACCKSEL = 0x8 // Analog Comparator Clock Select + AC0CON_AC0M = 0x7 // Analog Comparator 0 Multiplexer Register + + // AC1CON: Analog Comparator 1 Control Register + AC1CON_AC1EN = 0x80 // Analog Comparator 1 Enable Bit + AC1CON_AC1IE = 0x40 // Analog Comparator 1 Interrupt Enable Bit + AC1CON_AC1IS = 0x30 // Analog Comparator 1 Interrupt Select Bit + AC1CON_AC1ICE = 0x8 // Analog Comparator 1 Interrupt Capture Enable Bit + AC1CON_AC1M = 0x7 // Analog Comparator 1 Multiplexer Register + + // AC2CON: Analog Comparator 2 Control Register + AC2CON_AC2EN = 0x80 // Analog Comparator 2 Enable Bit + AC2CON_AC2IE = 0x40 // Analog Comparator 2 Interrupt Enable Bit + AC2CON_AC2IS = 0x30 // Analog Comparator 2 Interrupt Select Bit + AC2CON_AC2M = 0x7 // Analog Comparator 2 Multiplexer Register + + // AC3CON: Analog Comparator 3 Control Register + AC3CON_AC3EN = 0x80 // Analog Comparator 3 Enable Bit + AC3CON_AC3IE = 0x40 // Analog Comparator 3 Interrupt Enable Bit + AC3CON_AC3IS = 0x30 // Analog Comparator 3 Interrupt Select Bit + AC3CON_AC3M = 0x7 // Analog Comparator 3 Multiplexer Register + + // ACSR: Analog Comparator Status Register + ACSR_AC3IF = 0x80 // Analog Comparator 3 Interrupt Flag Bit + ACSR_AC2IF = 0x40 // Analog Comparator 2 Interrupt Flag Bit + ACSR_AC1IF = 0x20 // Analog Comparator 1 Interrupt Flag Bit + ACSR_AC0IF = 0x10 // Analog Comparator 0 Interrupt Flag Bit + ACSR_AC3O = 0x8 // Analog Comparator 3 Output Bit + ACSR_AC2O = 0x4 // Analog Comparator 2 Output Bit + ACSR_AC1O = 0x2 // Analog Comparator 1 Output Bit + ACSR_AC0O = 0x1 // Analog Comparator 0 Output Bit +) + +// Bitfields for DAC: Digital-to-Analog Converter +const ( + // DACL: DAC Data Register + + // DACH: DAC Data Register + DAC_DACH = 0xff00 // DAC Data Register High Byte Bits + DAC_DACL = 0xff // DAC Data Register Low Byte Bits + + // DACON: DAC Control Register + DACON_DAATE = 0x80 // DAC Auto Trigger Enable Bit + DACON_DATS = 0x70 // DAC Trigger Selection Bits + DACON_DALA = 0x4 // DAC Left Adjust + DACON_DAOE = 0x2 // DAC Output Enable + DACON_DAEN = 0x1 // DAC Enable Bit +) + +// Bitfields for CPU: CPU Registers +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable + + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // MCUCR: MCU Control Register + MCUCR_SPIPS = 0x80 // SPI Pin Select + MCUCR_PUD = 0x10 // Pull-up disable + MCUCR_IVSEL = 0x2 // Interrupt Vector Select + MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable + + // MCUSR: MCU Status Register + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BORF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 + + // PLLCSR: PLL Control And Status Register + PLLCSR_PLLF = 0x4 // PLL Factor + PLLCSR_PLLE = 0x2 // PLL Enable + PLLCSR_PLOCK = 0x1 // PLL Lock Detector + + // PRR: Power Reduction Register + PRR_PRCAN = 0x40 // Power Reduction CAN + PRR_PRPSC = 0x20 // Power Reduction PSC + PRR_PRTIM1 = 0x10 // Power Reduction Timer/Counter1 + PRR_PRTIM0 = 0x8 // Power Reduction Timer/Counter0 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRLIN = 0x2 // Power Reduction LIN UART + PRR_PRADC = 0x1 // Power Reduction ADC +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCNT0: Timer/Counter0 + TCNT0_TCNT0 = 0xff // Timer/Counter0 bits + + // OCR0A: Timer/Counter0 Output Compare Register + OCR0A_OCR0A = 0xff // Timer/Counter0 Output Compare bits + + // OCR0B: Timer/Counter0 Output Compare Register + OCR0B_OCR0B = 0xff // Timer/Counter0 Output Compare bits +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TIMSK1: Timer/Counter Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output CompareB Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output CompareA Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 + TCCR1C_FOC1B = 0x40 + + // TCNT1L: Timer/Counter1 Bytes + + // TCNT1H: Timer/Counter1 Bytes + TCNT1_TCNT1 = 0xffff // Timer/Counter1 bits + + // OCR1AL: Timer/Counter1 Output Compare Register Bytes + + // OCR1AH: Timer/Counter1 Output Compare Register Bytes + OCR1A_OCR1A = 0xffff // Timer/Counter1 Output Compare bits + + // OCR1BL: Timer/Counter1 Output Compare Register Bytes + + // OCR1BH: Timer/Counter1 Output Compare Register Bytes + OCR1B_OCR1B = 0xffff // Timer/Counter1 Output Compare bits + + // ICR1L: Timer/Counter1 Input Capture Register Bytes + + // ICR1H: Timer/Counter1 Input Capture Register Bytes + ICR1_ICR1 = 0xffff // Timer/Counter1 Input Capture bits +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCL: ADC Data Register Bytes + + // ADCH: ADC Data Register Bytes + ADC_ADC = 0x3ff // ADC Data bits + + // ADCSRB: ADC Control and Status Register B + ADCSRB_ADHSM = 0x80 // ADC High Speed Mode + ADCSRB_ISRCEN = 0x40 // Current Source Enable + ADCSRB_AREFEN = 0x20 // Analog Reference pin Enable + ADCSRB_ADTS = 0xf // ADC Auto Trigger Sources + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable + + // DIDR1: Digital Input Disable Register 0 + DIDR1_AMP2PD = 0x40 // AMP2P Pin Digital input Disable + DIDR1_ACMP0D = 0x20 // ACMP0 Pin Digital input Disable + DIDR1_AMP0PD = 0x10 // AMP0P Pin Digital input Disable + DIDR1_AMP0ND = 0x8 // AMP0N Pin Digital input Disable + DIDR1_ADC10D = 0x4 // ADC10 Pin Digital input Disable + DIDR1_ADC9D = 0x2 // ADC9 Pin Digital input Disable + DIDR1_ADC8D = 0x1 // ADC8 Pin Digital input Disable + + // AMP0CSR + AMP0CSR_AMP0EN = 0x80 + AMP0CSR_AMP0IS = 0x40 + AMP0CSR_AMP0G = 0x30 + AMP0CSR_AMPCMP0 = 0x8 // Amplifier 0 - Comparator 0 Connection + AMP0CSR_AMP0TS = 0x7 + + // AMP1CSR + AMP1CSR_AMP1EN = 0x80 + AMP1CSR_AMP1IS = 0x40 + AMP1CSR_AMP1G = 0x30 + AMP1CSR_AMPCMP1 = 0x8 // Amplifier 1 - Comparator 1 Connection + AMP1CSR_AMP1TS = 0x7 + + // AMP2CSR + AMP2CSR_AMP2EN = 0x80 + AMP2CSR_AMP2IS = 0x40 + AMP2CSR_AMP2G = 0x30 + AMP2CSR_AMPCMP2 = 0x8 // Amplifier 2 - Comparator 2 Connection + AMP2CSR_AMP2TS = 0x7 +) + +// Bitfields for LINUART: Local Interconnect Network +const ( + // LINCR: LIN Control Register + LINCR_LSWRES = 0x80 // Software Reset + LINCR_LIN13 = 0x40 // LIN Standard + LINCR_LCONF = 0x30 // LIN Configuration bits + LINCR_LENA = 0x8 // LIN or UART Enable + LINCR_LCMD = 0x7 // LIN Command and Mode bits + + // LINSIR: LIN Status and Interrupt Register + LINSIR_LIDST = 0xe0 // Identifier Status bits + LINSIR_LBUSY = 0x10 // Busy Signal + LINSIR_LERR = 0x8 // Error Interrupt + LINSIR_LIDOK = 0x4 // Identifier Interrupt + LINSIR_LTXOK = 0x2 // Transmit Performed Interrupt + LINSIR_LRXOK = 0x1 // Receive Performed Interrupt + + // LINENIR: LIN Enable Interrupt Register + LINENIR_LENERR = 0x8 // Enable Error Interrupt + LINENIR_LENIDOK = 0x4 // Enable Identifier Interrupt + LINENIR_LENTXOK = 0x2 // Enable Transmit Performed Interrupt + LINENIR_LENRXOK = 0x1 // Enable Receive Performed Interrupt + + // LINERR: LIN Error Register + LINERR_LABORT = 0x80 // Abort Flag + LINERR_LTOERR = 0x40 // Frame Time Out Error Flag + LINERR_LOVERR = 0x20 // Overrun Error Flag + LINERR_LFERR = 0x10 // Framing Error Flag + LINERR_LSERR = 0x8 // Synchronization Error Flag + LINERR_LPERR = 0x4 // Parity Error Flag + LINERR_LCERR = 0x2 // Checksum Error Flag + LINERR_LBERR = 0x1 // Bit Error Flag + + // LINBTR: LIN Bit Timing Register + LINBTR_LDISR = 0x80 // Disable Bit Timing Resynchronization + LINBTR_LBT = 0x3f // LIN Bit Timing bits + + // LINBRRL: LIN Baud Rate Register + + // LINBRRH: LIN Baud Rate Register + LINBRR_LDIV = 0xfff + + // LINDLR: LIN Data Length Register + LINDLR_LTXDL = 0xf0 // LIN Transmit Data Length bits + LINDLR_LRXDL = 0xf // LIN Receive Data Length bits + + // LINIDR: LIN Identifier Register + LINIDR_LP = 0xc0 // Parity bits + LINIDR_LID = 0x3f // Identifier bit 5 or Data Length bits + + // LINSEL: LIN Data Buffer Selection Register + LINSEL_LAINC = 0x8 // Auto Increment of Data Buffer Index (Active Low) + LINSEL_LINDX = 0x7 // FIFO LIN Data Buffer Index bits + + // LINDAT: LIN Data Register + LINDAT_LDATA = 0xff +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPDR: SPI Data Register + SPDR_SPDR = 0xff // SPI Data bits +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register + EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control 1 Bits + EICRA_ISC0 = 0x3 // External Interrupt Sense Control 0 Bits + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xf // External Interrupt Request 3 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xf // External Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0xf // Pin Change Interrupt Enables + + // PCMSK3: Pin Change Mask Register 3 + PCMSK3_PCINT = 0x7 // Pin Change Enable Masks + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0xf // Pin Change Interrupt Flags +) + +// Bitfields for EEPROM: EEPROM +const ( + // EEARL: EEPROM Read/Write Access + + // EEARH: EEPROM Read/Write Access + EEAR_EEAR = 0x3ff // EEPROM Address bits + + // EEDR: EEPROM Data Register + EEDR_EEDR = 0xff // EEPROM Data bits + + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming mode + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) diff --git a/src/device/avr/atmega32c1.ld b/src/device/avr/atmega32c1.ld new file mode 100644 index 00000000..20e2f655 --- /dev/null +++ b/src/device/avr/atmega32c1.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega32C1.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_size = 0x800; +__num_isrs = 31; diff --git a/src/device/avr/atmega32hvb.go b/src/device/avr/atmega32hvb.go new file mode 100644 index 00000000..d6ccfa10 --- /dev/null +++ b/src/device/avr/atmega32hvb.go @@ -0,0 +1,796 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega32HVB.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega32hvb + +// Device information for the ATmega32HVB. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega32HVB" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset + IRQ_BPINT = 1 // Battery Protection Interrupt + IRQ_VREGMON = 2 // Voltage regulator monitor interrupt + IRQ_INT0 = 3 // External Interrupt Request 0 + IRQ_INT1 = 4 // External Interrupt Request 1 + IRQ_INT2 = 5 // External Interrupt Request 2 + IRQ_INT3 = 6 // External Interrupt Request 3 + IRQ_PCINT0 = 7 // Pin Change Interrupt 0 + IRQ_PCINT1 = 8 // Pin Change Interrupt 1 + IRQ_WDT = 9 // Watchdog Timeout Interrupt + IRQ_BGSCD = 10 // Bandgap Buffer Short Circuit Detected + IRQ_CHDET = 11 // Charger Detect + IRQ_TIMER1_IC = 12 // Timer 1 Input capture + IRQ_TIMER1_COMPA = 13 // Timer 1 Compare Match A + IRQ_TIMER1_COMPB = 14 // Timer 1 Compare Match B + IRQ_TIMER1_OVF = 15 // Timer 1 overflow + IRQ_TIMER0_IC = 16 // Timer 0 Input Capture + IRQ_TIMER0_COMPA = 17 // Timer 0 Comapre Match A + IRQ_TIMER0_COMPB = 18 // Timer 0 Compare Match B + IRQ_TIMER0_OVF = 19 // Timer 0 Overflow + IRQ_TWIBUSCD = 20 // Two-Wire Bus Connect/Disconnect + IRQ_TWI = 21 // Two-Wire Serial Interface + IRQ_SPI_STC = 22 // SPI Serial transfer complete + IRQ_VADC = 23 // Voltage ADC Conversion Complete + IRQ_CCADC_CONV = 24 // Coulomb Counter ADC Conversion Complete + IRQ_CCADC_REG_CUR = 25 // Coloumb Counter ADC Regular Current + IRQ_CCADC_ACC = 26 // Coloumb Counter ADC Accumulator + IRQ_EE_READY = 27 // EEPROM Ready + IRQ_SPM = 28 // SPM Ready + IRQ_max = 28 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + LOW __reg + HIGH __reg + }{ + LOW: 0x0, + HIGH: 0x1, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog-to-Digital Converter + ADC = struct { + VADMUX __reg + VADCL __reg + VADCH __reg + VADCSR __reg + }{ + VADMUX: 0x7c, // The VADC multiplexer Selection Register + VADCL: 0x78, // VADC Data Register Bytes + VADCH: 0x78, // VADC Data Register Bytes + VADCSR: 0x7a, // The VADC Control and Status register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // FET Control + FET = struct { + FCSR __reg + }{ + FCSR: 0xf0, // FET Control and Status Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access + EEARH: 0x41, // EEPROM Read/Write Access + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Coulomb Counter + COULOMB_COUNTER = struct { + CADCSRA __reg + CADCSRB __reg + CADCSRC __reg + CADICL __reg + CADICH __reg + CADAC3 __reg + CADAC2 __reg + CADAC1 __reg + CADAC0 __reg + CADRCC __reg + CADRDC __reg + }{ + CADCSRA: 0xe6, // CC-ADC Control and Status Register A + CADCSRB: 0xe7, // CC-ADC Control and Status Register B + CADCSRC: 0xe8, // CC-ADC Control and Status Register C + CADICL: 0xe4, // CC-ADC Instantaneous Current + CADICH: 0xe4, // CC-ADC Instantaneous Current + CADAC3: 0xe3, // ADC Accumulate Current + CADAC2: 0xe2, // ADC Accumulate Current + CADAC1: 0xe1, // ADC Accumulate Current + CADAC0: 0xe0, // ADC Accumulate Current + CADRCC: 0xe9, // CC-ADC Regular Charge Current + CADRDC: 0xea, // CC-ADC Regular Discharge Current + } + + // Two Wire Serial Interface + TWI = struct { + TWBCSR __reg + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWBCSR: 0xbe, // TWI Bus Control and Status Register + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCICR __reg + PCIFR __reg + PCMSK1 __reg + PCMSK0 __reg + }{ + EICRA: 0x69, // External Interrupt Control Register + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + PCMSK1: 0x6c, // Pin Change Enable Mask Register 1 + PCMSK0: 0x6b, // Pin Change Enable Mask Register 0 + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1B __reg + TCCR1A __reg + TCNT1L __reg + TCNT1H __reg + OCR1A __reg + OCR1B __reg + TIMSK1 __reg + TIFR1 __reg + TCCR0B __reg + TCCR0A __reg + TCNT0L __reg + TCNT0H __reg + OCR0A __reg + OCR0B __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1A: 0x80, // Timer/Counter 1 Control Register A + TCNT1L: 0x84, // Timer Counter 1 Bytes + TCNT1H: 0x84, // Timer Counter 1 Bytes + OCR1A: 0x88, // Output Compare Register 1A + OCR1B: 0x89, // Output Compare Register B + TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR0B: 0x45, // Timer/Counter0 Control Register B + TCCR0A: 0x44, // Timer/Counter 0 Control Register A + TCNT0L: 0x46, // Timer Counter 0 Bytes + TCNT0H: 0x46, // Timer Counter 0 Bytes + OCR0A: 0x48, // Output Compare Register A + OCR0B: 0x49, // Output Compare Register B + TIMSK0: 0x6e, // Timer/Counter Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter Interrupt Flag register + } + + // Cell Balancing + CELL_BALANCING = struct { + CBCR __reg + }{ + CBCR: 0xf1, // Cell Balancing Control Register + } + + // Battery Protection + BATTERY_PROTECTION = struct { + BPPLR __reg + BPCR __reg + BPHCTR __reg + BPOCTR __reg + BPSCTR __reg + BPCHCD __reg + BPDHCD __reg + BPCOCD __reg + BPDOCD __reg + BPSCD __reg + BPIFR __reg + BPIMSK __reg + }{ + BPPLR: 0xfe, // Battery Protection Parameter Lock Register + BPCR: 0xfd, // Battery Protection Control Register + BPHCTR: 0xfc, // Battery Protection Short-current Timing Register + BPOCTR: 0xfb, // Battery Protection Over-current Timing Register + BPSCTR: 0xfa, // Battery Protection Short-current Timing Register + BPCHCD: 0xf9, // Battery Protection Charge-High-current Detection Level Register + BPDHCD: 0xf8, // Battery Protection Discharge-High-current Detection Level Register + BPCOCD: 0xf7, // Battery Protection Charge-Over-current Detection Level Register + BPDOCD: 0xf6, // Battery Protection Discharge-Over-current Detection Level Register + BPSCD: 0xf5, // Battery Protection Short-Circuit Detection Level Register + BPIFR: 0xf3, // Battery Protection Interrupt Flag Register + BPIMSK: 0xf2, // Battery Protection Interrupt Mask Register + } + + // Charger Detect + CHARGER_DETECT = struct { + CHGDCSR __reg + }{ + CHGDCSR: 0xd4, // Charger Detect Control and Status Register + } + + // Voltage Regulator + VOLTAGE_REGULATOR = struct { + ROCR __reg + }{ + ROCR: 0xc8, // Regulator Operating Condition Register + } + + // Bandgap + BANDGAP = struct { + BGCSR __reg + BGCRR __reg + BGCCR __reg + }{ + BGCSR: 0xd2, // Bandgap Control and Status Register + BGCRR: 0xd1, // Bandgap Calibration of Resistor Ladder + BGCCR: 0xd0, // Bandgap Calibration Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + MCUCR __reg + MCUSR __reg + FOSCCAL __reg + OSICSR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + DIDR0 __reg + PRR0 __reg + CLKPR __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + FOSCCAL: 0x66, // Fast Oscillator Calibration Value + OSICSR: 0x37, // Oscillator Sampling Interface Control and Status Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + DIDR0: 0x7e, // Digital Input Disable Register + PRR0: 0x64, // Power Reduction Register 0 + CLKPR: 0x61, // Clock Prescale Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + PINC __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + PINC: 0x26, // Port C Input Pins + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control and Status Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // LOW + LOW_WDTON = 0x80 // Watch-dog Timer always on + LOW_EESAVE = 0x40 // Preserve EEPROM through the Chip Erase cycle + LOW_SPIEN = 0x20 // Serial program downloading (SPI) enabled + LOW_SUT = 0x1c // Select start-up time + LOW_OSCSEL = 0x3 // Oscillator select + + // HIGH + HIGH_CKDIV8 = 0x10 // Clock Divide mode + HIGH_DWEN = 0x8 // Debug Wire enable + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // VADMUX: The VADC multiplexer Selection Register + VADMUX_VADMUX = 0xf // Analog Channel and Gain Selection Bits + + // VADCL: VADC Data Register Bytes + + // VADCH: VADC Data Register Bytes + VADC_VADC = 0xfff // VADC Data bits + + // VADCSR: The VADC Control and Status register + VADCSR_VADEN = 0x8 // VADC Enable + VADCSR_VADSC = 0x4 // VADC Satrt Conversion + VADCSR_VADCCIF = 0x2 // VADC Conversion Complete Interrupt Flag + VADCSR_VADCCIE = 0x1 // VADC Conversion Complete Interrupt Enable +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for FET: FET Control +const ( + // FCSR: FET Control and Status Register + FCSR_DUVRD = 0x8 // Deep Under-Voltage Recovery Disable + FCSR_CPS = 0x4 // Current Protection Status + FCSR_DFE = 0x2 // Discharge FET Enable + FCSR_CFE = 0x1 // Charge FET Enable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPDR: SPI Data Register + SPDR_SPDR = 0xff // SPI Data bits +) + +// Bitfields for EEPROM: EEPROM +const ( + // EEARL: EEPROM Read/Write Access + + // EEARH: EEPROM Read/Write Access + EEAR_EEAR = 0x3ff // EEPROM Address bits + + // EEDR: EEPROM Data Register + EEDR_EEDR = 0xff // EEPROM Data bits + + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 + EECR_EERIE = 0x8 // EEProm Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for COULOMB_COUNTER: Coulomb Counter +const ( + // CADCSRA: CC-ADC Control and Status Register A + CADCSRA_CADEN = 0x80 // When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled. + CADCSRA_CADPOL = 0x40 + CADCSRA_CADUB = 0x20 // CC_ADC Update Busy + CADCSRA_CADAS = 0x18 // CC_ADC Accumulate Current Select Bits + CADCSRA_CADSI = 0x6 // The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. + CADCSRA_CADSE = 0x1 // When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode. + + // CADCSRB: CC-ADC Control and Status Register B + CADCSRB_CADACIE = 0x40 + CADCSRB_CADRCIE = 0x20 // Regular Current Interrupt Enable + CADCSRB_CADICIE = 0x10 // CAD Instantenous Current Interrupt Enable + CADCSRB_CADACIF = 0x4 // CC-ADC Accumulate Current Interrupt Flag + CADCSRB_CADRCIF = 0x2 // CC-ADC Accumulate Current Interrupt Flag + CADCSRB_CADICIF = 0x1 // CC-ADC Instantaneous Current Interrupt Flag + + // CADCSRC: CC-ADC Control and Status Register C + CADCSRC_CADVSE = 0x1 // CC-ADC Voltage Scaling Enable + + // CADICL: CC-ADC Instantaneous Current + + // CADICH: CC-ADC Instantaneous Current + CADIC_CADIC = 0xffff // CC-ADC Instantaneous Current + + // CADAC3: ADC Accumulate Current + CADAC3_CADAC = 0xff // ADC accumulate current bits + + // CADAC2: ADC Accumulate Current + CADAC2_CADAC = 0xff // ADC accumulate current bits + + // CADAC1: ADC Accumulate Current + CADAC1_CADAC = 0xfc // ADC accumulate current bits + CADAC1_CADAC0 = 0x3 // ADC accumulate current bits + + // CADAC0: ADC Accumulate Current + CADAC0_CADAC0 = 0xff // ADC accumulate current bits + + // CADRCC: CC-ADC Regular Charge Current + CADRCC_CADRCC = 0xff // CC-ADC Regular Charge Current + + // CADRDC: CC-ADC Regular Discharge Current + CADRDC_CADRDC = 0xff // CC-ADC Regular Discharge Current +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWBCSR: TWI Bus Control and Status Register + TWBCSR_TWBCIF = 0x80 // TWI Bus Connect/Disconnect Interrupt Flag + TWBCSR_TWBCIE = 0x40 // TWI Bus Connect/Disconnect Interrupt Enable + TWBCSR_TWBDT = 0x6 // TWI Bus Disconnect Time-out Period + TWBCSR_TWBCIP = 0x1 // TWI Bus Connect/Disconnect Interrupt Polarity + + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWBR: TWI Bit Rate register + TWBR_TWBR = 0xff // TWI Bit Rate bits + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWDR: TWI Data register + TWDR_TWD = 0xff // TWI Data Bits + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register + EICRA_ISC3 = 0xc0 // External Interrupt Sense Control 3 Bits + EICRA_ISC2 = 0x30 // External Interrupt Sense Control 2 Bits + EICRA_ISC1 = 0xc // External Interrupt Sense Control 1 Bits + EICRA_ISC0 = 0x3 // External Interrupt Sense Control 0 Bits + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xf // External Interrupt Request 3 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xf // External Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0x3 // Pin Change Interrupt Enables + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0x3 // Pin Change Interrupt Flags + + // PCMSK1: Pin Change Enable Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Enable Mask + + // PCMSK0: Pin Change Enable Mask Register 0 + PCMSK0_PCINT = 0xf // Pin Change Enable Mask +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_CS = 0x7 // Clock Select1 bis + + // TCCR1A: Timer/Counter 1 Control Register A + TCCR1A_TCW1 = 0x80 // Timer/Counter Width + TCCR1A_ICEN1 = 0x40 // Input Capture Mode Enable + TCCR1A_ICNC1 = 0x20 // Input Capture Noise Canceler + TCCR1A_ICES1 = 0x10 // Input Capture Edge Select + TCCR1A_ICS1 = 0x8 // Input Capture Select + TCCR1A_WGM10 = 0x1 // Waveform Generation Mode + + // TCNT1L: Timer Counter 1 Bytes + + // TCNT1H: Timer Counter 1 Bytes + TCNT1_TCNT1 = 0xffff // Timer Counter 1 bits + + // OCR1A: Output Compare Register 1A + OCR1A_OCR1A = 0xff // Output Compare 1 A bits + + // OCR1B: Output Compare Register B + OCR1B_OCR1B = 0xff // Output Compare 1 B bits + + // TIMSK1: Timer/Counter Interrupt Mask Register + TIMSK1_ICIE1 = 0x8 // Timer/Counter n Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x8 // Timer/Counter 1 Input Capture Flag + TIFR1_OCF1B = 0x4 // Timer/Counter1 Output Compare Flag B + TIFR1_OCF1A = 0x2 // Timer/Counter1 Output Compare Flag A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR0B: Timer/Counter0 Control Register B + TCCR0B_CS02 = 0x4 // Clock Select0 bit 2 + TCCR0B_CS01 = 0x2 // Clock Select0 bit 1 + TCCR0B_CS00 = 0x1 // Clock Select0 bit 0 + + // TCCR0A: Timer/Counter 0 Control Register A + TCCR0A_TCW0 = 0x80 // Timer/Counter Width + TCCR0A_ICEN0 = 0x40 // Input Capture Mode Enable + TCCR0A_ICNC0 = 0x20 // Input Capture Noise Canceler + TCCR0A_ICES0 = 0x10 // Input Capture Edge Select + TCCR0A_ICS0 = 0x8 // Input Capture Select + TCCR0A_WGM00 = 0x1 // Waveform Generation Mode + + // TCNT0L: Timer Counter 0 Bytes + + // TCNT0H: Timer Counter 0 Bytes + TCNT0_TCNT0 = 0xffff // Timer Counter 0 bits + + // OCR0A: Output Compare Register A + OCR0A_OCR0A = 0xff // Output Compare 0 A bits + + // OCR0B: Output Compare Register B + OCR0B_OCR0B = 0xff // Output Compare 0 B bits + + // TIMSK0: Timer/Counter Interrupt Mask Register + TIMSK0_ICIE0 = 0x8 // Timer/Counter n Input Capture Interrupt Enable + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter Interrupt Flag register + TIFR0_ICF0 = 0x8 // Timer/Counter 0 Input Capture Flag + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for CELL_BALANCING: Cell Balancing +const ( + // CBCR: Cell Balancing Control Register + CBCR_CBE = 0xf // Cell Balancing Enables +) + +// Bitfields for BATTERY_PROTECTION: Battery Protection +const ( + // BPPLR: Battery Protection Parameter Lock Register + BPPLR_BPPLE = 0x2 // Battery Protection Parameter Lock Enable + BPPLR_BPPL = 0x1 // Battery Protection Parameter Lock + + // BPCR: Battery Protection Control Register + BPCR_EPID = 0x20 // External Protection Input Disable + BPCR_SCD = 0x10 // Short Circuit Protection Disabled + BPCR_DOCD = 0x8 // Discharge Over-current Protection Disabled + BPCR_COCD = 0x4 // Charge Over-current Protection Disabled + BPCR_DHCD = 0x2 // Discharge High-current Protection Disable + BPCR_CHCD = 0x1 // Charge High-current Protection Disable + + // BPHCTR: Battery Protection Short-current Timing Register + BPHCTR_HCPT = 0x3f // Battery Protection Short-current Timing bits + + // BPOCTR: Battery Protection Over-current Timing Register + BPOCTR_OCPT = 0x3f // Battery Protection Over-current Timing bits + + // BPSCTR: Battery Protection Short-current Timing Register + BPSCTR_SCPT = 0x7f // Battery Protection Short-current Timing bits + + // BPCHCD: Battery Protection Charge-High-current Detection Level Register + BPCHCD_CHCDL = 0xff // Battery Protection Charge-High-current Detection Level bits + + // BPDHCD: Battery Protection Discharge-High-current Detection Level Register + BPDHCD_DHCDL = 0xff // Battery Protection Discharge-High-current Detection Level bits + + // BPCOCD: Battery Protection Charge-Over-current Detection Level Register + BPCOCD_COCDL = 0xff // Battery Protection Charge-Over-current Detection Level bits + + // BPDOCD: Battery Protection Discharge-Over-current Detection Level Register + BPDOCD_DOCDL = 0xff // Battery Protection Discharge-Over-current Detection Level bits + + // BPSCD: Battery Protection Short-Circuit Detection Level Register + BPSCD_SCDL = 0xff // Battery Protection Short-Circuit Detection Level Register bits + + // BPIFR: Battery Protection Interrupt Flag Register + BPIFR_SCIF = 0x10 // Short-circuit Protection Activated Interrupt Flag + BPIFR_DOCIF = 0x8 // Discharge Over-current Protection Activated Interrupt Flag + BPIFR_COCIF = 0x4 // Charge Over-current Protection Activated Interrupt Flag + BPIFR_DHCIF = 0x2 // Disharge High-current Protection Activated Interrupt + BPIFR_CHCIF = 0x1 // Charge High-current Protection Activated Interrupt + + // BPIMSK: Battery Protection Interrupt Mask Register + BPIMSK_SCIE = 0x10 // Short-circuit Protection Activated Interrupt Enable + BPIMSK_DOCIE = 0x8 // Discharge Over-current Protection Activated Interrupt Enable + BPIMSK_COCIE = 0x4 // Charge Over-current Protection Activated Interrupt Enable + BPIMSK_DHCIE = 0x2 // Discharger High-current Protection Activated Interrupt + BPIMSK_CHCIE = 0x1 // Charger High-current Protection Activated Interrupt +) + +// Bitfields for CHARGER_DETECT: Charger Detect +const ( + // CHGDCSR: Charger Detect Control and Status Register + CHGDCSR_BATTPVL = 0x10 // BATT Pin Voltage Level + CHGDCSR_CHGDISC = 0xc // Charger Detect Interrupt Sense Control + CHGDCSR_CHGDIF = 0x2 // Charger Detect Interrupt Flag + CHGDCSR_CHGDIE = 0x1 // Charger Detect Interrupt Enable +) + +// Bitfields for VOLTAGE_REGULATOR: Voltage Regulator +const ( + // ROCR: Regulator Operating Condition Register + ROCR_ROCS = 0x80 // ROC Status + ROCR_ROCD = 0x10 // ROC Disable + ROCR_ROCWIF = 0x2 // ROC Warning Interrupt Flag + ROCR_ROCWIE = 0x1 // ROC Warning Interrupt Enable +) + +// Bitfields for BANDGAP: Bandgap +const ( + // BGCSR: Bandgap Control and Status Register + BGCSR_BGD = 0x20 // Bandgap Disable + BGCSR_BGSCDE = 0x10 // Bandgap Short Circuit Detection Enabled + BGCSR_BGSCDIF = 0x2 // Bandgap Short Circuit Detection Interrupt Flag + BGCSR_BGSCDIE = 0x1 // Bandgap Short Circuit Detection Interrupt Enable + + // BGCRR: Bandgap Calibration of Resistor Ladder + BGCRR_BGCR = 0xff // Bandgap Calibration of Resistor Ladder Bits + + // BGCCR: Bandgap Calibration Register + BGCCR_BGCC = 0x3f // BG Calibration of PTAT Current Bits +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // MCUCR: MCU Control Register + MCUCR_CKOE = 0x20 // Clock Output Enable + MCUCR_PUD = 0x10 // Pull-up disable + MCUCR_IVSEL = 0x2 // Interrupt Vector Select + MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable + + // MCUSR: MCU Status Register + MCUSR_OCDRF = 0x10 // OCD Reset Flag + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BODRF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // FOSCCAL: Fast Oscillator Calibration Value + FOSCCAL_FCAL = 0xff // Fast Oscillator Calibration Value + + // OSICSR: Oscillator Sampling Interface Control and Status Register + OSICSR_OSISEL0 = 0x10 // Oscillator Sampling Interface Select 0 + OSICSR_OSIST = 0x2 // Oscillator Sampling Interface Status + OSICSR_OSIEN = 0x1 // Oscillator Sampling Interface Enable + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR2 = 0xff // General Purpose IO bits + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR1 = 0xff // General Purpose IO bits + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR0 = 0xff // General Purpose IO bits + + // DIDR0: Digital Input Disable Register + DIDR0_PA1DID = 0x2 // When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled. + DIDR0_PA0DID = 0x1 // When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled. + + // PRR0: Power Reduction Register 0 + PRR0_PRTWI = 0x40 // Power Reduction TWI + PRR0_PRVRM = 0x20 // Power Reduction Voltage Regulator Monitor + PRR0_PRSPI = 0x8 // Power reduction SPI + PRR0_PRTIM1 = 0x4 // Power Reduction Timer/Counter1 + PRR0_PRTIM0 = 0x2 // Power Reduction Timer/Counter0 + PRR0_PRVADC = 0x1 // Power Reduction V-ADC + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0x3 // Clock Prescaler Select Bits +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control and Status Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read-While-Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read-While-Write Section Read Enable + SPMCSR_LBSET = 0x8 // Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) diff --git a/src/device/avr/atmega32hvb.ld b/src/device/avr/atmega32hvb.ld new file mode 100644 index 00000000..174d7129 --- /dev/null +++ b/src/device/avr/atmega32hvb.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega32HVB.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_size = 0x800; +__num_isrs = 29; diff --git a/src/device/avr/atmega32hvbrevb.go b/src/device/avr/atmega32hvbrevb.go new file mode 100644 index 00000000..b49af713 --- /dev/null +++ b/src/device/avr/atmega32hvbrevb.go @@ -0,0 +1,683 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega32HVBrevB.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega32hvbrevb + +// Device information for the ATmega32HVBrevB. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega32HVBrevB" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset + IRQ_BPINT = 1 // Battery Protection Interrupt + IRQ_VREGMON = 2 // Voltage regulator monitor interrupt + IRQ_INT0 = 3 // External Interrupt Request 0 + IRQ_INT1 = 4 // External Interrupt Request 1 + IRQ_INT2 = 5 // External Interrupt Request 2 + IRQ_INT3 = 6 // External Interrupt Request 3 + IRQ_PCINT0 = 7 // Pin Change Interrupt 0 + IRQ_PCINT1 = 8 // Pin Change Interrupt 1 + IRQ_WDT = 9 // Watchdog Timeout Interrupt + IRQ_BGSCD = 10 // Bandgap Buffer Short Circuit Detected + IRQ_CHDET = 11 // Charger Detect + IRQ_TIMER1_IC = 12 // Timer 1 Input capture + IRQ_TIMER1_COMPA = 13 // Timer 1 Compare Match A + IRQ_TIMER1_COMPB = 14 // Timer 1 Compare Match B + IRQ_TIMER1_OVF = 15 // Timer 1 overflow + IRQ_TIMER0_IC = 16 // Timer 0 Input Capture + IRQ_TIMER0_COMPA = 17 // Timer 0 Comapre Match A + IRQ_TIMER0_COMPB = 18 // Timer 0 Compare Match B + IRQ_TIMER0_OVF = 19 // Timer 0 Overflow + IRQ_TWIBUSCD = 20 // Two-Wire Bus Connect/Disconnect + IRQ_TWI = 21 // Two-Wire Serial Interface + IRQ_SPI_STC = 22 // SPI Serial transfer complete + IRQ_VADC = 23 // Voltage ADC Conversion Complete + IRQ_CCADC_CONV = 24 // Coulomb Counter ADC Conversion Complete + IRQ_CCADC_REG_CUR = 25 // Coloumb Counter ADC Regular Current + IRQ_CCADC_ACC = 26 // Coloumb Counter ADC Accumulator + IRQ_EE_READY = 27 // EEPROM Ready + IRQ_SPM = 28 // SPM Ready + IRQ_max = 28 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + LOW __reg + HIGH __reg + }{ + LOW: 0x0, + HIGH: 0x1, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog-to-Digital Converter + ADC = struct { + VADMUX __reg + VADCL __reg + VADCH __reg + VADCSR __reg + }{ + VADMUX: 0x7c, // The VADC multiplexer Selection Register + VADCL: 0x78, // VADC Data Register Bytes + VADCH: 0x78, // VADC Data Register Bytes + VADCSR: 0x7a, // The VADC Control and Status register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // FET Control + FET = struct { + FCSR __reg + }{ + FCSR: 0xf0, // FET Control and Status Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access + EEARH: 0x41, // EEPROM Read/Write Access + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Coulomb Counter + COULOMB_COUNTER = struct { + CADCSRA __reg + CADCSRB __reg + CADCSRC __reg + CADICL __reg + CADICH __reg + CADAC3 __reg + CADAC2 __reg + CADAC1 __reg + CADAC0 __reg + CADRCC __reg + CADRDC __reg + }{ + CADCSRA: 0xe6, // CC-ADC Control and Status Register A + CADCSRB: 0xe7, // CC-ADC Control and Status Register B + CADCSRC: 0xe8, // CC-ADC Control and Status Register C + CADICL: 0xe4, // CC-ADC Instantaneous Current + CADICH: 0xe4, // CC-ADC Instantaneous Current + CADAC3: 0xe3, // ADC Accumulate Current + CADAC2: 0xe2, // ADC Accumulate Current + CADAC1: 0xe1, // ADC Accumulate Current + CADAC0: 0xe0, // ADC Accumulate Current + CADRCC: 0xe9, // CC-ADC Regular Charge Current + CADRDC: 0xea, // CC-ADC Regular Discharge Current + } + + // Two Wire Serial Interface + TWI = struct { + TWBCSR __reg + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWBCSR: 0xbe, // TWI Bus Control and Status Register + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCICR __reg + PCIFR __reg + PCMSK1 __reg + PCMSK0 __reg + }{ + EICRA: 0x69, // External Interrupt Control Register + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + PCMSK1: 0x6c, // Pin Change Enable Mask Register 1 + PCMSK0: 0x6b, // Pin Change Enable Mask Register 0 + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1B __reg + TCCR1A __reg + TCNT1L __reg + TCNT1H __reg + OCR1A __reg + OCR1B __reg + TIMSK1 __reg + TIFR1 __reg + TCCR0B __reg + TCCR0A __reg + TCNT0L __reg + TCNT0H __reg + OCR0A __reg + OCR0B __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1A: 0x80, // Timer/Counter 1 Control Register A + TCNT1L: 0x84, // Timer Counter 1 Bytes + TCNT1H: 0x84, // Timer Counter 1 Bytes + OCR1A: 0x88, // Output Compare Register 1A + OCR1B: 0x89, // Output Compare Register B + TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR0B: 0x45, // Timer/Counter0 Control Register B + TCCR0A: 0x44, // Timer/Counter 0 Control Register A + TCNT0L: 0x46, // Timer Counter 0 Bytes + TCNT0H: 0x46, // Timer Counter 0 Bytes + OCR0A: 0x48, // Output Compare Register 0A + OCR0B: 0x49, // Output Compare Register B + TIMSK0: 0x6e, // Timer/Counter Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter Interrupt Flag register + } + + // Cell Balancing + CELL_BALANCING = struct { + CBCR __reg + }{ + CBCR: 0xf1, // Cell Balancing Control Register + } + + // Battery Protection + BATTERY_PROTECTION = struct { + BPPLR __reg + BPCR __reg + BPHCTR __reg + BPOCTR __reg + BPSCTR __reg + BPCHCD __reg + BPDHCD __reg + BPCOCD __reg + BPDOCD __reg + BPSCD __reg + BPIFR __reg + BPIMSK __reg + }{ + BPPLR: 0xfe, // Battery Protection Parameter Lock Register + BPCR: 0xfd, // Battery Protection Control Register + BPHCTR: 0xfc, // Battery Protection Short-current Timing Register + BPOCTR: 0xfb, // Battery Protection Over-current Timing Register + BPSCTR: 0xfa, // Battery Protection Short-current Timing Register + BPCHCD: 0xf9, // Battery Protection Charge-High-current Detection Level Register + BPDHCD: 0xf8, // Battery Protection Discharge-High-current Detection Level Register + BPCOCD: 0xf7, // Battery Protection Charge-Over-current Detection Level Register + BPDOCD: 0xf6, // Battery Protection Discharge-Over-current Detection Level Register + BPSCD: 0xf5, // Battery Protection Short-Circuit Detection Level Register + BPIFR: 0xf3, // Battery Protection Interrupt Flag Register + BPIMSK: 0xf2, // Battery Protection Interrupt Mask Register + } + + // Charger Detect + CHARGER_DETECT = struct { + CHGDCSR __reg + }{ + CHGDCSR: 0xd4, // Charger Detect Control and Status Register + } + + // Voltage Regulator + VOLTAGE_REGULATOR = struct { + ROCR __reg + }{ + ROCR: 0xc8, // Regulator Operating Condition Register + } + + // Bandgap + BANDGAP = struct { + BGCSR __reg + BGCRR __reg + BGCCR __reg + }{ + BGCSR: 0xd2, // Bandgap Control and Status Register + BGCRR: 0xd1, // Bandgap Calibration of Resistor Ladder + BGCCR: 0xd0, // Bandgap Calibration Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + MCUCR __reg + MCUSR __reg + FOSCCAL __reg + OSICSR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + DIDR0 __reg + PRR0 __reg + CLKPR __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + FOSCCAL: 0x66, // Fast Oscillator Calibration Value + OSICSR: 0x37, // Oscillator Sampling Interface Control and Status Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + DIDR0: 0x7e, // Digital Input Disable Register + PRR0: 0x64, // Power Reduction Register 0 + CLKPR: 0x61, // Clock Prescale Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + PINC __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + PINC: 0x26, // Port C Input Pins + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control and Status Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // LOW + LOW_WDTON = 0x80 // Watch-dog Timer always on + LOW_EESAVE = 0x40 // Preserve EEPROM through the Chip Erase cycle + LOW_SPIEN = 0x20 // Serial program downloading (SPI) enabled + LOW_SUT = 0x1c // Select start-up time + LOW_OSCSEL = 0x3 // Oscillator select + + // HIGH + HIGH_DUVRDINIT = 0x10 // DUVR mode on + HIGH_DWEN = 0x8 // Debug Wire enable + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // VADMUX: The VADC multiplexer Selection Register + VADMUX_VADMUX = 0xf // Analog Channel and Gain Selection Bits + + // VADCSR: The VADC Control and Status register + VADCSR_VADEN = 0x8 // VADC Enable + VADCSR_VADSC = 0x4 // VADC Satrt Conversion + VADCSR_VADCCIF = 0x2 // VADC Conversion Complete Interrupt Flag + VADCSR_VADCCIE = 0x1 // VADC Conversion Complete Interrupt Enable +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for FET: FET Control +const ( + // FCSR: FET Control and Status Register + FCSR_DUVRD = 0x8 // Deep Under-Voltage Recovery Disable + FCSR_CPS = 0x4 // Current Protection Status + FCSR_DFE = 0x2 // Discharge FET Enable + FCSR_CFE = 0x1 // Charge FET Enable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 + EECR_EERIE = 0x8 // EEProm Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for COULOMB_COUNTER: Coulomb Counter +const ( + // CADCSRA: CC-ADC Control and Status Register A + CADCSRA_CADEN = 0x80 // When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled. + CADCSRA_CADPOL = 0x40 + CADCSRA_CADUB = 0x20 // CC_ADC Update Busy + CADCSRA_CADAS = 0x18 // CC_ADC Accumulate Current Select Bits + CADCSRA_CADSI = 0x6 // The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. + CADCSRA_CADSE = 0x1 // When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode. + + // CADCSRB: CC-ADC Control and Status Register B + CADCSRB_CADACIE = 0x40 + CADCSRB_CADRCIE = 0x20 // Regular Current Interrupt Enable + CADCSRB_CADICIE = 0x10 // CAD Instantenous Current Interrupt Enable + CADCSRB_CADACIF = 0x4 // CC-ADC Accumulate Current Interrupt Flag + CADCSRB_CADRCIF = 0x2 // CC-ADC Accumulate Current Interrupt Flag + CADCSRB_CADICIF = 0x1 // CC-ADC Instantaneous Current Interrupt Flag + + // CADCSRC: CC-ADC Control and Status Register C + CADCSRC_CADVSE = 0x1 // CC-ADC Voltage Scaling Enable +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWBCSR: TWI Bus Control and Status Register + TWBCSR_TWBCIF = 0x80 // TWI Bus Connect/Disconnect Interrupt Flag + TWBCSR_TWBCIE = 0x40 // TWI Bus Connect/Disconnect Interrupt Enable + TWBCSR_TWBDT = 0x6 // TWI Bus Disconnect Time-out Period + TWBCSR_TWBCIP = 0x1 // TWI Bus Connect/Disconnect Interrupt Polarity + + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register + EICRA_ISC3 = 0xc0 // External Interrupt Sense Control 3 Bits + EICRA_ISC2 = 0x30 // External Interrupt Sense Control 2 Bits + EICRA_ISC1 = 0xc // External Interrupt Sense Control 1 Bits + EICRA_ISC0 = 0x3 // External Interrupt Sense Control 0 Bits + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xf // External Interrupt Request 3 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xf // External Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0x3 // Pin Change Interrupt Enables + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0x3 // Pin Change Interrupt Flags +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_CS = 0x7 // Clock Select1 bis + + // TCCR1A: Timer/Counter 1 Control Register A + TCCR1A_TCW1 = 0x80 // Timer/Counter Width + TCCR1A_ICEN1 = 0x40 // Input Capture Mode Enable + TCCR1A_ICNC1 = 0x20 // Input Capture Noise Canceler + TCCR1A_ICES1 = 0x10 // Input Capture Edge Select + TCCR1A_ICS1 = 0x8 // Input Capture Select + TCCR1A_WGM10 = 0x1 // Waveform Generation Mode + + // TIMSK1: Timer/Counter Interrupt Mask Register + TIMSK1_ICIE1 = 0x8 // Timer/Counter n Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x8 // Timer/Counter 1 Input Capture Flag + TIFR1_OCF1B = 0x4 // Timer/Counter1 Output Compare Flag B + TIFR1_OCF1A = 0x2 // Timer/Counter1 Output Compare Flag A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR0B: Timer/Counter0 Control Register B + TCCR0B_CS02 = 0x4 // Clock Select0 bit 2 + TCCR0B_CS01 = 0x2 // Clock Select0 bit 1 + TCCR0B_CS00 = 0x1 // Clock Select0 bit 0 + + // TCCR0A: Timer/Counter 0 Control Register A + TCCR0A_TCW0 = 0x80 // Timer/Counter Width + TCCR0A_ICEN0 = 0x40 // Input Capture Mode Enable + TCCR0A_ICNC0 = 0x20 // Input Capture Noise Canceler + TCCR0A_ICES0 = 0x10 // Input Capture Edge Select + TCCR0A_ICS0 = 0x8 // Input Capture Select + TCCR0A_WGM00 = 0x1 // Waveform Generation Mode + + // TIMSK0: Timer/Counter Interrupt Mask Register + TIMSK0_ICIE0 = 0x8 // Timer/Counter n Input Capture Interrupt Enable + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter Interrupt Flag register + TIFR0_ICF0 = 0x8 // Timer/Counter 0 Input Capture Flag + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for CELL_BALANCING: Cell Balancing +const ( + // CBCR: Cell Balancing Control Register + CBCR_CBE = 0xf // Cell Balancing Enables +) + +// Bitfields for BATTERY_PROTECTION: Battery Protection +const ( + // BPPLR: Battery Protection Parameter Lock Register + BPPLR_BPPLE = 0x2 // Battery Protection Parameter Lock Enable + BPPLR_BPPL = 0x1 // Battery Protection Parameter Lock + + // BPCR: Battery Protection Control Register + BPCR_EPID = 0x20 // External Protection Input Disable + BPCR_SCD = 0x10 // Short Circuit Protection Disabled + BPCR_DOCD = 0x8 // Discharge Over-current Protection Disabled + BPCR_COCD = 0x4 // Charge Over-current Protection Disabled + BPCR_DHCD = 0x2 // Discharge High-current Protection Disable + BPCR_CHCD = 0x1 // Charge High-current Protection Disable + + // BPIFR: Battery Protection Interrupt Flag Register + BPIFR_SCIF = 0x10 // Short-circuit Protection Activated Interrupt Flag + BPIFR_DOCIF = 0x8 // Discharge Over-current Protection Activated Interrupt Flag + BPIFR_COCIF = 0x4 // Charge Over-current Protection Activated Interrupt Flag + BPIFR_DHCIF = 0x2 // Disharge High-current Protection Activated Interrupt + BPIFR_CHCIF = 0x1 // Charge High-current Protection Activated Interrupt + + // BPIMSK: Battery Protection Interrupt Mask Register + BPIMSK_SCIE = 0x10 // Short-circuit Protection Activated Interrupt Enable + BPIMSK_DOCIE = 0x8 // Discharge Over-current Protection Activated Interrupt Enable + BPIMSK_COCIE = 0x4 // Charge Over-current Protection Activated Interrupt Enable + BPIMSK_DHCIE = 0x2 // Discharger High-current Protection Activated Interrupt + BPIMSK_CHCIE = 0x1 // Charger High-current Protection Activated Interrupt +) + +// Bitfields for CHARGER_DETECT: Charger Detect +const ( + // CHGDCSR: Charger Detect Control and Status Register + CHGDCSR_BATTPVL = 0x10 // BATT Pin Voltage Level + CHGDCSR_CHGDISC = 0xc // Charger Detect Interrupt Sense Control + CHGDCSR_CHGDIF = 0x2 // Charger Detect Interrupt Flag + CHGDCSR_CHGDIE = 0x1 // Charger Detect Interrupt Enable +) + +// Bitfields for VOLTAGE_REGULATOR: Voltage Regulator +const ( + // ROCR: Regulator Operating Condition Register + ROCR_ROCS = 0x80 // ROC Status + ROCR_ROCD = 0x10 // ROC Disable + ROCR_ROCWIF = 0x2 // ROC Warning Interrupt Flag + ROCR_ROCWIE = 0x1 // ROC Warning Interrupt Enable +) + +// Bitfields for BANDGAP: Bandgap +const ( + // BGCSR: Bandgap Control and Status Register + BGCSR_BGD = 0x20 // Bandgap Disable + BGCSR_BGSCDE = 0x10 // Bandgap Short Circuit Detection Enabled + BGCSR_BGSCDIF = 0x2 // Bandgap Short Circuit Detection Interrupt Flag + BGCSR_BGSCDIE = 0x1 // Bandgap Short Circuit Detection Interrupt Enable + + // BGCCR: Bandgap Calibration Register + BGCCR_BGCC = 0x3f // BG Calibration of PTAT Current Bits +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // MCUCR: MCU Control Register + MCUCR_CKOE = 0x20 // Clock Output Enable + MCUCR_PUD = 0x10 // Pull-up disable + MCUCR_IVSEL = 0x2 // Interrupt Vector Select + MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable + + // MCUSR: MCU Status Register + MCUSR_OCDRF = 0x10 // OCD Reset Flag + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BODRF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // OSICSR: Oscillator Sampling Interface Control and Status Register + OSICSR_OSISEL0 = 0x10 // Oscillator Sampling Interface Select 0 + OSICSR_OSIST = 0x2 // Oscillator Sampling Interface Status + OSICSR_OSIEN = 0x1 // Oscillator Sampling Interface Enable + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // DIDR0: Digital Input Disable Register + DIDR0_PA1DID = 0x2 // When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled. + DIDR0_PA0DID = 0x1 // When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled. + + // PRR0: Power Reduction Register 0 + PRR0_PRTWI = 0x40 // Power Reduction TWI + PRR0_PRVRM = 0x20 // Power Reduction Voltage Regulator Monitor + PRR0_PRSPI = 0x8 // Power reduction SPI + PRR0_PRTIM1 = 0x4 // Power Reduction Timer/Counter1 + PRR0_PRTIM0 = 0x2 // Power Reduction Timer/Counter0 + PRR0_PRVADC = 0x1 // Power Reduction V-ADC + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0x3 // Clock Prescaler Select Bits +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control and Status Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read-While-Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read-While-Write Section Read Enable + SPMCSR_LBSET = 0x8 // Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) diff --git a/src/device/avr/atmega32hvbrevb.ld b/src/device/avr/atmega32hvbrevb.ld new file mode 100644 index 00000000..36973fe0 --- /dev/null +++ b/src/device/avr/atmega32hvbrevb.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega32HVBrevB.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_size = 0x800; +__num_isrs = 29; diff --git a/src/device/avr/atmega32m1.go b/src/device/avr/atmega32m1.go new file mode 100644 index 00000000..d5c4e574 --- /dev/null +++ b/src/device/avr/atmega32m1.go @@ -0,0 +1,1019 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega32M1.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega32m1 + +// Device information for the ATmega32M1. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega32M1" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset + IRQ_ANACOMP0 = 1 // Analog Comparator 0 + IRQ_ANACOMP1 = 2 // Analog Comparator 1 + IRQ_ANACOMP2 = 3 // Analog Comparator 2 + IRQ_ANACOMP3 = 4 // Analog Comparator 3 + IRQ_PSC_FAULT = 5 // PSC Fault + IRQ_PSC_EC = 6 // PSC End of Cycle + IRQ_INT0 = 7 // External Interrupt Request 0 + IRQ_INT1 = 8 // External Interrupt Request 1 + IRQ_INT2 = 9 // External Interrupt Request 2 + IRQ_INT3 = 10 // External Interrupt Request 3 + IRQ_TIMER1_CAPT = 11 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 12 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 13 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 14 // Timer1/Counter1 Overflow + IRQ_TIMER0_COMPA = 15 // Timer/Counter0 Compare Match A + IRQ_TIMER0_COMPB = 16 // Timer/Counter0 Compare Match B + IRQ_TIMER0_OVF = 17 // Timer/Counter0 Overflow + IRQ_CAN_INT = 18 // CAN MOB, Burst, General Errors + IRQ_CAN_TOVF = 19 // CAN Timer Overflow + IRQ_LIN_TC = 20 // LIN Transfer Complete + IRQ_LIN_ERR = 21 // LIN Error + IRQ_PCINT0 = 22 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 23 // Pin Change Interrupt Request 1 + IRQ_PCINT2 = 24 // Pin Change Interrupt Request 2 + IRQ_PCINT3 = 25 // Pin Change Interrupt Request 3 + IRQ_SPI_STC = 26 // SPI Serial Transfer Complete + IRQ_ADC = 27 // ADC Conversion Complete + IRQ_WDT = 28 // Watchdog Time-Out Interrupt + IRQ_EE_READY = 29 // EEPROM Ready + IRQ_SPM_READY = 30 // Store Program Memory Read + IRQ_max = 30 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // I/O Port + PORT = struct { + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + }{ + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Port E Data Register + DDRE: 0x2d, // Port E Data Direction Register + PINE: 0x2c, // Port E Input Pins + } + + // Controller Area Network + CAN = struct { + CANGCON __reg + CANGSTA __reg + CANGIT __reg + CANGIE __reg + CANEN2 __reg + CANEN1 __reg + CANIE2 __reg + CANIE1 __reg + CANSIT2 __reg + CANSIT1 __reg + CANBT1 __reg + CANBT2 __reg + CANBT3 __reg + CANTCON __reg + CANTIML __reg + CANTIMH __reg + CANTTCL __reg + CANTTCH __reg + CANTEC __reg + CANREC __reg + CANHPMOB __reg + CANPAGE __reg + CANSTMOB __reg + CANCDMOB __reg + CANIDT4 __reg + CANIDT3 __reg + CANIDT2 __reg + CANIDT1 __reg + CANIDM4 __reg + CANIDM3 __reg + CANIDM2 __reg + CANIDM1 __reg + CANSTML __reg + CANSTMH __reg + CANMSG __reg + }{ + CANGCON: 0xd8, // CAN General Control Register + CANGSTA: 0xd9, // CAN General Status Register + CANGIT: 0xda, // CAN General Interrupt Register Flags + CANGIE: 0xdb, // CAN General Interrupt Enable Register + CANEN2: 0xdc, // Enable MOb Register 2 + CANEN1: 0xdd, // Enable MOb Register 1(empty) + CANIE2: 0xde, // Enable Interrupt MOb Register 2 + CANIE1: 0xdf, // Enable Interrupt MOb Register 1 (empty) + CANSIT2: 0xe0, // CAN Status Interrupt MOb Register 2 + CANSIT1: 0xe1, // CAN Status Interrupt MOb Register 1 (empty) + CANBT1: 0xe2, // CAN Bit Timing Register 1 + CANBT2: 0xe3, // CAN Bit Timing Register 2 + CANBT3: 0xe4, // CAN Bit Timing Register 3 + CANTCON: 0xe5, // Timer Control Register + CANTIML: 0xe6, // Timer Register Low + CANTIMH: 0xe7, // Timer Register High + CANTTCL: 0xe8, // TTC Timer Register Low + CANTTCH: 0xe9, // TTC Timer Register High + CANTEC: 0xea, // Transmit Error Counter Register + CANREC: 0xeb, // Receive Error Counter Register + CANHPMOB: 0xec, // Highest Priority MOb Register + CANPAGE: 0xed, // Page MOb Register + CANSTMOB: 0xee, // MOb Status Register + CANCDMOB: 0xef, // MOb Control and DLC Register + CANIDT4: 0xf0, // Identifier Tag Register 4 + CANIDT3: 0xf1, // Identifier Tag Register 3 + CANIDT2: 0xf2, // Identifier Tag Register 2 + CANIDT1: 0xf3, // Identifier Tag Register 1 + CANIDM4: 0xf4, // Identifier Mask Register 4 + CANIDM3: 0xf5, // Identifier Mask Register 3 + CANIDM2: 0xf6, // Identifier Mask Register 2 + CANIDM1: 0xf7, // Identifier Mask Register 1 + CANSTML: 0xf8, // Time Stamp Register Low + CANSTMH: 0xf9, // Time Stamp Register High + CANMSG: 0xfa, // Message Data Register + } + + // Analog Comparator + AC = struct { + AC0CON __reg + AC1CON __reg + AC2CON __reg + AC3CON __reg + ACSR __reg + }{ + AC0CON: 0x94, // Analog Comparator 0 Control Register + AC1CON: 0x95, // Analog Comparator 1 Control Register + AC2CON: 0x96, // Analog Comparator 2 Control Register + AC3CON: 0x97, // Analog Comparator 3 Control Register + ACSR: 0x50, // Analog Comparator Status Register + } + + // Digital-to-Analog Converter + DAC = struct { + DACH __reg + DACL __reg + DACON __reg + }{ + DACH: 0x92, // DAC Data Register High Byte + DACL: 0x91, // DAC Data Register Low Byte + DACON: 0x90, // DAC Control Register + } + + // CPU Registers + CPU = struct { + SPMCSR __reg + SREG __reg + SPL __reg + SPH __reg + MCUCR __reg + MCUSR __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PLLCSR __reg + PRR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x3a, // General Purpose IO Register 2 + GPIOR1: 0x39, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PLLCSR: 0x49, // PLL Control And Status Register + PRR: 0x64, // Power Reduction Register + } + + // Timer/Counter, 8-bit + TC8 = struct { + TIMSK0 __reg + TIFR0 __reg + TCCR0A __reg + TCCR0B __reg + TCNT0 __reg + OCR0A __reg + OCR0B __reg + }{ + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + TCCR0A: 0x44, // Timer/Counter Control Register A + TCCR0B: 0x45, // Timer/Counter Control Register B + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + ADCSRB __reg + DIDR0 __reg + DIDR1 __reg + AMP0CSR __reg + AMP1CSR __reg + AMP2CSR __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRB: 0x7b, // ADC Control and Status Register B + DIDR0: 0x7e, // Digital Input Disable Register 0 + DIDR1: 0x7f, // Digital Input Disable Register 0 + AMP0CSR: 0x75, + AMP1CSR: 0x76, + AMP2CSR: 0x77, + } + + // Local Interconnect Network + LINUART = struct { + LINCR __reg + LINSIR __reg + LINENIR __reg + LINERR __reg + LINBTR __reg + LINBRRL __reg + LINBRRH __reg + LINDLR __reg + LINIDR __reg + LINSEL __reg + LINDAT __reg + }{ + LINCR: 0xc8, // LIN Control Register + LINSIR: 0xc9, // LIN Status and Interrupt Register + LINENIR: 0xca, // LIN Enable Interrupt Register + LINERR: 0xcb, // LIN Error Register + LINBTR: 0xcc, // LIN Bit Timing Register + LINBRRL: 0xcd, // LIN Baud Rate Low Register + LINBRRH: 0xce, // LIN Baud Rate High Register + LINDLR: 0xcf, // LIN Data Length Register + LINIDR: 0xd0, // LIN Identifier Register + LINSEL: 0xd1, // LIN Data Buffer Selection Register + LINDAT: 0xd2, // LIN Data Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCICR __reg + PCMSK3 __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + PCMSK3: 0x6d, // Pin Change Mask Register 3 + PCMSK2: 0x6c, // Pin Change Mask Register 2 + PCMSK1: 0x6b, // Pin Change Mask Register 1 + PCMSK0: 0x6a, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access + EEARH: 0x41, // EEPROM Read/Write Access + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Power Stage Controller + PSC = struct { + PIFR __reg + PIM __reg + PMIC2 __reg + PMIC1 __reg + PMIC0 __reg + PCTL __reg + POC __reg + PCNF __reg + PSYNC __reg + POCR_RBL __reg + POCR_RBH __reg + POCR2SBL __reg + POCR2SBH __reg + POCR2RAL __reg + POCR2RAH __reg + POCR2SAL __reg + POCR2SAH __reg + POCR1SBL __reg + POCR1SBH __reg + POCR1RAL __reg + POCR1RAH __reg + POCR1SAL __reg + POCR1SAH __reg + POCR0SBL __reg + POCR0SBH __reg + POCR0RAL __reg + POCR0RAH __reg + POCR0SAL __reg + POCR0SAH __reg + }{ + PIFR: 0xbc, // PSC Interrupt Flag Register + PIM: 0xbb, // PSC Interrupt Mask Register + PMIC2: 0xba, // PSC Module 2 Input Control Register + PMIC1: 0xb9, // PSC Module 1 Input Control Register + PMIC0: 0xb8, // PSC Module 0 Input Control Register + PCTL: 0xb7, // PSC Control Register + POC: 0xb6, // PSC Output Configuration + PCNF: 0xb5, // PSC Configuration Register + PSYNC: 0xb4, // PSC Synchro Configuration + POCR_RBL: 0xb2, // PSC Output Compare RB Register + POCR_RBH: 0xb2, // PSC Output Compare RB Register + POCR2SBL: 0xb0, // PSC Module 2 Output Compare SB Register + POCR2SBH: 0xb0, // PSC Module 2 Output Compare SB Register + POCR2RAL: 0xae, // PSC Module 2 Output Compare RA Register + POCR2RAH: 0xae, // PSC Module 2 Output Compare RA Register + POCR2SAL: 0xac, // PSC Module 2 Output Compare SA Register + POCR2SAH: 0xac, // PSC Module 2 Output Compare SA Register + POCR1SBL: 0xaa, // PSC Module 1 Output Compare SB Register + POCR1SBH: 0xaa, // PSC Module 1 Output Compare SB Register + POCR1RAL: 0xa8, // PSC Module 1 Output Compare RA Register + POCR1RAH: 0xa8, // PSC Module 1 Output Compare RA Register + POCR1SAL: 0xa6, // PSC Output Compare SA Register + POCR1SAH: 0xa6, // PSC Output Compare SA Register + POCR0SBL: 0xa4, // PSC Output Compare SB Register + POCR0SBH: 0xa4, // PSC Output Compare SB Register + POCR0RAL: 0xa2, // PSC Module 0 Output Compare RA Register + POCR0RAH: 0xa2, // PSC Module 0 Output Compare RA Register + POCR0SAL: 0xa0, // PSC Module 0 Output Compare SA Register + POCR0SAH: 0xa0, // PSC Module 0 Output Compare SA Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_PSCRB = 0x20 // PSC Reset Behavior + EXTENDED_PSCRVA = 0x10 // PSCOUTnA Reset Value + EXTENDED_PSCRVB = 0x8 // PSC0UTnB Reset Value + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector Trigger Level + + // HIGH + HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PC6 as i/o pin) + HIGH_DWEN = 0x40 // Debug Wire enable + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watch-dog Timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Select Reset Vector + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTD1 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for CAN: Controller Area Network +const ( + // CANGCON: CAN General Control Register + CANGCON_ABRQ = 0x80 // Abort Request + CANGCON_OVRQ = 0x40 // Overload Frame Request + CANGCON_TTC = 0x20 // Time Trigger Communication + CANGCON_SYNTTC = 0x10 // Synchronization of TTC + CANGCON_LISTEN = 0x8 // Listening Mode + CANGCON_TEST = 0x4 // Test Mode + CANGCON_ENASTB = 0x2 // Enable / Standby + CANGCON_SWRES = 0x1 // Software Reset Request + + // CANGSTA: CAN General Status Register + CANGSTA_OVFG = 0x40 // Overload Frame Flag + CANGSTA_TXBSY = 0x10 // Transmitter Busy + CANGSTA_RXBSY = 0x8 // Receiver Busy + CANGSTA_ENFG = 0x4 // Enable Flag + CANGSTA_BOFF = 0x2 // Bus Off Mode + CANGSTA_ERRP = 0x1 // Error Passive Mode + + // CANGIT: CAN General Interrupt Register Flags + CANGIT_CANIT = 0x80 // General Interrupt Flag + CANGIT_BOFFIT = 0x40 // Bus Off Interrupt Flag + CANGIT_OVRTIM = 0x20 // Overrun CAN Timer Flag + CANGIT_BXOK = 0x10 // Burst Receive Interrupt Flag + CANGIT_SERG = 0x8 // Stuff Error General Flag + CANGIT_CERG = 0x4 // CRC Error General Flag + CANGIT_FERG = 0x2 // Form Error General Flag + CANGIT_AERG = 0x1 // Ackknowledgement Error General Flag + + // CANGIE: CAN General Interrupt Enable Register + CANGIE_ENIT = 0x80 // Enable all Interrupts + CANGIE_ENBOFF = 0x40 // Enable Bus Off Interrupt + CANGIE_ENRX = 0x20 // Enable Receive Interrupt + CANGIE_ENTX = 0x10 // Enable Transmitt Interrupt + CANGIE_ENERR = 0x8 // Enable MOb Error Interrupt + CANGIE_ENBX = 0x4 // Enable Burst Receive Interrupt + CANGIE_ENERG = 0x2 // Enable General Error Interrupt + CANGIE_ENOVRT = 0x1 // Enable CAN Timer Overrun Interrupt + + // CANEN2: Enable MOb Register 2 + CANEN2_ENMOB = 0x3f // Enable MObs + + // CANIE2: Enable Interrupt MOb Register 2 + CANIE2_IEMOB = 0x3f // Interrupt Enable MObs + + // CANSIT2: CAN Status Interrupt MOb Register 2 + CANSIT2_SIT = 0x3f // Status of Interrupt MObs + + // CANBT1: CAN Bit Timing Register 1 + CANBT1_BRP = 0x7e // Baud Rate Prescaler bits + + // CANBT2: CAN Bit Timing Register 2 + CANBT2_SJW = 0x60 // Re-Sync Jump Width bits + CANBT2_PRS = 0xe // Propagation Time Segment bits + + // CANBT3: CAN Bit Timing Register 3 + CANBT3_PHS2 = 0x70 // Phase Segment 2 bits + CANBT3_PHS1 = 0xe // Phase Segment 1 bits + CANBT3_SMP = 0x1 // Sample Type + + // CANHPMOB: Highest Priority MOb Register + CANHPMOB_HPMOB = 0xf0 // Highest Priority MOb Number bits + CANHPMOB_CGP = 0xf // CAN General Purpose bits + + // CANPAGE: Page MOb Register + CANPAGE_MOBNB = 0xf0 // MOb Number bits + CANPAGE_AINC = 0x8 // MOb Data Buffer Auto Increment (Active Low) + CANPAGE_INDX = 0x7 // Data Buffer Index bits + + // CANSTMOB: MOb Status Register + CANSTMOB_DLCW = 0x80 // Data Length Code Warning on MOb + CANSTMOB_TXOK = 0x40 // Transmit OK on MOb + CANSTMOB_RXOK = 0x20 // Receive OK on MOb + CANSTMOB_BERR = 0x10 // Bit Error on MOb + CANSTMOB_SERR = 0x8 // Stuff Error on MOb + CANSTMOB_CERR = 0x4 // CRC Error on MOb + CANSTMOB_FERR = 0x2 // Form Error on MOb + CANSTMOB_AERR = 0x1 // Ackknowledgement Error on MOb + + // CANCDMOB: MOb Control and DLC Register + CANCDMOB_CONMOB = 0xc0 // MOb Config bits + CANCDMOB_RPLV = 0x20 // Reply Valid + CANCDMOB_IDE = 0x10 // Identifier Extension + CANCDMOB_DLC = 0xf // Data Length Code bits + + // CANIDT4: Identifier Tag Register 4 + CANIDT4_IDT = 0xf8 + CANIDT4_RTRTAG = 0x4 + CANIDT4_RB1TAG = 0x2 + CANIDT4_RB0TAG = 0x1 +) + +// Bitfields for AC: Analog Comparator +const ( + // AC0CON: Analog Comparator 0 Control Register + AC0CON_AC0EN = 0x80 // Analog Comparator 0 Enable Bit + AC0CON_AC0IE = 0x40 // Analog Comparator 0 Interrupt Enable Bit + AC0CON_AC0IS = 0x30 // Analog Comparator 0 Interrupt Select Bits + AC0CON_ACCKSEL = 0x8 // Analog Comparator Clock Select + AC0CON_AC0M = 0x7 // Analog Comparator 0 Multiplexer Register + + // AC1CON: Analog Comparator 1 Control Register + AC1CON_AC1EN = 0x80 // Analog Comparator 1 Enable Bit + AC1CON_AC1IE = 0x40 // Analog Comparator 1 Interrupt Enable Bit + AC1CON_AC1IS = 0x30 // Analog Comparator 1 Interrupt Select Bit + AC1CON_AC1ICE = 0x8 // Analog Comparator 1 Interrupt Capture Enable Bit + AC1CON_AC1M = 0x7 // Analog Comparator 1 Multiplexer Register + + // AC2CON: Analog Comparator 2 Control Register + AC2CON_AC2EN = 0x80 // Analog Comparator 2 Enable Bit + AC2CON_AC2IE = 0x40 // Analog Comparator 2 Interrupt Enable Bit + AC2CON_AC2IS = 0x30 // Analog Comparator 2 Interrupt Select Bit + AC2CON_AC2M = 0x7 // Analog Comparator 2 Multiplexer Register + + // AC3CON: Analog Comparator 3 Control Register + AC3CON_AC3EN = 0x80 // Analog Comparator 3 Enable Bit + AC3CON_AC3IE = 0x40 // Analog Comparator 3 Interrupt Enable Bit + AC3CON_AC3IS = 0x30 // Analog Comparator 3 Interrupt Select Bit + AC3CON_AC3M = 0x7 // Analog Comparator 3 Multiplexer Register + + // ACSR: Analog Comparator Status Register + ACSR_AC3IF = 0x80 // Analog Comparator 3 Interrupt Flag Bit + ACSR_AC2IF = 0x40 // Analog Comparator 2 Interrupt Flag Bit + ACSR_AC1IF = 0x20 // Analog Comparator 1 Interrupt Flag Bit + ACSR_AC0IF = 0x10 // Analog Comparator 0 Interrupt Flag Bit + ACSR_AC3O = 0x8 // Analog Comparator 3 Output Bit + ACSR_AC2O = 0x4 // Analog Comparator 2 Output Bit + ACSR_AC1O = 0x2 // Analog Comparator 1 Output Bit + ACSR_AC0O = 0x1 // Analog Comparator 0 Output Bit +) + +// Bitfields for DAC: Digital-to-Analog Converter +const ( + // DACH: DAC Data Register High Byte + DACH_DACH = 0xff // DAC Data Register High Byte Bits + + // DACL: DAC Data Register Low Byte + DACL_DACL = 0xff // DAC Data Register Low Byte Bits + + // DACON: DAC Control Register + DACON_DAATE = 0x80 // DAC Auto Trigger Enable Bit + DACON_DATS = 0x70 // DAC Trigger Selection Bits + DACON_DALA = 0x4 // DAC Left Adjust + DACON_DAEN = 0x1 // DAC Enable Bit +) + +// Bitfields for CPU: CPU Registers +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable + + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // MCUCR: MCU Control Register + MCUCR_SPIPS = 0x80 // SPI Pin Select + MCUCR_PUD = 0x10 // Pull-up disable + MCUCR_IVSEL = 0x2 // Interrupt Vector Select + MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable + + // MCUSR: MCU Status Register + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BORF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 + + // PLLCSR: PLL Control And Status Register + PLLCSR_PLLF = 0x4 // PLL Factor + PLLCSR_PLLE = 0x2 // PLL Enable + PLLCSR_PLOCK = 0x1 // PLL Lock Detector + + // PRR: Power Reduction Register + PRR_PRCAN = 0x40 // Power Reduction CAN + PRR_PRPSC = 0x20 // Power Reduction PSC + PRR_PRTIM1 = 0x10 // Power Reduction Timer/Counter1 + PRR_PRTIM0 = 0x8 // Power Reduction Timer/Counter0 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRLIN = 0x2 // Power Reduction LIN UART + PRR_PRADC = 0x1 // Power Reduction ADC +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TIMSK1: Timer/Counter Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output CompareB Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output CompareA Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 + TCCR1C_FOC1B = 0x40 +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCSRB: ADC Control and Status Register B + ADCSRB_ADHSM = 0x80 // ADC High Speed Mode + ADCSRB_ISRCEN = 0x40 // Current Source Enable + ADCSRB_AREFEN = 0x20 // Analog Reference pin Enable + ADCSRB_ADTS = 0xf // ADC Auto Trigger Sources + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable + + // DIDR1: Digital Input Disable Register 0 + DIDR1_AMP2PD = 0x40 // AMP2P Pin Digital input Disable + DIDR1_ACMP0D = 0x20 // ACMP0 Pin Digital input Disable + DIDR1_AMP0PD = 0x10 // AMP0P Pin Digital input Disable + DIDR1_AMP0ND = 0x8 // AMP0N Pin Digital input Disable + DIDR1_ADC10D = 0x4 // ADC10 Pin Digital input Disable + DIDR1_ADC9D = 0x2 // ADC9 Pin Digital input Disable + DIDR1_ADC8D = 0x1 // ADC8 Pin Digital input Disable + + // AMP0CSR + AMP0CSR_AMP0EN = 0x80 + AMP0CSR_AMP0IS = 0x40 + AMP0CSR_AMP0G = 0x30 + AMP0CSR_AMPCMP0 = 0x8 // Amplifier 0 - Comparator 0 Connection + AMP0CSR_AMP0TS = 0x7 + + // AMP1CSR + AMP1CSR_AMP1EN = 0x80 + AMP1CSR_AMP1IS = 0x40 + AMP1CSR_AMP1G = 0x30 + AMP1CSR_AMPCMP1 = 0x8 // Amplifier 1 - Comparator 1 Connection + AMP1CSR_AMP1TS = 0x7 + + // AMP2CSR + AMP2CSR_AMP2EN = 0x80 + AMP2CSR_AMP2IS = 0x40 + AMP2CSR_AMP2G = 0x30 + AMP2CSR_AMPCMP2 = 0x8 // Amplifier 2 - Comparator 2 Connection + AMP2CSR_AMP2TS = 0x7 +) + +// Bitfields for LINUART: Local Interconnect Network +const ( + // LINCR: LIN Control Register + LINCR_LSWRES = 0x80 // Software Reset + LINCR_LIN13 = 0x40 // LIN Standard + LINCR_LCONF = 0x30 // LIN Configuration bits + LINCR_LENA = 0x8 // LIN or UART Enable + LINCR_LCMD = 0x7 // LIN Command and Mode bits + + // LINSIR: LIN Status and Interrupt Register + LINSIR_LIDST = 0xe0 // Identifier Status bits + LINSIR_LBUSY = 0x10 // Busy Signal + LINSIR_LERR = 0x8 // Error Interrupt + LINSIR_LIDOK = 0x4 // Identifier Interrupt + LINSIR_LTXOK = 0x2 // Transmit Performed Interrupt + LINSIR_LRXOK = 0x1 // Receive Performed Interrupt + + // LINENIR: LIN Enable Interrupt Register + LINENIR_LENERR = 0x8 // Enable Error Interrupt + LINENIR_LENIDOK = 0x4 // Enable Identifier Interrupt + LINENIR_LENTXOK = 0x2 // Enable Transmit Performed Interrupt + LINENIR_LENRXOK = 0x1 // Enable Receive Performed Interrupt + + // LINERR: LIN Error Register + LINERR_LABORT = 0x80 // Abort Flag + LINERR_LTOERR = 0x40 // Frame Time Out Error Flag + LINERR_LOVERR = 0x20 // Overrun Error Flag + LINERR_LFERR = 0x10 // Framing Error Flag + LINERR_LSERR = 0x8 // Synchronization Error Flag + LINERR_LPERR = 0x4 // Parity Error Flag + LINERR_LCERR = 0x2 // Checksum Error Flag + LINERR_LBERR = 0x1 // Bit Error Flag + + // LINBTR: LIN Bit Timing Register + LINBTR_LDISR = 0x80 // Disable Bit Timing Resynchronization + LINBTR_LBT = 0x3f // LIN Bit Timing bits + + // LINBRRL: LIN Baud Rate Low Register + LINBRRL_LDIV = 0xff + + // LINBRRH: LIN Baud Rate High Register + LINBRRH_LDIV = 0xf + + // LINDLR: LIN Data Length Register + LINDLR_LTXDL = 0xf0 // LIN Transmit Data Length bits + LINDLR_LRXDL = 0xf // LIN Receive Data Length bits + + // LINIDR: LIN Identifier Register + LINIDR_LP = 0xc0 // Parity bits + LINIDR_LID = 0x3f // Identifier bit 5 or Data Length bits + + // LINSEL: LIN Data Buffer Selection Register + LINSEL_LAINC = 0x8 // Auto Increment of Data Buffer Index (Active Low) + LINSEL_LINDX = 0x7 // FIFO LIN Data Buffer Index bits + + // LINDAT: LIN Data Register + LINDAT_LDATA = 0xff +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register + EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control 1 Bits + EICRA_ISC0 = 0x3 // External Interrupt Sense Control 0 Bits + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xf // External Interrupt Request 3 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xf // External Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0xf // Pin Change Interrupt Enables + + // PCMSK3: Pin Change Mask Register 3 + PCMSK3_PCINT = 0x7 // Pin Change Enable Masks + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0xf // Pin Change Interrupt Flags +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 + EECR_EERIE = 0x8 // EEProm Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for PSC: Power Stage Controller +const ( + // PIFR: PSC Interrupt Flag Register + PIFR_PEV = 0xe // PSC External Event 2 Interrupt + PIFR_PEOP = 0x1 // PSC End of Cycle Interrupt + + // PIM: PSC Interrupt Mask Register + PIM_PEVE = 0xe // External Event 2 Interrupt Enable + PIM_PEOPE = 0x1 // PSC End of Cycle Interrupt Enable + + // PMIC2: PSC Module 2 Input Control Register + PMIC2_POVEN2 = 0x80 // PSC Module 2 Overlap Enable + PMIC2_PISEL2 = 0x40 // PSC Module 2 Input Select + PMIC2_PELEV2 = 0x20 // PSC Module 2 Input Level Selector + PMIC2_PFLTE2 = 0x10 // PSC Module 2 Input Filter Enable + PMIC2_PAOC2 = 0x8 // PSC Module 2 Asynchronous Output Control + PMIC2_PRFM2 = 0x7 // PSC Module 2 Input Mode bits + + // PMIC1: PSC Module 1 Input Control Register + PMIC1_POVEN1 = 0x80 // PSC Module 1 Overlap Enable + PMIC1_PISEL1 = 0x40 // PSC Module 1 Input Select + PMIC1_PELEV1 = 0x20 // PSC Module 1 Input Level Selector + PMIC1_PFLTE1 = 0x10 // PSC Module 1 Input Filter Enable + PMIC1_PAOC1 = 0x8 // PSC Module 1 Asynchronous Output Control + PMIC1_PRFM1 = 0x7 // PSC Module 1 Input Mode bits + + // PMIC0: PSC Module 0 Input Control Register + PMIC0_POVEN0 = 0x80 // PSC Module 0 Overlap Enable + PMIC0_PISEL0 = 0x40 // PSC Module 0 Input Select + PMIC0_PELEV0 = 0x20 // PSC Module 0 Input Level Selector + PMIC0_PFLTE0 = 0x10 // PSC Module 0 Input Filter Enable + PMIC0_PAOC0 = 0x8 // PSC Module 0 Asynchronous Output Control + PMIC0_PRFM0 = 0x7 // PSC Module 0 Input Mode bits + + // PCTL: PSC Control Register + PCTL_PPRE = 0xc0 // PSC Prescaler Select bits + PCTL_PCLKSEL = 0x20 // PSC Input Clock Select + PCTL_PCCYC = 0x2 // PSC Complete Cycle + PCTL_PRUN = 0x1 // PSC Run + + // POC: PSC Output Configuration + POC_POEN2B = 0x20 // PSC Output 2B Enable + POC_POEN2A = 0x10 // PSC Output 2A Enable + POC_POEN1B = 0x8 // PSC Output 1B Enable + POC_POEN1A = 0x4 // PSC Output 1A Enable + POC_POEN0B = 0x2 // PSC Output 0B Enable + POC_POEN0A = 0x1 // PSC Output 0A Enable + + // PCNF: PSC Configuration Register + PCNF_PULOCK = 0x20 // PSC Update Lock + PCNF_PMODE = 0x10 // PSC Mode + PCNF_POPB = 0x8 // PSC Output B Polarity + PCNF_POPA = 0x4 // PSC Output A Polarity + + // PSYNC: PSC Synchro Configuration + PSYNC_PSYNC2 = 0x30 // Selection of Synchronization Out for ADC + PSYNC_PSYNC1 = 0xc // Selection of Synchronization Out for ADC + PSYNC_PSYNC0 = 0x3 // Selection of Synchronization Out for ADC +) diff --git a/src/device/avr/atmega32m1.ld b/src/device/avr/atmega32m1.ld new file mode 100644 index 00000000..35894cfe --- /dev/null +++ b/src/device/avr/atmega32m1.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega32M1.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_size = 0x800; +__num_isrs = 31; diff --git a/src/device/avr/atmega32u2.go b/src/device/avr/atmega32u2.go new file mode 100644 index 00000000..089e6d1c --- /dev/null +++ b/src/device/avr/atmega32u2.go @@ -0,0 +1,789 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega32U2.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega32u2 + +// Device information for the ATmega32U2. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega32U2" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_INT3 = 4 // External Interrupt Request 3 + IRQ_INT4 = 5 // External Interrupt Request 4 + IRQ_INT5 = 6 // External Interrupt Request 5 + IRQ_INT6 = 7 // External Interrupt Request 6 + IRQ_INT7 = 8 // External Interrupt Request 7 + IRQ_PCINT0 = 9 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 10 // Pin Change Interrupt Request 1 + IRQ_USB_GEN = 11 // USB General Interrupt Request + IRQ_USB_COM = 12 // USB Endpoint/Pipe Interrupt Communication Request + IRQ_WDT = 13 // Watchdog Time-out Interrupt + IRQ_TIMER1_CAPT = 14 // Timer/Counter2 Capture Event + IRQ_TIMER1_COMPA = 15 // Timer/Counter2 Compare Match B + IRQ_TIMER1_COMPB = 16 // Timer/Counter2 Compare Match B + IRQ_TIMER1_COMPC = 17 // Timer/Counter2 Compare Match C + IRQ_TIMER1_OVF = 18 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 19 // Timer/Counter0 Compare Match A + IRQ_TIMER0_COMPB = 20 // Timer/Counter0 Compare Match B + IRQ_TIMER0_OVF = 21 // Timer/Counter0 Overflow + IRQ_SPI_STC = 22 // SPI Serial Transfer Complete + IRQ_USART1_RX = 23 // USART1, Rx Complete + IRQ_USART1_UDRE = 24 // USART1 Data register Empty + IRQ_USART1_TX = 25 // USART1, Tx Complete + IRQ_ANALOG_COMP = 26 // Analog Comparator + IRQ_EE_READY = 27 // EEPROM Ready + IRQ_SPM_READY = 28 // Store Program Memory Read + IRQ_max = 28 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // I/O Port + PORT = struct { + PORTB __reg + DDRB __reg + PINB __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTC __reg + DDRC __reg + PINC __reg + }{ + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Low Bytes + EEARH: 0x41, // EEPROM Address Register Low Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + GTCCR __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + GTCCR: 0x43, // General Timer/Counter Control Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + OCR1CL __reg + OCR1CH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1CL: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + OCR1CH: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // Phase Locked Loop + PLL = struct { + PLLCSR __reg + }{ + PLLCSR: 0x49, // PLL Status and Control register + } + + // USB Device Registers + USB_DEVICE = struct { + UPOE __reg + UEINT __reg + UEBCLX __reg + UEDATX __reg + UEIENX __reg + UESTA1X __reg + UESTA0X __reg + UECFG1X __reg + UECFG0X __reg + UECONX __reg + UERST __reg + UENUM __reg + UEINTX __reg + UDMFN __reg + UDFNUML __reg + UDFNUMH __reg + UDADDR __reg + UDIEN __reg + UDINT __reg + UDCON __reg + USBCON __reg + REGCR __reg + }{ + UPOE: 0xfb, // USB Software Output Enable register + UEINT: 0xf4, // USB Endpoint Number Interrupt Register + UEBCLX: 0xf2, // USB Endpoint Byte Count Register + UEDATX: 0xf1, // USB Data Endpoint + UEIENX: 0xf0, // USB Endpoint Interrupt Enable Register + UESTA1X: 0xef, // USB Endpoint Status 1 Register + UESTA0X: 0xee, // USB Endpoint Status 0 Register + UECFG1X: 0xed, // USB Endpoint Configuration 1 Register + UECFG0X: 0xec, // USB Endpoint Configuration 0 Register + UECONX: 0xeb, // USB Endpoint Control Register + UERST: 0xea, // USB Endpoint Reset Register + UENUM: 0xe9, // USB Endpoint Number + UEINTX: 0xe8, // USB Endpoint Interrupt Register + UDMFN: 0xe6, // USB Device Micro Frame Number + UDFNUML: 0xe4, // USB Device Frame Number High Register + UDFNUMH: 0xe4, // USB Device Frame Number High Register + UDADDR: 0xe3, // USB Device Address Register + UDIEN: 0xe2, // USB Device Interrupt Enable Register + UDINT: 0xe1, // USB Device Interrupt Register + UDCON: 0xe0, // USB Device Control Registers + USBCON: 0xd8, // USB General Control Register + REGCR: 0x63, // Regulator Control Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + MCUCR __reg + MCUSR __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + EIND __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PRR1 __reg + PRR0 __reg + CLKSTA __reg + CLKSEL1 __reg + CLKSEL0 __reg + DWDR __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, + SMCR: 0x53, // Sleep Mode Control Register + EIND: 0x5c, // Extended Indirect Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PRR1: 0x65, // Power Reduction Register1 + PRR0: 0x64, // Power Reduction Register0 + CLKSTA: 0xd2, + CLKSEL1: 0xd1, + CLKSEL0: 0xd0, + DWDR: 0x51, // debugWire communication register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EICRB __reg + EIMSK __reg + EIFR __reg + PCMSK0 __reg + PCMSK1 __reg + PCIFR __reg + PCICR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EICRB: 0x6a, // External Interrupt Control Register B + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + } + + // USART + USART = struct { + UDR1 __reg + UCSR1A __reg + UCSR1B __reg + UCSR1C __reg + UCSR1D __reg + UBRR1L __reg + UBRR1H __reg + }{ + UDR1: 0xce, // USART I/O Data Register + UCSR1A: 0xc8, // USART Control and Status Register A + UCSR1B: 0xc9, // USART Control and Status Register B + UCSR1C: 0xca, // USART Control and Status Register C + UCSR1D: 0xcb, // USART Control and Status Register D + UBRR1L: 0xcc, // USART Baud Rate Register Bytes + UBRR1H: 0xcc, // USART Baud Rate Register Bytes + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + WDTCKD __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + WDTCKD: 0x62, // Watchdog Timer Clock Divider + } + + // Analog Comparator + AC = struct { + ACSR __reg + ACMUX __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + ACMUX: 0x7d, // Analog Comparator Input Multiplexer + DIDR1: 0x7f, + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level + EXTENDED_HWBE = 0x8 // Hardware Boot Enable + + // HIGH + HIGH_DWEN = 0x80 // Debug Wire enable + HIGH_RSTDISBL = 0x40 // Reset Disabled (Enable PC6 as i/o pin) + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTC7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for PORT: I/O Port +const ( + // PORTC: Port C Data Register + PORTC_PORTC = 0xf0 // Port C Data Register bits + PORTC_PORTC = 0x7 // Port C Data Register bits + + // DDRC: Port C Data Direction Register + DDRC_DDC = 0xf0 // Port C Data Direction Register bits + DDRC_DDC = 0x7 // Port C Data Direction Register bits + + // PINC: Port C Input Pins + PINC_PINC = 0xf0 // Port C Input Pins bits + PINC_PINC = 0x7 // Port C Input Pins bits +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag + + // GTCCR: General Timer/Counter Control Register + GTCCR_TSM = 0x80 // Timer/Counter Synchronization Mode + GTCCR_PSRSYNC = 0x1 // Prescaler Reset Timer/Counter1 and Timer/Counter0 +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_COM1C = 0xc // Compare Output Mode 1C, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + TCCR1C_FOC1C = 0x20 // Force Output Compare 1C + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1C = 0x8 // Timer/Counter1 Output Compare C Match Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1C = 0x8 // Output Compare Flag 1C + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for PLL: Phase Locked Loop +const ( + // PLLCSR: PLL Status and Control register + PLLCSR_PLLP = 0x1c // PLL prescaler Bits + PLLCSR_PLLE = 0x2 // PLL Enable Bit + PLLCSR_PLOCK = 0x1 // PLL Lock Status Bit +) + +// Bitfields for USB_DEVICE: USB Device Registers +const ( + // UPOE: USB Software Output Enable register + UPOE_UPWE = 0xc0 // USB Buffers Direct Drive enable configuration + UPOE_UPDRV = 0x30 // USB direct drive values + UPOE_DPI = 0x2 // D+ Input value + UPOE_DMI = 0x1 // D- Input value + + // UEINT: USB Endpoint Number Interrupt Register + UEINT_EPINT = 0x1f // Byte Count bits + + // UEBCLX: USB Endpoint Byte Count Register + UEBCLX_BYCT = 0xff // Byte Count bits + + // UEDATX: USB Data Endpoint + UEDATX_DAT = 0xff // Data bits + + // UEIENX: USB Endpoint Interrupt Enable Register + UEIENX_FLERRE = 0x80 // Flow Error Interrupt Enable Flag + UEIENX_NAKINE = 0x40 // NAK IN Interrupt Enable Bit + UEIENX_NAKOUTE = 0x10 // NAK OUT Interrupt Enable Bit + UEIENX_RXSTPE = 0x8 // Received SETUP Interrupt Enable Flag + UEIENX_RXOUTE = 0x4 // Received OUT Data Interrupt Enable Flag + UEIENX_STALLEDE = 0x2 // Stalled Interrupt Enable Flag + UEIENX_TXINE = 0x1 // Transmitter Ready Interrupt Enable Flag + + // UESTA1X: USB Endpoint Status 1 Register + UESTA1X_CTRLDIR = 0x4 // Control Direction + UESTA1X_CURRBK = 0x3 // Current Bank + + // UESTA0X: USB Endpoint Status 0 Register + UESTA0X_CFGOK = 0x80 // Configuration Status Flag + UESTA0X_OVERFI = 0x40 // Overflow Error Interrupt Flag + UESTA0X_UNDERFI = 0x20 // Underflow Error Interrupt Flag + UESTA0X_DTSEQ = 0xc // Data Toggle Sequencing Flag + UESTA0X_NBUSYBK = 0x3 // Busy Bank Flag + + // UECFG1X: USB Endpoint Configuration 1 Register + UECFG1X_EPSIZE = 0x70 // Endpoint Size Bits + UECFG1X_EPBK = 0xc // Endpoint Bank Bits + UECFG1X_ALLOC = 0x2 // Endpoint Allocation Bit + + // UECFG0X: USB Endpoint Configuration 0 Register + UECFG0X_EPTYPE = 0xc0 // Endpoint Type Bits + UECFG0X_EPDIR = 0x1 // Endpoint Direction Bit + + // UECONX: USB Endpoint Control Register + UECONX_STALLRQ = 0x20 // STALL Request Handshake Bit + UECONX_STALLRQC = 0x10 // STALL Request Clear Handshake Bit + UECONX_RSTDT = 0x8 // Reset Data Toggle Bit + UECONX_EPEN = 0x1 // Endpoint Enable Bit + + // UERST: USB Endpoint Reset Register + UERST_EPRST = 0x1f // Endpoint FIFO Reset Bits + + // UENUM: USB Endpoint Number + UENUM_EPNUM = 0x7 // Endpoint Number bits + + // UEINTX: USB Endpoint Interrupt Register + UEINTX_FIFOCON = 0x80 // FIFO Control Bit + UEINTX_NAKINI = 0x40 // NAK IN Received Interrupt Flag + UEINTX_RWAL = 0x20 // Read/Write Allowed Flag + UEINTX_NAKOUTI = 0x10 // NAK OUT Received Interrupt Flag + UEINTX_RXSTPI = 0x8 // Received SETUP Interrupt Flag + UEINTX_RXOUTI = 0x4 // Received OUT Data Interrupt Flag + UEINTX_STALLEDI = 0x2 // STALLEDI Interrupt Flag + UEINTX_TXINI = 0x1 // Transmitter Ready Interrupt Flag + + // UDMFN: USB Device Micro Frame Number + UDMFN_FNCERR = 0x10 // Frame Number CRC Error Flag + + // UDFNUML: USB Device Frame Number High Register + + // UDFNUMH: USB Device Frame Number High Register + UDFNUM_FNUM = 0x7ff // Frame Number Upper Flag + + // UDADDR: USB Device Address Register + UDADDR_ADDEN = 0x80 // Address Enable Bit + UDADDR_UADD = 0x7f // USB Address Bits + + // UDIEN: USB Device Interrupt Enable Register + UDIEN_UPRSME = 0x40 // Upstream Resume Interrupt Enable Bit + UDIEN_EORSME = 0x20 // End Of Resume Interrupt Enable Bit + UDIEN_WAKEUPE = 0x10 // Wake-up CPU Interrupt Enable Bit + UDIEN_EORSTE = 0x8 // End Of Reset Interrupt Enable Bit + UDIEN_SOFE = 0x4 // Start Of Frame Interrupt Enable Bit + UDIEN_SUSPE = 0x1 // Suspend Interrupt Enable Bit + + // UDINT: USB Device Interrupt Register + UDINT_UPRSMI = 0x40 // Upstream Resume Interrupt Flag + UDINT_EORSMI = 0x20 // End Of Resume Interrupt Flag + UDINT_WAKEUPI = 0x10 // Wake-up CPU Interrupt Flag + UDINT_EORSTI = 0x8 // End Of Reset Interrupt Flag + UDINT_SOFI = 0x4 // Start Of Frame Interrupt Flag + UDINT_SUSPI = 0x1 // Suspend Interrupt Flag + + // UDCON: USB Device Control Registers + UDCON_RSTCPU = 0x4 // USB Reset CPU Bit + UDCON_RMWKUP = 0x2 // Remote Wake-up Bit + UDCON_DETACH = 0x1 // Detach Bit + + // USBCON: USB General Control Register + USBCON_USBE = 0x80 // USB macro Enable Bit + USBCON_FRZCLK = 0x20 // Freeze USB Clock Bit + + // REGCR: Regulator Control Register + REGCR_REGDIS = 0x1 // Regulator Disable +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // MCUCR: MCU Control Register + MCUCR_PUD = 0x10 // Pull-up disable + MCUCR_IVSEL = 0x2 // Interrupt Vector Select + MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable + + // MCUSR: MCU Status Register + MCUSR_USBRF = 0x20 // USB reset flag + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BORF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 + + // PRR1: Power Reduction Register1 + PRR1_PRUSB = 0x80 // Power Reduction USB + PRR1_PRUSART1 = 0x1 // Power Reduction USART1 + + // PRR0: Power Reduction Register0 + PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + + // CLKSTA + CLKSTA_RCON = 0x2 + CLKSTA_EXTON = 0x1 + + // CLKSEL1 + CLKSEL1_RCCKSEL = 0xf0 + CLKSEL1_EXCKSEL = 0xf + + // CLKSEL0 + CLKSEL0_RCSUT = 0xc0 + CLKSEL0_EXSUT = 0x30 + CLKSEL0_RCE = 0x8 + CLKSEL0_EXTE = 0x4 + CLKSEL0_CLKS = 0x1 +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EICRB: External Interrupt Control Register B + EICRB_ISC7 = 0xc0 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC6 = 0x30 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC5 = 0xc // External Interrupt 7-4 Sense Control Bit + EICRB_ISC4 = 0x3 // External Interrupt 7-4 Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xff // External Interrupt Request 7 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xff // External Interrupt Flags + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0x1f + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0x3 // Pin Change Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0x3 // Pin Change Interrupt Enables +) + +// Bitfields for USART: USART +const ( + // UCSR1A: USART Control and Status Register A + UCSR1A_RXC1 = 0x80 // USART Receive Complete + UCSR1A_TXC1 = 0x40 // USART Transmitt Complete + UCSR1A_UDRE1 = 0x20 // USART Data Register Empty + UCSR1A_FE1 = 0x10 // Framing Error + UCSR1A_DOR1 = 0x8 // Data overRun + UCSR1A_UPE1 = 0x4 // Parity Error + UCSR1A_U2X1 = 0x2 // Double the USART transmission speed + UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode + + // UCSR1B: USART Control and Status Register B + UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable + UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable + UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable + UCSR1B_RXEN1 = 0x10 // Receiver Enable + UCSR1B_TXEN1 = 0x8 // Transmitter Enable + UCSR1B_UCSZ12 = 0x4 // Character Size + UCSR1B_RXB81 = 0x2 // Receive Data Bit 8 + UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8 + + // UCSR1C: USART Control and Status Register C + UCSR1C_UMSEL1 = 0xc0 // USART Mode Select + UCSR1C_UPM1 = 0x30 // Parity Mode Bits + UCSR1C_USBS1 = 0x8 // Stop Bit Select + UCSR1C_UCSZ1 = 0x6 // Character Size + UCSR1C_UCPOL1 = 0x1 // Clock Polarity + + // UCSR1D: USART Control and Status Register D + UCSR1D_CTSEN = 0x2 // CTS Enable + UCSR1D_RTSEN = 0x1 // RTS Enable +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable + + // WDTCKD: Watchdog Timer Clock Divider + WDTCKD_WDEWIF = 0x8 // Watchdog Early Warning Interrupt Flag + WDTCKD_WDEWIE = 0x4 // Watchdog Early Warning Interrupt Enable + WDTCKD_WCLKD = 0x3 // Watchdog Timer Clock Dividers +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // ACMUX: Analog Comparator Input Multiplexer + ACMUX_CMUX = 0x7 // Analog Comparator Selection Bits + + // DIDR1 + DIDR1_AIN7D = 0x80 // AIN7 Digital Input Disable + DIDR1_AIN6D = 0x40 // AIN6 Digital Input Disable + DIDR1_AIN5D = 0x20 // AIN5 Digital Input Disable + DIDR1_AIN4D = 0x10 // AIN4 Digital Input Disable + DIDR1_AIN3D = 0x8 // AIN3 Digital Input Disable + DIDR1_AIN2D = 0x4 // AIN2 Digital Input Disable + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) diff --git a/src/device/avr/atmega32u2.ld b/src/device/avr/atmega32u2.ld new file mode 100644 index 00000000..8390cdd8 --- /dev/null +++ b/src/device/avr/atmega32u2.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega32U2.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_size = 0x400; +__num_isrs = 29; diff --git a/src/device/avr/atmega32u4.go b/src/device/avr/atmega32u4.go new file mode 100644 index 00000000..ac308bf9 --- /dev/null +++ b/src/device/avr/atmega32u4.go @@ -0,0 +1,1022 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega32U4.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega32u4 + +// Device information for the ATmega32U4. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega32U4" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_INT3 = 4 // External Interrupt Request 3 + IRQ_Reserved1 = 5 // Reserved1 + IRQ_Reserved2 = 6 // Reserved2 + IRQ_INT6 = 7 // External Interrupt Request 6 + IRQ_Reserved3 = 8 // Reserved3 + IRQ_PCINT0 = 9 // Pin Change Interrupt Request 0 + IRQ_USB_GEN = 10 // USB General Interrupt Request + IRQ_USB_COM = 11 // USB Endpoint/Pipe Interrupt Communication Request + IRQ_WDT = 12 // Watchdog Time-out Interrupt + IRQ_Reserved4 = 13 // Reserved4 + IRQ_Reserved5 = 14 // Reserved5 + IRQ_Reserved6 = 15 // Reserved6 + IRQ_TIMER1_CAPT = 16 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 17 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 18 // Timer/Counter1 Compare Match B + IRQ_TIMER1_COMPC = 19 // Timer/Counter1 Compare Match C + IRQ_TIMER1_OVF = 20 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 21 // Timer/Counter0 Compare Match A + IRQ_TIMER0_COMPB = 22 // Timer/Counter0 Compare Match B + IRQ_TIMER0_OVF = 23 // Timer/Counter0 Overflow + IRQ_SPI_STC = 24 // SPI Serial Transfer Complete + IRQ_USART1_RX = 25 // USART1, Rx Complete + IRQ_USART1_UDRE = 26 // USART1 Data register Empty + IRQ_USART1_TX = 27 // USART1, Tx Complete + IRQ_ANALOG_COMP = 28 // Analog Comparator + IRQ_ADC = 29 // ADC Conversion Complete + IRQ_EE_READY = 30 // EEPROM Ready + IRQ_TIMER3_CAPT = 31 // Timer/Counter3 Capture Event + IRQ_TIMER3_COMPA = 32 // Timer/Counter3 Compare Match A + IRQ_TIMER3_COMPB = 33 // Timer/Counter3 Compare Match B + IRQ_TIMER3_COMPC = 34 // Timer/Counter3 Compare Match C + IRQ_TIMER3_OVF = 35 // Timer/Counter3 Overflow + IRQ_TWI = 36 // 2-wire Serial Interface + IRQ_SPM_READY = 37 // Store Program Memory Read + IRQ_TIMER4_COMPA = 38 // Timer/Counter4 Compare Match A + IRQ_TIMER4_COMPB = 39 // Timer/Counter4 Compare Match B + IRQ_TIMER4_COMPD = 40 // Timer/Counter4 Compare Match D + IRQ_TIMER4_OVF = 41 // Timer/Counter4 Overflow + IRQ_TIMER4_FPF = 42 // Timer/Counter4 Fault Protection Interrupt + IRQ_max = 42 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // I/O Port + PORT = struct { + PORTD __reg + DDRD __reg + PIND __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + }{ + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // USART + USART = struct { + UDR1 __reg + UCSR1A __reg + UCSR1B __reg + UCSR1C __reg + UCSR1D __reg + UBRR1L __reg + UBRR1H __reg + }{ + UDR1: 0xce, // USART I/O Data Register + UCSR1A: 0xc8, // USART Control and Status Register A + UCSR1B: 0xc9, // USART Control and Status Register B + UCSR1C: 0xca, // USART Control and Status Register C + UCSR1D: 0xcb, // USART Control and Status Register D + UBRR1L: 0xcc, // USART Baud Rate Register Bytes + UBRR1H: 0xcc, // USART Baud Rate Register Bytes + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Low Bytes + EEARH: 0x41, // EEPROM Address Register Low Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + GTCCR __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + GTCCR: 0x43, // General Timer/Counter Control Register + } + + // Timer/Counter, 10-bit + TC10 = struct { + TCCR4A __reg + TCCR4B __reg + TCCR4C __reg + TCCR4D __reg + TCCR4E __reg + TCNT4 __reg + TC4H __reg + OCR4A __reg + OCR4B __reg + OCR4C __reg + OCR4D __reg + TIMSK4 __reg + TIFR4 __reg + DT4 __reg + }{ + TCCR4A: 0xc0, // Timer/Counter4 Control Register A + TCCR4B: 0xc1, // Timer/Counter4 Control Register B + TCCR4C: 0xc2, // Timer/Counter 4 Control Register C + TCCR4D: 0xc3, // Timer/Counter 4 Control Register D + TCCR4E: 0xc4, // Timer/Counter 4 Control Register E + TCNT4: 0xbe, // Timer/Counter4 Low Bytes + TC4H: 0xbf, // Timer/Counter4 + OCR4A: 0xcf, // Timer/Counter4 Output Compare Register A + OCR4B: 0xd0, // Timer/Counter4 Output Compare Register B + OCR4C: 0xd1, // Timer/Counter4 Output Compare Register C + OCR4D: 0xd2, // Timer/Counter4 Output Compare Register D + TIMSK4: 0x72, // Timer/Counter4 Interrupt Mask Register + TIFR4: 0x39, // Timer/Counter4 Interrupt Flag register + DT4: 0xd4, // Timer/Counter 4 Dead Time Value + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR3A __reg + TCCR3B __reg + TCCR3C __reg + TCNT3L __reg + TCNT3H __reg + OCR3AL __reg + OCR3AH __reg + OCR3BL __reg + OCR3BH __reg + OCR3CL __reg + OCR3CH __reg + ICR3L __reg + ICR3H __reg + TIMSK3 __reg + TIFR3 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + OCR1CL __reg + OCR1CH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR3A: 0x90, // Timer/Counter3 Control Register A + TCCR3B: 0x91, // Timer/Counter3 Control Register B + TCCR3C: 0x92, // Timer/Counter 3 Control Register C + TCNT3L: 0x94, // Timer/Counter3 Bytes + TCNT3H: 0x94, // Timer/Counter3 Bytes + OCR3AL: 0x98, // Timer/Counter3 Output Compare Register A Bytes + OCR3AH: 0x98, // Timer/Counter3 Output Compare Register A Bytes + OCR3BL: 0x9a, // Timer/Counter3 Output Compare Register B Bytes + OCR3BH: 0x9a, // Timer/Counter3 Output Compare Register B Bytes + OCR3CL: 0x9c, // Timer/Counter3 Output Compare Register B Bytes + OCR3CH: 0x9c, // Timer/Counter3 Output Compare Register B Bytes + ICR3L: 0x96, // Timer/Counter3 Input Capture Register Bytes + ICR3H: 0x96, // Timer/Counter3 Input Capture Register Bytes + TIMSK3: 0x71, // Timer/Counter3 Interrupt Mask Register + TIFR3: 0x38, // Timer/Counter3 Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1CL: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + OCR1CH: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EICRB __reg + EIMSK __reg + EIFR __reg + PCMSK0 __reg + PCIFR __reg + PCICR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EICRB: 0x6a, // External Interrupt Control Register B + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + DIDR2 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 0 + DIDR2: 0x7d, // Digital Input Disable Register 2 + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + RCCTRL __reg + CLKPR __reg + SMCR __reg + EIND __reg + RAMPZ __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PRR1 __reg + PRR0 __reg + CLKSTA __reg + CLKSEL1 __reg + CLKSEL0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + RCCTRL: 0x67, // Oscillator Control Register + CLKPR: 0x61, + SMCR: 0x53, // Sleep Mode Control Register + EIND: 0x5c, // Extended Indirect Register + RAMPZ: 0x5b, // Extended Z-pointer Register for ELPM/SPM + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PRR1: 0x65, // Power Reduction Register1 + PRR0: 0x64, // Power Reduction Register0 + CLKSTA: 0xc7, + CLKSEL1: 0xc6, + CLKSEL0: 0xc5, + } + + // Phase Locked Loop + PLL = struct { + PLLCSR __reg + PLLFRQ __reg + }{ + PLLCSR: 0x49, // PLL Status and Control register + PLLFRQ: 0x52, // PLL Frequency Control Register + } + + // USB Device Registers + USB_DEVICE = struct { + UEINT __reg + UEBCHX __reg + UEBCLX __reg + UEDATX __reg + UEIENX __reg + UESTA1X __reg + UESTA0X __reg + UECFG1X __reg + UECFG0X __reg + UECONX __reg + UERST __reg + UENUM __reg + UEINTX __reg + UDMFN __reg + UDFNUML __reg + UDFNUMH __reg + UDADDR __reg + UDIEN __reg + UDINT __reg + UDCON __reg + USBCON __reg + USBINT __reg + USBSTA __reg + UHWCON __reg + }{ + UEINT: 0xf4, + UEBCHX: 0xf3, + UEBCLX: 0xf2, + UEDATX: 0xf1, + UEIENX: 0xf0, + UESTA1X: 0xef, + UESTA0X: 0xee, + UECFG1X: 0xed, + UECFG0X: 0xec, + UECONX: 0xeb, + UERST: 0xea, + UENUM: 0xe9, + UEINTX: 0xe8, + UDMFN: 0xe6, + UDFNUML: 0xe4, + UDFNUMH: 0xe4, + UDADDR: 0xe3, + UDIEN: 0xe2, + UDINT: 0xe1, + UDCON: 0xe0, + USBCON: 0xd8, // USB General Control Register + USBINT: 0xda, + USBSTA: 0xd9, + UHWCON: 0xd7, + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level + EXTENDED_HWBE = 0x8 // Hardware Boot Enable + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTC7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for USART: USART +const ( + // UCSR1A: USART Control and Status Register A + UCSR1A_RXC1 = 0x80 // USART Receive Complete + UCSR1A_TXC1 = 0x40 // USART Transmitt Complete + UCSR1A_UDRE1 = 0x20 // USART Data Register Empty + UCSR1A_FE1 = 0x10 // Framing Error + UCSR1A_DOR1 = 0x8 // Data overRun + UCSR1A_UPE1 = 0x4 // Parity Error + UCSR1A_U2X1 = 0x2 // Double the USART transmission speed + UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode + + // UCSR1B: USART Control and Status Register B + UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable + UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable + UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable + UCSR1B_RXEN1 = 0x10 // Receiver Enable + UCSR1B_TXEN1 = 0x8 // Transmitter Enable + UCSR1B_UCSZ12 = 0x4 // Character Size + UCSR1B_RXB81 = 0x2 // Receive Data Bit 8 + UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8 + + // UCSR1C: USART Control and Status Register C + UCSR1C_UMSEL1 = 0xc0 // USART Mode Select + UCSR1C_UPM1 = 0x30 // Parity Mode Bits + UCSR1C_USBS1 = 0x8 // Stop Bit Select + UCSR1C_UCSZ1 = 0x6 // Character Size + UCSR1C_UCPOL1 = 0x1 // Clock Polarity + + // UCSR1D: USART Control and Status Register D + UCSR1D_CTSEN = 0x2 // CTS Enable + UCSR1D_RTSEN = 0x1 // RTS Enable +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag + + // GTCCR: General Timer/Counter Control Register + GTCCR_TSM = 0x80 // Timer/Counter Synchronization Mode + GTCCR_PSRSYNC = 0x1 // Prescaler Reset Timer/Counter1 and Timer/Counter0 +) + +// Bitfields for TC10: Timer/Counter, 10-bit +const ( + // TCCR4A: Timer/Counter4 Control Register A + TCCR4A_COM4A = 0xc0 // Compare Output Mode 1A, bits + TCCR4A_COM4B = 0x30 // Compare Output Mode 4B, bits + TCCR4A_FOC4A = 0x8 // Force Output Compare Match 4A + TCCR4A_FOC4B = 0x4 // Force Output Compare Match 4B + TCCR4A_PWM4A = 0x2 + TCCR4A_PWM4B = 0x1 + + // TCCR4B: Timer/Counter4 Control Register B + TCCR4B_PWM4X = 0x80 // PWM Inversion Mode + TCCR4B_PSR4 = 0x40 // Prescaler Reset Timer/Counter 4 + TCCR4B_DTPS4 = 0x30 // Dead Time Prescaler Bits + TCCR4B_CS4 = 0xf // Clock Select Bits + + // TCCR4C: Timer/Counter 4 Control Register C + TCCR4C_COM4A1S = 0x80 // Comparator A Output Mode + TCCR4C_COM4A0S = 0x40 // Comparator A Output Mode + TCCR4C_COM4B1S = 0x20 // Comparator B Output Mode + TCCR4C_COM4B0S = 0x10 // Comparator B Output Mode + TCCR4C_COM4D = 0xc // Comparator D Output Mode + TCCR4C_FOC4D = 0x2 // Force Output Compare Match 4D + TCCR4C_PWM4D = 0x1 // Pulse Width Modulator D Enable + + // TCCR4D: Timer/Counter 4 Control Register D + TCCR4D_FPIE4 = 0x80 // Fault Protection Interrupt Enable + TCCR4D_FPEN4 = 0x40 // Fault Protection Mode Enable + TCCR4D_FPNC4 = 0x20 // Fault Protection Noise Canceler + TCCR4D_FPES4 = 0x10 // Fault Protection Edge Select + TCCR4D_FPAC4 = 0x8 // Fault Protection Analog Comparator Enable + TCCR4D_FPF4 = 0x4 // Fault Protection Interrupt Flag + TCCR4D_WGM4 = 0x3 // Waveform Generation Mode bits + + // TCCR4E: Timer/Counter 4 Control Register E + TCCR4E_TLOCK4 = 0x80 // Register Update Lock + TCCR4E_ENHC4 = 0x40 // Enhanced Compare/PWM Mode + TCCR4E_OC4OE = 0x3f // Output Compare Override Enable bit + + // TIMSK4: Timer/Counter4 Interrupt Mask Register + TIMSK4_OCIE4D = 0x80 // Timer/Counter4 Output Compare D Match Interrupt Enable + TIMSK4_OCIE4A = 0x40 // Timer/Counter4 Output Compare A Match Interrupt Enable + TIMSK4_OCIE4B = 0x20 // Timer/Counter4 Output Compare B Match Interrupt Enable + TIMSK4_TOIE4 = 0x4 // Timer/Counter4 Overflow Interrupt Enable + + // TIFR4: Timer/Counter4 Interrupt Flag register + TIFR4_OCF4D = 0x80 // Output Compare Flag 4D + TIFR4_OCF4A = 0x40 // Output Compare Flag 4A + TIFR4_OCF4B = 0x20 // Output Compare Flag 4B + TIFR4_TOV4 = 0x4 // Timer/Counter4 Overflow Flag + + // DT4: Timer/Counter 4 Dead Time Value + DT4_DT4L = 0xff // Timer/Counter 4 Dead Time Value Bits +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR3A: Timer/Counter3 Control Register A + TCCR3A_COM3A = 0xc0 // Compare Output Mode 1A, bits + TCCR3A_COM3B = 0x30 // Compare Output Mode 3B, bits + TCCR3A_COM3C = 0xc // Compare Output Mode 3C, bits + TCCR3A_WGM3 = 0x3 // Waveform Generation Mode + + // TCCR3B: Timer/Counter3 Control Register B + TCCR3B_ICNC3 = 0x80 // Input Capture 3 Noise Canceler + TCCR3B_ICES3 = 0x40 // Input Capture 3 Edge Select + TCCR3B_WGM3 = 0x18 // Waveform Generation Mode + TCCR3B_CS3 = 0x7 // Prescaler source of Timer/Counter 3 + + // TCCR3C: Timer/Counter 3 Control Register C + TCCR3C_FOC3A = 0x80 // Force Output Compare 3A + TCCR3C_FOC3B = 0x40 // Force Output Compare 3B + TCCR3C_FOC3C = 0x20 // Force Output Compare 3C + + // TIMSK3: Timer/Counter3 Interrupt Mask Register + TIMSK3_ICIE3 = 0x20 // Timer/Counter3 Input Capture Interrupt Enable + TIMSK3_OCIE3C = 0x8 // Timer/Counter3 Output Compare C Match Interrupt Enable + TIMSK3_OCIE3B = 0x4 // Timer/Counter3 Output Compare B Match Interrupt Enable + TIMSK3_OCIE3A = 0x2 // Timer/Counter3 Output Compare A Match Interrupt Enable + TIMSK3_TOIE3 = 0x1 // Timer/Counter3 Overflow Interrupt Enable + + // TIFR3: Timer/Counter3 Interrupt Flag register + TIFR3_ICF3 = 0x20 // Input Capture Flag 3 + TIFR3_OCF3C = 0x8 // Output Compare Flag 3C + TIFR3_OCF3B = 0x4 // Output Compare Flag 3B + TIFR3_OCF3A = 0x2 // Output Compare Flag 3A + TIFR3_TOV3 = 0x1 // Timer/Counter3 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_COM1C = 0xc // Compare Output Mode 1C, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + TCCR1C_FOC1C = 0x20 // Force Output Compare 1C + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1C = 0x8 // Timer/Counter1 Output Compare C Match Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1C = 0x8 // Output Compare Flag 1C + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EICRB: External Interrupt Control Register B + EICRB_ISC7 = 0xc0 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC6 = 0x30 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC5 = 0xc // External Interrupt 7-4 Sense Control Bit + EICRB_ISC4 = 0x3 // External Interrupt 7-4 Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xff // External Interrupt Request 7 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xff // External Interrupt Flags + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF0 = 0x1 // Pin Change Interrupt Flag 0 + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE0 = 0x1 // Pin Change Interrupt Enable 0 +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable + + // DIDR2: Digital Input Disable Register 2 + DIDR2_ADC13D = 0x20 // ADC13 Digital input Disable + DIDR2_ADC12D = 0x10 // ADC12 Digital input Disable + DIDR2_ADC11D = 0x8 // ADC11 Digital input Disable + DIDR2_ADC10D = 0x4 // ADC10 Digital input Disable + DIDR2_ADC9D = 0x2 // ADC9 Digital input Disable + DIDR2_ADC8D = 0x1 // ADC8 Digital input Disable +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // RCCTRL: Oscillator Control Register + RCCTRL_RCFREQ = 0x1 + + // CLKPR + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // RAMPZ: Extended Z-pointer Register for ELPM/SPM + RAMPZ_Res = 0xfc // Reserved + RAMPZ_RAMPZ = 0x3 // Extended Z-Pointer Value + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 + + // PRR1: Power Reduction Register1 + PRR1_PRUSB = 0x80 // Power Reduction USB + PRR1_PRTIM4 = 0x10 // Power Reduction Timer/Counter4 + PRR1_PRTIM3 = 0x8 // Power Reduction Timer/Counter3 + PRR1_PRUSART1 = 0x1 // Power Reduction USART1 + + // PRR0: Power Reduction Register0 + PRR0_PRTWI = 0x80 // Power Reduction TWI + PRR0_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR0_PRUSART0 = 0x2 // Power Reduction USART + PRR0_PRADC = 0x1 // Power Reduction ADC + + // CLKSTA + CLKSTA_RCON = 0x2 + CLKSTA_EXTON = 0x1 + + // CLKSEL1 + CLKSEL1_RCCKSEL = 0xf0 + CLKSEL1_EXCKSEL = 0xf + + // CLKSEL0 + CLKSEL0_RCSUT = 0xc0 + CLKSEL0_EXSUT = 0x30 + CLKSEL0_RCE = 0x8 + CLKSEL0_EXTE = 0x4 + CLKSEL0_CLKS = 0x1 +) + +// Bitfields for PLL: Phase Locked Loop +const ( + // PLLCSR: PLL Status and Control register + PLLCSR_PINDIV = 0x10 // PLL prescaler Bit 2 + PLLCSR_PLLE = 0x2 // PLL Enable Bit + PLLCSR_PLOCK = 0x1 // PLL Lock Status Bit + + // PLLFRQ: PLL Frequency Control Register + PLLFRQ_PINMUX = 0x80 + PLLFRQ_PLLUSB = 0x40 + PLLFRQ_PLLTM = 0x30 + PLLFRQ_PDIV = 0xf +) + +// Bitfields for USB_DEVICE: USB Device Registers +const ( + // UEDATX + UEDATX_DAT = 0xff + + // UEIENX + UEIENX_FLERRE = 0x80 + UEIENX_NAKINE = 0x40 + UEIENX_NAKOUTE = 0x10 + UEIENX_RXSTPE = 0x8 + UEIENX_RXOUTE = 0x4 + UEIENX_STALLEDE = 0x2 + UEIENX_TXINE = 0x1 + + // UESTA1X + UESTA1X_CTRLDIR = 0x4 + UESTA1X_CURRBK = 0x3 + + // UESTA0X + UESTA0X_CFGOK = 0x80 + UESTA0X_OVERFI = 0x40 + UESTA0X_UNDERFI = 0x20 + UESTA0X_DTSEQ = 0xc + UESTA0X_NBUSYBK = 0x3 + + // UECFG1X + UECFG1X_EPSIZE = 0x70 + UECFG1X_EPBK = 0xc + UECFG1X_ALLOC = 0x2 + + // UECFG0X + UECFG0X_EPTYPE = 0xc0 + UECFG0X_EPDIR = 0x1 + + // UECONX + UECONX_STALLRQ = 0x20 + UECONX_STALLRQC = 0x10 + UECONX_RSTDT = 0x8 + UECONX_EPEN = 0x1 + + // UERST + UERST_EPRST = 0x7f + + // UEINTX + UEINTX_FIFOCON = 0x80 + UEINTX_NAKINI = 0x40 + UEINTX_RWAL = 0x20 + UEINTX_NAKOUTI = 0x10 + UEINTX_RXSTPI = 0x8 + UEINTX_RXOUTI = 0x4 + UEINTX_STALLEDI = 0x2 + UEINTX_TXINI = 0x1 + + // UDMFN + UDMFN_FNCERR = 0x10 + + // UDADDR + UDADDR_ADDEN = 0x80 + UDADDR_UADD = 0x7f + + // UDIEN + UDIEN_UPRSME = 0x40 + UDIEN_EORSME = 0x20 + UDIEN_WAKEUPE = 0x10 + UDIEN_EORSTE = 0x8 + UDIEN_SOFE = 0x4 + UDIEN_SUSPE = 0x1 + + // UDINT + UDINT_UPRSMI = 0x40 + UDINT_EORSMI = 0x20 + UDINT_WAKEUPI = 0x10 + UDINT_EORSTI = 0x8 + UDINT_SOFI = 0x4 + UDINT_SUSPI = 0x1 + + // UDCON + UDCON_LSM = 0x4 // USB low speed mode + UDCON_RSTCPU = 0x8 + UDCON_RMWKUP = 0x2 + UDCON_DETACH = 0x1 + + // USBCON: USB General Control Register + USBCON_USBE = 0x80 + USBCON_FRZCLK = 0x20 + USBCON_OTGPADE = 0x10 + USBCON_VBUSTE = 0x1 + + // USBINT + USBINT_VBUSTI = 0x1 + + // USBSTA + USBSTA_SPEED = 0x8 + USBSTA_VBUS = 0x1 + + // UHWCON + UHWCON_UVREGE = 0x1 +) diff --git a/src/device/avr/atmega32u4.ld b/src/device/avr/atmega32u4.ld new file mode 100644 index 00000000..02ff7f0c --- /dev/null +++ b/src/device/avr/atmega32u4.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega32U4.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x8000; +__ram_size = 0xa00; +__num_isrs = 43; diff --git a/src/device/avr/atmega406.go b/src/device/avr/atmega406.go new file mode 100644 index 00000000..ec6d6e53 --- /dev/null +++ b/src/device/avr/atmega406.go @@ -0,0 +1,613 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega406.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega406 + +// Device information for the ATmega406. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega406" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset + IRQ_BPINT = 1 // Battery Protection Interrupt + IRQ_INT0 = 2 // External Interrupt Request 0 + IRQ_INT1 = 3 // External Interrupt Request 1 + IRQ_INT2 = 4 // External Interrupt Request 2 + IRQ_INT3 = 5 // External Interrupt Request 3 + IRQ_PCINT0 = 6 // Pin Change Interrupt 0 + IRQ_PCINT1 = 7 // Pin Change Interrupt 1 + IRQ_WDT = 8 // Watchdog Timeout Interrupt + IRQ_WAKE_UP = 9 // Wakeup timer overflow + IRQ_TIM1_COMP = 10 // Timer/Counter 1 Compare Match + IRQ_TIM1_OVF = 11 // Timer/Counter 1 Overflow + IRQ_TIM0_COMPA = 12 // Timer/Counter0 Compare A Match + IRQ_TIM0_COMPB = 13 // Timer/Counter0 Compare B Match + IRQ_TIM0_OVF = 14 // Timer/Counter0 Overflow + IRQ_TWI_BUS_CD = 15 // Two-Wire Bus Connect/Disconnect + IRQ_TWI = 16 // Two-Wire Serial Interface + IRQ_VADC = 17 // Voltage ADC Conversion Complete + IRQ_CCADC_CONV = 18 // Coulomb Counter ADC Conversion Complete + IRQ_CCADC_REG_CUR = 19 // Coloumb Counter ADC Regular Current + IRQ_CCADC_ACC = 20 // Coloumb Counter ADC Accumulator + IRQ_EE_READY = 21 // EEPROM Ready + IRQ_SPM_READY = 22 // Store Program Memory Ready + IRQ_max = 22 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + HIGH __reg + LOW __reg + }{ + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog-to-Digital Converter + ADC = struct { + VADMUX __reg + VADCL __reg + VADCH __reg + VADCSR __reg + }{ + VADMUX: 0x7c, // The VADC multiplexer Selection Register + VADCL: 0x78, // VADC Data Register Bytes + VADCH: 0x78, // VADC Data Register Bytes + VADCSR: 0x7a, // The VADC Control and Status register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCICR __reg + PCIFR __reg + PCMSK1 __reg + PCMSK0 __reg + }{ + EICRA: 0x69, // External Interrupt Control Register + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + PCMSK1: 0x6c, // Pin Change Enable Mask Register 1 + PCMSK0: 0x6b, // Pin Change Enable Mask Register 0 + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1B __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + TIMSK1 __reg + TIFR1 __reg + GTCCR __reg + }{ + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCNT1L: 0x84, // Timer Counter 1 Bytes + TCNT1H: 0x84, // Timer Counter 1 Bytes + OCR1AL: 0x88, // Output Compare Register 1A Low byte + OCR1AH: 0x89, // Output Compare Register 1A High byte + TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + GTCCR: 0x43, // General Timer/Counter Control Register + } + + // Wakeup Timer + WAKEUP_TIMER = struct { + WUTCSR __reg + }{ + WUTCSR: 0x62, // Wake-up Timer Control Register + } + + // Battery Protection + BATTERY_PROTECTION = struct { + BPPLR __reg + BPCR __reg + CBPTR __reg + BPOCD __reg + BPSCD __reg + BPDUV __reg + BPIR __reg + }{ + BPPLR: 0xf8, // Battery Protection Parameter Lock Register + BPCR: 0xf7, // Battery Protection Control Register + CBPTR: 0xf6, // Current Battery Protection Timing Register + BPOCD: 0xf5, // Battery Protection OverCurrent Detection Level Register + BPSCD: 0xf4, // Battery Protection Short-Circuit Detection Level Register + BPDUV: 0xf3, // Battery Protection Deep Under Voltage Register + BPIR: 0xf2, // Battery Protection Interrupt Register + } + + // FET Control + FET = struct { + FCSR __reg + }{ + FCSR: 0xf0, + } + + // Coulomb Counter + COULOMB_COUNTER = struct { + CADCSRA __reg + CADCSRB __reg + CADICL __reg + CADICH __reg + CADAC3 __reg + CADAC2 __reg + CADAC1 __reg + CADAC0 __reg + CADRCC __reg + CADRDC __reg + }{ + CADCSRA: 0xe4, // CC-ADC Control and Status Register A + CADCSRB: 0xe5, // CC-ADC Control and Status Register B + CADICL: 0xe8, // CC-ADC Instantaneous Current + CADICH: 0xe8, // CC-ADC Instantaneous Current + CADAC3: 0xe3, // ADC Accumulate Current + CADAC2: 0xe2, // ADC Accumulate Current + CADAC1: 0xe1, // ADC Accumulate Current + CADAC0: 0xe0, // ADC Accumulate Current + CADRCC: 0xe6, // CC-ADC Regular Charge Current + CADRDC: 0xe7, // CC-ADC Regular Discharge Current + } + + // Cell Balancing + CELL_BALANCING = struct { + CBCR __reg + }{ + CBCR: 0xf1, // Cell Balancing Control Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + MCUCR __reg + MCUSR __reg + FOSCCAL __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + CCSR __reg + DIDR0 __reg + PRR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + FOSCCAL: 0x66, // Fast Oscillator Calibration Value + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + CCSR: 0xc0, // Clock Control and Status Register + DIDR0: 0x7e, // Digital Input Disable Register + PRR0: 0x64, // Power Reduction Register 0 + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0A __reg + TCCR0B __reg + TCNT0 __reg + OCR0A __reg + OCR0B __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR0A: 0x44, // Timer/Counter0 Control Register + TCCR0B: 0x45, // Timer/Counter0 Control Register + TCNT0: 0x46, // Timer Counter 0 + OCR0A: 0x47, // Output compare Register A + OCR0B: 0x48, // Output compare Register B + TIMSK0: 0x6e, // Timer/Counter Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter Interrupt Flag register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + PORTD __reg + DDRD __reg + PIND __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + PORTD: 0x2b, // Data Register, Port D + DDRD: 0x2a, // Data Direction Register, Port D + PIND: 0x29, // Input Pins, Port D + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // Two Wire Serial Interface + TWI = struct { + TWBCSR __reg + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWBCSR: 0xbe, // TWI Bus Control and Status Register + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // Bandgap + BANDGAP = struct { + BGCRR __reg + BGCCR __reg + }{ + BGCRR: 0xd1, // Bandgap Calibration of Resistor Ladder + BGCCR: 0xd0, // Bandgap Calibration Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Bytes + EEARH: 0x41, // EEPROM Address Register Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // HIGH + HIGH_OCDEN = 0x2 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x1 // JTAG Interface Enabled + + // LOW + LOW_WDTON = 0x80 // Watchdog timer always on + LOW_EESAVE = 0x40 // Preserve EEPROM through the Chip Erase cycle + LOW_BOOTSZ = 0x30 // Select boot size + LOW_BOOTRST = 0x8 // Boot Reset vector Enabled + LOW_SUT_CKSEL = 0x7 // Clock Selection +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // VADMUX: The VADC multiplexer Selection Register + VADMUX_VADMUX = 0xf // Analog Channel and Gain Selection Bits + + // VADCSR: The VADC Control and Status register + VADCSR_VADEN = 0x8 // VADC Enable + VADCSR_VADSC = 0x4 // VADC Satrt Conversion + VADCSR_VADCCIF = 0x2 // VADC Conversion Complete Interrupt Flag + VADCSR_VADCCIE = 0x1 // VADC Conversion Complete Interrupt Enable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register + EICRA_ISC3 = 0xc0 // External Interrupt Sense Control 3 Bits + EICRA_ISC2 = 0x30 // External Interrupt Sense Control 2 Bits + EICRA_ISC1 = 0xc // External Interrupt Sense Control 1 Bits + EICRA_ISC0 = 0x3 // External Interrupt Sense Control 0 Bits + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xf // External Interrupt Request 1 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xf // External Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0x3 // Pin Change Interrupt Enables + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0x3 // Pin Change Interrupt Flags +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_CTC1 = 0x8 // Clear Timer/Counter on Compare Match + TCCR1B_CS1 = 0x7 // Clock Select1 bits + + // TIMSK1: Timer/Counter Interrupt Mask Register + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_OCF1A = 0x2 // Timer/Counter1 Output Compare Flag A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // GTCCR: General Timer/Counter Control Register + GTCCR_TSM = 0x80 // Timer/Counter Synchronization Mode + GTCCR_PSRSYNC = 0x1 // Prescaler Reset +) + +// Bitfields for WAKEUP_TIMER: Wakeup Timer +const ( + // WUTCSR: Wake-up Timer Control Register + WUTCSR_WUTIF = 0x80 // Wake-up Timer Interrupt Flag + WUTCSR_WUTIE = 0x40 // Wake-up Timer Interrupt Enable + WUTCSR_WUTCF = 0x20 // Wake-up timer Calibration Flag + WUTCSR_WUTR = 0x10 // Wake-up Timer Reset + WUTCSR_WUTE = 0x8 // Wake-up Timer Enable + WUTCSR_WUTP = 0x7 // Wake-up Timer Prescaler Bits +) + +// Bitfields for BATTERY_PROTECTION: Battery Protection +const ( + // BPPLR: Battery Protection Parameter Lock Register + BPPLR_BPPLE = 0x2 // Battery Protection Parameter Lock Enable + BPPLR_BPPL = 0x1 // Battery Protection Parameter Lock + + // BPCR: Battery Protection Control Register + BPCR_DUVD = 0x8 + BPCR_SCD = 0x4 + BPCR_DCD = 0x2 + BPCR_CCD = 0x1 + + // CBPTR: Current Battery Protection Timing Register + CBPTR_SCPT = 0xf0 + CBPTR_OCPT = 0xf + + // BPOCD: Battery Protection OverCurrent Detection Level Register + BPOCD_DCDL = 0xf0 + BPOCD_CCDL = 0xf + + // BPSCD: Battery Protection Short-Circuit Detection Level Register + BPSCD_SCDL = 0xf + + // BPDUV: Battery Protection Deep Under Voltage Register + BPDUV_DUVT = 0x30 + BPDUV_DUDL = 0xf + + // BPIR: Battery Protection Interrupt Register + BPIR_DUVIF = 0x80 // Deep Under-voltage Early Warning Interrupt Flag + BPIR_COCIF = 0x40 // Charge Over-current Protection Activated Interrupt Flag + BPIR_DOCIF = 0x20 + BPIR_SCIF = 0x10 + BPIR_DUVIE = 0x8 // Deep Under-voltage Early Warning Interrupt Enable + BPIR_COCIE = 0x4 + BPIR_DOCIE = 0x2 + BPIR_SCIE = 0x1 +) + +// Bitfields for FET: FET Control +const ( + // FCSR + FCSR_PWMOC = 0x20 // Pulse Width Modulation of OC output + FCSR_PWMOPC = 0x10 // Pulse Width Modulation Modulation of OPC output + FCSR_CPS = 0x8 // Current Protection Status + FCSR_DFE = 0x4 // Discharge FET Enable + FCSR_CFE = 0x2 // Charge FET Enable + FCSR_PFD = 0x1 // Precharge FET disable +) + +// Bitfields for COULOMB_COUNTER: Coulomb Counter +const ( + // CADCSRA: CC-ADC Control and Status Register A + CADCSRA_CADEN = 0x80 // When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled. + CADCSRA_CADUB = 0x20 // CC_ADC Update Busy + CADCSRA_CADAS = 0x18 // CC_ADC Accumulate Current Select Bits + CADCSRA_CADSI = 0x6 // The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. + CADCSRA_CADSE = 0x1 // When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode. + + // CADCSRB: CC-ADC Control and Status Register B + CADCSRB_CADACIE = 0x40 + CADCSRB_CADRCIE = 0x20 // Regular Current Interrupt Enable + CADCSRB_CADICIE = 0x10 // CAD Instantenous Current Interrupt Enable + CADCSRB_CADACIF = 0x4 // CC-ADC Accumulate Current Interrupt Flag + CADCSRB_CADRCIF = 0x2 // CC-ADC Accumulate Current Interrupt Flag + CADCSRB_CADICIF = 0x1 // CC-ADC Instantaneous Current Interrupt Flag +) + +// Bitfields for CELL_BALANCING: Cell Balancing +const ( + // CBCR: Cell Balancing Control Register + CBCR_CBE = 0xf // Cell Balancing Enables +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // MCUCR: MCU Control Register + MCUCR_JTD = 0x80 // JTAG Disable + MCUCR_PUD = 0x10 // Pull-up disable + MCUCR_IVSEL = 0x2 // Interrupt Vector Select + MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable + + // MCUSR: MCU Status Register + MCUSR_JTRF = 0x10 // JTAG Reset Flag + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BODRF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // CCSR: Clock Control and Status Register + CCSR_XOE = 0x2 // 32 kHz Crystal Oscillator Enable + CCSR_ACS = 0x1 // Asynchronous Clock Select + + // PRR0: Power Reduction Register 0 + PRR0_PRTWI = 0x8 // Power Reduction TWI + PRR0_PRTIM1 = 0x4 // Power Reduction Timer/Counter1 + PRR0_PRTIM0 = 0x2 // Power Reduction Timer/Counter0 + PRR0_PRVADC = 0x1 // Power Reduction V-ADC +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0A: Timer/Counter0 Control Register + TCCR0A_COM0A = 0xc0 // Force Output Compare + TCCR0A_COM0B = 0x30 + TCCR0A_WGM0 = 0x3 // Clock Select0 bits + + // TCCR0B: Timer/Counter0 Control Register + TCCR0B_FOC0A = 0x80 // Force Output Compare + TCCR0B_FOC0B = 0x40 // Waveform Generation Mode + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select0 bits + + // OCR0A: Output compare Register A + OCR0A_OCR0A = 0xff + + // OCR0B: Output compare Register B + OCR0B_OCR0B = 0xff + + // TIMSK0: Timer/Counter Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Output Compare Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Output Compare Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Overflow Interrupt Enable + + // TIFR0: Timer/Counter Interrupt Flag register + TIFR0_OCF0B = 0x4 // Output Compare Flag + TIFR0_OCF0A = 0x2 // Output Compare Flag + TIFR0_TOV0 = 0x1 // Overflow Flag +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWBCSR: TWI Bus Control and Status Register + TWBCSR_TWBCIF = 0x80 // TWI Bus Connect/Disconnect Interrupt Flag + TWBCSR_TWBCIE = 0x40 // TWI Bus Connect/Disconnect Interrupt Enable + TWBCSR_TWBDT = 0x6 // TWI Bus Disconnect Time-out Period + TWBCSR_TWBCIP = 0x1 // TWI Bus Connect/Disconnect Interrupt Polarity + + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for BANDGAP: Bandgap +const ( + // BGCCR: Bandgap Calibration Register + BGCCR_BGD = 0x80 // Setting the BGD bit to one will disable the bandgap voltage reference. This bit must be cleared before enabling CC-ADC or V-ADC, and must remain unset while either ADC is enabled. + BGCCR_BGCC = 0x3f // BG Calibration of PTAT Current Bits +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Programming Enable + EECR_EEPE = 0x2 // EEPROM Programming Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) diff --git a/src/device/avr/atmega406.ld b/src/device/avr/atmega406.ld new file mode 100644 index 00000000..cda70056 --- /dev/null +++ b/src/device/avr/atmega406.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega406.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0xa000; +__ram_size = 0x800; +__num_isrs = 23; diff --git a/src/device/avr/atmega48.go b/src/device/avr/atmega48.go new file mode 100644 index 00000000..000fcaa5 --- /dev/null +++ b/src/device/avr/atmega48.go @@ -0,0 +1,633 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega48.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega48 + +// Device information for the ATmega48. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega48" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_PCINT0 = 3 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 4 // Pin Change Interrupt Request 0 + IRQ_PCINT2 = 5 // Pin Change Interrupt Request 1 + IRQ_WDT = 6 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 7 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 8 // Timer/Counter2 Compare Match A + IRQ_TIMER2_OVF = 9 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 10 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 11 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 12 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 13 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 14 // TimerCounter0 Compare Match A + IRQ_TIMER0_COMPB = 15 // TimerCounter0 Compare Match B + IRQ_TIMER0_OVF = 16 // Timer/Couner0 Overflow + IRQ_SPI_STC = 17 // SPI Serial Transfer Complete + IRQ_USART_RX = 18 // USART Rx Complete + IRQ_USART_UDRE = 19 // USART, Data Register Empty + IRQ_USART_TX = 20 // USART Tx Complete + IRQ_ADC = 21 // ADC Conversion Complete + IRQ_EE_READY = 22 // EEPROM Ready + IRQ_ANALOG_COMP = 23 // Analog Comparator + IRQ_TWI = 24 // Two-wire Serial Interface + IRQ_SPM_Ready = 25 // Store Program Memory Read + IRQ_max = 25 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + ADCSRB __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // The ADC Control and Status register A + ADCSRB: 0x7b, // The ADC Control and Status register B + DIDR0: 0x7e, // Digital Input Disable Register + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // I/O Port + PORT = struct { + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + }{ + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCICR __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + } + + // Serial Peripheral Interface + SPI = struct { + SPDR __reg + SPSR __reg + SPCR __reg + }{ + SPDR: 0x4e, // SPI Data Register + SPSR: 0x4d, // SPI Status Register + SPCR: 0x4c, // SPI Control Register + } + + // CPU Registers + CPU = struct { + PRR __reg + OSCCAL __reg + CLKPR __reg + SREG __reg + SPL __reg + SPH __reg + SPMCSR __reg + MCUCR __reg + MCUSR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + PRR: 0x64, // Power Reduction Register + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + SPMCSR: 0x57, // Store Program Memory Control Register + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose I/O Register 2 + GPIOR1: 0x4a, // General Purpose I/O Register 1 + GPIOR0: 0x3e, // General Purpose I/O Register 0 + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Low Byte + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_SELFPRGEN = 0x1 // Self Programming enable + + // HIGH + HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PC6 as i/o pin) + HIGH_DWEN = 0x40 // Debug Wire enable + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watch-dog Timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTB0 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0xc0 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TIMSK1: Timer/Counter Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output CompareB Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output CompareA Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 + TCCR1C_FOC1B = 0x40 +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2B = 0x4 // Output Compare Flag 2B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Output Mode bits + TCCR2A_COM2B = 0x30 // Compare Output Mode bits + TCCR2A_WGM2 = 0x3 // Waveform Genration Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy + ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0xf // Analog Channel Selection Bits + + // ADCSRA: The ADC Control and Status register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCSRB: The ADC Control and Status register B + ADCSRB_ACME = 0x40 + ADCSRB_ADTS = 0x7 // ADC Auto Trigger Source bits + + // DIDR0: Digital Input Disable Register + DIDR0_ADC5D = 0x20 + DIDR0_ADC4D = 0x10 + DIDR0_ADC3D = 0x8 + DIDR0_ADC2D = 0x4 + DIDR0_ADC1D = 0x2 + DIDR0_ADC0D = 0x1 +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register + EICRA_ISC1 = 0xc // External Interrupt Sense Control 1 Bits + EICRA_ISC0 = 0x3 // External Interrupt Sense Control 0 Bits + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0x3 // External Interrupt Request 1 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0x3 // External Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0x7 // Pin Change Interrupt Enables + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0x7f // Pin Change Enable Masks + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0x7 // Pin Change Interrupt Flags +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects +) + +// Bitfields for CPU: CPU Registers +const ( + // PRR: Power Reduction Register + PRR_PRTWI = 0x80 // Power Reduction TWI + PRR_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read-While-Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read-While-Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SELFPRGEN = 0x1 // Self Programming Enable + + // MCUCR: MCU Control Register + MCUCR_PUD = 0x10 // Pull-up Disable + + // MCUSR: MCU Status Register + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BORF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode + SMCR_SE = 0x1 // Sleep Enable +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) diff --git a/src/device/avr/atmega48.ld b/src/device/avr/atmega48.ld new file mode 100644 index 00000000..f65c92f8 --- /dev/null +++ b/src/device/avr/atmega48.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega48.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x1000; +__ram_size = 0x200; +__num_isrs = 26; diff --git a/src/device/avr/atmega4808.go b/src/device/avr/atmega4808.go new file mode 100644 index 00000000..8cea0df1 --- /dev/null +++ b/src/device/avr/atmega4808.go @@ -0,0 +1,1291 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega4808.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega4808 + +// Device information for the ATmega4808. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega4808" + ARCH = "AVR8X" + FAMILY = "AVR MEGA" +) + +// Interrupts +const ( + IRQ_NMI = 1 // + IRQ_VLM = 2 // + IRQ_CNT = 3 // + IRQ_PIT = 4 // + IRQ_CCL = 5 // + IRQ_PORT = 6 // + IRQ_LUNF = 7 // + IRQ_OVF = 7 // + IRQ_HUNF = 8 // + IRQ_LCMP0 = 9 // + IRQ_CMP0 = 9 // + IRQ_CMP1 = 10 // + IRQ_LCMP1 = 10 // + IRQ_CMP2 = 11 // + IRQ_LCMP2 = 11 // + IRQ_INT = 12 // + IRQ_INT = 13 // + IRQ_TWIS = 14 // + IRQ_TWIM = 15 // + IRQ_INT = 16 // + IRQ_RXC = 17 // + IRQ_DRE = 18 // + IRQ_TXC = 19 // + IRQ_PORT = 20 // + IRQ_AC = 21 // + IRQ_RESRDY = 22 // + IRQ_WCOMP = 23 // + IRQ_PORT = 24 // + IRQ_INT = 25 // + IRQ_RXC = 26 // + IRQ_DRE = 27 // + IRQ_TXC = 28 // + IRQ_PORT = 29 // + IRQ_EE = 30 // + IRQ_RXC = 31 // + IRQ_DRE = 32 // + IRQ_TXC = 33 // + IRQ_PORT = 34 // + IRQ_PORT = 35 // + IRQ_max = 35 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Analog Comparator + AC = struct { + DACREF __reg + MUXCTRLA __reg + }{ + DACREF: 0x4, // Referance scale control + MUXCTRLA: 0x2, // Mux Control A + } + + // Analog to Digital Converter + ADC = struct { + COMMAND __reg + CTRLE __reg + MUXPOS __reg + RESL __reg + RESH __reg + SAMPCTRL __reg + WINHTL __reg + WINHTH __reg + WINLTL __reg + WINLTH __reg + }{ + COMMAND: 0x8, // Command + CTRLE: 0x4, // Control E + MUXPOS: 0x6, // Positive mux input + RESL: 0x10, // ADC Accumulator Result + RESH: 0x10, // ADC Accumulator Result + SAMPCTRL: 0x5, // Sample Control + WINHTL: 0x14, // Window comparator high threshold + WINHTH: 0x14, // Window comparator high threshold + WINLTL: 0x12, // Window comparator low threshold + WINLTH: 0x12, // Window comparator low threshold + } + + // Bod interface + BOD = struct { + VLMCTRLA __reg + }{ + VLMCTRLA: 0x8, // Voltage level monitor Control + } + + // Configurable Custom Logic + CCL = struct { + INTCTRL0 __reg + LUT0CTRLA __reg + LUT0CTRLB __reg + LUT0CTRLC __reg + LUT1CTRLA __reg + LUT1CTRLB __reg + LUT1CTRLC __reg + LUT2CTRLA __reg + LUT2CTRLB __reg + LUT2CTRLC __reg + LUT3CTRLA __reg + LUT3CTRLB __reg + LUT3CTRLC __reg + SEQCTRL0 __reg + TRUTH0 __reg + TRUTH1 __reg + TRUTH2 __reg + TRUTH3 __reg + }{ + INTCTRL0: 0x5, // Interrupt Control 0 + LUT0CTRLA: 0x8, // LUT Control 0 A + LUT0CTRLB: 0x9, // LUT Control 0 B + LUT0CTRLC: 0xa, // LUT Control 0 C + LUT1CTRLA: 0xc, // LUT Control 1 A + LUT1CTRLB: 0xd, // LUT Control 1 B + LUT1CTRLC: 0xe, // LUT Control 1 C + LUT2CTRLA: 0x10, // LUT Control 2 A + LUT2CTRLB: 0x11, // LUT Control 2 B + LUT2CTRLC: 0x12, // LUT Control 2 C + LUT3CTRLA: 0x14, // LUT Control 3 A + LUT3CTRLB: 0x15, // LUT Control 3 B + LUT3CTRLC: 0x16, // LUT Control 3 C + SEQCTRL0: 0x1, // Sequential Control 0 + TRUTH0: 0xb, // Truth 0 + TRUTH1: 0xf, // Truth 1 + TRUTH2: 0x13, // Truth 2 + TRUTH3: 0x17, // Truth 3 + } + + // Clock controller + CLKCTRL = struct { + MCLKCTRLA __reg + MCLKCTRLB __reg + MCLKLOCK __reg + MCLKSTATUS __reg + OSC20MCALIBA __reg + OSC20MCALIBB __reg + OSC20MCTRLA __reg + OSC32KCALIB __reg + OSC32KCTRLA __reg + XOSC32KCTRLA __reg + }{ + MCLKCTRLA: 0x0, // MCLK Control A + MCLKCTRLB: 0x1, // MCLK Control B + MCLKLOCK: 0x2, // MCLK Lock + MCLKSTATUS: 0x3, // MCLK Status + OSC20MCALIBA: 0x11, // OSC20M Calibration A + OSC20MCALIBB: 0x12, // OSC20M Calibration B + OSC20MCTRLA: 0x10, // OSC20M Control A + OSC32KCALIB: 0x19, // OSC32K Calibration + OSC32KCTRLA: 0x18, // OSC32K Control A + XOSC32KCTRLA: 0x1c, // XOSC32K Control A + } + + // CPU + CPU = struct { + CCP __reg + RAMPZ __reg + SPH __reg + SPL __reg + SREG __reg + }{ + CCP: 0x4, // Configuration Change Protection + RAMPZ: 0xb, // Extended Z-pointer Register + SPH: 0xe, // Stack Pointer High + SPL: 0xd, // Stack Pointer Low + SREG: 0xf, // Status Register + } + + // Interrupt Controller + CPUINT = struct { + LVL0PRI __reg + LVL1VEC __reg + }{ + LVL0PRI: 0x2, // Interrupt Level 0 Priority + LVL1VEC: 0x3, // Interrupt Level 1 Priority Vector + } + + // CRCSCAN + CRCSCAN = struct { + }{} + + // Event System + EVSYS = struct { + CHANNEL0 __reg + CHANNEL1 __reg + CHANNEL2 __reg + CHANNEL3 __reg + CHANNEL4 __reg + CHANNEL5 __reg + STROBE __reg + USERADC0 __reg + USERCCLLUT0A __reg + USERCCLLUT0B __reg + USERCCLLUT1A __reg + USERCCLLUT1B __reg + USERCCLLUT2A __reg + USERCCLLUT2B __reg + USERCCLLUT3A __reg + USERCCLLUT3B __reg + USEREVOUTA __reg + USEREVOUTB __reg + USEREVOUTC __reg + USEREVOUTD __reg + USEREVOUTE __reg + USEREVOUTF __reg + USERTCA0 __reg + USERTCB0 __reg + USERTCB1 __reg + USERTCB2 __reg + USERTCB3 __reg + USERUSART0 __reg + USERUSART1 __reg + USERUSART2 __reg + USERUSART3 __reg + }{ + CHANNEL0: 0x10, // Multiplexer Channel 0 + CHANNEL1: 0x11, // Multiplexer Channel 1 + CHANNEL2: 0x12, // Multiplexer Channel 2 + CHANNEL3: 0x13, // Multiplexer Channel 3 + CHANNEL4: 0x14, // Multiplexer Channel 4 + CHANNEL5: 0x15, // Multiplexer Channel 5 + STROBE: 0x0, // Channel Strobe + USERADC0: 0x28, // User ADC0 + USERCCLLUT0A: 0x20, // User CCL LUT0 Event A + USERCCLLUT0B: 0x21, // User CCL LUT0 Event B + USERCCLLUT1A: 0x22, // User CCL LUT1 Event A + USERCCLLUT1B: 0x23, // User CCL LUT1 Event B + USERCCLLUT2A: 0x24, // User CCL LUT2 Event A + USERCCLLUT2B: 0x25, // User CCL LUT2 Event B + USERCCLLUT3A: 0x26, // User CCL LUT3 Event A + USERCCLLUT3B: 0x27, // User CCL LUT3 Event B + USEREVOUTA: 0x29, // User EVOUT Port A + USEREVOUTB: 0x2a, // User EVOUT Port B + USEREVOUTC: 0x2b, // User EVOUT Port C + USEREVOUTD: 0x2c, // User EVOUT Port D + USEREVOUTE: 0x2d, // User EVOUT Port E + USEREVOUTF: 0x2e, // User EVOUT Port F + USERTCA0: 0x33, // User TCA0 + USERTCB0: 0x34, // User TCB0 + USERTCB1: 0x35, // User TCB1 + USERTCB2: 0x36, // User TCB2 + USERTCB3: 0x37, // User TCB3 + USERUSART0: 0x2f, // User USART0 + USERUSART1: 0x30, // User USART1 + USERUSART2: 0x31, // User USART2 + USERUSART3: 0x32, // User USART3 + } + + // Fuses + FUSE = struct { + APPEND __reg + BODCFG __reg + BOOTEND __reg + OSCCFG __reg + SYSCFG0 __reg + SYSCFG1 __reg + TCD0CFG __reg + WDTCFG __reg + }{ + APPEND: 0x7, // Application Code Section End + BODCFG: 0x1, // BOD Configuration + BOOTEND: 0x8, // Boot Section End + OSCCFG: 0x2, // Oscillator Configuration + SYSCFG0: 0x5, // System Configuration 0 + SYSCFG1: 0x6, // System Configuration 1 + TCD0CFG: 0x4, // TCD0 Configuration + WDTCFG: 0x0, // Watchdog Configuration + } + + // General Purpose IO + GPIO = struct { + GPIOR0 __reg + GPIOR1 __reg + GPIOR2 __reg + GPIOR3 __reg + }{ + GPIOR0: 0x0, // General Purpose IO Register 0 + GPIOR1: 0x1, // General Purpose IO Register 1 + GPIOR2: 0x2, // General Purpose IO Register 2 + GPIOR3: 0x3, // General Purpose IO Register 3 + } + + // Lockbit + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, // Lock Bits + } + + // BIST in the NVMCTRL module + NVMBIST = struct { + ADDRPAT __reg + DATAPAT __reg + }{ + ADDRPAT: 0x1, // Address pattern + DATAPAT: 0x2, // Data pattern + } + + // Non-volatile Memory Controller + NVMCTRL = struct { + ADDRL __reg + ADDRH __reg + }{ + ADDRL: 0x8, // Address + ADDRH: 0x8, // Address + } + + // I/O Ports + PORT = struct { + DIRCLR __reg + DIRSET __reg + DIRTGL __reg + OUTCLR __reg + OUTSET __reg + OUTTGL __reg + PIN0CTRL __reg + PIN1CTRL __reg + PIN2CTRL __reg + PIN3CTRL __reg + PIN4CTRL __reg + PIN5CTRL __reg + PIN6CTRL __reg + PIN7CTRL __reg + PORTCTRL __reg + }{ + DIRCLR: 0x2, // Data Direction Clear + DIRSET: 0x1, // Data Direction Set + DIRTGL: 0x3, // Data Direction Toggle + OUTCLR: 0x6, // Output Value Clear + OUTSET: 0x5, // Output Value Set + OUTTGL: 0x7, // Output Value Toggle + PIN0CTRL: 0x10, // Pin 0 Control + PIN1CTRL: 0x11, // Pin 1 Control + PIN2CTRL: 0x12, // Pin 2 Control + PIN3CTRL: 0x13, // Pin 3 Control + PIN4CTRL: 0x14, // Pin 4 Control + PIN5CTRL: 0x15, // Pin 5 Control + PIN6CTRL: 0x16, // Pin 6 Control + PIN7CTRL: 0x17, // Pin 7 Control + PORTCTRL: 0xa, // Port Control + } + + // Port Multiplexer + PORTMUX = struct { + CCLROUTEA __reg + EVSYSROUTEA __reg + TCAROUTEA __reg + TCBROUTEA __reg + TWISPIROUTEA __reg + USARTROUTEA __reg + }{ + CCLROUTEA: 0x1, // Port Multiplexer CCL + EVSYSROUTEA: 0x0, // Port Multiplexer EVSYS + TCAROUTEA: 0x4, // Port Multiplexer TCA + TCBROUTEA: 0x5, // Port Multiplexer TCB + TWISPIROUTEA: 0x3, // Port Multiplexer TWI and SPI + USARTROUTEA: 0x2, // Port Multiplexer USART register A + } + + // Reset controller + RSTCTRL = struct { + RSTFR __reg + SWRR __reg + }{ + RSTFR: 0x0, // Reset Flags + SWRR: 0x1, // Software Reset + } + + // Real-Time Counter + RTC = struct { + CLKSEL __reg + CMPL __reg + CMPH __reg + PITCTRLA __reg + PITDBGCTRL __reg + PITINTCTRL __reg + PITINTFLAGS __reg + PITSTATUS __reg + }{ + CLKSEL: 0x7, // Clock Select + CMPL: 0xc, // Compare + CMPH: 0xc, // Compare + PITCTRLA: 0x10, // PIT Control A + PITDBGCTRL: 0x15, // PIT Debug control + PITINTCTRL: 0x12, // PIT Interrupt Control + PITINTFLAGS: 0x13, // PIT Interrupt Flags + PITSTATUS: 0x11, // PIT Status + } + + // Signature row + SIGROW = struct { + CHECKSUM1 __reg + DEVICEID0 __reg + DEVICEID1 __reg + DEVICEID2 __reg + OSCCAL16M0 __reg + OSCCAL16M1 __reg + OSCCAL20M0 __reg + OSCCAL20M1 __reg + OSCCAL32K __reg + OSC16ERR3V __reg + OSC16ERR5V __reg + OSC20ERR3V __reg + OSC20ERR5V __reg + SERNUM0 __reg + SERNUM1 __reg + SERNUM2 __reg + SERNUM3 __reg + SERNUM4 __reg + SERNUM5 __reg + SERNUM6 __reg + SERNUM7 __reg + SERNUM8 __reg + SERNUM9 __reg + TEMPSENSE0 __reg + TEMPSENSE1 __reg + }{ + CHECKSUM1: 0x2f, // CRC Checksum Byte 1 + DEVICEID0: 0x0, // Device ID Byte 0 + DEVICEID1: 0x1, // Device ID Byte 1 + DEVICEID2: 0x2, // Device ID Byte 2 + OSCCAL16M0: 0x18, // Oscillator Calibration 16 MHz Byte 0 + OSCCAL16M1: 0x19, // Oscillator Calibration 16 MHz Byte 1 + OSCCAL20M0: 0x1a, // Oscillator Calibration 20 MHz Byte 0 + OSCCAL20M1: 0x1b, // Oscillator Calibration 20 MHz Byte 1 + OSCCAL32K: 0x14, // Oscillator Calibration for 32kHz ULP + OSC16ERR3V: 0x22, // OSC16 error at 3V + OSC16ERR5V: 0x23, // OSC16 error at 5V + OSC20ERR3V: 0x24, // OSC20 error at 3V + OSC20ERR5V: 0x25, // OSC20 error at 5V + SERNUM0: 0x3, // Serial Number Byte 0 + SERNUM1: 0x4, // Serial Number Byte 1 + SERNUM2: 0x5, // Serial Number Byte 2 + SERNUM3: 0x6, // Serial Number Byte 3 + SERNUM4: 0x7, // Serial Number Byte 4 + SERNUM5: 0x8, // Serial Number Byte 5 + SERNUM6: 0x9, // Serial Number Byte 6 + SERNUM7: 0xa, // Serial Number Byte 7 + SERNUM8: 0xb, // Serial Number Byte 8 + SERNUM9: 0xc, // Serial Number Byte 9 + TEMPSENSE0: 0x20, // Temperature Sensor Calibration Byte 0 + TEMPSENSE1: 0x21, // Temperature Sensor Calibration Byte 1 + } + + // Sleep Controller + SLPCTRL = struct { + }{} + + // Serial Peripheral Interface + SPI = struct { + }{} + + // System Configuration Registers + SYSCFG = struct { + EXTBRK __reg + OCDM __reg + OCDMS __reg + REVID __reg + }{ + EXTBRK: 0x2, // External Break + OCDM: 0x18, // OCD Message Register + OCDMS: 0x19, // OCD Message Status + REVID: 0x1, // Revision ID + } + + // 16-bit Timer/Counter Type A + TCA = struct { + CMP0L __reg + CMP0H __reg + CMP0BUFL __reg + CMP0BUFH __reg + CMP1L __reg + CMP1H __reg + CMP1BUFL __reg + CMP1BUFH __reg + CMP2L __reg + CMP2H __reg + CMP2BUFL __reg + CMP2BUFH __reg + CTRLFCLR __reg + CTRLFSET __reg + PERBUFL __reg + PERBUFH __reg + HCMP0 __reg + HCMP1 __reg + HCMP2 __reg + HCNT __reg + HPER __reg + LCMP0 __reg + LCMP1 __reg + LCMP2 __reg + LCNT __reg + LPER __reg + }{ + CMP0L: 0x28, // Compare 0 + CMP0H: 0x28, // Compare 0 + CMP0BUFL: 0x38, // Compare 0 Buffer + CMP0BUFH: 0x38, // Compare 0 Buffer + CMP1L: 0x2a, // Compare 1 + CMP1H: 0x2a, // Compare 1 + CMP1BUFL: 0x3a, // Compare 1 Buffer + CMP1BUFH: 0x3a, // Compare 1 Buffer + CMP2L: 0x2c, // Compare 2 + CMP2H: 0x2c, // Compare 2 + CMP2BUFL: 0x3c, // Compare 2 Buffer + CMP2BUFH: 0x3c, // Compare 2 Buffer + CTRLFCLR: 0x6, // Control F Clear + CTRLFSET: 0x7, // Control F Set + PERBUFL: 0x36, // Period Buffer + PERBUFH: 0x36, // Period Buffer + HCMP0: 0x29, // High Compare + HCMP1: 0x2b, // High Compare + HCMP2: 0x2d, // High Compare + HCNT: 0x21, // High Count + HPER: 0x27, // High Period + LCMP0: 0x28, // Low Compare + LCMP1: 0x2a, // Low Compare + LCMP2: 0x2c, // Low Compare + LCNT: 0x20, // Low Count + LPER: 0x26, // Low Period + } + + // 16-bit Timer Type B + TCB = struct { + CCMPL __reg + CCMPH __reg + }{ + CCMPL: 0xc, // Compare or Capture + CCMPH: 0xc, // Compare or Capture + } + + // Two-Wire Interface + TWI = struct { + BRIDGECTRL __reg + MADDR __reg + MBAUD __reg + MCTRLA __reg + MCTRLB __reg + MDATA __reg + MSTATUS __reg + SADDR __reg + SADDRMASK __reg + SCTRLA __reg + SCTRLB __reg + SDATA __reg + SSTATUS __reg + }{ + BRIDGECTRL: 0x1, // Bridge Control + MADDR: 0x7, // Master Address + MBAUD: 0x6, // Master Baurd Rate Control + MCTRLA: 0x3, // Master Control A + MCTRLB: 0x4, // Master Control B + MDATA: 0x8, // Master Data + MSTATUS: 0x5, // Master Status + SADDR: 0xc, // Slave Address + SADDRMASK: 0xe, // Slave Address Mask + SCTRLA: 0x9, // Slave Control A + SCTRLB: 0xa, // Slave Control B + SDATA: 0xd, // Slave Data + SSTATUS: 0xb, // Slave Status + } + + // Universal Synchronous and Asynchronous Receiver and Transmitter + USART = struct { + BAUDL __reg + BAUDH __reg + RXDATAH __reg + RXDATAL __reg + RXPLCTRL __reg + TXDATAH __reg + TXDATAL __reg + TXPLCTRL __reg + }{ + BAUDL: 0x8, // Baud Rate + BAUDH: 0x8, // Baud Rate + RXDATAH: 0x1, // Receive Data High Byte + RXDATAL: 0x0, // Receive Data Low Byte + RXPLCTRL: 0xe, // IRCOM Receiver Pulse Length Control + TXDATAH: 0x3, // Transmit Data High Byte + TXDATAL: 0x2, // Transmit Data Low Byte + TXPLCTRL: 0xd, // IRCOM Transmitter Pulse Length Control + } + + // User Row + USERROW = struct { + USERROW0 __reg + USERROW1 __reg + USERROW2 __reg + USERROW3 __reg + USERROW4 __reg + USERROW5 __reg + USERROW6 __reg + USERROW7 __reg + USERROW8 __reg + USERROW9 __reg + USERROW10 __reg + USERROW11 __reg + USERROW12 __reg + USERROW13 __reg + USERROW14 __reg + USERROW15 __reg + USERROW16 __reg + USERROW17 __reg + USERROW18 __reg + USERROW19 __reg + USERROW20 __reg + USERROW21 __reg + USERROW22 __reg + USERROW23 __reg + USERROW24 __reg + USERROW25 __reg + USERROW26 __reg + USERROW27 __reg + USERROW28 __reg + USERROW29 __reg + USERROW30 __reg + USERROW31 __reg + USERROW32 __reg + USERROW33 __reg + USERROW34 __reg + USERROW35 __reg + USERROW36 __reg + USERROW37 __reg + USERROW38 __reg + USERROW39 __reg + USERROW40 __reg + USERROW41 __reg + USERROW42 __reg + USERROW43 __reg + USERROW44 __reg + USERROW45 __reg + USERROW46 __reg + USERROW47 __reg + USERROW48 __reg + USERROW49 __reg + USERROW50 __reg + USERROW51 __reg + USERROW52 __reg + USERROW53 __reg + USERROW54 __reg + USERROW55 __reg + USERROW56 __reg + USERROW57 __reg + USERROW58 __reg + USERROW59 __reg + USERROW60 __reg + USERROW61 __reg + USERROW62 __reg + USERROW63 __reg + }{ + USERROW0: 0x0, // User Row Byte 0 + USERROW1: 0x1, // User Row Byte 1 + USERROW2: 0x2, // User Row Byte 2 + USERROW3: 0x3, // User Row Byte 3 + USERROW4: 0x4, // User Row Byte 4 + USERROW5: 0x5, // User Row Byte 5 + USERROW6: 0x6, // User Row Byte 6 + USERROW7: 0x7, // User Row Byte 7 + USERROW8: 0x8, // User Row Byte 8 + USERROW9: 0x9, // User Row Byte 9 + USERROW10: 0xa, // User Row Byte 10 + USERROW11: 0xb, // User Row Byte 11 + USERROW12: 0xc, // User Row Byte 12 + USERROW13: 0xd, // User Row Byte 13 + USERROW14: 0xe, // User Row Byte 14 + USERROW15: 0xf, // User Row Byte 15 + USERROW16: 0x10, // User Row Byte 16 + USERROW17: 0x11, // User Row Byte 17 + USERROW18: 0x12, // User Row Byte 18 + USERROW19: 0x13, // User Row Byte 19 + USERROW20: 0x14, // User Row Byte 20 + USERROW21: 0x15, // User Row Byte 21 + USERROW22: 0x16, // User Row Byte 22 + USERROW23: 0x17, // User Row Byte 23 + USERROW24: 0x18, // User Row Byte 24 + USERROW25: 0x19, // User Row Byte 25 + USERROW26: 0x1a, // User Row Byte 26 + USERROW27: 0x1b, // User Row Byte 27 + USERROW28: 0x1c, // User Row Byte 28 + USERROW29: 0x1d, // User Row Byte 29 + USERROW30: 0x1e, // User Row Byte 30 + USERROW31: 0x1f, // User Row Byte 31 + USERROW32: 0x20, // User Row Byte 32 + USERROW33: 0x21, // User Row Byte 33 + USERROW34: 0x22, // User Row Byte 34 + USERROW35: 0x23, // User Row Byte 35 + USERROW36: 0x24, // User Row Byte 36 + USERROW37: 0x25, // User Row Byte 37 + USERROW38: 0x26, // User Row Byte 38 + USERROW39: 0x27, // User Row Byte 39 + USERROW40: 0x28, // User Row Byte 40 + USERROW41: 0x29, // User Row Byte 41 + USERROW42: 0x2a, // User Row Byte 42 + USERROW43: 0x2b, // User Row Byte 43 + USERROW44: 0x2c, // User Row Byte 44 + USERROW45: 0x2d, // User Row Byte 45 + USERROW46: 0x2e, // User Row Byte 46 + USERROW47: 0x2f, // User Row Byte 47 + USERROW48: 0x30, // User Row Byte 48 + USERROW49: 0x31, // User Row Byte 49 + USERROW50: 0x32, // User Row Byte 50 + USERROW51: 0x33, // User Row Byte 51 + USERROW52: 0x34, // User Row Byte 52 + USERROW53: 0x35, // User Row Byte 53 + USERROW54: 0x36, // User Row Byte 54 + USERROW55: 0x37, // User Row Byte 55 + USERROW56: 0x38, // User Row Byte 56 + USERROW57: 0x39, // User Row Byte 57 + USERROW58: 0x3a, // User Row Byte 58 + USERROW59: 0x3b, // User Row Byte 59 + USERROW60: 0x3c, // User Row Byte 60 + USERROW61: 0x3d, // User Row Byte 61 + USERROW62: 0x3e, // User Row Byte 62 + USERROW63: 0x3f, // User Row Byte 63 + } + + // Virtual Ports + VPORT = struct { + }{} + + // Voltage reference + VREF = struct { + }{} + + // Watch-Dog Timer + WDT = struct { + }{} +) + +// Bitfields for AC: Analog Comparator +const ( + // DACREF: Referance scale control + DACREF_DATA = 0xff // DAC voltage reference + + // MUXCTRLA: Mux Control A + MUXCTRLA_INVERT = 0x80 // Invert AC Output + MUXCTRLA_MUXNEG = 0x3 // Negative Input MUX Selection + MUXCTRLA_MUXPOS = 0x18 // Positive Input MUX Selection +) + +// Bitfields for ADC: Analog to Digital Converter +const ( + // COMMAND: Command + COMMAND_STCONV = 0x1 // Start Conversion Operation + + // CTRLE: Control E + CTRLE_WINCM = 0x7 // Window Comparator Mode + + // MUXPOS: Positive mux input + MUXPOS_MUXPOS = 0x1f // Analog Channel Selection Bits + + // SAMPCTRL: Sample Control + SAMPCTRL_SAMPLEN = 0x1f // Sample lenght +) + +// Bitfields for BOD: Bod interface +const ( + // VLMCTRLA: Voltage level monitor Control + VLMCTRLA_VLMLVL = 0x3 // voltage level monitor level +) + +// Bitfields for CCL: Configurable Custom Logic +const ( + // INTCTRL0: Interrupt Control 0 + INTCTRL0_INTMODE0 = 0x3 // Interrupt Mode for LUT0 + INTCTRL0_INTMODE1 = 0xc // Interrupt Mode for LUT1 + INTCTRL0_INTMODE2 = 0x30 // Interrupt Mode for LUT2 + INTCTRL0_INTMODE3 = 0xc0 // Interrupt Mode for LUT3 + + // LUT0CTRLA: LUT Control 0 A + LUT0CTRLA_CLKSRC = 0xe // Clock Source Selection + LUT0CTRLA_EDGEDET = 0x80 // Edge Detection Enable + LUT0CTRLA_ENABLE = 0x1 // LUT Enable + LUT0CTRLA_FILTSEL = 0x30 // Filter Selection + LUT0CTRLA_OUTEN = 0x40 // Output Enable + + // LUT0CTRLB: LUT Control 0 B + LUT0CTRLB_INSEL0 = 0xf // LUT Input 0 Source Selection + LUT0CTRLB_INSEL1 = 0xf0 // LUT Input 1 Source Selection + + // LUT0CTRLC: LUT Control 0 C + LUT0CTRLC_INSEL2 = 0xf // LUT Input 2 Source Selection + + // LUT1CTRLA: LUT Control 1 A + LUT1CTRLA_CLKSRC = 0xe // Clock Source Selection + LUT1CTRLA_EDGEDET = 0x80 // Edge Detection Enable + LUT1CTRLA_ENABLE = 0x1 // LUT Enable + LUT1CTRLA_FILTSEL = 0x30 // Filter Selection + LUT1CTRLA_OUTEN = 0x40 // Output Enable + + // LUT1CTRLB: LUT Control 1 B + LUT1CTRLB_INSEL0 = 0xf // LUT Input 0 Source Selection + LUT1CTRLB_INSEL1 = 0xf0 // LUT Input 1 Source Selection + + // LUT1CTRLC: LUT Control 1 C + LUT1CTRLC_INSEL2 = 0xf // LUT Input 2 Source Selection + + // LUT2CTRLA: LUT Control 2 A + LUT2CTRLA_CLKSRC = 0xe // Clock Source Selection + LUT2CTRLA_EDGEDET = 0x80 // Edge Detection Enable + LUT2CTRLA_ENABLE = 0x1 // LUT Enable + LUT2CTRLA_FILTSEL = 0x30 // Filter Selection + LUT2CTRLA_OUTEN = 0x40 // Output Enable + + // LUT2CTRLB: LUT Control 2 B + LUT2CTRLB_INSEL0 = 0xf // LUT Input 0 Source Selection + LUT2CTRLB_INSEL1 = 0xf0 // LUT Input 1 Source Selection + + // LUT2CTRLC: LUT Control 2 C + LUT2CTRLC_INSEL2 = 0xf // LUT Input 2 Source Selection + + // LUT3CTRLA: LUT Control 3 A + LUT3CTRLA_CLKSRC = 0xe // Clock Source Selection + LUT3CTRLA_EDGEDET = 0x80 // Edge Detection Enable + LUT3CTRLA_ENABLE = 0x1 // LUT Enable + LUT3CTRLA_FILTSEL = 0x30 // Filter Selection + LUT3CTRLA_OUTEN = 0x40 // Output Enable + + // LUT3CTRLB: LUT Control 3 B + LUT3CTRLB_INSEL0 = 0xf // LUT Input 0 Source Selection + LUT3CTRLB_INSEL1 = 0xf0 // LUT Input 1 Source Selection + + // LUT3CTRLC: LUT Control 3 C + LUT3CTRLC_INSEL2 = 0xf // LUT Input 2 Source Selection + + // SEQCTRL0: Sequential Control 0 + SEQCTRL0_SEQSEL = 0x7 // Sequential Selection +) + +// Bitfields for CLKCTRL: Clock controller +const ( + // MCLKCTRLA: MCLK Control A + MCLKCTRLA_CLKOUT = 0x80 // System clock out + MCLKCTRLA_CLKSEL = 0x3 // clock select + + // MCLKCTRLB: MCLK Control B + MCLKCTRLB_PDIV = 0x1e // Prescaler division + MCLKCTRLB_PEN = 0x1 // Prescaler enable + + // MCLKLOCK: MCLK Lock + MCLKLOCK_LOCKEN = 0x1 // lock ebable + + // MCLKSTATUS: MCLK Status + MCLKSTATUS_EXTS = 0x80 // External Clock status + MCLKSTATUS_OSC20MS = 0x10 // 20MHz oscillator status + MCLKSTATUS_OSC32KS = 0x20 // 32KHz oscillator status + MCLKSTATUS_SOSC = 0x1 // System Oscillator changing + MCLKSTATUS_XOSC32KS = 0x40 // 32.768 kHz Crystal Oscillator status + + // OSC20MCALIBA: OSC20M Calibration A + OSC20MCALIBA_CALSEL20M = 0x80 // Calibration freq select + OSC20MCALIBA_CAL20M = 0x7f // Calibration + + // OSC20MCALIBB: OSC20M Calibration B + OSC20MCALIBB_LOCK = 0x80 // Lock + OSC20MCALIBB_TEMPCAL20M = 0xf // Oscillator temperature coefficient + + // OSC20MCTRLA: OSC20M Control A + OSC20MCTRLA_RUNSTDBY = 0x2 // Run standby + + // OSC32KCALIB: OSC32K Calibration + OSC32KCALIB_CAL32K = 0x3f // Calibration + + // OSC32KCTRLA: OSC32K Control A + OSC32KCTRLA_RUNSTDBY = 0x2 // Run standby + + // XOSC32KCTRLA: XOSC32K Control A + XOSC32KCTRLA_CSUT = 0x30 // Crystal startup time + XOSC32KCTRLA_ENABLE = 0x1 // Enable + XOSC32KCTRLA_RUNSTDBY = 0x2 // Run standby + XOSC32KCTRLA_SEL = 0x4 // Select +) + +// Bitfields for CPU: CPU +const ( + // CCP: Configuration Change Protection + CCP_CCP = 0xff // CCP signature + + // SREG: Status Register + SREG_C = 0x1 // Carry Flag + SREG_H = 0x20 // Half Carry Flag + SREG_I = 0x80 // Global Interrupt Enable Flag + SREG_N = 0x4 // Negative Flag + SREG_S = 0x10 // N Exclusive Or V Flag + SREG_T = 0x40 // Transfer Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_Z = 0x2 // Zero Flag +) + +// Bitfields for CPUINT: Interrupt Controller +const ( + // LVL0PRI: Interrupt Level 0 Priority + LVL0PRI_LVL0PRI = 0xff // Interrupt Level Priority + + // LVL1VEC: Interrupt Level 1 Priority Vector + LVL1VEC_LVL1VEC = 0xff // Interrupt Vector with High Priority +) + +// Bitfields for EVSYS: Event System +const ( + // CHANNEL0: Multiplexer Channel 0 + CHANNEL0_GENERATOR = 0xff // Generator selector + + // CHANNEL1: Multiplexer Channel 1 + CHANNEL1_GENERATOR = 0xff // Generator selector + + // CHANNEL2: Multiplexer Channel 2 + CHANNEL2_GENERATOR = 0xff // Generator selector + + // CHANNEL3: Multiplexer Channel 3 + CHANNEL3_GENERATOR = 0xff // Generator selector + + // CHANNEL4: Multiplexer Channel 4 + CHANNEL4_GENERATOR = 0xff // Generator selector + + // CHANNEL5: Multiplexer Channel 5 + CHANNEL5_GENERATOR = 0xff // Generator selector + + // STROBE: Channel Strobe + STROBE_STROBE0 = 0xff // Software event on channels + + // USERADC0: User ADC0 + USERADC0_CHANNEL = 0xff // Channel selector + + // USERCCLLUT0A: User CCL LUT0 Event A + USERCCLLUT0A_CHANNEL = 0xff // Channel selector + + // USERCCLLUT0B: User CCL LUT0 Event B + USERCCLLUT0B_CHANNEL = 0xff // Channel selector + + // USERCCLLUT1A: User CCL LUT1 Event A + USERCCLLUT1A_CHANNEL = 0xff // Channel selector + + // USERCCLLUT1B: User CCL LUT1 Event B + USERCCLLUT1B_CHANNEL = 0xff // Channel selector + + // USERCCLLUT2A: User CCL LUT2 Event A + USERCCLLUT2A_CHANNEL = 0xff // Channel selector + + // USERCCLLUT2B: User CCL LUT2 Event B + USERCCLLUT2B_CHANNEL = 0xff // Channel selector + + // USERCCLLUT3A: User CCL LUT3 Event A + USERCCLLUT3A_CHANNEL = 0xff // Channel selector + + // USERCCLLUT3B: User CCL LUT3 Event B + USERCCLLUT3B_CHANNEL = 0xff // Channel selector + + // USEREVOUTA: User EVOUT Port A + USEREVOUTA_CHANNEL = 0xff // Channel selector + + // USEREVOUTB: User EVOUT Port B + USEREVOUTB_CHANNEL = 0xff // Channel selector + + // USEREVOUTC: User EVOUT Port C + USEREVOUTC_CHANNEL = 0xff // Channel selector + + // USEREVOUTD: User EVOUT Port D + USEREVOUTD_CHANNEL = 0xff // Channel selector + + // USEREVOUTE: User EVOUT Port E + USEREVOUTE_CHANNEL = 0xff // Channel selector + + // USEREVOUTF: User EVOUT Port F + USEREVOUTF_CHANNEL = 0xff // Channel selector + + // USERTCA0: User TCA0 + USERTCA0_CHANNEL = 0xff // Channel selector + + // USERTCB0: User TCB0 + USERTCB0_CHANNEL = 0xff // Channel selector + + // USERTCB1: User TCB1 + USERTCB1_CHANNEL = 0xff // Channel selector + + // USERTCB2: User TCB2 + USERTCB2_CHANNEL = 0xff // Channel selector + + // USERTCB3: User TCB3 + USERTCB3_CHANNEL = 0xff // Channel selector + + // USERUSART0: User USART0 + USERUSART0_CHANNEL = 0xff // Channel selector + + // USERUSART1: User USART1 + USERUSART1_CHANNEL = 0xff // Channel selector + + // USERUSART2: User USART2 + USERUSART2_CHANNEL = 0xff // Channel selector + + // USERUSART3: User USART3 + USERUSART3_CHANNEL = 0xff // Channel selector +) + +// Bitfields for FUSE: Fuses +const ( + // BODCFG: BOD Configuration + BODCFG_ACTIVE = 0xc // BOD Operation in Active Mode + BODCFG_LVL = 0xe0 // BOD Level + BODCFG_SAMPFREQ = 0x10 // BOD Sample Frequency + BODCFG_SLEEP = 0x3 // BOD Operation in Sleep Mode + + // OSCCFG: Oscillator Configuration + OSCCFG_FREQSEL = 0x3 // Frequency Select + OSCCFG_OSCLOCK = 0x80 // Oscillator Lock + + // SYSCFG0: System Configuration 0 + SYSCFG0_CRCSRC = 0xc0 // CRC Source + SYSCFG0_EESAVE = 0x1 // EEPROM Save + SYSCFG0_RSTPINCFG = 0x8 // Reset Pin Configuration + + // SYSCFG1: System Configuration 1 + SYSCFG1_SUT = 0x7 // Startup Time + + // TCD0CFG: TCD0 Configuration + TCD0CFG_CMPA = 0x1 // Compare A Default Output Value + TCD0CFG_CMPAEN = 0x10 // Compare A Output Enable + TCD0CFG_CMPB = 0x2 // Compare B Default Output Value + TCD0CFG_CMPBEN = 0x20 // Compare B Output Enable + TCD0CFG_CMPC = 0x4 // Compare C Default Output Value + TCD0CFG_CMPCEN = 0x40 // Compare C Output Enable + TCD0CFG_CMPD = 0x8 // Compare D Default Output Value + TCD0CFG_CMPDEN = 0x80 // Compare D Output Enable + + // WDTCFG: Watchdog Configuration + WDTCFG_PERIOD = 0xf // Watchdog Timeout Period + WDTCFG_WINDOW = 0xf0 // Watchdog Window Timeout Period +) + +// Bitfields for LOCKBIT: Lockbit +const ( + // LOCKBIT: Lock Bits + LOCKBIT_LB = 0xff // Lock Bits +) + +// Bitfields for NVMBIST: BIST in the NVMCTRL module +const ( + // ADDRPAT: Address pattern + ADDRPAT_AMODE = 0x70 // Address mode + ADDRPAT_XMODE = 0x3 // X address mode + ADDRPAT_YMODE = 0xc // Y address mode + + // DATAPAT: Data pattern + DATAPAT_PATTERN = 0x3 // Data check pattern + END_END = 0xffffff +) + +// Bitfields for PORT: I/O Ports +const ( + // PIN0CTRL: Pin 0 Control + PIN0CTRL_INVEN = 0x80 // Inverted I/O Enable + PIN0CTRL_ISC = 0x7 // Input/Sense Configuration + PIN0CTRL_PULLUPEN = 0x8 // Pullup enable + + // PIN1CTRL: Pin 1 Control + PIN1CTRL_INVEN = 0x80 // Inverted I/O Enable + PIN1CTRL_ISC = 0x7 // Input/Sense Configuration + PIN1CTRL_PULLUPEN = 0x8 // Pullup enable + + // PIN2CTRL: Pin 2 Control + PIN2CTRL_INVEN = 0x80 // Inverted I/O Enable + PIN2CTRL_ISC = 0x7 // Input/Sense Configuration + PIN2CTRL_PULLUPEN = 0x8 // Pullup enable + + // PIN3CTRL: Pin 3 Control + PIN3CTRL_INVEN = 0x80 // Inverted I/O Enable + PIN3CTRL_ISC = 0x7 // Input/Sense Configuration + PIN3CTRL_PULLUPEN = 0x8 // Pullup enable + + // PIN4CTRL: Pin 4 Control + PIN4CTRL_INVEN = 0x80 // Inverted I/O Enable + PIN4CTRL_ISC = 0x7 // Input/Sense Configuration + PIN4CTRL_PULLUPEN = 0x8 // Pullup enable + + // PIN5CTRL: Pin 5 Control + PIN5CTRL_INVEN = 0x80 // Inverted I/O Enable + PIN5CTRL_ISC = 0x7 // Input/Sense Configuration + PIN5CTRL_PULLUPEN = 0x8 // Pullup enable + + // PIN6CTRL: Pin 6 Control + PIN6CTRL_INVEN = 0x80 // Inverted I/O Enable + PIN6CTRL_ISC = 0x7 // Input/Sense Configuration + PIN6CTRL_PULLUPEN = 0x8 // Pullup enable + + // PIN7CTRL: Pin 7 Control + PIN7CTRL_INVEN = 0x80 // Inverted I/O Enable + PIN7CTRL_ISC = 0x7 // Input/Sense Configuration + PIN7CTRL_PULLUPEN = 0x8 // Pullup enable + + // PORTCTRL: Port Control + PORTCTRL_SRL = 0x1 // Slew Rate Limit Enable +) + +// Bitfields for PORTMUX: Port Multiplexer +const ( + // CCLROUTEA: Port Multiplexer CCL + CCLROUTEA_LUT0 = 0x1 // CCL LUT0 + CCLROUTEA_LUT1 = 0x2 // CCL LUT1 + CCLROUTEA_LUT2 = 0x4 // CCL LUT2 + CCLROUTEA_LUT3 = 0x8 // CCL LUT3 + + // EVSYSROUTEA: Port Multiplexer EVSYS + EVSYSROUTEA_EVOUT0 = 0x1 // Event Output 0 + EVSYSROUTEA_EVOUT1 = 0x2 // Event Output 1 + EVSYSROUTEA_EVOUT2 = 0x4 // Event Output 2 + EVSYSROUTEA_EVOUT3 = 0x8 // Event Output 3 + EVSYSROUTEA_EVOUT4 = 0x10 // Event Output 4 + EVSYSROUTEA_EVOUT5 = 0x20 // Event Output 5 + + // TCAROUTEA: Port Multiplexer TCA + TCAROUTEA_TCA0 = 0x7 // Port Multiplexer TCA0 + + // TCBROUTEA: Port Multiplexer TCB + TCBROUTEA_TCB0 = 0x1 // Port Multiplexer TCB0 + TCBROUTEA_TCB1 = 0x2 // Port Multiplexer TCB1 + TCBROUTEA_TCB2 = 0x4 // Port Multiplexer TCB2 + TCBROUTEA_TCB3 = 0x8 // Port Multiplexer TCB3 + + // TWISPIROUTEA: Port Multiplexer TWI and SPI + TWISPIROUTEA_SPI0 = 0x3 // Port Multiplexer SPI0 + TWISPIROUTEA_TWI0 = 0x30 // Port Multiplexer TWI0 + + // USARTROUTEA: Port Multiplexer USART register A + USARTROUTEA_USART0 = 0x3 // Port Multiplexer USART0 + USARTROUTEA_USART1 = 0xc // Port Multiplexer USART1 + USARTROUTEA_USART2 = 0x30 // Port Multiplexer USART2 + USARTROUTEA_USART3 = 0xc0 // Port Multiplexer USART3 +) + +// Bitfields for RSTCTRL: Reset controller +const ( + // RSTFR: Reset Flags + RSTFR_BORF = 0x2 // Brown out detector Reset flag + RSTFR_EXTRF = 0x4 // External Reset flag + RSTFR_PORF = 0x1 // Power on Reset flag + RSTFR_SWRF = 0x10 // Software Reset flag + RSTFR_UPDIRF = 0x20 // UPDI Reset flag + RSTFR_WDRF = 0x8 // Watch dog Reset flag + + // SWRR: Software Reset + SWRR_SWRE = 0x1 // Software reset enable +) + +// Bitfields for RTC: Real-Time Counter +const ( + // CLKSEL: Clock Select + CLKSEL_CLKSEL = 0x3 // Clock Select + + // PITCTRLA: PIT Control A + PITCTRLA_PERIOD = 0x78 // Period + PITCTRLA_PITEN = 0x1 // Enable + + // PITDBGCTRL: PIT Debug control + PITDBGCTRL_DBGRUN = 0x1 // Run in debug + + // PITINTCTRL: PIT Interrupt Control + PITINTCTRL_PI = 0x1 // Periodic Interrupt + + // PITINTFLAGS: PIT Interrupt Flags + PITINTFLAGS_PI = 0x1 // Periodic Interrupt + + // PITSTATUS: PIT Status + PITSTATUS_CTRLBUSY = 0x1 // CTRLA Synchronization Busy Flag +) + +// Bitfields for SYSCFG: System Configuration Registers +const ( + // EXTBRK: External Break + EXTBRK_ENEXTBRK = 0x1 // External break enable + + // OCDMS: OCD Message Status + OCDMS_OCDMR = 0x1 // OCD Message Read +) + +// Bitfields for TCA: 16-bit Timer/Counter Type A +const ( + // CTRLFCLR: Control F Clear + CTRLFCLR_CMP0BV = 0x2 // Compare 0 Buffer Valid + CTRLFCLR_CMP1BV = 0x4 // Compare 1 Buffer Valid + CTRLFCLR_CMP2BV = 0x8 // Compare 2 Buffer Valid + CTRLFCLR_PERBV = 0x1 // Period Buffer Valid + + // CTRLFSET: Control F Set + CTRLFSET_CMP0BV = 0x2 // Compare 0 Buffer Valid + CTRLFSET_CMP1BV = 0x4 // Compare 1 Buffer Valid + CTRLFSET_CMP2BV = 0x8 // Compare 2 Buffer Valid + CTRLFSET_PERBV = 0x1 // Period Buffer Valid +) + +// Bitfields for TWI: Two-Wire Interface +const ( + // BRIDGECTRL: Bridge Control + BRIDGECTRL_ENABLE = 0x1 // Bridge Enable + BRIDGECTRL_FMPEN = 0x2 // FM Plus Enable + BRIDGECTRL_SDAHOLD = 0xc // SDA Hold Time + + // MCTRLA: Master Control A + MCTRLA_ENABLE = 0x1 // Enable TWI Master + MCTRLA_QCEN = 0x10 // Quick Command Enable + MCTRLA_RIEN = 0x80 // Read Interrupt Enable + MCTRLA_SMEN = 0x2 // Smart Mode Enable + MCTRLA_TIMEOUT = 0xc // Inactive Bus Timeout + MCTRLA_WIEN = 0x40 // Write Interrupt Enable + + // MCTRLB: Master Control B + MCTRLB_ACKACT = 0x4 // Acknowledge Action + MCTRLB_FLUSH = 0x8 // Flush + MCTRLB_MCMD = 0x3 // Command + + // MSTATUS: Master Status + MSTATUS_ARBLOST = 0x8 // Arbitration Lost + MSTATUS_BUSERR = 0x4 // Bus Error + MSTATUS_BUSSTATE = 0x3 // Bus State + MSTATUS_CLKHOLD = 0x20 // Clock Hold + MSTATUS_RIF = 0x80 // Read Interrupt Flag + MSTATUS_RXACK = 0x10 // Received Acknowledge + MSTATUS_WIF = 0x40 // Write Interrupt Flag + + // SADDRMASK: Slave Address Mask + SADDRMASK_ADDREN = 0x1 // Address Enable + SADDRMASK_ADDRMASK = 0xfe // Address Mask + + // SCTRLA: Slave Control A + SCTRLA_APIEN = 0x40 // Address/Stop Interrupt Enable + SCTRLA_DIEN = 0x80 // Data Interrupt Enable + SCTRLA_ENABLE = 0x1 // Enable TWI Slave + SCTRLA_PIEN = 0x20 // Stop Interrupt Enable + SCTRLA_PMEN = 0x4 // Promiscuous Mode Enable + SCTRLA_SMEN = 0x2 // Smart Mode Enable + + // SCTRLB: Slave Control B + SCTRLB_ACKACT = 0x4 // Acknowledge Action + SCTRLB_SCMD = 0x3 // Command + + // SSTATUS: Slave Status + SSTATUS_AP = 0x1 // Slave Address or Stop + SSTATUS_APIF = 0x40 // Address/Stop Interrupt Flag + SSTATUS_BUSERR = 0x4 // Bus Error + SSTATUS_CLKHOLD = 0x20 // Clock Hold + SSTATUS_COLL = 0x8 // Collision + SSTATUS_DIF = 0x80 // Data Interrupt Flag + SSTATUS_DIR = 0x2 // Read/Write Direction + SSTATUS_RXACK = 0x10 // Received Acknowledge +) + +// Bitfields for USART: Universal Synchronous and Asynchronous Receiver and Transmitter +const ( + // RXDATAH: Receive Data High Byte + RXDATAH_BUFOVF = 0x40 // Buffer Overflow + RXDATAH_DATA8 = 0x1 // Receiver Data Register + RXDATAH_FERR = 0x4 // Frame Error + RXDATAH_PERR = 0x2 // Parity Error + RXDATAH_RXCIF = 0x80 // Receive Complete Interrupt Flag + + // RXDATAL: Receive Data Low Byte + RXDATAL_DATA = 0xff // RX Data + + // RXPLCTRL: IRCOM Receiver Pulse Length Control + RXPLCTRL_RXPL = 0x7f // Receiver Pulse Lenght + + // TXDATAH: Transmit Data High Byte + TXDATAH_DATA8 = 0x1 // Transmit Data Register (CHSIZE=9bit) + + // TXDATAL: Transmit Data Low Byte + TXDATAL_DATA = 0xff // Transmit Data Register + + // TXPLCTRL: IRCOM Transmitter Pulse Length Control + TXPLCTRL_TXPL = 0xff // Transmit pulse length +) diff --git a/src/device/avr/atmega4808.ld b/src/device/avr/atmega4808.ld new file mode 100644 index 00000000..3ff22d7f --- /dev/null +++ b/src/device/avr/atmega4808.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega4808.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0xc000; +__ram_size = 0x1800; +__num_isrs = 39; diff --git a/src/device/avr/atmega4809.go b/src/device/avr/atmega4809.go new file mode 100644 index 00000000..8e8417ff --- /dev/null +++ b/src/device/avr/atmega4809.go @@ -0,0 +1,1305 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega4809.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega4809 + +// Device information for the ATmega4809. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega4809" + ARCH = "AVR8X" + FAMILY = "AVR MEGA" +) + +// Interrupts +const ( + IRQ_NMI = 1 // + IRQ_VLM = 2 // + IRQ_CNT = 3 // + IRQ_PIT = 4 // + IRQ_CCL = 5 // + IRQ_PORT = 6 // + IRQ_LUNF = 7 // + IRQ_OVF = 7 // + IRQ_HUNF = 8 // + IRQ_LCMP0 = 9 // + IRQ_CMP0 = 9 // + IRQ_CMP1 = 10 // + IRQ_LCMP1 = 10 // + IRQ_CMP2 = 11 // + IRQ_LCMP2 = 11 // + IRQ_INT = 12 // + IRQ_INT = 13 // + IRQ_TWIS = 14 // + IRQ_TWIM = 15 // + IRQ_INT = 16 // + IRQ_RXC = 17 // + IRQ_DRE = 18 // + IRQ_TXC = 19 // + IRQ_PORT = 20 // + IRQ_AC = 21 // + IRQ_RESRDY = 22 // + IRQ_WCOMP = 23 // + IRQ_PORT = 24 // + IRQ_INT = 25 // + IRQ_RXC = 26 // + IRQ_DRE = 27 // + IRQ_TXC = 28 // + IRQ_PORT = 29 // + IRQ_EE = 30 // + IRQ_RXC = 31 // + IRQ_DRE = 32 // + IRQ_TXC = 33 // + IRQ_PORT = 34 // + IRQ_PORT = 35 // + IRQ_INT = 36 // + IRQ_RXC = 37 // + IRQ_DRE = 38 // + IRQ_TXC = 39 // + IRQ_max = 39 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Analog Comparator + AC = struct { + DACREF __reg + MUXCTRLA __reg + }{ + DACREF: 0x4, // Referance scale control + MUXCTRLA: 0x2, // Mux Control A + } + + // Analog to Digital Converter + ADC = struct { + COMMAND __reg + CTRLE __reg + MUXPOS __reg + RESL __reg + RESH __reg + SAMPCTRL __reg + WINHTL __reg + WINHTH __reg + WINLTL __reg + WINLTH __reg + }{ + COMMAND: 0x8, // Command + CTRLE: 0x4, // Control E + MUXPOS: 0x6, // Positive mux input + RESL: 0x10, // ADC Accumulator Result + RESH: 0x10, // ADC Accumulator Result + SAMPCTRL: 0x5, // Sample Control + WINHTL: 0x14, // Window comparator high threshold + WINHTH: 0x14, // Window comparator high threshold + WINLTL: 0x12, // Window comparator low threshold + WINLTH: 0x12, // Window comparator low threshold + } + + // Bod interface + BOD = struct { + VLMCTRLA __reg + }{ + VLMCTRLA: 0x8, // Voltage level monitor Control + } + + // Configurable Custom Logic + CCL = struct { + INTCTRL0 __reg + LUT0CTRLA __reg + LUT0CTRLB __reg + LUT0CTRLC __reg + LUT1CTRLA __reg + LUT1CTRLB __reg + LUT1CTRLC __reg + LUT2CTRLA __reg + LUT2CTRLB __reg + LUT2CTRLC __reg + LUT3CTRLA __reg + LUT3CTRLB __reg + LUT3CTRLC __reg + SEQCTRL0 __reg + TRUTH0 __reg + TRUTH1 __reg + TRUTH2 __reg + TRUTH3 __reg + }{ + INTCTRL0: 0x5, // Interrupt Control 0 + LUT0CTRLA: 0x8, // LUT Control 0 A + LUT0CTRLB: 0x9, // LUT Control 0 B + LUT0CTRLC: 0xa, // LUT Control 0 C + LUT1CTRLA: 0xc, // LUT Control 1 A + LUT1CTRLB: 0xd, // LUT Control 1 B + LUT1CTRLC: 0xe, // LUT Control 1 C + LUT2CTRLA: 0x10, // LUT Control 2 A + LUT2CTRLB: 0x11, // LUT Control 2 B + LUT2CTRLC: 0x12, // LUT Control 2 C + LUT3CTRLA: 0x14, // LUT Control 3 A + LUT3CTRLB: 0x15, // LUT Control 3 B + LUT3CTRLC: 0x16, // LUT Control 3 C + SEQCTRL0: 0x1, // Sequential Control 0 + TRUTH0: 0xb, // Truth 0 + TRUTH1: 0xf, // Truth 1 + TRUTH2: 0x13, // Truth 2 + TRUTH3: 0x17, // Truth 3 + } + + // Clock controller + CLKCTRL = struct { + MCLKCTRLA __reg + MCLKCTRLB __reg + MCLKLOCK __reg + MCLKSTATUS __reg + OSC20MCALIBA __reg + OSC20MCALIBB __reg + OSC20MCTRLA __reg + OSC32KCALIB __reg + OSC32KCTRLA __reg + XOSC32KCTRLA __reg + }{ + MCLKCTRLA: 0x0, // MCLK Control A + MCLKCTRLB: 0x1, // MCLK Control B + MCLKLOCK: 0x2, // MCLK Lock + MCLKSTATUS: 0x3, // MCLK Status + OSC20MCALIBA: 0x11, // OSC20M Calibration A + OSC20MCALIBB: 0x12, // OSC20M Calibration B + OSC20MCTRLA: 0x10, // OSC20M Control A + OSC32KCALIB: 0x19, // OSC32K Calibration + OSC32KCTRLA: 0x18, // OSC32K Control A + XOSC32KCTRLA: 0x1c, // XOSC32K Control A + } + + // CPU + CPU = struct { + CCP __reg + RAMPZ __reg + SPH __reg + SPL __reg + SREG __reg + }{ + CCP: 0x4, // Configuration Change Protection + RAMPZ: 0xb, // Extended Z-pointer Register + SPH: 0xe, // Stack Pointer High + SPL: 0xd, // Stack Pointer Low + SREG: 0xf, // Status Register + } + + // Interrupt Controller + CPUINT = struct { + LVL0PRI __reg + LVL1VEC __reg + }{ + LVL0PRI: 0x2, // Interrupt Level 0 Priority + LVL1VEC: 0x3, // Interrupt Level 1 Priority Vector + } + + // CRCSCAN + CRCSCAN = struct { + }{} + + // Event System + EVSYS = struct { + CHANNEL0 __reg + CHANNEL1 __reg + CHANNEL2 __reg + CHANNEL3 __reg + CHANNEL4 __reg + CHANNEL5 __reg + CHANNEL6 __reg + CHANNEL7 __reg + STROBE __reg + USERADC0 __reg + USERCCLLUT0A __reg + USERCCLLUT0B __reg + USERCCLLUT1A __reg + USERCCLLUT1B __reg + USERCCLLUT2A __reg + USERCCLLUT2B __reg + USERCCLLUT3A __reg + USERCCLLUT3B __reg + USEREVOUTA __reg + USEREVOUTB __reg + USEREVOUTC __reg + USEREVOUTD __reg + USEREVOUTE __reg + USEREVOUTF __reg + USERTCA0 __reg + USERTCB0 __reg + USERTCB1 __reg + USERTCB2 __reg + USERTCB3 __reg + USERUSART0 __reg + USERUSART1 __reg + USERUSART2 __reg + USERUSART3 __reg + }{ + CHANNEL0: 0x10, // Multiplexer Channel 0 + CHANNEL1: 0x11, // Multiplexer Channel 1 + CHANNEL2: 0x12, // Multiplexer Channel 2 + CHANNEL3: 0x13, // Multiplexer Channel 3 + CHANNEL4: 0x14, // Multiplexer Channel 4 + CHANNEL5: 0x15, // Multiplexer Channel 5 + CHANNEL6: 0x16, // Multiplexer Channel 6 + CHANNEL7: 0x17, // Multiplexer Channel 7 + STROBE: 0x0, // Channel Strobe + USERADC0: 0x28, // User ADC0 + USERCCLLUT0A: 0x20, // User CCL LUT0 Event A + USERCCLLUT0B: 0x21, // User CCL LUT0 Event B + USERCCLLUT1A: 0x22, // User CCL LUT1 Event A + USERCCLLUT1B: 0x23, // User CCL LUT1 Event B + USERCCLLUT2A: 0x24, // User CCL LUT2 Event A + USERCCLLUT2B: 0x25, // User CCL LUT2 Event B + USERCCLLUT3A: 0x26, // User CCL LUT3 Event A + USERCCLLUT3B: 0x27, // User CCL LUT3 Event B + USEREVOUTA: 0x29, // User EVOUT Port A + USEREVOUTB: 0x2a, // User EVOUT Port B + USEREVOUTC: 0x2b, // User EVOUT Port C + USEREVOUTD: 0x2c, // User EVOUT Port D + USEREVOUTE: 0x2d, // User EVOUT Port E + USEREVOUTF: 0x2e, // User EVOUT Port F + USERTCA0: 0x33, // User TCA0 + USERTCB0: 0x34, // User TCB0 + USERTCB1: 0x35, // User TCB1 + USERTCB2: 0x36, // User TCB2 + USERTCB3: 0x37, // User TCB3 + USERUSART0: 0x2f, // User USART0 + USERUSART1: 0x30, // User USART1 + USERUSART2: 0x31, // User USART2 + USERUSART3: 0x32, // User USART3 + } + + // Fuses + FUSE = struct { + APPEND __reg + BODCFG __reg + BOOTEND __reg + OSCCFG __reg + SYSCFG0 __reg + SYSCFG1 __reg + TCD0CFG __reg + WDTCFG __reg + }{ + APPEND: 0x7, // Application Code Section End + BODCFG: 0x1, // BOD Configuration + BOOTEND: 0x8, // Boot Section End + OSCCFG: 0x2, // Oscillator Configuration + SYSCFG0: 0x5, // System Configuration 0 + SYSCFG1: 0x6, // System Configuration 1 + TCD0CFG: 0x4, // TCD0 Configuration + WDTCFG: 0x0, // Watchdog Configuration + } + + // General Purpose IO + GPIO = struct { + GPIOR0 __reg + GPIOR1 __reg + GPIOR2 __reg + GPIOR3 __reg + }{ + GPIOR0: 0x0, // General Purpose IO Register 0 + GPIOR1: 0x1, // General Purpose IO Register 1 + GPIOR2: 0x2, // General Purpose IO Register 2 + GPIOR3: 0x3, // General Purpose IO Register 3 + } + + // Lockbit + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, // Lock Bits + } + + // BIST in the NVMCTRL module + NVMBIST = struct { + ADDRPAT __reg + DATAPAT __reg + }{ + ADDRPAT: 0x1, // Address pattern + DATAPAT: 0x2, // Data pattern + } + + // Non-volatile Memory Controller + NVMCTRL = struct { + ADDRL __reg + ADDRH __reg + }{ + ADDRL: 0x8, // Address + ADDRH: 0x8, // Address + } + + // I/O Ports + PORT = struct { + DIRCLR __reg + DIRSET __reg + DIRTGL __reg + OUTCLR __reg + OUTSET __reg + OUTTGL __reg + PIN0CTRL __reg + PIN1CTRL __reg + PIN2CTRL __reg + PIN3CTRL __reg + PIN4CTRL __reg + PIN5CTRL __reg + PIN6CTRL __reg + PIN7CTRL __reg + PORTCTRL __reg + }{ + DIRCLR: 0x2, // Data Direction Clear + DIRSET: 0x1, // Data Direction Set + DIRTGL: 0x3, // Data Direction Toggle + OUTCLR: 0x6, // Output Value Clear + OUTSET: 0x5, // Output Value Set + OUTTGL: 0x7, // Output Value Toggle + PIN0CTRL: 0x10, // Pin 0 Control + PIN1CTRL: 0x11, // Pin 1 Control + PIN2CTRL: 0x12, // Pin 2 Control + PIN3CTRL: 0x13, // Pin 3 Control + PIN4CTRL: 0x14, // Pin 4 Control + PIN5CTRL: 0x15, // Pin 5 Control + PIN6CTRL: 0x16, // Pin 6 Control + PIN7CTRL: 0x17, // Pin 7 Control + PORTCTRL: 0xa, // Port Control + } + + // Port Multiplexer + PORTMUX = struct { + CCLROUTEA __reg + EVSYSROUTEA __reg + TCAROUTEA __reg + TCBROUTEA __reg + TWISPIROUTEA __reg + USARTROUTEA __reg + }{ + CCLROUTEA: 0x1, // Port Multiplexer CCL + EVSYSROUTEA: 0x0, // Port Multiplexer EVSYS + TCAROUTEA: 0x4, // Port Multiplexer TCA + TCBROUTEA: 0x5, // Port Multiplexer TCB + TWISPIROUTEA: 0x3, // Port Multiplexer TWI and SPI + USARTROUTEA: 0x2, // Port Multiplexer USART register A + } + + // Reset controller + RSTCTRL = struct { + RSTFR __reg + SWRR __reg + }{ + RSTFR: 0x0, // Reset Flags + SWRR: 0x1, // Software Reset + } + + // Real-Time Counter + RTC = struct { + CLKSEL __reg + CMPL __reg + CMPH __reg + PITCTRLA __reg + PITDBGCTRL __reg + PITINTCTRL __reg + PITINTFLAGS __reg + PITSTATUS __reg + }{ + CLKSEL: 0x7, // Clock Select + CMPL: 0xc, // Compare + CMPH: 0xc, // Compare + PITCTRLA: 0x10, // PIT Control A + PITDBGCTRL: 0x15, // PIT Debug control + PITINTCTRL: 0x12, // PIT Interrupt Control + PITINTFLAGS: 0x13, // PIT Interrupt Flags + PITSTATUS: 0x11, // PIT Status + } + + // Signature row + SIGROW = struct { + CHECKSUM1 __reg + DEVICEID0 __reg + DEVICEID1 __reg + DEVICEID2 __reg + OSCCAL16M0 __reg + OSCCAL16M1 __reg + OSCCAL20M0 __reg + OSCCAL20M1 __reg + OSCCAL32K __reg + OSC16ERR3V __reg + OSC16ERR5V __reg + OSC20ERR3V __reg + OSC20ERR5V __reg + SERNUM0 __reg + SERNUM1 __reg + SERNUM2 __reg + SERNUM3 __reg + SERNUM4 __reg + SERNUM5 __reg + SERNUM6 __reg + SERNUM7 __reg + SERNUM8 __reg + SERNUM9 __reg + TEMPSENSE0 __reg + TEMPSENSE1 __reg + }{ + CHECKSUM1: 0x2f, // CRC Checksum Byte 1 + DEVICEID0: 0x0, // Device ID Byte 0 + DEVICEID1: 0x1, // Device ID Byte 1 + DEVICEID2: 0x2, // Device ID Byte 2 + OSCCAL16M0: 0x18, // Oscillator Calibration 16 MHz Byte 0 + OSCCAL16M1: 0x19, // Oscillator Calibration 16 MHz Byte 1 + OSCCAL20M0: 0x1a, // Oscillator Calibration 20 MHz Byte 0 + OSCCAL20M1: 0x1b, // Oscillator Calibration 20 MHz Byte 1 + OSCCAL32K: 0x14, // Oscillator Calibration for 32kHz ULP + OSC16ERR3V: 0x22, // OSC16 error at 3V + OSC16ERR5V: 0x23, // OSC16 error at 5V + OSC20ERR3V: 0x24, // OSC20 error at 3V + OSC20ERR5V: 0x25, // OSC20 error at 5V + SERNUM0: 0x3, // Serial Number Byte 0 + SERNUM1: 0x4, // Serial Number Byte 1 + SERNUM2: 0x5, // Serial Number Byte 2 + SERNUM3: 0x6, // Serial Number Byte 3 + SERNUM4: 0x7, // Serial Number Byte 4 + SERNUM5: 0x8, // Serial Number Byte 5 + SERNUM6: 0x9, // Serial Number Byte 6 + SERNUM7: 0xa, // Serial Number Byte 7 + SERNUM8: 0xb, // Serial Number Byte 8 + SERNUM9: 0xc, // Serial Number Byte 9 + TEMPSENSE0: 0x20, // Temperature Sensor Calibration Byte 0 + TEMPSENSE1: 0x21, // Temperature Sensor Calibration Byte 1 + } + + // Sleep Controller + SLPCTRL = struct { + }{} + + // Serial Peripheral Interface + SPI = struct { + }{} + + // System Configuration Registers + SYSCFG = struct { + EXTBRK __reg + OCDM __reg + OCDMS __reg + REVID __reg + }{ + EXTBRK: 0x2, // External Break + OCDM: 0x18, // OCD Message Register + OCDMS: 0x19, // OCD Message Status + REVID: 0x1, // Revision ID + } + + // 16-bit Timer/Counter Type A + TCA = struct { + CMP0L __reg + CMP0H __reg + CMP0BUFL __reg + CMP0BUFH __reg + CMP1L __reg + CMP1H __reg + CMP1BUFL __reg + CMP1BUFH __reg + CMP2L __reg + CMP2H __reg + CMP2BUFL __reg + CMP2BUFH __reg + CTRLFCLR __reg + CTRLFSET __reg + PERBUFL __reg + PERBUFH __reg + HCMP0 __reg + HCMP1 __reg + HCMP2 __reg + HCNT __reg + HPER __reg + LCMP0 __reg + LCMP1 __reg + LCMP2 __reg + LCNT __reg + LPER __reg + }{ + CMP0L: 0x28, // Compare 0 + CMP0H: 0x28, // Compare 0 + CMP0BUFL: 0x38, // Compare 0 Buffer + CMP0BUFH: 0x38, // Compare 0 Buffer + CMP1L: 0x2a, // Compare 1 + CMP1H: 0x2a, // Compare 1 + CMP1BUFL: 0x3a, // Compare 1 Buffer + CMP1BUFH: 0x3a, // Compare 1 Buffer + CMP2L: 0x2c, // Compare 2 + CMP2H: 0x2c, // Compare 2 + CMP2BUFL: 0x3c, // Compare 2 Buffer + CMP2BUFH: 0x3c, // Compare 2 Buffer + CTRLFCLR: 0x6, // Control F Clear + CTRLFSET: 0x7, // Control F Set + PERBUFL: 0x36, // Period Buffer + PERBUFH: 0x36, // Period Buffer + HCMP0: 0x29, // High Compare + HCMP1: 0x2b, // High Compare + HCMP2: 0x2d, // High Compare + HCNT: 0x21, // High Count + HPER: 0x27, // High Period + LCMP0: 0x28, // Low Compare + LCMP1: 0x2a, // Low Compare + LCMP2: 0x2c, // Low Compare + LCNT: 0x20, // Low Count + LPER: 0x26, // Low Period + } + + // 16-bit Timer Type B + TCB = struct { + CCMPL __reg + CCMPH __reg + }{ + CCMPL: 0xc, // Compare or Capture + CCMPH: 0xc, // Compare or Capture + } + + // Two-Wire Interface + TWI = struct { + BRIDGECTRL __reg + MADDR __reg + MBAUD __reg + MCTRLA __reg + MCTRLB __reg + MDATA __reg + MSTATUS __reg + SADDR __reg + SADDRMASK __reg + SCTRLA __reg + SCTRLB __reg + SDATA __reg + SSTATUS __reg + }{ + BRIDGECTRL: 0x1, // Bridge Control + MADDR: 0x7, // Master Address + MBAUD: 0x6, // Master Baurd Rate Control + MCTRLA: 0x3, // Master Control A + MCTRLB: 0x4, // Master Control B + MDATA: 0x8, // Master Data + MSTATUS: 0x5, // Master Status + SADDR: 0xc, // Slave Address + SADDRMASK: 0xe, // Slave Address Mask + SCTRLA: 0x9, // Slave Control A + SCTRLB: 0xa, // Slave Control B + SDATA: 0xd, // Slave Data + SSTATUS: 0xb, // Slave Status + } + + // Universal Synchronous and Asynchronous Receiver and Transmitter + USART = struct { + BAUDL __reg + BAUDH __reg + RXDATAH __reg + RXDATAL __reg + RXPLCTRL __reg + TXDATAH __reg + TXDATAL __reg + TXPLCTRL __reg + }{ + BAUDL: 0x8, // Baud Rate + BAUDH: 0x8, // Baud Rate + RXDATAH: 0x1, // Receive Data High Byte + RXDATAL: 0x0, // Receive Data Low Byte + RXPLCTRL: 0xe, // IRCOM Receiver Pulse Length Control + TXDATAH: 0x3, // Transmit Data High Byte + TXDATAL: 0x2, // Transmit Data Low Byte + TXPLCTRL: 0xd, // IRCOM Transmitter Pulse Length Control + } + + // User Row + USERROW = struct { + USERROW0 __reg + USERROW1 __reg + USERROW2 __reg + USERROW3 __reg + USERROW4 __reg + USERROW5 __reg + USERROW6 __reg + USERROW7 __reg + USERROW8 __reg + USERROW9 __reg + USERROW10 __reg + USERROW11 __reg + USERROW12 __reg + USERROW13 __reg + USERROW14 __reg + USERROW15 __reg + USERROW16 __reg + USERROW17 __reg + USERROW18 __reg + USERROW19 __reg + USERROW20 __reg + USERROW21 __reg + USERROW22 __reg + USERROW23 __reg + USERROW24 __reg + USERROW25 __reg + USERROW26 __reg + USERROW27 __reg + USERROW28 __reg + USERROW29 __reg + USERROW30 __reg + USERROW31 __reg + USERROW32 __reg + USERROW33 __reg + USERROW34 __reg + USERROW35 __reg + USERROW36 __reg + USERROW37 __reg + USERROW38 __reg + USERROW39 __reg + USERROW40 __reg + USERROW41 __reg + USERROW42 __reg + USERROW43 __reg + USERROW44 __reg + USERROW45 __reg + USERROW46 __reg + USERROW47 __reg + USERROW48 __reg + USERROW49 __reg + USERROW50 __reg + USERROW51 __reg + USERROW52 __reg + USERROW53 __reg + USERROW54 __reg + USERROW55 __reg + USERROW56 __reg + USERROW57 __reg + USERROW58 __reg + USERROW59 __reg + USERROW60 __reg + USERROW61 __reg + USERROW62 __reg + USERROW63 __reg + }{ + USERROW0: 0x0, // User Row Byte 0 + USERROW1: 0x1, // User Row Byte 1 + USERROW2: 0x2, // User Row Byte 2 + USERROW3: 0x3, // User Row Byte 3 + USERROW4: 0x4, // User Row Byte 4 + USERROW5: 0x5, // User Row Byte 5 + USERROW6: 0x6, // User Row Byte 6 + USERROW7: 0x7, // User Row Byte 7 + USERROW8: 0x8, // User Row Byte 8 + USERROW9: 0x9, // User Row Byte 9 + USERROW10: 0xa, // User Row Byte 10 + USERROW11: 0xb, // User Row Byte 11 + USERROW12: 0xc, // User Row Byte 12 + USERROW13: 0xd, // User Row Byte 13 + USERROW14: 0xe, // User Row Byte 14 + USERROW15: 0xf, // User Row Byte 15 + USERROW16: 0x10, // User Row Byte 16 + USERROW17: 0x11, // User Row Byte 17 + USERROW18: 0x12, // User Row Byte 18 + USERROW19: 0x13, // User Row Byte 19 + USERROW20: 0x14, // User Row Byte 20 + USERROW21: 0x15, // User Row Byte 21 + USERROW22: 0x16, // User Row Byte 22 + USERROW23: 0x17, // User Row Byte 23 + USERROW24: 0x18, // User Row Byte 24 + USERROW25: 0x19, // User Row Byte 25 + USERROW26: 0x1a, // User Row Byte 26 + USERROW27: 0x1b, // User Row Byte 27 + USERROW28: 0x1c, // User Row Byte 28 + USERROW29: 0x1d, // User Row Byte 29 + USERROW30: 0x1e, // User Row Byte 30 + USERROW31: 0x1f, // User Row Byte 31 + USERROW32: 0x20, // User Row Byte 32 + USERROW33: 0x21, // User Row Byte 33 + USERROW34: 0x22, // User Row Byte 34 + USERROW35: 0x23, // User Row Byte 35 + USERROW36: 0x24, // User Row Byte 36 + USERROW37: 0x25, // User Row Byte 37 + USERROW38: 0x26, // User Row Byte 38 + USERROW39: 0x27, // User Row Byte 39 + USERROW40: 0x28, // User Row Byte 40 + USERROW41: 0x29, // User Row Byte 41 + USERROW42: 0x2a, // User Row Byte 42 + USERROW43: 0x2b, // User Row Byte 43 + USERROW44: 0x2c, // User Row Byte 44 + USERROW45: 0x2d, // User Row Byte 45 + USERROW46: 0x2e, // User Row Byte 46 + USERROW47: 0x2f, // User Row Byte 47 + USERROW48: 0x30, // User Row Byte 48 + USERROW49: 0x31, // User Row Byte 49 + USERROW50: 0x32, // User Row Byte 50 + USERROW51: 0x33, // User Row Byte 51 + USERROW52: 0x34, // User Row Byte 52 + USERROW53: 0x35, // User Row Byte 53 + USERROW54: 0x36, // User Row Byte 54 + USERROW55: 0x37, // User Row Byte 55 + USERROW56: 0x38, // User Row Byte 56 + USERROW57: 0x39, // User Row Byte 57 + USERROW58: 0x3a, // User Row Byte 58 + USERROW59: 0x3b, // User Row Byte 59 + USERROW60: 0x3c, // User Row Byte 60 + USERROW61: 0x3d, // User Row Byte 61 + USERROW62: 0x3e, // User Row Byte 62 + USERROW63: 0x3f, // User Row Byte 63 + } + + // Virtual Ports + VPORT = struct { + }{} + + // Voltage reference + VREF = struct { + }{} + + // Watch-Dog Timer + WDT = struct { + }{} +) + +// Bitfields for AC: Analog Comparator +const ( + // DACREF: Referance scale control + DACREF_DATA = 0xff // DAC voltage reference + + // MUXCTRLA: Mux Control A + MUXCTRLA_INVERT = 0x80 // Invert AC Output + MUXCTRLA_MUXNEG = 0x3 // Negative Input MUX Selection + MUXCTRLA_MUXPOS = 0x18 // Positive Input MUX Selection +) + +// Bitfields for ADC: Analog to Digital Converter +const ( + // COMMAND: Command + COMMAND_STCONV = 0x1 // Start Conversion Operation + + // CTRLE: Control E + CTRLE_WINCM = 0x7 // Window Comparator Mode + + // MUXPOS: Positive mux input + MUXPOS_MUXPOS = 0x1f // Analog Channel Selection Bits + + // SAMPCTRL: Sample Control + SAMPCTRL_SAMPLEN = 0x1f // Sample lenght +) + +// Bitfields for BOD: Bod interface +const ( + // VLMCTRLA: Voltage level monitor Control + VLMCTRLA_VLMLVL = 0x3 // voltage level monitor level +) + +// Bitfields for CCL: Configurable Custom Logic +const ( + // INTCTRL0: Interrupt Control 0 + INTCTRL0_INTMODE0 = 0x3 // Interrupt Mode for LUT0 + INTCTRL0_INTMODE1 = 0xc // Interrupt Mode for LUT1 + INTCTRL0_INTMODE2 = 0x30 // Interrupt Mode for LUT2 + INTCTRL0_INTMODE3 = 0xc0 // Interrupt Mode for LUT3 + + // LUT0CTRLA: LUT Control 0 A + LUT0CTRLA_CLKSRC = 0xe // Clock Source Selection + LUT0CTRLA_EDGEDET = 0x80 // Edge Detection Enable + LUT0CTRLA_ENABLE = 0x1 // LUT Enable + LUT0CTRLA_FILTSEL = 0x30 // Filter Selection + LUT0CTRLA_OUTEN = 0x40 // Output Enable + + // LUT0CTRLB: LUT Control 0 B + LUT0CTRLB_INSEL0 = 0xf // LUT Input 0 Source Selection + LUT0CTRLB_INSEL1 = 0xf0 // LUT Input 1 Source Selection + + // LUT0CTRLC: LUT Control 0 C + LUT0CTRLC_INSEL2 = 0xf // LUT Input 2 Source Selection + + // LUT1CTRLA: LUT Control 1 A + LUT1CTRLA_CLKSRC = 0xe // Clock Source Selection + LUT1CTRLA_EDGEDET = 0x80 // Edge Detection Enable + LUT1CTRLA_ENABLE = 0x1 // LUT Enable + LUT1CTRLA_FILTSEL = 0x30 // Filter Selection + LUT1CTRLA_OUTEN = 0x40 // Output Enable + + // LUT1CTRLB: LUT Control 1 B + LUT1CTRLB_INSEL0 = 0xf // LUT Input 0 Source Selection + LUT1CTRLB_INSEL1 = 0xf0 // LUT Input 1 Source Selection + + // LUT1CTRLC: LUT Control 1 C + LUT1CTRLC_INSEL2 = 0xf // LUT Input 2 Source Selection + + // LUT2CTRLA: LUT Control 2 A + LUT2CTRLA_CLKSRC = 0xe // Clock Source Selection + LUT2CTRLA_EDGEDET = 0x80 // Edge Detection Enable + LUT2CTRLA_ENABLE = 0x1 // LUT Enable + LUT2CTRLA_FILTSEL = 0x30 // Filter Selection + LUT2CTRLA_OUTEN = 0x40 // Output Enable + + // LUT2CTRLB: LUT Control 2 B + LUT2CTRLB_INSEL0 = 0xf // LUT Input 0 Source Selection + LUT2CTRLB_INSEL1 = 0xf0 // LUT Input 1 Source Selection + + // LUT2CTRLC: LUT Control 2 C + LUT2CTRLC_INSEL2 = 0xf // LUT Input 2 Source Selection + + // LUT3CTRLA: LUT Control 3 A + LUT3CTRLA_CLKSRC = 0xe // Clock Source Selection + LUT3CTRLA_EDGEDET = 0x80 // Edge Detection Enable + LUT3CTRLA_ENABLE = 0x1 // LUT Enable + LUT3CTRLA_FILTSEL = 0x30 // Filter Selection + LUT3CTRLA_OUTEN = 0x40 // Output Enable + + // LUT3CTRLB: LUT Control 3 B + LUT3CTRLB_INSEL0 = 0xf // LUT Input 0 Source Selection + LUT3CTRLB_INSEL1 = 0xf0 // LUT Input 1 Source Selection + + // LUT3CTRLC: LUT Control 3 C + LUT3CTRLC_INSEL2 = 0xf // LUT Input 2 Source Selection + + // SEQCTRL0: Sequential Control 0 + SEQCTRL0_SEQSEL = 0x7 // Sequential Selection +) + +// Bitfields for CLKCTRL: Clock controller +const ( + // MCLKCTRLA: MCLK Control A + MCLKCTRLA_CLKOUT = 0x80 // System clock out + MCLKCTRLA_CLKSEL = 0x3 // clock select + + // MCLKCTRLB: MCLK Control B + MCLKCTRLB_PDIV = 0x1e // Prescaler division + MCLKCTRLB_PEN = 0x1 // Prescaler enable + + // MCLKLOCK: MCLK Lock + MCLKLOCK_LOCKEN = 0x1 // lock ebable + + // MCLKSTATUS: MCLK Status + MCLKSTATUS_EXTS = 0x80 // External Clock status + MCLKSTATUS_OSC20MS = 0x10 // 20MHz oscillator status + MCLKSTATUS_OSC32KS = 0x20 // 32KHz oscillator status + MCLKSTATUS_SOSC = 0x1 // System Oscillator changing + MCLKSTATUS_XOSC32KS = 0x40 // 32.768 kHz Crystal Oscillator status + + // OSC20MCALIBA: OSC20M Calibration A + OSC20MCALIBA_CALSEL20M = 0x80 // Calibration freq select + OSC20MCALIBA_CAL20M = 0x7f // Calibration + + // OSC20MCALIBB: OSC20M Calibration B + OSC20MCALIBB_LOCK = 0x80 // Lock + OSC20MCALIBB_TEMPCAL20M = 0xf // Oscillator temperature coefficient + + // OSC20MCTRLA: OSC20M Control A + OSC20MCTRLA_RUNSTDBY = 0x2 // Run standby + + // OSC32KCALIB: OSC32K Calibration + OSC32KCALIB_CAL32K = 0x3f // Calibration + + // OSC32KCTRLA: OSC32K Control A + OSC32KCTRLA_RUNSTDBY = 0x2 // Run standby + + // XOSC32KCTRLA: XOSC32K Control A + XOSC32KCTRLA_CSUT = 0x30 // Crystal startup time + XOSC32KCTRLA_ENABLE = 0x1 // Enable + XOSC32KCTRLA_RUNSTDBY = 0x2 // Run standby + XOSC32KCTRLA_SEL = 0x4 // Select +) + +// Bitfields for CPU: CPU +const ( + // CCP: Configuration Change Protection + CCP_CCP = 0xff // CCP signature + + // SREG: Status Register + SREG_C = 0x1 // Carry Flag + SREG_H = 0x20 // Half Carry Flag + SREG_I = 0x80 // Global Interrupt Enable Flag + SREG_N = 0x4 // Negative Flag + SREG_S = 0x10 // N Exclusive Or V Flag + SREG_T = 0x40 // Transfer Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_Z = 0x2 // Zero Flag +) + +// Bitfields for CPUINT: Interrupt Controller +const ( + // LVL0PRI: Interrupt Level 0 Priority + LVL0PRI_LVL0PRI = 0xff // Interrupt Level Priority + + // LVL1VEC: Interrupt Level 1 Priority Vector + LVL1VEC_LVL1VEC = 0xff // Interrupt Vector with High Priority +) + +// Bitfields for EVSYS: Event System +const ( + // CHANNEL0: Multiplexer Channel 0 + CHANNEL0_GENERATOR = 0xff // Generator selector + + // CHANNEL1: Multiplexer Channel 1 + CHANNEL1_GENERATOR = 0xff // Generator selector + + // CHANNEL2: Multiplexer Channel 2 + CHANNEL2_GENERATOR = 0xff // Generator selector + + // CHANNEL3: Multiplexer Channel 3 + CHANNEL3_GENERATOR = 0xff // Generator selector + + // CHANNEL4: Multiplexer Channel 4 + CHANNEL4_GENERATOR = 0xff // Generator selector + + // CHANNEL5: Multiplexer Channel 5 + CHANNEL5_GENERATOR = 0xff // Generator selector + + // CHANNEL6: Multiplexer Channel 6 + CHANNEL6_GENERATOR = 0xff // Generator selector + + // CHANNEL7: Multiplexer Channel 7 + CHANNEL7_GENERATOR = 0xff // Generator selector + + // STROBE: Channel Strobe + STROBE_STROBE0 = 0xff // Software event on channels + + // USERADC0: User ADC0 + USERADC0_CHANNEL = 0xff // Channel selector + + // USERCCLLUT0A: User CCL LUT0 Event A + USERCCLLUT0A_CHANNEL = 0xff // Channel selector + + // USERCCLLUT0B: User CCL LUT0 Event B + USERCCLLUT0B_CHANNEL = 0xff // Channel selector + + // USERCCLLUT1A: User CCL LUT1 Event A + USERCCLLUT1A_CHANNEL = 0xff // Channel selector + + // USERCCLLUT1B: User CCL LUT1 Event B + USERCCLLUT1B_CHANNEL = 0xff // Channel selector + + // USERCCLLUT2A: User CCL LUT2 Event A + USERCCLLUT2A_CHANNEL = 0xff // Channel selector + + // USERCCLLUT2B: User CCL LUT2 Event B + USERCCLLUT2B_CHANNEL = 0xff // Channel selector + + // USERCCLLUT3A: User CCL LUT3 Event A + USERCCLLUT3A_CHANNEL = 0xff // Channel selector + + // USERCCLLUT3B: User CCL LUT3 Event B + USERCCLLUT3B_CHANNEL = 0xff // Channel selector + + // USEREVOUTA: User EVOUT Port A + USEREVOUTA_CHANNEL = 0xff // Channel selector + + // USEREVOUTB: User EVOUT Port B + USEREVOUTB_CHANNEL = 0xff // Channel selector + + // USEREVOUTC: User EVOUT Port C + USEREVOUTC_CHANNEL = 0xff // Channel selector + + // USEREVOUTD: User EVOUT Port D + USEREVOUTD_CHANNEL = 0xff // Channel selector + + // USEREVOUTE: User EVOUT Port E + USEREVOUTE_CHANNEL = 0xff // Channel selector + + // USEREVOUTF: User EVOUT Port F + USEREVOUTF_CHANNEL = 0xff // Channel selector + + // USERTCA0: User TCA0 + USERTCA0_CHANNEL = 0xff // Channel selector + + // USERTCB0: User TCB0 + USERTCB0_CHANNEL = 0xff // Channel selector + + // USERTCB1: User TCB1 + USERTCB1_CHANNEL = 0xff // Channel selector + + // USERTCB2: User TCB2 + USERTCB2_CHANNEL = 0xff // Channel selector + + // USERTCB3: User TCB3 + USERTCB3_CHANNEL = 0xff // Channel selector + + // USERUSART0: User USART0 + USERUSART0_CHANNEL = 0xff // Channel selector + + // USERUSART1: User USART1 + USERUSART1_CHANNEL = 0xff // Channel selector + + // USERUSART2: User USART2 + USERUSART2_CHANNEL = 0xff // Channel selector + + // USERUSART3: User USART3 + USERUSART3_CHANNEL = 0xff // Channel selector +) + +// Bitfields for FUSE: Fuses +const ( + // BODCFG: BOD Configuration + BODCFG_ACTIVE = 0xc // BOD Operation in Active Mode + BODCFG_LVL = 0xe0 // BOD Level + BODCFG_SAMPFREQ = 0x10 // BOD Sample Frequency + BODCFG_SLEEP = 0x3 // BOD Operation in Sleep Mode + + // OSCCFG: Oscillator Configuration + OSCCFG_FREQSEL = 0x3 // Frequency Select + OSCCFG_OSCLOCK = 0x80 // Oscillator Lock + + // SYSCFG0: System Configuration 0 + SYSCFG0_CRCSRC = 0xc0 // CRC Source + SYSCFG0_EESAVE = 0x1 // EEPROM Save + SYSCFG0_RSTPINCFG = 0x8 // Reset Pin Configuration + + // SYSCFG1: System Configuration 1 + SYSCFG1_SUT = 0x7 // Startup Time + + // TCD0CFG: TCD0 Configuration + TCD0CFG_CMPA = 0x1 // Compare A Default Output Value + TCD0CFG_CMPAEN = 0x10 // Compare A Output Enable + TCD0CFG_CMPB = 0x2 // Compare B Default Output Value + TCD0CFG_CMPBEN = 0x20 // Compare B Output Enable + TCD0CFG_CMPC = 0x4 // Compare C Default Output Value + TCD0CFG_CMPCEN = 0x40 // Compare C Output Enable + TCD0CFG_CMPD = 0x8 // Compare D Default Output Value + TCD0CFG_CMPDEN = 0x80 // Compare D Output Enable + + // WDTCFG: Watchdog Configuration + WDTCFG_PERIOD = 0xf // Watchdog Timeout Period + WDTCFG_WINDOW = 0xf0 // Watchdog Window Timeout Period +) + +// Bitfields for LOCKBIT: Lockbit +const ( + // LOCKBIT: Lock Bits + LOCKBIT_LB = 0xff // Lock Bits +) + +// Bitfields for NVMBIST: BIST in the NVMCTRL module +const ( + // ADDRPAT: Address pattern + ADDRPAT_AMODE = 0x70 // Address mode + ADDRPAT_XMODE = 0x3 // X address mode + ADDRPAT_YMODE = 0xc // Y address mode + + // DATAPAT: Data pattern + DATAPAT_PATTERN = 0x3 // Data check pattern + END_END = 0xffffff +) + +// Bitfields for PORT: I/O Ports +const ( + // PIN0CTRL: Pin 0 Control + PIN0CTRL_INVEN = 0x80 // Inverted I/O Enable + PIN0CTRL_ISC = 0x7 // Input/Sense Configuration + PIN0CTRL_PULLUPEN = 0x8 // Pullup enable + + // PIN1CTRL: Pin 1 Control + PIN1CTRL_INVEN = 0x80 // Inverted I/O Enable + PIN1CTRL_ISC = 0x7 // Input/Sense Configuration + PIN1CTRL_PULLUPEN = 0x8 // Pullup enable + + // PIN2CTRL: Pin 2 Control + PIN2CTRL_INVEN = 0x80 // Inverted I/O Enable + PIN2CTRL_ISC = 0x7 // Input/Sense Configuration + PIN2CTRL_PULLUPEN = 0x8 // Pullup enable + + // PIN3CTRL: Pin 3 Control + PIN3CTRL_INVEN = 0x80 // Inverted I/O Enable + PIN3CTRL_ISC = 0x7 // Input/Sense Configuration + PIN3CTRL_PULLUPEN = 0x8 // Pullup enable + + // PIN4CTRL: Pin 4 Control + PIN4CTRL_INVEN = 0x80 // Inverted I/O Enable + PIN4CTRL_ISC = 0x7 // Input/Sense Configuration + PIN4CTRL_PULLUPEN = 0x8 // Pullup enable + + // PIN5CTRL: Pin 5 Control + PIN5CTRL_INVEN = 0x80 // Inverted I/O Enable + PIN5CTRL_ISC = 0x7 // Input/Sense Configuration + PIN5CTRL_PULLUPEN = 0x8 // Pullup enable + + // PIN6CTRL: Pin 6 Control + PIN6CTRL_INVEN = 0x80 // Inverted I/O Enable + PIN6CTRL_ISC = 0x7 // Input/Sense Configuration + PIN6CTRL_PULLUPEN = 0x8 // Pullup enable + + // PIN7CTRL: Pin 7 Control + PIN7CTRL_INVEN = 0x80 // Inverted I/O Enable + PIN7CTRL_ISC = 0x7 // Input/Sense Configuration + PIN7CTRL_PULLUPEN = 0x8 // Pullup enable + + // PORTCTRL: Port Control + PORTCTRL_SRL = 0x1 // Slew Rate Limit Enable +) + +// Bitfields for PORTMUX: Port Multiplexer +const ( + // CCLROUTEA: Port Multiplexer CCL + CCLROUTEA_LUT0 = 0x1 // CCL LUT0 + CCLROUTEA_LUT1 = 0x2 // CCL LUT1 + CCLROUTEA_LUT2 = 0x4 // CCL LUT2 + CCLROUTEA_LUT3 = 0x8 // CCL LUT3 + + // EVSYSROUTEA: Port Multiplexer EVSYS + EVSYSROUTEA_EVOUT0 = 0x1 // Event Output 0 + EVSYSROUTEA_EVOUT1 = 0x2 // Event Output 1 + EVSYSROUTEA_EVOUT2 = 0x4 // Event Output 2 + EVSYSROUTEA_EVOUT3 = 0x8 // Event Output 3 + EVSYSROUTEA_EVOUT4 = 0x10 // Event Output 4 + EVSYSROUTEA_EVOUT5 = 0x20 // Event Output 5 + + // TCAROUTEA: Port Multiplexer TCA + TCAROUTEA_TCA0 = 0x7 // Port Multiplexer TCA0 + + // TCBROUTEA: Port Multiplexer TCB + TCBROUTEA_TCB0 = 0x1 // Port Multiplexer TCB0 + TCBROUTEA_TCB1 = 0x2 // Port Multiplexer TCB1 + TCBROUTEA_TCB2 = 0x4 // Port Multiplexer TCB2 + TCBROUTEA_TCB3 = 0x8 // Port Multiplexer TCB3 + + // TWISPIROUTEA: Port Multiplexer TWI and SPI + TWISPIROUTEA_SPI0 = 0x3 // Port Multiplexer SPI0 + TWISPIROUTEA_TWI0 = 0x30 // Port Multiplexer TWI0 + + // USARTROUTEA: Port Multiplexer USART register A + USARTROUTEA_USART0 = 0x3 // Port Multiplexer USART0 + USARTROUTEA_USART1 = 0xc // Port Multiplexer USART1 + USARTROUTEA_USART2 = 0x30 // Port Multiplexer USART2 + USARTROUTEA_USART3 = 0xc0 // Port Multiplexer USART3 +) + +// Bitfields for RSTCTRL: Reset controller +const ( + // RSTFR: Reset Flags + RSTFR_BORF = 0x2 // Brown out detector Reset flag + RSTFR_EXTRF = 0x4 // External Reset flag + RSTFR_PORF = 0x1 // Power on Reset flag + RSTFR_SWRF = 0x10 // Software Reset flag + RSTFR_UPDIRF = 0x20 // UPDI Reset flag + RSTFR_WDRF = 0x8 // Watch dog Reset flag + + // SWRR: Software Reset + SWRR_SWRE = 0x1 // Software reset enable +) + +// Bitfields for RTC: Real-Time Counter +const ( + // CLKSEL: Clock Select + CLKSEL_CLKSEL = 0x3 // Clock Select + + // PITCTRLA: PIT Control A + PITCTRLA_PERIOD = 0x78 // Period + PITCTRLA_PITEN = 0x1 // Enable + + // PITDBGCTRL: PIT Debug control + PITDBGCTRL_DBGRUN = 0x1 // Run in debug + + // PITINTCTRL: PIT Interrupt Control + PITINTCTRL_PI = 0x1 // Periodic Interrupt + + // PITINTFLAGS: PIT Interrupt Flags + PITINTFLAGS_PI = 0x1 // Periodic Interrupt + + // PITSTATUS: PIT Status + PITSTATUS_CTRLBUSY = 0x1 // CTRLA Synchronization Busy Flag +) + +// Bitfields for SYSCFG: System Configuration Registers +const ( + // EXTBRK: External Break + EXTBRK_ENEXTBRK = 0x1 // External break enable + + // OCDMS: OCD Message Status + OCDMS_OCDMR = 0x1 // OCD Message Read +) + +// Bitfields for TCA: 16-bit Timer/Counter Type A +const ( + // CTRLFCLR: Control F Clear + CTRLFCLR_CMP0BV = 0x2 // Compare 0 Buffer Valid + CTRLFCLR_CMP1BV = 0x4 // Compare 1 Buffer Valid + CTRLFCLR_CMP2BV = 0x8 // Compare 2 Buffer Valid + CTRLFCLR_PERBV = 0x1 // Period Buffer Valid + + // CTRLFSET: Control F Set + CTRLFSET_CMP0BV = 0x2 // Compare 0 Buffer Valid + CTRLFSET_CMP1BV = 0x4 // Compare 1 Buffer Valid + CTRLFSET_CMP2BV = 0x8 // Compare 2 Buffer Valid + CTRLFSET_PERBV = 0x1 // Period Buffer Valid +) + +// Bitfields for TWI: Two-Wire Interface +const ( + // BRIDGECTRL: Bridge Control + BRIDGECTRL_ENABLE = 0x1 // Bridge Enable + BRIDGECTRL_FMPEN = 0x2 // FM Plus Enable + BRIDGECTRL_SDAHOLD = 0xc // SDA Hold Time + + // MCTRLA: Master Control A + MCTRLA_ENABLE = 0x1 // Enable TWI Master + MCTRLA_QCEN = 0x10 // Quick Command Enable + MCTRLA_RIEN = 0x80 // Read Interrupt Enable + MCTRLA_SMEN = 0x2 // Smart Mode Enable + MCTRLA_TIMEOUT = 0xc // Inactive Bus Timeout + MCTRLA_WIEN = 0x40 // Write Interrupt Enable + + // MCTRLB: Master Control B + MCTRLB_ACKACT = 0x4 // Acknowledge Action + MCTRLB_FLUSH = 0x8 // Flush + MCTRLB_MCMD = 0x3 // Command + + // MSTATUS: Master Status + MSTATUS_ARBLOST = 0x8 // Arbitration Lost + MSTATUS_BUSERR = 0x4 // Bus Error + MSTATUS_BUSSTATE = 0x3 // Bus State + MSTATUS_CLKHOLD = 0x20 // Clock Hold + MSTATUS_RIF = 0x80 // Read Interrupt Flag + MSTATUS_RXACK = 0x10 // Received Acknowledge + MSTATUS_WIF = 0x40 // Write Interrupt Flag + + // SADDRMASK: Slave Address Mask + SADDRMASK_ADDREN = 0x1 // Address Enable + SADDRMASK_ADDRMASK = 0xfe // Address Mask + + // SCTRLA: Slave Control A + SCTRLA_APIEN = 0x40 // Address/Stop Interrupt Enable + SCTRLA_DIEN = 0x80 // Data Interrupt Enable + SCTRLA_ENABLE = 0x1 // Enable TWI Slave + SCTRLA_PIEN = 0x20 // Stop Interrupt Enable + SCTRLA_PMEN = 0x4 // Promiscuous Mode Enable + SCTRLA_SMEN = 0x2 // Smart Mode Enable + + // SCTRLB: Slave Control B + SCTRLB_ACKACT = 0x4 // Acknowledge Action + SCTRLB_SCMD = 0x3 // Command + + // SSTATUS: Slave Status + SSTATUS_AP = 0x1 // Slave Address or Stop + SSTATUS_APIF = 0x40 // Address/Stop Interrupt Flag + SSTATUS_BUSERR = 0x4 // Bus Error + SSTATUS_CLKHOLD = 0x20 // Clock Hold + SSTATUS_COLL = 0x8 // Collision + SSTATUS_DIF = 0x80 // Data Interrupt Flag + SSTATUS_DIR = 0x2 // Read/Write Direction + SSTATUS_RXACK = 0x10 // Received Acknowledge +) + +// Bitfields for USART: Universal Synchronous and Asynchronous Receiver and Transmitter +const ( + // RXDATAH: Receive Data High Byte + RXDATAH_BUFOVF = 0x40 // Buffer Overflow + RXDATAH_DATA8 = 0x1 // Receiver Data Register + RXDATAH_FERR = 0x4 // Frame Error + RXDATAH_PERR = 0x2 // Parity Error + RXDATAH_RXCIF = 0x80 // Receive Complete Interrupt Flag + + // RXDATAL: Receive Data Low Byte + RXDATAL_DATA = 0xff // RX Data + + // RXPLCTRL: IRCOM Receiver Pulse Length Control + RXPLCTRL_RXPL = 0x7f // Receiver Pulse Lenght + + // TXDATAH: Transmit Data High Byte + TXDATAH_DATA8 = 0x1 // Transmit Data Register (CHSIZE=9bit) + + // TXDATAL: Transmit Data Low Byte + TXDATAL_DATA = 0xff // Transmit Data Register + + // TXPLCTRL: IRCOM Transmitter Pulse Length Control + TXPLCTRL_TXPL = 0xff // Transmit pulse length +) diff --git a/src/device/avr/atmega4809.ld b/src/device/avr/atmega4809.ld new file mode 100644 index 00000000..d2b6543d --- /dev/null +++ b/src/device/avr/atmega4809.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega4809.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0xc000; +__ram_size = 0x1800; +__num_isrs = 43; diff --git a/src/device/avr/atmega48a.go b/src/device/avr/atmega48a.go new file mode 100644 index 00000000..bd437e22 --- /dev/null +++ b/src/device/avr/atmega48a.go @@ -0,0 +1,642 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega48A.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega48a + +// Device information for the ATmega48A. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega48A" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_PCINT0 = 3 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 4 // Pin Change Interrupt Request 0 + IRQ_PCINT2 = 5 // Pin Change Interrupt Request 1 + IRQ_WDT = 6 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 7 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 8 // Timer/Counter2 Compare Match A + IRQ_TIMER2_OVF = 9 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 10 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 11 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 12 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 13 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 14 // TimerCounter0 Compare Match A + IRQ_TIMER0_COMPB = 15 // TimerCounter0 Compare Match B + IRQ_TIMER0_OVF = 16 // Timer/Couner0 Overflow + IRQ_SPI_STC = 17 // SPI Serial Transfer Complete + IRQ_USART_RX = 18 // USART Rx Complete + IRQ_USART_UDRE = 19 // USART, Data Register Empty + IRQ_USART_TX = 20 // USART Tx Complete + IRQ_ADC = 21 // ADC Conversion Complete + IRQ_EE_READY = 22 // EEPROM Ready + IRQ_ANALOG_COMP = 23 // Analog Comparator + IRQ_TWI = 24 // Two-wire Serial Interface + IRQ_SPM_Ready = 25 // Store Program Memory Read + IRQ_max = 25 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + ADCSRB __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // The ADC Control and Status register A + ADCSRB: 0x7b, // The ADC Control and Status register B + DIDR0: 0x7e, // Digital Input Disable Register + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // I/O Port + PORT = struct { + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + }{ + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCICR __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + } + + // Serial Peripheral Interface + SPI = struct { + SPDR __reg + SPSR __reg + SPCR __reg + }{ + SPDR: 0x4e, // SPI Data Register + SPSR: 0x4d, // SPI Status Register + SPCR: 0x4c, // SPI Control Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // EEPROM + EEPROM = struct { + EEARH __reg + EEARL __reg + EEDR __reg + EECR __reg + }{ + EEARH: 0x42, // EEPROM Address Register High Byte + EEARL: 0x41, // EEPROM Address Register Low Byte + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // CPU Registers + CPU = struct { + PRR __reg + OSCCAL __reg + CLKPR __reg + SREG __reg + SPL __reg + SPH __reg + SPMCSR __reg + MCUCR __reg + MCUSR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + PRR: 0x64, // Power Reduction Register + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + SPMCSR: 0x57, // Store Program Memory Control and Status Register + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose I/O Register 2 + GPIOR1: 0x4a, // General Purpose I/O Register 1 + GPIOR0: 0x3e, // General Purpose I/O Register 0 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_SELFPRGEN = 0x1 // Self Programming enable + + // HIGH + HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PC6 as i/o pin) + HIGH_DWEN = 0x40 // Debug Wire enable + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watch-dog Timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTB0 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0xc0 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TIMSK1: Timer/Counter Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output CompareB Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output CompareA Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 + TCCR1C_FOC1B = 0x40 +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2B = 0x4 // Output Compare Flag 2B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Output Mode bits + TCCR2A_COM2B = 0x30 // Compare Output Mode bits + TCCR2A_WGM2 = 0x3 // Waveform Genration Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy + ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0xf // Analog Channel Selection Bits + + // ADCSRA: The ADC Control and Status register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCSRB: The ADC Control and Status register B + ADCSRB_ACME = 0x40 + ADCSRB_ADTS = 0x7 // ADC Auto Trigger Source bits + + // DIDR0: Digital Input Disable Register + DIDR0_ADC5D = 0x20 + DIDR0_ADC4D = 0x10 + DIDR0_ADC3D = 0x8 + DIDR0_ADC2D = 0x4 + DIDR0_ADC1D = 0x2 + DIDR0_ADC0D = 0x1 +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register + EICRA_ISC1 = 0xc // External Interrupt Sense Control 1 Bits + EICRA_ISC0 = 0x3 // External Interrupt Sense Control 0 Bits + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0x3 // External Interrupt Request 1 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0x3 // External Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0x7 // Pin Change Interrupt Enables + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0x7f // Pin Change Enable Masks + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0x7 // Pin Change Interrupt Flags +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for EEPROM: EEPROM +const ( + // EEARH: EEPROM Address Register High Byte + EEARH_EEAR8 = 0x1 + EEARH_EEAR9 = 0x2 + + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for CPU: CPU Registers +const ( + // PRR: Power Reduction Register + PRR_PRTWI = 0x80 // Power Reduction TWI + PRR_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // SPMCSR: Store Program Memory Control and Status Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read-While-Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read-While-Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory + + // MCUCR: MCU Control Register + MCUCR_PUD = 0x10 // Pull-up Disable + MCUCR_IVSEL = 0x2 // Interrupt Vector Select + MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable + + // MCUSR: MCU Status Register + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BORF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select Bits + SMCR_SE = 0x1 // Sleep Enable +) diff --git a/src/device/avr/atmega48a.ld b/src/device/avr/atmega48a.ld new file mode 100644 index 00000000..9343dd69 --- /dev/null +++ b/src/device/avr/atmega48a.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega48A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x1000; +__ram_size = 0x200; +__num_isrs = 26; diff --git a/src/device/avr/atmega48p.go b/src/device/avr/atmega48p.go new file mode 100644 index 00000000..fd12c7b1 --- /dev/null +++ b/src/device/avr/atmega48p.go @@ -0,0 +1,635 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega48P.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega48p + +// Device information for the ATmega48P. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega48P" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_PCINT0 = 3 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 4 // Pin Change Interrupt Request 0 + IRQ_PCINT2 = 5 // Pin Change Interrupt Request 1 + IRQ_WDT = 6 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 7 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 8 // Timer/Counter2 Compare Match A + IRQ_TIMER2_OVF = 9 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 10 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 11 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 12 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 13 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 14 // TimerCounter0 Compare Match A + IRQ_TIMER0_COMPB = 15 // TimerCounter0 Compare Match B + IRQ_TIMER0_OVF = 16 // Timer/Couner0 Overflow + IRQ_SPI_STC = 17 // SPI Serial Transfer Complete + IRQ_USART_RX = 18 // USART Rx Complete + IRQ_USART_UDRE = 19 // USART, Data Register Empty + IRQ_USART_TX = 20 // USART Tx Complete + IRQ_ADC = 21 // ADC Conversion Complete + IRQ_EE_READY = 22 // EEPROM Ready + IRQ_ANALOG_COMP = 23 // Analog Comparator + IRQ_TWI = 24 // Two-wire Serial Interface + IRQ_SPM_Ready = 25 // Store Program Memory Read + IRQ_max = 25 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + ADCSRB __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // The ADC Control and Status register A + ADCSRB: 0x7b, // The ADC Control and Status register B + DIDR0: 0x7e, // Digital Input Disable Register + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // I/O Port + PORT = struct { + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + }{ + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCICR __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + } + + // Serial Peripheral Interface + SPI = struct { + SPDR __reg + SPSR __reg + SPCR __reg + }{ + SPDR: 0x4e, // SPI Data Register + SPSR: 0x4d, // SPI Status Register + SPCR: 0x4c, // SPI Control Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Low Byte + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // CPU Registers + CPU = struct { + PRR __reg + OSCCAL __reg + CLKPR __reg + SREG __reg + SPL __reg + SPH __reg + SPMCSR __reg + MCUCR __reg + MCUSR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + PRR: 0x64, // Power Reduction Register + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + SPMCSR: 0x57, // Store Program Memory Control and Status Register + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose I/O Register 2 + GPIOR1: 0x4a, // General Purpose I/O Register 1 + GPIOR0: 0x3e, // General Purpose I/O Register 0 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_SELFPRGEN = 0x1 // Self Programming enable + + // HIGH + HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PC6 as i/o pin) + HIGH_DWEN = 0x40 // Debug Wire enable + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watch-dog Timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTB0 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0xc0 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TIMSK1: Timer/Counter Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output CompareB Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output CompareA Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 + TCCR1C_FOC1B = 0x40 +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2B = 0x4 // Output Compare Flag 2B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Output Mode bits + TCCR2A_COM2B = 0x30 // Compare Output Mode bits + TCCR2A_WGM2 = 0x3 // Waveform Genration Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy + ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0xf // Analog Channel Selection Bits + + // ADCSRA: The ADC Control and Status register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCSRB: The ADC Control and Status register B + ADCSRB_ACME = 0x40 + ADCSRB_ADTS = 0x7 // ADC Auto Trigger Source bits + + // DIDR0: Digital Input Disable Register + DIDR0_ADC5D = 0x20 + DIDR0_ADC4D = 0x10 + DIDR0_ADC3D = 0x8 + DIDR0_ADC2D = 0x4 + DIDR0_ADC1D = 0x2 + DIDR0_ADC0D = 0x1 +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register + EICRA_ISC1 = 0xc // External Interrupt Sense Control 1 Bits + EICRA_ISC0 = 0x3 // External Interrupt Sense Control 0 Bits + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0x3 // External Interrupt Request 1 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0x3 // External Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0x7 // Pin Change Interrupt Enables + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0x7f // Pin Change Enable Masks + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0x7 // Pin Change Interrupt Flags +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for CPU: CPU Registers +const ( + // PRR: Power Reduction Register + PRR_PRTWI = 0x80 // Power Reduction TWI + PRR_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // SPMCSR: Store Program Memory Control and Status Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read-While-Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read-While-Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SELFPRGEN = 0x1 // Self Programming Enable + + // MCUCR: MCU Control Register + MCUCR_BODS = 0x40 // BOD Sleep + MCUCR_BODSE = 0x20 // BOD Sleep Enable + MCUCR_PUD = 0x10 + + // MCUSR: MCU Status Register + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BORF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select Bits + SMCR_SE = 0x1 // Sleep Enable +) diff --git a/src/device/avr/atmega48p.ld b/src/device/avr/atmega48p.ld new file mode 100644 index 00000000..b2b4b6e7 --- /dev/null +++ b/src/device/avr/atmega48p.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega48P.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x1000; +__ram_size = 0x200; +__num_isrs = 26; diff --git a/src/device/avr/atmega48pa.go b/src/device/avr/atmega48pa.go new file mode 100644 index 00000000..6f98cc2a --- /dev/null +++ b/src/device/avr/atmega48pa.go @@ -0,0 +1,644 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega48PA.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega48pa + +// Device information for the ATmega48PA. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega48PA" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_PCINT0 = 3 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 4 // Pin Change Interrupt Request 0 + IRQ_PCINT2 = 5 // Pin Change Interrupt Request 1 + IRQ_WDT = 6 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 7 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 8 // Timer/Counter2 Compare Match A + IRQ_TIMER2_OVF = 9 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 10 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 11 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 12 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 13 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 14 // TimerCounter0 Compare Match A + IRQ_TIMER0_COMPB = 15 // TimerCounter0 Compare Match B + IRQ_TIMER0_OVF = 16 // Timer/Couner0 Overflow + IRQ_SPI_STC = 17 // SPI Serial Transfer Complete + IRQ_USART_RX = 18 // USART Rx Complete + IRQ_USART_UDRE = 19 // USART, Data Register Empty + IRQ_USART_TX = 20 // USART Tx Complete + IRQ_ADC = 21 // ADC Conversion Complete + IRQ_EE_READY = 22 // EEPROM Ready + IRQ_ANALOG_COMP = 23 // Analog Comparator + IRQ_TWI = 24 // Two-wire Serial Interface + IRQ_SPM_Ready = 25 // Store Program Memory Read + IRQ_max = 25 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + ADCSRB __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // The ADC Control and Status register A + ADCSRB: 0x7b, // The ADC Control and Status register B + DIDR0: 0x7e, // Digital Input Disable Register + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // I/O Port + PORT = struct { + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + }{ + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCICR __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + } + + // Serial Peripheral Interface + SPI = struct { + SPDR __reg + SPSR __reg + SPCR __reg + }{ + SPDR: 0x4e, // SPI Data Register + SPSR: 0x4d, // SPI Status Register + SPCR: 0x4c, // SPI Control Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // EEPROM + EEPROM = struct { + EEARH __reg + EEARL __reg + EEDR __reg + EECR __reg + }{ + EEARH: 0x42, // EEPROM Address Register High Byte + EEARL: 0x41, // EEPROM Address Register Low Byte + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // CPU Registers + CPU = struct { + PRR __reg + OSCCAL __reg + CLKPR __reg + SREG __reg + SPL __reg + SPH __reg + SPMCSR __reg + MCUCR __reg + MCUSR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + PRR: 0x64, // Power Reduction Register + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + SPMCSR: 0x57, // Store Program Memory Control and Status Register + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose I/O Register 2 + GPIOR1: 0x4a, // General Purpose I/O Register 1 + GPIOR0: 0x3e, // General Purpose I/O Register 0 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_SELFPRGEN = 0x1 // Self Programming enable + + // HIGH + HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PC6 as i/o pin) + HIGH_DWEN = 0x40 // Debug Wire enable + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watch-dog Timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTB0 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0xc0 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TIMSK1: Timer/Counter Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output CompareB Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output CompareA Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 + TCCR1C_FOC1B = 0x40 +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2B = 0x4 // Output Compare Flag 2B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Output Mode bits + TCCR2A_COM2B = 0x30 // Compare Output Mode bits + TCCR2A_WGM2 = 0x3 // Waveform Genration Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy + ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0xf // Analog Channel Selection Bits + + // ADCSRA: The ADC Control and Status register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCSRB: The ADC Control and Status register B + ADCSRB_ACME = 0x40 + ADCSRB_ADTS = 0x7 // ADC Auto Trigger Source bits + + // DIDR0: Digital Input Disable Register + DIDR0_ADC5D = 0x20 + DIDR0_ADC4D = 0x10 + DIDR0_ADC3D = 0x8 + DIDR0_ADC2D = 0x4 + DIDR0_ADC1D = 0x2 + DIDR0_ADC0D = 0x1 +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register + EICRA_ISC1 = 0xc // External Interrupt Sense Control 1 Bits + EICRA_ISC0 = 0x3 // External Interrupt Sense Control 0 Bits + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0x3 // External Interrupt Request 1 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0x3 // External Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0x7 // Pin Change Interrupt Enables + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0x7f // Pin Change Enable Masks + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0x7 // Pin Change Interrupt Flags +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for EEPROM: EEPROM +const ( + // EEARH: EEPROM Address Register High Byte + EEARH_EEAR8 = 0x1 + EEARH_EEAR9 = 0x2 + + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for CPU: CPU Registers +const ( + // PRR: Power Reduction Register + PRR_PRTWI = 0x80 // Power Reduction TWI + PRR_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // SPMCSR: Store Program Memory Control and Status Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read-While-Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read-While-Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory + + // MCUCR: MCU Control Register + MCUCR_BODS = 0x40 // BOD Sleep + MCUCR_BODSE = 0x20 // BOD Sleep Enable + MCUCR_PUD = 0x10 // Pull-up Disable + MCUCR_IVSEL = 0x2 // Interrupt Vector Select + MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable + + // MCUSR: MCU Status Register + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BORF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select Bits + SMCR_SE = 0x1 // Sleep Enable +) diff --git a/src/device/avr/atmega48pa.ld b/src/device/avr/atmega48pa.ld new file mode 100644 index 00000000..b9778f34 --- /dev/null +++ b/src/device/avr/atmega48pa.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega48PA.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x1000; +__ram_size = 0x200; +__num_isrs = 26; diff --git a/src/device/avr/atmega48pb.go b/src/device/avr/atmega48pb.go new file mode 100644 index 00000000..0ee75ed4 --- /dev/null +++ b/src/device/avr/atmega48pb.go @@ -0,0 +1,677 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega48PB.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega48pb + +// Device information for the ATmega48PB. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega48PB" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_PCINT0 = 3 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 4 // Pin Change Interrupt Request 0 + IRQ_PCINT2 = 5 // Pin Change Interrupt Request 1 + IRQ_WDT = 6 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 7 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 8 // Timer/Counter2 Compare Match A + IRQ_TIMER2_OVF = 9 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 10 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 11 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 12 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 13 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 14 // TimerCounter0 Compare Match A + IRQ_TIMER0_COMPB = 15 // TimerCounter0 Compare Match B + IRQ_TIMER0_OVF = 16 // Timer/Couner0 Overflow + IRQ_SPI_STC = 17 // SPI Serial Transfer Complete + IRQ_USART_RX = 18 // USART Rx Complete + IRQ_USART_UDRE = 19 // USART, Data Register Empty + IRQ_USART_TX = 20 // USART Tx Complete + IRQ_ADC = 21 // ADC Conversion Complete + IRQ_EE_READY = 22 // EEPROM Ready + IRQ_ANALOG_COMP = 23 // Analog Comparator + IRQ_TWI = 24 // Two-wire Serial Interface + IRQ_SPM_Ready = 25 // Store Program Memory Read + IRQ_USART_START = 26 // USART Start Edge Interrupt + IRQ_max = 26 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Device ID + DEVICEID = struct { + DEVID0 __reg + DEVID1 __reg + DEVID2 __reg + DEVID3 __reg + DEVID4 __reg + DEVID5 __reg + DEVID6 __reg + DEVID7 __reg + DEVID8 __reg + }{ + DEVID0: 0xf0, + DEVID1: 0xf1, + DEVID2: 0xf2, + DEVID3: 0xf3, + DEVID4: 0xf4, + DEVID5: 0xf5, + DEVID6: 0xf6, + DEVID7: 0xf7, + DEVID8: 0xf8, + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UCSR0D __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UCSR0D: 0xc3, // USART Control and Status Register D + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + ADCSRB __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // The ADC Control and Status register A + ADCSRB: 0x7b, // The ADC Control and Status register B + DIDR0: 0x7e, // Digital Input Disable Register + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + ACSRB __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + ACSRB: 0x4f, // Analog Comparator Status Register B + } + + // I/O Port + PORT = struct { + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + }{ + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Port E Data Register + DDRE: 0x2d, // Port E Data Direction Register + PINE: 0x2c, // Port E Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCICR __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + } + + // Serial Peripheral Interface + SPI = struct { + SPDR __reg + SPSR __reg + SPCR __reg + }{ + SPDR: 0x4e, // SPI Data Register + SPSR: 0x4d, // SPI Status Register + SPCR: 0x4c, // SPI Control Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Low Byte + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // CPU Registers + CPU = struct { + PRR __reg + OSCCAL __reg + CLKPR __reg + SREG __reg + SPL __reg + SPH __reg + SPMCSR __reg + MCUCR __reg + MCUSR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + PRR: 0x64, // Power Reduction Register + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + SPMCSR: 0x57, // Store Program Memory Control and Status Register + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose I/O Register 2 + GPIOR1: 0x4a, // General Purpose I/O Register 1 + GPIOR0: 0x3e, // General Purpose I/O Register 0 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_SELFPRGEN = 0x1 // Self Programming enable + + // HIGH + HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PC6 as i/o pin) + HIGH_DWEN = 0x40 // Debug Wire enable + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watch-dog Timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTB0 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0xc0 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity + + // UCSR0D: USART Control and Status Register D + UCSR0D_RXSIE = 0x80 // RX Start Interrupt Enable + UCSR0D_RXS = 0x40 // RX Start + UCSR0D_SFDE = 0x20 // Start Frame Detection Enable +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TIMSK1: Timer/Counter Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output CompareB Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output CompareA Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 + TCCR1C_FOC1B = 0x40 +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2B = 0x4 // Output Compare Flag 2B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Output Mode bits + TCCR2A_COM2B = 0x30 // Compare Output Mode bits + TCCR2A_WGM2 = 0x3 // Waveform Genration Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy + ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0xf // Analog Channel Selection Bits + + // ADCSRA: The ADC Control and Status register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCSRB: The ADC Control and Status register B + ADCSRB_ACME = 0x40 + ADCSRB_ADTS = 0x7 // ADC Auto Trigger Source bits + + // DIDR0: Digital Input Disable Register + DIDR0_ADC5D = 0x20 + DIDR0_ADC4D = 0x10 + DIDR0_ADC3D = 0x8 + DIDR0_ADC2D = 0x4 + DIDR0_ADC1D = 0x2 + DIDR0_ADC0D = 0x1 +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable + + // ACSRB: Analog Comparator Status Register B + ACSRB_ACOE = 0x1 // Analog Comparator Output Enable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register + EICRA_ISC1 = 0xc // External Interrupt Sense Control 1 Bits + EICRA_ISC0 = 0x3 // External Interrupt Sense Control 0 Bits + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0x3 // External Interrupt Request 1 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0x3 // External Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0x7 // Pin Change Interrupt Enables + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0x7f // Pin Change Enable Masks + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0x7 // Pin Change Interrupt Flags +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for CPU: CPU Registers +const ( + // PRR: Power Reduction Register + PRR_PRTWI = 0x80 // Power Reduction TWI + PRR_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // SPMCSR: Store Program Memory Control and Status Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read-While-Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read-While-Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SELFPRGEN = 0x1 // Self Programming Enable + + // MCUCR: MCU Control Register + MCUCR_BODS = 0x40 // BOD Sleep + MCUCR_BODSE = 0x20 // BOD Sleep Enable + MCUCR_PUD = 0x10 + + // MCUSR: MCU Status Register + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BORF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select Bits + SMCR_SE = 0x1 // Sleep Enable +) diff --git a/src/device/avr/atmega48pb.ld b/src/device/avr/atmega48pb.ld new file mode 100644 index 00000000..88c6df6e --- /dev/null +++ b/src/device/avr/atmega48pb.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega48PB.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x1000; +__ram_size = 0x200; +__num_isrs = 27; diff --git a/src/device/avr/atmega64.go b/src/device/avr/atmega64.go new file mode 100644 index 00000000..90dfe6ed --- /dev/null +++ b/src/device/avr/atmega64.go @@ -0,0 +1,670 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega64.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega64 + +// Device information for the ATmega64. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega64" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_INT3 = 4 // External Interrupt Request 3 + IRQ_INT4 = 5 // External Interrupt Request 4 + IRQ_INT5 = 6 // External Interrupt Request 5 + IRQ_INT6 = 7 // External Interrupt Request 6 + IRQ_INT7 = 8 // External Interrupt Request 7 + IRQ_TIMER2_COMP = 9 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 10 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 11 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 12 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 13 // Timer/Counter Compare Match B + IRQ_TIMER1_OVF = 14 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 15 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 16 // Timer/Counter0 Overflow + IRQ_SPI_STC = 17 // SPI Serial Transfer Complete + IRQ_USART0_RX = 18 // USART0, Rx Complete + IRQ_USART0_UDRE = 19 // USART0 Data Register Empty + IRQ_USART0_TX = 20 // USART0, Tx Complete + IRQ_ADC = 21 // ADC Conversion Complete + IRQ_EE_READY = 22 // EEPROM Ready + IRQ_ANALOG_COMP = 23 // Analog Comparator + IRQ_TIMER1_COMPC = 24 // Timer/Counter1 Compare Match C + IRQ_TIMER3_CAPT = 25 // Timer/Counter3 Capture Event + IRQ_TIMER3_COMPA = 26 // Timer/Counter3 Compare Match A + IRQ_TIMER3_COMPB = 27 // Timer/Counter3 Compare Match B + IRQ_TIMER3_COMPC = 28 // Timer/Counter3 Compare Match C + IRQ_TIMER3_OVF = 29 // Timer/Counter3 Overflow + IRQ_USART1_RX = 30 // USART1, Rx Complete + IRQ_USART1_UDRE = 31 // USART1, Data Register Empty + IRQ_USART1_TX = 32 // USART1, Tx Complete + IRQ_TWI = 33 // 2-wire Serial Interface + IRQ_SPM_READY = 34 // Store Program Memory Read + IRQ_max = 34 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog Comparator + AC = struct { + ACSR __reg + }{ + ACSR: 0x28, // Analog Comparator Control And Status Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + ADCSRB __reg + }{ + ADMUX: 0x27, // The ADC multiplexer Selection Register + ADCL: 0x24, // ADC Data Register Bytes + ADCH: 0x24, // ADC Data Register Bytes + ADCSRA: 0x26, // The ADC Control and Status register A + ADCSRB: 0x8e, // The ADC Control and Status register B + } + + // Serial Peripheral Interface + SPI = struct { + SPDR __reg + SPSR __reg + SPCR __reg + }{ + SPDR: 0x2f, // SPI Data Register + SPSR: 0x2e, // SPI Status Register + SPCR: 0x2d, // SPI Control Register + } + + // Two Wire Serial Interface + TWI = struct { + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWBR: 0x70, // TWI Bit Rate register + TWCR: 0x74, // TWI Control Register + TWSR: 0x71, // TWI Status Register + TWDR: 0x73, // TWI Data register + TWAR: 0x72, // TWI (Slave) Address register + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0H __reg + UBRR0L __reg + UDR1 __reg + UCSR1A __reg + UCSR1B __reg + UCSR1C __reg + UBRR1H __reg + UBRR1L __reg + }{ + UDR0: 0x2c, // USART I/O Data Register + UCSR0A: 0x2b, // USART Control and Status Register A + UCSR0B: 0x2a, // USART Control and Status Register B + UCSR0C: 0x95, // USART Control and Status Register C + UBRR0H: 0x90, // USART Baud Rate Register Hight Byte + UBRR0L: 0x29, // USART Baud Rate Register Low Byte + UDR1: 0x9c, // USART I/O Data Register + UCSR1A: 0x9b, // USART Control and Status Register A + UCSR1B: 0x9a, // USART Control and Status Register B + UCSR1C: 0x9d, // USART Control and Status Register C + UBRR1H: 0x98, // USART Baud Rate Register Hight Byte + UBRR1L: 0x99, // USART Baud Rate Register Low Byte + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + MCUCR __reg + XMCRA __reg + XMCRB __reg + OSCCAL __reg + XDIV __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + MCUCR: 0x55, // MCU Control Register + XMCRA: 0x6d, // External Memory Control Register A + XMCRB: 0x6c, // External Memory Control Register B + OSCCAL: 0x6f, // Oscillator Calibration Value + XDIV: 0x5c, // XTAL Divide Control Register + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x68, // Store Program Memory Control Register + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x42, // On-Chip Debug Related Register in I/O Memory + } + + // Other Registers + MISC = struct { + }{} + + // External Interrupts + EXINT = struct { + EICRA __reg + EICRB __reg + EIMSK __reg + EIFR __reg + }{ + EICRA: 0x6a, // External Interrupt Control Register A + EICRB: 0x5a, // External Interrupt Control Register B + EIMSK: 0x59, // External Interrupt Mask Register + EIFR: 0x58, // External Interrupt Flag Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x3e, // EEPROM Read/Write Access Bytes + EEARH: 0x3e, // EEPROM Read/Write Access Bytes + EEDR: 0x3d, // EEPROM Data Register + EECR: 0x3c, // EEPROM Control Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + }{ + PORTA: 0x3b, // Port A Data Register + DDRA: 0x3a, // Port A Data Direction Register + PINA: 0x39, // Port A Input Pins + PORTB: 0x38, // Port B Data Register + DDRB: 0x37, // Port B Data Direction Register + PINB: 0x36, // Port B Input Pins + PORTC: 0x35, // Port C Data Register + DDRC: 0x34, // Port C Data Direction Register + PINC: 0x33, // Port C Input Pins + PORTD: 0x32, // Port D Data Register + DDRD: 0x31, // Port D Data Direction Register + PIND: 0x30, // Port D Input Pins + PORTE: 0x23, // Data Register, Port E + DDRE: 0x22, // Data Direction Register, Port E + PINE: 0x21, // Input Pins, Port E + PORTF: 0x62, // Data Register, Port F + DDRF: 0x61, // Data Direction Register, Port F + PINF: 0x20, // Input Pins, Port F + PORTG: 0x65, // Data Register, Port G + DDRG: 0x64, // Data Direction Register, Port G + PING: 0x63, // Input Pins, Port G + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR0 __reg + TCNT0 __reg + OCR0 __reg + ASSR __reg + }{ + TCCR0: 0x53, // Timer/Counter Control Register + TCNT0: 0x52, // Timer/Counter Register + OCR0: 0x51, // Output Compare Register + ASSR: 0x50, // Asynchronus Status Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + OCR1CL __reg + OCR1CH __reg + ICR1L __reg + ICR1H __reg + TCCR3A __reg + TCCR3B __reg + TCCR3C __reg + TCNT3L __reg + TCNT3H __reg + OCR3AL __reg + OCR3AH __reg + OCR3BL __reg + OCR3BH __reg + OCR3CL __reg + OCR3CH __reg + ICR3L __reg + ICR3H __reg + }{ + TCCR1A: 0x4f, // Timer/Counter1 Control Register A + TCCR1B: 0x4e, // Timer/Counter1 Control Register B + TCCR1C: 0x7a, // Timer/Counter1 Control Register C + TCNT1L: 0x4c, // Timer/Counter1 Bytes + TCNT1H: 0x4c, // Timer/Counter1 Bytes + OCR1AL: 0x4a, // Timer/Counter1 Output Compare Register Bytes + OCR1AH: 0x4a, // Timer/Counter1 Output Compare Register Bytes + OCR1BL: 0x48, // Timer/Counter1 Output Compare Register Bytes + OCR1BH: 0x48, // Timer/Counter1 Output Compare Register Bytes + OCR1CL: 0x78, // Timer/Counter1 Output Compare Register Bytes + OCR1CH: 0x78, // Timer/Counter1 Output Compare Register Bytes + ICR1L: 0x46, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x46, // Timer/Counter1 Input Capture Register Bytes + TCCR3A: 0x8b, // Timer/Counter3 Control Register A + TCCR3B: 0x8a, // Timer/Counter3 Control Register B + TCCR3C: 0x8c, // Timer/Counter3 Control Register C + TCNT3L: 0x88, // Timer/Counter3 Bytes + TCNT3H: 0x88, // Timer/Counter3 Bytes + OCR3AL: 0x86, // Timer/Counter3 Output Compare Register A Bytes + OCR3AH: 0x86, // Timer/Counter3 Output Compare Register A Bytes + OCR3BL: 0x84, // Timer/Counter3 Output Compare Register B Bytes + OCR3BH: 0x84, // Timer/Counter3 Output Compare Register B Bytes + OCR3CL: 0x82, // Timer/Counter3 Output compare Register C Bytes + OCR3CH: 0x82, // Timer/Counter3 Output compare Register C Bytes + ICR3L: 0x80, // Timer/Counter3 Input Capture Register Bytes + ICR3H: 0x80, // Timer/Counter3 Input Capture Register Bytes + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR2 __reg + TCNT2 __reg + OCR2 __reg + }{ + TCCR2: 0x45, // Timer/Counter Control Register + TCNT2: 0x44, // Timer/Counter Register + OCR2: 0x43, // Output Compare Register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x41, // Watchdog Timer Control Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_M103C = 0x2 // ATmega103 Compatibility Mode + EXTENDED_WDTON = 0x1 // Watchdog Timer always on + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + HIGH_CKOPT = 0x10 // CKOPT fuse (operation dependent of CKSEL fuses) + + // LOW + LOW_BODLEVEL = 0x80 // Brownout detector trigger level + LOW_BODEN = 0x40 // Brown-out detection enabled + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCSRB: The ADC Control and Status register B + ADCSRB_ADTS = 0x7 // ADC Auto Trigger Source bits +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0x40 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity + + // UCSR1A: USART Control and Status Register A + UCSR1A_RXC1 = 0x80 // USART Receive Complete + UCSR1A_TXC1 = 0x40 // USART Transmitt Complete + UCSR1A_UDRE1 = 0x20 // USART Data Register Empty + UCSR1A_FE1 = 0x10 // Framing Error + UCSR1A_DOR1 = 0x8 // Data overRun + UCSR1A_UPE1 = 0x4 // Parity Error + UCSR1A_U2X1 = 0x2 // Double the USART transmission speed + UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode + + // UCSR1B: USART Control and Status Register B + UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable + UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable + UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable + UCSR1B_RXEN1 = 0x10 // Receiver Enable + UCSR1B_TXEN1 = 0x8 // Transmitter Enable + UCSR1B_UCSZ12 = 0x4 // Character Size + UCSR1B_RXB81 = 0x2 // Receive Data Bit 8 + UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8 + + // UCSR1C: USART Control and Status Register C + UCSR1C_UMSEL1 = 0x40 // USART Mode Select + UCSR1C_UPM1 = 0x30 // Parity Mode Bits + UCSR1C_USBS1 = 0x8 // Stop Bit Select + UCSR1C_UCSZ1 = 0x6 // Character Size + UCSR1C_UCPOL1 = 0x1 // Clock Polarity +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // MCUCR: MCU Control Register + MCUCR_SRE = 0x80 // External SRAM Enable + MCUCR_SRW10 = 0x40 // External SRAM Wait State Select + MCUCR_SE = 0x20 // Sleep Enable + MCUCR_SM = 0x18 // Sleep Mode Select + MCUCR_SM2 = 0x4 // Sleep Mode Select + MCUCR_IVSEL = 0x2 // Interrupt Vector Select + MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable + + // XMCRA: External Memory Control Register A + XMCRA_SRL = 0x70 // Wait state page limit + XMCRA_SRW0 = 0xc // Wait state select bit lower page + XMCRA_SRW11 = 0x2 // Wait state select bit upper page + + // XMCRB: External Memory Control Register B + XMCRB_XMBK = 0x80 // External Memory Bus Keeper Enable + XMCRB_XMM = 0x7 // External Memory High Mask + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // XDIV: XTAL Divide Control Register + XDIV_XDIVEN = 0x80 // XTAL Divide Enable + XDIV_XDIV = 0x7f // XTAl Divide Select Bits +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for JTAG: JTAG Interface +const ( + // OCDR: On-Chip Debug Related Register in I/O Memory + OCDR_OCDR = 0xff // On-Chip Debug Register Bits +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EICRB: External Interrupt Control Register B + EICRB_ISC7 = 0xc0 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC6 = 0x30 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC5 = 0xc // External Interrupt 7-4 Sense Control Bit + EICRB_ISC4 = 0x3 // External Interrupt 7-4 Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xff // External Interrupt Request 7 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xff // External Interrupt Flags +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR0: Timer/Counter Control Register + TCCR0_FOC0 = 0x80 // Force Output Compare + TCCR0_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0_COM0 = 0x30 // Compare Match Output Modes + TCCR0_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0_CS0 = 0x7 // Clock Selects + + // ASSR: Asynchronus Status Register + ASSR_AS0 = 0x8 // Asynchronus Timer/Counter 0 + ASSR_TCN0UB = 0x4 // Timer/Counter0 Update Busy + ASSR_OCR0UB = 0x2 // Output Compare register 0 Busy + ASSR_TCR0UB = 0x1 // Timer/Counter Control Register 0 Update Busy +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_COM1C = 0xc // Compare Output Mode 1C, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode Bits + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Clock Select1 bits + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare for channel A + TCCR1C_FOC1B = 0x40 // Force Output Compare for channel B + TCCR1C_FOC1C = 0x20 // Force Output Compare for channel C + + // TCCR3A: Timer/Counter3 Control Register A + TCCR3A_COM3A = 0xc0 // Compare Output Mode 3A, bits + TCCR3A_COM3B = 0x30 // Compare Output Mode 3B, bits + TCCR3A_COM3C = 0xc // Compare Output Mode 3C, bits + TCCR3A_WGM3 = 0x3 // Waveform Generation Mode Bits + + // TCCR3B: Timer/Counter3 Control Register B + TCCR3B_ICNC3 = 0x80 // Input Capture 3 Noise Canceler + TCCR3B_ICES3 = 0x40 // Input Capture 3 Edge Select + TCCR3B_WGM3 = 0x18 // Waveform Generation Mode + TCCR3B_CS3 = 0x7 // Clock Select3 bits + + // TCCR3C: Timer/Counter3 Control Register C + TCCR3C_FOC3A = 0x80 // Force Output Compare for channel A + TCCR3C_FOC3B = 0x40 // Force Output Compare for channel B + TCCR3C_FOC3C = 0x20 // Force Output Compare for channel C +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR2: Timer/Counter Control Register + TCCR2_FOC2 = 0x80 // Force Output Compare + TCCR2_WGM20 = 0x40 // Wafeform Generation Mode + TCCR2_COM2 = 0x30 // Compare Match Output Mode + TCCR2_WGM21 = 0x8 // Waveform Generation Mode + TCCR2_CS2 = 0x7 // Clock Select +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) diff --git a/src/device/avr/atmega64.ld b/src/device/avr/atmega64.ld new file mode 100644 index 00000000..f123b99b --- /dev/null +++ b/src/device/avr/atmega64.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega64.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_size = 0x1000; +__num_isrs = 35; diff --git a/src/device/avr/atmega640.go b/src/device/avr/atmega640.go new file mode 100644 index 00000000..dc065410 --- /dev/null +++ b/src/device/avr/atmega640.go @@ -0,0 +1,1079 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega640.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega640 + +// Device information for the ATmega640. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega640" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_INT3 = 4 // External Interrupt Request 3 + IRQ_INT4 = 5 // External Interrupt Request 4 + IRQ_INT5 = 6 // External Interrupt Request 5 + IRQ_INT6 = 7 // External Interrupt Request 6 + IRQ_INT7 = 8 // External Interrupt Request 7 + IRQ_PCINT0 = 9 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 10 // Pin Change Interrupt Request 1 + IRQ_PCINT2 = 11 // Pin Change Interrupt Request 2 + IRQ_WDT = 12 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 13 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 14 // Timer/Counter2 Compare Match B + IRQ_TIMER2_OVF = 15 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 16 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 17 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 18 // Timer/Counter1 Compare Match B + IRQ_TIMER1_COMPC = 19 // Timer/Counter1 Compare Match C + IRQ_TIMER1_OVF = 20 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 21 // Timer/Counter0 Compare Match A + IRQ_TIMER0_COMPB = 22 // Timer/Counter0 Compare Match B + IRQ_TIMER0_OVF = 23 // Timer/Counter0 Overflow + IRQ_SPI_STC = 24 // SPI Serial Transfer Complete + IRQ_USART0_RX = 25 // USART0, Rx Complete + IRQ_USART0_UDRE = 26 // USART0 Data register Empty + IRQ_USART0_TX = 27 // USART0, Tx Complete + IRQ_ANALOG_COMP = 28 // Analog Comparator + IRQ_ADC = 29 // ADC Conversion Complete + IRQ_EE_READY = 30 // EEPROM Ready + IRQ_TIMER3_CAPT = 31 // Timer/Counter3 Capture Event + IRQ_TIMER3_COMPA = 32 // Timer/Counter3 Compare Match A + IRQ_TIMER3_COMPB = 33 // Timer/Counter3 Compare Match B + IRQ_TIMER3_COMPC = 34 // Timer/Counter3 Compare Match C + IRQ_TIMER3_OVF = 35 // Timer/Counter3 Overflow + IRQ_USART1_RX = 36 // USART1, Rx Complete + IRQ_USART1_UDRE = 37 // USART1 Data register Empty + IRQ_USART1_TX = 38 // USART1, Tx Complete + IRQ_TWI = 39 // 2-wire Serial Interface + IRQ_SPM_READY = 40 // Store Program Memory Read + IRQ_TIMER4_CAPT = 41 // Timer/Counter4 Capture Event + IRQ_TIMER4_COMPA = 42 // Timer/Counter4 Compare Match A + IRQ_TIMER4_COMPB = 43 // Timer/Counter4 Compare Match B + IRQ_TIMER4_COMPC = 44 // Timer/Counter4 Compare Match C + IRQ_TIMER4_OVF = 45 // Timer/Counter4 Overflow + IRQ_TIMER5_CAPT = 46 // Timer/Counter5 Capture Event + IRQ_TIMER5_COMPA = 47 // Timer/Counter5 Compare Match A + IRQ_TIMER5_COMPB = 48 // Timer/Counter5 Compare Match B + IRQ_TIMER5_COMPC = 49 // Timer/Counter5 Compare Match C + IRQ_TIMER5_OVF = 50 // Timer/Counter5 Overflow + IRQ_USART2_RX = 51 // USART2, Rx Complete + IRQ_USART2_UDRE = 52 // USART2 Data register Empty + IRQ_USART2_TX = 53 // USART2, Tx Complete + IRQ_USART3_RX = 54 // USART3, Rx Complete + IRQ_USART3_UDRE = 55 // USART3 Data register Empty + IRQ_USART3_TX = 56 // USART3, Tx Complete + IRQ_max = 56 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + UDR1 __reg + UCSR1A __reg + UCSR1B __reg + UCSR1C __reg + UBRR1L __reg + UBRR1H __reg + UDR2 __reg + UCSR2A __reg + UCSR2B __reg + UCSR2C __reg + UBRR2L __reg + UBRR2H __reg + UDR3 __reg + UCSR3A __reg + UCSR3B __reg + UCSR3C __reg + UBRR3L __reg + UBRR3H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + UDR1: 0xce, // USART I/O Data Register + UCSR1A: 0xc8, // USART Control and Status Register A + UCSR1B: 0xc9, // USART Control and Status Register B + UCSR1C: 0xca, // USART Control and Status Register C + UBRR1L: 0xcc, // USART Baud Rate Register Bytes + UBRR1H: 0xcc, // USART Baud Rate Register Bytes + UDR2: 0xd6, // USART I/O Data Register + UCSR2A: 0xd0, // USART Control and Status Register A + UCSR2B: 0xd1, // USART Control and Status Register B + UCSR2C: 0xd2, // USART Control and Status Register C + UBRR2L: 0xd4, // USART Baud Rate Register Bytes + UBRR2H: 0xd4, // USART Baud Rate Register Bytes + UDR3: 0x136, // USART I/O Data Register + UCSR3A: 0x130, // USART Control and Status Register A + UCSR3B: 0x131, // USART Control and Status Register B + UCSR3C: 0x132, // USART Control and Status Register C + UBRR3L: 0x134, // USART Baud Rate Register Bytes + UBRR3H: 0x134, // USART Baud Rate Register Bytes + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + PORTH __reg + DDRH __reg + PINH __reg + PORTJ __reg + DDRJ __reg + PINJ __reg + PORTK __reg + DDRK __reg + PINK __reg + PORTL __reg + DDRL __reg + PINL __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + PORTG: 0x34, // Data Register, Port G + DDRG: 0x33, // Data Direction Register, Port G + PING: 0x32, // Input Pins, Port G + PORTH: 0x102, // PORT H Data Register + DDRH: 0x101, // PORT H Data Direction Register + PINH: 0x100, // PORT H Input Pins + PORTJ: 0x105, // PORT J Data Register + DDRJ: 0x104, // PORT J Data Direction Register + PINJ: 0x103, // PORT J Input Pins + PORTK: 0x108, // PORT K Data Register + DDRK: 0x107, // PORT K Data Direction Register + PINK: 0x106, // PORT K Input Pins + PORTL: 0x10b, // PORT L Data Register + DDRL: 0x10a, // PORT L Data Direction Register + PINL: 0x109, // PORT L Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Low Bytes + EEARH: 0x41, // EEPROM Address Register Low Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR5A __reg + TCCR5B __reg + TCCR5C __reg + TCNT5L __reg + TCNT5H __reg + OCR5AL __reg + OCR5AH __reg + OCR5BL __reg + OCR5BH __reg + OCR5CL __reg + OCR5CH __reg + ICR5L __reg + ICR5H __reg + TIMSK5 __reg + TIFR5 __reg + TCCR4A __reg + TCCR4B __reg + TCCR4C __reg + TCNT4L __reg + TCNT4H __reg + OCR4AL __reg + OCR4AH __reg + OCR4BL __reg + OCR4BH __reg + OCR4CL __reg + OCR4CH __reg + ICR4L __reg + ICR4H __reg + TIMSK4 __reg + TIFR4 __reg + TCCR3A __reg + TCCR3B __reg + TCCR3C __reg + TCNT3L __reg + TCNT3H __reg + OCR3AL __reg + OCR3AH __reg + OCR3BL __reg + OCR3BH __reg + OCR3CL __reg + OCR3CH __reg + ICR3L __reg + ICR3H __reg + TIMSK3 __reg + TIFR3 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + OCR1CL __reg + OCR1CH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR5A: 0x120, // Timer/Counter5 Control Register A + TCCR5B: 0x121, // Timer/Counter5 Control Register B + TCCR5C: 0x122, // Timer/Counter 5 Control Register C + TCNT5L: 0x124, // Timer/Counter5 Bytes + TCNT5H: 0x124, // Timer/Counter5 Bytes + OCR5AL: 0x128, // Timer/Counter5 Output Compare Register A Bytes + OCR5AH: 0x128, // Timer/Counter5 Output Compare Register A Bytes + OCR5BL: 0x12a, // Timer/Counter5 Output Compare Register B Bytes + OCR5BH: 0x12a, // Timer/Counter5 Output Compare Register B Bytes + OCR5CL: 0x12c, // Timer/Counter5 Output Compare Register B Bytes + OCR5CH: 0x12c, // Timer/Counter5 Output Compare Register B Bytes + ICR5L: 0x126, // Timer/Counter5 Input Capture Register Bytes + ICR5H: 0x126, // Timer/Counter5 Input Capture Register Bytes + TIMSK5: 0x73, // Timer/Counter5 Interrupt Mask Register + TIFR5: 0x3a, // Timer/Counter5 Interrupt Flag register + TCCR4A: 0xa0, // Timer/Counter4 Control Register A + TCCR4B: 0xa1, // Timer/Counter4 Control Register B + TCCR4C: 0xa2, // Timer/Counter 4 Control Register C + TCNT4L: 0xa4, // Timer/Counter4 Bytes + TCNT4H: 0xa4, // Timer/Counter4 Bytes + OCR4AL: 0xa8, // Timer/Counter4 Output Compare Register A Bytes + OCR4AH: 0xa8, // Timer/Counter4 Output Compare Register A Bytes + OCR4BL: 0xaa, // Timer/Counter4 Output Compare Register B Bytes + OCR4BH: 0xaa, // Timer/Counter4 Output Compare Register B Bytes + OCR4CL: 0xac, // Timer/Counter4 Output Compare Register B Bytes + OCR4CH: 0xac, // Timer/Counter4 Output Compare Register B Bytes + ICR4L: 0xa6, // Timer/Counter4 Input Capture Register Bytes + ICR4H: 0xa6, // Timer/Counter4 Input Capture Register Bytes + TIMSK4: 0x72, // Timer/Counter4 Interrupt Mask Register + TIFR4: 0x39, // Timer/Counter4 Interrupt Flag register + TCCR3A: 0x90, // Timer/Counter3 Control Register A + TCCR3B: 0x91, // Timer/Counter3 Control Register B + TCCR3C: 0x92, // Timer/Counter 3 Control Register C + TCNT3L: 0x94, // Timer/Counter3 Bytes + TCNT3H: 0x94, // Timer/Counter3 Bytes + OCR3AL: 0x98, // Timer/Counter3 Output Compare Register A Bytes + OCR3AH: 0x98, // Timer/Counter3 Output Compare Register A Bytes + OCR3BL: 0x9a, // Timer/Counter3 Output Compare Register B Bytes + OCR3BH: 0x9a, // Timer/Counter3 Output Compare Register B Bytes + OCR3CL: 0x9c, // Timer/Counter3 Output Compare Register B Bytes + OCR3CH: 0x9c, // Timer/Counter3 Output Compare Register B Bytes + ICR3L: 0x96, // Timer/Counter3 Input Capture Register Bytes + ICR3H: 0x96, // Timer/Counter3 Input Capture Register Bytes + TIMSK3: 0x71, // Timer/Counter3 Interrupt Mask Register + TIFR3: 0x38, // Timer/Counter3 Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1CL: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + OCR1CH: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EICRB __reg + EIMSK __reg + EIFR __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + PCICR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EICRB: 0x6a, // External Interrupt Control Register B + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + XMCRA __reg + XMCRB __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + EIND __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PRR1 __reg + PRR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + XMCRA: 0x74, // External Memory Control Register A + XMCRB: 0x75, // External Memory Control Register B + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, + SMCR: 0x53, // Sleep Mode Control Register + EIND: 0x5c, // Extended Indirect Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PRR1: 0x65, // Power Reduction Register1 + PRR0: 0x64, // Power Reduction Register0 + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + DIDR2 __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // The ADC Control and Status register A + DIDR2: 0x7d, // Digital Input Disable Register + DIDR0: 0x7e, // Digital Input Disable Register + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled (default address=$0000) + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0xc0 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity + + // UCSR1A: USART Control and Status Register A + UCSR1A_RXC1 = 0x80 // USART Receive Complete + UCSR1A_TXC1 = 0x40 // USART Transmitt Complete + UCSR1A_UDRE1 = 0x20 // USART Data Register Empty + UCSR1A_FE1 = 0x10 // Framing Error + UCSR1A_DOR1 = 0x8 // Data overRun + UCSR1A_UPE1 = 0x4 // Parity Error + UCSR1A_U2X1 = 0x2 // Double the USART transmission speed + UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode + + // UCSR1B: USART Control and Status Register B + UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable + UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable + UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable + UCSR1B_RXEN1 = 0x10 // Receiver Enable + UCSR1B_TXEN1 = 0x8 // Transmitter Enable + UCSR1B_UCSZ12 = 0x4 // Character Size + UCSR1B_RXB81 = 0x2 // Receive Data Bit 8 + UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8 + + // UCSR1C: USART Control and Status Register C + UCSR1C_UMSEL1 = 0xc0 // USART Mode Select + UCSR1C_UPM1 = 0x30 // Parity Mode Bits + UCSR1C_USBS1 = 0x8 // Stop Bit Select + UCSR1C_UCSZ1 = 0x6 // Character Size + UCSR1C_UCPOL1 = 0x1 // Clock Polarity + + // UCSR2A: USART Control and Status Register A + UCSR2A_RXC2 = 0x80 // USART Receive Complete + UCSR2A_TXC2 = 0x40 // USART Transmitt Complete + UCSR2A_UDRE2 = 0x20 // USART Data Register Empty + UCSR2A_FE2 = 0x10 // Framing Error + UCSR2A_DOR2 = 0x8 // Data overRun + UCSR2A_UPE2 = 0x4 // Parity Error + UCSR2A_U2X2 = 0x2 // Double the USART transmission speed + UCSR2A_MPCM2 = 0x1 // Multi-processor Communication Mode + + // UCSR2B: USART Control and Status Register B + UCSR2B_RXCIE2 = 0x80 // RX Complete Interrupt Enable + UCSR2B_TXCIE2 = 0x40 // TX Complete Interrupt Enable + UCSR2B_UDRIE2 = 0x20 // USART Data register Empty Interrupt Enable + UCSR2B_RXEN2 = 0x10 // Receiver Enable + UCSR2B_TXEN2 = 0x8 // Transmitter Enable + UCSR2B_UCSZ22 = 0x4 // Character Size + UCSR2B_RXB82 = 0x2 // Receive Data Bit 8 + UCSR2B_TXB82 = 0x1 // Transmit Data Bit 8 + + // UCSR2C: USART Control and Status Register C + UCSR2C_UMSEL2 = 0xc0 // USART Mode Select + UCSR2C_UPM2 = 0x30 // Parity Mode Bits + UCSR2C_USBS2 = 0x8 // Stop Bit Select + UCSR2C_UCSZ2 = 0x6 // Character Size + UCSR2C_UCPOL2 = 0x1 // Clock Polarity + + // UCSR3A: USART Control and Status Register A + UCSR3A_RXC3 = 0x80 // USART Receive Complete + UCSR3A_TXC3 = 0x40 // USART Transmitt Complete + UCSR3A_UDRE3 = 0x20 // USART Data Register Empty + UCSR3A_FE3 = 0x10 // Framing Error + UCSR3A_DOR3 = 0x8 // Data overRun + UCSR3A_UPE3 = 0x4 // Parity Error + UCSR3A_U2X3 = 0x2 // Double the USART transmission speed + UCSR3A_MPCM3 = 0x1 // Multi-processor Communication Mode + + // UCSR3B: USART Control and Status Register B + UCSR3B_RXCIE3 = 0x80 // RX Complete Interrupt Enable + UCSR3B_TXCIE3 = 0x40 // TX Complete Interrupt Enable + UCSR3B_UDRIE3 = 0x20 // USART Data register Empty Interrupt Enable + UCSR3B_RXEN3 = 0x10 // Receiver Enable + UCSR3B_TXEN3 = 0x8 // Transmitter Enable + UCSR3B_UCSZ32 = 0x4 // Character Size + UCSR3B_RXB83 = 0x2 // Receive Data Bit 8 + UCSR3B_TXB83 = 0x1 // Transmit Data Bit 8 + + // UCSR3C: USART Control and Status Register C + UCSR3C_UMSEL3 = 0xc0 // USART Mode Select + UCSR3C_UPM3 = 0x30 // Parity Mode Bits + UCSR3C_USBS3 = 0x8 // Stop Bit Select + UCSR3C_UCSZ3 = 0x6 // Character Size + UCSR3C_UCPOL3 = 0x1 // Clock Polarity +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2B = 0x4 // Output Compare Flag 2B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Output Mode bits + TCCR2A_COM2B = 0x30 // Compare Output Mode bits + TCCR2A_WGM2 = 0x3 // Waveform Genration Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy + ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR5A: Timer/Counter5 Control Register A + TCCR5A_COM5A = 0xc0 // Compare Output Mode 1A, bits + TCCR5A_COM5B = 0x30 // Compare Output Mode 5B, bits + TCCR5A_COM5C = 0xc // Compare Output Mode 5C, bits + TCCR5A_WGM5 = 0x3 // Waveform Generation Mode + + // TCCR5B: Timer/Counter5 Control Register B + TCCR5B_ICNC5 = 0x80 // Input Capture 5 Noise Canceler + TCCR5B_ICES5 = 0x40 // Input Capture 5 Edge Select + TCCR5B_WGM5 = 0x18 // Waveform Generation Mode + TCCR5B_CS5 = 0x7 // Prescaler source of Timer/Counter 5 + + // TCCR5C: Timer/Counter 5 Control Register C + TCCR5C_FOC5A = 0x80 // Force Output Compare 5A + TCCR5C_FOC5B = 0x40 // Force Output Compare 5B + TCCR5C_FOC5C = 0x20 // Force Output Compare 5C + + // TIMSK5: Timer/Counter5 Interrupt Mask Register + TIMSK5_ICIE5 = 0x20 // Timer/Counter5 Input Capture Interrupt Enable + TIMSK5_OCIE5C = 0x8 // Timer/Counter5 Output Compare C Match Interrupt Enable + TIMSK5_OCIE5B = 0x4 // Timer/Counter5 Output Compare B Match Interrupt Enable + TIMSK5_OCIE5A = 0x2 // Timer/Counter5 Output Compare A Match Interrupt Enable + TIMSK5_TOIE5 = 0x1 // Timer/Counter5 Overflow Interrupt Enable + + // TIFR5: Timer/Counter5 Interrupt Flag register + TIFR5_ICF5 = 0x20 // Input Capture Flag 5 + TIFR5_OCF5C = 0x8 // Output Compare Flag 5C + TIFR5_OCF5B = 0x4 // Output Compare Flag 5B + TIFR5_OCF5A = 0x2 // Output Compare Flag 5A + TIFR5_TOV5 = 0x1 // Timer/Counter5 Overflow Flag + + // TCCR4A: Timer/Counter4 Control Register A + TCCR4A_COM4A = 0xc0 // Compare Output Mode 1A, bits + TCCR4A_COM4B = 0x30 // Compare Output Mode 4B, bits + TCCR4A_COM4C = 0xc // Compare Output Mode 4C, bits + TCCR4A_WGM4 = 0x3 // Waveform Generation Mode + + // TCCR4B: Timer/Counter4 Control Register B + TCCR4B_ICNC4 = 0x80 // Input Capture 4 Noise Canceler + TCCR4B_ICES4 = 0x40 // Input Capture 4 Edge Select + TCCR4B_WGM4 = 0x18 // Waveform Generation Mode + TCCR4B_CS4 = 0x7 // Prescaler source of Timer/Counter 4 + + // TCCR4C: Timer/Counter 4 Control Register C + TCCR4C_FOC4A = 0x80 // Force Output Compare 4A + TCCR4C_FOC4B = 0x40 // Force Output Compare 4B + TCCR4C_FOC4C = 0x20 // Force Output Compare 4C + + // TIMSK4: Timer/Counter4 Interrupt Mask Register + TIMSK4_ICIE4 = 0x20 // Timer/Counter4 Input Capture Interrupt Enable + TIMSK4_OCIE4C = 0x8 // Timer/Counter4 Output Compare C Match Interrupt Enable + TIMSK4_OCIE4B = 0x4 // Timer/Counter4 Output Compare B Match Interrupt Enable + TIMSK4_OCIE4A = 0x2 // Timer/Counter4 Output Compare A Match Interrupt Enable + TIMSK4_TOIE4 = 0x1 // Timer/Counter4 Overflow Interrupt Enable + + // TIFR4: Timer/Counter4 Interrupt Flag register + TIFR4_ICF4 = 0x20 // Input Capture Flag 4 + TIFR4_OCF4C = 0x8 // Output Compare Flag 4C + TIFR4_OCF4B = 0x4 // Output Compare Flag 4B + TIFR4_OCF4A = 0x2 // Output Compare Flag 4A + TIFR4_TOV4 = 0x1 // Timer/Counter4 Overflow Flag + + // TCCR3A: Timer/Counter3 Control Register A + TCCR3A_COM3A = 0xc0 // Compare Output Mode 1A, bits + TCCR3A_COM3B = 0x30 // Compare Output Mode 3B, bits + TCCR3A_COM3C = 0xc // Compare Output Mode 3C, bits + TCCR3A_WGM3 = 0x3 // Waveform Generation Mode + + // TCCR3B: Timer/Counter3 Control Register B + TCCR3B_ICNC3 = 0x80 // Input Capture 3 Noise Canceler + TCCR3B_ICES3 = 0x40 // Input Capture 3 Edge Select + TCCR3B_WGM3 = 0x18 // Waveform Generation Mode + TCCR3B_CS3 = 0x7 // Prescaler source of Timer/Counter 3 + + // TCCR3C: Timer/Counter 3 Control Register C + TCCR3C_FOC3A = 0x80 // Force Output Compare 3A + TCCR3C_FOC3B = 0x40 // Force Output Compare 3B + TCCR3C_FOC3C = 0x20 // Force Output Compare 3C + + // TIMSK3: Timer/Counter3 Interrupt Mask Register + TIMSK3_ICIE3 = 0x20 // Timer/Counter3 Input Capture Interrupt Enable + TIMSK3_OCIE3C = 0x8 // Timer/Counter3 Output Compare C Match Interrupt Enable + TIMSK3_OCIE3B = 0x4 // Timer/Counter3 Output Compare B Match Interrupt Enable + TIMSK3_OCIE3A = 0x2 // Timer/Counter3 Output Compare A Match Interrupt Enable + TIMSK3_TOIE3 = 0x1 // Timer/Counter3 Overflow Interrupt Enable + + // TIFR3: Timer/Counter3 Interrupt Flag register + TIFR3_ICF3 = 0x20 // Input Capture Flag 3 + TIFR3_OCF3C = 0x8 // Output Compare Flag 3C + TIFR3_OCF3B = 0x4 // Output Compare Flag 3B + TIFR3_OCF3A = 0x2 // Output Compare Flag 3A + TIFR3_TOV3 = 0x1 // Timer/Counter3 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_COM1C = 0xc // Compare Output Mode 1C, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + TCCR1C_FOC1C = 0x20 // Force Output Compare 1C + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1C = 0x8 // Timer/Counter1 Output Compare C Match Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1C = 0x8 // Output Compare Flag 1C + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EICRB: External Interrupt Control Register B + EICRB_ISC7 = 0xc0 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC6 = 0x30 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC5 = 0xc // External Interrupt 7-4 Sense Control Bit + EICRB_ISC4 = 0x3 // External Interrupt 7-4 Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xff // External Interrupt Request 7 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xff // External Interrupt Flags + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0x7 // Pin Change Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0x7 // Pin Change Interrupt Enables +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // XMCRA: External Memory Control Register A + XMCRA_SRE = 0x80 // External SRAM Enable + XMCRA_SRL = 0x70 // Wait state page limit + XMCRA_SRW1 = 0xc // Wait state select bit upper page + XMCRA_SRW0 = 0x3 // Wait state select bit lower page + + // XMCRB: External Memory Control Register B + XMCRB_XMBK = 0x80 // External Memory Bus Keeper Enable + XMCRB_XMM = 0x7 // External Memory High Mask + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 + + // PRR1: Power Reduction Register1 + PRR1_PRTIM5 = 0x20 // Power Reduction Timer/Counter5 + PRR1_PRTIM4 = 0x10 // Power Reduction Timer/Counter4 + PRR1_PRTIM3 = 0x8 // Power Reduction Timer/Counter3 + PRR1_PRUSART3 = 0x4 // Power Reduction USART3 + PRR1_PRUSART2 = 0x2 // Power Reduction USART2 + PRR1_PRUSART1 = 0x1 // Power Reduction USART1 + + // PRR0: Power Reduction Register0 + PRR0_PRTWI = 0x80 // Power Reduction TWI + PRR0_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR0_PRUSART0 = 0x2 // Power Reduction USART0 + PRR0_PRADC = 0x1 // Power Reduction ADC +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR2: Digital Input Disable Register + DIDR2_ADC15D = 0x80 + DIDR2_ADC14D = 0x40 + DIDR2_ADC13D = 0x20 + DIDR2_ADC12D = 0x10 + DIDR2_ADC11D = 0x8 + DIDR2_ADC10D = 0x4 + DIDR2_ADC9D = 0x2 + DIDR2_ADC8D = 0x1 + + // DIDR0: Digital Input Disable Register + DIDR0_ADC7D = 0x80 + DIDR0_ADC6D = 0x40 + DIDR0_ADC5D = 0x20 + DIDR0_ADC4D = 0x10 + DIDR0_ADC3D = 0x8 + DIDR0_ADC2D = 0x4 + DIDR0_ADC1D = 0x2 + DIDR0_ADC0D = 0x1 +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) diff --git a/src/device/avr/atmega640.ld b/src/device/avr/atmega640.ld new file mode 100644 index 00000000..8c612fc0 --- /dev/null +++ b/src/device/avr/atmega640.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega640.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_size = 0x2000; +__num_isrs = 57; diff --git a/src/device/avr/atmega644.go b/src/device/avr/atmega644.go new file mode 100644 index 00000000..e29b0945 --- /dev/null +++ b/src/device/avr/atmega644.go @@ -0,0 +1,667 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega644.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega644 + +// Device information for the ATmega644. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega644" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_PCINT0 = 4 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 5 // Pin Change Interrupt Request 1 + IRQ_PCINT2 = 6 // Pin Change Interrupt Request 2 + IRQ_PCINT3 = 7 // Pin Change Interrupt Request 3 + IRQ_WDT = 8 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 9 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 10 // Timer/Counter2 Compare Match B + IRQ_TIMER2_OVF = 11 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 12 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 13 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 14 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 15 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 16 // Timer/Counter0 Compare Match A + IRQ_TIMER0_COMPB = 17 // Timer/Counter0 Compare Match B + IRQ_TIMER0_OVF = 18 // Timer/Counter0 Overflow + IRQ_SPI_STC = 19 // SPI Serial Transfer Complete + IRQ_USART0_RX = 20 // USART0, Rx Complete + IRQ_USART0_UDRE = 21 // USART0 Data register Empty + IRQ_USART0_TX = 22 // USART0, Tx Complete + IRQ_ANALOG_COMP = 23 // Analog Comparator + IRQ_ADC = 24 // ADC Conversion Complete + IRQ_EE_READY = 25 // EEPROM Ready + IRQ_TWI = 26 // 2-wire Serial Interface + IRQ_SPM_READY = 27 // Store Program Memory Read + IRQ_max = 27 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK3 __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + PCICR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK3: 0x73, // Pin Change Mask Register 3 + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // The ADC Control and Status register A + DIDR0: 0x7e, // Digital Input Disable Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Low Bytes + EEARH: 0x41, // EEPROM Address Register Low Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // Serial Peripheral Interface + SPI = struct { + SPDR __reg + SPSR __reg + SPCR __reg + }{ + SPDR: 0x4e, // SPI Data Register + SPSR: 0x4d, // SPI Status Register + SPCR: 0x4c, // SPI Control Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PRR __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PRR: 0x64, // Power Reduction Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTB1 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0xc0 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2B = 0x4 // Output Compare Flag 2B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Output Mode bits + TCCR2A_COM2B = 0x30 // Compare Output Mode bits + TCCR2A_WGM2 = 0x3 // Waveform Genration Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy + ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0x7 // External Interrupt Request 2 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0x7 // External Interrupt Flags + + // PCMSK3: Pin Change Mask Register 3 + PCMSK3_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0xf // Pin Change Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0xf // Pin Change Interrupt Enables +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register + DIDR0_ADC7D = 0x80 + DIDR0_ADC6D = 0x40 + DIDR0_ADC5D = 0x20 + DIDR0_ADC4D = 0x10 + DIDR0_ADC3D = 0x8 + DIDR0_ADC2D = 0x4 + DIDR0_ADC1D = 0x2 + DIDR0_ADC0D = 0x1 +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Timer/Counter1 Input Capture Flag + TIFR1_OCF1B = 0x4 // Timer/Counter1 Output Compare B Match Flag + TIFR1_OCF1A = 0x2 // Timer/Counter1 Output Compare A Match Flag + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Pulse Width Modulator Select Bits + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode Bits + TCCR1B_CS1 = 0x7 // Clock Select1 bits + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare for Channel A + TCCR1C_FOC1B = 0x40 // Force Output Compare for Channel B +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 + + // PRR: Power Reduction Register + PRR_PRTWI = 0x80 // Power Reduction TWI + PRR_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC +) diff --git a/src/device/avr/atmega644.ld b/src/device/avr/atmega644.ld new file mode 100644 index 00000000..89279f87 --- /dev/null +++ b/src/device/avr/atmega644.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega644.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_size = 0x1000; +__num_isrs = 28; diff --git a/src/device/avr/atmega644a.go b/src/device/avr/atmega644a.go new file mode 100644 index 00000000..83803936 --- /dev/null +++ b/src/device/avr/atmega644a.go @@ -0,0 +1,710 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega644A.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega644a + +// Device information for the ATmega644A. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega644A" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_PCINT0 = 4 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 5 // Pin Change Interrupt Request 1 + IRQ_PCINT2 = 6 // Pin Change Interrupt Request 2 + IRQ_PCINT3 = 7 // Pin Change Interrupt Request 3 + IRQ_WDT = 8 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 9 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 10 // Timer/Counter2 Compare Match B + IRQ_TIMER2_OVF = 11 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 12 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 13 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 14 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 15 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 16 // Timer/Counter0 Compare Match A + IRQ_TIMER0_COMPB = 17 // Timer/Counter0 Compare Match B + IRQ_TIMER0_OVF = 18 // Timer/Counter0 Overflow + IRQ_SPI_STC = 19 // SPI Serial Transfer Complete + IRQ_USART0_RX = 20 // USART0, Rx Complete + IRQ_USART0_UDRE = 21 // USART0 Data register Empty + IRQ_USART0_TX = 22 // USART0, Tx Complete + IRQ_ANALOG_COMP = 23 // Analog Comparator + IRQ_ADC = 24 // ADC Conversion Complete + IRQ_EE_READY = 25 // EEPROM Ready + IRQ_TWI = 26 // 2-wire Serial Interface + IRQ_SPM_READY = 27 // Store Program Memory Read + IRQ_USART1_RX = 28 // USART1 RX complete + IRQ_USART1_UDRE = 29 // USART1 Data Register Empty + IRQ_USART1_TX = 30 // USART1 TX complete + IRQ_max = 30 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + UDR1 __reg + UCSR1A __reg + UCSR1B __reg + UCSR1C __reg + UBRR1L __reg + UBRR1H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + UDR1: 0xce, // USART I/O Data Register + UCSR1A: 0xc8, // USART Control and Status Register A + UCSR1B: 0xc9, // USART Control and Status Register B + UCSR1C: 0xca, // USART Control and Status Register C + UBRR1L: 0xcc, // USART Baud Rate Register Bytes + UBRR1H: 0xcc, // USART Baud Rate Register Bytes + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK3 __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + PCICR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK3: 0x73, // Pin Change Mask Register 3 + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // The ADC Control and Status register A + DIDR0: 0x7e, // Digital Input Disable Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Low Bytes + EEARH: 0x41, // EEPROM Address Register Low Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // Serial Peripheral Interface + SPI = struct { + SPDR __reg + SPSR __reg + SPCR __reg + }{ + SPDR: 0x4e, // SPI Data Register + SPSR: 0x4d, // SPI Status Register + SPCR: 0x4c, // SPI Control Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PRR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PRR0: 0x64, // Power Reduction Register0 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTB1 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0xc0 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity + + // UCSR1A: USART Control and Status Register A + UCSR1A_RXC1 = 0x80 // USART Receive Complete + UCSR1A_TXC1 = 0x40 // USART Transmitt Complete + UCSR1A_UDRE1 = 0x20 // USART Data Register Empty + UCSR1A_FE1 = 0x10 // Framing Error + UCSR1A_DOR1 = 0x8 // Data overRun + UCSR1A_UPE1 = 0x4 // Parity Error + UCSR1A_U2X1 = 0x2 // Double the USART transmission speed + UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode + + // UCSR1B: USART Control and Status Register B + UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable + UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable + UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable + UCSR1B_RXEN1 = 0x10 // Receiver Enable + UCSR1B_TXEN1 = 0x8 // Transmitter Enable + UCSR1B_UCSZ12 = 0x4 // Character Size + UCSR1B_RXB81 = 0x2 // Receive Data Bit 8 + UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8 + + // UCSR1C: USART Control and Status Register C + UCSR1C_UMSEL1 = 0xc0 // USART Mode Select + UCSR1C_UPM1 = 0x30 // Parity Mode Bits + UCSR1C_USBS1 = 0x8 // Stop Bit Select + UCSR1C_UCSZ1 = 0x6 // Character Size + UCSR1C_UCPOL1 = 0x1 // Clock Polarity +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2B = 0x4 // Output Compare Flag 2B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Output Mode bits + TCCR2A_COM2B = 0x30 // Compare Output Mode bits + TCCR2A_WGM2 = 0x3 // Waveform Genration Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy + ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0x7 // External Interrupt Request 2 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0x7 // External Interrupt Flags + + // PCMSK3: Pin Change Mask Register 3 + PCMSK3_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0xf // Pin Change Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0xf // Pin Change Interrupt Enables +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register + DIDR0_ADC7D = 0x80 + DIDR0_ADC6D = 0x40 + DIDR0_ADC5D = 0x20 + DIDR0_ADC4D = 0x10 + DIDR0_ADC3D = 0x8 + DIDR0_ADC2D = 0x4 + DIDR0_ADC1D = 0x2 + DIDR0_ADC0D = 0x1 +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Timer/Counter1 Input Capture Flag + TIFR1_OCF1B = 0x4 // Timer/Counter1 Output Compare B Match Flag + TIFR1_OCF1A = 0x2 // Timer/Counter1 Output Compare A Match Flag + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Pulse Width Modulator Select Bits + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode Bits + TCCR1B_CS1 = 0x7 // Clock Select1 bits + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare for Channel A + TCCR1C_FOC1B = 0x40 // Force Output Compare for Channel B +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 + + // PRR0: Power Reduction Register0 + PRR0_PRTWI = 0x80 // Power Reduction TWI + PRR0_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR0_PRUSART1 = 0x10 // Power Reduction USART1 + PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR0_PRUSART0 = 0x2 // Power Reduction USART0 + PRR0_PRADC = 0x1 // Power Reduction ADC +) diff --git a/src/device/avr/atmega644a.ld b/src/device/avr/atmega644a.ld new file mode 100644 index 00000000..81de62f9 --- /dev/null +++ b/src/device/avr/atmega644a.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega644A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_size = 0x1000; +__num_isrs = 31; diff --git a/src/device/avr/atmega644p.go b/src/device/avr/atmega644p.go new file mode 100644 index 00000000..8511d495 --- /dev/null +++ b/src/device/avr/atmega644p.go @@ -0,0 +1,710 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega644P.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega644p + +// Device information for the ATmega644P. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega644P" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_PCINT0 = 4 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 5 // Pin Change Interrupt Request 1 + IRQ_PCINT2 = 6 // Pin Change Interrupt Request 2 + IRQ_PCINT3 = 7 // Pin Change Interrupt Request 3 + IRQ_WDT = 8 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 9 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 10 // Timer/Counter2 Compare Match B + IRQ_TIMER2_OVF = 11 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 12 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 13 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 14 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 15 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 16 // Timer/Counter0 Compare Match A + IRQ_TIMER0_COMPB = 17 // Timer/Counter0 Compare Match B + IRQ_TIMER0_OVF = 18 // Timer/Counter0 Overflow + IRQ_SPI_STC = 19 // SPI Serial Transfer Complete + IRQ_USART0_RX = 20 // USART0, Rx Complete + IRQ_USART0_UDRE = 21 // USART0 Data register Empty + IRQ_USART0_TX = 22 // USART0, Tx Complete + IRQ_ANALOG_COMP = 23 // Analog Comparator + IRQ_ADC = 24 // ADC Conversion Complete + IRQ_EE_READY = 25 // EEPROM Ready + IRQ_TWI = 26 // 2-wire Serial Interface + IRQ_SPM_READY = 27 // Store Program Memory Read + IRQ_USART1_RX = 28 // USART1 RX complete + IRQ_USART1_UDRE = 29 // USART1 Data Register Empty + IRQ_USART1_TX = 30 // USART1 TX complete + IRQ_max = 30 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + UDR1 __reg + UCSR1A __reg + UCSR1B __reg + UCSR1C __reg + UBRR1L __reg + UBRR1H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + UDR1: 0xce, // USART I/O Data Register + UCSR1A: 0xc8, // USART Control and Status Register A + UCSR1B: 0xc9, // USART Control and Status Register B + UCSR1C: 0xca, // USART Control and Status Register C + UBRR1L: 0xcc, // USART Baud Rate Register Bytes + UBRR1H: 0xcc, // USART Baud Rate Register Bytes + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK3 __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + PCICR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK3: 0x73, // Pin Change Mask Register 3 + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // The ADC Control and Status register A + DIDR0: 0x7e, // Digital Input Disable Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Low Bytes + EEARH: 0x41, // EEPROM Address Register Low Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PRR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PRR0: 0x64, // Power Reduction Register0 + } + + // Serial Peripheral Interface + SPI = struct { + SPDR __reg + SPSR __reg + SPCR __reg + }{ + SPDR: 0x4e, // SPI Data Register + SPSR: 0x4d, // SPI Status Register + SPCR: 0x4c, // SPI Control Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTB1 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0xc0 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity + + // UCSR1A: USART Control and Status Register A + UCSR1A_RXC1 = 0x80 // USART Receive Complete + UCSR1A_TXC1 = 0x40 // USART Transmitt Complete + UCSR1A_UDRE1 = 0x20 // USART Data Register Empty + UCSR1A_FE1 = 0x10 // Framing Error + UCSR1A_DOR1 = 0x8 // Data overRun + UCSR1A_UPE1 = 0x4 // Parity Error + UCSR1A_U2X1 = 0x2 // Double the USART transmission speed + UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode + + // UCSR1B: USART Control and Status Register B + UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable + UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable + UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable + UCSR1B_RXEN1 = 0x10 // Receiver Enable + UCSR1B_TXEN1 = 0x8 // Transmitter Enable + UCSR1B_UCSZ12 = 0x4 // Character Size + UCSR1B_RXB81 = 0x2 // Receive Data Bit 8 + UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8 + + // UCSR1C: USART Control and Status Register C + UCSR1C_UMSEL1 = 0xc0 // USART Mode Select + UCSR1C_UPM1 = 0x30 // Parity Mode Bits + UCSR1C_USBS1 = 0x8 // Stop Bit Select + UCSR1C_UCSZ1 = 0x6 // Character Size + UCSR1C_UCPOL1 = 0x1 // Clock Polarity +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2B = 0x4 // Output Compare Flag 2B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Output Mode bits + TCCR2A_COM2B = 0x30 // Compare Output Mode bits + TCCR2A_WGM2 = 0x3 // Waveform Genration Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy + ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0x7 // External Interrupt Request 2 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0x7 // External Interrupt Flags + + // PCMSK3: Pin Change Mask Register 3 + PCMSK3_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0xf // Pin Change Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0xf // Pin Change Interrupt Enables +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register + DIDR0_ADC7D = 0x80 + DIDR0_ADC6D = 0x40 + DIDR0_ADC5D = 0x20 + DIDR0_ADC4D = 0x10 + DIDR0_ADC3D = 0x8 + DIDR0_ADC2D = 0x4 + DIDR0_ADC1D = 0x2 + DIDR0_ADC0D = 0x1 +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Timer/Counter1 Input Capture Flag + TIFR1_OCF1B = 0x4 // Timer/Counter1 Output Compare B Match Flag + TIFR1_OCF1A = 0x2 // Timer/Counter1 Output Compare A Match Flag + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Pulse Width Modulator Select Bits + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode Bits + TCCR1B_CS1 = 0x7 // Clock Select1 bits + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare for Channel A + TCCR1C_FOC1B = 0x40 // Force Output Compare for Channel B +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 + + // PRR0: Power Reduction Register0 + PRR0_PRTWI = 0x80 // Power Reduction TWI + PRR0_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR0_PRUSART1 = 0x10 // Power Reduction USART1 + PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR0_PRUSART0 = 0x2 // Power Reduction USART0 + PRR0_PRADC = 0x1 // Power Reduction ADC +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects +) diff --git a/src/device/avr/atmega644p.ld b/src/device/avr/atmega644p.ld new file mode 100644 index 00000000..f43a61b9 --- /dev/null +++ b/src/device/avr/atmega644p.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega644P.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_size = 0x1000; +__num_isrs = 31; diff --git a/src/device/avr/atmega644pa.go b/src/device/avr/atmega644pa.go new file mode 100644 index 00000000..91dfd200 --- /dev/null +++ b/src/device/avr/atmega644pa.go @@ -0,0 +1,710 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega644PA.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega644pa + +// Device information for the ATmega644PA. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega644PA" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_PCINT0 = 4 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 5 // Pin Change Interrupt Request 1 + IRQ_PCINT2 = 6 // Pin Change Interrupt Request 2 + IRQ_PCINT3 = 7 // Pin Change Interrupt Request 3 + IRQ_WDT = 8 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 9 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 10 // Timer/Counter2 Compare Match B + IRQ_TIMER2_OVF = 11 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 12 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 13 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 14 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 15 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 16 // Timer/Counter0 Compare Match A + IRQ_TIMER0_COMPB = 17 // Timer/Counter0 Compare Match B + IRQ_TIMER0_OVF = 18 // Timer/Counter0 Overflow + IRQ_SPI_STC = 19 // SPI Serial Transfer Complete + IRQ_USART0_RX = 20 // USART0, Rx Complete + IRQ_USART0_UDRE = 21 // USART0 Data register Empty + IRQ_USART0_TX = 22 // USART0, Tx Complete + IRQ_ANALOG_COMP = 23 // Analog Comparator + IRQ_ADC = 24 // ADC Conversion Complete + IRQ_EE_READY = 25 // EEPROM Ready + IRQ_TWI = 26 // 2-wire Serial Interface + IRQ_SPM_READY = 27 // Store Program Memory Read + IRQ_USART1_RX = 28 // USART1 RX complete + IRQ_USART1_UDRE = 29 // USART1 Data Register Empty + IRQ_USART1_TX = 30 // USART1 TX complete + IRQ_max = 30 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + UDR1 __reg + UCSR1A __reg + UCSR1B __reg + UCSR1C __reg + UBRR1L __reg + UBRR1H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + UDR1: 0xce, // USART I/O Data Register + UCSR1A: 0xc8, // USART Control and Status Register A + UCSR1B: 0xc9, // USART Control and Status Register B + UCSR1C: 0xca, // USART Control and Status Register C + UBRR1L: 0xcc, // USART Baud Rate Register Bytes + UBRR1H: 0xcc, // USART Baud Rate Register Bytes + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK3 __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + PCICR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK3: 0x73, // Pin Change Mask Register 3 + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // The ADC Control and Status register A + DIDR0: 0x7e, // Digital Input Disable Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Low Bytes + EEARH: 0x41, // EEPROM Address Register Low Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PRR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PRR0: 0x64, // Power Reduction Register0 + } + + // Serial Peripheral Interface + SPI = struct { + SPDR __reg + SPSR __reg + SPCR __reg + }{ + SPDR: 0x4e, // SPI Data Register + SPSR: 0x4d, // SPI Status Register + SPCR: 0x4c, // SPI Control Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTB1 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0xc0 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity + + // UCSR1A: USART Control and Status Register A + UCSR1A_RXC1 = 0x80 // USART Receive Complete + UCSR1A_TXC1 = 0x40 // USART Transmitt Complete + UCSR1A_UDRE1 = 0x20 // USART Data Register Empty + UCSR1A_FE1 = 0x10 // Framing Error + UCSR1A_DOR1 = 0x8 // Data overRun + UCSR1A_UPE1 = 0x4 // Parity Error + UCSR1A_U2X1 = 0x2 // Double the USART transmission speed + UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode + + // UCSR1B: USART Control and Status Register B + UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable + UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable + UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable + UCSR1B_RXEN1 = 0x10 // Receiver Enable + UCSR1B_TXEN1 = 0x8 // Transmitter Enable + UCSR1B_UCSZ12 = 0x4 // Character Size + UCSR1B_RXB81 = 0x2 // Receive Data Bit 8 + UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8 + + // UCSR1C: USART Control and Status Register C + UCSR1C_UMSEL1 = 0xc0 // USART Mode Select + UCSR1C_UPM1 = 0x30 // Parity Mode Bits + UCSR1C_USBS1 = 0x8 // Stop Bit Select + UCSR1C_UCSZ1 = 0x6 // Character Size + UCSR1C_UCPOL1 = 0x1 // Clock Polarity +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2B = 0x4 // Output Compare Flag 2B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Output Mode bits + TCCR2A_COM2B = 0x30 // Compare Output Mode bits + TCCR2A_WGM2 = 0x3 // Waveform Genration Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy + ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0x7 // External Interrupt Request 2 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0x7 // External Interrupt Flags + + // PCMSK3: Pin Change Mask Register 3 + PCMSK3_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0xf // Pin Change Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0xf // Pin Change Interrupt Enables +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register + DIDR0_ADC7D = 0x80 + DIDR0_ADC6D = 0x40 + DIDR0_ADC5D = 0x20 + DIDR0_ADC4D = 0x10 + DIDR0_ADC3D = 0x8 + DIDR0_ADC2D = 0x4 + DIDR0_ADC1D = 0x2 + DIDR0_ADC0D = 0x1 +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Timer/Counter1 Input Capture Flag + TIFR1_OCF1B = 0x4 // Timer/Counter1 Output Compare B Match Flag + TIFR1_OCF1A = 0x2 // Timer/Counter1 Output Compare A Match Flag + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Pulse Width Modulator Select Bits + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode Bits + TCCR1B_CS1 = 0x7 // Clock Select1 bits + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare for Channel A + TCCR1C_FOC1B = 0x40 // Force Output Compare for Channel B +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 + + // PRR0: Power Reduction Register0 + PRR0_PRTWI = 0x80 // Power Reduction TWI + PRR0_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR0_PRUSART1 = 0x10 // Power Reduction USART1 + PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR0_PRUSART0 = 0x2 // Power Reduction USART0 + PRR0_PRADC = 0x1 // Power Reduction ADC +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects +) diff --git a/src/device/avr/atmega644pa.ld b/src/device/avr/atmega644pa.ld new file mode 100644 index 00000000..da53db94 --- /dev/null +++ b/src/device/avr/atmega644pa.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega644PA.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_size = 0x1000; +__num_isrs = 31; diff --git a/src/device/avr/atmega644rfr2.go b/src/device/avr/atmega644rfr2.go new file mode 100644 index 00000000..37899f48 --- /dev/null +++ b/src/device/avr/atmega644rfr2.go @@ -0,0 +1,1760 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega644RFR2.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega644rfr2 + +// Device information for the ATmega644RFR2. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega644RFR2" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_INT3 = 4 // External Interrupt Request 3 + IRQ_INT4 = 5 // External Interrupt Request 4 + IRQ_INT5 = 6 // External Interrupt Request 5 + IRQ_INT6 = 7 // External Interrupt Request 6 + IRQ_INT7 = 8 // External Interrupt Request 7 + IRQ_PCINT0 = 9 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 10 // Pin Change Interrupt Request 1 + IRQ_PCINT2 = 11 // Pin Change Interrupt Request 2 + IRQ_WDT = 12 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 13 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 14 // Timer/Counter2 Compare Match B + IRQ_TIMER2_OVF = 15 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 16 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 17 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 18 // Timer/Counter1 Compare Match B + IRQ_TIMER1_COMPC = 19 // Timer/Counter1 Compare Match C + IRQ_TIMER1_OVF = 20 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 21 // Timer/Counter0 Compare Match A + IRQ_TIMER0_COMPB = 22 // Timer/Counter0 Compare Match B + IRQ_TIMER0_OVF = 23 // Timer/Counter0 Overflow + IRQ_SPI_STC = 24 // SPI Serial Transfer Complete + IRQ_USART0_RX = 25 // USART0, Rx Complete + IRQ_USART0_UDRE = 26 // USART0 Data register Empty + IRQ_USART0_TX = 27 // USART0, Tx Complete + IRQ_ANALOG_COMP = 28 // Analog Comparator + IRQ_ADC = 29 // ADC Conversion Complete + IRQ_EE_READY = 30 // EEPROM Ready + IRQ_TIMER3_CAPT = 31 // Timer/Counter3 Capture Event + IRQ_TIMER3_COMPA = 32 // Timer/Counter3 Compare Match A + IRQ_TIMER3_COMPB = 33 // Timer/Counter3 Compare Match B + IRQ_TIMER3_COMPC = 34 // Timer/Counter3 Compare Match C + IRQ_TIMER3_OVF = 35 // Timer/Counter3 Overflow + IRQ_USART1_RX = 36 // USART1, Rx Complete + IRQ_USART1_UDRE = 37 // USART1 Data register Empty + IRQ_USART1_TX = 38 // USART1, Tx Complete + IRQ_TWI = 39 // 2-wire Serial Interface + IRQ_SPM_READY = 40 // Store Program Memory Read + IRQ_TIMER4_CAPT = 41 // Timer/Counter4 Capture Event + IRQ_TIMER4_COMPA = 42 // Timer/Counter4 Compare Match A + IRQ_TIMER4_COMPB = 43 // Timer/Counter4 Compare Match B + IRQ_TIMER4_COMPC = 44 // Timer/Counter4 Compare Match C + IRQ_TIMER4_OVF = 45 // Timer/Counter4 Overflow + IRQ_TIMER5_CAPT = 46 // Timer/Counter5 Capture Event + IRQ_TIMER5_COMPA = 47 // Timer/Counter5 Compare Match A + IRQ_TIMER5_COMPB = 48 // Timer/Counter5 Compare Match B + IRQ_TIMER5_COMPC = 49 // Timer/Counter5 Compare Match C + IRQ_TIMER5_OVF = 50 // Timer/Counter5 Overflow + IRQ_TRX24_PLL_LOCK = 57 // TRX24 - PLL lock interrupt + IRQ_TRX24_PLL_UNLOCK = 58 // TRX24 - PLL unlock interrupt + IRQ_TRX24_RX_START = 59 // TRX24 - Receive start interrupt + IRQ_TRX24_RX_END = 60 // TRX24 - RX_END interrupt + IRQ_TRX24_CCA_ED_DONE = 61 // TRX24 - CCA/ED done interrupt + IRQ_TRX24_XAH_AMI = 62 // TRX24 - XAH - AMI + IRQ_TRX24_TX_END = 63 // TRX24 - TX_END interrupt + IRQ_TRX24_AWAKE = 64 // TRX24 AWAKE - tranceiver is reaching state TRX_OFF + IRQ_SCNT_CMP1 = 65 // Symbol counter - compare match 1 interrupt + IRQ_SCNT_CMP2 = 66 // Symbol counter - compare match 2 interrupt + IRQ_SCNT_CMP3 = 67 // Symbol counter - compare match 3 interrupt + IRQ_SCNT_OVFL = 68 // Symbol counter - overflow interrupt + IRQ_SCNT_BACKOFF = 69 // Symbol counter - backoff interrupt + IRQ_AES_READY = 70 // AES engine ready interrupt + IRQ_BAT_LOW = 71 // Battery monitor indicates supply voltage below threshold + IRQ_TRX24_TX_START = 72 // TRX24 TX start interrupt + IRQ_TRX24_AMI0 = 73 // Address match interrupt of address filter 0 + IRQ_TRX24_AMI1 = 74 // Address match interrupt of address filter 1 + IRQ_TRX24_AMI2 = 75 // Address match interrupt of address filter 2 + IRQ_TRX24_AMI3 = 76 // Address match interrupt of address filter 3 + IRQ_max = 76 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // USART + USART = struct { + UDR0 __reg + UBRR0L __reg + UBRR0H __reg + UDR1 __reg + UBRR1L __reg + UBRR1H __reg + }{ + UDR0: 0xc6, // USART0 I/O Data Register + UBRR0L: 0xc4, // USART0 Baud Rate Register Bytes + UBRR0H: 0xc4, // USART0 Baud Rate Register Bytes + UDR1: 0xce, // USART1 I/O Data Register + UBRR1L: 0xcc, // USART1 Baud Rate Register Bytes + UBRR1H: 0xcc, // USART1 Baud Rate Register Bytes + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate Register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data Register + TWAR: 0xba, // TWI (Slave) Address Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins Address + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins Address + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins Address + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins Address + PORTE: 0x2e, // Port E Data Register + DDRE: 0x2d, // Port E Data Direction Register + PINE: 0x2c, // Port E Input Pins Address + PORTF: 0x31, // Port F Data Register + DDRF: 0x30, // Port F Data Direction Register + PINF: 0x2f, // Port F Input Pins Address + PORTG: 0x34, // Port G Data Register + DDRG: 0x33, // Port G Data Direction Register + PING: 0x32, // Port G Input Pins Address + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register B + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 Register + TCCR0B: 0x45, // Timer/Counter0 Control Register B + TCCR0A: 0x44, // Timer/Counter0 Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag Register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR5A __reg + TCCR5B __reg + TCCR5C __reg + TCNT5L __reg + TCNT5H __reg + OCR5AL __reg + OCR5AH __reg + OCR5BL __reg + OCR5BH __reg + OCR5CL __reg + OCR5CH __reg + ICR5L __reg + ICR5H __reg + TIMSK5 __reg + TIFR5 __reg + TCCR4A __reg + TCCR4B __reg + TCCR4C __reg + TCNT4L __reg + TCNT4H __reg + OCR4AL __reg + OCR4AH __reg + OCR4BL __reg + OCR4BH __reg + OCR4CL __reg + OCR4CH __reg + ICR4L __reg + ICR4H __reg + TIMSK4 __reg + TIFR4 __reg + TCCR3A __reg + TCCR3B __reg + TCCR3C __reg + TCNT3L __reg + TCNT3H __reg + OCR3AL __reg + OCR3AH __reg + OCR3BL __reg + OCR3BH __reg + OCR3CL __reg + OCR3CH __reg + ICR3L __reg + ICR3H __reg + TIMSK3 __reg + TIFR3 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + OCR1CL __reg + OCR1CH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR5A: 0x120, // Timer/Counter5 Control Register A + TCCR5B: 0x121, // Timer/Counter5 Control Register B + TCCR5C: 0x122, // Timer/Counter5 Control Register C + TCNT5L: 0x124, // Timer/Counter5 Bytes + TCNT5H: 0x124, // Timer/Counter5 Bytes + OCR5AL: 0x128, // Timer/Counter5 Output Compare Register A Bytes + OCR5AH: 0x128, // Timer/Counter5 Output Compare Register A Bytes + OCR5BL: 0x12a, // Timer/Counter5 Output Compare Register B Bytes + OCR5BH: 0x12a, // Timer/Counter5 Output Compare Register B Bytes + OCR5CL: 0x12c, // Timer/Counter5 Output Compare Register C Bytes + OCR5CH: 0x12c, // Timer/Counter5 Output Compare Register C Bytes + ICR5L: 0x126, // Timer/Counter5 Input Capture Register Bytes + ICR5H: 0x126, // Timer/Counter5 Input Capture Register Bytes + TIMSK5: 0x73, // Timer/Counter5 Interrupt Mask Register + TIFR5: 0x3a, // Timer/Counter5 Interrupt Flag Register + TCCR4A: 0xa0, // Timer/Counter4 Control Register A + TCCR4B: 0xa1, // Timer/Counter4 Control Register B + TCCR4C: 0xa2, // Timer/Counter4 Control Register C + TCNT4L: 0xa4, // Timer/Counter4 Bytes + TCNT4H: 0xa4, // Timer/Counter4 Bytes + OCR4AL: 0xa8, // Timer/Counter4 Output Compare Register A Bytes + OCR4AH: 0xa8, // Timer/Counter4 Output Compare Register A Bytes + OCR4BL: 0xaa, // Timer/Counter4 Output Compare Register B Bytes + OCR4BH: 0xaa, // Timer/Counter4 Output Compare Register B Bytes + OCR4CL: 0xac, // Timer/Counter4 Output Compare Register C Bytes + OCR4CH: 0xac, // Timer/Counter4 Output Compare Register C Bytes + ICR4L: 0xa6, // Timer/Counter4 Input Capture Register Bytes + ICR4H: 0xa6, // Timer/Counter4 Input Capture Register Bytes + TIMSK4: 0x72, // Timer/Counter4 Interrupt Mask Register + TIFR4: 0x39, // Timer/Counter4 Interrupt Flag Register + TCCR3A: 0x90, // Timer/Counter3 Control Register A + TCCR3B: 0x91, // Timer/Counter3 Control Register B + TCCR3C: 0x92, // Timer/Counter3 Control Register C + TCNT3L: 0x94, // Timer/Counter3 Bytes + TCNT3H: 0x94, // Timer/Counter3 Bytes + OCR3AL: 0x98, // Timer/Counter3 Output Compare Register A Bytes + OCR3AH: 0x98, // Timer/Counter3 Output Compare Register A Bytes + OCR3BL: 0x9a, // Timer/Counter3 Output Compare Register B Bytes + OCR3BH: 0x9a, // Timer/Counter3 Output Compare Register B Bytes + OCR3CL: 0x9c, // Timer/Counter3 Output Compare Register C Bytes + OCR3CH: 0x9c, // Timer/Counter3 Output Compare Register C Bytes + ICR3L: 0x96, // Timer/Counter3 Input Capture Register Bytes + ICR3H: 0x96, // Timer/Counter3 Input Capture Register Bytes + TIMSK3: 0x71, // Timer/Counter3 Interrupt Mask Register + TIFR3: 0x38, // Timer/Counter3 Interrupt Flag Register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1CL: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + OCR1CH: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag Register + } + + // Low-Power 2.4 GHz Transceiver + TRX24 = struct { + PARCR __reg + MAFSA0L __reg + MAFSA0H __reg + MAFPA0L __reg + MAFPA0H __reg + MAFSA1L __reg + MAFSA1H __reg + MAFPA1L __reg + MAFPA1H __reg + MAFSA2L __reg + MAFSA2H __reg + MAFPA2L __reg + MAFPA2H __reg + MAFSA3L __reg + MAFSA3H __reg + MAFPA3L __reg + MAFPA3H __reg + MAFCR0 __reg + MAFCR1 __reg + AES_CTRL __reg + AES_STATUS __reg + AES_STATE __reg + AES_KEY __reg + TRX_STATUS __reg + TRX_STATE __reg + TRX_CTRL_0 __reg + TRX_CTRL_1 __reg + PHY_TX_PWR __reg + PHY_RSSI __reg + PHY_ED_LEVEL __reg + PHY_CC_CCA __reg + CCA_THRES __reg + RX_CTRL __reg + SFD_VALUE __reg + TRX_CTRL_2 __reg + ANT_DIV __reg + IRQ_MASK __reg + IRQ_STATUS __reg + IRQ_MASK1 __reg + IRQ_STATUS1 __reg + VREG_CTRL __reg + BATMON __reg + XOSC_CTRL __reg + CC_CTRL_0 __reg + CC_CTRL_1 __reg + RX_SYN __reg + TRX_RPC __reg + XAH_CTRL_1 __reg + FTN_CTRL __reg + PLL_CF __reg + PLL_DCU __reg + PART_NUM __reg + VERSION_NUM __reg + MAN_ID_0 __reg + MAN_ID_1 __reg + SHORT_ADDR_0 __reg + SHORT_ADDR_1 __reg + PAN_ID_0 __reg + PAN_ID_1 __reg + IEEE_ADDR_0 __reg + IEEE_ADDR_1 __reg + IEEE_ADDR_2 __reg + IEEE_ADDR_3 __reg + IEEE_ADDR_4 __reg + IEEE_ADDR_5 __reg + IEEE_ADDR_6 __reg + IEEE_ADDR_7 __reg + XAH_CTRL_0 __reg + CSMA_SEED_0 __reg + CSMA_SEED_1 __reg + CSMA_BE __reg + TST_CTRL_DIGI __reg + TST_RX_LENGTH __reg + TRXFBST __reg + TRXFBEND __reg + }{ + PARCR: 0x138, // Power Amplifier Ramp up/down Control Register + MAFSA0L: 0x10e, // Transceiver MAC Short Address Register for Frame Filter 0 (Low Byte) + MAFSA0H: 0x10f, // Transceiver MAC Short Address Register for Frame Filter 0 (High Byte) + MAFPA0L: 0x110, // Transceiver Personal Area Network ID Register for Frame Filter 0 (Low Byte) + MAFPA0H: 0x111, // Transceiver Personal Area Network ID Register for Frame Filter 0 (High Byte) + MAFSA1L: 0x112, // Transceiver MAC Short Address Register for Frame Filter 1 (Low Byte) + MAFSA1H: 0x113, // Transceiver MAC Short Address Register for Frame Filter 1 (High Byte) + MAFPA1L: 0x114, // Transceiver Personal Area Network ID Register for Frame Filter 1 (Low Byte) + MAFPA1H: 0x115, // Transceiver Personal Area Network ID Register for Frame Filter 1 (High Byte) + MAFSA2L: 0x116, // Transceiver MAC Short Address Register for Frame Filter 2 (Low Byte) + MAFSA2H: 0x117, // Transceiver MAC Short Address Register for Frame Filter 2 (High Byte) + MAFPA2L: 0x118, // Transceiver Personal Area Network ID Register for Frame Filter 2 (Low Byte) + MAFPA2H: 0x119, // Transceiver Personal Area Network ID Register for Frame Filter 2 (High Byte) + MAFSA3L: 0x11a, // Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte) + MAFSA3H: 0x11b, // Transceiver MAC Short Address Register for Frame Filter 3 (High Byte) + MAFPA3L: 0x11c, // Transceiver Personal Area Network ID Register for Frame Filter 3 (Low Byte) + MAFPA3H: 0x11d, // Transceiver Personal Area Network ID Register for Frame Filter 3 (High Byte) + MAFCR0: 0x10c, // Multiple Address Filter Configuration Register 0 + MAFCR1: 0x10d, // Multiple Address Filter Configuration Register 1 + AES_CTRL: 0x13c, // AES Control Register + AES_STATUS: 0x13d, // AES Status Register + AES_STATE: 0x13e, // AES Plain and Cipher Text Buffer Register + AES_KEY: 0x13f, // AES Encryption and Decryption Key Buffer Register + TRX_STATUS: 0x141, // Transceiver Status Register + TRX_STATE: 0x142, // Transceiver State Control Register + TRX_CTRL_0: 0x143, // Reserved + TRX_CTRL_1: 0x144, // Transceiver Control Register 1 + PHY_TX_PWR: 0x145, // Transceiver Transmit Power Control Register + PHY_RSSI: 0x146, // Receiver Signal Strength Indicator Register + PHY_ED_LEVEL: 0x147, // Transceiver Energy Detection Level Register + PHY_CC_CCA: 0x148, // Transceiver Clear Channel Assessment (CCA) Control Register + CCA_THRES: 0x149, // Transceiver CCA Threshold Setting Register + RX_CTRL: 0x14a, // Transceiver Receive Control Register + SFD_VALUE: 0x14b, // Start of Frame Delimiter Value Register + TRX_CTRL_2: 0x14c, // Transceiver Control Register 2 + ANT_DIV: 0x14d, // Antenna Diversity Control Register + IRQ_MASK: 0x14e, // Transceiver Interrupt Enable Register + IRQ_STATUS: 0x14f, // Transceiver Interrupt Status Register + IRQ_MASK1: 0xbe, // Transceiver Interrupt Enable Register 1 + IRQ_STATUS1: 0xbf, // Transceiver Interrupt Status Register 1 + VREG_CTRL: 0x150, // Voltage Regulator Control and Status Register + BATMON: 0x151, // Battery Monitor Control and Status Register + XOSC_CTRL: 0x152, // Crystal Oscillator Control Register + CC_CTRL_0: 0x153, // Channel Control Register 0 + CC_CTRL_1: 0x154, // Channel Control Register 1 + RX_SYN: 0x155, // Transceiver Receiver Sensitivity Control Register + TRX_RPC: 0x156, // Transceiver Reduced Power Consumption Control + XAH_CTRL_1: 0x157, // Transceiver Acknowledgment Frame Control Register 1 + FTN_CTRL: 0x158, // Transceiver Filter Tuning Control Register + PLL_CF: 0x15a, // Transceiver Center Frequency Calibration Control Register + PLL_DCU: 0x15b, // Transceiver Delay Cell Calibration Control Register + PART_NUM: 0x15c, // Device Identification Register (Part Number) + VERSION_NUM: 0x15d, // Device Identification Register (Version Number) + MAN_ID_0: 0x15e, // Device Identification Register (Manufacture ID Low Byte) + MAN_ID_1: 0x15f, // Device Identification Register (Manufacture ID High Byte) + SHORT_ADDR_0: 0x160, // Transceiver MAC Short Address Register (Low Byte) + SHORT_ADDR_1: 0x161, // Transceiver MAC Short Address Register (High Byte) + PAN_ID_0: 0x162, // Transceiver Personal Area Network ID Register (Low Byte) + PAN_ID_1: 0x163, // Transceiver Personal Area Network ID Register (High Byte) + IEEE_ADDR_0: 0x164, // Transceiver MAC IEEE Address Register 0 + IEEE_ADDR_1: 0x165, // Transceiver MAC IEEE Address Register 1 + IEEE_ADDR_2: 0x166, // Transceiver MAC IEEE Address Register 2 + IEEE_ADDR_3: 0x167, // Transceiver MAC IEEE Address Register 3 + IEEE_ADDR_4: 0x168, // Transceiver MAC IEEE Address Register 4 + IEEE_ADDR_5: 0x169, // Transceiver MAC IEEE Address Register 5 + IEEE_ADDR_6: 0x16a, // Transceiver MAC IEEE Address Register 6 + IEEE_ADDR_7: 0x16b, // Transceiver MAC IEEE Address Register 7 + XAH_CTRL_0: 0x16c, // Transceiver Extended Operating Mode Control Register + CSMA_SEED_0: 0x16d, // Transceiver CSMA-CA Random Number Generator Seed Register + CSMA_SEED_1: 0x16e, // Transceiver Acknowledgment Frame Control Register 2 + CSMA_BE: 0x16f, // Transceiver CSMA-CA Back-off Exponent Control Register + TST_CTRL_DIGI: 0x176, // Transceiver Digital Test Control Register + TST_RX_LENGTH: 0x17b, // Transceiver Received Frame Length Register + TRXFBST: 0x180, // Start of frame buffer + TRXFBEND: 0x1ff, // End of frame buffer + } + + // MAC Symbol Counter + SYMCNT = struct { + SCTSTRHH __reg + SCTSTRHL __reg + SCTSTRLH __reg + SCTSTRLL __reg + SCOCR1HH __reg + SCOCR1HL __reg + SCOCR1LH __reg + SCOCR1LL __reg + SCOCR2HH __reg + SCOCR2HL __reg + SCOCR2LH __reg + SCOCR2LL __reg + SCOCR3HH __reg + SCOCR3HL __reg + SCOCR3LH __reg + SCOCR3LL __reg + SCTSRHH __reg + SCTSRHL __reg + SCTSRLH __reg + SCTSRLL __reg + SCBTSRHH __reg + SCBTSRHL __reg + SCBTSRLH __reg + SCBTSRLL __reg + SCCNTHH __reg + SCCNTHL __reg + SCCNTLH __reg + SCCNTLL __reg + SCIRQS __reg + SCIRQM __reg + SCSR __reg + SCCR1 __reg + SCCR0 __reg + SCCSR __reg + SCRSTRHH __reg + SCRSTRHL __reg + SCRSTRLH __reg + SCRSTRLL __reg + }{ + SCTSTRHH: 0xfc, // Symbol Counter Transmit Frame Timestamp Register HH-Byte + SCTSTRHL: 0xfb, // Symbol Counter Transmit Frame Timestamp Register HL-Byte + SCTSTRLH: 0xfa, // Symbol Counter Transmit Frame Timestamp Register LH-Byte + SCTSTRLL: 0xf9, // Symbol Counter Transmit Frame Timestamp Register LL-Byte + SCOCR1HH: 0xf8, // Symbol Counter Output Compare Register 1 HH-Byte + SCOCR1HL: 0xf7, // Symbol Counter Output Compare Register 1 HL-Byte + SCOCR1LH: 0xf6, // Symbol Counter Output Compare Register 1 LH-Byte + SCOCR1LL: 0xf5, // Symbol Counter Output Compare Register 1 LL-Byte + SCOCR2HH: 0xf4, // Symbol Counter Output Compare Register 2 HH-Byte + SCOCR2HL: 0xf3, // Symbol Counter Output Compare Register 2 HL-Byte + SCOCR2LH: 0xf2, // Symbol Counter Output Compare Register 2 LH-Byte + SCOCR2LL: 0xf1, // Symbol Counter Output Compare Register 2 LL-Byte + SCOCR3HH: 0xf0, // Symbol Counter Output Compare Register 3 HH-Byte + SCOCR3HL: 0xef, // Symbol Counter Output Compare Register 3 HL-Byte + SCOCR3LH: 0xee, // Symbol Counter Output Compare Register 3 LH-Byte + SCOCR3LL: 0xed, // Symbol Counter Output Compare Register 3 LL-Byte + SCTSRHH: 0xec, // Symbol Counter Frame Timestamp Register HH-Byte + SCTSRHL: 0xeb, // Symbol Counter Frame Timestamp Register HL-Byte + SCTSRLH: 0xea, // Symbol Counter Frame Timestamp Register LH-Byte + SCTSRLL: 0xe9, // Symbol Counter Frame Timestamp Register LL-Byte + SCBTSRHH: 0xe8, // Symbol Counter Beacon Timestamp Register HH-Byte + SCBTSRHL: 0xe7, // Symbol Counter Beacon Timestamp Register HL-Byte + SCBTSRLH: 0xe6, // Symbol Counter Beacon Timestamp Register LH-Byte + SCBTSRLL: 0xe5, // Symbol Counter Beacon Timestamp Register LL-Byte + SCCNTHH: 0xe4, // Symbol Counter Register HH-Byte + SCCNTHL: 0xe3, // Symbol Counter Register HL-Byte + SCCNTLH: 0xe2, // Symbol Counter Register LH-Byte + SCCNTLL: 0xe1, // Symbol Counter Register LL-Byte + SCIRQS: 0xe0, // Symbol Counter Interrupt Status Register + SCIRQM: 0xdf, // Symbol Counter Interrupt Mask Register + SCSR: 0xde, // Symbol Counter Status Register + SCCR1: 0xdd, // Symbol Counter Control Register 1 + SCCR0: 0xdc, // Symbol Counter Control Register 0 + SCCSR: 0xdb, // Symbol Counter Compare Source Register + SCRSTRHH: 0xda, // Symbol Counter Received Frame Timestamp Register HH-Byte + SCRSTRHL: 0xd9, // Symbol Counter Received Frame Timestamp Register HL-Byte + SCRSTRLH: 0xd8, // Symbol Counter Received Frame Timestamp Register LH-Byte + SCRSTRLL: 0xd7, // Symbol Counter Received Frame Timestamp Register LL-Byte + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Bytes + EEARH: 0x41, // EEPROM Address Register Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EICRB __reg + EIMSK __reg + EIFR __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + PCICR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EICRB: 0x6a, // External Interrupt Control Register B + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + ADCSRC __reg + DIDR2 __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC Multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // The ADC Control and Status Register A + ADCSRC: 0x77, // The ADC Control and Status Register C + DIDR2: 0x7d, // Digital Input Disable Register 2 + DIDR0: 0x7e, // Digital Input Disable Register 0 + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PRR2 __reg + PRR1 __reg + PRR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose I/O Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PRR2: 0x63, // Power Reduction Register 2 + PRR1: 0x65, // Power Reduction Register 1 + PRR0: 0x64, // Power Reduction Register0 + } + + // FLASH Controller + FLASH = struct { + NEMCR __reg + BGCR __reg + }{ + NEMCR: 0x75, // Flash Extended-Mode Control-Register + BGCR: 0x67, // Reference Voltage Calibration Register + } + + // Power Controller + PWRCTRL = struct { + TRXPR __reg + DRTRAM0 __reg + DRTRAM1 __reg + DRTRAM2 __reg + DRTRAM3 __reg + LLDRL __reg + LLDRH __reg + LLCR __reg + DPDS0 __reg + DPDS1 __reg + }{ + TRXPR: 0x139, // Transceiver Pin Register + DRTRAM0: 0x135, // Data Retention Configuration Register #0 + DRTRAM1: 0x134, // Data Retention Configuration Register #1 + DRTRAM2: 0x133, // Data Retention Configuration Register #2 + DRTRAM3: 0x132, // Data Retention Configuration Register #3 + LLDRL: 0x130, // Low Leakage Voltage Regulator Data Register (Low-Byte) + LLDRH: 0x131, // Low Leakage Voltage Regulator Data Register (High-Byte) + LLCR: 0x12f, // Low Leakage Voltage Regulator Control Register + DPDS0: 0x136, // Port Driver Strength Register 0 + DPDS1: 0x137, // Port Driver Strength Register 1 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_CKSEL_SUT = 0x3f // Select Clock Source : Start-up time +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe // TWI Address Mask + TWAMR_Res = 0x1 // Reserved Bit + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI START Condition Bit + TWCR_TWSTO = 0x10 // TWI STOP Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collision Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_Res = 0x2 // Reserved Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_Res = 0x4 // Reserved Bit + TWSR_TWPS = 0x3 // TWI Prescaler Bits + + // TWAR: TWI (Slave) Address Register + TWAR_TWA = 0xfe // TWI (Slave) Address + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Select 1 and 0 + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter0 Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_Res = 0x30 // Reserved Bit + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter0 Control Register A + TCCR0A_COM0A = 0xc0 // Compare Match Output A Mode + TCCR0A_COM0B = 0x30 // Compare Match Output B Mode + TCCR0A_Res = 0xc // Reserved Bit + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag Register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare B Match Flag + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare A Match Flag + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_Res = 0xf8 // Reserved Bit + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_Res = 0xf8 // Reserved Bit + TIFR2_OCF2B = 0x4 // Output Compare Flag 2 B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2 A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Match Output A Mode + TCCR2A_COM2B = 0x30 // Compare Match Output B Mode + TCCR2A_WGM2 = 0x3 // Waveform Generation Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select + + // ASSR: Asynchronous Status Register + ASSR_EXCLKAMR = 0x80 // Enable External Clock Input for AMR + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Timer/Counter2 Asynchronous Mode + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Timer/Counter2 Output Compare Register A Update Busy + ASSR_OCR2BUB = 0x4 // Timer/Counter2 Output Compare Register B Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter2 Control Register A Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter2 Control Register B Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR5A: Timer/Counter5 Control Register A + TCCR5A_COM5A = 0xc0 // Compare Output Mode for Channel A + TCCR5A_COM5B = 0x30 // Compare Output Mode for Channel B + TCCR5A_COM5C = 0xc // Compare Output Mode for Channel C + TCCR5A_WGM5 = 0x3 // Waveform Generation Mode + + // TCCR5B: Timer/Counter5 Control Register B + TCCR5B_ICNC5 = 0x80 // Input Capture 5 Noise Canceller + TCCR5B_ICES5 = 0x40 // Input Capture 5 Edge Select + TCCR5B_Res = 0x20 // Reserved Bit + TCCR5B_WGM5 = 0x18 // Waveform Generation Mode + TCCR5B_CS5 = 0x7 // Clock Select + + // TCCR5C: Timer/Counter5 Control Register C + TCCR5C_FOC5A = 0x80 // Force Output Compare for Channel A + TCCR5C_FOC5B = 0x40 // Force Output Compare for Channel B + TCCR5C_FOC5C = 0x20 // Force Output Compare for Channel C + + // TIMSK5: Timer/Counter5 Interrupt Mask Register + TIMSK5_ICIE5 = 0x20 // Timer/Counter5 Input Capture Interrupt Enable + TIMSK5_OCIE5C = 0x8 // Timer/Counter5 Output Compare C Match Interrupt Enable + TIMSK5_OCIE5B = 0x4 // Timer/Counter5 Output Compare B Match Interrupt Enable + TIMSK5_OCIE5A = 0x2 // Timer/Counter5 Output Compare A Match Interrupt Enable + TIMSK5_TOIE5 = 0x1 // Timer/Counter5 Overflow Interrupt Enable + + // TIFR5: Timer/Counter5 Interrupt Flag Register + TIFR5_ICF5 = 0x20 // Timer/Counter5 Input Capture Flag + TIFR5_OCF5C = 0x8 // Timer/Counter5 Output Compare C Match Flag + TIFR5_OCF5B = 0x4 // Timer/Counter5 Output Compare B Match Flag + TIFR5_OCF5A = 0x2 // Timer/Counter5 Output Compare A Match Flag + TIFR5_TOV5 = 0x1 // Timer/Counter5 Overflow Flag + + // TCCR4A: Timer/Counter4 Control Register A + TCCR4A_COM4A = 0xc0 // Compare Output Mode for Channel A + TCCR4A_COM4B = 0x30 // Compare Output Mode for Channel B + TCCR4A_COM4C = 0xc // Compare Output Mode for Channel C + TCCR4A_WGM4 = 0x3 // Waveform Generation Mode + + // TCCR4B: Timer/Counter4 Control Register B + TCCR4B_ICNC4 = 0x80 // Input Capture 4 Noise Canceller + TCCR4B_ICES4 = 0x40 // Input Capture 4 Edge Select + TCCR4B_Res = 0x20 // Reserved Bit + TCCR4B_WGM4 = 0x18 // Waveform Generation Mode + TCCR4B_CS4 = 0x7 // Clock Select + + // TCCR4C: Timer/Counter4 Control Register C + TCCR4C_FOC4A = 0x80 // Force Output Compare for Channel A + TCCR4C_FOC4B = 0x40 // Force Output Compare for Channel B + TCCR4C_FOC4C = 0x20 // Force Output Compare for Channel C + + // TIMSK4: Timer/Counter4 Interrupt Mask Register + TIMSK4_ICIE4 = 0x20 // Timer/Counter4 Input Capture Interrupt Enable + TIMSK4_OCIE4C = 0x8 // Timer/Counter4 Output Compare C Match Interrupt Enable + TIMSK4_OCIE4B = 0x4 // Timer/Counter4 Output Compare B Match Interrupt Enable + TIMSK4_OCIE4A = 0x2 // Timer/Counter4 Output Compare A Match Interrupt Enable + TIMSK4_TOIE4 = 0x1 // Timer/Counter4 Overflow Interrupt Enable + + // TIFR4: Timer/Counter4 Interrupt Flag Register + TIFR4_ICF4 = 0x20 // Timer/Counter4 Input Capture Flag + TIFR4_OCF4C = 0x8 // Timer/Counter4 Output Compare C Match Flag + TIFR4_OCF4B = 0x4 // Timer/Counter4 Output Compare B Match Flag + TIFR4_OCF4A = 0x2 // Timer/Counter4 Output Compare A Match Flag + TIFR4_TOV4 = 0x1 // Timer/Counter4 Overflow Flag + + // TCCR3A: Timer/Counter3 Control Register A + TCCR3A_COM3A = 0xc0 // Compare Output Mode for Channel A + TCCR3A_COM3B = 0x30 // Compare Output Mode for Channel B + TCCR3A_COM3C = 0xc // Compare Output Mode for Channel C + TCCR3A_WGM3 = 0x3 // Waveform Generation Mode + + // TCCR3B: Timer/Counter3 Control Register B + TCCR3B_ICNC3 = 0x80 // Input Capture 3 Noise Canceller + TCCR3B_ICES3 = 0x40 // Input Capture 3 Edge Select + TCCR3B_Res = 0x20 // Reserved Bit + TCCR3B_WGM3 = 0x18 // Waveform Generation Mode + TCCR3B_CS3 = 0x7 // Clock Select + + // TCCR3C: Timer/Counter3 Control Register C + TCCR3C_FOC3A = 0x80 // Force Output Compare for Channel A + TCCR3C_FOC3B = 0x40 // Force Output Compare for Channel B + TCCR3C_FOC3C = 0x20 // Force Output Compare for Channel C + + // TIMSK3: Timer/Counter3 Interrupt Mask Register + TIMSK3_ICIE3 = 0x20 // Timer/Counter3 Input Capture Interrupt Enable + TIMSK3_OCIE3C = 0x8 // Timer/Counter3 Output Compare C Match Interrupt Enable + TIMSK3_OCIE3B = 0x4 // Timer/Counter3 Output Compare B Match Interrupt Enable + TIMSK3_OCIE3A = 0x2 // Timer/Counter3 Output Compare A Match Interrupt Enable + TIMSK3_TOIE3 = 0x1 // Timer/Counter3 Overflow Interrupt Enable + + // TIFR3: Timer/Counter3 Interrupt Flag Register + TIFR3_ICF3 = 0x20 // Timer/Counter3 Input Capture Flag + TIFR3_OCF3C = 0x8 // Timer/Counter3 Output Compare C Match Flag + TIFR3_OCF3B = 0x4 // Timer/Counter3 Output Compare B Match Flag + TIFR3_OCF3A = 0x2 // Timer/Counter3 Output Compare A Match Flag + TIFR3_TOV3 = 0x1 // Timer/Counter3 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode for Channel A + TCCR1A_COM1B = 0x30 // Compare Output Mode for Channel B + TCCR1A_COM1C = 0xc // Compare Output Mode for Channel C + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceller + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_Res = 0x20 // Reserved Bit + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Clock Select + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare for Channel A + TCCR1C_FOC1B = 0x40 // Force Output Compare for Channel B + TCCR1C_FOC1C = 0x20 // Force Output Compare for Channel C + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1C = 0x8 // Timer/Counter1 Output Compare C Match Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag Register + TIFR1_ICF1 = 0x20 // Timer/Counter1 Input Capture Flag + TIFR1_OCF1C = 0x8 // Timer/Counter1 Output Compare C Match Flag + TIFR1_OCF1B = 0x4 // Timer/Counter1 Output Compare B Match Flag + TIFR1_OCF1A = 0x2 // Timer/Counter1 Output Compare A Match Flag + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for TRX24: Low-Power 2.4 GHz Transceiver +const ( + // PARCR: Power Amplifier Ramp up/down Control Register + PARCR_PALTD = 0xe0 // ext. PA Ramp Down Lead Time + PARCR_PALTU = 0x1c // ext. PA Ramp Up Lead Time + PARCR_PARDFI = 0x2 // Power Amplifier Ramp Down Frequency Inversion + PARCR_PARUFI = 0x1 // Power Amplifier Ramp Up Frequency Inversion + + // MAFSA0L: Transceiver MAC Short Address Register for Frame Filter 0 (Low Byte) + MAFSA0L_MAFSA0L = 0xff // MAC Short Address low Byte for Frame Filter 0 + + // MAFSA0H: Transceiver MAC Short Address Register for Frame Filter 0 (High Byte) + MAFSA0H_MAFSA0H = 0xff // MAC Short Address high Byte for Frame Filter 0 + + // MAFPA0L: Transceiver Personal Area Network ID Register for Frame Filter 0 (Low Byte) + MAFPA0L_MAFPA0L = 0xff // MAC Personal Area Network ID low Byte for Frame Filter 0 + + // MAFPA0H: Transceiver Personal Area Network ID Register for Frame Filter 0 (High Byte) + MAFPA0H_MAFPA0H = 0xff // MAC Personal Area Network ID high Byte for Frame Filter 0 + + // MAFSA1L: Transceiver MAC Short Address Register for Frame Filter 1 (Low Byte) + MAFSA1L_MAFSA1L = 0xff // MAC Short Address low Byte for Frame Filter 1 + + // MAFSA1H: Transceiver MAC Short Address Register for Frame Filter 1 (High Byte) + MAFSA1H_MAFSA1H = 0xff // MAC Short Address high Byte for Frame Filter 1 + + // MAFPA1L: Transceiver Personal Area Network ID Register for Frame Filter 1 (Low Byte) + MAFPA1L_MAFPA1L = 0xff // MAC Personal Area Network ID low Byte for Frame Filter 1 + + // MAFPA1H: Transceiver Personal Area Network ID Register for Frame Filter 1 (High Byte) + MAFPA1H_MAFPA1H = 0xff // MAC Personal Area Network ID high Byte for Frame Filter 1 + + // MAFSA2L: Transceiver MAC Short Address Register for Frame Filter 2 (Low Byte) + MAFSA2L_MAFSA2L = 0xff // MAC Short Address low Byte for Frame Filter 2 + + // MAFSA2H: Transceiver MAC Short Address Register for Frame Filter 2 (High Byte) + MAFSA2H_MAFSA2H = 0xff // MAC Short Address high Byte for Frame Filter 2 + + // MAFPA2L: Transceiver Personal Area Network ID Register for Frame Filter 2 (Low Byte) + MAFPA2L_MAFPA2L = 0xff // MAC Personal Area Network ID low Byte for Frame Filter 2 + + // MAFPA2H: Transceiver Personal Area Network ID Register for Frame Filter 2 (High Byte) + MAFPA2H_MAFPA2H = 0xff // MAC Personal Area Network ID high Byte for Frame Filter 2 + + // MAFSA3L: Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte) + MAFSA3L_MAFSA3L = 0xff // MAC Short Address low Byte for Frame Filter 3 + + // MAFSA3H: Transceiver MAC Short Address Register for Frame Filter 3 (High Byte) + MAFSA3H_MAFSA3H = 0xff // MAC Short Address high Byte for Frame Filter 3 + + // MAFPA3L: Transceiver Personal Area Network ID Register for Frame Filter 3 (Low Byte) + MAFPA3L_MAFPA3L = 0xff // MAC Personal Area Network ID low Byte for Frame Filter 3 + + // MAFPA3H: Transceiver Personal Area Network ID Register for Frame Filter 3 (High Byte) + MAFPA3H_MAFPA3H = 0xff // MAC Personal Area Network ID high Byte for Frame Filter 3 + + // MAFCR0: Multiple Address Filter Configuration Register 0 + MAFCR0_Res = 0xf0 // Reserved Bit + MAFCR0_MAF3EN = 0x8 // Multiple Address Filter 3 Enable + MAFCR0_MAF2EN = 0x4 // Multiple Address Filter 2 Enable + MAFCR0_MAF1EN = 0x2 // Multiple Address Filter 1 Enable + MAFCR0_MAF0EN = 0x1 // Multiple Address Filter 0 Enable + + // MAFCR1: Multiple Address Filter Configuration Register 1 + MAFCR1_AACK_3_SET_PD = 0x80 // Set Data Pending bit for address filter 3. + MAFCR1_AACK_3_I_AM_COORD = 0x40 // Enable PAN Coordinator mode for address filter 3. + MAFCR1_AACK_2_SET_PD = 0x20 // Set Data Pending bit for address filter 2. + MAFCR1_AACK_2_I_AM_COORD = 0x10 // Enable PAN Coordinator mode for address filter 2. + MAFCR1_AACK_1_SET_PD = 0x8 // Set Data Pending bit for address filter 1. + MAFCR1_AACK_1_I_AM_COORD = 0x4 // Enable PAN Coordinator mode for address filter 1. + MAFCR1_AACK_0_SET_PD = 0x2 // Set Data Pending bit for address filter 0. + MAFCR1_AACK_0_I_AM_COORD = 0x1 // Enable PAN Coordinator mode for address filter 0. + + // AES_CTRL: AES Control Register + AES_CTRL_AES_REQUEST = 0x80 // Request AES Operation. + AES_CTRL_AES_MODE = 0x20 // Set AES Operation Mode + AES_CTRL_AES_DIR = 0x8 // Set AES Operation Direction + AES_CTRL_AES_IM = 0x4 // AES Interrupt Enable + + // AES_STATUS: AES Status Register + AES_STATUS_AES_ER = 0x80 // AES Operation Finished with Error + AES_STATUS_AES_DONE = 0x1 // AES Operation Finished with Success + + // AES_STATE: AES Plain and Cipher Text Buffer Register + AES_STATE_AES_STATE = 0xff // AES Plain and Cipher Text Buffer + + // AES_KEY: AES Encryption and Decryption Key Buffer Register + AES_KEY_AES_KEY = 0xff // AES Encryption/Decryption Key Buffer + + // TRX_STATUS: Transceiver Status Register + TRX_STATUS_CCA_DONE = 0x80 // CCA Algorithm Status + TRX_STATUS_CCA_STATUS = 0x40 // CCA Status Result + TRX_STATUS_TST_STATUS = 0x20 // Test mode status + TRX_STATUS_TRX_STATUS = 0x1f // Transceiver Main Status + + // TRX_STATE: Transceiver State Control Register + TRX_STATE_TRAC_STATUS = 0xe0 // Transaction Status + TRX_STATE_TRX_CMD = 0x1f // State Control Command + + // TRX_CTRL_0: Reserved + TRX_CTRL_0_Res7 = 0x80 // Reserved + TRX_CTRL_0_PMU_EN = 0x40 // Enable Phase Measurement Unit + TRX_CTRL_0_PMU_START = 0x20 // Start of Phase Measurement Unit + TRX_CTRL_0_PMU_IF_INV = 0x10 // PMU IF Inverse + + // TRX_CTRL_1: Transceiver Control Register 1 + TRX_CTRL_1_PA_EXT_EN = 0x80 // External PA support enable + TRX_CTRL_1_IRQ_2_EXT_EN = 0x40 // Connect Frame Start IRQ to TC1 + TRX_CTRL_1_TX_AUTO_CRC_ON = 0x20 // Enable Automatic CRC Calculation + TRX_CTRL_1_PLL_TX_FLT = 0x10 // Enable PLL TX filter + + // PHY_TX_PWR: Transceiver Transmit Power Control Register + PHY_TX_PWR_TX_PWR = 0xf // Transmit Power Setting + + // PHY_RSSI: Receiver Signal Strength Indicator Register + PHY_RSSI_RX_CRC_VALID = 0x80 // Received Frame CRC Status + PHY_RSSI_RND_VALUE = 0x60 // Random Value + PHY_RSSI_RSSI = 0x1f // Receiver Signal Strength Indicator + + // PHY_ED_LEVEL: Transceiver Energy Detection Level Register + PHY_ED_LEVEL_ED_LEVEL = 0xff // Energy Detection Level + + // PHY_CC_CCA: Transceiver Clear Channel Assessment (CCA) Control Register + PHY_CC_CCA_CCA_REQUEST = 0x80 // Manual CCA Measurement Request + PHY_CC_CCA_CCA_MODE = 0x60 // Select CCA Measurement Mode + PHY_CC_CCA_CHANNEL = 0x1f // RX/TX Channel Selection + + // CCA_THRES: Transceiver CCA Threshold Setting Register + CCA_THRES_CCA_CS_THRES = 0xf0 // CS Threshold Level for CCA Measurement + CCA_THRES_CCA_ED_THRES = 0xf // ED Threshold Level for CCA Measurement + + // RX_CTRL: Transceiver Receive Control Register + RX_CTRL_PDT_THRES = 0xf // Receiver Sensitivity Control + + // SFD_VALUE: Start of Frame Delimiter Value Register + SFD_VALUE_SFD_VALUE = 0xff // Start of Frame Delimiter Value + + // TRX_CTRL_2: Transceiver Control Register 2 + TRX_CTRL_2_RX_SAFE_MODE = 0x80 // RX Safe Mode + TRX_CTRL_2_OQPSK_DATA_RATE = 0x3 // Data Rate Selection + + // ANT_DIV: Antenna Diversity Control Register + ANT_DIV_ANT_SEL = 0x80 // Antenna Diversity Antenna Status + ANT_DIV_ANT_DIV_EN = 0x8 // Enable Antenna Diversity + ANT_DIV_ANT_EXT_SW_EN = 0x4 // Enable External Antenna Switch Control + ANT_DIV_ANT_CTRL = 0x3 // Static Antenna Diversity Switch Control + + // IRQ_MASK: Transceiver Interrupt Enable Register + IRQ_MASK_AWAKE_EN = 0x80 // Awake Interrupt Enable + IRQ_MASK_TX_END_EN = 0x40 // TX_END Interrupt Enable + IRQ_MASK_AMI_EN = 0x20 // Address Match Interrupt Enable + IRQ_MASK_CCA_ED_DONE_EN = 0x10 // End of ED Measurement Interrupt Enable + IRQ_MASK_RX_END_EN = 0x8 // RX_END Interrupt Enable + IRQ_MASK_RX_START_EN = 0x4 // RX_START Interrupt Enable + IRQ_MASK_PLL_UNLOCK_EN = 0x2 // PLL Unlock Interrupt Enable + IRQ_MASK_PLL_LOCK_EN = 0x1 // PLL Lock Interrupt Enable + + // IRQ_STATUS: Transceiver Interrupt Status Register + IRQ_STATUS_AWAKE = 0x80 // Awake Interrupt Status + IRQ_STATUS_TX_END = 0x40 // TX_END Interrupt Status + IRQ_STATUS_AMI = 0x20 // Address Match Interrupt Status + IRQ_STATUS_CCA_ED_DONE = 0x10 // End of ED Measurement Interrupt Status + IRQ_STATUS_RX_END = 0x8 // RX_END Interrupt Status + IRQ_STATUS_RX_START = 0x4 // RX_START Interrupt Status + IRQ_STATUS_PLL_UNLOCK = 0x2 // PLL Unlock Interrupt Status + IRQ_STATUS_PLL_LOCK = 0x1 // PLL Lock Interrupt Status + + // IRQ_MASK1: Transceiver Interrupt Enable Register 1 + IRQ_MASK1_Res = 0xe0 // Reserved Bit + IRQ_MASK1_MAF_3_AMI_EN = 0x10 // Address Match Interrupt enable Address filter 3 + IRQ_MASK1_MAF_2_AMI_EN = 0x8 // Address Match Interrupt enable Address filter 2 + IRQ_MASK1_MAF_1_AMI_EN = 0x4 // Address Match Interrupt enable Address filter 1 + IRQ_MASK1_MAF_0_AMI_EN = 0x2 // Address Match Interrupt enable Address filter 0 + IRQ_MASK1_TX_START_EN = 0x1 // Transmit Start Interrupt enable + + // IRQ_STATUS1: Transceiver Interrupt Status Register 1 + IRQ_STATUS1_Res = 0xe0 // Reserved Bit + IRQ_STATUS1_MAF_3_AMI = 0x10 // Address Match Interrupt Status Address filter 3 + IRQ_STATUS1_MAF_2_AMI = 0x8 // Address Match Interrupt Status Address filter 2 + IRQ_STATUS1_MAF_1_AMI = 0x4 // Address Match Interrupt Status Address filter 1 + IRQ_STATUS1_MAF_0_AMI = 0x2 // Address Match Interrupt Status Address filter 0 + IRQ_STATUS1_TX_START = 0x1 // Transmit Start Interrupt Status + + // VREG_CTRL: Voltage Regulator Control and Status Register + VREG_CTRL_AVREG_EXT = 0x80 // Use External AVDD Regulator + VREG_CTRL_AVDD_OK = 0x40 // AVDD Supply Voltage Valid + VREG_CTRL_DVREG_EXT = 0x8 // Use External DVDD Regulator + VREG_CTRL_DVDD_OK = 0x4 // DVDD Supply Voltage Valid + + // BATMON: Battery Monitor Control and Status Register + BATMON_BAT_LOW = 0x80 // Battery Monitor Interrupt Status + BATMON_BAT_LOW_EN = 0x40 // Battery Monitor Interrupt Enable + BATMON_BATMON_OK = 0x20 // Battery Monitor Status + BATMON_BATMON_HR = 0x10 // Battery Monitor Voltage Range + BATMON_BATMON_VTH = 0xf // Battery Monitor Threshold Voltage + + // XOSC_CTRL: Crystal Oscillator Control Register + XOSC_CTRL_XTAL_MODE = 0xf0 // Crystal Oscillator Operating Mode + XOSC_CTRL_XTAL_TRIM = 0xf // Crystal Oscillator Load Capacitance Trimming + + // CC_CTRL_0: Channel Control Register 0 + CC_CTRL_0_CC_NUMBER = 0xff // Channel Number + + // CC_CTRL_1: Channel Control Register 1 + CC_CTRL_1_CC_BAND = 0xf // Channel Band + + // RX_SYN: Transceiver Receiver Sensitivity Control Register + RX_SYN_RX_PDT_DIS = 0x80 // Prevent Frame Reception + RX_SYN_RX_OVERRIDE = 0x40 // Receiver Override Function + RX_SYN_RX_PDT_LEVEL = 0xf // Reduce Receiver Sensitivity + + // TRX_RPC: Transceiver Reduced Power Consumption Control + TRX_RPC_RX_RPC_CTRL = 0xc0 // Smart Receiving Mode Timing + TRX_RPC_RX_RPC_EN = 0x20 // Reciver Smart Receiving Mode Enable + TRX_RPC_PDT_RPC_EN = 0x10 // Smart Receiving Mode Reduced Sensitivity Enable + TRX_RPC_PLL_RPC_EN = 0x8 // PLL Smart Receiving Mode Enable + TRX_RPC_Res0 = 0x4 // Reserved + TRX_RPC_IPAN_RPC_EN = 0x2 // Smart Receiving Mode IPAN Handling Enable + TRX_RPC_XAH_RPC_EN = 0x1 // Smart Receiving in Extended Operating Modes Enable + + // XAH_CTRL_1: Transceiver Acknowledgment Frame Control Register 1 + XAH_CTRL_1_AACK_FLTR_RES_FT = 0x20 // Filter Reserved Frames + XAH_CTRL_1_AACK_UPLD_RES_FT = 0x10 // Process Reserved Frames + XAH_CTRL_1_AACK_ACK_TIME = 0x4 // Reduce Acknowledgment Time + XAH_CTRL_1_AACK_PROM_MODE = 0x2 // Enable Promiscuous Mode + + // FTN_CTRL: Transceiver Filter Tuning Control Register + FTN_CTRL_FTN_START = 0x80 // Start Calibration Loop of Filter Tuning Network + + // PLL_CF: Transceiver Center Frequency Calibration Control Register + PLL_CF_PLL_CF_START = 0x80 // Start Center Frequency Calibration + + // PLL_DCU: Transceiver Delay Cell Calibration Control Register + PLL_DCU_PLL_DCU_START = 0x80 // Start Delay Cell Calibration + + // PART_NUM: Device Identification Register (Part Number) + PART_NUM_PART_NUM = 0xff // Part Number + + // VERSION_NUM: Device Identification Register (Version Number) + VERSION_NUM_VERSION_NUM = 0xff // Version Number + + // MAN_ID_0: Device Identification Register (Manufacture ID Low Byte) + MAN_ID_0_MAN_ID_07 = 0x80 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_06 = 0x40 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_05 = 0x20 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_04 = 0x10 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_03 = 0x8 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_02 = 0x4 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_01 = 0x2 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_00 = 0x1 // Manufacturer ID (Low Byte) + + // MAN_ID_1: Device Identification Register (Manufacture ID High Byte) + MAN_ID_1_MAN_ID_ = 0xff // Manufacturer ID (High Byte) + + // SHORT_ADDR_0: Transceiver MAC Short Address Register (Low Byte) + SHORT_ADDR_0_SHORT_ADDR_07 = 0x80 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_06 = 0x40 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_05 = 0x20 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_04 = 0x10 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_03 = 0x8 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_02 = 0x4 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_01 = 0x2 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_00 = 0x1 // MAC Short Address + + // SHORT_ADDR_1: Transceiver MAC Short Address Register (High Byte) + SHORT_ADDR_1_SHORT_ADDR_ = 0xff // MAC Short Address + + // PAN_ID_0: Transceiver Personal Area Network ID Register (Low Byte) + PAN_ID_0_PAN_ID_07 = 0x80 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_06 = 0x40 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_05 = 0x20 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_04 = 0x10 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_03 = 0x8 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_02 = 0x4 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_01 = 0x2 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_00 = 0x1 // MAC Personal Area Network ID + + // PAN_ID_1: Transceiver Personal Area Network ID Register (High Byte) + PAN_ID_1_PAN_ID_ = 0xff // MAC Personal Area Network ID + + // IEEE_ADDR_0: Transceiver MAC IEEE Address Register 0 + IEEE_ADDR_0_IEEE_ADDR_07 = 0x80 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_06 = 0x40 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_05 = 0x20 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_04 = 0x10 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_03 = 0x8 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_02 = 0x4 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_01 = 0x2 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_00 = 0x1 // MAC IEEE Address + + // IEEE_ADDR_1: Transceiver MAC IEEE Address Register 1 + IEEE_ADDR_1_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // IEEE_ADDR_2: Transceiver MAC IEEE Address Register 2 + IEEE_ADDR_2_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // IEEE_ADDR_3: Transceiver MAC IEEE Address Register 3 + IEEE_ADDR_3_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // IEEE_ADDR_4: Transceiver MAC IEEE Address Register 4 + IEEE_ADDR_4_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // IEEE_ADDR_5: Transceiver MAC IEEE Address Register 5 + IEEE_ADDR_5_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // IEEE_ADDR_6: Transceiver MAC IEEE Address Register 6 + IEEE_ADDR_6_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // IEEE_ADDR_7: Transceiver MAC IEEE Address Register 7 + IEEE_ADDR_7_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // XAH_CTRL_0: Transceiver Extended Operating Mode Control Register + XAH_CTRL_0_MAX_FRAME_RETRIES = 0xf0 // Maximum Number of Frame Re-transmission Attempts + XAH_CTRL_0_MAX_CSMA_RETRIES = 0xe // Maximum Number of CSMA-CA Procedure Repetition Attempts + XAH_CTRL_0_SLOTTED_OPERATION = 0x1 // Set Slotted Acknowledgment + + // CSMA_SEED_0: Transceiver CSMA-CA Random Number Generator Seed Register + CSMA_SEED_0_CSMA_SEED_07 = 0x80 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_06 = 0x40 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_05 = 0x20 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_04 = 0x10 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_03 = 0x8 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_02 = 0x4 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_01 = 0x2 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_00 = 0x1 // Seed Value for CSMA Random Number Generator + + // CSMA_SEED_1: Transceiver Acknowledgment Frame Control Register 2 + CSMA_SEED_1_AACK_FVN_MODE = 0xc0 // Acknowledgment Frame Filter Mode + CSMA_SEED_1_AACK_SET_PD = 0x20 // Set Frame Pending Sub-field + CSMA_SEED_1_AACK_DIS_ACK = 0x10 // Disable Acknowledgment Frame Transmission + CSMA_SEED_1_AACK_I_AM_COORD = 0x8 // Set Personal Area Network Coordinator + CSMA_SEED_1_CSMA_SEED_1 = 0x7 // Seed Value for CSMA Random Number Generator + + // CSMA_BE: Transceiver CSMA-CA Back-off Exponent Control Register + CSMA_BE_MAX_BE = 0xf0 // Maximum Back-off Exponent + CSMA_BE_MIN_BE = 0xf // Minimum Back-off Exponent + + // TST_CTRL_DIGI: Transceiver Digital Test Control Register + TST_CTRL_DIGI_TST_CTRL_DIG = 0xf // Digital Test Controller Register + + // TST_RX_LENGTH: Transceiver Received Frame Length Register + TST_RX_LENGTH_RX_LENGTH = 0xff // Received Frame Length +) + +// Bitfields for SYMCNT: MAC Symbol Counter +const ( + // SCTSTRHH: Symbol Counter Transmit Frame Timestamp Register HH-Byte + SCTSTRHH_SCTSTRHH = 0xff // Symbol Counter Transmit Frame Timestamp Register HH-Byte + + // SCTSTRHL: Symbol Counter Transmit Frame Timestamp Register HL-Byte + SCTSTRHL_SCTSTRHL = 0xff // Symbol Counter Transmit Frame Timestamp Register HL-Byte + + // SCTSTRLH: Symbol Counter Transmit Frame Timestamp Register LH-Byte + SCTSTRLH_SCTSTRLH = 0xff // Symbol Counter Transmit Frame Timestamp Register LH-Byte + + // SCTSTRLL: Symbol Counter Transmit Frame Timestamp Register LL-Byte + SCTSTRLL_SCTSTRLL = 0xff // Symbol Counter Transmit Frame Timestamp Register LL-Byte + + // SCOCR1HH: Symbol Counter Output Compare Register 1 HH-Byte + SCOCR1HH_SCOCR1HH = 0xff // Symbol Counter Output Compare Register 1 HH-Byte + + // SCOCR1HL: Symbol Counter Output Compare Register 1 HL-Byte + SCOCR1HL_SCOCR1HL = 0xff // Symbol Counter Output Compare Register 1 HL-Byte + + // SCOCR1LH: Symbol Counter Output Compare Register 1 LH-Byte + SCOCR1LH_SCOCR1LH = 0xff // Symbol Counter Output Compare Register 1 LH-Byte + + // SCOCR1LL: Symbol Counter Output Compare Register 1 LL-Byte + SCOCR1LL_SCOCR1LL = 0xff // Symbol Counter Output Compare Register 1 LL-Byte + + // SCOCR2HH: Symbol Counter Output Compare Register 2 HH-Byte + SCOCR2HH_SCOCR2HH = 0xff // Symbol Counter Output Compare Register 2 HH-Byte + + // SCOCR2HL: Symbol Counter Output Compare Register 2 HL-Byte + SCOCR2HL_SCOCR2HL = 0xff // Symbol Counter Output Compare Register 2 HL-Byte + + // SCOCR2LH: Symbol Counter Output Compare Register 2 LH-Byte + SCOCR2LH_SCOCR2LH = 0xff // Symbol Counter Output Compare Register 2 LH-Byte + + // SCOCR2LL: Symbol Counter Output Compare Register 2 LL-Byte + SCOCR2LL_SCOCR2LL = 0xff // Symbol Counter Output Compare Register 2 LL-Byte + + // SCOCR3HH: Symbol Counter Output Compare Register 3 HH-Byte + SCOCR3HH_SCOCR3HH = 0xff // Symbol Counter Output Compare Register 3 HH-Byte + + // SCOCR3HL: Symbol Counter Output Compare Register 3 HL-Byte + SCOCR3HL_SCOCR3HL = 0xff // Symbol Counter Output Compare Register 3 HL-Byte + + // SCOCR3LH: Symbol Counter Output Compare Register 3 LH-Byte + SCOCR3LH_SCOCR3LH = 0xff // Symbol Counter Output Compare Register 3 LH-Byte + + // SCOCR3LL: Symbol Counter Output Compare Register 3 LL-Byte + SCOCR3LL_SCOCR3LL = 0xff // Symbol Counter Output Compare Register 3 LL-Byte + + // SCTSRHH: Symbol Counter Frame Timestamp Register HH-Byte + SCTSRHH_SCTSRHH = 0xff // Symbol Counter Frame Timestamp Register HH-Byte + + // SCTSRHL: Symbol Counter Frame Timestamp Register HL-Byte + SCTSRHL_SCTSRHL = 0xff // Symbol Counter Frame Timestamp Register HL-Byte + + // SCTSRLH: Symbol Counter Frame Timestamp Register LH-Byte + SCTSRLH_SCTSRLH = 0xff // Symbol Counter Frame Timestamp Register LH-Byte + + // SCTSRLL: Symbol Counter Frame Timestamp Register LL-Byte + SCTSRLL_SCTSRLL = 0xff // Symbol Counter Frame Timestamp Register LL-Byte + + // SCBTSRHH: Symbol Counter Beacon Timestamp Register HH-Byte + SCBTSRHH_SCBTSRHH = 0xff // Symbol Counter Beacon Timestamp Register HH-Byte + + // SCBTSRHL: Symbol Counter Beacon Timestamp Register HL-Byte + SCBTSRHL_SCBTSRHL = 0xff // Symbol Counter Beacon Timestamp Register HL-Byte + + // SCBTSRLH: Symbol Counter Beacon Timestamp Register LH-Byte + SCBTSRLH_SCBTSRLH = 0xff // Symbol Counter Beacon Timestamp Register LH-Byte + + // SCBTSRLL: Symbol Counter Beacon Timestamp Register LL-Byte + SCBTSRLL_SCBTSRLL = 0xff // Symbol Counter Beacon Timestamp Register LL-Byte + + // SCCNTHH: Symbol Counter Register HH-Byte + SCCNTHH_SCCNTHH = 0xff // Symbol Counter Register HH-Byte + + // SCCNTHL: Symbol Counter Register HL-Byte + SCCNTHL_SCCNTHL = 0xff // Symbol Counter Register HL-Byte + + // SCCNTLH: Symbol Counter Register LH-Byte + SCCNTLH_SCCNTLH = 0xff // Symbol Counter Register LH-Byte + + // SCCNTLL: Symbol Counter Register LL-Byte + SCCNTLL_SCCNTLL = 0xff // Symbol Counter Register LL-Byte + + // SCIRQS: Symbol Counter Interrupt Status Register + SCIRQS_IRQSBO = 0x10 // Backoff Slot Counter IRQ + SCIRQS_IRQSOF = 0x8 // Symbol Counter Overflow IRQ + SCIRQS_IRQSCP = 0x7 // Compare Unit 3 Compare Match IRQ + + // SCIRQM: Symbol Counter Interrupt Mask Register + SCIRQM_Res = 0xe0 // Reserved Bit + SCIRQM_IRQMBO = 0x10 // Backoff Slot Counter IRQ enable + SCIRQM_IRQMOF = 0x8 // Symbol Counter Overflow IRQ enable + SCIRQM_IRQMCP = 0x7 // Symbol Counter Compare Match 3 IRQ enable + + // SCSR: Symbol Counter Status Register + SCSR_Res = 0xfe // Reserved Bit + SCSR_SCBSY = 0x1 // Symbol Counter busy + + // SCCR1: Symbol Counter Control Register 1 + SCCR1_Res = 0xc0 // Reserved Bit + SCCR1_SCBTSM = 0x20 // Symbol Counter Beacon Timestamp Mask Register + SCCR1_SCCKDIV = 0x1c // Clock divider for synchronous clock source (16MHz Transceiver Clock) + SCCR1_SCEECLK = 0x2 // Enable External Clock Source on PG2 + SCCR1_SCENBO = 0x1 // Backoff Slot Counter enable + + // SCCR0: Symbol Counter Control Register 0 + SCCR0_SCRES = 0x80 // Symbol Counter Synchronization + SCCR0_SCMBTS = 0x40 // Manual Beacon Timestamp + SCCR0_SCEN = 0x20 // Symbol Counter enable + SCCR0_SCCKSEL = 0x10 // Symbol Counter Clock Source select + SCCR0_SCTSE = 0x8 // Symbol Counter Automatic Timestamping enable + SCCR0_SCCMP = 0x7 // Symbol Counter Compare Unit 3 Mode select + + // SCCSR: Symbol Counter Compare Source Register + SCCSR_Res = 0xc0 // Reserved Bit + SCCSR_SCCS3 = 0x30 // Symbol Counter Compare Source select register for Compare Unit 3 + SCCSR_SCCS2 = 0xc // Symbol Counter Compare Source select register for Compare Unit 2 + SCCSR_SCCS1 = 0x3 // Symbol Counter Compare Source select register for Compare Units + + // SCRSTRHH: Symbol Counter Received Frame Timestamp Register HH-Byte + SCRSTRHH_SCRSTRHH = 0xff // Symbol Counter Received Frame Timestamp Register HH-Byte + + // SCRSTRHL: Symbol Counter Received Frame Timestamp Register HL-Byte + SCRSTRHL_SCRSTRHL = 0xff // Symbol Counter Received Frame Timestamp Register HL-Byte + + // SCRSTRLH: Symbol Counter Received Frame Timestamp Register LH-Byte + SCRSTRLH_SCRSTRLH = 0xff // Symbol Counter Received Frame Timestamp Register LH-Byte + + // SCRSTRLL: Symbol Counter Received Frame Timestamp Register LL-Byte + SCRSTRLL_SCRSTRLL = 0xff // Symbol Counter Received Frame Timestamp Register LL-Byte +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Programming Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for JTAG: JTAG Interface +const ( + // OCDR: On-Chip Debug Register + OCDR_OCDR = 0xff // On-Chip Debug Register Data +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC3 = 0xc0 // External Interrupt 3 Sense Control Bit + EICRA_ISC2 = 0x30 // External Interrupt 2 Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt 1 Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt 0 Sense Control Bit + + // EICRB: External Interrupt Control Register B + EICRB_ISC7 = 0xc0 // External Interrupt 7 Sense Control Bit + EICRB_ISC6 = 0x30 // External Interrupt 6 Sense Control Bit + EICRB_ISC5 = 0xc // External Interrupt 5 Sense Control Bit + EICRB_ISC4 = 0x3 // External Interrupt 4 Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xff // External Interrupt Request Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xff // External Interrupt Flag + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Mask + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Enable Mask + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Mask + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_Res = 0xf8 // Reserved Bit + PCIFR_PCIF = 0x7 // Pin Change Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_Res = 0xf8 // Reserved Bit + PCICR_PCIE = 0x7 // Pin Change Interrupt Enables +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC Multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // ADC Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status Register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCSRC: The ADC Control and Status Register C + ADCSRC_ADTHT = 0xc0 // ADC Track-and-Hold Time + ADCSRC_Res0 = 0x20 // Reserved + ADCSRC_ADSUT = 0x1f // ADC Start-up Time + + // DIDR2: Digital Input Disable Register 2 + DIDR2_ADC15D = 0x80 // Reserved Bits + DIDR2_ADC14D = 0x40 // Reserved Bits + DIDR2_ADC13D = 0x20 // Reserved Bits + DIDR2_ADC12D = 0x10 // Reserved Bits + DIDR2_ADC11D = 0x8 // Reserved Bits + DIDR2_ADC10D = 0x4 // Reserved Bits + DIDR2_ADC9D = 0x2 // Reserved Bits + DIDR2_ADC8D = 0x1 // Reserved Bits + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // Disable ADC7:0 Digital Input + DIDR0_ADC6D = 0x40 // Disable ADC7:0 Digital Input + DIDR0_ADC5D = 0x20 // Disable ADC7:0 Digital Input + DIDR0_ADC4D = 0x10 // Disable ADC7:0 Digital Input + DIDR0_ADC3D = 0x8 // Disable ADC7:0 Digital Input + DIDR0_ADC2D = 0x4 // Disable ADC7:0 Digital Input + DIDR0_ADC1D = 0x2 // Disable ADC7:0 Digital Input + DIDR0_ADC0D = 0x1 // Disable ADC7:0 Digital Input +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write Section Read Enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_CAL = 0xff // Oscillator Calibration Tuning Value + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR2: General Purpose I/O Register 2 + GPIOR2_GPIOR = 0xff // General Purpose I/O Register 2 Value + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose I/O Register 1 Value + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR06 = 0x40 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR05 = 0x20 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR04 = 0x10 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR03 = 0x8 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR02 = 0x4 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR01 = 0x2 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR00 = 0x1 // General Purpose I/O Register 0 Value + + // PRR2: Power Reduction Register 2 + PRR2_PRRAM3 = 0x8 // Power Reduction SRAM3 + PRR2_PRRAM2 = 0x4 // Power Reduction SRAM2 + PRR2_PRRAM1 = 0x2 // Power Reduction SRAM1 + PRR2_PRRAM0 = 0x1 // Power Reduction SRAM0 + + // PRR1: Power Reduction Register 1 + PRR1_Res = 0x80 // Reserved Bit + PRR1_PRTRX24 = 0x40 // Power Reduction Transceiver + PRR1_PRTIM5 = 0x20 // Power Reduction Timer/Counter5 + PRR1_PRTIM4 = 0x10 // Power Reduction Timer/Counter4 + PRR1_PRTIM3 = 0x8 // Power Reduction Timer/Counter3 + PRR1_PRUSART1 = 0x1 // Power Reduction USART1 + + // PRR0: Power Reduction Register0 + PRR0_PRTWI = 0x80 // Power Reduction TWI + PRR0_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR0_PRPGA = 0x10 // Power Reduction PGA + PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR0_PRUSART0 = 0x2 // Power Reduction USART + PRR0_PRADC = 0x1 // Power Reduction ADC +) + +// Bitfields for FLASH: FLASH Controller +const ( + // NEMCR: Flash Extended-Mode Control-Register + NEMCR_ENEAM = 0x40 // Enable Extended Address Mode for Extra Rows + NEMCR_AEAM = 0x30 // Address for Extended Address Mode of Extra Rows + + // BGCR: Reference Voltage Calibration Register + BGCR_Res = 0x80 // Reserved Bit + BGCR_BGCAL_FINE = 0x78 // Fine Calibration Bits + BGCR_BGCAL = 0x7 // Coarse Calibration Bits +) + +// Bitfields for PWRCTRL: Power Controller +const ( + // TRXPR: Transceiver Pin Register + TRXPR_SLPTR = 0x2 // Multi-purpose Transceiver Control Bit + TRXPR_TRXRST = 0x1 // Force Transceiver Reset + + // DRTRAM0: Data Retention Configuration Register #0 + DRTRAM0_DRTSWOK = 0x20 // DRT Switch OK + DRTRAM0_ENDRT = 0x10 // Enable SRAM Data Retention + + // DRTRAM1: Data Retention Configuration Register #1 + DRTRAM1_DRTSWOK = 0x20 // DRT Switch OK + DRTRAM1_ENDRT = 0x10 // Enable SRAM Data Retention + + // DRTRAM2: Data Retention Configuration Register #2 + DRTRAM2_Res = 0x40 // Reserved Bit + DRTRAM2_DRTSWOK = 0x20 // DRT Switch OK + DRTRAM2_ENDRT = 0x10 // Enable SRAM Data Retention + + // DRTRAM3: Data Retention Configuration Register #3 + DRTRAM3_DRTSWOK = 0x20 // DRT Switch OK + DRTRAM3_ENDRT = 0x10 // Enable SRAM Data Retention + + // LLDRL: Low Leakage Voltage Regulator Data Register (Low-Byte) + LLDRL_LLDRL = 0xf // Low-Byte Data Register Bits + + // LLDRH: Low Leakage Voltage Regulator Data Register (High-Byte) + LLDRH_LLDRH = 0x1f // High-Byte Data Register Bits + + // LLCR: Low Leakage Voltage Regulator Control Register + LLCR_Res = 0xc0 // Reserved Bit + LLCR_LLDONE = 0x20 // Calibration Done + LLCR_LLCOMP = 0x10 // Comparator Output + LLCR_LLCAL = 0x8 // Calibration Active + LLCR_LLTCO = 0x4 // Temperature Coefficient of Current Source + LLCR_LLSHORT = 0x2 // Short Lower Calibration Circuit + LLCR_LLENCAL = 0x1 // Enable Automatic Calibration + + // DPDS0: Port Driver Strength Register 0 + DPDS0_PFDRV = 0xc0 // Driver Strength Port F + DPDS0_PEDRV = 0x30 // Driver Strength Port E + DPDS0_PDDRV = 0xc // Driver Strength Port D + DPDS0_PBDRV = 0x3 // Driver Strength Port B + + // DPDS1: Port Driver Strength Register 1 + DPDS1_PGDRV = 0x3 // Driver Strength Port G +) diff --git a/src/device/avr/atmega644rfr2.ld b/src/device/avr/atmega644rfr2.ld new file mode 100644 index 00000000..5dcfc801 --- /dev/null +++ b/src/device/avr/atmega644rfr2.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega644RFR2.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_size = 0x2000; +__num_isrs = 71; diff --git a/src/device/avr/atmega645.go b/src/device/avr/atmega645.go new file mode 100644 index 00000000..8ea3a192 --- /dev/null +++ b/src/device/avr/atmega645.go @@ -0,0 +1,599 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega645.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega645 + +// Device information for the ATmega645. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega645" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_PCINT0 = 2 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 3 // Pin Change Interrupt Request 1 + IRQ_TIMER2_COMP = 4 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 5 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 6 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 7 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 8 // Timer/Counter Compare Match B + IRQ_TIMER1_OVF = 9 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 10 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 11 // Timer/Counter0 Overflow + IRQ_SPI_STC = 12 // SPI Serial Transfer Complete + IRQ_USART0_RX = 13 // USART0, Rx Complete + IRQ_USART0_UDRE = 14 // USART0 Data register Empty + IRQ_USART0_TX = 15 // USART0, Tx Complete + IRQ_USI_START = 16 // USI Start Condition + IRQ_USI_OVERFLOW = 17 // USI Overflow + IRQ_ANALOG_COMP = 18 // Analog Comparator + IRQ_ADC = 19 // ADC Conversion Complete + IRQ_EE_READY = 20 // EEPROM Ready + IRQ_SPM_READY = 21 // Store Program Memory Read + IRQ_max = 21 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 0 + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // Universal Serial Interface + USI = struct { + USIDR __reg + USISR __reg + USICR __reg + }{ + USIDR: 0xba, // USI Data Register + USISR: 0xb9, // USI Status Register + USICR: 0xb8, // USI Control Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + PRR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + PRR: 0x64, // Power Reduction Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK1 __reg + PCMSK0 __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access Bytes + EEARH: 0x41, // EEPROM Read/Write Access Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + PORTG: 0x34, // Port G Data Register + DDRG: 0x33, // Port G Data Direction Register + PING: 0x32, // Port G Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0A __reg + TCNT0 __reg + OCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR0A: 0x44, // Timer/Counter0 Control Register + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2A __reg + TCNT2 __reg + OCR2A __reg + TIMSK2 __reg + TIFR2 __reg + ASSR __reg + }{ + TCCR2A: 0xb0, // Timer/Counter2 Control Register + TCNT2: 0xb2, // Timer/Counter2 + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register + TIMSK2: 0x70, // Timer/Counter2 Interrupt Mask register + TIFR2: 0x37, // Timer/Counter2 Interrupt Flag Register + ASSR: 0xb6, // Asynchronous Status Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x60, // Watchdog Timer Control Register + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x6 // Brown-out Detector trigger level + EXTENDED_RSTDISBL = 0x1 // External Reset Disable + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enable + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for USI: Universal Serial Interface +const ( + // USISR: USI Status Register + USISR_USISIF = 0x80 // Start Condition Interrupt Flag + USISR_USIOIF = 0x40 // Counter Overflow Interrupt Flag + USISR_USIPF = 0x20 // Stop Condition Flag + USISR_USIDC = 0x10 // Data Output Collision + USISR_USICNT = 0xf // USI Counter Value Bits + + // USICR: USI Control Register + USICR_USISIE = 0x80 // Start Condition Interrupt Enable + USICR_USIOIE = 0x40 // Counter Overflow Interrupt Enable + USICR_USIWM = 0x30 // USI Wire Mode Bits + USICR_USICS = 0xc // USI Clock Source Select Bits + USICR_USICLK = 0x2 // Clock Strobe + USICR_USITC = 0x1 // Toggle Clock Port Pin +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // PRR: Power Reduction Register + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC01 = 0x2 // External Interrupt Sense Control 0 Bit 1 + EICRA_ISC00 = 0x1 // External Interrupt Sense Control 0 Bit 0 + + // EIMSK: External Interrupt Mask Register + EIMSK_PCIE = 0xf0 // Pin Change Interrupt Enables + EIMSK_INT0 = 0x1 // External Interrupt Request 0 Enable + + // EIFR: External Interrupt Flag Register + EIFR_PCIF = 0xf0 // Pin Change Interrupt Flags + EIFR_INTF0 = 0x1 // External Interrupt Flag 0 +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0A: Timer/Counter0 Control Register + TCCR0A_FOC0A = 0x80 // Force Output Compare + TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0A_COM0A = 0x30 // Compare Match Output Modes + TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0A_CS0 = 0x7 // Clock Selects + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0 + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2A: Timer/Counter2 Control Register + TCCR2A_FOC2A = 0x80 // Force Output Compare A + TCCR2A_WGM20 = 0x40 // Waveform Generation Mode + TCCR2A_COM2A = 0x30 // Compare Output Mode bits + TCCR2A_WGM21 = 0x8 // Waveform Generation Mode + TCCR2A_CS2 = 0x7 // Clock Select bits + + // TIMSK2: Timer/Counter2 Interrupt Mask register + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter2 Interrupt Flag Register + TIFR2_OCF2A = 0x2 // Timer/Counter2 Output Compare Flag 2 + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x10 // Enable External Clock Interrupt + ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmit Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data OverRun + UCSR0A_UPE0 = 0x4 // USART Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART Transmission Speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data Register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0x40 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) diff --git a/src/device/avr/atmega645.ld b/src/device/avr/atmega645.ld new file mode 100644 index 00000000..8e7a4867 --- /dev/null +++ b/src/device/avr/atmega645.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega645.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_size = 0x1000; +__num_isrs = 22; diff --git a/src/device/avr/atmega6450.go b/src/device/avr/atmega6450.go new file mode 100644 index 00000000..776fa279 --- /dev/null +++ b/src/device/avr/atmega6450.go @@ -0,0 +1,618 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega6450.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega6450 + +// Device information for the ATmega6450. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega6450" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_PCINT0 = 2 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 3 // Pin Change Interrupt Request 1 + IRQ_TIMER2_COMP = 4 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 5 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 6 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 7 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 8 // Timer/Counter Compare Match B + IRQ_TIMER1_OVF = 9 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 10 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 11 // Timer/Counter0 Overflow + IRQ_SPI_STC = 12 // SPI Serial Transfer Complete + IRQ_USART_RX = 13 // USART, Rx Complete + IRQ_USART_UDRE = 14 // USART Data register Empty + IRQ_USART0_TX = 15 // USART0, Tx Complete + IRQ_USI_START = 16 // USI Start Condition + IRQ_USI_OVERFLOW = 17 // USI Overflow + IRQ_ANALOG_COMP = 18 // Analog Comparator + IRQ_ADC = 19 // ADC Conversion Complete + IRQ_EE_READY = 20 // EEPROM Ready + IRQ_SPM_READY = 21 // Store Program Memory Read + IRQ_NOT_USED = 22 // RESERVED + IRQ_PCINT2 = 23 // Pin Change Interrupt Request 2 + IRQ_PCINT3 = 24 // Pin Change Interrupt Request 3 + IRQ_max = 24 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 0 + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // Universal Serial Interface + USI = struct { + USIDR __reg + USISR __reg + USICR __reg + }{ + USIDR: 0xba, // USI Data Register + USISR: 0xb9, // USI Status Register + USICR: 0xb8, // USI Control Register + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + PRR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + PRR: 0x64, // Power Reduction Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access Bytes + EEARH: 0x41, // EEPROM Read/Write Access Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + PORTH __reg + DDRH __reg + PINH __reg + PORTJ __reg + DDRJ __reg + PINJ __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + PORTG: 0x34, // Port G Data Register + DDRG: 0x33, // Port G Data Direction Register + PING: 0x32, // Port G Input Pins + PORTH: 0xda, // PORT H Data Register + DDRH: 0xd9, // PORT H Data Direction Register + PINH: 0xd8, // PORT H Input Pins + PORTJ: 0xdd, // PORT J Data Register + DDRJ: 0xdc, // PORT J Data Direction Register + PINJ: 0xdb, // PORT J Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0A __reg + TCNT0 __reg + OCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR0A: 0x44, // Timer/Counter0 Control Register + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2A __reg + TCNT2 __reg + OCR2A __reg + TIMSK2 __reg + TIFR2 __reg + ASSR __reg + }{ + TCCR2A: 0xb0, // Timer/Counter2 Control Register + TCNT2: 0xb2, // Timer/Counter2 + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register + TIMSK2: 0x70, // Timer/Counter2 Interrupt Mask register + TIFR2: 0x37, // Timer/Counter2 Interrupt Flag Register + ASSR: 0xb6, // Asynchronous Status Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x60, // Watchdog Timer Control Register + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK3 __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK3: 0x73, // Pin Change Mask Register 3 + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x6 // Brown-out Detector trigger level + EXTENDED_RSTDISBL = 0x1 // External Reset Disable + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enable + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for USI: Universal Serial Interface +const ( + // USISR: USI Status Register + USISR_USISIF = 0x80 // Start Condition Interrupt Flag + USISR_USIOIF = 0x40 // Counter Overflow Interrupt Flag + USISR_USIPF = 0x20 // Stop Condition Flag + USISR_USIDC = 0x10 // Data Output Collision + USISR_USICNT = 0xf // USI Counter Value Bits + + // USICR: USI Control Register + USICR_USISIE = 0x80 // Start Condition Interrupt Enable + USICR_USIOIE = 0x40 // Counter Overflow Interrupt Enable + USICR_USIWM = 0x30 // USI Wire Mode Bits + USICR_USICS = 0xc // USI Clock Source Select Bits + USICR_USICLK = 0x2 // Clock Strobe + USICR_USITC = 0x1 // Toggle Clock Port Pin +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmit Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data OverRun + UCSR0A_UPE0 = 0x4 // USART Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART Transmission Speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data Register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0x40 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // PRR: Power Reduction Register + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0A: Timer/Counter0 Control Register + TCCR0A_FOC0A = 0x80 // Force Output Compare + TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0A_COM0A = 0x30 // Compare Match Output Modes + TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0A_CS0 = 0x7 // Clock Selects + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0 + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2A: Timer/Counter2 Control Register + TCCR2A_FOC2A = 0x80 // Force Output Compare A + TCCR2A_WGM20 = 0x40 // Waveform Generation Mode + TCCR2A_COM2A = 0x30 // Compare Output Mode bits + TCCR2A_WGM21 = 0x8 // Waveform Generation Mode + TCCR2A_CS2 = 0x7 // Clock Select bits + + // TIMSK2: Timer/Counter2 Interrupt Mask register + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter2 Interrupt Flag Register + TIFR2_OCF2A = 0x2 // Timer/Counter2 Output Compare Flag 2 + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x10 // Enable External Clock Interrupt + ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC01 = 0x2 // External Interrupt Sense Control 0 Bit 1 + EICRA_ISC00 = 0x1 // External Interrupt Sense Control 0 Bit 0 + + // EIMSK: External Interrupt Mask Register + EIMSK_PCIE = 0xf0 // Pin Change Interrupt Enables + EIMSK_INT0 = 0x1 // External Interrupt Request 0 Enable + + // EIFR: External Interrupt Flag Register + EIFR_PCIF = 0xf0 // Pin Change Interrupt Flags + EIFR_INTF0 = 0x1 // External Interrupt Flag 0 +) diff --git a/src/device/avr/atmega6450.ld b/src/device/avr/atmega6450.ld new file mode 100644 index 00000000..2dda1ed1 --- /dev/null +++ b/src/device/avr/atmega6450.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega6450.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_size = 0x1000; +__num_isrs = 25; diff --git a/src/device/avr/atmega6450a.go b/src/device/avr/atmega6450a.go new file mode 100644 index 00000000..ff2987ea --- /dev/null +++ b/src/device/avr/atmega6450a.go @@ -0,0 +1,618 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega6450A.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega6450a + +// Device information for the ATmega6450A. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega6450A" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_PCINT0 = 2 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 3 // Pin Change Interrupt Request 1 + IRQ_TIMER2_COMP = 4 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 5 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 6 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 7 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 8 // Timer/Counter Compare Match B + IRQ_TIMER1_OVF = 9 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 10 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 11 // Timer/Counter0 Overflow + IRQ_SPI_STC = 12 // SPI Serial Transfer Complete + IRQ_USART_RX = 13 // USART, Rx Complete + IRQ_USART_UDRE = 14 // USART Data register Empty + IRQ_USART0_TX = 15 // USART0, Tx Complete + IRQ_USI_START = 16 // USI Start Condition + IRQ_USI_OVERFLOW = 17 // USI Overflow + IRQ_ANALOG_COMP = 18 // Analog Comparator + IRQ_ADC = 19 // ADC Conversion Complete + IRQ_EE_READY = 20 // EEPROM Ready + IRQ_SPM_READY = 21 // Store Program Memory Read + IRQ_NOT_USED = 22 // RESERVED + IRQ_PCINT2 = 23 // Pin Change Interrupt Request 2 + IRQ_PCINT3 = 24 // Pin Change Interrupt Request 3 + IRQ_max = 24 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 0 + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // Universal Serial Interface + USI = struct { + USIDR __reg + USISR __reg + USICR __reg + }{ + USIDR: 0xba, // USI Data Register + USISR: 0xb9, // USI Status Register + USICR: 0xb8, // USI Control Register + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + PRR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + PRR: 0x64, // Power Reduction Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access Bytes + EEARH: 0x41, // EEPROM Read/Write Access Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + PORTH __reg + DDRH __reg + PINH __reg + PORTJ __reg + DDRJ __reg + PINJ __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + PORTG: 0x34, // Port G Data Register + DDRG: 0x33, // Port G Data Direction Register + PING: 0x32, // Port G Input Pins + PORTH: 0xda, // PORT H Data Register + DDRH: 0xd9, // PORT H Data Direction Register + PINH: 0xd8, // PORT H Input Pins + PORTJ: 0xdd, // PORT J Data Register + DDRJ: 0xdc, // PORT J Data Direction Register + PINJ: 0xdb, // PORT J Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0A __reg + TCNT0 __reg + OCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR0A: 0x44, // Timer/Counter0 Control Register + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2A __reg + TCNT2 __reg + OCR2A __reg + TIMSK2 __reg + TIFR2 __reg + ASSR __reg + }{ + TCCR2A: 0xb0, // Timer/Counter2 Control Register + TCNT2: 0xb2, // Timer/Counter2 + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register + TIMSK2: 0x70, // Timer/Counter2 Interrupt Mask register + TIFR2: 0x37, // Timer/Counter2 Interrupt Flag Register + ASSR: 0xb6, // Asynchronous Status Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x60, // Watchdog Timer Control Register + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK3 __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK3: 0x73, // Pin Change Mask Register 3 + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x6 // Brown-out Detector trigger level + EXTENDED_RSTDISBL = 0x1 // External Reset Disable + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enable + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for USI: Universal Serial Interface +const ( + // USISR: USI Status Register + USISR_USISIF = 0x80 // Start Condition Interrupt Flag + USISR_USIOIF = 0x40 // Counter Overflow Interrupt Flag + USISR_USIPF = 0x20 // Stop Condition Flag + USISR_USIDC = 0x10 // Data Output Collision + USISR_USICNT = 0xf // USI Counter Value Bits + + // USICR: USI Control Register + USICR_USISIE = 0x80 // Start Condition Interrupt Enable + USICR_USIOIE = 0x40 // Counter Overflow Interrupt Enable + USICR_USIWM = 0x30 // USI Wire Mode Bits + USICR_USICS = 0xc // USI Clock Source Select Bits + USICR_USICLK = 0x2 // Clock Strobe + USICR_USITC = 0x1 // Toggle Clock Port Pin +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmit Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data OverRun + UCSR0A_UPE0 = 0x4 // USART Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART Transmission Speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data Register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0x40 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // PRR: Power Reduction Register + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0A: Timer/Counter0 Control Register + TCCR0A_FOC0A = 0x80 // Force Output Compare + TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0A_COM0A = 0x30 // Compare Match Output Modes + TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0A_CS0 = 0x7 // Clock Selects + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0 + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2A: Timer/Counter2 Control Register + TCCR2A_FOC2A = 0x80 // Force Output Compare A + TCCR2A_WGM20 = 0x40 // Waveform Generation Mode + TCCR2A_COM2A = 0x30 // Compare Output Mode bits + TCCR2A_WGM21 = 0x8 // Waveform Generation Mode + TCCR2A_CS2 = 0x7 // Clock Select bits + + // TIMSK2: Timer/Counter2 Interrupt Mask register + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter2 Interrupt Flag Register + TIFR2_OCF2A = 0x2 // Timer/Counter2 Output Compare Flag 2 + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x10 // Enable External Clock Interrupt + ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC01 = 0x2 // External Interrupt Sense Control 0 Bit 1 + EICRA_ISC00 = 0x1 // External Interrupt Sense Control 0 Bit 0 + + // EIMSK: External Interrupt Mask Register + EIMSK_PCIE = 0xf0 // Pin Change Interrupt Enables + EIMSK_INT0 = 0x1 // External Interrupt Request 0 Enable + + // EIFR: External Interrupt Flag Register + EIFR_PCIF = 0xf0 // Pin Change Interrupt Flags + EIFR_INTF0 = 0x1 // External Interrupt Flag 0 +) diff --git a/src/device/avr/atmega6450a.ld b/src/device/avr/atmega6450a.ld new file mode 100644 index 00000000..9d0c4944 --- /dev/null +++ b/src/device/avr/atmega6450a.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega6450A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_size = 0x1000; +__num_isrs = 25; diff --git a/src/device/avr/atmega6450p.go b/src/device/avr/atmega6450p.go new file mode 100644 index 00000000..8f895f90 --- /dev/null +++ b/src/device/avr/atmega6450p.go @@ -0,0 +1,618 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega6450P.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega6450p + +// Device information for the ATmega6450P. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega6450P" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_PCINT0 = 2 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 3 // Pin Change Interrupt Request 1 + IRQ_TIMER2_COMP = 4 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 5 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 6 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 7 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 8 // Timer/Counter Compare Match B + IRQ_TIMER1_OVF = 9 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 10 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 11 // Timer/Counter0 Overflow + IRQ_SPI_STC = 12 // SPI Serial Transfer Complete + IRQ_USART_RX = 13 // USART, Rx Complete + IRQ_USART_UDRE = 14 // USART Data register Empty + IRQ_USART0_TX = 15 // USART0, Tx Complete + IRQ_USI_START = 16 // USI Start Condition + IRQ_USI_OVERFLOW = 17 // USI Overflow + IRQ_ANALOG_COMP = 18 // Analog Comparator + IRQ_ADC = 19 // ADC Conversion Complete + IRQ_EE_READY = 20 // EEPROM Ready + IRQ_SPM_READY = 21 // Store Program Memory Read + IRQ_NOT_USED = 22 // RESERVED + IRQ_PCINT2 = 23 // Pin Change Interrupt Request 2 + IRQ_PCINT3 = 24 // Pin Change Interrupt Request 3 + IRQ_max = 24 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 0 + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // Universal Serial Interface + USI = struct { + USIDR __reg + USISR __reg + USICR __reg + }{ + USIDR: 0xba, // USI Data Register + USISR: 0xb9, // USI Status Register + USICR: 0xb8, // USI Control Register + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + PRR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + PRR: 0x64, // Power Reduction Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access Bytes + EEARH: 0x41, // EEPROM Read/Write Access Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + PORTH __reg + DDRH __reg + PINH __reg + PORTJ __reg + DDRJ __reg + PINJ __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + PORTG: 0x34, // Port G Data Register + DDRG: 0x33, // Port G Data Direction Register + PING: 0x32, // Port G Input Pins + PORTH: 0xda, // PORT H Data Register + DDRH: 0xd9, // PORT H Data Direction Register + PINH: 0xd8, // PORT H Input Pins + PORTJ: 0xdd, // PORT J Data Register + DDRJ: 0xdc, // PORT J Data Direction Register + PINJ: 0xdb, // PORT J Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0A __reg + TCNT0 __reg + OCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR0A: 0x44, // Timer/Counter0 Control Register + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2A __reg + TCNT2 __reg + OCR2A __reg + TIMSK2 __reg + TIFR2 __reg + ASSR __reg + }{ + TCCR2A: 0xb0, // Timer/Counter2 Control Register + TCNT2: 0xb2, // Timer/Counter2 + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register + TIMSK2: 0x70, // Timer/Counter2 Interrupt Mask register + TIFR2: 0x37, // Timer/Counter2 Interrupt Flag Register + ASSR: 0xb6, // Asynchronous Status Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x60, // Watchdog Timer Control Register + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK3 __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK3: 0x73, // Pin Change Mask Register 3 + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x6 // Brown-out Detector trigger level + EXTENDED_RSTDISBL = 0x1 // External Reset Disable + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enable + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for USI: Universal Serial Interface +const ( + // USISR: USI Status Register + USISR_USISIF = 0x80 // Start Condition Interrupt Flag + USISR_USIOIF = 0x40 // Counter Overflow Interrupt Flag + USISR_USIPF = 0x20 // Stop Condition Flag + USISR_USIDC = 0x10 // Data Output Collision + USISR_USICNT = 0xf // USI Counter Value Bits + + // USICR: USI Control Register + USICR_USISIE = 0x80 // Start Condition Interrupt Enable + USICR_USIOIE = 0x40 // Counter Overflow Interrupt Enable + USICR_USIWM = 0x30 // USI Wire Mode Bits + USICR_USICS = 0xc // USI Clock Source Select Bits + USICR_USICLK = 0x2 // Clock Strobe + USICR_USITC = 0x1 // Toggle Clock Port Pin +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmit Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data OverRun + UCSR0A_UPE0 = 0x4 // USART Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART Transmission Speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data Register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0x40 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // PRR: Power Reduction Register + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0A: Timer/Counter0 Control Register + TCCR0A_FOC0A = 0x80 // Force Output Compare + TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0A_COM0A = 0x30 // Compare Match Output Modes + TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0A_CS0 = 0x7 // Clock Selects + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0 + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2A: Timer/Counter2 Control Register + TCCR2A_FOC2A = 0x80 // Force Output Compare A + TCCR2A_WGM20 = 0x40 // Waveform Generation Mode + TCCR2A_COM2A = 0x30 // Compare Output Mode bits + TCCR2A_WGM21 = 0x8 // Waveform Generation Mode + TCCR2A_CS2 = 0x7 // Clock Select bits + + // TIMSK2: Timer/Counter2 Interrupt Mask register + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter2 Interrupt Flag Register + TIFR2_OCF2A = 0x2 // Timer/Counter2 Output Compare Flag 2 + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x10 // Enable External Clock Interrupt + ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC01 = 0x2 // External Interrupt Sense Control 0 Bit 1 + EICRA_ISC00 = 0x1 // External Interrupt Sense Control 0 Bit 0 + + // EIMSK: External Interrupt Mask Register + EIMSK_PCIE = 0xf0 // Pin Change Interrupt Enables + EIMSK_INT0 = 0x1 // External Interrupt Request 0 Enable + + // EIFR: External Interrupt Flag Register + EIFR_PCIF = 0xf0 // Pin Change Interrupt Flags + EIFR_INTF0 = 0x1 // External Interrupt Flag 0 +) diff --git a/src/device/avr/atmega6450p.ld b/src/device/avr/atmega6450p.ld new file mode 100644 index 00000000..a1329e52 --- /dev/null +++ b/src/device/avr/atmega6450p.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega6450P.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_size = 0x1000; +__num_isrs = 25; diff --git a/src/device/avr/atmega645a.go b/src/device/avr/atmega645a.go new file mode 100644 index 00000000..49f1712e --- /dev/null +++ b/src/device/avr/atmega645a.go @@ -0,0 +1,600 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega645A.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega645a + +// Device information for the ATmega645A. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega645A" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_PCINT0 = 2 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 3 // Pin Change Interrupt Request 1 + IRQ_TIMER2_COMP = 4 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 5 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 6 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 7 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 8 // Timer/Counter Compare Match B + IRQ_TIMER1_OVF = 9 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 10 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 11 // Timer/Counter0 Overflow + IRQ_SPI_STC = 12 // SPI Serial Transfer Complete + IRQ_USART0_RX = 13 // USART0, Rx Complete + IRQ_USART0_UDRE = 14 // USART0 Data register Empty + IRQ_USART0_TX = 15 // USART0, Tx Complete + IRQ_USI_START = 16 // USI Start Condition + IRQ_USI_OVERFLOW = 17 // USI Overflow + IRQ_ANALOG_COMP = 18 // Analog Comparator + IRQ_ADC = 19 // ADC Conversion Complete + IRQ_EE_READY = 20 // EEPROM Ready + IRQ_SPM_READY = 21 // Store Program Memory Read + IRQ_max = 21 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 0 + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // Universal Serial Interface + USI = struct { + USIDR __reg + USISR __reg + USICR __reg + }{ + USIDR: 0xba, // USI Data Register + USISR: 0xb9, // USI Status Register + USICR: 0xb8, // USI Control Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + PRR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + PRR: 0x64, // Power Reduction Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK1 __reg + PCMSK0 __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access Bytes + EEARH: 0x41, // EEPROM Read/Write Access Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + PORTG: 0x34, // Port G Data Register + DDRG: 0x33, // Port G Data Direction Register + PING: 0x32, // Port G Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0A __reg + TCNT0 __reg + OCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR0A: 0x44, // Timer/Counter0 Control Register + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2A __reg + TCNT2 __reg + OCR2A __reg + TIMSK2 __reg + TIFR2 __reg + ASSR __reg + }{ + TCCR2A: 0xb0, // Timer/Counter2 Control Register + TCNT2: 0xb2, // Timer/Counter2 + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register + TIMSK2: 0x70, // Timer/Counter2 Interrupt Mask register + TIFR2: 0x37, // Timer/Counter2 Interrupt Flag Register + ASSR: 0xb6, // Asynchronous Status Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x60, // Watchdog Timer Control Register + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x6 // Brown-out Detector trigger level + EXTENDED_RSTDISBL = 0x1 // External Reset Disable + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enable + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for USI: Universal Serial Interface +const ( + // USISR: USI Status Register + USISR_USISIF = 0x80 // Start Condition Interrupt Flag + USISR_USIOIF = 0x40 // Counter Overflow Interrupt Flag + USISR_USIPF = 0x20 // Stop Condition Flag + USISR_USIDC = 0x10 // Data Output Collision + USISR_USICNT = 0xf // USI Counter Value Bits + + // USICR: USI Control Register + USICR_USISIE = 0x80 // Start Condition Interrupt Enable + USICR_USIOIE = 0x40 // Counter Overflow Interrupt Enable + USICR_USIWM = 0x30 // USI Wire Mode Bits + USICR_USICS = 0xc // USI Clock Source Select Bits + USICR_USICLK = 0x2 // Clock Strobe + USICR_USITC = 0x1 // Toggle Clock Port Pin +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // PRR: Power Reduction Register + PRR_PRLCD = 0x10 // Power Reduction LCD + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC01 = 0x2 // External Interrupt Sense Control 0 Bit 1 + EICRA_ISC00 = 0x1 // External Interrupt Sense Control 0 Bit 0 + + // EIMSK: External Interrupt Mask Register + EIMSK_PCIE = 0xf0 // Pin Change Interrupt Enables + EIMSK_INT0 = 0x1 // External Interrupt Request 0 Enable + + // EIFR: External Interrupt Flag Register + EIFR_PCIF = 0xf0 // Pin Change Interrupt Flags + EIFR_INTF0 = 0x1 // External Interrupt Flag 0 +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0A: Timer/Counter0 Control Register + TCCR0A_FOC0A = 0x80 // Force Output Compare + TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0A_COM0A = 0x30 // Compare Match Output Modes + TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0A_CS0 = 0x7 // Clock Selects + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0 + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2A: Timer/Counter2 Control Register + TCCR2A_FOC2A = 0x80 // Force Output Compare A + TCCR2A_WGM20 = 0x40 // Waveform Generation Mode + TCCR2A_COM2A = 0x30 // Compare Output Mode bits + TCCR2A_WGM21 = 0x8 // Waveform Generation Mode + TCCR2A_CS2 = 0x7 // Clock Select bits + + // TIMSK2: Timer/Counter2 Interrupt Mask register + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter2 Interrupt Flag Register + TIFR2_OCF2A = 0x2 // Timer/Counter2 Output Compare Flag 2 + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x10 // Enable External Clock Interrupt + ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmit Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data OverRun + UCSR0A_UPE0 = 0x4 // USART Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART Transmission Speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data Register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0x40 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) diff --git a/src/device/avr/atmega645a.ld b/src/device/avr/atmega645a.ld new file mode 100644 index 00000000..7695e59c --- /dev/null +++ b/src/device/avr/atmega645a.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega645A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_size = 0x1000; +__num_isrs = 22; diff --git a/src/device/avr/atmega645p.go b/src/device/avr/atmega645p.go new file mode 100644 index 00000000..65551ec7 --- /dev/null +++ b/src/device/avr/atmega645p.go @@ -0,0 +1,600 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega645P.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega645p + +// Device information for the ATmega645P. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega645P" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_PCINT0 = 2 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 3 // Pin Change Interrupt Request 1 + IRQ_TIMER2_COMP = 4 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 5 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 6 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 7 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 8 // Timer/Counter Compare Match B + IRQ_TIMER1_OVF = 9 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 10 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 11 // Timer/Counter0 Overflow + IRQ_SPI_STC = 12 // SPI Serial Transfer Complete + IRQ_USART0_RX = 13 // USART0, Rx Complete + IRQ_USART0_UDRE = 14 // USART0 Data register Empty + IRQ_USART0_TX = 15 // USART0, Tx Complete + IRQ_USI_START = 16 // USI Start Condition + IRQ_USI_OVERFLOW = 17 // USI Overflow + IRQ_ANALOG_COMP = 18 // Analog Comparator + IRQ_ADC = 19 // ADC Conversion Complete + IRQ_EE_READY = 20 // EEPROM Ready + IRQ_SPM_READY = 21 // Store Program Memory Read + IRQ_max = 21 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 0 + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // Universal Serial Interface + USI = struct { + USIDR __reg + USISR __reg + USICR __reg + }{ + USIDR: 0xba, // USI Data Register + USISR: 0xb9, // USI Status Register + USICR: 0xb8, // USI Control Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + PRR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + PRR: 0x64, // Power Reduction Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK1 __reg + PCMSK0 __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access Bytes + EEARH: 0x41, // EEPROM Read/Write Access Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + PORTG: 0x34, // Port G Data Register + DDRG: 0x33, // Port G Data Direction Register + PING: 0x32, // Port G Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0A __reg + TCNT0 __reg + OCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR0A: 0x44, // Timer/Counter0 Control Register + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2A __reg + TCNT2 __reg + OCR2A __reg + TIMSK2 __reg + TIFR2 __reg + ASSR __reg + }{ + TCCR2A: 0xb0, // Timer/Counter2 Control Register + TCNT2: 0xb2, // Timer/Counter2 + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register + TIMSK2: 0x70, // Timer/Counter2 Interrupt Mask register + TIFR2: 0x37, // Timer/Counter2 Interrupt Flag Register + ASSR: 0xb6, // Asynchronous Status Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x60, // Watchdog Timer Control Register + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x6 // Brown-out Detector trigger level + EXTENDED_RSTDISBL = 0x1 // External Reset Disable + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enable + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for USI: Universal Serial Interface +const ( + // USISR: USI Status Register + USISR_USISIF = 0x80 // Start Condition Interrupt Flag + USISR_USIOIF = 0x40 // Counter Overflow Interrupt Flag + USISR_USIPF = 0x20 // Stop Condition Flag + USISR_USIDC = 0x10 // Data Output Collision + USISR_USICNT = 0xf // USI Counter Value Bits + + // USICR: USI Control Register + USICR_USISIE = 0x80 // Start Condition Interrupt Enable + USICR_USIOIE = 0x40 // Counter Overflow Interrupt Enable + USICR_USIWM = 0x30 // USI Wire Mode Bits + USICR_USICS = 0xc // USI Clock Source Select Bits + USICR_USICLK = 0x2 // Clock Strobe + USICR_USITC = 0x1 // Toggle Clock Port Pin +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // PRR: Power Reduction Register + PRR_PRLCD = 0x10 // Power Reduction LCD + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC01 = 0x2 // External Interrupt Sense Control 0 Bit 1 + EICRA_ISC00 = 0x1 // External Interrupt Sense Control 0 Bit 0 + + // EIMSK: External Interrupt Mask Register + EIMSK_PCIE = 0xf0 // Pin Change Interrupt Enables + EIMSK_INT0 = 0x1 // External Interrupt Request 0 Enable + + // EIFR: External Interrupt Flag Register + EIFR_PCIF = 0xf0 // Pin Change Interrupt Flags + EIFR_INTF0 = 0x1 // External Interrupt Flag 0 +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0A: Timer/Counter0 Control Register + TCCR0A_FOC0A = 0x80 // Force Output Compare + TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0A_COM0A = 0x30 // Compare Match Output Modes + TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0A_CS0 = 0x7 // Clock Selects + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0 + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2A: Timer/Counter2 Control Register + TCCR2A_FOC2A = 0x80 // Force Output Compare A + TCCR2A_WGM20 = 0x40 // Waveform Generation Mode + TCCR2A_COM2A = 0x30 // Compare Output Mode bits + TCCR2A_WGM21 = 0x8 // Waveform Generation Mode + TCCR2A_CS2 = 0x7 // Clock Select bits + + // TIMSK2: Timer/Counter2 Interrupt Mask register + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter2 Interrupt Flag Register + TIFR2_OCF2A = 0x2 // Timer/Counter2 Output Compare Flag 2 + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x10 // Enable External Clock Interrupt + ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmit Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data OverRun + UCSR0A_UPE0 = 0x4 // USART Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART Transmission Speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data Register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0x40 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) diff --git a/src/device/avr/atmega645p.ld b/src/device/avr/atmega645p.ld new file mode 100644 index 00000000..9c46b680 --- /dev/null +++ b/src/device/avr/atmega645p.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega645P.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_size = 0x1000; +__num_isrs = 22; diff --git a/src/device/avr/atmega649.go b/src/device/avr/atmega649.go new file mode 100644 index 00000000..36e6ebe3 --- /dev/null +++ b/src/device/avr/atmega649.go @@ -0,0 +1,666 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega649.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega649 + +// Device information for the ATmega649. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega649" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_PCINT0 = 2 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 3 // Pin Change Interrupt Request 1 + IRQ_TIMER2_COMP = 4 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 5 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 6 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 7 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 8 // Timer/Counter Compare Match B + IRQ_TIMER1_OVF = 9 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 10 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 11 // Timer/Counter0 Overflow + IRQ_SPI_STC = 12 // SPI Serial Transfer Complete + IRQ_USART0_RX = 13 // USART0, Rx Complete + IRQ_USART0_UDRE = 14 // USART0 Data register Empty + IRQ_USART0_TX = 15 // USART0, Tx Complete + IRQ_USI_START = 16 // USI Start Condition + IRQ_USI_OVERFLOW = 17 // USI Overflow + IRQ_ANALOG_COMP = 18 // Analog Comparator + IRQ_ADC = 19 // ADC Conversion Complete + IRQ_EE_READY = 20 // EEPROM Ready + IRQ_SPM_READY = 21 // Store Program Memory Read + IRQ_LCD = 22 // LCD Start of Frame + IRQ_max = 22 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 0 + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // Universal Serial Interface + USI = struct { + USIDR __reg + USISR __reg + USICR __reg + }{ + USIDR: 0xba, // USI Data Register + USISR: 0xb9, // USI Status Register + USICR: 0xb8, // USI Control Register + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + PRR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + PRR: 0x64, // Power Reduction Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // Liquid Crystal Display + LCD = struct { + LCDDR18 __reg + LCDDR17 __reg + LCDDR16 __reg + LCDDR15 __reg + LCDDR13 __reg + LCDDR12 __reg + LCDDR11 __reg + LCDDR10 __reg + LCDDR8 __reg + LCDDR7 __reg + LCDDR6 __reg + LCDDR5 __reg + LCDDR3 __reg + LCDDR2 __reg + LCDDR1 __reg + LCDDR0 __reg + LCDCCR __reg + LCDFRR __reg + LCDCRB __reg + LCDCRA __reg + }{ + LCDDR18: 0xfe, // LCD Data Register 18 + LCDDR17: 0xfd, // LCD Data Register 17 + LCDDR16: 0xfc, // LCD Data Register 16 + LCDDR15: 0xfb, // LCD Data Register 15 + LCDDR13: 0xf9, // LCD Data Register 13 + LCDDR12: 0xf8, // LCD Data Register 12 + LCDDR11: 0xf7, // LCD Data Register 11 + LCDDR10: 0xf6, // LCD Data Register 10 + LCDDR8: 0xf4, // LCD Data Register 8 + LCDDR7: 0xf3, // LCD Data Register 7 + LCDDR6: 0xf2, // LCD Data Register 6 + LCDDR5: 0xf1, // LCD Data Register 5 + LCDDR3: 0xef, // LCD Data Register 3 + LCDDR2: 0xee, // LCD Data Register 2 + LCDDR1: 0xed, // LCD Data Register 1 + LCDDR0: 0xec, // LCD Data Register 0 + LCDCCR: 0xe7, // LCD Contrast Control Register + LCDFRR: 0xe6, // LCD Frame Rate Register + LCDCRB: 0xe5, // LCD Control and Status Register B + LCDCRA: 0xe4, // LCD Control Register A + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK1 __reg + PCMSK0 __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access Bytes + EEARH: 0x41, // EEPROM Read/Write Access Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + PORTG: 0x34, // Port G Data Register + DDRG: 0x33, // Port G Data Direction Register + PING: 0x32, // Port G Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0A __reg + TCNT0 __reg + OCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR0A: 0x44, // Timer/Counter0 Control Register + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2A __reg + TCNT2 __reg + OCR2A __reg + TIMSK2 __reg + TIFR2 __reg + ASSR __reg + }{ + TCCR2A: 0xb0, // Timer/Counter2 Control Register + TCNT2: 0xb2, // Timer/Counter2 + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register + TIMSK2: 0x70, // Timer/Counter2 Interrupt Mask register + TIFR2: 0x37, // Timer/Counter2 Interrupt Flag Register + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x60, // Watchdog Timer Control Register + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x6 // Brown-out Detector trigger level + EXTENDED_RSTDISBL = 0x1 // External Reset Disable + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enable + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for USI: Universal Serial Interface +const ( + // USISR: USI Status Register + USISR_USISIF = 0x80 // Start Condition Interrupt Flag + USISR_USIOIF = 0x40 // Counter Overflow Interrupt Flag + USISR_USIPF = 0x20 // Stop Condition Flag + USISR_USIDC = 0x10 // Data Output Collision + USISR_USICNT = 0xf // USI Counter Value Bits + + // USICR: USI Control Register + USICR_USISIE = 0x80 // Start Condition Interrupt Enable + USICR_USIOIE = 0x40 // Counter Overflow Interrupt Enable + USICR_USIWM = 0x30 // USI Wire Mode Bits + USICR_USICS = 0xc // USI Clock Source Select Bits + USICR_USICLK = 0x2 // Clock Strobe + USICR_USITC = 0x1 // Toggle Clock Port Pin +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmit Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data OverRun + UCSR0A_UPE0 = 0x4 // USART Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART Transmission Speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data Register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0x40 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // PRR: Power Reduction Register + PRR_PRLCD = 0x10 // Power Reduction LCD + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable +) + +// Bitfields for LCD: Liquid Crystal Display +const ( + // LCDFRR: LCD Frame Rate Register + LCDFRR_LCDPS = 0x70 // LCD Prescaler Selects + LCDFRR_LCDCD = 0x7 // LCD Clock Dividers + + // LCDCRB: LCD Control and Status Register B + LCDCRB_LCDCS = 0x80 // LCD CLock Select + LCDCRB_LCD2B = 0x40 // LCD 1/2 Bias Select + LCDCRB_LCDMUX = 0x30 // LCD Mux Selects + LCDCRB_LCDPM = 0xf // LCD Port Masks + + // LCDCRA: LCD Control Register A + LCDCRA_LCDEN = 0x80 // LCD Enable + LCDCRA_LCDAB = 0x40 // LCD A or B waveform + LCDCRA_LCDIF = 0x10 // LCD Interrupt Flag + LCDCRA_LCDIE = 0x8 // LCD Interrupt Enable + LCDCRA_LCDBL = 0x1 // LCD Blanking +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC01 = 0x2 // External Interrupt Sense Control 0 Bit 1 + EICRA_ISC00 = 0x1 // External Interrupt Sense Control 0 Bit 0 + + // EIMSK: External Interrupt Mask Register + EIMSK_PCIE = 0xf0 // Pin Change Interrupt Enables + EIMSK_INT0 = 0x1 // External Interrupt Request 0 Enable + + // EIFR: External Interrupt Flag Register + EIFR_PCIF = 0xf0 // Pin Change Interrupt Flags + EIFR_INTF0 = 0x1 // External Interrupt Flag 0 +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0A: Timer/Counter0 Control Register + TCCR0A_FOC0A = 0x80 // Force Output Compare + TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0A_COM0A = 0x30 // Compare Match Output Modes + TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0A_CS0 = 0x7 // Clock Selects + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0 + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2A: Timer/Counter2 Control Register + TCCR2A_FOC2A = 0x80 // Force Output Compare A + TCCR2A_WGM20 = 0x40 // Waveform Generation Mode + TCCR2A_COM2A = 0x30 // Compare Output Mode bits + TCCR2A_WGM21 = 0x8 // Waveform Generation Mode + TCCR2A_CS2 = 0x7 // Clock Select bits + + // TIMSK2: Timer/Counter2 Interrupt Mask register + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter2 Interrupt Flag Register + TIFR2_OCF2A = 0x2 // Timer/Counter2 Output Compare Flag 2 + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x10 // Enable External Clock Interrupt + ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) diff --git a/src/device/avr/atmega649.ld b/src/device/avr/atmega649.ld new file mode 100644 index 00000000..989b5a9b --- /dev/null +++ b/src/device/avr/atmega649.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega649.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_size = 0x1000; +__num_isrs = 23; diff --git a/src/device/avr/atmega6490.go b/src/device/avr/atmega6490.go new file mode 100644 index 00000000..30982cee --- /dev/null +++ b/src/device/avr/atmega6490.go @@ -0,0 +1,692 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega6490.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega6490 + +// Device information for the ATmega6490. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega6490" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_PCINT0 = 2 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 3 // Pin Change Interrupt Request 1 + IRQ_TIMER2_COMP = 4 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 5 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 6 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 7 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 8 // Timer/Counter Compare Match B + IRQ_TIMER1_OVF = 9 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 10 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 11 // Timer/Counter0 Overflow + IRQ_SPI_STC = 12 // SPI Serial Transfer Complete + IRQ_USART_RX = 13 // USART, Rx Complete + IRQ_USART_UDRE = 14 // USART Data register Empty + IRQ_USART0_TX = 15 // USART0, Tx Complete + IRQ_USI_START = 16 // USI Start Condition + IRQ_USI_OVERFLOW = 17 // USI Overflow + IRQ_ANALOG_COMP = 18 // Analog Comparator + IRQ_ADC = 19 // ADC Conversion Complete + IRQ_EE_READY = 20 // EEPROM Ready + IRQ_SPM_READY = 21 // Store Program Memory Read + IRQ_LCD = 22 // LCD Start of Frame + IRQ_PCINT2 = 23 // Pin Change Interrupt Request 2 + IRQ_PCINT3 = 24 // Pin Change Interrupt Request 3 + IRQ_max = 24 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 0 + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // Universal Serial Interface + USI = struct { + USIDR __reg + USISR __reg + USICR __reg + }{ + USIDR: 0xba, // USI Data Register + USISR: 0xb9, // USI Status Register + USICR: 0xb8, // USI Control Register + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + PRR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + PRR: 0x64, // Power Reduction Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access Bytes + EEARH: 0x41, // EEPROM Read/Write Access Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + PORTH __reg + DDRH __reg + PINH __reg + PORTJ __reg + DDRJ __reg + PINJ __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + PORTG: 0x34, // Port G Data Register + DDRG: 0x33, // Port G Data Direction Register + PING: 0x32, // Port G Input Pins + PORTH: 0xda, // PORT H Data Register + DDRH: 0xd9, // PORT H Data Direction Register + PINH: 0xd8, // PORT H Input Pins + PORTJ: 0xdd, // PORT J Data Register + DDRJ: 0xdc, // PORT J Data Direction Register + PINJ: 0xdb, // PORT J Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0A __reg + TCNT0 __reg + OCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR0A: 0x44, // Timer/Counter0 Control Register + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2A __reg + TCNT2 __reg + OCR2A __reg + TIMSK2 __reg + TIFR2 __reg + ASSR __reg + }{ + TCCR2A: 0xb0, // Timer/Counter2 Control Register + TCNT2: 0xb2, // Timer/Counter2 + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register + TIMSK2: 0x70, // Timer/Counter2 Interrupt Mask register + TIFR2: 0x37, // Timer/Counter2 Interrupt Flag Register + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x60, // Watchdog Timer Control Register + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // Liquid Crystal Display + LCD = struct { + LCDDR19 __reg + LCDDR18 __reg + LCDDR17 __reg + LCDDR16 __reg + LCDDR15 __reg + LCDDR14 __reg + LCDDR13 __reg + LCDDR12 __reg + LCDDR11 __reg + LCDDR10 __reg + LCDDR9 __reg + LCDDR8 __reg + LCDDR7 __reg + LCDDR6 __reg + LCDDR5 __reg + LCDDR4 __reg + LCDDR3 __reg + LCDDR2 __reg + LCDDR1 __reg + LCDDR0 __reg + LCDCCR __reg + LCDFRR __reg + LCDCRB __reg + LCDCRA __reg + }{ + LCDDR19: 0xff, // LCD Data Register 19 + LCDDR18: 0xfe, // LCD Data Register 18 + LCDDR17: 0xfd, // LCD Data Register 17 + LCDDR16: 0xfc, // LCD Data Register 16 + LCDDR15: 0xfb, // LCD Data Register 15 + LCDDR14: 0xfa, // LCD Data Register 14 + LCDDR13: 0xf9, // LCD Data Register 13 + LCDDR12: 0xf8, // LCD Data Register 12 + LCDDR11: 0xf7, // LCD Data Register 11 + LCDDR10: 0xf6, // LCD Data Register 10 + LCDDR9: 0xf5, // LCD Data Register 9 + LCDDR8: 0xf4, // LCD Data Register 8 + LCDDR7: 0xf3, // LCD Data Register 7 + LCDDR6: 0xf2, // LCD Data Register 6 + LCDDR5: 0xf1, // LCD Data Register 5 + LCDDR4: 0xf0, // LCD Data Register 4 + LCDDR3: 0xef, // LCD Data Register 3 + LCDDR2: 0xee, // LCD Data Register 2 + LCDDR1: 0xed, // LCD Data Register 1 + LCDDR0: 0xec, // LCD Data Register 0 + LCDCCR: 0xe7, // LCD Contrast Control Register + LCDFRR: 0xe6, // LCD Frame Rate Register + LCDCRB: 0xe5, // LCD Control and Status Register B + LCDCRA: 0xe4, // LCD Control and Status Register A + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK3 __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK3: 0x73, // Pin Change Mask Register 3 + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x6 // Brown-out Detector trigger level + EXTENDED_RSTDISBL = 0x1 // External Reset Disable + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enable + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for USI: Universal Serial Interface +const ( + // USISR: USI Status Register + USISR_USISIF = 0x80 // Start Condition Interrupt Flag + USISR_USIOIF = 0x40 // Counter Overflow Interrupt Flag + USISR_USIPF = 0x20 // Stop Condition Flag + USISR_USIDC = 0x10 // Data Output Collision + USISR_USICNT = 0xf // USI Counter Value Bits + + // USICR: USI Control Register + USICR_USISIE = 0x80 // Start Condition Interrupt Enable + USICR_USIOIE = 0x40 // Counter Overflow Interrupt Enable + USICR_USIWM = 0x30 // USI Wire Mode Bits + USICR_USICS = 0xc // USI Clock Source Select Bits + USICR_USICLK = 0x2 // Clock Strobe + USICR_USITC = 0x1 // Toggle Clock Port Pin +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmit Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data OverRun + UCSR0A_UPE0 = 0x4 // USART Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART Transmission Speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data Register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0x40 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // PRR: Power Reduction Register + PRR_PRLCD = 0x10 // Power Reduction LCD + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0A: Timer/Counter0 Control Register + TCCR0A_FOC0A = 0x80 // Force Output Compare + TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0A_COM0A = 0x30 // Compare Match Output Modes + TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0A_CS0 = 0x7 // Clock Selects + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0 + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2A: Timer/Counter2 Control Register + TCCR2A_FOC2A = 0x80 // Force Output Compare A + TCCR2A_WGM20 = 0x40 // Waveform Generation Mode + TCCR2A_COM2A = 0x30 // Compare Output Mode bits + TCCR2A_WGM21 = 0x8 // Waveform Generation Mode + TCCR2A_CS2 = 0x7 // Clock Select bits + + // TIMSK2: Timer/Counter2 Interrupt Mask register + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter2 Interrupt Flag Register + TIFR2_OCF2A = 0x2 // Timer/Counter2 Output Compare Flag 2 + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x10 // Enable External Clock Interrupt + ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for LCD: Liquid Crystal Display +const ( + // LCDFRR: LCD Frame Rate Register + LCDFRR_LCDPS = 0x70 // LCD Prescaler Selects + LCDFRR_LCDCD = 0x7 // LCD Clock Dividers + + // LCDCRB: LCD Control and Status Register B + LCDCRB_LCDCS = 0x80 // LCD CLock Select + LCDCRB_LCD2B = 0x40 // LCD 1/2 Bias Select + LCDCRB_LCDMUX = 0x30 // LCD Mux Selects + LCDCRB_LCDPM = 0xf // LCD Port Masks + + // LCDCRA: LCD Control and Status Register A + LCDCRA_LCDEN = 0x80 // LCD Enable + LCDCRA_LCDAB = 0x40 // LCD A or B waveform + LCDCRA_LCDIF = 0x10 // LCD Interrupt Flag + LCDCRA_LCDIE = 0x8 // LCD Interrupt Enable + LCDCRA_LCDBL = 0x1 // LCD Blanking +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC01 = 0x2 // External Interrupt Sense Control 0 Bit 1 + EICRA_ISC00 = 0x1 // External Interrupt Sense Control 0 Bit 0 + + // EIMSK: External Interrupt Mask Register + EIMSK_PCIE = 0xf0 // Pin Change Interrupt Enables + EIMSK_INT0 = 0x1 // External Interrupt Request 0 Enable + + // EIFR: External Interrupt Flag Register + EIFR_PCIF = 0xf0 // Pin Change Interrupt Flags + EIFR_INTF0 = 0x1 // External Interrupt Flag 0 +) diff --git a/src/device/avr/atmega6490.ld b/src/device/avr/atmega6490.ld new file mode 100644 index 00000000..6cf0ce90 --- /dev/null +++ b/src/device/avr/atmega6490.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega6490.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_size = 0x1000; +__num_isrs = 25; diff --git a/src/device/avr/atmega6490a.go b/src/device/avr/atmega6490a.go new file mode 100644 index 00000000..685f26b1 --- /dev/null +++ b/src/device/avr/atmega6490a.go @@ -0,0 +1,692 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega6490A.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega6490a + +// Device information for the ATmega6490A. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega6490A" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_PCINT0 = 2 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 3 // Pin Change Interrupt Request 1 + IRQ_TIMER2_COMP = 4 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 5 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 6 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 7 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 8 // Timer/Counter Compare Match B + IRQ_TIMER1_OVF = 9 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 10 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 11 // Timer/Counter0 Overflow + IRQ_SPI_STC = 12 // SPI Serial Transfer Complete + IRQ_USART_RX = 13 // USART, Rx Complete + IRQ_USART_UDRE = 14 // USART Data register Empty + IRQ_USART0_TX = 15 // USART0, Tx Complete + IRQ_USI_START = 16 // USI Start Condition + IRQ_USI_OVERFLOW = 17 // USI Overflow + IRQ_ANALOG_COMP = 18 // Analog Comparator + IRQ_ADC = 19 // ADC Conversion Complete + IRQ_EE_READY = 20 // EEPROM Ready + IRQ_SPM_READY = 21 // Store Program Memory Read + IRQ_LCD = 22 // LCD Start of Frame + IRQ_PCINT2 = 23 // Pin Change Interrupt Request 2 + IRQ_PCINT3 = 24 // Pin Change Interrupt Request 3 + IRQ_max = 24 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 0 + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // Universal Serial Interface + USI = struct { + USIDR __reg + USISR __reg + USICR __reg + }{ + USIDR: 0xba, // USI Data Register + USISR: 0xb9, // USI Status Register + USICR: 0xb8, // USI Control Register + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + PRR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + PRR: 0x64, // Power Reduction Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access Bytes + EEARH: 0x41, // EEPROM Read/Write Access Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + PORTH __reg + DDRH __reg + PINH __reg + PORTJ __reg + DDRJ __reg + PINJ __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + PORTG: 0x34, // Port G Data Register + DDRG: 0x33, // Port G Data Direction Register + PING: 0x32, // Port G Input Pins + PORTH: 0xda, // PORT H Data Register + DDRH: 0xd9, // PORT H Data Direction Register + PINH: 0xd8, // PORT H Input Pins + PORTJ: 0xdd, // PORT J Data Register + DDRJ: 0xdc, // PORT J Data Direction Register + PINJ: 0xdb, // PORT J Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0A __reg + TCNT0 __reg + OCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR0A: 0x44, // Timer/Counter0 Control Register + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2A __reg + TCNT2 __reg + OCR2A __reg + TIMSK2 __reg + TIFR2 __reg + ASSR __reg + }{ + TCCR2A: 0xb0, // Timer/Counter2 Control Register + TCNT2: 0xb2, // Timer/Counter2 + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register + TIMSK2: 0x70, // Timer/Counter2 Interrupt Mask register + TIFR2: 0x37, // Timer/Counter2 Interrupt Flag Register + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x60, // Watchdog Timer Control Register + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // Liquid Crystal Display + LCD = struct { + LCDDR19 __reg + LCDDR18 __reg + LCDDR17 __reg + LCDDR16 __reg + LCDDR15 __reg + LCDDR14 __reg + LCDDR13 __reg + LCDDR12 __reg + LCDDR11 __reg + LCDDR10 __reg + LCDDR9 __reg + LCDDR8 __reg + LCDDR7 __reg + LCDDR6 __reg + LCDDR5 __reg + LCDDR4 __reg + LCDDR3 __reg + LCDDR2 __reg + LCDDR1 __reg + LCDDR0 __reg + LCDCCR __reg + LCDFRR __reg + LCDCRB __reg + LCDCRA __reg + }{ + LCDDR19: 0xff, // LCD Data Register 19 + LCDDR18: 0xfe, // LCD Data Register 18 + LCDDR17: 0xfd, // LCD Data Register 17 + LCDDR16: 0xfc, // LCD Data Register 16 + LCDDR15: 0xfb, // LCD Data Register 15 + LCDDR14: 0xfa, // LCD Data Register 14 + LCDDR13: 0xf9, // LCD Data Register 13 + LCDDR12: 0xf8, // LCD Data Register 12 + LCDDR11: 0xf7, // LCD Data Register 11 + LCDDR10: 0xf6, // LCD Data Register 10 + LCDDR9: 0xf5, // LCD Data Register 9 + LCDDR8: 0xf4, // LCD Data Register 8 + LCDDR7: 0xf3, // LCD Data Register 7 + LCDDR6: 0xf2, // LCD Data Register 6 + LCDDR5: 0xf1, // LCD Data Register 5 + LCDDR4: 0xf0, // LCD Data Register 4 + LCDDR3: 0xef, // LCD Data Register 3 + LCDDR2: 0xee, // LCD Data Register 2 + LCDDR1: 0xed, // LCD Data Register 1 + LCDDR0: 0xec, // LCD Data Register 0 + LCDCCR: 0xe7, // LCD Contrast Control Register + LCDFRR: 0xe6, // LCD Frame Rate Register + LCDCRB: 0xe5, // LCD Control and Status Register B + LCDCRA: 0xe4, // LCD Control and Status Register A + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK3 __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK3: 0x73, // Pin Change Mask Register 3 + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x6 // Brown-out Detector trigger level + EXTENDED_RSTDISBL = 0x1 // External Reset Disable + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enable + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for USI: Universal Serial Interface +const ( + // USISR: USI Status Register + USISR_USISIF = 0x80 // Start Condition Interrupt Flag + USISR_USIOIF = 0x40 // Counter Overflow Interrupt Flag + USISR_USIPF = 0x20 // Stop Condition Flag + USISR_USIDC = 0x10 // Data Output Collision + USISR_USICNT = 0xf // USI Counter Value Bits + + // USICR: USI Control Register + USICR_USISIE = 0x80 // Start Condition Interrupt Enable + USICR_USIOIE = 0x40 // Counter Overflow Interrupt Enable + USICR_USIWM = 0x30 // USI Wire Mode Bits + USICR_USICS = 0xc // USI Clock Source Select Bits + USICR_USICLK = 0x2 // Clock Strobe + USICR_USITC = 0x1 // Toggle Clock Port Pin +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmit Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data OverRun + UCSR0A_UPE0 = 0x4 // USART Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART Transmission Speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data Register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0x40 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // PRR: Power Reduction Register + PRR_PRLCD = 0x10 // Power Reduction LCD + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0A: Timer/Counter0 Control Register + TCCR0A_FOC0A = 0x80 // Force Output Compare + TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0A_COM0A = 0x30 // Compare Match Output Modes + TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0A_CS0 = 0x7 // Clock Selects + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0 + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2A: Timer/Counter2 Control Register + TCCR2A_FOC2A = 0x80 // Force Output Compare A + TCCR2A_WGM20 = 0x40 // Waveform Generation Mode + TCCR2A_COM2A = 0x30 // Compare Output Mode bits + TCCR2A_WGM21 = 0x8 // Waveform Generation Mode + TCCR2A_CS2 = 0x7 // Clock Select bits + + // TIMSK2: Timer/Counter2 Interrupt Mask register + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter2 Interrupt Flag Register + TIFR2_OCF2A = 0x2 // Timer/Counter2 Output Compare Flag 2 + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x10 // Enable External Clock Interrupt + ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for LCD: Liquid Crystal Display +const ( + // LCDFRR: LCD Frame Rate Register + LCDFRR_LCDPS = 0x70 // LCD Prescaler Selects + LCDFRR_LCDCD = 0x7 // LCD Clock Dividers + + // LCDCRB: LCD Control and Status Register B + LCDCRB_LCDCS = 0x80 // LCD CLock Select + LCDCRB_LCD2B = 0x40 // LCD 1/2 Bias Select + LCDCRB_LCDMUX = 0x30 // LCD Mux Selects + LCDCRB_LCDPM = 0xf // LCD Port Masks + + // LCDCRA: LCD Control and Status Register A + LCDCRA_LCDEN = 0x80 // LCD Enable + LCDCRA_LCDAB = 0x40 // LCD A or B waveform + LCDCRA_LCDIF = 0x10 // LCD Interrupt Flag + LCDCRA_LCDIE = 0x8 // LCD Interrupt Enable + LCDCRA_LCDBL = 0x1 // LCD Blanking +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC01 = 0x2 // External Interrupt Sense Control 0 Bit 1 + EICRA_ISC00 = 0x1 // External Interrupt Sense Control 0 Bit 0 + + // EIMSK: External Interrupt Mask Register + EIMSK_PCIE = 0xf0 // Pin Change Interrupt Enables + EIMSK_INT0 = 0x1 // External Interrupt Request 0 Enable + + // EIFR: External Interrupt Flag Register + EIFR_PCIF = 0xf0 // Pin Change Interrupt Flags + EIFR_INTF0 = 0x1 // External Interrupt Flag 0 +) diff --git a/src/device/avr/atmega6490a.ld b/src/device/avr/atmega6490a.ld new file mode 100644 index 00000000..1b91bc81 --- /dev/null +++ b/src/device/avr/atmega6490a.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega6490A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_size = 0x1000; +__num_isrs = 25; diff --git a/src/device/avr/atmega6490p.go b/src/device/avr/atmega6490p.go new file mode 100644 index 00000000..46930df4 --- /dev/null +++ b/src/device/avr/atmega6490p.go @@ -0,0 +1,692 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega6490P.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega6490p + +// Device information for the ATmega6490P. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega6490P" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_PCINT0 = 2 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 3 // Pin Change Interrupt Request 1 + IRQ_TIMER2_COMP = 4 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 5 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 6 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 7 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 8 // Timer/Counter Compare Match B + IRQ_TIMER1_OVF = 9 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 10 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 11 // Timer/Counter0 Overflow + IRQ_SPI_STC = 12 // SPI Serial Transfer Complete + IRQ_USART_RX = 13 // USART, Rx Complete + IRQ_USART_UDRE = 14 // USART Data register Empty + IRQ_USART0_TX = 15 // USART0, Tx Complete + IRQ_USI_START = 16 // USI Start Condition + IRQ_USI_OVERFLOW = 17 // USI Overflow + IRQ_ANALOG_COMP = 18 // Analog Comparator + IRQ_ADC = 19 // ADC Conversion Complete + IRQ_EE_READY = 20 // EEPROM Ready + IRQ_SPM_READY = 21 // Store Program Memory Read + IRQ_LCD = 22 // LCD Start of Frame + IRQ_PCINT2 = 23 // Pin Change Interrupt Request 2 + IRQ_PCINT3 = 24 // Pin Change Interrupt Request 3 + IRQ_max = 24 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 0 + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // Universal Serial Interface + USI = struct { + USIDR __reg + USISR __reg + USICR __reg + }{ + USIDR: 0xba, // USI Data Register + USISR: 0xb9, // USI Status Register + USICR: 0xb8, // USI Control Register + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + PRR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + PRR: 0x64, // Power Reduction Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access Bytes + EEARH: 0x41, // EEPROM Read/Write Access Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + PORTH __reg + DDRH __reg + PINH __reg + PORTJ __reg + DDRJ __reg + PINJ __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + PORTG: 0x34, // Port G Data Register + DDRG: 0x33, // Port G Data Direction Register + PING: 0x32, // Port G Input Pins + PORTH: 0xda, // PORT H Data Register + DDRH: 0xd9, // PORT H Data Direction Register + PINH: 0xd8, // PORT H Input Pins + PORTJ: 0xdd, // PORT J Data Register + DDRJ: 0xdc, // PORT J Data Direction Register + PINJ: 0xdb, // PORT J Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0A __reg + TCNT0 __reg + OCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR0A: 0x44, // Timer/Counter0 Control Register + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2A __reg + TCNT2 __reg + OCR2A __reg + TIMSK2 __reg + TIFR2 __reg + ASSR __reg + }{ + TCCR2A: 0xb0, // Timer/Counter2 Control Register + TCNT2: 0xb2, // Timer/Counter2 + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register + TIMSK2: 0x70, // Timer/Counter2 Interrupt Mask register + TIFR2: 0x37, // Timer/Counter2 Interrupt Flag Register + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x60, // Watchdog Timer Control Register + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // Liquid Crystal Display + LCD = struct { + LCDDR19 __reg + LCDDR18 __reg + LCDDR17 __reg + LCDDR16 __reg + LCDDR15 __reg + LCDDR14 __reg + LCDDR13 __reg + LCDDR12 __reg + LCDDR11 __reg + LCDDR10 __reg + LCDDR9 __reg + LCDDR8 __reg + LCDDR7 __reg + LCDDR6 __reg + LCDDR5 __reg + LCDDR4 __reg + LCDDR3 __reg + LCDDR2 __reg + LCDDR1 __reg + LCDDR0 __reg + LCDCCR __reg + LCDFRR __reg + LCDCRB __reg + LCDCRA __reg + }{ + LCDDR19: 0xff, // LCD Data Register 19 + LCDDR18: 0xfe, // LCD Data Register 18 + LCDDR17: 0xfd, // LCD Data Register 17 + LCDDR16: 0xfc, // LCD Data Register 16 + LCDDR15: 0xfb, // LCD Data Register 15 + LCDDR14: 0xfa, // LCD Data Register 14 + LCDDR13: 0xf9, // LCD Data Register 13 + LCDDR12: 0xf8, // LCD Data Register 12 + LCDDR11: 0xf7, // LCD Data Register 11 + LCDDR10: 0xf6, // LCD Data Register 10 + LCDDR9: 0xf5, // LCD Data Register 9 + LCDDR8: 0xf4, // LCD Data Register 8 + LCDDR7: 0xf3, // LCD Data Register 7 + LCDDR6: 0xf2, // LCD Data Register 6 + LCDDR5: 0xf1, // LCD Data Register 5 + LCDDR4: 0xf0, // LCD Data Register 4 + LCDDR3: 0xef, // LCD Data Register 3 + LCDDR2: 0xee, // LCD Data Register 2 + LCDDR1: 0xed, // LCD Data Register 1 + LCDDR0: 0xec, // LCD Data Register 0 + LCDCCR: 0xe7, // LCD Contrast Control Register + LCDFRR: 0xe6, // LCD Frame Rate Register + LCDCRB: 0xe5, // LCD Control and Status Register B + LCDCRA: 0xe4, // LCD Control and Status Register A + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK3 __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK3: 0x73, // Pin Change Mask Register 3 + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x6 // Brown-out Detector trigger level + EXTENDED_RSTDISBL = 0x1 // External Reset Disable + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enable + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for USI: Universal Serial Interface +const ( + // USISR: USI Status Register + USISR_USISIF = 0x80 // Start Condition Interrupt Flag + USISR_USIOIF = 0x40 // Counter Overflow Interrupt Flag + USISR_USIPF = 0x20 // Stop Condition Flag + USISR_USIDC = 0x10 // Data Output Collision + USISR_USICNT = 0xf // USI Counter Value Bits + + // USICR: USI Control Register + USICR_USISIE = 0x80 // Start Condition Interrupt Enable + USICR_USIOIE = 0x40 // Counter Overflow Interrupt Enable + USICR_USIWM = 0x30 // USI Wire Mode Bits + USICR_USICS = 0xc // USI Clock Source Select Bits + USICR_USICLK = 0x2 // Clock Strobe + USICR_USITC = 0x1 // Toggle Clock Port Pin +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmit Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data OverRun + UCSR0A_UPE0 = 0x4 // USART Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART Transmission Speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data Register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0x40 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // PRR: Power Reduction Register + PRR_PRLCD = 0x10 // Power Reduction LCD + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0A: Timer/Counter0 Control Register + TCCR0A_FOC0A = 0x80 // Force Output Compare + TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0A_COM0A = 0x30 // Compare Match Output Modes + TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0A_CS0 = 0x7 // Clock Selects + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0 + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2A: Timer/Counter2 Control Register + TCCR2A_FOC2A = 0x80 // Force Output Compare A + TCCR2A_WGM20 = 0x40 // Waveform Generation Mode + TCCR2A_COM2A = 0x30 // Compare Output Mode bits + TCCR2A_WGM21 = 0x8 // Waveform Generation Mode + TCCR2A_CS2 = 0x7 // Clock Select bits + + // TIMSK2: Timer/Counter2 Interrupt Mask register + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter2 Interrupt Flag Register + TIFR2_OCF2A = 0x2 // Timer/Counter2 Output Compare Flag 2 + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x10 // Enable External Clock Interrupt + ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for LCD: Liquid Crystal Display +const ( + // LCDFRR: LCD Frame Rate Register + LCDFRR_LCDPS = 0x70 // LCD Prescaler Selects + LCDFRR_LCDCD = 0x7 // LCD Clock Dividers + + // LCDCRB: LCD Control and Status Register B + LCDCRB_LCDCS = 0x80 // LCD CLock Select + LCDCRB_LCD2B = 0x40 // LCD 1/2 Bias Select + LCDCRB_LCDMUX = 0x30 // LCD Mux Selects + LCDCRB_LCDPM = 0xf // LCD Port Masks + + // LCDCRA: LCD Control and Status Register A + LCDCRA_LCDEN = 0x80 // LCD Enable + LCDCRA_LCDAB = 0x40 // LCD A or B waveform + LCDCRA_LCDIF = 0x10 // LCD Interrupt Flag + LCDCRA_LCDIE = 0x8 // LCD Interrupt Enable + LCDCRA_LCDBL = 0x1 // LCD Blanking +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC01 = 0x2 // External Interrupt Sense Control 0 Bit 1 + EICRA_ISC00 = 0x1 // External Interrupt Sense Control 0 Bit 0 + + // EIMSK: External Interrupt Mask Register + EIMSK_PCIE = 0xf0 // Pin Change Interrupt Enables + EIMSK_INT0 = 0x1 // External Interrupt Request 0 Enable + + // EIFR: External Interrupt Flag Register + EIFR_PCIF = 0xf0 // Pin Change Interrupt Flags + EIFR_INTF0 = 0x1 // External Interrupt Flag 0 +) diff --git a/src/device/avr/atmega6490p.ld b/src/device/avr/atmega6490p.ld new file mode 100644 index 00000000..a8c639d2 --- /dev/null +++ b/src/device/avr/atmega6490p.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega6490P.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_size = 0x1000; +__num_isrs = 25; diff --git a/src/device/avr/atmega649a.go b/src/device/avr/atmega649a.go new file mode 100644 index 00000000..543a2ed4 --- /dev/null +++ b/src/device/avr/atmega649a.go @@ -0,0 +1,666 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega649A.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega649a + +// Device information for the ATmega649A. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega649A" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_PCINT0 = 2 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 3 // Pin Change Interrupt Request 1 + IRQ_TIMER2_COMP = 4 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 5 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 6 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 7 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 8 // Timer/Counter Compare Match B + IRQ_TIMER1_OVF = 9 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 10 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 11 // Timer/Counter0 Overflow + IRQ_SPI_STC = 12 // SPI Serial Transfer Complete + IRQ_USART0_RX = 13 // USART0, Rx Complete + IRQ_USART0_UDRE = 14 // USART0 Data register Empty + IRQ_USART0_TX = 15 // USART0, Tx Complete + IRQ_USI_START = 16 // USI Start Condition + IRQ_USI_OVERFLOW = 17 // USI Overflow + IRQ_ANALOG_COMP = 18 // Analog Comparator + IRQ_ADC = 19 // ADC Conversion Complete + IRQ_EE_READY = 20 // EEPROM Ready + IRQ_SPM_READY = 21 // Store Program Memory Read + IRQ_LCD = 22 // LCD Start of Frame + IRQ_max = 22 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 0 + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // Universal Serial Interface + USI = struct { + USIDR __reg + USISR __reg + USICR __reg + }{ + USIDR: 0xba, // USI Data Register + USISR: 0xb9, // USI Status Register + USICR: 0xb8, // USI Control Register + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + PRR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + PRR: 0x64, // Power Reduction Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // Liquid Crystal Display + LCD = struct { + LCDDR18 __reg + LCDDR17 __reg + LCDDR16 __reg + LCDDR15 __reg + LCDDR13 __reg + LCDDR12 __reg + LCDDR11 __reg + LCDDR10 __reg + LCDDR8 __reg + LCDDR7 __reg + LCDDR6 __reg + LCDDR5 __reg + LCDDR3 __reg + LCDDR2 __reg + LCDDR1 __reg + LCDDR0 __reg + LCDCCR __reg + LCDFRR __reg + LCDCRB __reg + LCDCRA __reg + }{ + LCDDR18: 0xfe, // LCD Data Register 18 + LCDDR17: 0xfd, // LCD Data Register 17 + LCDDR16: 0xfc, // LCD Data Register 16 + LCDDR15: 0xfb, // LCD Data Register 15 + LCDDR13: 0xf9, // LCD Data Register 13 + LCDDR12: 0xf8, // LCD Data Register 12 + LCDDR11: 0xf7, // LCD Data Register 11 + LCDDR10: 0xf6, // LCD Data Register 10 + LCDDR8: 0xf4, // LCD Data Register 8 + LCDDR7: 0xf3, // LCD Data Register 7 + LCDDR6: 0xf2, // LCD Data Register 6 + LCDDR5: 0xf1, // LCD Data Register 5 + LCDDR3: 0xef, // LCD Data Register 3 + LCDDR2: 0xee, // LCD Data Register 2 + LCDDR1: 0xed, // LCD Data Register 1 + LCDDR0: 0xec, // LCD Data Register 0 + LCDCCR: 0xe7, // LCD Contrast Control Register + LCDFRR: 0xe6, // LCD Frame Rate Register + LCDCRB: 0xe5, // LCD Control and Status Register B + LCDCRA: 0xe4, // LCD Control Register A + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK1 __reg + PCMSK0 __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access Bytes + EEARH: 0x41, // EEPROM Read/Write Access Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + PORTG: 0x34, // Port G Data Register + DDRG: 0x33, // Port G Data Direction Register + PING: 0x32, // Port G Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0A __reg + TCNT0 __reg + OCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR0A: 0x44, // Timer/Counter0 Control Register + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2A __reg + TCNT2 __reg + OCR2A __reg + TIMSK2 __reg + TIFR2 __reg + ASSR __reg + }{ + TCCR2A: 0xb0, // Timer/Counter2 Control Register + TCNT2: 0xb2, // Timer/Counter2 + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register + TIMSK2: 0x70, // Timer/Counter2 Interrupt Mask register + TIFR2: 0x37, // Timer/Counter2 Interrupt Flag Register + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x60, // Watchdog Timer Control Register + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x6 // Brown-out Detector trigger level + EXTENDED_RSTDISBL = 0x1 // External Reset Disable + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enable + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for USI: Universal Serial Interface +const ( + // USISR: USI Status Register + USISR_USISIF = 0x80 // Start Condition Interrupt Flag + USISR_USIOIF = 0x40 // Counter Overflow Interrupt Flag + USISR_USIPF = 0x20 // Stop Condition Flag + USISR_USIDC = 0x10 // Data Output Collision + USISR_USICNT = 0xf // USI Counter Value Bits + + // USICR: USI Control Register + USICR_USISIE = 0x80 // Start Condition Interrupt Enable + USICR_USIOIE = 0x40 // Counter Overflow Interrupt Enable + USICR_USIWM = 0x30 // USI Wire Mode Bits + USICR_USICS = 0xc // USI Clock Source Select Bits + USICR_USICLK = 0x2 // Clock Strobe + USICR_USITC = 0x1 // Toggle Clock Port Pin +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmit Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data OverRun + UCSR0A_UPE0 = 0x4 // USART Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART Transmission Speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data Register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0x40 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // PRR: Power Reduction Register + PRR_PRLCD = 0x10 // Power Reduction LCD + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable +) + +// Bitfields for LCD: Liquid Crystal Display +const ( + // LCDFRR: LCD Frame Rate Register + LCDFRR_LCDPS = 0x70 // LCD Prescaler Selects + LCDFRR_LCDCD = 0x7 // LCD Clock Dividers + + // LCDCRB: LCD Control and Status Register B + LCDCRB_LCDCS = 0x80 // LCD CLock Select + LCDCRB_LCD2B = 0x40 // LCD 1/2 Bias Select + LCDCRB_LCDMUX = 0x30 // LCD Mux Selects + LCDCRB_LCDPM = 0xf // LCD Port Masks + + // LCDCRA: LCD Control Register A + LCDCRA_LCDEN = 0x80 // LCD Enable + LCDCRA_LCDAB = 0x40 // LCD A or B waveform + LCDCRA_LCDIF = 0x10 // LCD Interrupt Flag + LCDCRA_LCDIE = 0x8 // LCD Interrupt Enable + LCDCRA_LCDBL = 0x1 // LCD Blanking +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC01 = 0x2 // External Interrupt Sense Control 0 Bit 1 + EICRA_ISC00 = 0x1 // External Interrupt Sense Control 0 Bit 0 + + // EIMSK: External Interrupt Mask Register + EIMSK_PCIE = 0xf0 // Pin Change Interrupt Enables + EIMSK_INT0 = 0x1 // External Interrupt Request 0 Enable + + // EIFR: External Interrupt Flag Register + EIFR_PCIF = 0xf0 // Pin Change Interrupt Flags + EIFR_INTF0 = 0x1 // External Interrupt Flag 0 +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0A: Timer/Counter0 Control Register + TCCR0A_FOC0A = 0x80 // Force Output Compare + TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0A_COM0A = 0x30 // Compare Match Output Modes + TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0A_CS0 = 0x7 // Clock Selects + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0 + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2A: Timer/Counter2 Control Register + TCCR2A_FOC2A = 0x80 // Force Output Compare A + TCCR2A_WGM20 = 0x40 // Waveform Generation Mode + TCCR2A_COM2A = 0x30 // Compare Output Mode bits + TCCR2A_WGM21 = 0x8 // Waveform Generation Mode + TCCR2A_CS2 = 0x7 // Clock Select bits + + // TIMSK2: Timer/Counter2 Interrupt Mask register + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter2 Interrupt Flag Register + TIFR2_OCF2A = 0x2 // Timer/Counter2 Output Compare Flag 2 + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x10 // Enable External Clock Interrupt + ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) diff --git a/src/device/avr/atmega649a.ld b/src/device/avr/atmega649a.ld new file mode 100644 index 00000000..d5388148 --- /dev/null +++ b/src/device/avr/atmega649a.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega649A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_size = 0x1000; +__num_isrs = 23; diff --git a/src/device/avr/atmega649p.go b/src/device/avr/atmega649p.go new file mode 100644 index 00000000..5edecbe0 --- /dev/null +++ b/src/device/avr/atmega649p.go @@ -0,0 +1,666 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega649P.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega649p + +// Device information for the ATmega649P. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega649P" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_PCINT0 = 2 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 3 // Pin Change Interrupt Request 1 + IRQ_TIMER2_COMP = 4 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 5 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 6 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 7 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 8 // Timer/Counter Compare Match B + IRQ_TIMER1_OVF = 9 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 10 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 11 // Timer/Counter0 Overflow + IRQ_SPI_STC = 12 // SPI Serial Transfer Complete + IRQ_USART0_RX = 13 // USART0, Rx Complete + IRQ_USART0_UDRE = 14 // USART0 Data register Empty + IRQ_USART0_TX = 15 // USART0, Tx Complete + IRQ_USI_START = 16 // USI Start Condition + IRQ_USI_OVERFLOW = 17 // USI Overflow + IRQ_ANALOG_COMP = 18 // Analog Comparator + IRQ_ADC = 19 // ADC Conversion Complete + IRQ_EE_READY = 20 // EEPROM Ready + IRQ_SPM_READY = 21 // Store Program Memory Read + IRQ_LCD = 22 // LCD Start of Frame + IRQ_max = 22 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + DIDR0: 0x7e, // Digital Input Disable Register 0 + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // Universal Serial Interface + USI = struct { + USIDR __reg + USISR __reg + USICR __reg + }{ + USIDR: 0xba, // USI Data Register + USISR: 0xb9, // USI Status Register + USICR: 0xb8, // USI Control Register + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + PRR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + PRR: 0x64, // Power Reduction Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory + } + + // Liquid Crystal Display + LCD = struct { + LCDDR18 __reg + LCDDR17 __reg + LCDDR16 __reg + LCDDR15 __reg + LCDDR13 __reg + LCDDR12 __reg + LCDDR11 __reg + LCDDR10 __reg + LCDDR8 __reg + LCDDR7 __reg + LCDDR6 __reg + LCDDR5 __reg + LCDDR3 __reg + LCDDR2 __reg + LCDDR1 __reg + LCDDR0 __reg + LCDCCR __reg + LCDFRR __reg + LCDCRB __reg + LCDCRA __reg + }{ + LCDDR18: 0xfe, // LCD Data Register 18 + LCDDR17: 0xfd, // LCD Data Register 17 + LCDDR16: 0xfc, // LCD Data Register 16 + LCDDR15: 0xfb, // LCD Data Register 15 + LCDDR13: 0xf9, // LCD Data Register 13 + LCDDR12: 0xf8, // LCD Data Register 12 + LCDDR11: 0xf7, // LCD Data Register 11 + LCDDR10: 0xf6, // LCD Data Register 10 + LCDDR8: 0xf4, // LCD Data Register 8 + LCDDR7: 0xf3, // LCD Data Register 7 + LCDDR6: 0xf2, // LCD Data Register 6 + LCDDR5: 0xf1, // LCD Data Register 5 + LCDDR3: 0xef, // LCD Data Register 3 + LCDDR2: 0xee, // LCD Data Register 2 + LCDDR1: 0xed, // LCD Data Register 1 + LCDDR0: 0xec, // LCD Data Register 0 + LCDCCR: 0xe7, // LCD Contrast Control Register + LCDFRR: 0xe6, // LCD Frame Rate Register + LCDCRB: 0xe5, // LCD Control and Status Register B + LCDCRA: 0xe4, // LCD Control Register A + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCMSK1 __reg + PCMSK0 __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access Bytes + EEARH: 0x41, // EEPROM Read/Write Access Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Data Register, Port E + DDRE: 0x2d, // Data Direction Register, Port E + PINE: 0x2c, // Input Pins, Port E + PORTF: 0x31, // Data Register, Port F + DDRF: 0x30, // Data Direction Register, Port F + PINF: 0x2f, // Input Pins, Port F + PORTG: 0x34, // Port G Data Register + DDRG: 0x33, // Port G Data Direction Register + PING: 0x32, // Port G Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0A __reg + TCNT0 __reg + OCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR0A: 0x44, // Timer/Counter0 Control Register + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2A __reg + TCNT2 __reg + OCR2A __reg + TIMSK2 __reg + TIFR2 __reg + ASSR __reg + }{ + TCCR2A: 0xb0, // Timer/Counter2 Control Register + TCNT2: 0xb2, // Timer/Counter2 + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register + TIMSK2: 0x70, // Timer/Counter2 Interrupt Mask register + TIFR2: 0x37, // Timer/Counter2 Interrupt Flag Register + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x60, // Watchdog Timer Control Register + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x6 // Brown-out Detector trigger level + EXTENDED_RSTDISBL = 0x1 // External Reset Disable + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enable + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for USI: Universal Serial Interface +const ( + // USISR: USI Status Register + USISR_USISIF = 0x80 // Start Condition Interrupt Flag + USISR_USIOIF = 0x40 // Counter Overflow Interrupt Flag + USISR_USIPF = 0x20 // Stop Condition Flag + USISR_USIDC = 0x10 // Data Output Collision + USISR_USICNT = 0xf // USI Counter Value Bits + + // USICR: USI Control Register + USICR_USISIE = 0x80 // Start Condition Interrupt Enable + USICR_USIOIE = 0x40 // Counter Overflow Interrupt Enable + USICR_USIWM = 0x30 // USI Wire Mode Bits + USICR_USICS = 0xc // USI Clock Source Select Bits + USICR_USICLK = 0x2 // Clock Strobe + USICR_USITC = 0x1 // Toggle Clock Port Pin +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmit Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data OverRun + UCSR0A_UPE0 = 0x4 // USART Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART Transmission Speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data Register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0x40 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // PRR: Power Reduction Register + PRR_PRLCD = 0x10 // Power Reduction LCD + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable +) + +// Bitfields for LCD: Liquid Crystal Display +const ( + // LCDFRR: LCD Frame Rate Register + LCDFRR_LCDPS = 0x70 // LCD Prescaler Selects + LCDFRR_LCDCD = 0x7 // LCD Clock Dividers + + // LCDCRB: LCD Control and Status Register B + LCDCRB_LCDCS = 0x80 // LCD CLock Select + LCDCRB_LCD2B = 0x40 // LCD 1/2 Bias Select + LCDCRB_LCDMUX = 0x30 // LCD Mux Selects + LCDCRB_LCDPM = 0xf // LCD Port Masks + + // LCDCRA: LCD Control Register A + LCDCRA_LCDEN = 0x80 // LCD Enable + LCDCRA_LCDAB = 0x40 // LCD A or B waveform + LCDCRA_LCDIF = 0x10 // LCD Interrupt Flag + LCDCRA_LCDIE = 0x8 // LCD Interrupt Enable + LCDCRA_LCDBL = 0x1 // LCD Blanking +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC01 = 0x2 // External Interrupt Sense Control 0 Bit 1 + EICRA_ISC00 = 0x1 // External Interrupt Sense Control 0 Bit 0 + + // EIMSK: External Interrupt Mask Register + EIMSK_PCIE = 0xf0 // Pin Change Interrupt Enables + EIMSK_INT0 = 0x1 // External Interrupt Request 0 Enable + + // EIFR: External Interrupt Flag Register + EIFR_PCIF = 0xf0 // Pin Change Interrupt Flags + EIFR_INTF0 = 0x1 // External Interrupt Flag 0 +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0A: Timer/Counter0 Control Register + TCCR0A_FOC0A = 0x80 // Force Output Compare + TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0A_COM0A = 0x30 // Compare Match Output Modes + TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0A_CS0 = 0x7 // Clock Selects + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0 + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2A: Timer/Counter2 Control Register + TCCR2A_FOC2A = 0x80 // Force Output Compare A + TCCR2A_WGM20 = 0x40 // Waveform Generation Mode + TCCR2A_COM2A = 0x30 // Compare Output Mode bits + TCCR2A_WGM21 = 0x8 // Waveform Generation Mode + TCCR2A_CS2 = 0x7 // Clock Select bits + + // TIMSK2: Timer/Counter2 Interrupt Mask register + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter2 Interrupt Flag Register + TIFR2_OCF2A = 0x2 // Timer/Counter2 Output Compare Flag 2 + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x10 // Enable External Clock Interrupt + ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) diff --git a/src/device/avr/atmega649p.ld b/src/device/avr/atmega649p.ld new file mode 100644 index 00000000..0f17f447 --- /dev/null +++ b/src/device/avr/atmega649p.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega649P.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_size = 0x1000; +__num_isrs = 23; diff --git a/src/device/avr/atmega64a.go b/src/device/avr/atmega64a.go new file mode 100644 index 00000000..060330e1 --- /dev/null +++ b/src/device/avr/atmega64a.go @@ -0,0 +1,670 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega64A.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega64a + +// Device information for the ATmega64A. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega64A" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_INT3 = 4 // External Interrupt Request 3 + IRQ_INT4 = 5 // External Interrupt Request 4 + IRQ_INT5 = 6 // External Interrupt Request 5 + IRQ_INT6 = 7 // External Interrupt Request 6 + IRQ_INT7 = 8 // External Interrupt Request 7 + IRQ_TIMER2_COMP = 9 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 10 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 11 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 12 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 13 // Timer/Counter Compare Match B + IRQ_TIMER1_OVF = 14 // Timer/Counter1 Overflow + IRQ_TIMER0_COMP = 15 // Timer/Counter0 Compare Match + IRQ_TIMER0_OVF = 16 // Timer/Counter0 Overflow + IRQ_SPI_STC = 17 // SPI Serial Transfer Complete + IRQ_USART0_RX = 18 // USART0, Rx Complete + IRQ_USART0_UDRE = 19 // USART0 Data Register Empty + IRQ_USART0_TX = 20 // USART0, Tx Complete + IRQ_ADC = 21 // ADC Conversion Complete + IRQ_EE_READY = 22 // EEPROM Ready + IRQ_ANALOG_COMP = 23 // Analog Comparator + IRQ_TIMER1_COMPC = 24 // Timer/Counter1 Compare Match C + IRQ_TIMER3_CAPT = 25 // Timer/Counter3 Capture Event + IRQ_TIMER3_COMPA = 26 // Timer/Counter3 Compare Match A + IRQ_TIMER3_COMPB = 27 // Timer/Counter3 Compare Match B + IRQ_TIMER3_COMPC = 28 // Timer/Counter3 Compare Match C + IRQ_TIMER3_OVF = 29 // Timer/Counter3 Overflow + IRQ_USART1_RX = 30 // USART1, Rx Complete + IRQ_USART1_UDRE = 31 // USART1, Data Register Empty + IRQ_USART1_TX = 32 // USART1, Tx Complete + IRQ_TWI = 33 // 2-wire Serial Interface + IRQ_SPM_READY = 34 // Store Program Memory Read + IRQ_max = 34 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog Comparator + AC = struct { + ACSR __reg + }{ + ACSR: 0x28, // Analog Comparator Control And Status Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + ADCSRB __reg + }{ + ADMUX: 0x27, // The ADC multiplexer Selection Register + ADCL: 0x24, // ADC Data Register Bytes + ADCH: 0x24, // ADC Data Register Bytes + ADCSRA: 0x26, // The ADC Control and Status register A + ADCSRB: 0x8e, // The ADC Control and Status register B + } + + // Serial Peripheral Interface + SPI = struct { + SPDR __reg + SPSR __reg + SPCR __reg + }{ + SPDR: 0x2f, // SPI Data Register + SPSR: 0x2e, // SPI Status Register + SPCR: 0x2d, // SPI Control Register + } + + // Two Wire Serial Interface + TWI = struct { + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWBR: 0x70, // TWI Bit Rate register + TWCR: 0x74, // TWI Control Register + TWSR: 0x71, // TWI Status Register + TWDR: 0x73, // TWI Data register + TWAR: 0x72, // TWI (Slave) Address register + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0H __reg + UBRR0L __reg + UDR1 __reg + UCSR1A __reg + UCSR1B __reg + UCSR1C __reg + UBRR1H __reg + UBRR1L __reg + }{ + UDR0: 0x2c, // USART I/O Data Register + UCSR0A: 0x2b, // USART Control and Status Register A + UCSR0B: 0x2a, // USART Control and Status Register B + UCSR0C: 0x95, // USART Control and Status Register C + UBRR0H: 0x90, // USART Baud Rate Register Hight Byte + UBRR0L: 0x29, // USART Baud Rate Register Low Byte + UDR1: 0x9c, // USART I/O Data Register + UCSR1A: 0x9b, // USART Control and Status Register A + UCSR1B: 0x9a, // USART Control and Status Register B + UCSR1C: 0x9d, // USART Control and Status Register C + UBRR1H: 0x98, // USART Baud Rate Register Hight Byte + UBRR1L: 0x99, // USART Baud Rate Register Low Byte + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + MCUCR __reg + XMCRA __reg + XMCRB __reg + OSCCAL __reg + XDIV __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + MCUCR: 0x55, // MCU Control Register + XMCRA: 0x6d, // External Memory Control Register A + XMCRB: 0x6c, // External Memory Control Register B + OSCCAL: 0x6f, // Oscillator Calibration Value + XDIV: 0x5c, // XTAL Divide Control Register + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x68, // Store Program Memory Control Register + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x42, // On-Chip Debug Related Register in I/O Memory + } + + // Other Registers + MISC = struct { + }{} + + // External Interrupts + EXINT = struct { + EICRA __reg + EICRB __reg + EIMSK __reg + EIFR __reg + }{ + EICRA: 0x6a, // External Interrupt Control Register A + EICRB: 0x5a, // External Interrupt Control Register B + EIMSK: 0x59, // External Interrupt Mask Register + EIFR: 0x58, // External Interrupt Flag Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x3e, // EEPROM Read/Write Access Bytes + EEARH: 0x3e, // EEPROM Read/Write Access Bytes + EEDR: 0x3d, // EEPROM Data Register + EECR: 0x3c, // EEPROM Control Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + }{ + PORTA: 0x3b, // Port A Data Register + DDRA: 0x3a, // Port A Data Direction Register + PINA: 0x39, // Port A Input Pins + PORTB: 0x38, // Port B Data Register + DDRB: 0x37, // Port B Data Direction Register + PINB: 0x36, // Port B Input Pins + PORTC: 0x35, // Port C Data Register + DDRC: 0x34, // Port C Data Direction Register + PINC: 0x33, // Port C Input Pins + PORTD: 0x32, // Port D Data Register + DDRD: 0x31, // Port D Data Direction Register + PIND: 0x30, // Port D Input Pins + PORTE: 0x23, // Data Register, Port E + DDRE: 0x22, // Data Direction Register, Port E + PINE: 0x21, // Input Pins, Port E + PORTF: 0x62, // Data Register, Port F + DDRF: 0x61, // Data Direction Register, Port F + PINF: 0x20, // Input Pins, Port F + PORTG: 0x65, // Data Register, Port G + DDRG: 0x64, // Data Direction Register, Port G + PING: 0x63, // Input Pins, Port G + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR0 __reg + TCNT0 __reg + OCR0 __reg + ASSR __reg + }{ + TCCR0: 0x53, // Timer/Counter Control Register + TCNT0: 0x52, // Timer/Counter Register + OCR0: 0x51, // Output Compare Register + ASSR: 0x50, // Asynchronus Status Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + OCR1CL __reg + OCR1CH __reg + ICR1L __reg + ICR1H __reg + TCCR3A __reg + TCCR3B __reg + TCCR3C __reg + TCNT3L __reg + TCNT3H __reg + OCR3AL __reg + OCR3AH __reg + OCR3BL __reg + OCR3BH __reg + OCR3CL __reg + OCR3CH __reg + ICR3L __reg + ICR3H __reg + }{ + TCCR1A: 0x4f, // Timer/Counter1 Control Register A + TCCR1B: 0x4e, // Timer/Counter1 Control Register B + TCCR1C: 0x7a, // Timer/Counter1 Control Register C + TCNT1L: 0x4c, // Timer/Counter1 Bytes + TCNT1H: 0x4c, // Timer/Counter1 Bytes + OCR1AL: 0x4a, // Timer/Counter1 Output Compare Register Bytes + OCR1AH: 0x4a, // Timer/Counter1 Output Compare Register Bytes + OCR1BL: 0x48, // Timer/Counter1 Output Compare Register Bytes + OCR1BH: 0x48, // Timer/Counter1 Output Compare Register Bytes + OCR1CL: 0x78, // Timer/Counter1 Output Compare Register Bytes + OCR1CH: 0x78, // Timer/Counter1 Output Compare Register Bytes + ICR1L: 0x46, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x46, // Timer/Counter1 Input Capture Register Bytes + TCCR3A: 0x8b, // Timer/Counter3 Control Register A + TCCR3B: 0x8a, // Timer/Counter3 Control Register B + TCCR3C: 0x8c, // Timer/Counter3 Control Register C + TCNT3L: 0x88, // Timer/Counter3 Bytes + TCNT3H: 0x88, // Timer/Counter3 Bytes + OCR3AL: 0x86, // Timer/Counter3 Output Compare Register A Bytes + OCR3AH: 0x86, // Timer/Counter3 Output Compare Register A Bytes + OCR3BL: 0x84, // Timer/Counter3 Output Compare Register B Bytes + OCR3BH: 0x84, // Timer/Counter3 Output Compare Register B Bytes + OCR3CL: 0x82, // Timer/Counter3 Output compare Register C Bytes + OCR3CH: 0x82, // Timer/Counter3 Output compare Register C Bytes + ICR3L: 0x80, // Timer/Counter3 Input Capture Register Bytes + ICR3H: 0x80, // Timer/Counter3 Input Capture Register Bytes + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR2 __reg + TCNT2 __reg + OCR2 __reg + }{ + TCCR2: 0x45, // Timer/Counter Control Register + TCNT2: 0x44, // Timer/Counter Register + OCR2: 0x43, // Output Compare Register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x41, // Watchdog Timer Control Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_M103C = 0x2 // ATmega103 Compatibility Mode + EXTENDED_WDTON = 0x1 // Watchdog Timer always on + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + HIGH_CKOPT = 0x10 // CKOPT fuse (operation dependent of CKSEL fuses) + + // LOW + LOW_BODLEVEL = 0x80 // Brownout detector trigger level + LOW_BODEN = 0x40 // Brown-out detection enabled + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCSRB: The ADC Control and Status register B + ADCSRB_ADTS = 0x7 // ADC Auto Trigger Source bits +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0x40 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity + + // UCSR1A: USART Control and Status Register A + UCSR1A_RXC1 = 0x80 // USART Receive Complete + UCSR1A_TXC1 = 0x40 // USART Transmitt Complete + UCSR1A_UDRE1 = 0x20 // USART Data Register Empty + UCSR1A_FE1 = 0x10 // Framing Error + UCSR1A_DOR1 = 0x8 // Data overRun + UCSR1A_UPE1 = 0x4 // Parity Error + UCSR1A_U2X1 = 0x2 // Double the USART transmission speed + UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode + + // UCSR1B: USART Control and Status Register B + UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable + UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable + UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable + UCSR1B_RXEN1 = 0x10 // Receiver Enable + UCSR1B_TXEN1 = 0x8 // Transmitter Enable + UCSR1B_UCSZ12 = 0x4 // Character Size + UCSR1B_RXB81 = 0x2 // Receive Data Bit 8 + UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8 + + // UCSR1C: USART Control and Status Register C + UCSR1C_UMSEL1 = 0x40 // USART Mode Select + UCSR1C_UPM1 = 0x30 // Parity Mode Bits + UCSR1C_USBS1 = 0x8 // Stop Bit Select + UCSR1C_UCSZ1 = 0x6 // Character Size + UCSR1C_UCPOL1 = 0x1 // Clock Polarity +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // MCUCR: MCU Control Register + MCUCR_SRE = 0x80 // External SRAM Enable + MCUCR_SRW10 = 0x40 // External SRAM Wait State Select + MCUCR_SE = 0x20 // Sleep Enable + MCUCR_SM = 0x18 // Sleep Mode Select + MCUCR_SM2 = 0x4 // Sleep Mode Select + MCUCR_IVSEL = 0x2 // Interrupt Vector Select + MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable + + // XMCRA: External Memory Control Register A + XMCRA_SRL = 0x70 // Wait state page limit + XMCRA_SRW0 = 0xc // Wait state select bit lower page + XMCRA_SRW11 = 0x2 // Wait state select bit upper page + + // XMCRB: External Memory Control Register B + XMCRB_XMBK = 0x80 // External Memory Bus Keeper Enable + XMCRB_XMM = 0x7 // External Memory High Mask + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // XDIV: XTAL Divide Control Register + XDIV_XDIVEN = 0x80 // XTAL Divide Enable + XDIV_XDIV = 0x7f // XTAl Divide Select Bits +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for JTAG: JTAG Interface +const ( + // OCDR: On-Chip Debug Related Register in I/O Memory + OCDR_OCDR = 0xff // On-Chip Debug Register Bits +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EICRB: External Interrupt Control Register B + EICRB_ISC7 = 0xc0 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC6 = 0x30 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC5 = 0xc // External Interrupt 7-4 Sense Control Bit + EICRB_ISC4 = 0x3 // External Interrupt 7-4 Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xff // External Interrupt Request 7 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xff // External Interrupt Flags +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR0: Timer/Counter Control Register + TCCR0_FOC0 = 0x80 // Force Output Compare + TCCR0_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0_COM0 = 0x30 // Compare Match Output Modes + TCCR0_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0_CS0 = 0x7 // Clock Selects + + // ASSR: Asynchronus Status Register + ASSR_AS0 = 0x8 // Asynchronus Timer/Counter 0 + ASSR_TCN0UB = 0x4 // Timer/Counter0 Update Busy + ASSR_OCR0UB = 0x2 // Output Compare register 0 Busy + ASSR_TCR0UB = 0x1 // Timer/Counter Control Register 0 Update Busy +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_COM1C = 0xc // Compare Output Mode 1C, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode Bits + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Clock Select1 bits + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare for channel A + TCCR1C_FOC1B = 0x40 // Force Output Compare for channel B + TCCR1C_FOC1C = 0x20 // Force Output Compare for channel C + + // TCCR3A: Timer/Counter3 Control Register A + TCCR3A_COM3A = 0xc0 // Compare Output Mode 3A, bits + TCCR3A_COM3B = 0x30 // Compare Output Mode 3B, bits + TCCR3A_COM3C = 0xc // Compare Output Mode 3C, bits + TCCR3A_WGM3 = 0x3 // Waveform Generation Mode Bits + + // TCCR3B: Timer/Counter3 Control Register B + TCCR3B_ICNC3 = 0x80 // Input Capture 3 Noise Canceler + TCCR3B_ICES3 = 0x40 // Input Capture 3 Edge Select + TCCR3B_WGM3 = 0x18 // Waveform Generation Mode + TCCR3B_CS3 = 0x7 // Clock Select3 bits + + // TCCR3C: Timer/Counter3 Control Register C + TCCR3C_FOC3A = 0x80 // Force Output Compare for channel A + TCCR3C_FOC3B = 0x40 // Force Output Compare for channel B + TCCR3C_FOC3C = 0x20 // Force Output Compare for channel C +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR2: Timer/Counter Control Register + TCCR2_FOC2 = 0x80 // Force Output Compare + TCCR2_WGM20 = 0x40 // Wafeform Generation Mode + TCCR2_COM2 = 0x30 // Compare Match Output Mode + TCCR2_WGM21 = 0x8 // Waveform Generation Mode + TCCR2_CS2 = 0x7 // Clock Select +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) diff --git a/src/device/avr/atmega64a.ld b/src/device/avr/atmega64a.ld new file mode 100644 index 00000000..513d0377 --- /dev/null +++ b/src/device/avr/atmega64a.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega64A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_size = 0x1000; +__num_isrs = 35; diff --git a/src/device/avr/atmega64c1.go b/src/device/avr/atmega64c1.go new file mode 100644 index 00000000..9f2c725f --- /dev/null +++ b/src/device/avr/atmega64c1.go @@ -0,0 +1,896 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega64C1.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega64c1 + +// Device information for the ATmega64C1. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega64C1" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset + IRQ_ANACOMP0 = 1 // Analog Comparator 0 + IRQ_ANACOMP1 = 2 // Analog Comparator 1 + IRQ_ANACOMP2 = 3 // Analog Comparator 2 + IRQ_ANACOMP3 = 4 // Analog Comparator 3 + IRQ_PSC_FAULT = 5 // PSC Fault + IRQ_PSC_EC = 6 // PSC End of Cycle + IRQ_INT0 = 7 // External Interrupt Request 0 + IRQ_INT1 = 8 // External Interrupt Request 1 + IRQ_INT2 = 9 // External Interrupt Request 2 + IRQ_INT3 = 10 // External Interrupt Request 3 + IRQ_TIMER1_CAPT = 11 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 12 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 13 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 14 // Timer1/Counter1 Overflow + IRQ_TIMER0_COMPA = 15 // Timer/Counter0 Compare Match A + IRQ_TIMER0_COMPB = 16 // Timer/Counter0 Compare Match B + IRQ_TIMER0_OVF = 17 // Timer/Counter0 Overflow + IRQ_CAN_INT = 18 // CAN MOB, Burst, General Errors + IRQ_CAN_TOVF = 19 // CAN Timer Overflow + IRQ_LIN_TC = 20 // LIN Transfer Complete + IRQ_LIN_ERR = 21 // LIN Error + IRQ_PCINT0 = 22 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 23 // Pin Change Interrupt Request 1 + IRQ_PCINT2 = 24 // Pin Change Interrupt Request 2 + IRQ_PCINT3 = 25 // Pin Change Interrupt Request 3 + IRQ_SPI_STC = 26 // SPI Serial Transfer Complete + IRQ_ADC = 27 // ADC Conversion Complete + IRQ_WDT = 28 // Watchdog Time-Out Interrupt + IRQ_EE_READY = 29 // EEPROM Ready + IRQ_SPM_READY = 30 // Store Program Memory Read + IRQ_max = 30 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // I/O Port + PORT = struct { + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + }{ + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Port E Data Register + DDRE: 0x2d, // Port E Data Direction Register + PINE: 0x2c, // Port E Input Pins + } + + // Controller Area Network + CAN = struct { + CANGCON __reg + CANGSTA __reg + CANGIT __reg + CANGIE __reg + CANEN2 __reg + CANEN1 __reg + CANIE2 __reg + CANIE1 __reg + CANSIT2 __reg + CANSIT1 __reg + CANBT1 __reg + CANBT2 __reg + CANBT3 __reg + CANTCON __reg + CANTIML __reg + CANTIMH __reg + CANTTCL __reg + CANTTCH __reg + CANTEC __reg + CANREC __reg + CANHPMOB __reg + CANPAGE __reg + CANSTMOB __reg + CANCDMOB __reg + CANIDT4 __reg + CANIDT3 __reg + CANIDT2 __reg + CANIDT1 __reg + CANIDM4 __reg + CANIDM3 __reg + CANIDM2 __reg + CANIDM1 __reg + CANSTML __reg + CANSTMH __reg + CANMSG __reg + }{ + CANGCON: 0xd8, // CAN General Control Register + CANGSTA: 0xd9, // CAN General Status Register + CANGIT: 0xda, // CAN General Interrupt Register Flags + CANGIE: 0xdb, // CAN General Interrupt Enable Register + CANEN2: 0xdc, // Enable MOb Register 2 + CANEN1: 0xdd, // Enable MOb Register 1(empty) + CANIE2: 0xde, // Enable Interrupt MOb Register 2 + CANIE1: 0xdf, // Enable Interrupt MOb Register 1 (empty) + CANSIT2: 0xe0, // CAN Status Interrupt MOb Register 2 + CANSIT1: 0xe1, // CAN Status Interrupt MOb Register 1 (empty) + CANBT1: 0xe2, // CAN Bit Timing Register 1 + CANBT2: 0xe3, // CAN Bit Timing Register 2 + CANBT3: 0xe4, // CAN Bit Timing Register 3 + CANTCON: 0xe5, // Timer Control Register + CANTIML: 0xe6, // Timer Register Low + CANTIMH: 0xe7, // Timer Register High + CANTTCL: 0xe8, // TTC Timer Register Low + CANTTCH: 0xe9, // TTC Timer Register High + CANTEC: 0xea, // Transmit Error Counter Register + CANREC: 0xeb, // Receive Error Counter Register + CANHPMOB: 0xec, // Highest Priority MOb Register + CANPAGE: 0xed, // Page MOb Register + CANSTMOB: 0xee, // MOb Status Register + CANCDMOB: 0xef, // MOb Control and DLC Register + CANIDT4: 0xf0, // Identifier Tag Register 4 + CANIDT3: 0xf1, // Identifier Tag Register 3 + CANIDT2: 0xf2, // Identifier Tag Register 2 + CANIDT1: 0xf3, // Identifier Tag Register 1 + CANIDM4: 0xf4, // Identifier Mask Register 4 + CANIDM3: 0xf5, // Identifier Mask Register 3 + CANIDM2: 0xf6, // Identifier Mask Register 2 + CANIDM1: 0xf7, // Identifier Mask Register 1 + CANSTML: 0xf8, // Time Stamp Register Low + CANSTMH: 0xf9, // Time Stamp Register High + CANMSG: 0xfa, // Message Data Register + } + + // Analog Comparator + AC = struct { + AC0CON __reg + AC1CON __reg + AC2CON __reg + AC3CON __reg + ACSR __reg + }{ + AC0CON: 0x94, // Analog Comparator 0 Control Register + AC1CON: 0x95, // Analog Comparator 1 Control Register + AC2CON: 0x96, // Analog Comparator 2 Control Register + AC3CON: 0x97, // Analog Comparator 3 Control Register + ACSR: 0x50, // Analog Comparator Status Register + } + + // Digital-to-Analog Converter + DAC = struct { + DACH __reg + DACL __reg + DACON __reg + }{ + DACH: 0x92, // DAC Data Register High Byte + DACL: 0x91, // DAC Data Register Low Byte + DACON: 0x90, // DAC Control Register + } + + // CPU Registers + CPU = struct { + SPMCSR __reg + SREG __reg + SPL __reg + SPH __reg + MCUCR __reg + MCUSR __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PLLCSR __reg + PRR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x3a, // General Purpose IO Register 2 + GPIOR1: 0x39, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PLLCSR: 0x49, // PLL Control And Status Register + PRR: 0x64, // Power Reduction Register + } + + // Timer/Counter, 8-bit + TC8 = struct { + TIMSK0 __reg + TIFR0 __reg + TCCR0A __reg + TCCR0B __reg + TCNT0 __reg + OCR0A __reg + OCR0B __reg + }{ + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + TCCR0A: 0x44, // Timer/Counter Control Register A + TCCR0B: 0x45, // Timer/Counter Control Register B + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + ADCSRB __reg + DIDR0 __reg + DIDR1 __reg + AMP0CSR __reg + AMP1CSR __reg + AMP2CSR __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRB: 0x7b, // ADC Control and Status Register B + DIDR0: 0x7e, // Digital Input Disable Register 0 + DIDR1: 0x7f, // Digital Input Disable Register 0 + AMP0CSR: 0x75, + AMP1CSR: 0x76, + AMP2CSR: 0x77, + } + + // Local Interconnect Network + LINUART = struct { + LINCR __reg + LINSIR __reg + LINENIR __reg + LINERR __reg + LINBTR __reg + LINBRRL __reg + LINBRRH __reg + LINDLR __reg + LINIDR __reg + LINSEL __reg + LINDAT __reg + }{ + LINCR: 0xc8, // LIN Control Register + LINSIR: 0xc9, // LIN Status and Interrupt Register + LINENIR: 0xca, // LIN Enable Interrupt Register + LINERR: 0xcb, // LIN Error Register + LINBTR: 0xcc, // LIN Bit Timing Register + LINBRRL: 0xcd, // LIN Baud Rate Low Register + LINBRRH: 0xce, // LIN Baud Rate High Register + LINDLR: 0xcf, // LIN Data Length Register + LINIDR: 0xd0, // LIN Identifier Register + LINSEL: 0xd1, // LIN Data Buffer Selection Register + LINDAT: 0xd2, // LIN Data Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCICR __reg + PCMSK3 __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + PCMSK3: 0x6d, // Pin Change Mask Register 3 + PCMSK2: 0x6c, // Pin Change Mask Register 2 + PCMSK1: 0x6b, // Pin Change Mask Register 1 + PCMSK0: 0x6a, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access + EEARH: 0x41, // EEPROM Read/Write Access + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_PSCRB = 0x20 // PSC Reset Behavior + EXTENDED_PSCRVA = 0x10 // PSCOUTnA Reset Value + EXTENDED_PSCRVB = 0x8 // PSC0UTnB Reset Value + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector Trigger Level + + // HIGH + HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PC6 as i/o pin) + HIGH_DWEN = 0x40 // Debug Wire enable + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watch-dog Timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Select Reset Vector + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTD1 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for CAN: Controller Area Network +const ( + // CANGCON: CAN General Control Register + CANGCON_ABRQ = 0x80 // Abort Request + CANGCON_OVRQ = 0x40 // Overload Frame Request + CANGCON_TTC = 0x20 // Time Trigger Communication + CANGCON_SYNTTC = 0x10 // Synchronization of TTC + CANGCON_LISTEN = 0x8 // Listening Mode + CANGCON_TEST = 0x4 // Test Mode + CANGCON_ENASTB = 0x2 // Enable / Standby + CANGCON_SWRES = 0x1 // Software Reset Request + + // CANGSTA: CAN General Status Register + CANGSTA_OVFG = 0x40 // Overload Frame Flag + CANGSTA_TXBSY = 0x10 // Transmitter Busy + CANGSTA_RXBSY = 0x8 // Receiver Busy + CANGSTA_ENFG = 0x4 // Enable Flag + CANGSTA_BOFF = 0x2 // Bus Off Mode + CANGSTA_ERRP = 0x1 // Error Passive Mode + + // CANGIT: CAN General Interrupt Register Flags + CANGIT_CANIT = 0x80 // General Interrupt Flag + CANGIT_BOFFIT = 0x40 // Bus Off Interrupt Flag + CANGIT_OVRTIM = 0x20 // Overrun CAN Timer Flag + CANGIT_BXOK = 0x10 // Burst Receive Interrupt Flag + CANGIT_SERG = 0x8 // Stuff Error General Flag + CANGIT_CERG = 0x4 // CRC Error General Flag + CANGIT_FERG = 0x2 // Form Error General Flag + CANGIT_AERG = 0x1 // Ackknowledgement Error General Flag + + // CANGIE: CAN General Interrupt Enable Register + CANGIE_ENIT = 0x80 // Enable all Interrupts + CANGIE_ENBOFF = 0x40 // Enable Bus Off Interrupt + CANGIE_ENRX = 0x20 // Enable Receive Interrupt + CANGIE_ENTX = 0x10 // Enable Transmitt Interrupt + CANGIE_ENERR = 0x8 // Enable MOb Error Interrupt + CANGIE_ENBX = 0x4 // Enable Burst Receive Interrupt + CANGIE_ENERG = 0x2 // Enable General Error Interrupt + CANGIE_ENOVRT = 0x1 // Enable CAN Timer Overrun Interrupt + + // CANEN2: Enable MOb Register 2 + CANEN2_ENMOB = 0x3f // Enable MObs + + // CANIE2: Enable Interrupt MOb Register 2 + CANIE2_IEMOB = 0x3f // Interrupt Enable MObs + + // CANSIT2: CAN Status Interrupt MOb Register 2 + CANSIT2_SIT = 0x3f // Status of Interrupt MObs + + // CANBT1: CAN Bit Timing Register 1 + CANBT1_BRP = 0x7e // Baud Rate Prescaler bits + + // CANBT2: CAN Bit Timing Register 2 + CANBT2_SJW = 0x60 // Re-Sync Jump Width bits + CANBT2_PRS = 0xe // Propagation Time Segment bits + + // CANBT3: CAN Bit Timing Register 3 + CANBT3_PHS2 = 0x70 // Phase Segment 2 bits + CANBT3_PHS1 = 0xe // Phase Segment 1 bits + CANBT3_SMP = 0x1 // Sample Type + + // CANHPMOB: Highest Priority MOb Register + CANHPMOB_HPMOB = 0xf0 // Highest Priority MOb Number bits + CANHPMOB_CGP = 0xf // CAN General Purpose bits + + // CANPAGE: Page MOb Register + CANPAGE_MOBNB = 0xf0 // MOb Number bits + CANPAGE_AINC = 0x8 // MOb Data Buffer Auto Increment (Active Low) + CANPAGE_INDX = 0x7 // Data Buffer Index bits + + // CANSTMOB: MOb Status Register + CANSTMOB_DLCW = 0x80 // Data Length Code Warning on MOb + CANSTMOB_TXOK = 0x40 // Transmit OK on MOb + CANSTMOB_RXOK = 0x20 // Receive OK on MOb + CANSTMOB_BERR = 0x10 // Bit Error on MOb + CANSTMOB_SERR = 0x8 // Stuff Error on MOb + CANSTMOB_CERR = 0x4 // CRC Error on MOb + CANSTMOB_FERR = 0x2 // Form Error on MOb + CANSTMOB_AERR = 0x1 // Ackknowledgement Error on MOb + + // CANCDMOB: MOb Control and DLC Register + CANCDMOB_CONMOB = 0xc0 // MOb Config bits + CANCDMOB_RPLV = 0x20 // Reply Valid + CANCDMOB_IDE = 0x10 // Identifier Extension + CANCDMOB_DLC = 0xf // Data Length Code bits + + // CANIDT4: Identifier Tag Register 4 + CANIDT4_IDT = 0xf8 + CANIDT4_RTRTAG = 0x4 + CANIDT4_RB1TAG = 0x2 + CANIDT4_RB0TAG = 0x1 +) + +// Bitfields for AC: Analog Comparator +const ( + // AC0CON: Analog Comparator 0 Control Register + AC0CON_AC0EN = 0x80 // Analog Comparator 0 Enable Bit + AC0CON_AC0IE = 0x40 // Analog Comparator 0 Interrupt Enable Bit + AC0CON_AC0IS = 0x30 // Analog Comparator 0 Interrupt Select Bits + AC0CON_ACCKSEL = 0x8 // Analog Comparator Clock Select + AC0CON_AC0M = 0x7 // Analog Comparator 0 Multiplexer Register + + // AC1CON: Analog Comparator 1 Control Register + AC1CON_AC1EN = 0x80 // Analog Comparator 1 Enable Bit + AC1CON_AC1IE = 0x40 // Analog Comparator 1 Interrupt Enable Bit + AC1CON_AC1IS = 0x30 // Analog Comparator 1 Interrupt Select Bit + AC1CON_AC1ICE = 0x8 // Analog Comparator 1 Interrupt Capture Enable Bit + AC1CON_AC1M = 0x7 // Analog Comparator 1 Multiplexer Register + + // AC2CON: Analog Comparator 2 Control Register + AC2CON_AC2EN = 0x80 // Analog Comparator 2 Enable Bit + AC2CON_AC2IE = 0x40 // Analog Comparator 2 Interrupt Enable Bit + AC2CON_AC2IS = 0x30 // Analog Comparator 2 Interrupt Select Bit + AC2CON_AC2M = 0x7 // Analog Comparator 2 Multiplexer Register + + // AC3CON: Analog Comparator 3 Control Register + AC3CON_AC3EN = 0x80 // Analog Comparator 3 Enable Bit + AC3CON_AC3IE = 0x40 // Analog Comparator 3 Interrupt Enable Bit + AC3CON_AC3IS = 0x30 // Analog Comparator 3 Interrupt Select Bit + AC3CON_AC3M = 0x7 // Analog Comparator 3 Multiplexer Register + + // ACSR: Analog Comparator Status Register + ACSR_AC3IF = 0x80 // Analog Comparator 3 Interrupt Flag Bit + ACSR_AC2IF = 0x40 // Analog Comparator 2 Interrupt Flag Bit + ACSR_AC1IF = 0x20 // Analog Comparator 1 Interrupt Flag Bit + ACSR_AC0IF = 0x10 // Analog Comparator 0 Interrupt Flag Bit + ACSR_AC3O = 0x8 // Analog Comparator 3 Output Bit + ACSR_AC2O = 0x4 // Analog Comparator 2 Output Bit + ACSR_AC1O = 0x2 // Analog Comparator 1 Output Bit + ACSR_AC0O = 0x1 // Analog Comparator 0 Output Bit +) + +// Bitfields for DAC: Digital-to-Analog Converter +const ( + // DACH: DAC Data Register High Byte + DACH_DACH = 0xff // DAC Data Register High Byte Bits + + // DACL: DAC Data Register Low Byte + DACL_DACL = 0xff // DAC Data Register Low Byte Bits + + // DACON: DAC Control Register + DACON_DAATE = 0x80 // DAC Auto Trigger Enable Bit + DACON_DATS = 0x70 // DAC Trigger Selection Bits + DACON_DALA = 0x4 // DAC Left Adjust + DACON_DAEN = 0x1 // DAC Enable Bit +) + +// Bitfields for CPU: CPU Registers +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable + + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // MCUCR: MCU Control Register + MCUCR_SPIPS = 0x80 // SPI Pin Select + MCUCR_PUD = 0x10 // Pull-up disable + MCUCR_IVSEL = 0x2 // Interrupt Vector Select + MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable + + // MCUSR: MCU Status Register + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BORF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 + + // PLLCSR: PLL Control And Status Register + PLLCSR_PLLF = 0x4 // PLL Factor + PLLCSR_PLLE = 0x2 // PLL Enable + PLLCSR_PLOCK = 0x1 // PLL Lock Detector + + // PRR: Power Reduction Register + PRR_PRCAN = 0x40 // Power Reduction CAN + PRR_PRPSC = 0x20 // Power Reduction PSC + PRR_PRTIM1 = 0x10 // Power Reduction Timer/Counter1 + PRR_PRTIM0 = 0x8 // Power Reduction Timer/Counter0 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRLIN = 0x2 // Power Reduction LIN UART + PRR_PRADC = 0x1 // Power Reduction ADC +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TIMSK1: Timer/Counter Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output CompareB Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output CompareA Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 + TCCR1C_FOC1B = 0x40 +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCSRB: ADC Control and Status Register B + ADCSRB_ADHSM = 0x80 // ADC High Speed Mode + ADCSRB_ISRCEN = 0x40 // Current Source Enable + ADCSRB_AREFEN = 0x20 // Analog Reference pin Enable + ADCSRB_ADTS = 0xf // ADC Auto Trigger Sources + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable + + // DIDR1: Digital Input Disable Register 0 + DIDR1_AMP2PD = 0x40 // AMP2P Pin Digital input Disable + DIDR1_ACMP0D = 0x20 // ACMP0 Pin Digital input Disable + DIDR1_AMP0PD = 0x10 // AMP0P Pin Digital input Disable + DIDR1_AMP0ND = 0x8 // AMP0N Pin Digital input Disable + DIDR1_ADC10D = 0x4 // ADC10 Pin Digital input Disable + DIDR1_ADC9D = 0x2 // ADC9 Pin Digital input Disable + DIDR1_ADC8D = 0x1 // ADC8 Pin Digital input Disable + + // AMP0CSR + AMP0CSR_AMP0EN = 0x80 + AMP0CSR_AMP0IS = 0x40 + AMP0CSR_AMP0G = 0x30 + AMP0CSR_AMPCMP0 = 0x8 // Amplifier 0 - Comparator 0 Connection + AMP0CSR_AMP0TS = 0x7 + + // AMP1CSR + AMP1CSR_AMP1EN = 0x80 + AMP1CSR_AMP1IS = 0x40 + AMP1CSR_AMP1G = 0x30 + AMP1CSR_AMPCMP1 = 0x8 // Amplifier 1 - Comparator 1 Connection + AMP1CSR_AMP1TS = 0x7 + + // AMP2CSR + AMP2CSR_AMP2EN = 0x80 + AMP2CSR_AMP2IS = 0x40 + AMP2CSR_AMP2G = 0x30 + AMP2CSR_AMPCMP2 = 0x8 // Amplifier 2 - Comparator 2 Connection + AMP2CSR_AMP2TS = 0x7 +) + +// Bitfields for LINUART: Local Interconnect Network +const ( + // LINCR: LIN Control Register + LINCR_LSWRES = 0x80 // Software Reset + LINCR_LIN13 = 0x40 // LIN Standard + LINCR_LCONF = 0x30 // LIN Configuration bits + LINCR_LENA = 0x8 // LIN or UART Enable + LINCR_LCMD = 0x7 // LIN Command and Mode bits + + // LINSIR: LIN Status and Interrupt Register + LINSIR_LIDST = 0xe0 // Identifier Status bits + LINSIR_LBUSY = 0x10 // Busy Signal + LINSIR_LERR = 0x8 // Error Interrupt + LINSIR_LIDOK = 0x4 // Identifier Interrupt + LINSIR_LTXOK = 0x2 // Transmit Performed Interrupt + LINSIR_LRXOK = 0x1 // Receive Performed Interrupt + + // LINENIR: LIN Enable Interrupt Register + LINENIR_LENERR = 0x8 // Enable Error Interrupt + LINENIR_LENIDOK = 0x4 // Enable Identifier Interrupt + LINENIR_LENTXOK = 0x2 // Enable Transmit Performed Interrupt + LINENIR_LENRXOK = 0x1 // Enable Receive Performed Interrupt + + // LINERR: LIN Error Register + LINERR_LABORT = 0x80 // Abort Flag + LINERR_LTOERR = 0x40 // Frame Time Out Error Flag + LINERR_LOVERR = 0x20 // Overrun Error Flag + LINERR_LFERR = 0x10 // Framing Error Flag + LINERR_LSERR = 0x8 // Synchronization Error Flag + LINERR_LPERR = 0x4 // Parity Error Flag + LINERR_LCERR = 0x2 // Checksum Error Flag + LINERR_LBERR = 0x1 // Bit Error Flag + + // LINBTR: LIN Bit Timing Register + LINBTR_LDISR = 0x80 // Disable Bit Timing Resynchronization + LINBTR_LBT = 0x3f // LIN Bit Timing bits + + // LINBRRL: LIN Baud Rate Low Register + LINBRRL_LDIV = 0xff + + // LINBRRH: LIN Baud Rate High Register + LINBRRH_LDIV = 0xf + + // LINDLR: LIN Data Length Register + LINDLR_LTXDL = 0xf0 // LIN Transmit Data Length bits + LINDLR_LRXDL = 0xf // LIN Receive Data Length bits + + // LINIDR: LIN Identifier Register + LINIDR_LP = 0xc0 // Parity bits + LINIDR_LID = 0x3f // Identifier bit 5 or Data Length bits + + // LINSEL: LIN Data Buffer Selection Register + LINSEL_LAINC = 0x8 // Auto Increment of Data Buffer Index (Active Low) + LINSEL_LINDX = 0x7 // FIFO LIN Data Buffer Index bits + + // LINDAT: LIN Data Register + LINDAT_LDATA = 0xff +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register + EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control 1 Bits + EICRA_ISC0 = 0x3 // External Interrupt Sense Control 0 Bits + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xf // External Interrupt Request 3 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xf // External Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0xf // Pin Change Interrupt Enables + + // PCMSK3: Pin Change Mask Register 3 + PCMSK3_PCINT = 0x7 // Pin Change Enable Masks + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0xf // Pin Change Interrupt Flags +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 + EECR_EERIE = 0x8 // EEProm Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) diff --git a/src/device/avr/atmega64c1.ld b/src/device/avr/atmega64c1.ld new file mode 100644 index 00000000..6d8707d4 --- /dev/null +++ b/src/device/avr/atmega64c1.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega64C1.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_size = 0x1000; +__num_isrs = 31; diff --git a/src/device/avr/atmega64hve2.go b/src/device/avr/atmega64hve2.go new file mode 100644 index 00000000..03d11175 --- /dev/null +++ b/src/device/avr/atmega64hve2.go @@ -0,0 +1,664 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega64HVE2.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega64hve2 + +// Device information for the ATmega64HVE2. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega64HVE2" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset + IRQ_INT0 = 1 // External Interrupt 0 + IRQ_PCINT0 = 2 // Pin Change Interrupt 0 + IRQ_PCINT1 = 3 // Pin Change Interrupt 1 + IRQ_WDT = 4 // Watchdog Timeout Interrupt + IRQ_WAKEUP = 5 // Wakeup Timer Overflow + IRQ_TIMER1_IC = 6 // Timer 1 Input capture + IRQ_TIMER1_COMPA = 7 // Timer 1 Compare Match A + IRQ_TIMER1_COMPB = 8 // Timer 1 Compare Match B + IRQ_TIMER1_OVF = 9 // Timer 1 overflow + IRQ_TIMER0_IC = 10 // Timer 0 Input Capture + IRQ_TIMER0_COMPA = 11 // Timer 0 Comapre Match A + IRQ_TIMER0_COMPB = 12 // Timer 0 Compare Match B + IRQ_TIMER0_OVF = 13 // Timer 0 Overflow + IRQ_LIN_STATUS = 14 // LIN Status Interrupt + IRQ_LIN_ERROR = 15 // LIN Error Interrupt + IRQ_SPI_STC = 16 // SPI Serial transfer complete + IRQ_VADC_CONV = 17 // Voltage ADC Instantaneous Conversion Complete + IRQ_VADC_ACC = 18 // Voltage ADC Accumulated Conversion Complete + IRQ_CADC_CONV = 19 // C-ADC Instantaneous Conversion Complete + IRQ_CADC_REG_CUR = 20 // C-ADC Regular Current + IRQ_CADC_ACC = 21 // C-ADC Accumulated Conversion Complete + IRQ_EE_READY = 22 // EEPROM Ready + IRQ_SPM = 23 // SPM Ready + IRQ_PLL = 24 // PLL Lock Change Interrupt + IRQ_max = 24 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + LOW __reg + HIGH __reg + }{ + LOW: 0x0, + HIGH: 0x1, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access + EEARH: 0x41, // EEPROM Read/Write Access + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1B __reg + TCCR1A __reg + TCNT1L __reg + TCNT1H __reg + OCR1A __reg + OCR1B __reg + TIMSK1 __reg + TIFR1 __reg + TCCR0B __reg + TCCR0A __reg + TCNT0L __reg + TCNT0H __reg + OCR0A __reg + OCR0B __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1A: 0x80, // Timer/Counter 1 Control Register A + TCNT1L: 0x84, // Timer Counter 1 Bytes + TCNT1H: 0x84, // Timer Counter 1 Bytes + OCR1A: 0x88, // Output Compare Register 1A + OCR1B: 0x89, // Output Compare Register B + TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR0B: 0x45, // Timer/Counter0 Control Register B + TCCR0A: 0x44, // Timer/Counter 0 Control Register A + TCNT0L: 0x46, // Timer Counter 0 Bytes + TCNT0H: 0x46, // Timer Counter 0 Bytes + OCR0A: 0x48, // Output Compare Register 0A + OCR0B: 0x49, // Output Compare Register B + TIMSK0: 0x6e, // Timer/Counter Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter Interrupt Flag register + } + + // I/O Port + PORT = struct { + PORTB __reg + DDRB __reg + PINB __reg + PBOV __reg + PORTA __reg + DDRA __reg + PINA __reg + }{ + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PBOV: 0xdc, // Port B Override + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control and Status Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADSCSRA __reg + ADSCSRB __reg + ADCRA __reg + ADCRB __reg + ADCRC __reg + ADCRD __reg + ADCRE __reg + ADIFR __reg + ADIMR __reg + CADRCLL __reg + CADRCLH __reg + VADICL __reg + VADICH __reg + VADAC3 __reg + VADAC2 __reg + VADAC1 __reg + VADAC0 __reg + CADICL __reg + CADICH __reg + CADAC3 __reg + CADAC2 __reg + CADAC1 __reg + CADAC0 __reg + }{ + ADSCSRA: 0xe0, // ADC Synchronization Control and Status Register + ADSCSRB: 0xe1, // ADC Synchronization Control and Status Register + ADCRA: 0xe2, // ADC Control Register A + ADCRB: 0xe3, // ADC Control Register B + ADCRC: 0xe4, // ADC Control Register B + ADCRD: 0xe5, // ADC Control Register D + ADCRE: 0xe6, // ADC Control Register E + ADIFR: 0xe7, // ADC Interrupt Flag Register + ADIMR: 0xe8, // ADC Interrupt Mask Register + CADRCLL: 0xe9, // CC-ADC Regulator Current Comparator Threshold Level + CADRCLH: 0xe9, // CC-ADC Regulator Current Comparator Threshold Level + VADICL: 0xf1, // V-ADC Instantaneous Conversion Result + VADICH: 0xf1, // V-ADC Instantaneous Conversion Result + VADAC3: 0xf6, // V-ADC Accumulated Conversion Result + VADAC2: 0xf5, // V-ADC Accumulated Conversion Result + VADAC1: 0xf4, // V-ADC Accumulated Conversion Result + VADAC0: 0xf3, // V-ADC Accumulated Conversion Result + CADICL: 0xeb, // C-ADC Instantaneous Conversion Result + CADICH: 0xeb, // C-ADC Instantaneous Conversion Result + CADAC3: 0xf0, // C-ADC Accumulated Conversion Result + CADAC2: 0xef, // C-ADC Accumulated Conversion Result + CADAC1: 0xee, // C-ADC Accumulated Conversion Result + CADAC0: 0xed, // C-ADC Accumulated Conversion Result + } + + // Bandgap + BANDGAP = struct { + BGCSRA __reg + BGCRA __reg + BGCRB __reg + BGLR __reg + }{ + BGCSRA: 0xd1, // Bandgap Control and Status Register A + BGCRA: 0xd3, // Band Gap Calibration Register A + BGCRB: 0xd2, // Band Gap Calibration Register B + BGLR: 0xd4, // Band Gap Lock Register + } + + // Local Interconnect Network + LINUART = struct { + LINCR __reg + LINSIR __reg + LINENIR __reg + LINERR __reg + LINBTR __reg + LINBRRL __reg + LINBRRH __reg + LINDLR __reg + LINIDR __reg + LINSEL __reg + LINDAT __reg + }{ + LINCR: 0xc0, // LIN Control Register + LINSIR: 0xc1, // LIN Status and Interrupt Register + LINENIR: 0xc2, // LIN Enable Interrupt Register + LINERR: 0xc3, // LIN Error Register + LINBTR: 0xc4, // LIN Bit Timing Register + LINBRRL: 0xc5, // LIN Baud Rate Low Register + LINBRRH: 0xc6, // LIN Baud Rate High Register + LINDLR: 0xc7, // LIN Data Length Register + LINIDR: 0xc8, // LIN Identifier Register + LINSEL: 0xc9, // LIN Data Buffer Selection Register + LINDAT: 0xca, // LIN Data Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + MCUCR __reg + MCUSR __reg + SOSCCALA __reg + SOSCCALB __reg + PLLCSR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + DIDR0 __reg + PRR0 __reg + CLKPR __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + SOSCCALA: 0x66, // Slow Oscillator Calibration Register A + SOSCCALB: 0x67, // Oscillator Calibration Register B + PLLCSR: 0xd8, // PLL Control and Status Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + DIDR0: 0x7e, // Digital Input Disable Register + PRR0: 0x64, // Power Reduction Register 0 + CLKPR: 0x61, // Clock Prescale Register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCICR __reg + PCIFR __reg + PCMSK1 __reg + PCMSK0 __reg + }{ + EICRA: 0x69, // External Interrupt Control Register + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + PCMSK1: 0x6c, // Pin Change Enable Mask Register 1 + PCMSK0: 0x6b, // Pin Change Enable Mask Register 0 + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + WDTCLR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + WDTCLR: 0x63, // Watchdog Timer Configuration Lock Register + } + + // Wakeup Timer + WAKEUP_TIMER = struct { + WUTCSR __reg + }{ + WUTCSR: 0x62, // Wake-up Timer Control and Status Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // LOW + LOW_WDTON = 0x80 // Watch-dog Timer always on + LOW_EESAVE = 0x40 // Preserve EEPROM through the Chip Erase cycle + LOW_SPIEN = 0x20 // Serial program downloading (SPI) enabled + LOW_BODEN = 0x10 // Brown-out detection enabled + LOW_CKDIV8 = 0x8 // Divide clock by 8 + LOW_SUT = 0x6 // Select start-up time + LOW_OSCSEL0 = 0x1 // Oscillator select + + // HIGH + HIGH_DWEN = 0x8 // Debug Wire enable + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 + EECR_EERIE = 0x8 // EEProm Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_CS = 0x7 // Clock Select1 bis + + // TCCR1A: Timer/Counter 1 Control Register A + TCCR1A_TCW1 = 0x80 // Timer/Counter Width + TCCR1A_ICEN1 = 0x40 // Input Capture Mode Enable + TCCR1A_ICNC1 = 0x20 // Input Capture Noise Canceler + TCCR1A_ICES1 = 0x10 // Input Capture Edge Select + TCCR1A_ICS1 = 0x8 // Input Capture Select + TCCR1A_WGM10 = 0x1 // Waveform Generation Mode + + // TIMSK1: Timer/Counter Interrupt Mask Register + TIMSK1_ICIE1 = 0x8 // Timer/Counter n Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x8 // Timer/Counter 1 Input Capture Flag + TIFR1_OCF1B = 0x4 // Timer/Counter1 Output Compare Flag B + TIFR1_OCF1A = 0x2 // Timer/Counter1 Output Compare Flag A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR0B: Timer/Counter0 Control Register B + TCCR0B_CS02 = 0x4 // Clock Select0 bit 2 + TCCR0B_CS01 = 0x2 // Clock Select0 bit 1 + TCCR0B_CS00 = 0x1 // Clock Select0 bit 0 + + // TCCR0A: Timer/Counter 0 Control Register A + TCCR0A_TCW0 = 0x80 // Timer/Counter Width + TCCR0A_ICEN0 = 0x40 // Input Capture Mode Enable + TCCR0A_ICNC0 = 0x20 // Input Capture Noise Canceler + TCCR0A_ICES0 = 0x10 // Input Capture Edge Select + TCCR0A_ICS0 = 0x8 // Input Capture Select + TCCR0A_WGM00 = 0x1 // Waveform Generation Mode + + // TIMSK0: Timer/Counter Interrupt Mask Register + TIMSK0_ICIE0 = 0x8 // Timer/Counter n Input Capture Interrupt Enable + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter Interrupt Flag register + TIFR0_ICF0 = 0x8 // Timer/Counter 0 Input Capture Flag + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for PORT: I/O Port +const ( + // PBOV: Port B Override + PBOV_PBOVCE = 0x80 // Port B Override Change Enable + PBOV_PBOE3 = 0x8 // Port B Override Enable 3 + PBOV_PBOE0 = 0x1 // Port B Override Enable 0 +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control and Status Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read-While-Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read-While-Write Section Read Enable + SPMCSR_LBSET = 0x8 // Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADSCSRA: ADC Synchronization Control and Status Register + ADSCSRA_SBSY = 0x4 // Synchronization Busy + ADSCSRA_SCMD = 0x3 // Synchronization Command + + // ADSCSRB: ADC Synchronization Control and Status Register + ADSCSRB_VADICPS = 0x40 // V-ADC Instantaneous Conversion Polarity Status + ADSCSRB_VADACRB = 0x20 // VADAC Data Read Out Busy + ADSCSRB_VADICRB = 0x10 // VADIC Data Read Out Busy + ADSCSRB_CADICPS = 0x4 // C-ADC Instantaneous Conversion Polarity Status + ADSCSRB_CADACRB = 0x2 // CADAC Data Read Out Busy + ADSCSRB_CADICRB = 0x1 // CADIC Data Read Out Busy + + // ADCRA: ADC Control Register A + ADCRA_ADPSEL = 0x8 // ADC Polarity Select + ADCRA_ADCMS = 0x6 // C-ADC Chopper Mode Select + ADCRA_CKSEL = 0x1 // Sampling Clock Select + + // ADCRB: ADC Control Register B + ADCRB_ADIDES = 0x18 // Instantaneous Decimation Ratio Select + ADCRB_ADADES = 0x7 // Accumulated Decimation Ratio Select + + // ADCRC: ADC Control Register B + ADCRC_CADEN = 0x80 // C-ADC Enable + ADCRC_CADRCM = 0x30 // C-ADC Regular Current Comparator Mode + ADCRC_CADRCT = 0xf // C-ADC Regular Current Count Threshold + + // ADCRD: ADC Control Register D + ADCRD_CADG = 0x38 // C-ADC Gain + ADCRD_CADPDM = 0x6 // C-ADC Pin Diagnostics Mode + ADCRD_CADDSEL = 0x1 // C-ADC Diagnostics Channel Select + + // ADCRE: ADC Control Register E + ADCRE_VADEN = 0x80 // V-ADC Enable + ADCRE_VADREFS = 0x20 // V-ADC Reference Select + ADCRE_VADPDM = 0x18 // V-ADC Pin Diagnostics Mode + ADCRE_VADMUX = 0x7 // V-ADC Channel Select + + // ADIFR: ADC Interrupt Flag Register + ADIFR_VADACIF = 0x20 // V-ADC Accumulated Voltage Interrupt Flag + ADIFR_VADICIF = 0x10 // V-DAC Instantaneous Voltage Interrupt Flag + ADIFR_CADRCIF = 0x4 // C-ADC Regulator Current Interrupt Flag + ADIFR_CADACIF = 0x2 // C-ADC Accumulated Current Interrupt Flag + ADIFR_CADICIF = 0x1 // C-ADC Instantaneous Current Interrupt Flag + + // ADIMR: ADC Interrupt Mask Register + ADIMR_VADACIE = 0x20 // V-ADC Accumulated Voltage Interrupt Enable + ADIMR_VADICIE = 0x10 // V-DAC Instantaneous Voltage Interrupt Enable + ADIMR_CADRCIE = 0x4 // C-ADC Regulator Current Interrupt Enable + ADIMR_CADACIE = 0x2 // C-ADC Accumulated Current Interrupt Enable + ADIMR_CADICIE = 0x1 // C-ADC Instantaneous Current Interrupt Enable +) + +// Bitfields for BANDGAP: Bandgap +const ( + // BGCSRA: Bandgap Control and Status Register A + BGCSRA_BGSC = 0x7 // Band Gap Sample Configuration + + // BGCRA: Band Gap Calibration Register A + BGCRA_BGCN = 0xff // Band Gap Calibration Nominal + + // BGCRB: Band Gap Calibration Register B + BGCRB_BGCL = 0xff // Band Gap Calibration Linear + + // BGLR: Band Gap Lock Register + BGLR_BGPLE = 0x2 // Band Gap Lock Enable + BGLR_BGPL = 0x1 // Band Gap Lock +) + +// Bitfields for LINUART: Local Interconnect Network +const ( + // LINCR: LIN Control Register + LINCR_LSWRES = 0x80 // Software Reset + LINCR_LIN13 = 0x40 // LIN Standard + LINCR_LCONF = 0x30 // LIN Configuration bits + LINCR_LENA = 0x8 // LIN or UART Enable + LINCR_LCMD = 0x7 // LIN Command and Mode bits + + // LINSIR: LIN Status and Interrupt Register + LINSIR_LIDST = 0xe0 // Identifier Status bits + LINSIR_LBUSY = 0x10 // Busy Signal + LINSIR_LERR = 0x8 // Error Interrupt + LINSIR_LIDOK = 0x4 // Identifier Interrupt + LINSIR_LTXOK = 0x2 // Transmit Performed Interrupt + LINSIR_LRXOK = 0x1 // Receive Performed Interrupt + + // LINENIR: LIN Enable Interrupt Register + LINENIR_LENERR = 0x8 // Enable Error Interrupt + LINENIR_LENIDOK = 0x4 // Enable Identifier Interrupt + LINENIR_LENTXOK = 0x2 // Enable Transmit Performed Interrupt + LINENIR_LENRXOK = 0x1 // Enable Receive Performed Interrupt + + // LINERR: LIN Error Register + LINERR_LABORT = 0x80 // Abort Flag + LINERR_LTOERR = 0x40 // Frame Time Out Error Flag + LINERR_LOVERR = 0x20 // Overrun Error Flag + LINERR_LFERR = 0x10 // Framing Error Flag + LINERR_LSERR = 0x8 // Synchronization Error Flag + LINERR_LPERR = 0x4 // Parity Error Flag + LINERR_LCERR = 0x2 // Checksum Error Flag + LINERR_LBERR = 0x1 // Bit Error Flag + + // LINBTR: LIN Bit Timing Register + LINBTR_LDISR = 0x80 // Disable Bit Timing Resynchronization + LINBTR_LBT = 0x3f // LIN Bit Timing bits + + // LINBRRL: LIN Baud Rate Low Register + LINBRRL_LDIV = 0xff + + // LINBRRH: LIN Baud Rate High Register + LINBRRH_LDIV = 0xf + + // LINDLR: LIN Data Length Register + LINDLR_LTXDL = 0xf0 // LIN Transmit Data Length bits + LINDLR_LRXDL = 0xf // LIN Receive Data Length bits + + // LINIDR: LIN Identifier Register + LINIDR_LP = 0xc0 // Parity bits + LINIDR_LID = 0x3f // Identifier bit 5 or Data Length bits + + // LINSEL: LIN Data Buffer Selection Register + LINSEL_LAINC = 0x8 // Auto Increment of Data Buffer Index (Active Low) + LINSEL_LINDX = 0x7 // FIFO LIN Data Buffer Index bits + + // LINDAT: LIN Data Register + LINDAT_LDATA = 0xff +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // MCUCR: MCU Control Register + MCUCR_CKOE = 0x20 // Clock Output Enable + MCUCR_PUD = 0x10 // Pull-up disable + MCUCR_IVSEL = 0x2 // Interrupt Vector Select + MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable + + // MCUSR: MCU Status Register + MCUSR_OCDRF = 0x10 // OCD Reset Flag + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BODRF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // PLLCSR: PLL Control and Status Register + PLLCSR_SWEN = 0x20 // PLL Software Enable + PLLCSR_LOCK = 0x10 // PLL Lock + PLLCSR_PLLCIF = 0x2 // PLL Lock Change Interrupt Flag + PLLCSR_PLLCIE = 0x1 // PLL Lock Change Interrupt Enable + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // DIDR0: Digital Input Disable Register + DIDR0_PA1DID = 0x2 // When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled. + DIDR0_PA0DID = 0x1 // When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled. + + // PRR0: Power Reduction Register 0 + PRR0_PRLIN = 0x8 // Power Reduction LIN UART Interface + PRR0_PRSPI = 0x4 // Power reduction SPI + PRR0_PRTIM1 = 0x2 // Power Reduction Timer/Counter1 + PRR0_PRTIM0 = 0x1 // Power Reduction Timer/Counter0 + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0x3 // Clock Prescaler Select Bits +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register + EICRA_ISC01 = 0x2 // External Interrupt Sense Control 0 Bit 1 + EICRA_ISC00 = 0x1 // External Interrupt Sense Control 0 Bit 0 + + // EIMSK: External Interrupt Mask Register + EIMSK_INT0 = 0x1 // External Interrupt Request 0 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF0 = 0x1 // External Interrupt Flag 0 + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0x3 // Pin Change Interrupt Enables + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0x3 // Pin Change Interrupt Flags +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable + + // WDTCLR: Watchdog Timer Configuration Lock Register + WDTCLR_WDCL = 0x6 // Watchdog Timer Comfiguration Lock bits + WDTCLR_WDCLE = 0x1 // Watchdog Timer Comfiguration Lock Enable +) + +// Bitfields for WAKEUP_TIMER: Wakeup Timer +const ( + // WUTCSR: Wake-up Timer Control and Status Register + WUTCSR_WUTIF = 0x80 // Wake-up Timer Interrupt Flag + WUTCSR_WUTIE = 0x40 // Wake-up Timer Interrupt Enable + WUTCSR_WUTR = 0x10 // Wake-up Timer Reset + WUTCSR_WUTE = 0x8 // Wake-up Timer Enable + WUTCSR_WUTP = 0x7 // Wake-up Timer Prescaler Bits +) diff --git a/src/device/avr/atmega64hve2.ld b/src/device/avr/atmega64hve2.ld new file mode 100644 index 00000000..e443aec4 --- /dev/null +++ b/src/device/avr/atmega64hve2.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega64HVE2.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_size = 0x1000; +__num_isrs = 25; diff --git a/src/device/avr/atmega64m1.go b/src/device/avr/atmega64m1.go new file mode 100644 index 00000000..fdc932a6 --- /dev/null +++ b/src/device/avr/atmega64m1.go @@ -0,0 +1,1019 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega64M1.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega64m1 + +// Device information for the ATmega64M1. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega64M1" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset + IRQ_ANACOMP0 = 1 // Analog Comparator 0 + IRQ_ANACOMP1 = 2 // Analog Comparator 1 + IRQ_ANACOMP2 = 3 // Analog Comparator 2 + IRQ_ANACOMP3 = 4 // Analog Comparator 3 + IRQ_PSC_FAULT = 5 // PSC Fault + IRQ_PSC_EC = 6 // PSC End of Cycle + IRQ_INT0 = 7 // External Interrupt Request 0 + IRQ_INT1 = 8 // External Interrupt Request 1 + IRQ_INT2 = 9 // External Interrupt Request 2 + IRQ_INT3 = 10 // External Interrupt Request 3 + IRQ_TIMER1_CAPT = 11 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 12 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 13 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 14 // Timer1/Counter1 Overflow + IRQ_TIMER0_COMPA = 15 // Timer/Counter0 Compare Match A + IRQ_TIMER0_COMPB = 16 // Timer/Counter0 Compare Match B + IRQ_TIMER0_OVF = 17 // Timer/Counter0 Overflow + IRQ_CAN_INT = 18 // CAN MOB, Burst, General Errors + IRQ_CAN_TOVF = 19 // CAN Timer Overflow + IRQ_LIN_TC = 20 // LIN Transfer Complete + IRQ_LIN_ERR = 21 // LIN Error + IRQ_PCINT0 = 22 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 23 // Pin Change Interrupt Request 1 + IRQ_PCINT2 = 24 // Pin Change Interrupt Request 2 + IRQ_PCINT3 = 25 // Pin Change Interrupt Request 3 + IRQ_SPI_STC = 26 // SPI Serial Transfer Complete + IRQ_ADC = 27 // ADC Conversion Complete + IRQ_WDT = 28 // Watchdog Time-Out Interrupt + IRQ_EE_READY = 29 // EEPROM Ready + IRQ_SPM_READY = 30 // Store Program Memory Read + IRQ_max = 30 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // I/O Port + PORT = struct { + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + }{ + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Port E Data Register + DDRE: 0x2d, // Port E Data Direction Register + PINE: 0x2c, // Port E Input Pins + } + + // Controller Area Network + CAN = struct { + CANGCON __reg + CANGSTA __reg + CANGIT __reg + CANGIE __reg + CANEN2 __reg + CANEN1 __reg + CANIE2 __reg + CANIE1 __reg + CANSIT2 __reg + CANSIT1 __reg + CANBT1 __reg + CANBT2 __reg + CANBT3 __reg + CANTCON __reg + CANTIML __reg + CANTIMH __reg + CANTTCL __reg + CANTTCH __reg + CANTEC __reg + CANREC __reg + CANHPMOB __reg + CANPAGE __reg + CANSTMOB __reg + CANCDMOB __reg + CANIDT4 __reg + CANIDT3 __reg + CANIDT2 __reg + CANIDT1 __reg + CANIDM4 __reg + CANIDM3 __reg + CANIDM2 __reg + CANIDM1 __reg + CANSTML __reg + CANSTMH __reg + CANMSG __reg + }{ + CANGCON: 0xd8, // CAN General Control Register + CANGSTA: 0xd9, // CAN General Status Register + CANGIT: 0xda, // CAN General Interrupt Register Flags + CANGIE: 0xdb, // CAN General Interrupt Enable Register + CANEN2: 0xdc, // Enable MOb Register 2 + CANEN1: 0xdd, // Enable MOb Register 1(empty) + CANIE2: 0xde, // Enable Interrupt MOb Register 2 + CANIE1: 0xdf, // Enable Interrupt MOb Register 1 (empty) + CANSIT2: 0xe0, // CAN Status Interrupt MOb Register 2 + CANSIT1: 0xe1, // CAN Status Interrupt MOb Register 1 (empty) + CANBT1: 0xe2, // CAN Bit Timing Register 1 + CANBT2: 0xe3, // CAN Bit Timing Register 2 + CANBT3: 0xe4, // CAN Bit Timing Register 3 + CANTCON: 0xe5, // Timer Control Register + CANTIML: 0xe6, // Timer Register Low + CANTIMH: 0xe7, // Timer Register High + CANTTCL: 0xe8, // TTC Timer Register Low + CANTTCH: 0xe9, // TTC Timer Register High + CANTEC: 0xea, // Transmit Error Counter Register + CANREC: 0xeb, // Receive Error Counter Register + CANHPMOB: 0xec, // Highest Priority MOb Register + CANPAGE: 0xed, // Page MOb Register + CANSTMOB: 0xee, // MOb Status Register + CANCDMOB: 0xef, // MOb Control and DLC Register + CANIDT4: 0xf0, // Identifier Tag Register 4 + CANIDT3: 0xf1, // Identifier Tag Register 3 + CANIDT2: 0xf2, // Identifier Tag Register 2 + CANIDT1: 0xf3, // Identifier Tag Register 1 + CANIDM4: 0xf4, // Identifier Mask Register 4 + CANIDM3: 0xf5, // Identifier Mask Register 3 + CANIDM2: 0xf6, // Identifier Mask Register 2 + CANIDM1: 0xf7, // Identifier Mask Register 1 + CANSTML: 0xf8, // Time Stamp Register Low + CANSTMH: 0xf9, // Time Stamp Register High + CANMSG: 0xfa, // Message Data Register + } + + // Analog Comparator + AC = struct { + AC0CON __reg + AC1CON __reg + AC2CON __reg + AC3CON __reg + ACSR __reg + }{ + AC0CON: 0x94, // Analog Comparator 0 Control Register + AC1CON: 0x95, // Analog Comparator 1 Control Register + AC2CON: 0x96, // Analog Comparator 2 Control Register + AC3CON: 0x97, // Analog Comparator 3 Control Register + ACSR: 0x50, // Analog Comparator Status Register + } + + // Digital-to-Analog Converter + DAC = struct { + DACH __reg + DACL __reg + DACON __reg + }{ + DACH: 0x92, // DAC Data Register High Byte + DACL: 0x91, // DAC Data Register Low Byte + DACON: 0x90, // DAC Control Register + } + + // CPU Registers + CPU = struct { + SPMCSR __reg + SREG __reg + SPL __reg + SPH __reg + MCUCR __reg + MCUSR __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PLLCSR __reg + PRR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x3a, // General Purpose IO Register 2 + GPIOR1: 0x39, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PLLCSR: 0x49, // PLL Control And Status Register + PRR: 0x64, // Power Reduction Register + } + + // Timer/Counter, 8-bit + TC8 = struct { + TIMSK0 __reg + TIFR0 __reg + TCCR0A __reg + TCCR0B __reg + TCNT0 __reg + OCR0A __reg + OCR0B __reg + }{ + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + TCCR0A: 0x44, // Timer/Counter Control Register A + TCCR0B: 0x45, // Timer/Counter Control Register B + TCNT0: 0x46, // Timer/Counter0 + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + ADCSRB __reg + DIDR0 __reg + DIDR1 __reg + AMP0CSR __reg + AMP1CSR __reg + AMP2CSR __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCSRA: 0x7a, // The ADC Control and Status register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRB: 0x7b, // ADC Control and Status Register B + DIDR0: 0x7e, // Digital Input Disable Register 0 + DIDR1: 0x7f, // Digital Input Disable Register 0 + AMP0CSR: 0x75, + AMP1CSR: 0x76, + AMP2CSR: 0x77, + } + + // Local Interconnect Network + LINUART = struct { + LINCR __reg + LINSIR __reg + LINENIR __reg + LINERR __reg + LINBTR __reg + LINBRRL __reg + LINBRRH __reg + LINDLR __reg + LINIDR __reg + LINSEL __reg + LINDAT __reg + }{ + LINCR: 0xc8, // LIN Control Register + LINSIR: 0xc9, // LIN Status and Interrupt Register + LINENIR: 0xca, // LIN Enable Interrupt Register + LINERR: 0xcb, // LIN Error Register + LINBTR: 0xcc, // LIN Bit Timing Register + LINBRRL: 0xcd, // LIN Baud Rate Low Register + LINBRRH: 0xce, // LIN Baud Rate High Register + LINDLR: 0xcf, // LIN Data Length Register + LINIDR: 0xd0, // LIN Identifier Register + LINSEL: 0xd1, // LIN Data Buffer Selection Register + LINDAT: 0xd2, // LIN Data Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCICR __reg + PCMSK3 __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + PCMSK3: 0x6d, // Pin Change Mask Register 3 + PCMSK2: 0x6c, // Pin Change Mask Register 2 + PCMSK1: 0x6b, // Pin Change Mask Register 1 + PCMSK0: 0x6a, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Read/Write Access + EEARH: 0x41, // EEPROM Read/Write Access + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Power Stage Controller + PSC = struct { + PIFR __reg + PIM __reg + PMIC2 __reg + PMIC1 __reg + PMIC0 __reg + PCTL __reg + POC __reg + PCNF __reg + PSYNC __reg + POCR_RBL __reg + POCR_RBH __reg + POCR2SBL __reg + POCR2SBH __reg + POCR2RAL __reg + POCR2RAH __reg + POCR2SAL __reg + POCR2SAH __reg + POCR1SBL __reg + POCR1SBH __reg + POCR1RAL __reg + POCR1RAH __reg + POCR1SAL __reg + POCR1SAH __reg + POCR0SBL __reg + POCR0SBH __reg + POCR0RAL __reg + POCR0RAH __reg + POCR0SAL __reg + POCR0SAH __reg + }{ + PIFR: 0xbc, // PSC Interrupt Flag Register + PIM: 0xbb, // PSC Interrupt Mask Register + PMIC2: 0xba, // PSC Module 2 Input Control Register + PMIC1: 0xb9, // PSC Module 1 Input Control Register + PMIC0: 0xb8, // PSC Module 0 Input Control Register + PCTL: 0xb7, // PSC Control Register + POC: 0xb6, // PSC Output Configuration + PCNF: 0xb5, // PSC Configuration Register + PSYNC: 0xb4, // PSC Synchro Configuration + POCR_RBL: 0xb2, // PSC Output Compare RB Register + POCR_RBH: 0xb2, // PSC Output Compare RB Register + POCR2SBL: 0xb0, // PSC Module 2 Output Compare SB Register + POCR2SBH: 0xb0, // PSC Module 2 Output Compare SB Register + POCR2RAL: 0xae, // PSC Module 2 Output Compare RA Register + POCR2RAH: 0xae, // PSC Module 2 Output Compare RA Register + POCR2SAL: 0xac, // PSC Module 2 Output Compare SA Register + POCR2SAH: 0xac, // PSC Module 2 Output Compare SA Register + POCR1SBL: 0xaa, // PSC Module 1 Output Compare SB Register + POCR1SBH: 0xaa, // PSC Module 1 Output Compare SB Register + POCR1RAL: 0xa8, // PSC Module 1 Output Compare RA Register + POCR1RAH: 0xa8, // PSC Module 1 Output Compare RA Register + POCR1SAL: 0xa6, // PSC Output Compare SA Register + POCR1SAH: 0xa6, // PSC Output Compare SA Register + POCR0SBL: 0xa4, // PSC Output Compare SB Register + POCR0SBH: 0xa4, // PSC Output Compare SB Register + POCR0RAL: 0xa2, // PSC Module 0 Output Compare RA Register + POCR0RAH: 0xa2, // PSC Module 0 Output Compare RA Register + POCR0SAL: 0xa0, // PSC Module 0 Output Compare SA Register + POCR0SAH: 0xa0, // PSC Module 0 Output Compare SA Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_PSCRB = 0x20 // PSC Reset Behavior + EXTENDED_PSCRVA = 0x10 // PSCOUTnA Reset Value + EXTENDED_PSCRVB = 0x8 // PSC0UTnB Reset Value + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector Trigger Level + + // HIGH + HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PC6 as i/o pin) + HIGH_DWEN = 0x40 // Debug Wire enable + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watch-dog Timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Select Reset Vector + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTD1 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for CAN: Controller Area Network +const ( + // CANGCON: CAN General Control Register + CANGCON_ABRQ = 0x80 // Abort Request + CANGCON_OVRQ = 0x40 // Overload Frame Request + CANGCON_TTC = 0x20 // Time Trigger Communication + CANGCON_SYNTTC = 0x10 // Synchronization of TTC + CANGCON_LISTEN = 0x8 // Listening Mode + CANGCON_TEST = 0x4 // Test Mode + CANGCON_ENASTB = 0x2 // Enable / Standby + CANGCON_SWRES = 0x1 // Software Reset Request + + // CANGSTA: CAN General Status Register + CANGSTA_OVFG = 0x40 // Overload Frame Flag + CANGSTA_TXBSY = 0x10 // Transmitter Busy + CANGSTA_RXBSY = 0x8 // Receiver Busy + CANGSTA_ENFG = 0x4 // Enable Flag + CANGSTA_BOFF = 0x2 // Bus Off Mode + CANGSTA_ERRP = 0x1 // Error Passive Mode + + // CANGIT: CAN General Interrupt Register Flags + CANGIT_CANIT = 0x80 // General Interrupt Flag + CANGIT_BOFFIT = 0x40 // Bus Off Interrupt Flag + CANGIT_OVRTIM = 0x20 // Overrun CAN Timer Flag + CANGIT_BXOK = 0x10 // Burst Receive Interrupt Flag + CANGIT_SERG = 0x8 // Stuff Error General Flag + CANGIT_CERG = 0x4 // CRC Error General Flag + CANGIT_FERG = 0x2 // Form Error General Flag + CANGIT_AERG = 0x1 // Ackknowledgement Error General Flag + + // CANGIE: CAN General Interrupt Enable Register + CANGIE_ENIT = 0x80 // Enable all Interrupts + CANGIE_ENBOFF = 0x40 // Enable Bus Off Interrupt + CANGIE_ENRX = 0x20 // Enable Receive Interrupt + CANGIE_ENTX = 0x10 // Enable Transmitt Interrupt + CANGIE_ENERR = 0x8 // Enable MOb Error Interrupt + CANGIE_ENBX = 0x4 // Enable Burst Receive Interrupt + CANGIE_ENERG = 0x2 // Enable General Error Interrupt + CANGIE_ENOVRT = 0x1 // Enable CAN Timer Overrun Interrupt + + // CANEN2: Enable MOb Register 2 + CANEN2_ENMOB = 0x3f // Enable MObs + + // CANIE2: Enable Interrupt MOb Register 2 + CANIE2_IEMOB = 0x3f // Interrupt Enable MObs + + // CANSIT2: CAN Status Interrupt MOb Register 2 + CANSIT2_SIT = 0x3f // Status of Interrupt MObs + + // CANBT1: CAN Bit Timing Register 1 + CANBT1_BRP = 0x7e // Baud Rate Prescaler bits + + // CANBT2: CAN Bit Timing Register 2 + CANBT2_SJW = 0x60 // Re-Sync Jump Width bits + CANBT2_PRS = 0xe // Propagation Time Segment bits + + // CANBT3: CAN Bit Timing Register 3 + CANBT3_PHS2 = 0x70 // Phase Segment 2 bits + CANBT3_PHS1 = 0xe // Phase Segment 1 bits + CANBT3_SMP = 0x1 // Sample Type + + // CANHPMOB: Highest Priority MOb Register + CANHPMOB_HPMOB = 0xf0 // Highest Priority MOb Number bits + CANHPMOB_CGP = 0xf // CAN General Purpose bits + + // CANPAGE: Page MOb Register + CANPAGE_MOBNB = 0xf0 // MOb Number bits + CANPAGE_AINC = 0x8 // MOb Data Buffer Auto Increment (Active Low) + CANPAGE_INDX = 0x7 // Data Buffer Index bits + + // CANSTMOB: MOb Status Register + CANSTMOB_DLCW = 0x80 // Data Length Code Warning on MOb + CANSTMOB_TXOK = 0x40 // Transmit OK on MOb + CANSTMOB_RXOK = 0x20 // Receive OK on MOb + CANSTMOB_BERR = 0x10 // Bit Error on MOb + CANSTMOB_SERR = 0x8 // Stuff Error on MOb + CANSTMOB_CERR = 0x4 // CRC Error on MOb + CANSTMOB_FERR = 0x2 // Form Error on MOb + CANSTMOB_AERR = 0x1 // Ackknowledgement Error on MOb + + // CANCDMOB: MOb Control and DLC Register + CANCDMOB_CONMOB = 0xc0 // MOb Config bits + CANCDMOB_RPLV = 0x20 // Reply Valid + CANCDMOB_IDE = 0x10 // Identifier Extension + CANCDMOB_DLC = 0xf // Data Length Code bits + + // CANIDT4: Identifier Tag Register 4 + CANIDT4_IDT = 0xf8 + CANIDT4_RTRTAG = 0x4 + CANIDT4_RB1TAG = 0x2 + CANIDT4_RB0TAG = 0x1 +) + +// Bitfields for AC: Analog Comparator +const ( + // AC0CON: Analog Comparator 0 Control Register + AC0CON_AC0EN = 0x80 // Analog Comparator 0 Enable Bit + AC0CON_AC0IE = 0x40 // Analog Comparator 0 Interrupt Enable Bit + AC0CON_AC0IS = 0x30 // Analog Comparator 0 Interrupt Select Bits + AC0CON_ACCKSEL = 0x8 // Analog Comparator Clock Select + AC0CON_AC0M = 0x7 // Analog Comparator 0 Multiplexer Register + + // AC1CON: Analog Comparator 1 Control Register + AC1CON_AC1EN = 0x80 // Analog Comparator 1 Enable Bit + AC1CON_AC1IE = 0x40 // Analog Comparator 1 Interrupt Enable Bit + AC1CON_AC1IS = 0x30 // Analog Comparator 1 Interrupt Select Bit + AC1CON_AC1ICE = 0x8 // Analog Comparator 1 Interrupt Capture Enable Bit + AC1CON_AC1M = 0x7 // Analog Comparator 1 Multiplexer Register + + // AC2CON: Analog Comparator 2 Control Register + AC2CON_AC2EN = 0x80 // Analog Comparator 2 Enable Bit + AC2CON_AC2IE = 0x40 // Analog Comparator 2 Interrupt Enable Bit + AC2CON_AC2IS = 0x30 // Analog Comparator 2 Interrupt Select Bit + AC2CON_AC2M = 0x7 // Analog Comparator 2 Multiplexer Register + + // AC3CON: Analog Comparator 3 Control Register + AC3CON_AC3EN = 0x80 // Analog Comparator 3 Enable Bit + AC3CON_AC3IE = 0x40 // Analog Comparator 3 Interrupt Enable Bit + AC3CON_AC3IS = 0x30 // Analog Comparator 3 Interrupt Select Bit + AC3CON_AC3M = 0x7 // Analog Comparator 3 Multiplexer Register + + // ACSR: Analog Comparator Status Register + ACSR_AC3IF = 0x80 // Analog Comparator 3 Interrupt Flag Bit + ACSR_AC2IF = 0x40 // Analog Comparator 2 Interrupt Flag Bit + ACSR_AC1IF = 0x20 // Analog Comparator 1 Interrupt Flag Bit + ACSR_AC0IF = 0x10 // Analog Comparator 0 Interrupt Flag Bit + ACSR_AC3O = 0x8 // Analog Comparator 3 Output Bit + ACSR_AC2O = 0x4 // Analog Comparator 2 Output Bit + ACSR_AC1O = 0x2 // Analog Comparator 1 Output Bit + ACSR_AC0O = 0x1 // Analog Comparator 0 Output Bit +) + +// Bitfields for DAC: Digital-to-Analog Converter +const ( + // DACH: DAC Data Register High Byte + DACH_DACH = 0xff // DAC Data Register High Byte Bits + + // DACL: DAC Data Register Low Byte + DACL_DACL = 0xff // DAC Data Register Low Byte Bits + + // DACON: DAC Control Register + DACON_DAATE = 0x80 // DAC Auto Trigger Enable Bit + DACON_DATS = 0x70 // DAC Trigger Selection Bits + DACON_DALA = 0x4 // DAC Left Adjust + DACON_DAEN = 0x1 // DAC Enable Bit +) + +// Bitfields for CPU: CPU Registers +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable + + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // MCUCR: MCU Control Register + MCUCR_SPIPS = 0x80 // SPI Pin Select + MCUCR_PUD = 0x10 // Pull-up disable + MCUCR_IVSEL = 0x2 // Interrupt Vector Select + MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable + + // MCUSR: MCU Status Register + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BORF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 + + // PLLCSR: PLL Control And Status Register + PLLCSR_PLLF = 0x4 // PLL Factor + PLLCSR_PLLE = 0x2 // PLL Enable + PLLCSR_PLOCK = 0x1 // PLL Lock Detector + + // PRR: Power Reduction Register + PRR_PRCAN = 0x40 // Power Reduction CAN + PRR_PRPSC = 0x20 // Power Reduction PSC + PRR_PRTIM1 = 0x10 // Power Reduction Timer/Counter1 + PRR_PRTIM0 = 0x8 // Power Reduction Timer/Counter0 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRLIN = 0x2 // Power Reduction LIN UART + PRR_PRADC = 0x1 // Power Reduction ADC +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TIMSK1: Timer/Counter Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output CompareB Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output CompareA Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 + TCCR1C_FOC1B = 0x40 +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCSRB: ADC Control and Status Register B + ADCSRB_ADHSM = 0x80 // ADC High Speed Mode + ADCSRB_ISRCEN = 0x40 // Current Source Enable + ADCSRB_AREFEN = 0x20 // Analog Reference pin Enable + ADCSRB_ADTS = 0xf // ADC Auto Trigger Sources + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable + DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable + DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable + DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable + DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable + DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable + DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable + DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable + + // DIDR1: Digital Input Disable Register 0 + DIDR1_AMP2PD = 0x40 // AMP2P Pin Digital input Disable + DIDR1_ACMP0D = 0x20 // ACMP0 Pin Digital input Disable + DIDR1_AMP0PD = 0x10 // AMP0P Pin Digital input Disable + DIDR1_AMP0ND = 0x8 // AMP0N Pin Digital input Disable + DIDR1_ADC10D = 0x4 // ADC10 Pin Digital input Disable + DIDR1_ADC9D = 0x2 // ADC9 Pin Digital input Disable + DIDR1_ADC8D = 0x1 // ADC8 Pin Digital input Disable + + // AMP0CSR + AMP0CSR_AMP0EN = 0x80 + AMP0CSR_AMP0IS = 0x40 + AMP0CSR_AMP0G = 0x30 + AMP0CSR_AMPCMP0 = 0x8 // Amplifier 0 - Comparator 0 Connection + AMP0CSR_AMP0TS = 0x7 + + // AMP1CSR + AMP1CSR_AMP1EN = 0x80 + AMP1CSR_AMP1IS = 0x40 + AMP1CSR_AMP1G = 0x30 + AMP1CSR_AMPCMP1 = 0x8 // Amplifier 1 - Comparator 1 Connection + AMP1CSR_AMP1TS = 0x7 + + // AMP2CSR + AMP2CSR_AMP2EN = 0x80 + AMP2CSR_AMP2IS = 0x40 + AMP2CSR_AMP2G = 0x30 + AMP2CSR_AMPCMP2 = 0x8 // Amplifier 2 - Comparator 2 Connection + AMP2CSR_AMP2TS = 0x7 +) + +// Bitfields for LINUART: Local Interconnect Network +const ( + // LINCR: LIN Control Register + LINCR_LSWRES = 0x80 // Software Reset + LINCR_LIN13 = 0x40 // LIN Standard + LINCR_LCONF = 0x30 // LIN Configuration bits + LINCR_LENA = 0x8 // LIN or UART Enable + LINCR_LCMD = 0x7 // LIN Command and Mode bits + + // LINSIR: LIN Status and Interrupt Register + LINSIR_LIDST = 0xe0 // Identifier Status bits + LINSIR_LBUSY = 0x10 // Busy Signal + LINSIR_LERR = 0x8 // Error Interrupt + LINSIR_LIDOK = 0x4 // Identifier Interrupt + LINSIR_LTXOK = 0x2 // Transmit Performed Interrupt + LINSIR_LRXOK = 0x1 // Receive Performed Interrupt + + // LINENIR: LIN Enable Interrupt Register + LINENIR_LENERR = 0x8 // Enable Error Interrupt + LINENIR_LENIDOK = 0x4 // Enable Identifier Interrupt + LINENIR_LENTXOK = 0x2 // Enable Transmit Performed Interrupt + LINENIR_LENRXOK = 0x1 // Enable Receive Performed Interrupt + + // LINERR: LIN Error Register + LINERR_LABORT = 0x80 // Abort Flag + LINERR_LTOERR = 0x40 // Frame Time Out Error Flag + LINERR_LOVERR = 0x20 // Overrun Error Flag + LINERR_LFERR = 0x10 // Framing Error Flag + LINERR_LSERR = 0x8 // Synchronization Error Flag + LINERR_LPERR = 0x4 // Parity Error Flag + LINERR_LCERR = 0x2 // Checksum Error Flag + LINERR_LBERR = 0x1 // Bit Error Flag + + // LINBTR: LIN Bit Timing Register + LINBTR_LDISR = 0x80 // Disable Bit Timing Resynchronization + LINBTR_LBT = 0x3f // LIN Bit Timing bits + + // LINBRRL: LIN Baud Rate Low Register + LINBRRL_LDIV = 0xff + + // LINBRRH: LIN Baud Rate High Register + LINBRRH_LDIV = 0xf + + // LINDLR: LIN Data Length Register + LINDLR_LTXDL = 0xf0 // LIN Transmit Data Length bits + LINDLR_LRXDL = 0xf // LIN Receive Data Length bits + + // LINIDR: LIN Identifier Register + LINIDR_LP = 0xc0 // Parity bits + LINIDR_LID = 0x3f // Identifier bit 5 or Data Length bits + + // LINSEL: LIN Data Buffer Selection Register + LINSEL_LAINC = 0x8 // Auto Increment of Data Buffer Index (Active Low) + LINSEL_LINDX = 0x7 // FIFO LIN Data Buffer Index bits + + // LINDAT: LIN Data Register + LINDAT_LDATA = 0xff +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register + EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control 1 Bits + EICRA_ISC0 = 0x3 // External Interrupt Sense Control 0 Bits + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xf // External Interrupt Request 3 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xf // External Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0xf // Pin Change Interrupt Enables + + // PCMSK3: Pin Change Mask Register 3 + PCMSK3_PCINT = 0x7 // Pin Change Enable Masks + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0xf // Pin Change Interrupt Flags +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 + EECR_EERIE = 0x8 // EEProm Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for PSC: Power Stage Controller +const ( + // PIFR: PSC Interrupt Flag Register + PIFR_PEV = 0xe // PSC External Event 2 Interrupt + PIFR_PEOP = 0x1 // PSC End of Cycle Interrupt + + // PIM: PSC Interrupt Mask Register + PIM_PEVE = 0xe // External Event 2 Interrupt Enable + PIM_PEOPE = 0x1 // PSC End of Cycle Interrupt Enable + + // PMIC2: PSC Module 2 Input Control Register + PMIC2_POVEN2 = 0x80 // PSC Module 2 Overlap Enable + PMIC2_PISEL2 = 0x40 // PSC Module 2 Input Select + PMIC2_PELEV2 = 0x20 // PSC Module 2 Input Level Selector + PMIC2_PFLTE2 = 0x10 // PSC Module 2 Input Filter Enable + PMIC2_PAOC2 = 0x8 // PSC Module 2 Asynchronous Output Control + PMIC2_PRFM2 = 0x7 // PSC Module 2 Input Mode bits + + // PMIC1: PSC Module 1 Input Control Register + PMIC1_POVEN1 = 0x80 // PSC Module 1 Overlap Enable + PMIC1_PISEL1 = 0x40 // PSC Module 1 Input Select + PMIC1_PELEV1 = 0x20 // PSC Module 1 Input Level Selector + PMIC1_PFLTE1 = 0x10 // PSC Module 1 Input Filter Enable + PMIC1_PAOC1 = 0x8 // PSC Module 1 Asynchronous Output Control + PMIC1_PRFM1 = 0x7 // PSC Module 1 Input Mode bits + + // PMIC0: PSC Module 0 Input Control Register + PMIC0_POVEN0 = 0x80 // PSC Module 0 Overlap Enable + PMIC0_PISEL0 = 0x40 // PSC Module 0 Input Select + PMIC0_PELEV0 = 0x20 // PSC Module 0 Input Level Selector + PMIC0_PFLTE0 = 0x10 // PSC Module 0 Input Filter Enable + PMIC0_PAOC0 = 0x8 // PSC Module 0 Asynchronous Output Control + PMIC0_PRFM0 = 0x7 // PSC Module 0 Input Mode bits + + // PCTL: PSC Control Register + PCTL_PPRE = 0xc0 // PSC Prescaler Select bits + PCTL_PCLKSEL = 0x20 // PSC Input Clock Select + PCTL_PCCYC = 0x2 // PSC Complete Cycle + PCTL_PRUN = 0x1 // PSC Run + + // POC: PSC Output Configuration + POC_POEN2B = 0x20 // PSC Output 2B Enable + POC_POEN2A = 0x10 // PSC Output 2A Enable + POC_POEN1B = 0x8 // PSC Output 1B Enable + POC_POEN1A = 0x4 // PSC Output 1A Enable + POC_POEN0B = 0x2 // PSC Output 0B Enable + POC_POEN0A = 0x1 // PSC Output 0A Enable + + // PCNF: PSC Configuration Register + PCNF_PULOCK = 0x20 // PSC Update Lock + PCNF_PMODE = 0x10 // PSC Mode + PCNF_POPB = 0x8 // PSC Output B Polarity + PCNF_POPA = 0x4 // PSC Output A Polarity + + // PSYNC: PSC Synchro Configuration + PSYNC_PSYNC2 = 0x30 // Selection of Synchronization Out for ADC + PSYNC_PSYNC1 = 0xc // Selection of Synchronization Out for ADC + PSYNC_PSYNC0 = 0x3 // Selection of Synchronization Out for ADC +) diff --git a/src/device/avr/atmega64m1.ld b/src/device/avr/atmega64m1.ld new file mode 100644 index 00000000..1a83f874 --- /dev/null +++ b/src/device/avr/atmega64m1.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega64M1.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_size = 0x1000; +__num_isrs = 31; diff --git a/src/device/avr/atmega64rfr2.go b/src/device/avr/atmega64rfr2.go new file mode 100644 index 00000000..7b2baca8 --- /dev/null +++ b/src/device/avr/atmega64rfr2.go @@ -0,0 +1,1738 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega64RFR2.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega64rfr2 + +// Device information for the ATmega64RFR2. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega64RFR2" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_INT3 = 4 // External Interrupt Request 3 + IRQ_INT4 = 5 // External Interrupt Request 4 + IRQ_INT5 = 6 // External Interrupt Request 5 + IRQ_INT6 = 7 // External Interrupt Request 6 + IRQ_INT7 = 8 // External Interrupt Request 7 + IRQ_PCINT0 = 9 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 10 // Pin Change Interrupt Request 1 + IRQ_PCINT2 = 11 // Pin Change Interrupt Request 2 + IRQ_WDT = 12 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 13 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 14 // Timer/Counter2 Compare Match B + IRQ_TIMER2_OVF = 15 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 16 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 17 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 18 // Timer/Counter1 Compare Match B + IRQ_TIMER1_COMPC = 19 // Timer/Counter1 Compare Match C + IRQ_TIMER1_OVF = 20 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 21 // Timer/Counter0 Compare Match A + IRQ_TIMER0_COMPB = 22 // Timer/Counter0 Compare Match B + IRQ_TIMER0_OVF = 23 // Timer/Counter0 Overflow + IRQ_SPI_STC = 24 // SPI Serial Transfer Complete + IRQ_USART0_RX = 25 // USART0, Rx Complete + IRQ_USART0_UDRE = 26 // USART0 Data register Empty + IRQ_USART0_TX = 27 // USART0, Tx Complete + IRQ_ANALOG_COMP = 28 // Analog Comparator + IRQ_ADC = 29 // ADC Conversion Complete + IRQ_EE_READY = 30 // EEPROM Ready + IRQ_TIMER3_CAPT = 31 // Timer/Counter3 Capture Event + IRQ_TIMER3_COMPA = 32 // Timer/Counter3 Compare Match A + IRQ_TIMER3_COMPB = 33 // Timer/Counter3 Compare Match B + IRQ_TIMER3_COMPC = 34 // Timer/Counter3 Compare Match C + IRQ_TIMER3_OVF = 35 // Timer/Counter3 Overflow + IRQ_USART1_RX = 36 // USART1, Rx Complete + IRQ_USART1_UDRE = 37 // USART1 Data register Empty + IRQ_USART1_TX = 38 // USART1, Tx Complete + IRQ_TWI = 39 // 2-wire Serial Interface + IRQ_SPM_READY = 40 // Store Program Memory Read + IRQ_TIMER4_CAPT = 41 // Timer/Counter4 Capture Event + IRQ_TIMER4_COMPA = 42 // Timer/Counter4 Compare Match A + IRQ_TIMER4_COMPB = 43 // Timer/Counter4 Compare Match B + IRQ_TIMER4_COMPC = 44 // Timer/Counter4 Compare Match C + IRQ_TIMER4_OVF = 45 // Timer/Counter4 Overflow + IRQ_TIMER5_CAPT = 46 // Timer/Counter5 Capture Event + IRQ_TIMER5_COMPA = 47 // Timer/Counter5 Compare Match A + IRQ_TIMER5_COMPB = 48 // Timer/Counter5 Compare Match B + IRQ_TIMER5_COMPC = 49 // Timer/Counter5 Compare Match C + IRQ_TIMER5_OVF = 50 // Timer/Counter5 Overflow + IRQ_TRX24_PLL_LOCK = 57 // TRX24 - PLL lock interrupt + IRQ_TRX24_PLL_UNLOCK = 58 // TRX24 - PLL unlock interrupt + IRQ_TRX24_RX_START = 59 // TRX24 - Receive start interrupt + IRQ_TRX24_RX_END = 60 // TRX24 - RX_END interrupt + IRQ_TRX24_CCA_ED_DONE = 61 // TRX24 - CCA/ED done interrupt + IRQ_TRX24_XAH_AMI = 62 // TRX24 - XAH - AMI + IRQ_TRX24_TX_END = 63 // TRX24 - TX_END interrupt + IRQ_TRX24_AWAKE = 64 // TRX24 AWAKE - tranceiver is reaching state TRX_OFF + IRQ_SCNT_CMP1 = 65 // Symbol counter - compare match 1 interrupt + IRQ_SCNT_CMP2 = 66 // Symbol counter - compare match 2 interrupt + IRQ_SCNT_CMP3 = 67 // Symbol counter - compare match 3 interrupt + IRQ_SCNT_OVFL = 68 // Symbol counter - overflow interrupt + IRQ_SCNT_BACKOFF = 69 // Symbol counter - backoff interrupt + IRQ_AES_READY = 70 // AES engine ready interrupt + IRQ_BAT_LOW = 71 // Battery monitor indicates supply voltage below threshold + IRQ_TRX24_TX_START = 72 // TRX24 TX start interrupt + IRQ_TRX24_AMI0 = 73 // Address match interrupt of address filter 0 + IRQ_TRX24_AMI1 = 74 // Address match interrupt of address filter 1 + IRQ_TRX24_AMI2 = 75 // Address match interrupt of address filter 2 + IRQ_TRX24_AMI3 = 76 // Address match interrupt of address filter 3 + IRQ_max = 76 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // USART + USART = struct { + UDR0 __reg + UBRR0L __reg + UBRR0H __reg + UDR1 __reg + UBRR1L __reg + UBRR1H __reg + }{ + UDR0: 0xc6, // USART0 I/O Data Register + UBRR0L: 0xc4, // USART0 Baud Rate Register Bytes + UBRR0H: 0xc4, // USART0 Baud Rate Register Bytes + UDR1: 0xce, // USART1 I/O Data Register + UBRR1L: 0xcc, // USART1 Baud Rate Register Bytes + UBRR1H: 0xcc, // USART1 Baud Rate Register Bytes + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate Register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data Register + TWAR: 0xba, // TWI (Slave) Address Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + PORTF __reg + DDRF __reg + PINF __reg + PORTG __reg + DDRG __reg + PING __reg + }{ + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins Address + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins Address + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins Address + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins Address + PORTE: 0x2e, // Port E Data Register + DDRE: 0x2d, // Port E Data Direction Register + PINE: 0x2c, // Port E Input Pins Address + PORTF: 0x31, // Port F Data Register + DDRF: 0x30, // Port F Data Direction Register + PINF: 0x2f, // Port F Input Pins Address + PORTG: 0x34, // Port G Data Register + DDRG: 0x33, // Port G Data Direction Register + PING: 0x32, // Port G Input Pins Address + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register B + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 Register + TCCR0B: 0x45, // Timer/Counter0 Control Register B + TCCR0A: 0x44, // Timer/Counter0 Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag Register + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR5A __reg + TCCR5B __reg + TCCR5C __reg + TCNT5L __reg + TCNT5H __reg + OCR5AL __reg + OCR5AH __reg + OCR5BL __reg + OCR5BH __reg + OCR5CL __reg + OCR5CH __reg + ICR5L __reg + ICR5H __reg + TIMSK5 __reg + TIFR5 __reg + TCCR4A __reg + TCCR4B __reg + TCCR4C __reg + TCNT4L __reg + TCNT4H __reg + OCR4AL __reg + OCR4AH __reg + OCR4BL __reg + OCR4BH __reg + OCR4CL __reg + OCR4CH __reg + ICR4L __reg + ICR4H __reg + TIMSK4 __reg + TIFR4 __reg + TCCR3A __reg + TCCR3B __reg + TCCR3C __reg + TCNT3L __reg + TCNT3H __reg + OCR3AL __reg + OCR3AH __reg + OCR3BL __reg + OCR3BH __reg + OCR3CL __reg + OCR3CH __reg + ICR3L __reg + ICR3H __reg + TIMSK3 __reg + TIFR3 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + OCR1CL __reg + OCR1CH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR5A: 0x120, // Timer/Counter5 Control Register A + TCCR5B: 0x121, // Timer/Counter5 Control Register B + TCCR5C: 0x122, // Timer/Counter5 Control Register C + TCNT5L: 0x124, // Timer/Counter5 Bytes + TCNT5H: 0x124, // Timer/Counter5 Bytes + OCR5AL: 0x128, // Timer/Counter5 Output Compare Register A Bytes + OCR5AH: 0x128, // Timer/Counter5 Output Compare Register A Bytes + OCR5BL: 0x12a, // Timer/Counter5 Output Compare Register B Bytes + OCR5BH: 0x12a, // Timer/Counter5 Output Compare Register B Bytes + OCR5CL: 0x12c, // Timer/Counter5 Output Compare Register C Bytes + OCR5CH: 0x12c, // Timer/Counter5 Output Compare Register C Bytes + ICR5L: 0x126, // Timer/Counter5 Input Capture Register Bytes + ICR5H: 0x126, // Timer/Counter5 Input Capture Register Bytes + TIMSK5: 0x73, // Timer/Counter5 Interrupt Mask Register + TIFR5: 0x3a, // Timer/Counter5 Interrupt Flag Register + TCCR4A: 0xa0, // Timer/Counter4 Control Register A + TCCR4B: 0xa1, // Timer/Counter4 Control Register B + TCCR4C: 0xa2, // Timer/Counter4 Control Register C + TCNT4L: 0xa4, // Timer/Counter4 Bytes + TCNT4H: 0xa4, // Timer/Counter4 Bytes + OCR4AL: 0xa8, // Timer/Counter4 Output Compare Register A Bytes + OCR4AH: 0xa8, // Timer/Counter4 Output Compare Register A Bytes + OCR4BL: 0xaa, // Timer/Counter4 Output Compare Register B Bytes + OCR4BH: 0xaa, // Timer/Counter4 Output Compare Register B Bytes + OCR4CL: 0xac, // Timer/Counter4 Output Compare Register C Bytes + OCR4CH: 0xac, // Timer/Counter4 Output Compare Register C Bytes + ICR4L: 0xa6, // Timer/Counter4 Input Capture Register Bytes + ICR4H: 0xa6, // Timer/Counter4 Input Capture Register Bytes + TIMSK4: 0x72, // Timer/Counter4 Interrupt Mask Register + TIFR4: 0x39, // Timer/Counter4 Interrupt Flag Register + TCCR3A: 0x90, // Timer/Counter3 Control Register A + TCCR3B: 0x91, // Timer/Counter3 Control Register B + TCCR3C: 0x92, // Timer/Counter3 Control Register C + TCNT3L: 0x94, // Timer/Counter3 Bytes + TCNT3H: 0x94, // Timer/Counter3 Bytes + OCR3AL: 0x98, // Timer/Counter3 Output Compare Register A Bytes + OCR3AH: 0x98, // Timer/Counter3 Output Compare Register A Bytes + OCR3BL: 0x9a, // Timer/Counter3 Output Compare Register B Bytes + OCR3BH: 0x9a, // Timer/Counter3 Output Compare Register B Bytes + OCR3CL: 0x9c, // Timer/Counter3 Output Compare Register C Bytes + OCR3CH: 0x9c, // Timer/Counter3 Output Compare Register C Bytes + ICR3L: 0x96, // Timer/Counter3 Input Capture Register Bytes + ICR3H: 0x96, // Timer/Counter3 Input Capture Register Bytes + TIMSK3: 0x71, // Timer/Counter3 Interrupt Mask Register + TIFR3: 0x38, // Timer/Counter3 Interrupt Flag Register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1CL: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + OCR1CH: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag Register + } + + // Low-Power 2.4 GHz Transceiver + TRX24 = struct { + PARCR __reg + MAFSA0L __reg + MAFSA0H __reg + MAFPA0L __reg + MAFPA0H __reg + MAFSA1L __reg + MAFSA1H __reg + MAFPA1L __reg + MAFPA1H __reg + MAFSA2L __reg + MAFSA2H __reg + MAFPA2L __reg + MAFPA2H __reg + MAFSA3L __reg + MAFSA3H __reg + MAFPA3L __reg + MAFPA3H __reg + MAFCR0 __reg + MAFCR1 __reg + AES_CTRL __reg + AES_STATUS __reg + AES_STATE __reg + AES_KEY __reg + TRX_STATUS __reg + TRX_STATE __reg + TRX_CTRL_0 __reg + TRX_CTRL_1 __reg + PHY_TX_PWR __reg + PHY_RSSI __reg + PHY_ED_LEVEL __reg + PHY_CC_CCA __reg + CCA_THRES __reg + RX_CTRL __reg + SFD_VALUE __reg + TRX_CTRL_2 __reg + ANT_DIV __reg + IRQ_MASK __reg + IRQ_STATUS __reg + IRQ_MASK1 __reg + IRQ_STATUS1 __reg + VREG_CTRL __reg + BATMON __reg + XOSC_CTRL __reg + CC_CTRL_0 __reg + CC_CTRL_1 __reg + RX_SYN __reg + TRX_RPC __reg + XAH_CTRL_1 __reg + FTN_CTRL __reg + PLL_CF __reg + PLL_DCU __reg + PART_NUM __reg + VERSION_NUM __reg + MAN_ID_0 __reg + MAN_ID_1 __reg + SHORT_ADDR_0 __reg + SHORT_ADDR_1 __reg + PAN_ID_0 __reg + PAN_ID_1 __reg + IEEE_ADDR_0 __reg + IEEE_ADDR_1 __reg + IEEE_ADDR_2 __reg + IEEE_ADDR_3 __reg + IEEE_ADDR_4 __reg + IEEE_ADDR_5 __reg + IEEE_ADDR_6 __reg + IEEE_ADDR_7 __reg + XAH_CTRL_0 __reg + CSMA_SEED_0 __reg + CSMA_SEED_1 __reg + CSMA_BE __reg + TST_CTRL_DIGI __reg + TST_RX_LENGTH __reg + TRXFBST __reg + TRXFBEND __reg + }{ + PARCR: 0x138, // Power Amplifier Ramp up/down Control Register + MAFSA0L: 0x10e, // Transceiver MAC Short Address Register for Frame Filter 0 (Low Byte) + MAFSA0H: 0x10f, // Transceiver MAC Short Address Register for Frame Filter 0 (High Byte) + MAFPA0L: 0x110, // Transceiver Personal Area Network ID Register for Frame Filter 0 (Low Byte) + MAFPA0H: 0x111, // Transceiver Personal Area Network ID Register for Frame Filter 0 (High Byte) + MAFSA1L: 0x112, // Transceiver MAC Short Address Register for Frame Filter 1 (Low Byte) + MAFSA1H: 0x113, // Transceiver MAC Short Address Register for Frame Filter 1 (High Byte) + MAFPA1L: 0x114, // Transceiver Personal Area Network ID Register for Frame Filter 1 (Low Byte) + MAFPA1H: 0x115, // Transceiver Personal Area Network ID Register for Frame Filter 1 (High Byte) + MAFSA2L: 0x116, // Transceiver MAC Short Address Register for Frame Filter 2 (Low Byte) + MAFSA2H: 0x117, // Transceiver MAC Short Address Register for Frame Filter 2 (High Byte) + MAFPA2L: 0x118, // Transceiver Personal Area Network ID Register for Frame Filter 2 (Low Byte) + MAFPA2H: 0x119, // Transceiver Personal Area Network ID Register for Frame Filter 2 (High Byte) + MAFSA3L: 0x11a, // Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte) + MAFSA3H: 0x11b, // Transceiver MAC Short Address Register for Frame Filter 3 (High Byte) + MAFPA3L: 0x11c, // Transceiver Personal Area Network ID Register for Frame Filter 3 (Low Byte) + MAFPA3H: 0x11d, // Transceiver Personal Area Network ID Register for Frame Filter 3 (High Byte) + MAFCR0: 0x10c, // Multiple Address Filter Configuration Register 0 + MAFCR1: 0x10d, // Multiple Address Filter Configuration Register 1 + AES_CTRL: 0x13c, // AES Control Register + AES_STATUS: 0x13d, // AES Status Register + AES_STATE: 0x13e, // AES Plain and Cipher Text Buffer Register + AES_KEY: 0x13f, // AES Encryption and Decryption Key Buffer Register + TRX_STATUS: 0x141, // Transceiver Status Register + TRX_STATE: 0x142, // Transceiver State Control Register + TRX_CTRL_0: 0x143, // Reserved + TRX_CTRL_1: 0x144, // Transceiver Control Register 1 + PHY_TX_PWR: 0x145, // Transceiver Transmit Power Control Register + PHY_RSSI: 0x146, // Receiver Signal Strength Indicator Register + PHY_ED_LEVEL: 0x147, // Transceiver Energy Detection Level Register + PHY_CC_CCA: 0x148, // Transceiver Clear Channel Assessment (CCA) Control Register + CCA_THRES: 0x149, // Transceiver CCA Threshold Setting Register + RX_CTRL: 0x14a, // Transceiver Receive Control Register + SFD_VALUE: 0x14b, // Start of Frame Delimiter Value Register + TRX_CTRL_2: 0x14c, // Transceiver Control Register 2 + ANT_DIV: 0x14d, // Antenna Diversity Control Register + IRQ_MASK: 0x14e, // Transceiver Interrupt Enable Register + IRQ_STATUS: 0x14f, // Transceiver Interrupt Status Register + IRQ_MASK1: 0xbe, // Transceiver Interrupt Enable Register 1 + IRQ_STATUS1: 0xbf, // Transceiver Interrupt Status Register 1 + VREG_CTRL: 0x150, // Voltage Regulator Control and Status Register + BATMON: 0x151, // Battery Monitor Control and Status Register + XOSC_CTRL: 0x152, // Crystal Oscillator Control Register + CC_CTRL_0: 0x153, // Channel Control Register 0 + CC_CTRL_1: 0x154, // Channel Control Register 1 + RX_SYN: 0x155, // Transceiver Receiver Sensitivity Control Register + TRX_RPC: 0x156, // Transceiver Reduced Power Consumption Control + XAH_CTRL_1: 0x157, // Transceiver Acknowledgment Frame Control Register 1 + FTN_CTRL: 0x158, // Transceiver Filter Tuning Control Register + PLL_CF: 0x15a, // Transceiver Center Frequency Calibration Control Register + PLL_DCU: 0x15b, // Transceiver Delay Cell Calibration Control Register + PART_NUM: 0x15c, // Device Identification Register (Part Number) + VERSION_NUM: 0x15d, // Device Identification Register (Version Number) + MAN_ID_0: 0x15e, // Device Identification Register (Manufacture ID Low Byte) + MAN_ID_1: 0x15f, // Device Identification Register (Manufacture ID High Byte) + SHORT_ADDR_0: 0x160, // Transceiver MAC Short Address Register (Low Byte) + SHORT_ADDR_1: 0x161, // Transceiver MAC Short Address Register (High Byte) + PAN_ID_0: 0x162, // Transceiver Personal Area Network ID Register (Low Byte) + PAN_ID_1: 0x163, // Transceiver Personal Area Network ID Register (High Byte) + IEEE_ADDR_0: 0x164, // Transceiver MAC IEEE Address Register 0 + IEEE_ADDR_1: 0x165, // Transceiver MAC IEEE Address Register 1 + IEEE_ADDR_2: 0x166, // Transceiver MAC IEEE Address Register 2 + IEEE_ADDR_3: 0x167, // Transceiver MAC IEEE Address Register 3 + IEEE_ADDR_4: 0x168, // Transceiver MAC IEEE Address Register 4 + IEEE_ADDR_5: 0x169, // Transceiver MAC IEEE Address Register 5 + IEEE_ADDR_6: 0x16a, // Transceiver MAC IEEE Address Register 6 + IEEE_ADDR_7: 0x16b, // Transceiver MAC IEEE Address Register 7 + XAH_CTRL_0: 0x16c, // Transceiver Extended Operating Mode Control Register + CSMA_SEED_0: 0x16d, // Transceiver CSMA-CA Random Number Generator Seed Register + CSMA_SEED_1: 0x16e, // Transceiver Acknowledgment Frame Control Register 2 + CSMA_BE: 0x16f, // Transceiver CSMA-CA Back-off Exponent Control Register + TST_CTRL_DIGI: 0x176, // Transceiver Digital Test Control Register + TST_RX_LENGTH: 0x17b, // Transceiver Received Frame Length Register + TRXFBST: 0x180, // Start of frame buffer + TRXFBEND: 0x1ff, // End of frame buffer + } + + // MAC Symbol Counter + SYMCNT = struct { + SCTSTRHH __reg + SCTSTRHL __reg + SCTSTRLH __reg + SCTSTRLL __reg + SCOCR1HH __reg + SCOCR1HL __reg + SCOCR1LH __reg + SCOCR1LL __reg + SCOCR2HH __reg + SCOCR2HL __reg + SCOCR2LH __reg + SCOCR2LL __reg + SCOCR3HH __reg + SCOCR3HL __reg + SCOCR3LH __reg + SCOCR3LL __reg + SCTSRHH __reg + SCTSRHL __reg + SCTSRLH __reg + SCTSRLL __reg + SCBTSRHH __reg + SCBTSRHL __reg + SCBTSRLH __reg + SCBTSRLL __reg + SCCNTHH __reg + SCCNTHL __reg + SCCNTLH __reg + SCCNTLL __reg + SCIRQS __reg + SCIRQM __reg + SCSR __reg + SCCR1 __reg + SCCR0 __reg + SCCSR __reg + SCRSTRHH __reg + SCRSTRHL __reg + SCRSTRLH __reg + SCRSTRLL __reg + }{ + SCTSTRHH: 0xfc, // Symbol Counter Transmit Frame Timestamp Register HH-Byte + SCTSTRHL: 0xfb, // Symbol Counter Transmit Frame Timestamp Register HL-Byte + SCTSTRLH: 0xfa, // Symbol Counter Transmit Frame Timestamp Register LH-Byte + SCTSTRLL: 0xf9, // Symbol Counter Transmit Frame Timestamp Register LL-Byte + SCOCR1HH: 0xf8, // Symbol Counter Output Compare Register 1 HH-Byte + SCOCR1HL: 0xf7, // Symbol Counter Output Compare Register 1 HL-Byte + SCOCR1LH: 0xf6, // Symbol Counter Output Compare Register 1 LH-Byte + SCOCR1LL: 0xf5, // Symbol Counter Output Compare Register 1 LL-Byte + SCOCR2HH: 0xf4, // Symbol Counter Output Compare Register 2 HH-Byte + SCOCR2HL: 0xf3, // Symbol Counter Output Compare Register 2 HL-Byte + SCOCR2LH: 0xf2, // Symbol Counter Output Compare Register 2 LH-Byte + SCOCR2LL: 0xf1, // Symbol Counter Output Compare Register 2 LL-Byte + SCOCR3HH: 0xf0, // Symbol Counter Output Compare Register 3 HH-Byte + SCOCR3HL: 0xef, // Symbol Counter Output Compare Register 3 HL-Byte + SCOCR3LH: 0xee, // Symbol Counter Output Compare Register 3 LH-Byte + SCOCR3LL: 0xed, // Symbol Counter Output Compare Register 3 LL-Byte + SCTSRHH: 0xec, // Symbol Counter Frame Timestamp Register HH-Byte + SCTSRHL: 0xeb, // Symbol Counter Frame Timestamp Register HL-Byte + SCTSRLH: 0xea, // Symbol Counter Frame Timestamp Register LH-Byte + SCTSRLL: 0xe9, // Symbol Counter Frame Timestamp Register LL-Byte + SCBTSRHH: 0xe8, // Symbol Counter Beacon Timestamp Register HH-Byte + SCBTSRHL: 0xe7, // Symbol Counter Beacon Timestamp Register HL-Byte + SCBTSRLH: 0xe6, // Symbol Counter Beacon Timestamp Register LH-Byte + SCBTSRLL: 0xe5, // Symbol Counter Beacon Timestamp Register LL-Byte + SCCNTHH: 0xe4, // Symbol Counter Register HH-Byte + SCCNTHL: 0xe3, // Symbol Counter Register HL-Byte + SCCNTLH: 0xe2, // Symbol Counter Register LH-Byte + SCCNTLL: 0xe1, // Symbol Counter Register LL-Byte + SCIRQS: 0xe0, // Symbol Counter Interrupt Status Register + SCIRQM: 0xdf, // Symbol Counter Interrupt Mask Register + SCSR: 0xde, // Symbol Counter Status Register + SCCR1: 0xdd, // Symbol Counter Control Register 1 + SCCR0: 0xdc, // Symbol Counter Control Register 0 + SCCSR: 0xdb, // Symbol Counter Compare Source Register + SCRSTRHH: 0xda, // Symbol Counter Received Frame Timestamp Register HH-Byte + SCRSTRHL: 0xd9, // Symbol Counter Received Frame Timestamp Register HL-Byte + SCRSTRLH: 0xd8, // Symbol Counter Received Frame Timestamp Register LH-Byte + SCRSTRLL: 0xd7, // Symbol Counter Received Frame Timestamp Register LL-Byte + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Bytes + EEARH: 0x41, // EEPROM Address Register Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // JTAG Interface + JTAG = struct { + OCDR __reg + }{ + OCDR: 0x51, // On-Chip Debug Register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EICRB __reg + EIMSK __reg + EIFR __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + PCICR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EICRB: 0x6a, // External Interrupt Control Register B + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + ADCSRC __reg + DIDR2 __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC Multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // The ADC Control and Status Register A + ADCSRC: 0x77, // The ADC Control and Status Register C + DIDR2: 0x7d, // Digital Input Disable Register 2 + DIDR0: 0x7e, // Digital Input Disable Register 0 + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PRR2 __reg + PRR1 __reg + PRR0 __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose I/O Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PRR2: 0x63, // Power Reduction Register 2 + PRR1: 0x65, // Power Reduction Register 1 + PRR0: 0x64, // Power Reduction Register0 + } + + // FLASH Controller + FLASH = struct { + NEMCR __reg + BGCR __reg + }{ + NEMCR: 0x75, // Flash Extended-Mode Control-Register + BGCR: 0x67, // Reference Voltage Calibration Register + } + + // Power Controller + PWRCTRL = struct { + TRXPR __reg + DRTRAM0 __reg + DRTRAM1 __reg + DRTRAM2 __reg + DRTRAM3 __reg + LLDRL __reg + LLDRH __reg + LLCR __reg + DPDS0 __reg + DPDS1 __reg + }{ + TRXPR: 0x139, // Transceiver Pin Register + DRTRAM0: 0x135, // Data Retention Configuration Register #0 + DRTRAM1: 0x134, // Data Retention Configuration Register #1 + DRTRAM2: 0x133, // Data Retention Configuration Register #2 + DRTRAM3: 0x132, // Data Retention Configuration Register #3 + LLDRL: 0x130, // Low Leakage Voltage Regulator Data Register (Low-Byte) + LLDRH: 0x131, // Low Leakage Voltage Regulator Data Register (High-Byte) + LLCR: 0x12f, // Low Leakage Voltage Regulator Control Register + DPDS0: 0x136, // Port Driver Strength Register 0 + DPDS1: 0x137, // Port Driver Strength Register 1 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // HIGH + HIGH_OCDEN = 0x80 // On-Chip Debug Enabled + HIGH_JTAGEN = 0x40 // JTAG Interface Enabled + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTE7 + LOW_CKSEL_SUT = 0x3f // Select Clock Source : Start-up time +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe // TWI Address Mask + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI START Condition Bit + TWCR_TWSTO = 0x10 // TWI STOP Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collision Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler Bits + + // TWAR: TWI (Slave) Address Register + TWAR_TWA = 0xfe // TWI (Slave) Address + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Select 1 and 0 + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter0 Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter0 Control Register A + TCCR0A_COM0A = 0xc0 // Compare Match Output A Mode + TCCR0A_COM0B = 0x30 // Compare Match Output B Mode + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag Register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare B Match Flag + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare A Match Flag + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2B = 0x4 // Output Compare Flag 2 B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2 A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Match Output A Mode + TCCR2A_COM2B = 0x30 // Compare Match Output B Mode + TCCR2A_WGM2 = 0x3 // Waveform Generation Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select + + // ASSR: Asynchronous Status Register + ASSR_EXCLKAMR = 0x80 // Enable External Clock Input for AMR + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Timer/Counter2 Asynchronous Mode + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Timer/Counter2 Output Compare Register A Update Busy + ASSR_OCR2BUB = 0x4 // Timer/Counter2 Output Compare Register B Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter2 Control Register A Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter2 Control Register B Update Busy +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR5A: Timer/Counter5 Control Register A + TCCR5A_COM5A = 0xc0 // Compare Output Mode for Channel A + TCCR5A_COM5B = 0x30 // Compare Output Mode for Channel B + TCCR5A_COM5C = 0xc // Compare Output Mode for Channel C + TCCR5A_WGM5 = 0x3 // Waveform Generation Mode + + // TCCR5B: Timer/Counter5 Control Register B + TCCR5B_ICNC5 = 0x80 // Input Capture 5 Noise Canceller + TCCR5B_ICES5 = 0x40 // Input Capture 5 Edge Select + TCCR5B_WGM5 = 0x18 // Waveform Generation Mode + TCCR5B_CS5 = 0x7 // Clock Select + + // TCCR5C: Timer/Counter5 Control Register C + TCCR5C_FOC5A = 0x80 // Force Output Compare for Channel A + TCCR5C_FOC5B = 0x40 // Force Output Compare for Channel B + TCCR5C_FOC5C = 0x20 // Force Output Compare for Channel C + + // TIMSK5: Timer/Counter5 Interrupt Mask Register + TIMSK5_ICIE5 = 0x20 // Timer/Counter5 Input Capture Interrupt Enable + TIMSK5_OCIE5C = 0x8 // Timer/Counter5 Output Compare C Match Interrupt Enable + TIMSK5_OCIE5B = 0x4 // Timer/Counter5 Output Compare B Match Interrupt Enable + TIMSK5_OCIE5A = 0x2 // Timer/Counter5 Output Compare A Match Interrupt Enable + TIMSK5_TOIE5 = 0x1 // Timer/Counter5 Overflow Interrupt Enable + + // TIFR5: Timer/Counter5 Interrupt Flag Register + TIFR5_ICF5 = 0x20 // Timer/Counter5 Input Capture Flag + TIFR5_OCF5C = 0x8 // Timer/Counter5 Output Compare C Match Flag + TIFR5_OCF5B = 0x4 // Timer/Counter5 Output Compare B Match Flag + TIFR5_OCF5A = 0x2 // Timer/Counter5 Output Compare A Match Flag + TIFR5_TOV5 = 0x1 // Timer/Counter5 Overflow Flag + + // TCCR4A: Timer/Counter4 Control Register A + TCCR4A_COM4A = 0xc0 // Compare Output Mode for Channel A + TCCR4A_COM4B = 0x30 // Compare Output Mode for Channel B + TCCR4A_COM4C = 0xc // Compare Output Mode for Channel C + TCCR4A_WGM4 = 0x3 // Waveform Generation Mode + + // TCCR4B: Timer/Counter4 Control Register B + TCCR4B_ICNC4 = 0x80 // Input Capture 4 Noise Canceller + TCCR4B_ICES4 = 0x40 // Input Capture 4 Edge Select + TCCR4B_WGM4 = 0x18 // Waveform Generation Mode + TCCR4B_CS4 = 0x7 // Clock Select + + // TCCR4C: Timer/Counter4 Control Register C + TCCR4C_FOC4A = 0x80 // Force Output Compare for Channel A + TCCR4C_FOC4B = 0x40 // Force Output Compare for Channel B + TCCR4C_FOC4C = 0x20 // Force Output Compare for Channel C + + // TIMSK4: Timer/Counter4 Interrupt Mask Register + TIMSK4_ICIE4 = 0x20 // Timer/Counter4 Input Capture Interrupt Enable + TIMSK4_OCIE4C = 0x8 // Timer/Counter4 Output Compare C Match Interrupt Enable + TIMSK4_OCIE4B = 0x4 // Timer/Counter4 Output Compare B Match Interrupt Enable + TIMSK4_OCIE4A = 0x2 // Timer/Counter4 Output Compare A Match Interrupt Enable + TIMSK4_TOIE4 = 0x1 // Timer/Counter4 Overflow Interrupt Enable + + // TIFR4: Timer/Counter4 Interrupt Flag Register + TIFR4_ICF4 = 0x20 // Timer/Counter4 Input Capture Flag + TIFR4_OCF4C = 0x8 // Timer/Counter4 Output Compare C Match Flag + TIFR4_OCF4B = 0x4 // Timer/Counter4 Output Compare B Match Flag + TIFR4_OCF4A = 0x2 // Timer/Counter4 Output Compare A Match Flag + TIFR4_TOV4 = 0x1 // Timer/Counter4 Overflow Flag + + // TCCR3A: Timer/Counter3 Control Register A + TCCR3A_COM3A = 0xc0 // Compare Output Mode for Channel A + TCCR3A_COM3B = 0x30 // Compare Output Mode for Channel B + TCCR3A_COM3C = 0xc // Compare Output Mode for Channel C + TCCR3A_WGM3 = 0x3 // Waveform Generation Mode + + // TCCR3B: Timer/Counter3 Control Register B + TCCR3B_ICNC3 = 0x80 // Input Capture 3 Noise Canceller + TCCR3B_ICES3 = 0x40 // Input Capture 3 Edge Select + TCCR3B_WGM3 = 0x18 // Waveform Generation Mode + TCCR3B_CS3 = 0x7 // Clock Select + + // TCCR3C: Timer/Counter3 Control Register C + TCCR3C_FOC3A = 0x80 // Force Output Compare for Channel A + TCCR3C_FOC3B = 0x40 // Force Output Compare for Channel B + TCCR3C_FOC3C = 0x20 // Force Output Compare for Channel C + + // TIMSK3: Timer/Counter3 Interrupt Mask Register + TIMSK3_ICIE3 = 0x20 // Timer/Counter3 Input Capture Interrupt Enable + TIMSK3_OCIE3C = 0x8 // Timer/Counter3 Output Compare C Match Interrupt Enable + TIMSK3_OCIE3B = 0x4 // Timer/Counter3 Output Compare B Match Interrupt Enable + TIMSK3_OCIE3A = 0x2 // Timer/Counter3 Output Compare A Match Interrupt Enable + TIMSK3_TOIE3 = 0x1 // Timer/Counter3 Overflow Interrupt Enable + + // TIFR3: Timer/Counter3 Interrupt Flag Register + TIFR3_ICF3 = 0x20 // Timer/Counter3 Input Capture Flag + TIFR3_OCF3C = 0x8 // Timer/Counter3 Output Compare C Match Flag + TIFR3_OCF3B = 0x4 // Timer/Counter3 Output Compare B Match Flag + TIFR3_OCF3A = 0x2 // Timer/Counter3 Output Compare A Match Flag + TIFR3_TOV3 = 0x1 // Timer/Counter3 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode for Channel A + TCCR1A_COM1B = 0x30 // Compare Output Mode for Channel B + TCCR1A_COM1C = 0xc // Compare Output Mode for Channel C + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceller + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Clock Select + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare for Channel A + TCCR1C_FOC1B = 0x40 // Force Output Compare for Channel B + TCCR1C_FOC1C = 0x20 // Force Output Compare for Channel C + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1C = 0x8 // Timer/Counter1 Output Compare C Match Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag Register + TIFR1_ICF1 = 0x20 // Timer/Counter1 Input Capture Flag + TIFR1_OCF1C = 0x8 // Timer/Counter1 Output Compare C Match Flag + TIFR1_OCF1B = 0x4 // Timer/Counter1 Output Compare B Match Flag + TIFR1_OCF1A = 0x2 // Timer/Counter1 Output Compare A Match Flag + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for TRX24: Low-Power 2.4 GHz Transceiver +const ( + // PARCR: Power Amplifier Ramp up/down Control Register + PARCR_PALTD = 0xe0 // ext. PA Ramp Down Lead Time + PARCR_PALTU = 0x1c // ext. PA Ramp Up Lead Time + PARCR_PARDFI = 0x2 // Power Amplifier Ramp Down Frequency Inversion + PARCR_PARUFI = 0x1 // Power Amplifier Ramp Up Frequency Inversion + + // MAFSA0L: Transceiver MAC Short Address Register for Frame Filter 0 (Low Byte) + MAFSA0L_MAFSA0L = 0xff // MAC Short Address low Byte for Frame Filter 0 + + // MAFSA0H: Transceiver MAC Short Address Register for Frame Filter 0 (High Byte) + MAFSA0H_MAFSA0H = 0xff // MAC Short Address high Byte for Frame Filter 0 + + // MAFPA0L: Transceiver Personal Area Network ID Register for Frame Filter 0 (Low Byte) + MAFPA0L_MAFPA0L = 0xff // MAC Personal Area Network ID low Byte for Frame Filter 0 + + // MAFPA0H: Transceiver Personal Area Network ID Register for Frame Filter 0 (High Byte) + MAFPA0H_MAFPA0H = 0xff // MAC Personal Area Network ID high Byte for Frame Filter 0 + + // MAFSA1L: Transceiver MAC Short Address Register for Frame Filter 1 (Low Byte) + MAFSA1L_MAFSA1L = 0xff // MAC Short Address low Byte for Frame Filter 1 + + // MAFSA1H: Transceiver MAC Short Address Register for Frame Filter 1 (High Byte) + MAFSA1H_MAFSA1H = 0xff // MAC Short Address high Byte for Frame Filter 1 + + // MAFPA1L: Transceiver Personal Area Network ID Register for Frame Filter 1 (Low Byte) + MAFPA1L_MAFPA1L = 0xff // MAC Personal Area Network ID low Byte for Frame Filter 1 + + // MAFPA1H: Transceiver Personal Area Network ID Register for Frame Filter 1 (High Byte) + MAFPA1H_MAFPA1H = 0xff // MAC Personal Area Network ID high Byte for Frame Filter 1 + + // MAFSA2L: Transceiver MAC Short Address Register for Frame Filter 2 (Low Byte) + MAFSA2L_MAFSA2L = 0xff // MAC Short Address low Byte for Frame Filter 2 + + // MAFSA2H: Transceiver MAC Short Address Register for Frame Filter 2 (High Byte) + MAFSA2H_MAFSA2H = 0xff // MAC Short Address high Byte for Frame Filter 2 + + // MAFPA2L: Transceiver Personal Area Network ID Register for Frame Filter 2 (Low Byte) + MAFPA2L_MAFPA2L = 0xff // MAC Personal Area Network ID low Byte for Frame Filter 2 + + // MAFPA2H: Transceiver Personal Area Network ID Register for Frame Filter 2 (High Byte) + MAFPA2H_MAFPA2H = 0xff // MAC Personal Area Network ID high Byte for Frame Filter 2 + + // MAFSA3L: Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte) + MAFSA3L_MAFSA3L = 0xff // MAC Short Address low Byte for Frame Filter 3 + + // MAFSA3H: Transceiver MAC Short Address Register for Frame Filter 3 (High Byte) + MAFSA3H_MAFSA3H = 0xff // MAC Short Address high Byte for Frame Filter 3 + + // MAFPA3L: Transceiver Personal Area Network ID Register for Frame Filter 3 (Low Byte) + MAFPA3L_MAFPA3L = 0xff // MAC Personal Area Network ID low Byte for Frame Filter 3 + + // MAFPA3H: Transceiver Personal Area Network ID Register for Frame Filter 3 (High Byte) + MAFPA3H_MAFPA3H = 0xff // MAC Personal Area Network ID high Byte for Frame Filter 3 + + // MAFCR0: Multiple Address Filter Configuration Register 0 + MAFCR0_MAF3EN = 0x8 // Multiple Address Filter 3 Enable + MAFCR0_MAF2EN = 0x4 // Multiple Address Filter 2 Enable + MAFCR0_MAF1EN = 0x2 // Multiple Address Filter 1 Enable + MAFCR0_MAF0EN = 0x1 // Multiple Address Filter 0 Enable + + // MAFCR1: Multiple Address Filter Configuration Register 1 + MAFCR1_AACK_3_SET_PD = 0x80 // Set Data Pending bit for address filter 3. + MAFCR1_AACK_3_I_AM_COORD = 0x40 // Enable PAN Coordinator mode for address filter 3. + MAFCR1_AACK_2_SET_PD = 0x20 // Set Data Pending bit for address filter 2. + MAFCR1_AACK_2_I_AM_COORD = 0x10 // Enable PAN Coordinator mode for address filter 2. + MAFCR1_AACK_1_SET_PD = 0x8 // Set Data Pending bit for address filter 1. + MAFCR1_AACK_1_I_AM_COORD = 0x4 // Enable PAN Coordinator mode for address filter 1. + MAFCR1_AACK_0_SET_PD = 0x2 // Set Data Pending bit for address filter 0. + MAFCR1_AACK_0_I_AM_COORD = 0x1 // Enable PAN Coordinator mode for address filter 0. + + // AES_CTRL: AES Control Register + AES_CTRL_AES_REQUEST = 0x80 // Request AES Operation. + AES_CTRL_AES_MODE = 0x20 // Set AES Operation Mode + AES_CTRL_AES_DIR = 0x8 // Set AES Operation Direction + AES_CTRL_AES_IM = 0x4 // AES Interrupt Enable + + // AES_STATUS: AES Status Register + AES_STATUS_AES_ER = 0x80 // AES Operation Finished with Error + AES_STATUS_AES_DONE = 0x1 // AES Operation Finished with Success + + // AES_STATE: AES Plain and Cipher Text Buffer Register + AES_STATE_AES_STATE = 0xff // AES Plain and Cipher Text Buffer + + // AES_KEY: AES Encryption and Decryption Key Buffer Register + AES_KEY_AES_KEY = 0xff // AES Encryption/Decryption Key Buffer + + // TRX_STATUS: Transceiver Status Register + TRX_STATUS_CCA_DONE = 0x80 // CCA Algorithm Status + TRX_STATUS_CCA_STATUS = 0x40 // CCA Status Result + TRX_STATUS_TST_STATUS = 0x20 // Test mode status + TRX_STATUS_TRX_STATUS = 0x1f // Transceiver Main Status + + // TRX_STATE: Transceiver State Control Register + TRX_STATE_TRAC_STATUS = 0xe0 // Transaction Status + TRX_STATE_TRX_CMD = 0x1f // State Control Command + + // TRX_CTRL_0: Reserved + TRX_CTRL_0_Res7 = 0x80 // Reserved + TRX_CTRL_0_PMU_EN = 0x40 // Enable Phase Measurement Unit + TRX_CTRL_0_PMU_START = 0x20 // Start of Phase Measurement Unit + TRX_CTRL_0_PMU_IF_INV = 0x10 // PMU IF Inverse + + // TRX_CTRL_1: Transceiver Control Register 1 + TRX_CTRL_1_PA_EXT_EN = 0x80 // External PA support enable + TRX_CTRL_1_IRQ_2_EXT_EN = 0x40 // Connect Frame Start IRQ to TC1 + TRX_CTRL_1_TX_AUTO_CRC_ON = 0x20 // Enable Automatic CRC Calculation + TRX_CTRL_1_PLL_TX_FLT = 0x10 // Enable PLL TX filter + + // PHY_TX_PWR: Transceiver Transmit Power Control Register + PHY_TX_PWR_TX_PWR = 0xf // Transmit Power Setting + + // PHY_RSSI: Receiver Signal Strength Indicator Register + PHY_RSSI_RX_CRC_VALID = 0x80 // Received Frame CRC Status + PHY_RSSI_RND_VALUE = 0x60 // Random Value + PHY_RSSI_RSSI = 0x1f // Receiver Signal Strength Indicator + + // PHY_ED_LEVEL: Transceiver Energy Detection Level Register + PHY_ED_LEVEL_ED_LEVEL = 0xff // Energy Detection Level + + // PHY_CC_CCA: Transceiver Clear Channel Assessment (CCA) Control Register + PHY_CC_CCA_CCA_REQUEST = 0x80 // Manual CCA Measurement Request + PHY_CC_CCA_CCA_MODE = 0x60 // Select CCA Measurement Mode + PHY_CC_CCA_CHANNEL = 0x1f // RX/TX Channel Selection + + // CCA_THRES: Transceiver CCA Threshold Setting Register + CCA_THRES_CCA_CS_THRES = 0xf0 // CS Threshold Level for CCA Measurement + CCA_THRES_CCA_ED_THRES = 0xf // ED Threshold Level for CCA Measurement + + // RX_CTRL: Transceiver Receive Control Register + RX_CTRL_PDT_THRES = 0xf // Receiver Sensitivity Control + + // SFD_VALUE: Start of Frame Delimiter Value Register + SFD_VALUE_SFD_VALUE = 0xff // Start of Frame Delimiter Value + + // TRX_CTRL_2: Transceiver Control Register 2 + TRX_CTRL_2_RX_SAFE_MODE = 0x80 // RX Safe Mode + TRX_CTRL_2_OQPSK_DATA_RATE = 0x3 // Data Rate Selection + + // ANT_DIV: Antenna Diversity Control Register + ANT_DIV_ANT_SEL = 0x80 // Antenna Diversity Antenna Status + ANT_DIV_ANT_DIV_EN = 0x8 // Enable Antenna Diversity + ANT_DIV_ANT_EXT_SW_EN = 0x4 // Enable External Antenna Switch Control + ANT_DIV_ANT_CTRL = 0x3 // Static Antenna Diversity Switch Control + + // IRQ_MASK: Transceiver Interrupt Enable Register + IRQ_MASK_AWAKE_EN = 0x80 // Awake Interrupt Enable + IRQ_MASK_TX_END_EN = 0x40 // TX_END Interrupt Enable + IRQ_MASK_AMI_EN = 0x20 // Address Match Interrupt Enable + IRQ_MASK_CCA_ED_DONE_EN = 0x10 // End of ED Measurement Interrupt Enable + IRQ_MASK_RX_END_EN = 0x8 // RX_END Interrupt Enable + IRQ_MASK_RX_START_EN = 0x4 // RX_START Interrupt Enable + IRQ_MASK_PLL_UNLOCK_EN = 0x2 // PLL Unlock Interrupt Enable + IRQ_MASK_PLL_LOCK_EN = 0x1 // PLL Lock Interrupt Enable + + // IRQ_STATUS: Transceiver Interrupt Status Register + IRQ_STATUS_AWAKE = 0x80 // Awake Interrupt Status + IRQ_STATUS_TX_END = 0x40 // TX_END Interrupt Status + IRQ_STATUS_AMI = 0x20 // Address Match Interrupt Status + IRQ_STATUS_CCA_ED_DONE = 0x10 // End of ED Measurement Interrupt Status + IRQ_STATUS_RX_END = 0x8 // RX_END Interrupt Status + IRQ_STATUS_RX_START = 0x4 // RX_START Interrupt Status + IRQ_STATUS_PLL_UNLOCK = 0x2 // PLL Unlock Interrupt Status + IRQ_STATUS_PLL_LOCK = 0x1 // PLL Lock Interrupt Status + + // IRQ_MASK1: Transceiver Interrupt Enable Register 1 + IRQ_MASK1_MAF_3_AMI_EN = 0x10 // Address Match Interrupt enable Address filter 3 + IRQ_MASK1_MAF_2_AMI_EN = 0x8 // Address Match Interrupt enable Address filter 2 + IRQ_MASK1_MAF_1_AMI_EN = 0x4 // Address Match Interrupt enable Address filter 1 + IRQ_MASK1_MAF_0_AMI_EN = 0x2 // Address Match Interrupt enable Address filter 0 + IRQ_MASK1_TX_START_EN = 0x1 // Transmit Start Interrupt enable + + // IRQ_STATUS1: Transceiver Interrupt Status Register 1 + IRQ_STATUS1_MAF_3_AMI = 0x10 // Address Match Interrupt Status Address filter 3 + IRQ_STATUS1_MAF_2_AMI = 0x8 // Address Match Interrupt Status Address filter 2 + IRQ_STATUS1_MAF_1_AMI = 0x4 // Address Match Interrupt Status Address filter 1 + IRQ_STATUS1_MAF_0_AMI = 0x2 // Address Match Interrupt Status Address filter 0 + IRQ_STATUS1_TX_START = 0x1 // Transmit Start Interrupt Status + + // VREG_CTRL: Voltage Regulator Control and Status Register + VREG_CTRL_AVREG_EXT = 0x80 // Use External AVDD Regulator + VREG_CTRL_AVDD_OK = 0x40 // AVDD Supply Voltage Valid + VREG_CTRL_DVREG_EXT = 0x8 // Use External DVDD Regulator + VREG_CTRL_DVDD_OK = 0x4 // DVDD Supply Voltage Valid + + // BATMON: Battery Monitor Control and Status Register + BATMON_BAT_LOW = 0x80 // Battery Monitor Interrupt Status + BATMON_BAT_LOW_EN = 0x40 // Battery Monitor Interrupt Enable + BATMON_BATMON_OK = 0x20 // Battery Monitor Status + BATMON_BATMON_HR = 0x10 // Battery Monitor Voltage Range + BATMON_BATMON_VTH = 0xf // Battery Monitor Threshold Voltage + + // XOSC_CTRL: Crystal Oscillator Control Register + XOSC_CTRL_XTAL_MODE = 0xf0 // Crystal Oscillator Operating Mode + XOSC_CTRL_XTAL_TRIM = 0xf // Crystal Oscillator Load Capacitance Trimming + + // CC_CTRL_0: Channel Control Register 0 + CC_CTRL_0_CC_NUMBER = 0xff // Channel Number + + // CC_CTRL_1: Channel Control Register 1 + CC_CTRL_1_CC_BAND = 0xf // Channel Band + + // RX_SYN: Transceiver Receiver Sensitivity Control Register + RX_SYN_RX_PDT_DIS = 0x80 // Prevent Frame Reception + RX_SYN_RX_OVERRIDE = 0x40 // Receiver Override Function + RX_SYN_RX_PDT_LEVEL = 0xf // Reduce Receiver Sensitivity + + // TRX_RPC: Transceiver Reduced Power Consumption Control + TRX_RPC_RX_RPC_CTRL = 0xc0 // Smart Receiving Mode Timing + TRX_RPC_RX_RPC_EN = 0x20 // Reciver Smart Receiving Mode Enable + TRX_RPC_PDT_RPC_EN = 0x10 // Smart Receiving Mode Reduced Sensitivity Enable + TRX_RPC_PLL_RPC_EN = 0x8 // PLL Smart Receiving Mode Enable + TRX_RPC_Res0 = 0x4 // Reserved + TRX_RPC_IPAN_RPC_EN = 0x2 // Smart Receiving Mode IPAN Handling Enable + TRX_RPC_XAH_RPC_EN = 0x1 // Smart Receiving in Extended Operating Modes Enable + + // XAH_CTRL_1: Transceiver Acknowledgment Frame Control Register 1 + XAH_CTRL_1_AACK_FLTR_RES_FT = 0x20 // Filter Reserved Frames + XAH_CTRL_1_AACK_UPLD_RES_FT = 0x10 // Process Reserved Frames + XAH_CTRL_1_AACK_ACK_TIME = 0x4 // Reduce Acknowledgment Time + XAH_CTRL_1_AACK_PROM_MODE = 0x2 // Enable Promiscuous Mode + + // FTN_CTRL: Transceiver Filter Tuning Control Register + FTN_CTRL_FTN_START = 0x80 // Start Calibration Loop of Filter Tuning Network + + // PLL_CF: Transceiver Center Frequency Calibration Control Register + PLL_CF_PLL_CF_START = 0x80 // Start Center Frequency Calibration + + // PLL_DCU: Transceiver Delay Cell Calibration Control Register + PLL_DCU_PLL_DCU_START = 0x80 // Start Delay Cell Calibration + + // PART_NUM: Device Identification Register (Part Number) + PART_NUM_PART_NUM = 0xff // Part Number + + // VERSION_NUM: Device Identification Register (Version Number) + VERSION_NUM_VERSION_NUM = 0xff // Version Number + + // MAN_ID_0: Device Identification Register (Manufacture ID Low Byte) + MAN_ID_0_MAN_ID_07 = 0x80 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_06 = 0x40 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_05 = 0x20 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_04 = 0x10 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_03 = 0x8 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_02 = 0x4 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_01 = 0x2 // Manufacturer ID (Low Byte) + MAN_ID_0_MAN_ID_00 = 0x1 // Manufacturer ID (Low Byte) + + // MAN_ID_1: Device Identification Register (Manufacture ID High Byte) + MAN_ID_1_MAN_ID_ = 0xff // Manufacturer ID (High Byte) + + // SHORT_ADDR_0: Transceiver MAC Short Address Register (Low Byte) + SHORT_ADDR_0_SHORT_ADDR_07 = 0x80 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_06 = 0x40 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_05 = 0x20 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_04 = 0x10 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_03 = 0x8 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_02 = 0x4 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_01 = 0x2 // MAC Short Address + SHORT_ADDR_0_SHORT_ADDR_00 = 0x1 // MAC Short Address + + // SHORT_ADDR_1: Transceiver MAC Short Address Register (High Byte) + SHORT_ADDR_1_SHORT_ADDR_ = 0xff // MAC Short Address + + // PAN_ID_0: Transceiver Personal Area Network ID Register (Low Byte) + PAN_ID_0_PAN_ID_07 = 0x80 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_06 = 0x40 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_05 = 0x20 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_04 = 0x10 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_03 = 0x8 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_02 = 0x4 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_01 = 0x2 // MAC Personal Area Network ID + PAN_ID_0_PAN_ID_00 = 0x1 // MAC Personal Area Network ID + + // PAN_ID_1: Transceiver Personal Area Network ID Register (High Byte) + PAN_ID_1_PAN_ID_ = 0xff // MAC Personal Area Network ID + + // IEEE_ADDR_0: Transceiver MAC IEEE Address Register 0 + IEEE_ADDR_0_IEEE_ADDR_07 = 0x80 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_06 = 0x40 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_05 = 0x20 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_04 = 0x10 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_03 = 0x8 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_02 = 0x4 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_01 = 0x2 // MAC IEEE Address + IEEE_ADDR_0_IEEE_ADDR_00 = 0x1 // MAC IEEE Address + + // IEEE_ADDR_1: Transceiver MAC IEEE Address Register 1 + IEEE_ADDR_1_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // IEEE_ADDR_2: Transceiver MAC IEEE Address Register 2 + IEEE_ADDR_2_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // IEEE_ADDR_3: Transceiver MAC IEEE Address Register 3 + IEEE_ADDR_3_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // IEEE_ADDR_4: Transceiver MAC IEEE Address Register 4 + IEEE_ADDR_4_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // IEEE_ADDR_5: Transceiver MAC IEEE Address Register 5 + IEEE_ADDR_5_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // IEEE_ADDR_6: Transceiver MAC IEEE Address Register 6 + IEEE_ADDR_6_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // IEEE_ADDR_7: Transceiver MAC IEEE Address Register 7 + IEEE_ADDR_7_IEEE_ADDR_ = 0xff // MAC IEEE Address + + // XAH_CTRL_0: Transceiver Extended Operating Mode Control Register + XAH_CTRL_0_MAX_FRAME_RETRIES = 0xf0 // Maximum Number of Frame Re-transmission Attempts + XAH_CTRL_0_MAX_CSMA_RETRIES = 0xe // Maximum Number of CSMA-CA Procedure Repetition Attempts + XAH_CTRL_0_SLOTTED_OPERATION = 0x1 // Set Slotted Acknowledgment + + // CSMA_SEED_0: Transceiver CSMA-CA Random Number Generator Seed Register + CSMA_SEED_0_CSMA_SEED_07 = 0x80 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_06 = 0x40 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_05 = 0x20 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_04 = 0x10 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_03 = 0x8 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_02 = 0x4 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_01 = 0x2 // Seed Value for CSMA Random Number Generator + CSMA_SEED_0_CSMA_SEED_00 = 0x1 // Seed Value for CSMA Random Number Generator + + // CSMA_SEED_1: Transceiver Acknowledgment Frame Control Register 2 + CSMA_SEED_1_AACK_FVN_MODE = 0xc0 // Acknowledgment Frame Filter Mode + CSMA_SEED_1_AACK_SET_PD = 0x20 // Set Frame Pending Sub-field + CSMA_SEED_1_AACK_DIS_ACK = 0x10 // Disable Acknowledgment Frame Transmission + CSMA_SEED_1_AACK_I_AM_COORD = 0x8 // Set Personal Area Network Coordinator + CSMA_SEED_1_CSMA_SEED_1 = 0x7 // Seed Value for CSMA Random Number Generator + + // CSMA_BE: Transceiver CSMA-CA Back-off Exponent Control Register + CSMA_BE_MAX_BE = 0xf0 // Maximum Back-off Exponent + CSMA_BE_MIN_BE = 0xf // Minimum Back-off Exponent + + // TST_CTRL_DIGI: Transceiver Digital Test Control Register + TST_CTRL_DIGI_TST_CTRL_DIG = 0xf // Digital Test Controller Register + + // TST_RX_LENGTH: Transceiver Received Frame Length Register + TST_RX_LENGTH_RX_LENGTH = 0xff // Received Frame Length +) + +// Bitfields for SYMCNT: MAC Symbol Counter +const ( + // SCTSTRHH: Symbol Counter Transmit Frame Timestamp Register HH-Byte + SCTSTRHH_SCTSTRHH = 0xff // Symbol Counter Transmit Frame Timestamp Register HH-Byte + + // SCTSTRHL: Symbol Counter Transmit Frame Timestamp Register HL-Byte + SCTSTRHL_SCTSTRHL = 0xff // Symbol Counter Transmit Frame Timestamp Register HL-Byte + + // SCTSTRLH: Symbol Counter Transmit Frame Timestamp Register LH-Byte + SCTSTRLH_SCTSTRLH = 0xff // Symbol Counter Transmit Frame Timestamp Register LH-Byte + + // SCTSTRLL: Symbol Counter Transmit Frame Timestamp Register LL-Byte + SCTSTRLL_SCTSTRLL = 0xff // Symbol Counter Transmit Frame Timestamp Register LL-Byte + + // SCOCR1HH: Symbol Counter Output Compare Register 1 HH-Byte + SCOCR1HH_SCOCR1HH = 0xff // Symbol Counter Output Compare Register 1 HH-Byte + + // SCOCR1HL: Symbol Counter Output Compare Register 1 HL-Byte + SCOCR1HL_SCOCR1HL = 0xff // Symbol Counter Output Compare Register 1 HL-Byte + + // SCOCR1LH: Symbol Counter Output Compare Register 1 LH-Byte + SCOCR1LH_SCOCR1LH = 0xff // Symbol Counter Output Compare Register 1 LH-Byte + + // SCOCR1LL: Symbol Counter Output Compare Register 1 LL-Byte + SCOCR1LL_SCOCR1LL = 0xff // Symbol Counter Output Compare Register 1 LL-Byte + + // SCOCR2HH: Symbol Counter Output Compare Register 2 HH-Byte + SCOCR2HH_SCOCR2HH = 0xff // Symbol Counter Output Compare Register 2 HH-Byte + + // SCOCR2HL: Symbol Counter Output Compare Register 2 HL-Byte + SCOCR2HL_SCOCR2HL = 0xff // Symbol Counter Output Compare Register 2 HL-Byte + + // SCOCR2LH: Symbol Counter Output Compare Register 2 LH-Byte + SCOCR2LH_SCOCR2LH = 0xff // Symbol Counter Output Compare Register 2 LH-Byte + + // SCOCR2LL: Symbol Counter Output Compare Register 2 LL-Byte + SCOCR2LL_SCOCR2LL = 0xff // Symbol Counter Output Compare Register 2 LL-Byte + + // SCOCR3HH: Symbol Counter Output Compare Register 3 HH-Byte + SCOCR3HH_SCOCR3HH = 0xff // Symbol Counter Output Compare Register 3 HH-Byte + + // SCOCR3HL: Symbol Counter Output Compare Register 3 HL-Byte + SCOCR3HL_SCOCR3HL = 0xff // Symbol Counter Output Compare Register 3 HL-Byte + + // SCOCR3LH: Symbol Counter Output Compare Register 3 LH-Byte + SCOCR3LH_SCOCR3LH = 0xff // Symbol Counter Output Compare Register 3 LH-Byte + + // SCOCR3LL: Symbol Counter Output Compare Register 3 LL-Byte + SCOCR3LL_SCOCR3LL = 0xff // Symbol Counter Output Compare Register 3 LL-Byte + + // SCTSRHH: Symbol Counter Frame Timestamp Register HH-Byte + SCTSRHH_SCTSRHH = 0xff // Symbol Counter Frame Timestamp Register HH-Byte + + // SCTSRHL: Symbol Counter Frame Timestamp Register HL-Byte + SCTSRHL_SCTSRHL = 0xff // Symbol Counter Frame Timestamp Register HL-Byte + + // SCTSRLH: Symbol Counter Frame Timestamp Register LH-Byte + SCTSRLH_SCTSRLH = 0xff // Symbol Counter Frame Timestamp Register LH-Byte + + // SCTSRLL: Symbol Counter Frame Timestamp Register LL-Byte + SCTSRLL_SCTSRLL = 0xff // Symbol Counter Frame Timestamp Register LL-Byte + + // SCBTSRHH: Symbol Counter Beacon Timestamp Register HH-Byte + SCBTSRHH_SCBTSRHH = 0xff // Symbol Counter Beacon Timestamp Register HH-Byte + + // SCBTSRHL: Symbol Counter Beacon Timestamp Register HL-Byte + SCBTSRHL_SCBTSRHL = 0xff // Symbol Counter Beacon Timestamp Register HL-Byte + + // SCBTSRLH: Symbol Counter Beacon Timestamp Register LH-Byte + SCBTSRLH_SCBTSRLH = 0xff // Symbol Counter Beacon Timestamp Register LH-Byte + + // SCBTSRLL: Symbol Counter Beacon Timestamp Register LL-Byte + SCBTSRLL_SCBTSRLL = 0xff // Symbol Counter Beacon Timestamp Register LL-Byte + + // SCCNTHH: Symbol Counter Register HH-Byte + SCCNTHH_SCCNTHH = 0xff // Symbol Counter Register HH-Byte + + // SCCNTHL: Symbol Counter Register HL-Byte + SCCNTHL_SCCNTHL = 0xff // Symbol Counter Register HL-Byte + + // SCCNTLH: Symbol Counter Register LH-Byte + SCCNTLH_SCCNTLH = 0xff // Symbol Counter Register LH-Byte + + // SCCNTLL: Symbol Counter Register LL-Byte + SCCNTLL_SCCNTLL = 0xff // Symbol Counter Register LL-Byte + + // SCIRQS: Symbol Counter Interrupt Status Register + SCIRQS_IRQSBO = 0x10 // Backoff Slot Counter IRQ + SCIRQS_IRQSOF = 0x8 // Symbol Counter Overflow IRQ + SCIRQS_IRQSCP = 0x7 // Compare Unit 3 Compare Match IRQ + + // SCIRQM: Symbol Counter Interrupt Mask Register + SCIRQM_IRQMBO = 0x10 // Backoff Slot Counter IRQ enable + SCIRQM_IRQMOF = 0x8 // Symbol Counter Overflow IRQ enable + SCIRQM_IRQMCP = 0x7 // Symbol Counter Compare Match 3 IRQ enable + + // SCSR: Symbol Counter Status Register + SCSR_SCBSY = 0x1 // Symbol Counter busy + + // SCCR1: Symbol Counter Control Register 1 + SCCR1_Res = 0xc0 // Reserved Bit + SCCR1_SCBTSM = 0x20 // Symbol Counter Beacon Timestamp Mask Register + SCCR1_SCCKDIV = 0x1c // Clock divider for synchronous clock source (16MHz Transceiver Clock) + SCCR1_SCEECLK = 0x2 // Enable External Clock Source on PG2 + SCCR1_SCENBO = 0x1 // Backoff Slot Counter enable + + // SCCR0: Symbol Counter Control Register 0 + SCCR0_SCRES = 0x80 // Symbol Counter Synchronization + SCCR0_SCMBTS = 0x40 // Manual Beacon Timestamp + SCCR0_SCEN = 0x20 // Symbol Counter enable + SCCR0_SCCKSEL = 0x10 // Symbol Counter Clock Source select + SCCR0_SCTSE = 0x8 // Symbol Counter Automatic Timestamping enable + SCCR0_SCCMP = 0x7 // Symbol Counter Compare Unit 3 Mode select + + // SCCSR: Symbol Counter Compare Source Register + SCCSR_SCCS3 = 0x30 // Symbol Counter Compare Source select register for Compare Unit 3 + SCCSR_SCCS2 = 0xc // Symbol Counter Compare Source select register for Compare Unit 2 + SCCSR_SCCS1 = 0x3 // Symbol Counter Compare Source select register for Compare Units + + // SCRSTRHH: Symbol Counter Received Frame Timestamp Register HH-Byte + SCRSTRHH_SCRSTRHH = 0xff // Symbol Counter Received Frame Timestamp Register HH-Byte + + // SCRSTRHL: Symbol Counter Received Frame Timestamp Register HL-Byte + SCRSTRHL_SCRSTRHL = 0xff // Symbol Counter Received Frame Timestamp Register HL-Byte + + // SCRSTRLH: Symbol Counter Received Frame Timestamp Register LH-Byte + SCRSTRLH_SCRSTRLH = 0xff // Symbol Counter Received Frame Timestamp Register LH-Byte + + // SCRSTRLL: Symbol Counter Received Frame Timestamp Register LL-Byte + SCRSTRLL_SCRSTRLL = 0xff // Symbol Counter Received Frame Timestamp Register LL-Byte +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Programming Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for JTAG: JTAG Interface +const ( + // OCDR: On-Chip Debug Register + OCDR_OCDR = 0xff // On-Chip Debug Register Data +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC3 = 0xc0 // External Interrupt 3 Sense Control Bit + EICRA_ISC2 = 0x30 // External Interrupt 2 Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt 1 Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt 0 Sense Control Bit + + // EICRB: External Interrupt Control Register B + EICRB_ISC7 = 0xc0 // External Interrupt 7 Sense Control Bit + EICRB_ISC6 = 0x30 // External Interrupt 6 Sense Control Bit + EICRB_ISC5 = 0xc // External Interrupt 5 Sense Control Bit + EICRB_ISC4 = 0x3 // External Interrupt 4 Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xff // External Interrupt Request Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xff // External Interrupt Flag + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Mask + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0xff // Pin Change Enable Mask + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Mask + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0x7 // Pin Change Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0x7 // Pin Change Interrupt Enables +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC Multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // ADC Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status Register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCSRC: The ADC Control and Status Register C + ADCSRC_ADTHT = 0xc0 // ADC Track-and-Hold Time + ADCSRC_Res0 = 0x20 // Reserved + ADCSRC_ADSUT = 0x1f // ADC Start-up Time + + // DIDR2: Digital Input Disable Register 2 + DIDR2_ADC15D = 0x80 // Reserved Bits + DIDR2_ADC14D = 0x40 // Reserved Bits + DIDR2_ADC13D = 0x20 // Reserved Bits + DIDR2_ADC12D = 0x10 // Reserved Bits + DIDR2_ADC11D = 0x8 // Reserved Bits + DIDR2_ADC10D = 0x4 // Reserved Bits + DIDR2_ADC9D = 0x2 // Reserved Bits + DIDR2_ADC8D = 0x1 // Reserved Bits + + // DIDR0: Digital Input Disable Register 0 + DIDR0_ADC7D = 0x80 // Disable ADC7:0 Digital Input + DIDR0_ADC6D = 0x40 // Disable ADC7:0 Digital Input + DIDR0_ADC5D = 0x20 // Disable ADC7:0 Digital Input + DIDR0_ADC4D = 0x10 // Disable ADC7:0 Digital Input + DIDR0_ADC3D = 0x8 // Disable ADC7:0 Digital Input + DIDR0_ADC2D = 0x4 // Disable ADC7:0 Digital Input + DIDR0_ADC1D = 0x2 // Disable ADC7:0 Digital Input + DIDR0_ADC0D = 0x1 // Disable ADC7:0 Digital Input +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write Section Read Enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_CAL = 0xff // Oscillator Calibration Tuning Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR2: General Purpose I/O Register 2 + GPIOR2_GPIOR = 0xff // General Purpose I/O Register 2 Value + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose I/O Register 1 Value + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR06 = 0x40 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR05 = 0x20 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR04 = 0x10 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR03 = 0x8 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR02 = 0x4 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR01 = 0x2 // General Purpose I/O Register 0 Value + GPIOR0_GPIOR00 = 0x1 // General Purpose I/O Register 0 Value + + // PRR2: Power Reduction Register 2 + PRR2_PRRAM3 = 0x8 // Power Reduction SRAM3 + PRR2_PRRAM2 = 0x4 // Power Reduction SRAM2 + PRR2_PRRAM1 = 0x2 // Power Reduction SRAM1 + PRR2_PRRAM0 = 0x1 // Power Reduction SRAM0 + + // PRR1: Power Reduction Register 1 + PRR1_PRTRX24 = 0x40 // Power Reduction Transceiver + PRR1_PRTIM5 = 0x20 // Power Reduction Timer/Counter5 + PRR1_PRTIM4 = 0x10 // Power Reduction Timer/Counter4 + PRR1_PRTIM3 = 0x8 // Power Reduction Timer/Counter3 + PRR1_PRUSART1 = 0x1 // Power Reduction USART1 + + // PRR0: Power Reduction Register0 + PRR0_PRTWI = 0x80 // Power Reduction TWI + PRR0_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR0_PRPGA = 0x10 // Power Reduction PGA + PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR0_PRUSART0 = 0x2 // Power Reduction USART + PRR0_PRADC = 0x1 // Power Reduction ADC +) + +// Bitfields for FLASH: FLASH Controller +const ( + // NEMCR: Flash Extended-Mode Control-Register + NEMCR_ENEAM = 0x40 // Enable Extended Address Mode for Extra Rows + NEMCR_AEAM = 0x30 // Address for Extended Address Mode of Extra Rows + + // BGCR: Reference Voltage Calibration Register + BGCR_BGCAL_FINE = 0x78 // Fine Calibration Bits + BGCR_BGCAL = 0x7 // Coarse Calibration Bits +) + +// Bitfields for PWRCTRL: Power Controller +const ( + // TRXPR: Transceiver Pin Register + TRXPR_SLPTR = 0x2 // Multi-purpose Transceiver Control Bit + TRXPR_TRXRST = 0x1 // Force Transceiver Reset + + // DRTRAM0: Data Retention Configuration Register #0 + DRTRAM0_DRTSWOK = 0x20 // DRT Switch OK + DRTRAM0_ENDRT = 0x10 // Enable SRAM Data Retention + + // DRTRAM1: Data Retention Configuration Register #1 + DRTRAM1_DRTSWOK = 0x20 // DRT Switch OK + DRTRAM1_ENDRT = 0x10 // Enable SRAM Data Retention + + // DRTRAM2: Data Retention Configuration Register #2 + DRTRAM2_DRTSWOK = 0x20 // DRT Switch OK + DRTRAM2_ENDRT = 0x10 // Enable SRAM Data Retention + + // DRTRAM3: Data Retention Configuration Register #3 + DRTRAM3_DRTSWOK = 0x20 // DRT Switch OK + DRTRAM3_ENDRT = 0x10 // Enable SRAM Data Retention + + // LLDRL: Low Leakage Voltage Regulator Data Register (Low-Byte) + LLDRL_LLDRL = 0xf // Low-Byte Data Register Bits + + // LLDRH: Low Leakage Voltage Regulator Data Register (High-Byte) + LLDRH_LLDRH = 0x1f // High-Byte Data Register Bits + + // LLCR: Low Leakage Voltage Regulator Control Register + LLCR_LLDONE = 0x20 // Calibration Done + LLCR_LLCOMP = 0x10 // Comparator Output + LLCR_LLCAL = 0x8 // Calibration Active + LLCR_LLTCO = 0x4 // Temperature Coefficient of Current Source + LLCR_LLSHORT = 0x2 // Short Lower Calibration Circuit + LLCR_LLENCAL = 0x1 // Enable Automatic Calibration + + // DPDS0: Port Driver Strength Register 0 + DPDS0_PFDRV = 0xc0 // Driver Strength Port F + DPDS0_PEDRV = 0x30 // Driver Strength Port E + DPDS0_PDDRV = 0xc // Driver Strength Port D + DPDS0_PBDRV = 0x3 // Driver Strength Port B + + // DPDS1: Port Driver Strength Register 1 + DPDS1_PGDRV = 0x3 // Driver Strength Port G +) diff --git a/src/device/avr/atmega64rfr2.ld b/src/device/avr/atmega64rfr2.ld new file mode 100644 index 00000000..afa7348f --- /dev/null +++ b/src/device/avr/atmega64rfr2.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega64RFR2.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x10000; +__ram_size = 0x2000; +__num_isrs = 71; diff --git a/src/device/avr/atmega8.go b/src/device/avr/atmega8.go new file mode 100644 index 00000000..db309c69 --- /dev/null +++ b/src/device/avr/atmega8.go @@ -0,0 +1,463 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega8.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega8 + +// Device information for the ATmega8. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega8" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_TIMER2_COMP = 3 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 4 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 5 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 6 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 7 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 8 // Timer/Counter1 Overflow + IRQ_TIMER0_OVF = 9 // Timer/Counter0 Overflow + IRQ_SPI_STC = 10 // Serial Transfer Complete + IRQ_USART_RXC = 11 // USART, Rx Complete + IRQ_USART_UDRE = 12 // USART Data Register Empty + IRQ_USART_TXC = 13 // USART, Tx Complete + IRQ_ADC = 14 // ADC Conversion Complete + IRQ_EE_RDY = 15 // EEPROM Ready + IRQ_ANA_COMP = 16 // Analog Comparator + IRQ_TWI = 17 // 2-wire Serial Interface + IRQ_SPM_RDY = 18 // Store Program Memory Ready + IRQ_max = 18 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + HIGH __reg + LOW __reg + }{ + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog Comparator + AC = struct { + ACSR __reg + }{ + ACSR: 0x28, // Analog Comparator Control And Status Register + } + + // Serial Peripheral Interface + SPI = struct { + SPDR __reg + SPSR __reg + SPCR __reg + }{ + SPDR: 0x2f, // SPI Data Register + SPSR: 0x2e, // SPI Status Register + SPCR: 0x2d, // SPI Control Register + } + + // External Interrupts + EXINT = struct { + GICR __reg + GIFR __reg + }{ + GICR: 0x5b, // General Interrupt Control Register + GIFR: 0x5a, // General Interrupt Flag Register + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0 __reg + TCNT0 __reg + }{ + TCCR0: 0x53, // Timer/Counter0 Control Register + TCNT0: 0x52, // Timer Counter 0 + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TCCR1A: 0x4f, // Timer/Counter1 Control Register A + TCCR1B: 0x4e, // Timer/Counter1 Control Register B + TCNT1L: 0x4c, // Timer/Counter1 Bytes + TCNT1H: 0x4c, // Timer/Counter1 Bytes + OCR1AL: 0x4a, // Timer/Counter1 Output Compare Register Bytes + OCR1AH: 0x4a, // Timer/Counter1 Output Compare Register Bytes + OCR1BL: 0x48, // Timer/Counter1 Output Compare Register Bytes + OCR1BH: 0x48, // Timer/Counter1 Output Compare Register Bytes + ICR1L: 0x46, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x46, // Timer/Counter1 Input Capture Register Bytes + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2 __reg + TCNT2 __reg + OCR2 __reg + ASSR __reg + }{ + TCCR2: 0x45, // Timer/Counter2 Control Register + TCNT2: 0x44, // Timer/Counter2 + OCR2: 0x43, // Timer/Counter2 Output Compare Register + ASSR: 0x42, // Asynchronous Status Register + } + + // USART + USART = struct { + UDR __reg + UCSRA __reg + UCSRB __reg + UCSRC __reg + UBRRH __reg + UBRRL __reg + }{ + UDR: 0x2c, // USART I/O Data Register + UCSRA: 0x2b, // USART Control and Status Register A + UCSRB: 0x2a, // USART Control and Status Register B + UCSRC: 0x40, // USART Control and Status Register C + UBRRH: 0x40, // USART Baud Rate Register Hight Byte + UBRRL: 0x29, // USART Baud Rate Register Low Byte + } + + // Two Wire Serial Interface + TWI = struct { + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWBR: 0x20, // TWI Bit Rate register + TWCR: 0x56, // TWI Control Register + TWSR: 0x21, // TWI Status Register + TWDR: 0x23, // TWI Data register + TWAR: 0x22, // TWI (Slave) Address register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x41, // Watchdog Timer Control Register + } + + // I/O Port + PORT = struct { + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + }{ + PORTB: 0x38, // Port B Data Register + DDRB: 0x37, // Port B Data Direction Register + PINB: 0x36, // Port B Input Pins + PORTC: 0x35, // Port C Data Register + DDRC: 0x34, // Port C Data Direction Register + PINC: 0x33, // Port C Input Pins + PORTD: 0x32, // Port D Data Register + DDRD: 0x31, // Port D Data Direction Register + PIND: 0x30, // Port D Input Pins + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x3e, // EEPROM Address Register Bytes + EEARH: 0x3e, // EEPROM Address Register Bytes + EEDR: 0x3d, // EEPROM Data Register + EECR: 0x3c, // EEPROM Control Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + MCUCSR __reg + OSCCAL __reg + SPMCR __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + MCUCSR: 0x54, // MCU Control And Status Register + OSCCAL: 0x51, // Oscillator Calibration Value + SPMCR: 0x57, // Store Program Memory Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + }{ + ADMUX: 0x27, // The ADC multiplexer Selection Register + ADCSRA: 0x26, // The ADC Control and Status register + ADCL: 0x24, // ADC Data Register Bytes + ADCH: 0x24, // ADC Data Register Bytes + } +) + +// Bitfields for FUSE: Fuses +const ( + // HIGH + HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PC6 as i/o pin) + HIGH_WDTON = 0x40 // Watch-dog Timer always on + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + HIGH_CKOPT = 0x10 // CKOPT fuse (operation dependent of CKSEL fuses) + + // LOW + LOW_BODLEVEL = 0x80 // Brownout detector trigger level + LOW_BODEN = 0x40 // Brown-out detection enabled + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects +) + +// Bitfields for EXINT: External Interrupts +const ( + // GICR: General Interrupt Control Register + GICR_INT = 0xc0 // External Interrupt Request 1 Enable + GICR_IVSEL = 0x2 // Interrupt Vector Select + GICR_IVCE = 0x1 // Interrupt Vector Change Enable + + // GIFR: General Interrupt Flag Register + GIFR_INTF = 0xc0 // External Interrupt Flags +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0: Timer/Counter0 Control Register + TCCR0_CS02 = 0x4 // Clock Select0 bit 2 + TCCR0_CS01 = 0x2 // Clock Select0 bit 1 + TCCR0_CS00 = 0x1 // Clock Select0 bit 0 +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_FOC1A = 0x8 // Force Output Compare 1A + TCCR1A_FOC1B = 0x4 // Force Output Compare 1B + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2: Timer/Counter2 Control Register + TCCR2_FOC2 = 0x80 // Force Output Compare + TCCR2_WGM20 = 0x40 // Waveform Genration Mode + TCCR2_COM2 = 0x30 // Compare Output Mode bits + TCCR2_WGM21 = 0x8 // Waveform Generation Mode + TCCR2_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_AS2 = 0x8 // Asynchronous Timer/counter2 + ASSR_TCN2UB = 0x4 // Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // Timer/counter Control Register2 Update Busy +) + +// Bitfields for USART: USART +const ( + // UCSRA: USART Control and Status Register A + UCSRA_RXC = 0x80 // USART Receive Complete + UCSRA_TXC = 0x40 // USART Transmitt Complete + UCSRA_UDRE = 0x20 // USART Data Register Empty + UCSRA_FE = 0x10 // Framing Error + UCSRA_DOR = 0x8 // Data overRun + UCSRA_UPE = 0x4 // Parity Error + UCSRA_U2X = 0x2 // Double the USART transmission speed + UCSRA_MPCM = 0x1 // Multi-processor Communication Mode + + // UCSRB: USART Control and Status Register B + UCSRB_RXCIE = 0x80 // RX Complete Interrupt Enable + UCSRB_TXCIE = 0x40 // TX Complete Interrupt Enable + UCSRB_UDRIE = 0x20 // USART Data register Empty Interrupt Enable + UCSRB_RXEN = 0x10 // Receiver Enable + UCSRB_TXEN = 0x8 // Transmitter Enable + UCSRB_UCSZ2 = 0x4 // Character Size + UCSRB_RXB8 = 0x2 // Receive Data Bit 8 + UCSRB_TXB8 = 0x1 // Transmit Data Bit 8 + + // UCSRC: USART Control and Status Register C + UCSRC_URSEL = 0x80 // Register Select + UCSRC_UMSEL = 0x40 // USART Mode Select + UCSRC_UPM = 0x30 // Parity Mode Bits + UCSRC_USBS = 0x8 // Stop Bit Select + UCSRC_UCSZ = 0x6 // Character Size + UCSRC_UCPOL = 0x1 // Clock Polarity +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // MCUCSR: MCU Control And Status Register + MCUCSR_WDRF = 0x8 // Watchdog Reset Flag + MCUCSR_BORF = 0x4 // Brown-out Reset Flag + MCUCSR_EXTRF = 0x2 // External Reset Flag + MCUCSR_PORF = 0x1 // Power-on reset flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // SPMCR: Store Program Memory Control Register + SPMCR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCR_RWWSB = 0x40 // Read-While-Write Section Busy + SPMCR_RWWSRE = 0x10 // Read-While-Write Section Read Enable + SPMCR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCR_PGWRT = 0x4 // Page Write + SPMCR_PGERS = 0x2 // Page Erase + SPMCR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0xf // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADFR = 0x20 // ADC Free Running Select + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits +) diff --git a/src/device/avr/atmega8.ld b/src/device/avr/atmega8.ld new file mode 100644 index 00000000..44eebce2 --- /dev/null +++ b/src/device/avr/atmega8.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega8.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_size = 0x400; +__num_isrs = 19; diff --git a/src/device/avr/atmega8515.go b/src/device/avr/atmega8515.go new file mode 100644 index 00000000..5be2c373 --- /dev/null +++ b/src/device/avr/atmega8515.go @@ -0,0 +1,420 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega8515.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega8515 + +// Device information for the ATmega8515. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega8515" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Reset, Power-on Reset and Watchdog Reset + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_TIMER1_CAPT = 3 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 4 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 5 // Timer/Counter1 Compare MatchB + IRQ_TIMER1_OVF = 6 // Timer/Counter1 Overflow + IRQ_TIMER0_OVF = 7 // Timer/Counter0 Overflow + IRQ_SPI_STC = 8 // Serial Transfer Complete + IRQ_USART_RX = 9 // USART, Rx Complete + IRQ_USART_UDRE = 10 // USART Data Register Empty + IRQ_USART_TX = 11 // USART, Tx Complete + IRQ_ANA_COMP = 12 // Analog Comparator + IRQ_INT2 = 13 // External Interrupt Request 2 + IRQ_TIMER0_COMP = 14 // Timer 0 Compare Match + IRQ_EE_RDY = 15 // EEPROM Ready + IRQ_SPM_RDY = 16 // Store Program Memory Ready + IRQ_max = 16 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + HIGH __reg + LOW __reg + }{ + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog Comparator + AC = struct { + ACSR __reg + }{ + ACSR: 0x28, // Analog Comparator Control And Status Register + } + + // USART + USART = struct { + UDR __reg + UCSRA __reg + UCSRB __reg + UCSRC __reg + UBRRH __reg + UBRRL __reg + }{ + UDR: 0x2c, // USART I/O Data Register + UCSRA: 0x2b, // USART Control and Status Register A + UCSRB: 0x2a, // USART Control and Status Register B + UCSRC: 0x40, // USART Control and Status Register C + UBRRH: 0x40, // USART Baud Rate Register High Byte + UBRRL: 0x29, // USART Baud Rate Register Low Byte + } + + // Serial Peripheral Interface + SPI = struct { + SPDR __reg + SPSR __reg + SPCR __reg + }{ + SPDR: 0x2f, // SPI Data Register + SPSR: 0x2e, // SPI Status Register + SPCR: 0x2d, // SPI Control Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + EMCUCR __reg + MCUCR __reg + MCUCSR __reg + OSCCAL __reg + SPMCR __reg + SFIOR __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + EMCUCR: 0x56, // Extended MCU Control Register + MCUCR: 0x55, // MCU Control Register + MCUCSR: 0x54, // MCU Control And Status Register + OSCCAL: 0x24, // Oscillator Calibration Value + SPMCR: 0x57, // Store Program Memory Control Register + SFIOR: 0x50, // Special Function IO Register + } + + // External Interrupts + EXINT = struct { + GICR __reg + GIFR __reg + }{ + GICR: 0x5b, // General Interrupt Control Register + GIFR: 0x5a, // General Interrupt Flag Register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x41, // Watchdog Timer Control Register + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0 __reg + TCNT0 __reg + OCR0 __reg + }{ + TCCR0: 0x53, // Timer/Counter 0 Control Register + TCNT0: 0x52, // Timer/Counter 0 Register + OCR0: 0x51, // Timer/Counter 0 Output Compare Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TCCR1A: 0x4f, // Timer/Counter1 Control Register A + TCCR1B: 0x4e, // Timer/Counter1 Control Register B + TCNT1L: 0x4c, // Timer/Counter1 Bytes + TCNT1H: 0x4c, // Timer/Counter1 Bytes + OCR1AL: 0x4a, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x4a, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x48, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x48, // Timer/Counter1 Output Compare Register B Bytes + ICR1L: 0x44, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x44, // Timer/Counter1 Input Capture Register Bytes + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + }{ + PORTA: 0x3b, // Port A Data Register + DDRA: 0x3a, // Port A Data Direction Register + PINA: 0x39, // Port A Input Pins + PORTB: 0x38, // Port B Data Register + DDRB: 0x37, // Port B Data Direction Register + PINB: 0x36, // Port B Input Pins + PORTC: 0x35, // Port C Data Register + DDRC: 0x34, // Port C Data Direction Register + PINC: 0x33, // Port C Input Pins + PORTD: 0x32, // Port D Data Register + DDRD: 0x31, // Port D Data Direction Register + PIND: 0x30, // Port D Input Pins + PORTE: 0x27, // Port E Data Register + DDRE: 0x26, // Port E Data Direction Register + PINE: 0x25, // Port E Input Pins + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x3e, // EEPROM Address Register Bytes + EEARH: 0x3e, // EEPROM Address Register Bytes + EEDR: 0x3d, // EEPROM Data Register + EECR: 0x3c, // EEPROM Control Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // HIGH + HIGH_S8515C = 0x80 // AT90S4414/8515 compatibility mode + HIGH_WDTON = 0x40 // Watch-dog Timer always on + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + HIGH_CKOPT = 0x10 // CKOPT fuse (operation dependent of CKSEL fuses)] + + // LOW + LOW_BODLEVEL = 0x80 // Brownout detector trigger level + LOW_BODEN = 0x40 // Brown-out detection enabled + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits +) + +// Bitfields for USART: USART +const ( + // UCSRA: USART Control and Status Register A + UCSRA_RXC = 0x80 // USART Receive Complete + UCSRA_TXC = 0x40 // USART Transmitt Complete + UCSRA_UDRE = 0x20 // USART Data Register Empty + UCSRA_FE = 0x10 // Framing Error + UCSRA_DOR = 0x8 // Data overRun + UCSRA_UPE = 0x4 // Parity Error + UCSRA_U2X = 0x2 // Double the USART transmission speed + UCSRA_MPCM = 0x1 // Multi-processor Communication Mode + + // UCSRB: USART Control and Status Register B + UCSRB_RXCIE = 0x80 // RX Complete Interrupt Enable + UCSRB_TXCIE = 0x40 // TX Complete Interrupt Enable + UCSRB_UDRIE = 0x20 // USART Data register Empty Interrupt Enable + UCSRB_RXEN = 0x10 // Receiver Enable + UCSRB_TXEN = 0x8 // Transmitter Enable + UCSRB_UCSZ2 = 0x4 // Character Size Bit 2 + UCSRB_RXB8 = 0x2 // Receive Data Bit 8 + UCSRB_TXB8 = 0x1 // Transmit Data Bit 8 + + // UCSRC: USART Control and Status Register C + UCSRC_URSEL = 0x80 // Register Select + UCSRC_UMSEL = 0x40 // USART Mode Select + UCSRC_UPM = 0x30 // Parity Mode Bits + UCSRC_USBS = 0x8 // Stop Bit Select + UCSRC_UCSZ = 0x6 // Character Size Bits + UCSRC_UCPOL = 0x1 // Clock Polarity + + // UBRRH: USART Baud Rate Register High Byte + UBRRH_URSEL = 0x80 // Register Select + UBRRH_UBRR1 = 0xc // USART Baud Rate Register bit 11 + UBRRH_UBRR = 0x3 // USART Baud Rate Register bits +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // EMCUCR: Extended MCU Control Register + EMCUCR_SM0 = 0x80 // Sleep Mode Select Bit 0 + EMCUCR_SRL = 0x70 // Wait State Selector Limit bits + EMCUCR_SRW0 = 0xc // Wait State Select Bits for Lower Sector, bits + EMCUCR_SRW11 = 0x2 // Wait State Select Bits for Upper Sector, bit 1 + EMCUCR_ISC2 = 0x1 // Interrupt Sense Control 2 + + // MCUCR: MCU Control Register + MCUCR_SRE = 0x80 // External SRAM/XMEM Enable + MCUCR_SRW10 = 0x40 // Wait State Select Bits for Upper Sector, bit 0 + MCUCR_SE = 0x20 // Sleep Enable + MCUCR_SM1 = 0x10 // Sleep Mode Select Bit 1 + MCUCR_ISC1 = 0xc // Interrupt Sense Control 1 Bits + MCUCR_ISC0 = 0x3 // Interrupt Sense Control 0 Bits + + // MCUCSR: MCU Control And Status Register + MCUCSR_SM2 = 0x20 // Sleep Mode Select Bit 2 + MCUCSR_WDRF = 0x8 // Watchdog Reset Flag + MCUCSR_BORF = 0x4 // Brown-out Reset Flag + MCUCSR_EXTRF = 0x2 // External Reset Flag + MCUCSR_PORF = 0x1 // Power-on reset flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // SPMCR: Store Program Memory Control Register + SPMCR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCR_RWWSB = 0x40 // Read-While-Write Section Busy + SPMCR_RWWSRE = 0x10 // Read-While-Write Section Read Enable + SPMCR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCR_PGWRT = 0x4 // Page Write + SPMCR_PGERS = 0x2 // Page Erase + SPMCR_SPMEN = 0x1 // Store Program Memory Enable + + // SFIOR: Special Function IO Register + SFIOR_XMBK = 0x40 // External Memory Bus Keeper Enable + SFIOR_XMM = 0x38 // External Memory High Mask Bits + SFIOR_PUD = 0x4 // Pull-up Disable + SFIOR_PSR10 = 0x1 // Prescaler Reset Timer / Counter 1 and Timer / Counter 0 +) + +// Bitfields for EXINT: External Interrupts +const ( + // GICR: General Interrupt Control Register + GICR_INT0 = 0x40 // External Interrupt Request 0 Enable + GICR_INT1 = 0x80 // External Interrupt Request 1 Enable + GICR_INT2 = 0x20 // External Interrupt Request 2 Enable + GICR_IVSEL = 0x2 // Interrupt Vector Select + GICR_IVCE = 0x1 // Interrupt Vector Change Enable + + // GIFR: General Interrupt Flag Register + GIFR_INTF = 0xc0 // External Interrupt Flags + GIFR_INTF2 = 0x20 // External Interrupt Flag 2 +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0: Timer/Counter 0 Control Register + TCCR0_FOC0 = 0x80 // Force Output Compare + TCCR0_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0_COM0 = 0x30 // Compare Match Output Modes + TCCR0_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0_CS0 = 0x7 // Clock Selects +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_FOC1A = 0x8 // Force Output Compare for Channel A + TCCR1A_FOC1B = 0x4 // Force Output Compare for Channel B + TCCR1A_WGM1 = 0x3 // Pulse Width Modulator Select Bits + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Pulse Width Modulator Select Bits + TCCR1B_CS1 = 0x7 // Clock Select1 bits +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) diff --git a/src/device/avr/atmega8515.ld b/src/device/avr/atmega8515.ld new file mode 100644 index 00000000..d024d1ad --- /dev/null +++ b/src/device/avr/atmega8515.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega8515.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_size = 0x200; +__num_isrs = 17; diff --git a/src/device/avr/atmega8535.go b/src/device/avr/atmega8535.go new file mode 100644 index 00000000..b7a4e78f --- /dev/null +++ b/src/device/avr/atmega8535.go @@ -0,0 +1,475 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega8535.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega8535 + +// Device information for the ATmega8535. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega8535" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Reset, Power-on Reset and Watchdog Reset + IRQ_INT0 = 1 // External Interrupt 0 + IRQ_INT1 = 2 // External Interrupt 1 + IRQ_TIMER2_COMP = 3 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 4 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 5 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 6 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 7 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 8 // Timer/Counter1 Overflow + IRQ_TIMER0_OVF = 9 // Timer/Counter0 Overflow + IRQ_SPI_STC = 10 // SPI Serial Transfer Complete + IRQ_USART_RX = 11 // USART, RX Complete + IRQ_USART_UDRE = 12 // USART Data Register Empty + IRQ_USART_TX = 13 // USART, TX Complete + IRQ_ADC = 14 // ADC Conversion Complete + IRQ_EE_RDY = 15 // EEPROM Ready + IRQ_ANA_COMP = 16 // Analog Comparator + IRQ_TWI = 17 // Two-wire Serial Interface + IRQ_INT2 = 18 // External Interrupt Request 2 + IRQ_TIMER0_COMP = 19 // TimerCounter0 Compare Match + IRQ_SPM_RDY = 20 // Store Program Memory Read + IRQ_max = 20 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + HIGH __reg + LOW __reg + }{ + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + }{ + ADMUX: 0x27, // The ADC multiplexer Selection Register + ADCSRA: 0x26, // The ADC Control and Status register + ADCL: 0x24, // ADC Data Register Bytes + ADCH: 0x24, // ADC Data Register Bytes + } + + // Analog Comparator + AC = struct { + ACSR __reg + }{ + ACSR: 0x28, // Analog Comparator Control And Status Register + } + + // Two Wire Serial Interface + TWI = struct { + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWBR: 0x20, // TWI Bit Rate register + TWCR: 0x56, // TWI Control Register + TWSR: 0x21, // TWI Status Register + TWDR: 0x23, // TWI Data register + TWAR: 0x22, // TWI (Slave) Address register + } + + // USART + USART = struct { + UDR __reg + UCSRA __reg + UCSRB __reg + UCSRC __reg + UBRRH __reg + UBRRL __reg + }{ + UDR: 0x2c, // USART I/O Data Register + UCSRA: 0x2b, // USART Control and Status Register A + UCSRB: 0x2a, // USART Control and Status Register B + UCSRC: 0x40, // USART Control and Status Register C + UBRRH: 0x40, // USART Baud Rate Register High Byte + UBRRL: 0x29, // USART Baud Rate Register Low Byte + } + + // I/O Port + PORT = struct { + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + }{ + PORTA: 0x3b, // Port A Data Register + DDRA: 0x3a, // Port A Data Direction Register + PINA: 0x39, // Port A Input Pins + PORTB: 0x38, // Port B Data Register + DDRB: 0x37, // Port B Data Direction Register + PINB: 0x36, // Port B Input Pins + PORTC: 0x35, // Port C Data Register + DDRC: 0x34, // Port C Data Direction Register + PINC: 0x33, // Port C Input Pins + PORTD: 0x32, // Port D Data Register + DDRD: 0x31, // Port D Data Direction Register + PIND: 0x30, // Port D Input Pins + } + + // Serial Peripheral Interface + SPI = struct { + SPDR __reg + SPSR __reg + SPCR __reg + }{ + SPDR: 0x2f, // SPI Data Register + SPSR: 0x2e, // SPI Status Register + SPCR: 0x2d, // SPI Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x3e, // EEPROM Address Register Bytes + EEARH: 0x3e, // EEPROM Address Register Bytes + EEDR: 0x3d, // EEPROM Data Register + EECR: 0x3c, // EEPROM Control Register + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0 __reg + TCNT0 __reg + OCR0 __reg + }{ + TCCR0: 0x53, // Timer/Counter Control Register + TCNT0: 0x52, // Timer/Counter Register + OCR0: 0x5c, // Output Compare Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TCCR1A: 0x4f, // Timer/Counter1 Control Register A + TCCR1B: 0x4e, // Timer/Counter1 Control Register B + TCNT1L: 0x4c, // Timer/Counter1 Bytes + TCNT1H: 0x4c, // Timer/Counter1 Bytes + OCR1AL: 0x4a, // Timer/Counter1 Output Compare Register Bytes + OCR1AH: 0x4a, // Timer/Counter1 Output Compare Register Bytes + OCR1BL: 0x48, // Timer/Counter1 Output Compare Register Bytes + OCR1BH: 0x48, // Timer/Counter1 Output Compare Register Bytes + ICR1L: 0x46, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x46, // Timer/Counter1 Input Capture Register Bytes + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2 __reg + TCNT2 __reg + OCR2 __reg + ASSR __reg + }{ + TCCR2: 0x45, // Timer/Counter2 Control Register + TCNT2: 0x44, // Timer/Counter2 + OCR2: 0x43, // Timer/Counter2 Output Compare Register + ASSR: 0x42, // Asynchronous Status Register + } + + // External Interrupts + EXINT = struct { + GICR __reg + GIFR __reg + }{ + GICR: 0x5b, // General Interrupt Control Register + GIFR: 0x5a, // General Interrupt Flag Register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x41, // Watchdog Timer Control Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + OSCCAL __reg + SPMCR __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + OSCCAL: 0x51, // Oscillator Calibration Value + SPMCR: 0x57, + } +) + +// Bitfields for FUSE: Fuses +const ( + // HIGH + HIGH_S8535C = 0x80 // AT90S4434/8535 compatibility mode + HIGH_WDTON = 0x40 // Watch-dog Timer always on + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + HIGH_CKOPT = 0x10 // CKOPT fuse (operation dependent of CKSEL fuses) + + // LOW + LOW_BODLEVEL = 0x80 // Brownout detector trigger level + LOW_BODEN = 0x40 // Brown-out detection enabled + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for USART: USART +const ( + // UCSRA: USART Control and Status Register A + UCSRA_RXC = 0x80 // USART Receive Complete + UCSRA_TXC = 0x40 // USART Transmitt Complete + UCSRA_UDRE = 0x20 // USART Data Register Empty + UCSRA_FE = 0x10 // Framing Error + UCSRA_DOR = 0x8 // Data overRun + UCSRA_UPE = 0x4 // Parity Error + UCSRA_U2X = 0x2 // Double the USART transmission speed + UCSRA_MPCM = 0x1 // Multi-processor Communication Mode + + // UCSRB: USART Control and Status Register B + UCSRB_RXCIE = 0x80 // RX Complete Interrupt Enable + UCSRB_TXCIE = 0x40 // TX Complete Interrupt Enable + UCSRB_UDRIE = 0x20 // USART Data register Empty Interrupt Enable + UCSRB_RXEN = 0x10 // Receiver Enable + UCSRB_TXEN = 0x8 // Transmitter Enable + UCSRB_UCSZ2 = 0x4 // Character Size Bit 2 + UCSRB_RXB8 = 0x2 // Receive Data Bit 8 + UCSRB_TXB8 = 0x1 // Transmit Data Bit 8 + + // UCSRC: USART Control and Status Register C + UCSRC_URSEL = 0x80 // Register Select + UCSRC_UMSEL = 0x40 // USART Mode Select + UCSRC_UPM = 0x30 // Parity Mode Bits + UCSRC_USBS = 0x8 // Stop Bit Select + UCSRC_UCSZ = 0x6 // Character Size Bits + UCSRC_UCPOL = 0x1 // Clock Polarity + + // UBRRH: USART Baud Rate Register High Byte + UBRRH_URSEL = 0x80 // Register Select + UBRRH_UBRR1 = 0xc // USART Baud Rate Register bit 11 + UBRRH_UBRR = 0x3 // USART Baud Rate Register bits +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0: Timer/Counter Control Register + TCCR0_FOC0 = 0x80 // Force Output Compare + TCCR0_WGM00 = 0x40 // Waveform Generation Mode 0 + TCCR0_COM0 = 0x30 // Compare Match Output Modes + TCCR0_WGM01 = 0x8 // Waveform Generation Mode 1 + TCCR0_CS0 = 0x7 // Clock Selects +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_FOC1A = 0x8 // Force Output Compare 1A + TCCR1A_FOC1B = 0x4 // Force Output Compare 1B + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2: Timer/Counter2 Control Register + TCCR2_FOC2 = 0x80 // Force Output Compare + TCCR2_WGM20 = 0x40 // Waveform Genration Mode + TCCR2_COM2 = 0x30 // Compare Output Mode bits + TCCR2_WGM21 = 0x8 // Waveform Generation Mode + TCCR2_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_AS2 = 0x8 // Asynchronous Timer/counter2 + ASSR_TCN2UB = 0x4 // Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // Timer/counter Control Register2 Update Busy +) + +// Bitfields for EXINT: External Interrupts +const ( + // GICR: General Interrupt Control Register + GICR_INT0 = 0x40 // External Interrupt Request 0 Enable + GICR_INT1 = 0x80 // External Interrupt Request 1 Enable + GICR_INT2 = 0x20 // External Interrupt Request 2 Enable + GICR_IVSEL = 0x2 // Interrupt Vector Select + GICR_IVCE = 0x1 // Interrupt Vector Change Enable + + // GIFR: General Interrupt Flag Register + GIFR_INTF = 0xc0 // External Interrupt Flags + GIFR_INTF2 = 0x20 // External Interrupt Flag 2 +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // SPMCR + SPMCR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCR_RWWSB = 0x40 // Read-While-Write Section Busy + SPMCR_RWWSRE = 0x10 // Read-While-Write Section Read Enable + SPMCR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCR_PGWRT = 0x4 // Page Write + SPMCR_PGERS = 0x2 // Page Erase + SPMCR_SPMEN = 0x1 // Store Program Memory Enable +) diff --git a/src/device/avr/atmega8535.ld b/src/device/avr/atmega8535.ld new file mode 100644 index 00000000..b28fa919 --- /dev/null +++ b/src/device/avr/atmega8535.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega8535.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_size = 0x200; +__num_isrs = 21; diff --git a/src/device/avr/atmega88.go b/src/device/avr/atmega88.go new file mode 100644 index 00000000..cfd29546 --- /dev/null +++ b/src/device/avr/atmega88.go @@ -0,0 +1,640 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega88.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega88 + +// Device information for the ATmega88. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega88" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_PCINT0 = 3 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 4 // Pin Change Interrupt Request 0 + IRQ_PCINT2 = 5 // Pin Change Interrupt Request 1 + IRQ_WDT = 6 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 7 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 8 // Timer/Counter2 Compare Match A + IRQ_TIMER2_OVF = 9 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 10 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 11 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 12 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 13 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 14 // TimerCounter0 Compare Match A + IRQ_TIMER0_COMPB = 15 // TimerCounter0 Compare Match B + IRQ_TIMER0_OVF = 16 // Timer/Couner0 Overflow + IRQ_SPI_STC = 17 // SPI Serial Transfer Complete + IRQ_USART_RX = 18 // USART Rx Complete + IRQ_USART_UDRE = 19 // USART, Data Register Empty + IRQ_USART_TX = 20 // USART Tx Complete + IRQ_ADC = 21 // ADC Conversion Complete + IRQ_EE_READY = 22 // EEPROM Ready + IRQ_ANALOG_COMP = 23 // Analog Comparator + IRQ_TWI = 24 // Two-wire Serial Interface + IRQ_SPM_Ready = 25 // Store Program Memory Read + IRQ_max = 25 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + ADCSRB __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // The ADC Control and Status register A + ADCSRB: 0x7b, // The ADC Control and Status register B + DIDR0: 0x7e, // Digital Input Disable Register + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // I/O Port + PORT = struct { + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + }{ + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCICR __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + } + + // Serial Peripheral Interface + SPI = struct { + SPDR __reg + SPSR __reg + SPCR __reg + }{ + SPDR: 0x4e, // SPI Data Register + SPSR: 0x4d, // SPI Status Register + SPCR: 0x4c, // SPI Control Register + } + + // CPU Registers + CPU = struct { + PRR __reg + OSCCAL __reg + CLKPR __reg + SREG __reg + SPL __reg + SPH __reg + SPMCSR __reg + MCUCR __reg + MCUSR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + PRR: 0x64, // Power Reduction Register + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + SPMCSR: 0x57, // Store Program Memory Control and Status Register + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose I/O Register 2 + GPIOR1: 0x4a, // General Purpose I/O Register 1 + GPIOR0: 0x3e, // General Purpose I/O Register 0 + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Bytes + EEARH: 0x41, // EEPROM Address Register Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BOOTSZ = 0x6 // Select boot size + EXTENDED_BOOTRST = 0x1 // Boot Reset vector Enabled + + // HIGH + HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PC6 as i/o pin)] + HIGH_DWEN = 0x40 // Debug Wire enable + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watch-dog Timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTB0 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0xc0 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TIMSK1: Timer/Counter Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output CompareB Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output CompareA Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 + TCCR1C_FOC1B = 0x40 +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2B = 0x4 // Output Compare Flag 2B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Output Mode bits + TCCR2A_COM2B = 0x30 // Compare Output Mode bits + TCCR2A_WGM2 = 0x3 // Waveform Genration Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy + ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0xf // Analog Channel Selection Bits + + // ADCSRA: The ADC Control and Status register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCSRB: The ADC Control and Status register B + ADCSRB_ACME = 0x40 + ADCSRB_ADTS = 0x7 // ADC Auto Trigger Source bits + + // DIDR0: Digital Input Disable Register + DIDR0_ADC5D = 0x20 + DIDR0_ADC4D = 0x10 + DIDR0_ADC3D = 0x8 + DIDR0_ADC2D = 0x4 + DIDR0_ADC1D = 0x2 + DIDR0_ADC0D = 0x1 +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register + EICRA_ISC1 = 0xc // External Interrupt Sense Control 1 Bits + EICRA_ISC0 = 0x3 // External Interrupt Sense Control 0 Bits + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0x3 // External Interrupt Request 1 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0x3 // External Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0x7 // Pin Change Interrupt Enables + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0x7f // Pin Change Enable Masks + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0x7 // Pin Change Interrupt Flags +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects +) + +// Bitfields for CPU: CPU Registers +const ( + // PRR: Power Reduction Register + PRR_PRTWI = 0x80 // Power Reduction TWI + PRR_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // SPMCSR: Store Program Memory Control and Status Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read-While-Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read-While-Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SELFPRGEN = 0x1 // Self Programming Enable + + // MCUCR: MCU Control Register + MCUCR_PUD = 0x10 // Pull-up Disable + MCUCR_IVSEL = 0x2 // Interrupt Vector Select + MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable + + // MCUSR: MCU Status Register + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BORF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode + SMCR_SE = 0x1 // Sleep Enable +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) diff --git a/src/device/avr/atmega88.ld b/src/device/avr/atmega88.ld new file mode 100644 index 00000000..4dce5393 --- /dev/null +++ b/src/device/avr/atmega88.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega88.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_size = 0x400; +__num_isrs = 26; diff --git a/src/device/avr/atmega88a.go b/src/device/avr/atmega88a.go new file mode 100644 index 00000000..b9929532 --- /dev/null +++ b/src/device/avr/atmega88a.go @@ -0,0 +1,641 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega88A.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega88a + +// Device information for the ATmega88A. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega88A" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_PCINT0 = 3 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 4 // Pin Change Interrupt Request 0 + IRQ_PCINT2 = 5 // Pin Change Interrupt Request 1 + IRQ_WDT = 6 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 7 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 8 // Timer/Counter2 Compare Match A + IRQ_TIMER2_OVF = 9 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 10 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 11 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 12 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 13 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 14 // TimerCounter0 Compare Match A + IRQ_TIMER0_COMPB = 15 // TimerCounter0 Compare Match B + IRQ_TIMER0_OVF = 16 // Timer/Couner0 Overflow + IRQ_SPI_STC = 17 // SPI Serial Transfer Complete + IRQ_USART_RX = 18 // USART Rx Complete + IRQ_USART_UDRE = 19 // USART, Data Register Empty + IRQ_USART_TX = 20 // USART Tx Complete + IRQ_ADC = 21 // ADC Conversion Complete + IRQ_EE_READY = 22 // EEPROM Ready + IRQ_ANALOG_COMP = 23 // Analog Comparator + IRQ_TWI = 24 // Two-wire Serial Interface + IRQ_SPM_Ready = 25 // Store Program Memory Read + IRQ_max = 25 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + ADCSRB __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // The ADC Control and Status register A + ADCSRB: 0x7b, // The ADC Control and Status register B + DIDR0: 0x7e, // Digital Input Disable Register + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // I/O Port + PORT = struct { + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + }{ + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCICR __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + } + + // Serial Peripheral Interface + SPI = struct { + SPDR __reg + SPSR __reg + SPCR __reg + }{ + SPDR: 0x4e, // SPI Data Register + SPSR: 0x4d, // SPI Status Register + SPCR: 0x4c, // SPI Control Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Bytes + EEARH: 0x41, // EEPROM Address Register Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // CPU Registers + CPU = struct { + PRR __reg + OSCCAL __reg + CLKPR __reg + SREG __reg + SPL __reg + SPH __reg + SPMCSR __reg + MCUCR __reg + MCUSR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + PRR: 0x64, // Power Reduction Register + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + SPMCSR: 0x57, // Store Program Memory Control and Status Register + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose I/O Register 2 + GPIOR1: 0x4a, // General Purpose I/O Register 1 + GPIOR0: 0x3e, // General Purpose I/O Register 0 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BOOTSZ = 0x6 // Select boot size + EXTENDED_BOOTRST = 0x1 // Boot Reset vector Enabled + + // HIGH + HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PC6 as i/o pin)] + HIGH_DWEN = 0x40 // Debug Wire enable + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watch-dog Timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTB0 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0xc0 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TIMSK1: Timer/Counter Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output CompareB Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output CompareA Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 + TCCR1C_FOC1B = 0x40 +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2B = 0x4 // Output Compare Flag 2B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Output Mode bits + TCCR2A_COM2B = 0x30 // Compare Output Mode bits + TCCR2A_WGM2 = 0x3 // Waveform Genration Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy + ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0xf // Analog Channel Selection Bits + + // ADCSRA: The ADC Control and Status register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCSRB: The ADC Control and Status register B + ADCSRB_ACME = 0x40 + ADCSRB_ADTS = 0x7 // ADC Auto Trigger Source bits + + // DIDR0: Digital Input Disable Register + DIDR0_ADC5D = 0x20 + DIDR0_ADC4D = 0x10 + DIDR0_ADC3D = 0x8 + DIDR0_ADC2D = 0x4 + DIDR0_ADC1D = 0x2 + DIDR0_ADC0D = 0x1 +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register + EICRA_ISC1 = 0xc // External Interrupt Sense Control 1 Bits + EICRA_ISC0 = 0x3 // External Interrupt Sense Control 0 Bits + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0x3 // External Interrupt Request 1 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0x3 // External Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0x7 // Pin Change Interrupt Enables + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0x7f // Pin Change Enable Masks + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0x7 // Pin Change Interrupt Flags +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for CPU: CPU Registers +const ( + // PRR: Power Reduction Register + PRR_PRTWI = 0x80 // Power Reduction TWI + PRR_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // SPMCSR: Store Program Memory Control and Status Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read-While-Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read-While-Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory + + // MCUCR: MCU Control Register + MCUCR_PUD = 0x10 + MCUCR_IVSEL = 0x2 + MCUCR_IVCE = 0x1 + + // MCUSR: MCU Status Register + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BORF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select Bits + SMCR_SE = 0x1 // Sleep Enable +) diff --git a/src/device/avr/atmega88a.ld b/src/device/avr/atmega88a.ld new file mode 100644 index 00000000..5463aa05 --- /dev/null +++ b/src/device/avr/atmega88a.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega88A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_size = 0x400; +__num_isrs = 26; diff --git a/src/device/avr/atmega88p.go b/src/device/avr/atmega88p.go new file mode 100644 index 00000000..66a5c271 --- /dev/null +++ b/src/device/avr/atmega88p.go @@ -0,0 +1,642 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega88P.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega88p + +// Device information for the ATmega88P. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega88P" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_PCINT0 = 3 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 4 // Pin Change Interrupt Request 0 + IRQ_PCINT2 = 5 // Pin Change Interrupt Request 1 + IRQ_WDT = 6 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 7 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 8 // Timer/Counter2 Compare Match A + IRQ_TIMER2_OVF = 9 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 10 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 11 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 12 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 13 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 14 // TimerCounter0 Compare Match A + IRQ_TIMER0_COMPB = 15 // TimerCounter0 Compare Match B + IRQ_TIMER0_OVF = 16 // Timer/Couner0 Overflow + IRQ_SPI_STC = 17 // SPI Serial Transfer Complete + IRQ_USART_RX = 18 // USART Rx Complete + IRQ_USART_UDRE = 19 // USART, Data Register Empty + IRQ_USART_TX = 20 // USART Tx Complete + IRQ_ADC = 21 // ADC Conversion Complete + IRQ_EE_READY = 22 // EEPROM Ready + IRQ_ANALOG_COMP = 23 // Analog Comparator + IRQ_TWI = 24 // Two-wire Serial Interface + IRQ_SPM_Ready = 25 // Store Program Memory Read + IRQ_max = 25 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + ADCSRB __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // The ADC Control and Status register A + ADCSRB: 0x7b, // The ADC Control and Status register B + DIDR0: 0x7e, // Digital Input Disable Register + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // I/O Port + PORT = struct { + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + }{ + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCICR __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + } + + // Serial Peripheral Interface + SPI = struct { + SPDR __reg + SPSR __reg + SPCR __reg + }{ + SPDR: 0x4e, // SPI Data Register + SPSR: 0x4d, // SPI Status Register + SPCR: 0x4c, // SPI Control Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Bytes + EEARH: 0x41, // EEPROM Address Register Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // CPU Registers + CPU = struct { + PRR __reg + OSCCAL __reg + CLKPR __reg + SREG __reg + SPL __reg + SPH __reg + SPMCSR __reg + MCUCR __reg + MCUSR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + PRR: 0x64, // Power Reduction Register + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + SPMCSR: 0x57, // Store Program Memory Control and Status Register + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose I/O Register 2 + GPIOR1: 0x4a, // General Purpose I/O Register 1 + GPIOR0: 0x3e, // General Purpose I/O Register 0 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BOOTSZ = 0x6 // Select boot size + EXTENDED_BOOTRST = 0x1 // Boot Reset vector Enabled + + // HIGH + HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PC6 as i/o pin)] + HIGH_DWEN = 0x40 // Debug Wire enable + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watch-dog Timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTB0 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0xc0 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TIMSK1: Timer/Counter Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output CompareB Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output CompareA Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 + TCCR1C_FOC1B = 0x40 +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2B = 0x4 // Output Compare Flag 2B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Output Mode bits + TCCR2A_COM2B = 0x30 // Compare Output Mode bits + TCCR2A_WGM2 = 0x3 // Waveform Genration Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy + ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0xf // Analog Channel Selection Bits + + // ADCSRA: The ADC Control and Status register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCSRB: The ADC Control and Status register B + ADCSRB_ACME = 0x40 + ADCSRB_ADTS = 0x7 // ADC Auto Trigger Source bits + + // DIDR0: Digital Input Disable Register + DIDR0_ADC5D = 0x20 + DIDR0_ADC4D = 0x10 + DIDR0_ADC3D = 0x8 + DIDR0_ADC2D = 0x4 + DIDR0_ADC1D = 0x2 + DIDR0_ADC0D = 0x1 +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register + EICRA_ISC1 = 0xc // External Interrupt Sense Control 1 Bits + EICRA_ISC0 = 0x3 // External Interrupt Sense Control 0 Bits + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0x3 // External Interrupt Request 1 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0x3 // External Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0x7 // Pin Change Interrupt Enables + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0x7f // Pin Change Enable Masks + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0x7 // Pin Change Interrupt Flags +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for CPU: CPU Registers +const ( + // PRR: Power Reduction Register + PRR_PRTWI = 0x80 // Power Reduction TWI + PRR_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // SPMCSR: Store Program Memory Control and Status Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read-While-Write Section Busy + SPMCSR_RWWSRE = 0x10 // Read-While-Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SELFPRGEN = 0x1 // Self Programming Enable + + // MCUCR: MCU Control Register + MCUCR_BODS = 0x40 // BOD Sleep + MCUCR_BODSE = 0x20 // BOD Sleep Enable + MCUCR_PUD = 0x10 + MCUCR_IVSEL = 0x2 + MCUCR_IVCE = 0x1 + + // MCUSR: MCU Status Register + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BORF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select Bits + SMCR_SE = 0x1 // Sleep Enable +) diff --git a/src/device/avr/atmega88p.ld b/src/device/avr/atmega88p.ld new file mode 100644 index 00000000..1c94c761 --- /dev/null +++ b/src/device/avr/atmega88p.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega88P.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_size = 0x400; +__num_isrs = 26; diff --git a/src/device/avr/atmega88pa.go b/src/device/avr/atmega88pa.go new file mode 100644 index 00000000..5111bf72 --- /dev/null +++ b/src/device/avr/atmega88pa.go @@ -0,0 +1,643 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega88PA.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega88pa + +// Device information for the ATmega88PA. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega88PA" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_PCINT0 = 3 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 4 // Pin Change Interrupt Request 0 + IRQ_PCINT2 = 5 // Pin Change Interrupt Request 1 + IRQ_WDT = 6 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 7 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 8 // Timer/Counter2 Compare Match A + IRQ_TIMER2_OVF = 9 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 10 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 11 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 12 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 13 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 14 // TimerCounter0 Compare Match A + IRQ_TIMER0_COMPB = 15 // TimerCounter0 Compare Match B + IRQ_TIMER0_OVF = 16 // Timer/Couner0 Overflow + IRQ_SPI_STC = 17 // SPI Serial Transfer Complete + IRQ_USART_RX = 18 // USART Rx Complete + IRQ_USART_UDRE = 19 // USART, Data Register Empty + IRQ_USART_TX = 20 // USART Tx Complete + IRQ_ADC = 21 // ADC Conversion Complete + IRQ_EE_READY = 22 // EEPROM Ready + IRQ_ANALOG_COMP = 23 // Analog Comparator + IRQ_TWI = 24 // Two-wire Serial Interface + IRQ_SPM_Ready = 25 // Store Program Memory Read + IRQ_max = 25 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + ADCSRB __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // The ADC Control and Status register A + ADCSRB: 0x7b, // The ADC Control and Status register B + DIDR0: 0x7e, // Digital Input Disable Register + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + } + + // I/O Port + PORT = struct { + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + }{ + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCICR __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + } + + // Serial Peripheral Interface + SPI = struct { + SPDR __reg + SPSR __reg + SPCR __reg + }{ + SPDR: 0x4e, // SPI Data Register + SPSR: 0x4d, // SPI Status Register + SPCR: 0x4c, // SPI Control Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Bytes + EEARH: 0x41, // EEPROM Address Register Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // CPU Registers + CPU = struct { + PRR __reg + OSCCAL __reg + CLKPR __reg + SREG __reg + SPL __reg + SPH __reg + SPMCSR __reg + MCUCR __reg + MCUSR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + PRR: 0x64, // Power Reduction Register + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + SPMCSR: 0x57, // Store Program Memory Control and Status Register + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose I/O Register 2 + GPIOR1: 0x4a, // General Purpose I/O Register 1 + GPIOR0: 0x3e, // General Purpose I/O Register 0 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BOOTSZ = 0x6 // Select boot size + EXTENDED_BOOTRST = 0x1 // Boot Reset vector Enabled + + // HIGH + HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PC6 as i/o pin)] + HIGH_DWEN = 0x40 // Debug Wire enable + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watch-dog Timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTB0 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0xc0 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TIMSK1: Timer/Counter Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output CompareB Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output CompareA Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 + TCCR1C_FOC1B = 0x40 +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2B = 0x4 // Output Compare Flag 2B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Output Mode bits + TCCR2A_COM2B = 0x30 // Compare Output Mode bits + TCCR2A_WGM2 = 0x3 // Waveform Genration Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy + ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0xf // Analog Channel Selection Bits + + // ADCSRA: The ADC Control and Status register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCSRB: The ADC Control and Status register B + ADCSRB_ACME = 0x40 + ADCSRB_ADTS = 0x7 // ADC Auto Trigger Source bits + + // DIDR0: Digital Input Disable Register + DIDR0_ADC5D = 0x20 + DIDR0_ADC4D = 0x10 + DIDR0_ADC3D = 0x8 + DIDR0_ADC2D = 0x4 + DIDR0_ADC1D = 0x2 + DIDR0_ADC0D = 0x1 +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register + EICRA_ISC1 = 0xc // External Interrupt Sense Control 1 Bits + EICRA_ISC0 = 0x3 // External Interrupt Sense Control 0 Bits + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0x3 // External Interrupt Request 1 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0x3 // External Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0x7 // Pin Change Interrupt Enables + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0x7f // Pin Change Enable Masks + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0x7 // Pin Change Interrupt Flags +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for CPU: CPU Registers +const ( + // PRR: Power Reduction Register + PRR_PRTWI = 0x80 // Power Reduction TWI + PRR_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // SPMCSR: Store Program Memory Control and Status Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read-While-Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read-While-Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory + + // MCUCR: MCU Control Register + MCUCR_BODS = 0x40 // BOD Sleep + MCUCR_BODSE = 0x20 // BOD Sleep Enable + MCUCR_PUD = 0x10 + MCUCR_IVSEL = 0x2 + MCUCR_IVCE = 0x1 + + // MCUSR: MCU Status Register + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BORF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select Bits + SMCR_SE = 0x1 // Sleep Enable +) diff --git a/src/device/avr/atmega88pa.ld b/src/device/avr/atmega88pa.ld new file mode 100644 index 00000000..3fcdaa10 --- /dev/null +++ b/src/device/avr/atmega88pa.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega88PA.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_size = 0x400; +__num_isrs = 26; diff --git a/src/device/avr/atmega88pb.go b/src/device/avr/atmega88pb.go new file mode 100644 index 00000000..dab21438 --- /dev/null +++ b/src/device/avr/atmega88pb.go @@ -0,0 +1,685 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega88PB.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega88pb + +// Device information for the ATmega88PB. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega88PB" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_PCINT0 = 3 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 4 // Pin Change Interrupt Request 0 + IRQ_PCINT2 = 5 // Pin Change Interrupt Request 1 + IRQ_WDT = 6 // Watchdog Time-out Interrupt + IRQ_TIMER2_COMPA = 7 // Timer/Counter2 Compare Match A + IRQ_TIMER2_COMPB = 8 // Timer/Counter2 Compare Match A + IRQ_TIMER2_OVF = 9 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 10 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 11 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 12 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 13 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 14 // TimerCounter0 Compare Match A + IRQ_TIMER0_COMPB = 15 // TimerCounter0 Compare Match B + IRQ_TIMER0_OVF = 16 // Timer/Couner0 Overflow + IRQ_SPI_STC = 17 // SPI Serial Transfer Complete + IRQ_USART_RX = 18 // USART Rx Complete + IRQ_USART_UDRE = 19 // USART, Data Register Empty + IRQ_USART_TX = 20 // USART Tx Complete + IRQ_ADC = 21 // ADC Conversion Complete + IRQ_EE_READY = 22 // EEPROM Ready + IRQ_ANALOG_COMP = 23 // Analog Comparator + IRQ_TWI = 24 // Two-wire Serial Interface + IRQ_SPM_Ready = 25 // Store Program Memory Read + IRQ_USART_START = 26 // USART Start Edge Interrupt + IRQ_max = 26 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Device ID + DEVICEID = struct { + DEVID0 __reg + DEVID1 __reg + DEVID2 __reg + DEVID3 __reg + DEVID4 __reg + DEVID5 __reg + DEVID6 __reg + DEVID7 __reg + DEVID8 __reg + }{ + DEVID0: 0xf0, + DEVID1: 0xf1, + DEVID2: 0xf2, + DEVID3: 0xf3, + DEVID4: 0xf4, + DEVID5: 0xf5, + DEVID6: 0xf6, + DEVID7: 0xf7, + DEVID8: 0xf8, + } + + // USART + USART = struct { + UDR0 __reg + UCSR0A __reg + UCSR0B __reg + UCSR0C __reg + UCSR0D __reg + UBRR0L __reg + UBRR0H __reg + }{ + UDR0: 0xc6, // USART I/O Data Register + UCSR0A: 0xc0, // USART Control and Status Register A + UCSR0B: 0xc1, // USART Control and Status Register B + UCSR0C: 0xc2, // USART Control and Status Register C + UCSR0D: 0xc3, // USART Control and Status Register D + UBRR0L: 0xc4, // USART Baud Rate Register Bytes + UBRR0H: 0xc4, // USART Baud Rate Register Bytes + } + + // Two Wire Serial Interface + TWI = struct { + TWAMR __reg + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWAMR: 0xbd, // TWI (Slave) Address Mask Register + TWBR: 0xb8, // TWI Bit Rate register + TWCR: 0xbc, // TWI Control Register + TWSR: 0xb9, // TWI Status Register + TWDR: 0xbb, // TWI Data register + TWAR: 0xba, // TWI (Slave) Address register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TIMSK1 __reg + TIFR1 __reg + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TIMSK2 __reg + TIFR2 __reg + TCCR2A __reg + TCCR2B __reg + TCNT2 __reg + OCR2B __reg + OCR2A __reg + ASSR __reg + }{ + TIMSK2: 0x70, // Timer/Counter Interrupt Mask register + TIFR2: 0x37, // Timer/Counter Interrupt Flag Register + TCCR2A: 0xb0, // Timer/Counter2 Control Register A + TCCR2B: 0xb1, // Timer/Counter2 Control Register B + TCNT2: 0xb2, // Timer/Counter2 + OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B + OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A + ASSR: 0xb6, // Asynchronous Status Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCL __reg + ADCH __reg + ADCSRA __reg + ADCSRB __reg + DIDR0 __reg + }{ + ADMUX: 0x7c, // The ADC multiplexer Selection Register + ADCL: 0x78, // ADC Data Register Bytes + ADCH: 0x78, // ADC Data Register Bytes + ADCSRA: 0x7a, // The ADC Control and Status register A + ADCSRB: 0x7b, // The ADC Control and Status register B + DIDR0: 0x7e, // Digital Input Disable Register + } + + // Analog Comparator + AC = struct { + ACSR __reg + DIDR1 __reg + ACSRB __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + DIDR1: 0x7f, // Digital Input Disable Register 1 + ACSRB: 0x4f, // Analog Comparator Status Register B + } + + // I/O Port + PORT = struct { + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTE __reg + DDRE __reg + PINE __reg + }{ + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTE: 0x2e, // Port E Data Register + DDRE: 0x2d, // Port E Data Direction Register + PINE: 0x2c, // Port E Input Pins + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + PCICR __reg + PCMSK2 __reg + PCMSK1 __reg + PCMSK0 __reg + PCIFR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + PCMSK2: 0x6d, // Pin Change Mask Register 2 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + } + + // Serial Peripheral Interface + SPI = struct { + SPDR __reg + SPSR __reg + SPCR __reg + }{ + SPDR: 0x4e, // SPI Data Register + SPSR: 0x4d, // SPI Status Register + SPCR: 0x4c, // SPI Control Register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Bytes + EEARH: 0x41, // EEPROM Address Register Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // CPU Registers + CPU = struct { + PRR __reg + OSCCAL __reg + CLKPR __reg + SREG __reg + SPL __reg + SPH __reg + SPMCSR __reg + MCUCR __reg + MCUSR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + }{ + PRR: 0x64, // Power Reduction Register + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, // Clock Prescale Register + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + SPMCSR: 0x57, // Store Program Memory Control and Status Register + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose I/O Register 2 + GPIOR1: 0x4a, // General Purpose I/O Register 1 + GPIOR0: 0x3e, // General Purpose I/O Register 0 + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BOOTSZ = 0x6 // Select boot size + EXTENDED_BOOTRST = 0x1 // Boot Reset vector Enabled + + // HIGH + HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PC6 as i/o pin) + HIGH_DWEN = 0x40 // Debug Wire enable + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watch-dog Timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BODLEVEL = 0x7 // Brown-out Detector trigger level + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTB0 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for USART: USART +const ( + // UCSR0A: USART Control and Status Register A + UCSR0A_RXC0 = 0x80 // USART Receive Complete + UCSR0A_TXC0 = 0x40 // USART Transmitt Complete + UCSR0A_UDRE0 = 0x20 // USART Data Register Empty + UCSR0A_FE0 = 0x10 // Framing Error + UCSR0A_DOR0 = 0x8 // Data overRun + UCSR0A_UPE0 = 0x4 // Parity Error + UCSR0A_U2X0 = 0x2 // Double the USART transmission speed + UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode + + // UCSR0B: USART Control and Status Register B + UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable + UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable + UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable + UCSR0B_RXEN0 = 0x10 // Receiver Enable + UCSR0B_TXEN0 = 0x8 // Transmitter Enable + UCSR0B_UCSZ02 = 0x4 // Character Size + UCSR0B_RXB80 = 0x2 // Receive Data Bit 8 + UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8 + + // UCSR0C: USART Control and Status Register C + UCSR0C_UMSEL0 = 0xc0 // USART Mode Select + UCSR0C_UPM0 = 0x30 // Parity Mode Bits + UCSR0C_USBS0 = 0x8 // Stop Bit Select + UCSR0C_UCSZ0 = 0x6 // Character Size + UCSR0C_UCPOL0 = 0x1 // Clock Polarity + + // UCSR0D: USART Control and Status Register D + UCSR0D_RXSIE = 0x80 // RX Start Interrupt Enable + UCSR0D_RXS = 0x40 // RX Start + UCSR0D_SFDE = 0x20 // Start Frame Detection Enable +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWAMR: TWI (Slave) Address Mask Register + TWAMR_TWAM = 0xfe + + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TIMSK1: Timer/Counter Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output CompareB Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output CompareA Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter1 Control Register C + TCCR1C_FOC1A = 0x80 + TCCR1C_FOC1B = 0x40 +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TIMSK2: Timer/Counter Interrupt Mask register + TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable + TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable + TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable + + // TIFR2: Timer/Counter Interrupt Flag Register + TIFR2_OCF2B = 0x4 // Output Compare Flag 2B + TIFR2_OCF2A = 0x2 // Output Compare Flag 2A + TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag + + // TCCR2A: Timer/Counter2 Control Register A + TCCR2A_COM2A = 0xc0 // Compare Output Mode bits + TCCR2A_COM2B = 0x30 // Compare Output Mode bits + TCCR2A_WGM2 = 0x3 // Waveform Genration Mode + + // TCCR2B: Timer/Counter2 Control Register B + TCCR2B_FOC2A = 0x80 // Force Output Compare A + TCCR2B_FOC2B = 0x40 // Force Output Compare B + TCCR2B_WGM22 = 0x8 // Waveform Generation Mode + TCCR2B_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_EXCLK = 0x40 // Enable External Clock Input + ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2 + ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy + ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy + ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy + ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy + ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0xf // Analog Channel Selection Bits + + // ADCSRA: The ADC Control and Status register A + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits + + // ADCSRB: The ADC Control and Status register B + ADCSRB_ACME = 0x40 + ADCSRB_ADTS = 0x7 // ADC Auto Trigger Source bits + + // DIDR0: Digital Input Disable Register + DIDR0_ADC5D = 0x20 + DIDR0_ADC4D = 0x10 + DIDR0_ADC3D = 0x8 + DIDR0_ADC2D = 0x4 + DIDR0_ADC1D = 0x2 + DIDR0_ADC0D = 0x1 +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // DIDR1: Digital Input Disable Register 1 + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable + + // ACSRB: Analog Comparator Status Register B + ACSRB_ACOE = 0x1 // Analog Comparator Output Enable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register + EICRA_ISC1 = 0xc // External Interrupt Sense Control 1 Bits + EICRA_ISC0 = 0x3 // External Interrupt Sense Control 0 Bits + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0x3 // External Interrupt Request 1 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0x3 // External Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0x7 // Pin Change Interrupt Enables + + // PCMSK2: Pin Change Mask Register 2 + PCMSK2_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0x7f // Pin Change Enable Masks + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0x7 // Pin Change Interrupt Flags +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for CPU: CPU Registers +const ( + // PRR: Power Reduction Register + PRR_PRTWI = 0x80 // Power Reduction TWI + PRR_PRTIM2 = 0x40 // Power Reduction Timer/Counter2 + PRR_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + PRR_PRUSART0 = 0x2 // Power Reduction USART + PRR_PRADC = 0x1 // Power Reduction ADC + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits + + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // SPMCSR: Store Program Memory Control and Status Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read-While-Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read-While-Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory + + // MCUCR: MCU Control Register + MCUCR_BODS = 0x40 // BOD Sleep + MCUCR_BODSE = 0x20 // BOD Sleep Enable + MCUCR_PUD = 0x10 + MCUCR_IVSEL = 0x2 + MCUCR_IVCE = 0x1 + + // MCUSR: MCU Status Register + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BORF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select Bits + SMCR_SE = 0x1 // Sleep Enable +) diff --git a/src/device/avr/atmega88pb.ld b/src/device/avr/atmega88pb.ld new file mode 100644 index 00000000..cd08ed3b --- /dev/null +++ b/src/device/avr/atmega88pb.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega88PB.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_size = 0x400; +__num_isrs = 27; diff --git a/src/device/avr/atmega8a.go b/src/device/avr/atmega8a.go new file mode 100644 index 00000000..33c4ec2f --- /dev/null +++ b/src/device/avr/atmega8a.go @@ -0,0 +1,463 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega8A.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega8a + +// Device information for the ATmega8A. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega8A" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_TIMER2_COMP = 3 // Timer/Counter2 Compare Match + IRQ_TIMER2_OVF = 4 // Timer/Counter2 Overflow + IRQ_TIMER1_CAPT = 5 // Timer/Counter1 Capture Event + IRQ_TIMER1_COMPA = 6 // Timer/Counter1 Compare Match A + IRQ_TIMER1_COMPB = 7 // Timer/Counter1 Compare Match B + IRQ_TIMER1_OVF = 8 // Timer/Counter1 Overflow + IRQ_TIMER0_OVF = 9 // Timer/Counter0 Overflow + IRQ_SPI_STC = 10 // Serial Transfer Complete + IRQ_USART_RXC = 11 // USART, Rx Complete + IRQ_USART_UDRE = 12 // USART Data Register Empty + IRQ_USART_TXC = 13 // USART, Tx Complete + IRQ_ADC = 14 // ADC Conversion Complete + IRQ_EE_RDY = 15 // EEPROM Ready + IRQ_ANA_COMP = 16 // Analog Comparator + IRQ_TWI = 17 // 2-wire Serial Interface + IRQ_SPM_RDY = 18 // Store Program Memory Ready + IRQ_max = 18 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + HIGH __reg + LOW __reg + }{ + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog Comparator + AC = struct { + ACSR __reg + }{ + ACSR: 0x28, // Analog Comparator Control And Status Register + } + + // Serial Peripheral Interface + SPI = struct { + SPDR __reg + SPSR __reg + SPCR __reg + }{ + SPDR: 0x2f, // SPI Data Register + SPSR: 0x2e, // SPI Status Register + SPCR: 0x2d, // SPI Control Register + } + + // External Interrupts + EXINT = struct { + GICR __reg + GIFR __reg + }{ + GICR: 0x5b, // General Interrupt Control Register + GIFR: 0x5a, // General Interrupt Flag Register + } + + // Timer/Counter, 8-bit + TC8 = struct { + TCCR0 __reg + TCNT0 __reg + }{ + TCCR0: 0x53, // Timer/Counter0 Control Register + TCNT0: 0x52, // Timer Counter 0 + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + ICR1L __reg + ICR1H __reg + }{ + TCCR1A: 0x4f, // Timer/Counter1 Control Register A + TCCR1B: 0x4e, // Timer/Counter1 Control Register B + TCNT1L: 0x4c, // Timer/Counter1 Bytes + TCNT1H: 0x4c, // Timer/Counter1 Bytes + OCR1AL: 0x4a, // Timer/Counter1 Output Compare Register Bytes + OCR1AH: 0x4a, // Timer/Counter1 Output Compare Register Bytes + OCR1BL: 0x48, // Timer/Counter1 Output Compare Register Bytes + OCR1BH: 0x48, // Timer/Counter1 Output Compare Register Bytes + ICR1L: 0x46, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x46, // Timer/Counter1 Input Capture Register Bytes + } + + // Timer/Counter, 8-bit Async + TC8_ASYNC = struct { + TCCR2 __reg + TCNT2 __reg + OCR2 __reg + ASSR __reg + }{ + TCCR2: 0x45, // Timer/Counter2 Control Register + TCNT2: 0x44, // Timer/Counter2 + OCR2: 0x43, // Timer/Counter2 Output Compare Register + ASSR: 0x42, // Asynchronous Status Register + } + + // USART + USART = struct { + UDR __reg + UCSRA __reg + UCSRB __reg + UCSRC __reg + UBRRH __reg + UBRRL __reg + }{ + UDR: 0x2c, // USART I/O Data Register + UCSRA: 0x2b, // USART Control and Status Register A + UCSRB: 0x2a, // USART Control and Status Register B + UCSRC: 0x40, // USART Control and Status Register C + UBRRH: 0x40, // USART Baud Rate Register Hight Byte + UBRRL: 0x29, // USART Baud Rate Register Low Byte + } + + // Two Wire Serial Interface + TWI = struct { + TWBR __reg + TWCR __reg + TWSR __reg + TWDR __reg + TWAR __reg + }{ + TWBR: 0x20, // TWI Bit Rate register + TWCR: 0x56, // TWI Control Register + TWSR: 0x21, // TWI Status Register + TWDR: 0x23, // TWI Data register + TWAR: 0x22, // TWI (Slave) Address register + } + + // Watchdog Timer + WDT = struct { + WDTCR __reg + }{ + WDTCR: 0x41, // Watchdog Timer Control Register + } + + // I/O Port + PORT = struct { + PORTB __reg + DDRB __reg + PINB __reg + PORTC __reg + DDRC __reg + PINC __reg + PORTD __reg + DDRD __reg + PIND __reg + }{ + PORTB: 0x38, // Port B Data Register + DDRB: 0x37, // Port B Data Direction Register + PINB: 0x36, // Port B Input Pins + PORTC: 0x35, // Port C Data Register + DDRC: 0x34, // Port C Data Direction Register + PINC: 0x33, // Port C Input Pins + PORTD: 0x32, // Port D Data Register + DDRD: 0x31, // Port D Data Direction Register + PIND: 0x30, // Port D Input Pins + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x3e, // EEPROM Address Register Bytes + EEARH: 0x3e, // EEPROM Address Register Bytes + EEDR: 0x3d, // EEPROM Data Register + EECR: 0x3c, // EEPROM Control Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + MCUCSR __reg + OSCCAL __reg + SPMCR __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + MCUCSR: 0x54, // MCU Control And Status Register + OSCCAL: 0x51, // Oscillator Calibration Value + SPMCR: 0x57, // Store Program Memory Control Register + } + + // Analog-to-Digital Converter + ADC = struct { + ADMUX __reg + ADCSRA __reg + ADCL __reg + ADCH __reg + }{ + ADMUX: 0x27, // The ADC multiplexer Selection Register + ADCSRA: 0x26, // The ADC Control and Status register + ADCL: 0x24, // ADC Data Register Bytes + ADCH: 0x24, // ADC Data Register Bytes + } +) + +// Bitfields for FUSE: Fuses +const ( + // HIGH + HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PC6 as i/o pin) + HIGH_WDTON = 0x40 // Watch-dog Timer always on + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + HIGH_CKOPT = 0x10 // CKOPT fuse (operation dependent of CKSEL fuses) + + // LOW + LOW_BODLEVEL = 0x80 // Brownout detector trigger level + LOW_BODEN = 0x40 // Brown-out detection enabled + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit + + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects +) + +// Bitfields for EXINT: External Interrupts +const ( + // GICR: General Interrupt Control Register + GICR_INT = 0xc0 // External Interrupt Request 1 Enable + GICR_IVSEL = 0x2 // Interrupt Vector Select + GICR_IVCE = 0x1 // Interrupt Vector Change Enable + + // GIFR: General Interrupt Flag Register + GIFR_INTF = 0xc0 // External Interrupt Flags +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0: Timer/Counter0 Control Register + TCCR0_CS02 = 0x4 // Clock Select0 bit 2 + TCCR0_CS01 = 0x2 // Clock Select0 bit 1 + TCCR0_CS00 = 0x1 // Clock Select0 bit 0 +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_FOC1A = 0x8 // Force Output Compare 1A + TCCR1A_FOC1B = 0x4 // Force Output Compare 1B + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 +) + +// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async +const ( + // TCCR2: Timer/Counter2 Control Register + TCCR2_FOC2 = 0x80 // Force Output Compare + TCCR2_WGM20 = 0x40 // Waveform Genration Mode + TCCR2_COM2 = 0x30 // Compare Output Mode bits + TCCR2_WGM21 = 0x8 // Waveform Generation Mode + TCCR2_CS2 = 0x7 // Clock Select bits + + // ASSR: Asynchronous Status Register + ASSR_AS2 = 0x8 // Asynchronous Timer/counter2 + ASSR_TCN2UB = 0x4 // Timer/Counter2 Update Busy + ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy + ASSR_TCR2UB = 0x1 // Timer/counter Control Register2 Update Busy +) + +// Bitfields for USART: USART +const ( + // UCSRA: USART Control and Status Register A + UCSRA_RXC = 0x80 // USART Receive Complete + UCSRA_TXC = 0x40 // USART Transmitt Complete + UCSRA_UDRE = 0x20 // USART Data Register Empty + UCSRA_FE = 0x10 // Framing Error + UCSRA_DOR = 0x8 // Data overRun + UCSRA_UPE = 0x4 // Parity Error + UCSRA_U2X = 0x2 // Double the USART transmission speed + UCSRA_MPCM = 0x1 // Multi-processor Communication Mode + + // UCSRB: USART Control and Status Register B + UCSRB_RXCIE = 0x80 // RX Complete Interrupt Enable + UCSRB_TXCIE = 0x40 // TX Complete Interrupt Enable + UCSRB_UDRIE = 0x20 // USART Data register Empty Interrupt Enable + UCSRB_RXEN = 0x10 // Receiver Enable + UCSRB_TXEN = 0x8 // Transmitter Enable + UCSRB_UCSZ2 = 0x4 // Character Size + UCSRB_RXB8 = 0x2 // Receive Data Bit 8 + UCSRB_TXB8 = 0x1 // Transmit Data Bit 8 + + // UCSRC: USART Control and Status Register C + UCSRC_URSEL = 0x80 // Register Select + UCSRC_UMSEL = 0x40 // USART Mode Select + UCSRC_UPM = 0x30 // Parity Mode Bits + UCSRC_USBS = 0x8 // Stop Bit Select + UCSRC_UCSZ = 0x6 // Character Size + UCSRC_UCPOL = 0x1 // Clock Polarity +) + +// Bitfields for TWI: Two Wire Serial Interface +const ( + // TWCR: TWI Control Register + TWCR_TWINT = 0x80 // TWI Interrupt Flag + TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit + TWCR_TWSTA = 0x20 // TWI Start Condition Bit + TWCR_TWSTO = 0x10 // TWI Stop Condition Bit + TWCR_TWWC = 0x8 // TWI Write Collition Flag + TWCR_TWEN = 0x4 // TWI Enable Bit + TWCR_TWIE = 0x1 // TWI Interrupt Enable + + // TWSR: TWI Status Register + TWSR_TWS = 0xf8 // TWI Status + TWSR_TWPS = 0x3 // TWI Prescaler + + // TWAR: TWI (Slave) Address register + TWAR_TWA = 0xfe // TWI (Slave) Address register Bits + TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCR: Watchdog Timer Control Register + WDTCR_WDCE = 0x10 // Watchdog Change Enable + WDTCR_WDE = 0x8 // Watch Dog Enable + WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMWE = 0x4 // EEPROM Master Write Enable + EECR_EEWE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // MCUCSR: MCU Control And Status Register + MCUCSR_WDRF = 0x8 // Watchdog Reset Flag + MCUCSR_BORF = 0x4 // Brown-out Reset Flag + MCUCSR_EXTRF = 0x2 // External Reset Flag + MCUCSR_PORF = 0x1 // Power-on reset flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // SPMCR: Store Program Memory Control Register + SPMCR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCR_RWWSB = 0x40 // Read-While-Write Section Busy + SPMCR_RWWSRE = 0x10 // Read-While-Write Section Read Enable + SPMCR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCR_PGWRT = 0x4 // Page Write + SPMCR_PGERS = 0x2 // Page Erase + SPMCR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // ADMUX: The ADC multiplexer Selection Register + ADMUX_REFS = 0xc0 // Reference Selection Bits + ADMUX_ADLAR = 0x20 // Left Adjust Result + ADMUX_MUX = 0xf // Analog Channel and Gain Selection Bits + + // ADCSRA: The ADC Control and Status register + ADCSRA_ADEN = 0x80 // ADC Enable + ADCSRA_ADSC = 0x40 // ADC Start Conversion + ADCSRA_ADFR = 0x20 // ADC Free Running Select + ADCSRA_ADIF = 0x10 // ADC Interrupt Flag + ADCSRA_ADIE = 0x8 // ADC Interrupt Enable + ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits +) diff --git a/src/device/avr/atmega8a.ld b/src/device/avr/atmega8a.ld new file mode 100644 index 00000000..def85438 --- /dev/null +++ b/src/device/avr/atmega8a.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega8A.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_size = 0x400; +__num_isrs = 19; diff --git a/src/device/avr/atmega8hva.go b/src/device/avr/atmega8hva.go new file mode 100644 index 00000000..b8cf8899 --- /dev/null +++ b/src/device/avr/atmega8hva.go @@ -0,0 +1,560 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega8HVA.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega8hva + +// Device information for the ATmega8HVA. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega8HVA" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset + IRQ_BPINT = 1 // Battery Protection Interrupt + IRQ_VREGMON = 2 // Voltage regulator monitor interrupt + IRQ_INT0 = 3 // External Interrupt Request 0 + IRQ_INT1 = 4 // External Interrupt Request 1 + IRQ_INT2 = 5 // External Interrupt Request 2 + IRQ_WDT = 6 // Watchdog Timeout Interrupt + IRQ_TIMER1_IC = 7 // Timer 1 Input capture + IRQ_TIMER1_COMPA = 8 // Timer 1 Compare Match A + IRQ_TIMER1_COMPB = 9 // Timer 1 Compare Match B + IRQ_TIMER1_OVF = 10 // Timer 1 overflow + IRQ_TIMER0_IC = 11 // Timer 0 Input Capture + IRQ_TIMER0_COMPA = 12 // Timer 0 Comapre Match A + IRQ_TIMER0_COMPB = 13 // Timer 0 Compare Match B + IRQ_TIMER0_OVF = 14 // Timer 0 Overflow + IRQ_SPI_STC = 15 // SPI Serial transfer complete + IRQ_VADC = 16 // Voltage ADC Conversion Complete + IRQ_CCADC_CONV = 17 // Coulomb Counter ADC Conversion Complete + IRQ_CCADC_REG_CUR = 18 // Coloumb Counter ADC Regular Current + IRQ_CCADC_ACC = 19 // Coloumb Counter ADC Accumulator + IRQ_EE_READY = 20 // EEPROM Ready + IRQ_max = 20 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + LOW __reg + }{ + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // Analog-to-Digital Converter + ADC = struct { + VADMUX __reg + VADCL __reg + VADCH __reg + VADCSR __reg + }{ + VADMUX: 0x7c, // The VADC multiplexer Selection Register + VADCL: 0x78, // VADC Data Register Bytes + VADCH: 0x78, // VADC Data Register Bytes + VADCSR: 0x7a, // The VADC Control and Status register + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + } + + // Bandgap + BANDGAP = struct { + BGCRR __reg + BGCCR __reg + }{ + BGCRR: 0xd1, // Bandgap Calibration of Resistor Ladder + BGCCR: 0xd0, // Bandgap Calibration Register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EIMSK __reg + EIFR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + } + + // I/O Port + PORT = struct { + PORTC __reg + PINC __reg + PORTA __reg + DDRA __reg + PINA __reg + PORTB __reg + DDRB __reg + PINB __reg + }{ + PORTC: 0x28, // Port C Data Register + PINC: 0x26, // Port C Input Pins + PORTA: 0x22, // Port A Data Register + DDRA: 0x21, // Port A Data Direction Register + PINA: 0x20, // Port A Input Pins + PORTB: 0x25, // Data Register, Port B + DDRB: 0x24, // Data Direction Register, Port B + PINB: 0x23, // Input Pins, Port B + } + + // FET Control + FET = struct { + FCSR __reg + }{ + FCSR: 0xf0, // FET Control and Status Register + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control and Status Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + MCUCR __reg + MCUSR __reg + FOSCCAL __reg + OSICSR __reg + SMCR __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + DIDR0 __reg + PRR0 __reg + CLKPR __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + FOSCCAL: 0x66, // Fast Oscillator Calibration Value + OSICSR: 0x37, // Oscillator Sampling Interface Control and Status Register + SMCR: 0x53, // Sleep Mode Control Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + DIDR0: 0x7e, // Digital Input Disable Register + PRR0: 0x64, // Power Reduction Register 0 + CLKPR: 0x61, // Clock Prescale Register + } + + // Battery Protection + BATTERY_PROTECTION = struct { + BPPLR __reg + BPCR __reg + BPHCTR __reg + BPOCTR __reg + BPSCTR __reg + BPCHCD __reg + BPDHCD __reg + BPCOCD __reg + BPDOCD __reg + BPSCD __reg + BPIFR __reg + BPIMSK __reg + }{ + BPPLR: 0xfe, // Battery Protection Parameter Lock Register + BPCR: 0xfd, // Battery Protection Control Register + BPHCTR: 0xfc, // Battery Protection Short-current Timing Register + BPOCTR: 0xfb, // Battery Protection Over-current Timing Register + BPSCTR: 0xfa, // Battery Protection Short-current Timing Register + BPCHCD: 0xf9, // Battery Protection Charge-High-current Detection Level Register + BPDHCD: 0xf8, // Battery Protection Discharge-High-current Detection Level Register + BPCOCD: 0xf7, // Battery Protection Charge-Over-current Detection Level Register + BPDOCD: 0xf6, // Battery Protection Discharge-Over-current Detection Level Register + BPSCD: 0xf5, // Battery Protection Short-Circuit Detection Level Register + BPIFR: 0xf3, // Battery Protection Interrupt Flag Register + BPIMSK: 0xf2, // Battery Protection Interrupt Mask Register + } + + // EEPROM + EEPROM = struct { + EEAR __reg + EEDR __reg + EECR __reg + }{ + EEAR: 0x41, // EEPROM Read/Write Access + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1B __reg + TCCR1A __reg + TCNT1L __reg + TCNT1H __reg + OCR1A __reg + OCR1B __reg + TIMSK1 __reg + TIFR1 __reg + GTCCR __reg + TCCR0A __reg + TCCR0B __reg + TCNT0L __reg + TCNT0H __reg + OCR0A __reg + OCR0B __reg + TIMSK0 __reg + TIFR0 __reg + }{ + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1A: 0x80, // Timer/Counter 1 Control Register A + TCNT1L: 0x84, // Timer Counter 1 Bytes + TCNT1H: 0x84, // Timer Counter 1 Bytes + OCR1A: 0x88, // Output Compare Register 1A + OCR1B: 0x89, // Output Compare Register B + TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter Interrupt Flag register + GTCCR: 0x43, // General Timer/Counter Control Register + TCCR0A: 0x44, // Timer/Counter0 Control Register + TCCR0B: 0x45, // Timer/Counter0 Control Register + TCNT0L: 0x46, // Timer Counter 0 Bytes + TCNT0H: 0x46, // Timer Counter 0 Bytes + OCR0A: 0x48, // Output compare Register A + OCR0B: 0x49, // Output compare Register B + TIMSK0: 0x6e, // Timer/Counter Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter Interrupt Flag register + } + + // Coulomb Counter + COULOMB_COUNTER = struct { + CADCSRA __reg + CADCSRB __reg + CADICL __reg + CADICH __reg + CADAC3 __reg + CADAC2 __reg + CADAC1 __reg + CADAC0 __reg + CADRC __reg + }{ + CADCSRA: 0xe4, // CC-ADC Control and Status Register A + CADCSRB: 0xe5, // CC-ADC Control and Status Register B + CADICL: 0xe8, // CC-ADC Instantaneous Current + CADICH: 0xe8, // CC-ADC Instantaneous Current + CADAC3: 0xe3, // ADC Accumulate Current + CADAC2: 0xe2, // ADC Accumulate Current + CADAC1: 0xe1, // ADC Accumulate Current + CADAC0: 0xe0, // ADC Accumulate Current + CADRC: 0xe6, // CC-ADC Regular Current + } + + // Voltage Regulator + VOLTAGE_REGULATOR = struct { + ROCR __reg + }{ + ROCR: 0xc8, // Regulator Operating Condition Register + } +) + +// Bitfields for FUSE: Fuses +const ( + // LOW + LOW_WDTON = 0x80 // Watch-dog Timer always on + LOW_EESAVE = 0x40 // Preserve EEPROM through the Chip Erase cycle + LOW_SPIEN = 0x20 // Serial program downloading (SPI) enabled + LOW_DWEN = 0x10 // Debug Wire enable + LOW_SELFPRGEN = 0x8 // Self Programming enable + LOW_SUT = 0x7 // Select start-up time +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock +) + +// Bitfields for ADC: Analog-to-Digital Converter +const ( + // VADMUX: The VADC multiplexer Selection Register + VADMUX_VADMUX = 0xf // Analog Channel and Gain Selection Bits + + // VADCSR: The VADC Control and Status register + VADCSR_VADEN = 0x8 // VADC Enable + VADCSR_VADSC = 0x4 // VADC Satrt Conversion + VADCSR_VADCCIF = 0x2 // VADC Conversion Complete Interrupt Flag + VADCSR_VADCCIE = 0x1 // VADC Conversion Complete Interrupt Enable +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable +) + +// Bitfields for BANDGAP: Bandgap +const ( + // BGCRR: Bandgap Calibration of Resistor Ladder + BGCRR_BGCR = 0xff // Bandgap calibration bits + + // BGCCR: Bandgap Calibration Register + BGCCR_BGD = 0x80 // Setting the BGD bit to one will disable the bandgap voltage reference. This bit must be cleared before enabling CC-ADC or V-ADC, and must remain unset while either ADC is enabled. + BGCCR_BGCC = 0x3f // BG Calibration of PTAT Current Bits +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register + EICRA_ISC2 = 0x30 // External Interrupt Sense Control 2 Bits + EICRA_ISC1 = 0xc // External Interrupt Sense Control 1 Bits + EICRA_ISC0 = 0x3 // External Interrupt Sense Control 0 Bits + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0x7 // External Interrupt Request 2 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0x7 // External Interrupt Flags +) + +// Bitfields for FET: FET Control +const ( + // FCSR: FET Control and Status Register + FCSR_DUVRD = 0x8 // Deep Under-Voltage Recovery Disable + FCSR_CPS = 0x4 // Current Protection Status + FCSR_DFE = 0x2 // Discharge FET Enable + FCSR_CFE = 0x1 // Charge FET Enable +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control and Status Register + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_CTPB = 0x10 // Clear Temporary Page Buffer + SPMCSR_RFLB = 0x8 // Read Fuse and Lock Bits + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // MCUCR: MCU Control Register + MCUCR_CKOE = 0x20 // Clock Output Enable + MCUCR_PUD = 0x10 // Pull-up disable + + // MCUSR: MCU Status Register + MCUSR_OCDRF = 0x10 // OCD Reset Flag + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BODRF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // OSICSR: Oscillator Sampling Interface Control and Status Register + OSICSR_OSISEL0 = 0x10 // Oscillator Sampling Interface Select 0 + OSICSR_OSIST = 0x2 // Oscillator Sampling Interface Status + OSICSR_OSIEN = 0x1 // Oscillator Sampling Interface Enable + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // DIDR0: Digital Input Disable Register + DIDR0_PA1DID = 0x2 // When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled. + DIDR0_PA0DID = 0x1 // When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled. + + // PRR0: Power Reduction Register 0 + PRR0_PRVRM = 0x20 // Power Reduction Voltage Regulator Monitor + PRR0_PRSPI = 0x8 // Power reduction SPI + PRR0_PRTIM1 = 0x4 // Power Reduction Timer/Counter1 + PRR0_PRTIM0 = 0x2 // Power Reduction Timer/Counter0 + PRR0_PRVADC = 0x1 // Power Reduction V-ADC + + // CLKPR: Clock Prescale Register + CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable + CLKPR_CLKPS = 0x3 // Clock Prescaler Select Bits +) + +// Bitfields for BATTERY_PROTECTION: Battery Protection +const ( + // BPPLR: Battery Protection Parameter Lock Register + BPPLR_BPPLE = 0x2 // Battery Protection Parameter Lock Enable + BPPLR_BPPL = 0x1 // Battery Protection Parameter Lock + + // BPCR: Battery Protection Control Register + BPCR_SCD = 0x10 // Short Circuit Protection Disabled + BPCR_DOCD = 0x8 // Discharge Over-current Protection Disabled + BPCR_COCD = 0x4 // Charge Over-current Protection Disabled + BPCR_DHCD = 0x2 // Discharge High-current Protection Disable + BPCR_CHCD = 0x1 // Charge High-current Protection Disable + + // BPIFR: Battery Protection Interrupt Flag Register + BPIFR_SCIF = 0x10 // Short-circuit Protection Activated Interrupt Flag + BPIFR_DOCIF = 0x8 // Discharge Over-current Protection Activated Interrupt Flag + BPIFR_COCIF = 0x4 // Charge Over-current Protection Activated Interrupt Flag + BPIFR_DHCIF = 0x2 // Disharge High-current Protection Activated Interrupt + BPIFR_CHCIF = 0x1 // Charge High-current Protection Activated Interrupt + + // BPIMSK: Battery Protection Interrupt Mask Register + BPIMSK_SCIE = 0x10 // Short-circuit Protection Activated Interrupt Enable + BPIMSK_DOCIE = 0x8 // Discharge Over-current Protection Activated Interrupt Enable + BPIMSK_COCIE = 0x4 // Charge Over-current Protection Activated Interrupt Enable + BPIMSK_DHCIE = 0x2 // Discharger High-current Protection Activated Interrupt + BPIMSK_CHCIE = 0x1 // Charger High-current Protection Activated Interrupt +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 + EECR_EERIE = 0x8 // EEProm Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_CS = 0x7 // Clock Select1 bis + + // TCCR1A: Timer/Counter 1 Control Register A + TCCR1A_TCW1 = 0x80 // Timer/Counter Width + TCCR1A_ICEN1 = 0x40 // Input Capture Mode Enable + TCCR1A_ICNC1 = 0x20 // Input Capture Noise Canceler + TCCR1A_ICES1 = 0x10 // Input Capture Edge Select + TCCR1A_ICS1 = 0x8 // Input Capture Select + TCCR1A_WGM10 = 0x1 // Waveform Generation Mode + + // TIMSK1: Timer/Counter Interrupt Mask Register + TIMSK1_ICIE1 = 0x8 // Timer/Counter n Input Capture Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter Interrupt Flag register + TIFR1_ICF1 = 0x8 // Timer/Counter 1 Input Capture Flag + TIFR1_OCF1B = 0x4 // Timer/Counter1 Output Compare Flag B + TIFR1_OCF1A = 0x2 // Timer/Counter1 Output Compare Flag A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag + + // GTCCR: General Timer/Counter Control Register + GTCCR_TSM = 0x80 // Timer/Counter Synchronization Mode + GTCCR_PSRSYNC = 0x1 // Prescaler Reset + + // TCCR0A: Timer/Counter0 Control Register + TCCR0A_TCW0 = 0x80 // Timer/Counter Width + TCCR0A_ICEN0 = 0x40 // Input Capture Mode Enable + TCCR0A_ICNC0 = 0x20 // Input Capture Noise Canceler + TCCR0A_ICES0 = 0x10 // Input Capture Edge Select + TCCR0A_ICS0 = 0x8 // Input Capture Select + TCCR0A_WGM00 = 0x1 // Clock Select0 bit 0 + + // TCCR0B: Timer/Counter0 Control Register + TCCR0B_CS02 = 0x4 // Clock Select0 bit 2 + TCCR0B_CS01 = 0x2 // Clock Select0 bit 1 + TCCR0B_CS00 = 0x1 // Clock Select0 bit 0 + + // TIMSK0: Timer/Counter Interrupt Mask Register + TIMSK0_ICIE0 = 0x8 // Timer/Counter n Input Capture Interrupt Enable + TIMSK0_OCIE0B = 0x4 // Output Compare Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Output Compare Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Overflow Interrupt Enable + + // TIFR0: Timer/Counter Interrupt Flag register + TIFR0_ICF0 = 0x8 // Timer/Counter Interrupt Flag Register + TIFR0_OCF0B = 0x4 // Output Compare Flag + TIFR0_OCF0A = 0x2 // Output Compare Flag + TIFR0_TOV0 = 0x1 // Overflow Flag +) + +// Bitfields for COULOMB_COUNTER: Coulomb Counter +const ( + // CADCSRA: CC-ADC Control and Status Register A + CADCSRA_CADEN = 0x80 // When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled. + CADCSRA_CADPOL = 0x40 + CADCSRA_CADUB = 0x20 // CC_ADC Update Busy + CADCSRA_CADAS = 0x18 // CC_ADC Accumulate Current Select Bits + CADCSRA_CADSI = 0x6 // The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. + CADCSRA_CADSE = 0x1 // When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode. + + // CADCSRB: CC-ADC Control and Status Register B + CADCSRB_CADACIE = 0x40 + CADCSRB_CADRCIE = 0x20 // Regular Current Interrupt Enable + CADCSRB_CADICIE = 0x10 // CAD Instantenous Current Interrupt Enable + CADCSRB_CADACIF = 0x4 // CC-ADC Accumulate Current Interrupt Flag + CADCSRB_CADRCIF = 0x2 // CC-ADC Accumulate Current Interrupt Flag + CADCSRB_CADICIF = 0x1 // CC-ADC Instantaneous Current Interrupt Flag +) + +// Bitfields for VOLTAGE_REGULATOR: Voltage Regulator +const ( + // ROCR: Regulator Operating Condition Register + ROCR_ROCS = 0x80 // ROC Status + ROCR_ROCWIF = 0x2 // ROC Warning Interrupt Flag + ROCR_ROCWIE = 0x1 // ROC Warning Interrupt Enable +) diff --git a/src/device/avr/atmega8hva.ld b/src/device/avr/atmega8hva.ld new file mode 100644 index 00000000..b8ad51f5 --- /dev/null +++ b/src/device/avr/atmega8hva.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega8HVA.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_size = 0x200; +__num_isrs = 21; diff --git a/src/device/avr/atmega8u2.go b/src/device/avr/atmega8u2.go new file mode 100644 index 00000000..2bc86e7c --- /dev/null +++ b/src/device/avr/atmega8u2.go @@ -0,0 +1,789 @@ +// Automatically generated file. DO NOT EDIT. +// Generated by gen-device.py from ATmega8U2.atdf, see http://packs.download.atmel.com/ + +// +build avr,atmega8u2 + +// Device information for the ATmega8U2. +// +package avr + +// Magic type name for the compiler. +type __reg uint8 + +// Export this magic type name. +type RegValue = __reg + +// Some information about this device. +const ( + DEVICE = "ATmega8U2" + ARCH = "AVR8" + FAMILY = "megaAVR" +) + +// Interrupts +const ( + IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. + IRQ_INT0 = 1 // External Interrupt Request 0 + IRQ_INT1 = 2 // External Interrupt Request 1 + IRQ_INT2 = 3 // External Interrupt Request 2 + IRQ_INT3 = 4 // External Interrupt Request 3 + IRQ_INT4 = 5 // External Interrupt Request 4 + IRQ_INT5 = 6 // External Interrupt Request 5 + IRQ_INT6 = 7 // External Interrupt Request 6 + IRQ_INT7 = 8 // External Interrupt Request 7 + IRQ_PCINT0 = 9 // Pin Change Interrupt Request 0 + IRQ_PCINT1 = 10 // Pin Change Interrupt Request 1 + IRQ_USB_GEN = 11 // USB General Interrupt Request + IRQ_USB_COM = 12 // USB Endpoint/Pipe Interrupt Communication Request + IRQ_WDT = 13 // Watchdog Time-out Interrupt + IRQ_TIMER1_CAPT = 14 // Timer/Counter2 Capture Event + IRQ_TIMER1_COMPA = 15 // Timer/Counter2 Compare Match B + IRQ_TIMER1_COMPB = 16 // Timer/Counter2 Compare Match B + IRQ_TIMER1_COMPC = 17 // Timer/Counter2 Compare Match C + IRQ_TIMER1_OVF = 18 // Timer/Counter1 Overflow + IRQ_TIMER0_COMPA = 19 // Timer/Counter0 Compare Match A + IRQ_TIMER0_COMPB = 20 // Timer/Counter0 Compare Match B + IRQ_TIMER0_OVF = 21 // Timer/Counter0 Overflow + IRQ_SPI_STC = 22 // SPI Serial Transfer Complete + IRQ_USART1_RX = 23 // USART1, Rx Complete + IRQ_USART1_UDRE = 24 // USART1 Data register Empty + IRQ_USART1_TX = 25 // USART1, Tx Complete + IRQ_ANALOG_COMP = 26 // Analog Comparator + IRQ_EE_READY = 27 // EEPROM Ready + IRQ_SPM_READY = 28 // Store Program Memory Read + IRQ_max = 28 // Highest interrupt number on this device. +) + +// Peripherals +var ( + // Fuses + FUSE = struct { + EXTENDED __reg + HIGH __reg + LOW __reg + }{ + EXTENDED: 0x2, + HIGH: 0x1, + LOW: 0x0, + } + + // Lockbits + LOCKBIT = struct { + LOCKBIT __reg + }{ + LOCKBIT: 0x0, + } + + // I/O Port + PORT = struct { + PORTB __reg + DDRB __reg + PINB __reg + PORTD __reg + DDRD __reg + PIND __reg + PORTC __reg + DDRC __reg + PINC __reg + }{ + PORTB: 0x25, // Port B Data Register + DDRB: 0x24, // Port B Data Direction Register + PINB: 0x23, // Port B Input Pins + PORTD: 0x2b, // Port D Data Register + DDRD: 0x2a, // Port D Data Direction Register + PIND: 0x29, // Port D Input Pins + PORTC: 0x28, // Port C Data Register + DDRC: 0x27, // Port C Data Direction Register + PINC: 0x26, // Port C Input Pins + } + + // Serial Peripheral Interface + SPI = struct { + SPCR __reg + SPSR __reg + SPDR __reg + }{ + SPCR: 0x4c, // SPI Control Register + SPSR: 0x4d, // SPI Status Register + SPDR: 0x4e, // SPI Data Register + } + + // Bootloader + BOOT_LOAD = struct { + SPMCSR __reg + }{ + SPMCSR: 0x57, // Store Program Memory Control Register + } + + // EEPROM + EEPROM = struct { + EEARL __reg + EEARH __reg + EEDR __reg + EECR __reg + }{ + EEARL: 0x41, // EEPROM Address Register Low Bytes + EEARH: 0x41, // EEPROM Address Register Low Bytes + EEDR: 0x40, // EEPROM Data Register + EECR: 0x3f, // EEPROM Control Register + } + + // Timer/Counter, 8-bit + TC8 = struct { + OCR0B __reg + OCR0A __reg + TCNT0 __reg + TCCR0B __reg + TCCR0A __reg + TIMSK0 __reg + TIFR0 __reg + GTCCR __reg + }{ + OCR0B: 0x48, // Timer/Counter0 Output Compare Register + OCR0A: 0x47, // Timer/Counter0 Output Compare Register + TCNT0: 0x46, // Timer/Counter0 + TCCR0B: 0x45, // Timer/Counter Control Register B + TCCR0A: 0x44, // Timer/Counter Control Register A + TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register + TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register + GTCCR: 0x43, // General Timer/Counter Control Register + } + + // Timer/Counter, 16-bit + TC16 = struct { + TCCR1A __reg + TCCR1B __reg + TCCR1C __reg + TCNT1L __reg + TCNT1H __reg + OCR1AL __reg + OCR1AH __reg + OCR1BL __reg + OCR1BH __reg + OCR1CL __reg + OCR1CH __reg + ICR1L __reg + ICR1H __reg + TIMSK1 __reg + TIFR1 __reg + }{ + TCCR1A: 0x80, // Timer/Counter1 Control Register A + TCCR1B: 0x81, // Timer/Counter1 Control Register B + TCCR1C: 0x82, // Timer/Counter 1 Control Register C + TCNT1L: 0x84, // Timer/Counter1 Bytes + TCNT1H: 0x84, // Timer/Counter1 Bytes + OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes + OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes + OCR1CL: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + OCR1CH: 0x8c, // Timer/Counter1 Output Compare Register C Bytes + ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes + ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes + TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register + TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register + } + + // Phase Locked Loop + PLL = struct { + PLLCSR __reg + }{ + PLLCSR: 0x49, // PLL Status and Control register + } + + // USB Device Registers + USB_DEVICE = struct { + UPOE __reg + UEINT __reg + UEBCLX __reg + UEDATX __reg + UEIENX __reg + UESTA1X __reg + UESTA0X __reg + UECFG1X __reg + UECFG0X __reg + UECONX __reg + UERST __reg + UENUM __reg + UEINTX __reg + UDMFN __reg + UDFNUML __reg + UDFNUMH __reg + UDADDR __reg + UDIEN __reg + UDINT __reg + UDCON __reg + USBCON __reg + REGCR __reg + }{ + UPOE: 0xfb, // USB Software Output Enable register + UEINT: 0xf4, // USB Endpoint Number Interrupt Register + UEBCLX: 0xf2, // USB Endpoint Byte Count Register + UEDATX: 0xf1, // USB Data Endpoint + UEIENX: 0xf0, // USB Endpoint Interrupt Enable Register + UESTA1X: 0xef, // USB Endpoint Status 1 Register + UESTA0X: 0xee, // USB Endpoint Status 0 Register + UECFG1X: 0xed, // USB Endpoint Configuration 1 Register + UECFG0X: 0xec, // USB Endpoint Configuration 0 Register + UECONX: 0xeb, // USB Endpoint Control Register + UERST: 0xea, // USB Endpoint Reset Register + UENUM: 0xe9, // USB Endpoint Number + UEINTX: 0xe8, // USB Endpoint Interrupt Register + UDMFN: 0xe6, // USB Device Micro Frame Number + UDFNUML: 0xe4, // USB Device Frame Number High Register + UDFNUMH: 0xe4, // USB Device Frame Number High Register + UDADDR: 0xe3, // USB Device Address Register + UDIEN: 0xe2, // USB Device Interrupt Enable Register + UDINT: 0xe1, // USB Device Interrupt Register + UDCON: 0xe0, // USB Device Control Registers + USBCON: 0xd8, // USB General Control Register + REGCR: 0x63, // Regulator Control Register + } + + // CPU Registers + CPU = struct { + SREG __reg + SPL __reg + SPH __reg + MCUCR __reg + MCUSR __reg + OSCCAL __reg + CLKPR __reg + SMCR __reg + EIND __reg + GPIOR2 __reg + GPIOR1 __reg + GPIOR0 __reg + PRR1 __reg + PRR0 __reg + CLKSTA __reg + CLKSEL1 __reg + CLKSEL0 __reg + DWDR __reg + }{ + SREG: 0x5f, // Status Register + SPL: 0x5d, // Stack Pointer + SPH: 0x5d, // Stack Pointer + MCUCR: 0x55, // MCU Control Register + MCUSR: 0x54, // MCU Status Register + OSCCAL: 0x66, // Oscillator Calibration Value + CLKPR: 0x61, + SMCR: 0x53, // Sleep Mode Control Register + EIND: 0x5c, // Extended Indirect Register + GPIOR2: 0x4b, // General Purpose IO Register 2 + GPIOR1: 0x4a, // General Purpose IO Register 1 + GPIOR0: 0x3e, // General Purpose IO Register 0 + PRR1: 0x65, // Power Reduction Register1 + PRR0: 0x64, // Power Reduction Register0 + CLKSTA: 0xd2, + CLKSEL1: 0xd1, + CLKSEL0: 0xd0, + DWDR: 0x51, // debugWire communication register + } + + // External Interrupts + EXINT = struct { + EICRA __reg + EICRB __reg + EIMSK __reg + EIFR __reg + PCMSK0 __reg + PCMSK1 __reg + PCIFR __reg + PCICR __reg + }{ + EICRA: 0x69, // External Interrupt Control Register A + EICRB: 0x6a, // External Interrupt Control Register B + EIMSK: 0x3d, // External Interrupt Mask Register + EIFR: 0x3c, // External Interrupt Flag Register + PCMSK0: 0x6b, // Pin Change Mask Register 0 + PCMSK1: 0x6c, // Pin Change Mask Register 1 + PCIFR: 0x3b, // Pin Change Interrupt Flag Register + PCICR: 0x68, // Pin Change Interrupt Control Register + } + + // USART + USART = struct { + UDR1 __reg + UCSR1A __reg + UCSR1B __reg + UCSR1C __reg + UCSR1D __reg + UBRR1L __reg + UBRR1H __reg + }{ + UDR1: 0xce, // USART I/O Data Register + UCSR1A: 0xc8, // USART Control and Status Register A + UCSR1B: 0xc9, // USART Control and Status Register B + UCSR1C: 0xca, // USART Control and Status Register C + UCSR1D: 0xcb, // USART Control and Status Register D + UBRR1L: 0xcc, // USART Baud Rate Register Bytes + UBRR1H: 0xcc, // USART Baud Rate Register Bytes + } + + // Watchdog Timer + WDT = struct { + WDTCSR __reg + WDTCKD __reg + }{ + WDTCSR: 0x60, // Watchdog Timer Control Register + WDTCKD: 0x62, // Watchdog Timer Clock Divider + } + + // Analog Comparator + AC = struct { + ACSR __reg + ACMUX __reg + DIDR1 __reg + }{ + ACSR: 0x50, // Analog Comparator Control And Status Register + ACMUX: 0x7d, // Analog Comparator Input Multiplexer + DIDR1: 0x7f, + } +) + +// Bitfields for FUSE: Fuses +const ( + // EXTENDED + EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level + EXTENDED_HWBE = 0x8 // Hardware Boot Enable + + // HIGH + HIGH_DWEN = 0x80 // Debug Wire enable + HIGH_RSTDISBL = 0x40 // Reset Disabled (Enable PC6 as i/o pin) + HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled + HIGH_WDTON = 0x10 // Watchdog timer always on + HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle + HIGH_BOOTSZ = 0x6 // Select Boot Size + HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled + + // LOW + LOW_CKDIV8 = 0x80 // Divide clock by 8 internally + LOW_CKOUT = 0x40 // Clock output on PORTC7 + LOW_SUT_CKSEL = 0x3f // Select Clock Source +) + +// Bitfields for LOCKBIT: Lockbits +const ( + // LOCKBIT + LOCKBIT_LB = 0x3 // Memory Lock + LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode + LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode +) + +// Bitfields for PORT: I/O Port +const ( + // PORTC: Port C Data Register + PORTC_PORTC = 0xf0 // Port C Data Register bits + PORTC_PORTC = 0x7 // Port C Data Register bits + + // DDRC: Port C Data Direction Register + DDRC_DDC = 0xf0 // Port C Data Direction Register bits + DDRC_DDC = 0x7 // Port C Data Direction Register bits + + // PINC: Port C Input Pins + PINC_PINC = 0xf0 // Port C Input Pins bits + PINC_PINC = 0x7 // Port C Input Pins bits +) + +// Bitfields for SPI: Serial Peripheral Interface +const ( + // SPCR: SPI Control Register + SPCR_SPIE = 0x80 // SPI Interrupt Enable + SPCR_SPE = 0x40 // SPI Enable + SPCR_DORD = 0x20 // Data Order + SPCR_MSTR = 0x10 // Master/Slave Select + SPCR_CPOL = 0x8 // Clock polarity + SPCR_CPHA = 0x4 // Clock Phase + SPCR_SPR = 0x3 // SPI Clock Rate Selects + + // SPSR: SPI Status Register + SPSR_SPIF = 0x80 // SPI Interrupt Flag + SPSR_WCOL = 0x40 // Write Collision Flag + SPSR_SPI2X = 0x1 // Double SPI Speed Bit +) + +// Bitfields for BOOT_LOAD: Bootloader +const ( + // SPMCSR: Store Program Memory Control Register + SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable + SPMCSR_RWWSB = 0x40 // Read While Write Section Busy + SPMCSR_SIGRD = 0x20 // Signature Row Read + SPMCSR_RWWSRE = 0x10 // Read While Write section read enable + SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set + SPMCSR_PGWRT = 0x4 // Page Write + SPMCSR_PGERS = 0x2 // Page Erase + SPMCSR_SPMEN = 0x1 // Store Program Memory Enable +) + +// Bitfields for EEPROM: EEPROM +const ( + // EECR: EEPROM Control Register + EECR_EEPM = 0x30 // EEPROM Programming Mode Bits + EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable + EECR_EEMPE = 0x4 // EEPROM Master Write Enable + EECR_EEPE = 0x2 // EEPROM Write Enable + EECR_EERE = 0x1 // EEPROM Read Enable +) + +// Bitfields for TC8: Timer/Counter, 8-bit +const ( + // TCCR0B: Timer/Counter Control Register B + TCCR0B_FOC0A = 0x80 // Force Output Compare A + TCCR0B_FOC0B = 0x40 // Force Output Compare B + TCCR0B_WGM02 = 0x8 + TCCR0B_CS0 = 0x7 // Clock Select + + // TCCR0A: Timer/Counter Control Register A + TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode + TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm + TCCR0A_WGM0 = 0x3 // Waveform Generation Mode + + // TIMSK0: Timer/Counter0 Interrupt Mask Register + TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable + TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable + TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable + + // TIFR0: Timer/Counter0 Interrupt Flag register + TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B + TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A + TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag + + // GTCCR: General Timer/Counter Control Register + GTCCR_TSM = 0x80 // Timer/Counter Synchronization Mode + GTCCR_PSRSYNC = 0x1 // Prescaler Reset Timer/Counter1 and Timer/Counter0 +) + +// Bitfields for TC16: Timer/Counter, 16-bit +const ( + // TCCR1A: Timer/Counter1 Control Register A + TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits + TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits + TCCR1A_COM1C = 0xc // Compare Output Mode 1C, bits + TCCR1A_WGM1 = 0x3 // Waveform Generation Mode + + // TCCR1B: Timer/Counter1 Control Register B + TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler + TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select + TCCR1B_WGM1 = 0x18 // Waveform Generation Mode + TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1 + + // TCCR1C: Timer/Counter 1 Control Register C + TCCR1C_FOC1A = 0x80 // Force Output Compare 1A + TCCR1C_FOC1B = 0x40 // Force Output Compare 1B + TCCR1C_FOC1C = 0x20 // Force Output Compare 1C + + // TIMSK1: Timer/Counter1 Interrupt Mask Register + TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable + TIMSK1_OCIE1C = 0x8 // Timer/Counter1 Output Compare C Match Interrupt Enable + TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable + TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable + TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable + + // TIFR1: Timer/Counter1 Interrupt Flag register + TIFR1_ICF1 = 0x20 // Input Capture Flag 1 + TIFR1_OCF1C = 0x8 // Output Compare Flag 1C + TIFR1_OCF1B = 0x4 // Output Compare Flag 1B + TIFR1_OCF1A = 0x2 // Output Compare Flag 1A + TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag +) + +// Bitfields for PLL: Phase Locked Loop +const ( + // PLLCSR: PLL Status and Control register + PLLCSR_PLLP = 0x1c // PLL prescaler Bits + PLLCSR_PLLE = 0x2 // PLL Enable Bit + PLLCSR_PLOCK = 0x1 // PLL Lock Status Bit +) + +// Bitfields for USB_DEVICE: USB Device Registers +const ( + // UPOE: USB Software Output Enable register + UPOE_UPWE = 0xc0 // USB Buffers Direct Drive enable configuration + UPOE_UPDRV = 0x30 // USB direct drive values + UPOE_DPI = 0x2 // D+ Input value + UPOE_DMI = 0x1 // D- Input value + + // UEINT: USB Endpoint Number Interrupt Register + UEINT_EPINT = 0x1f // Byte Count bits + + // UEBCLX: USB Endpoint Byte Count Register + UEBCLX_BYCT = 0xff // Byte Count bits + + // UEDATX: USB Data Endpoint + UEDATX_DAT = 0xff // Data bits + + // UEIENX: USB Endpoint Interrupt Enable Register + UEIENX_FLERRE = 0x80 // Flow Error Interrupt Enable Flag + UEIENX_NAKINE = 0x40 // NAK IN Interrupt Enable Bit + UEIENX_NAKOUTE = 0x10 // NAK OUT Interrupt Enable Bit + UEIENX_RXSTPE = 0x8 // Received SETUP Interrupt Enable Flag + UEIENX_RXOUTE = 0x4 // Received OUT Data Interrupt Enable Flag + UEIENX_STALLEDE = 0x2 // Stalled Interrupt Enable Flag + UEIENX_TXINE = 0x1 // Transmitter Ready Interrupt Enable Flag + + // UESTA1X: USB Endpoint Status 1 Register + UESTA1X_CTRLDIR = 0x4 // Control Direction + UESTA1X_CURRBK = 0x3 // Current Bank + + // UESTA0X: USB Endpoint Status 0 Register + UESTA0X_CFGOK = 0x80 // Configuration Status Flag + UESTA0X_OVERFI = 0x40 // Overflow Error Interrupt Flag + UESTA0X_UNDERFI = 0x20 // Underflow Error Interrupt Flag + UESTA0X_DTSEQ = 0xc // Data Toggle Sequencing Flag + UESTA0X_NBUSYBK = 0x3 // Busy Bank Flag + + // UECFG1X: USB Endpoint Configuration 1 Register + UECFG1X_EPSIZE = 0x70 // Endpoint Size Bits + UECFG1X_EPBK = 0xc // Endpoint Bank Bits + UECFG1X_ALLOC = 0x2 // Endpoint Allocation Bit + + // UECFG0X: USB Endpoint Configuration 0 Register + UECFG0X_EPTYPE = 0xc0 // Endpoint Type Bits + UECFG0X_EPDIR = 0x1 // Endpoint Direction Bit + + // UECONX: USB Endpoint Control Register + UECONX_STALLRQ = 0x20 // STALL Request Handshake Bit + UECONX_STALLRQC = 0x10 // STALL Request Clear Handshake Bit + UECONX_RSTDT = 0x8 // Reset Data Toggle Bit + UECONX_EPEN = 0x1 // Endpoint Enable Bit + + // UERST: USB Endpoint Reset Register + UERST_EPRST = 0x1f // Endpoint FIFO Reset Bits + + // UENUM: USB Endpoint Number + UENUM_EPNUM = 0x7 // Endpoint Number bits + + // UEINTX: USB Endpoint Interrupt Register + UEINTX_FIFOCON = 0x80 // FIFO Control Bit + UEINTX_NAKINI = 0x40 // NAK IN Received Interrupt Flag + UEINTX_RWAL = 0x20 // Read/Write Allowed Flag + UEINTX_NAKOUTI = 0x10 // NAK OUT Received Interrupt Flag + UEINTX_RXSTPI = 0x8 // Received SETUP Interrupt Flag + UEINTX_RXOUTI = 0x4 // Received OUT Data Interrupt Flag + UEINTX_STALLEDI = 0x2 // STALLEDI Interrupt Flag + UEINTX_TXINI = 0x1 // Transmitter Ready Interrupt Flag + + // UDMFN: USB Device Micro Frame Number + UDMFN_FNCERR = 0x10 // Frame Number CRC Error Flag + + // UDFNUML: USB Device Frame Number High Register + + // UDFNUMH: USB Device Frame Number High Register + UDFNUM_FNUM = 0x7ff // Frame Number Upper Flag + + // UDADDR: USB Device Address Register + UDADDR_ADDEN = 0x80 // Address Enable Bit + UDADDR_UADD = 0x7f // USB Address Bits + + // UDIEN: USB Device Interrupt Enable Register + UDIEN_UPRSME = 0x40 // Upstream Resume Interrupt Enable Bit + UDIEN_EORSME = 0x20 // End Of Resume Interrupt Enable Bit + UDIEN_WAKEUPE = 0x10 // Wake-up CPU Interrupt Enable Bit + UDIEN_EORSTE = 0x8 // End Of Reset Interrupt Enable Bit + UDIEN_SOFE = 0x4 // Start Of Frame Interrupt Enable Bit + UDIEN_SUSPE = 0x1 // Suspend Interrupt Enable Bit + + // UDINT: USB Device Interrupt Register + UDINT_UPRSMI = 0x40 // Upstream Resume Interrupt Flag + UDINT_EORSMI = 0x20 // End Of Resume Interrupt Flag + UDINT_WAKEUPI = 0x10 // Wake-up CPU Interrupt Flag + UDINT_EORSTI = 0x8 // End Of Reset Interrupt Flag + UDINT_SOFI = 0x4 // Start Of Frame Interrupt Flag + UDINT_SUSPI = 0x1 // Suspend Interrupt Flag + + // UDCON: USB Device Control Registers + UDCON_RSTCPU = 0x4 // USB Reset CPU Bit + UDCON_RMWKUP = 0x2 // Remote Wake-up Bit + UDCON_DETACH = 0x1 // Detach Bit + + // USBCON: USB General Control Register + USBCON_USBE = 0x80 // USB macro Enable Bit + USBCON_FRZCLK = 0x20 // Freeze USB Clock Bit + + // REGCR: Regulator Control Register + REGCR_REGDIS = 0x1 // Regulator Disable +) + +// Bitfields for CPU: CPU Registers +const ( + // SREG: Status Register + SREG_I = 0x80 // Global Interrupt Enable + SREG_T = 0x40 // Bit Copy Storage + SREG_H = 0x20 // Half Carry Flag + SREG_S = 0x10 // Sign Bit + SREG_V = 0x8 // Two's Complement Overflow Flag + SREG_N = 0x4 // Negative Flag + SREG_Z = 0x2 // Zero Flag + SREG_C = 0x1 // Carry Flag + + // MCUCR: MCU Control Register + MCUCR_PUD = 0x10 // Pull-up disable + MCUCR_IVSEL = 0x2 // Interrupt Vector Select + MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable + + // MCUSR: MCU Status Register + MCUSR_USBRF = 0x20 // USB reset flag + MCUSR_WDRF = 0x8 // Watchdog Reset Flag + MCUSR_BORF = 0x4 // Brown-out Reset Flag + MCUSR_EXTRF = 0x2 // External Reset Flag + MCUSR_PORF = 0x1 // Power-on reset flag + + // OSCCAL: Oscillator Calibration Value + OSCCAL_OSCCAL = 0xff // Oscillator Calibration + + // CLKPR + CLKPR_CLKPCE = 0x80 + CLKPR_CLKPS = 0xf + + // SMCR: Sleep Mode Control Register + SMCR_SM = 0xe // Sleep Mode Select bits + SMCR_SE = 0x1 // Sleep Enable + + // GPIOR2: General Purpose IO Register 2 + GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis + + // GPIOR1: General Purpose IO Register 1 + GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis + + // GPIOR0: General Purpose IO Register 0 + GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7 + GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6 + GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5 + GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4 + GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3 + GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2 + GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1 + GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0 + + // PRR1: Power Reduction Register1 + PRR1_PRUSB = 0x80 // Power Reduction USB + PRR1_PRUSART1 = 0x1 // Power Reduction USART1 + + // PRR0: Power Reduction Register0 + PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0 + PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1 + PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface + + // CLKSTA + CLKSTA_RCON = 0x2 + CLKSTA_EXTON = 0x1 + + // CLKSEL1 + CLKSEL1_RCCKSEL = 0xf0 + CLKSEL1_EXCKSEL = 0xf + + // CLKSEL0 + CLKSEL0_RCSUT = 0xc0 + CLKSEL0_EXSUT = 0x30 + CLKSEL0_RCE = 0x8 + CLKSEL0_EXTE = 0x4 + CLKSEL0_CLKS = 0x1 +) + +// Bitfields for EXINT: External Interrupts +const ( + // EICRA: External Interrupt Control Register A + EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit + EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit + EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit + EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit + + // EICRB: External Interrupt Control Register B + EICRB_ISC7 = 0xc0 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC6 = 0x30 // External Interrupt 7-4 Sense Control Bit + EICRB_ISC5 = 0xc // External Interrupt 7-4 Sense Control Bit + EICRB_ISC4 = 0x3 // External Interrupt 7-4 Sense Control Bit + + // EIMSK: External Interrupt Mask Register + EIMSK_INT = 0xff // External Interrupt Request 7 Enable + + // EIFR: External Interrupt Flag Register + EIFR_INTF = 0xff // External Interrupt Flags + + // PCMSK0: Pin Change Mask Register 0 + PCMSK0_PCINT = 0xff // Pin Change Enable Masks + + // PCMSK1: Pin Change Mask Register 1 + PCMSK1_PCINT = 0x1f + + // PCIFR: Pin Change Interrupt Flag Register + PCIFR_PCIF = 0x3 // Pin Change Interrupt Flags + + // PCICR: Pin Change Interrupt Control Register + PCICR_PCIE = 0x3 // Pin Change Interrupt Enables +) + +// Bitfields for USART: USART +const ( + // UCSR1A: USART Control and Status Register A + UCSR1A_RXC1 = 0x80 // USART Receive Complete + UCSR1A_TXC1 = 0x40 // USART Transmitt Complete + UCSR1A_UDRE1 = 0x20 // USART Data Register Empty + UCSR1A_FE1 = 0x10 // Framing Error + UCSR1A_DOR1 = 0x8 // Data overRun + UCSR1A_UPE1 = 0x4 // Parity Error + UCSR1A_U2X1 = 0x2 // Double the USART transmission speed + UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode + + // UCSR1B: USART Control and Status Register B + UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable + UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable + UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable + UCSR1B_RXEN1 = 0x10 // Receiver Enable + UCSR1B_TXEN1 = 0x8 // Transmitter Enable + UCSR1B_UCSZ12 = 0x4 // Character Size + UCSR1B_RXB81 = 0x2 // Receive Data Bit 8 + UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8 + + // UCSR1C: USART Control and Status Register C + UCSR1C_UMSEL1 = 0xc0 // USART Mode Select + UCSR1C_UPM1 = 0x30 // Parity Mode Bits + UCSR1C_USBS1 = 0x8 // Stop Bit Select + UCSR1C_UCSZ1 = 0x6 // Character Size + UCSR1C_UCPOL1 = 0x1 // Clock Polarity + + // UCSR1D: USART Control and Status Register D + UCSR1D_CTSEN = 0x2 // CTS Enable + UCSR1D_RTSEN = 0x1 // RTS Enable +) + +// Bitfields for WDT: Watchdog Timer +const ( + // WDTCSR: Watchdog Timer Control Register + WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag + WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable + WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits + WDTCSR_WDCE = 0x10 // Watchdog Change Enable + WDTCSR_WDE = 0x8 // Watch Dog Enable + + // WDTCKD: Watchdog Timer Clock Divider + WDTCKD_WDEWIF = 0x8 // Watchdog Early Warning Interrupt Flag + WDTCKD_WDEWIE = 0x4 // Watchdog Early Warning Interrupt Enable + WDTCKD_WCLKD = 0x3 // Watchdog Timer Clock Dividers +) + +// Bitfields for AC: Analog Comparator +const ( + // ACSR: Analog Comparator Control And Status Register + ACSR_ACD = 0x80 // Analog Comparator Disable + ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select + ACSR_ACO = 0x20 // Analog Compare Output + ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag + ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable + ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable + ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits + + // ACMUX: Analog Comparator Input Multiplexer + ACMUX_CMUX = 0x7 // Analog Comparator Selection Bits + + // DIDR1 + DIDR1_AIN7D = 0x80 // AIN7 Digital Input Disable + DIDR1_AIN6D = 0x40 // AIN6 Digital Input Disable + DIDR1_AIN5D = 0x20 // AIN5 Digital Input Disable + DIDR1_AIN4D = 0x10 // AIN4 Digital Input Disable + DIDR1_AIN3D = 0x8 // AIN3 Digital Input Disable + DIDR1_AIN2D = 0x4 // AIN2 Digital Input Disable + DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable + DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable +) diff --git a/src/device/avr/atmega8u2.ld b/src/device/avr/atmega8u2.ld new file mode 100644 index 00000000..6c1f92ac --- /dev/null +++ b/src/device/avr/atmega8u2.ld @@ -0,0 +1,6 @@ +/* Automatically generated file. DO NOT EDIT. */ +/* Generated by gen-device.py from ATmega8U2.atdf, see http://packs.download.atmel.com/ */ + +__flash_size = 0x2000; +__ram_size = 0x200; +__num_isrs = 29; diff --git a/src/device/avr/avr.go b/src/device/avr/avr.go new file mode 100644 index 00000000..ba4347d2 --- /dev/null +++ b/src/device/avr/avr.go @@ -0,0 +1,9 @@ +package avr + +// Magic type recognozed by the compiler to mark this string as inline assembly. +type __asm string + +// Run the given assembly code. The code will be marked as having side effects, +// as it doesn't produce output and thus would normally be eliminated by the +// optimizer. +func Asm(asm __asm) diff --git a/src/machine/machine_avr.go b/src/machine/machine_avr.go new file mode 100644 index 00000000..664f8399 --- /dev/null +++ b/src/machine/machine_avr.go @@ -0,0 +1,50 @@ + +// +build avr + +package machine + +import ( + "device/avr" +) + +type GPIOMode uint8 + +const ( + GPIO_INPUT = iota + GPIO_OUTPUT +) + +// LED on the Arduino +const LED = 13 + +func (p GPIO) Configure(config GPIOConfig) { + if config.Mode == GPIO_OUTPUT { // set output bit + if p.Pin < 8 { + avr.PORT.DDRD |= 1 << p.Pin + } else { + avr.PORT.DDRB |= 1 << (p.Pin - 8) + } + } else { // configure input: clear output bit + if p.Pin < 8 { + avr.PORT.DDRD &^= 1 << p.Pin + } else { + avr.PORT.DDRB &^= 1 << (p.Pin - 8) + } + } +} + +func (p GPIO) Set(value bool) { + if value { // set bits + if p.Pin < 8 { + avr.PORT.PORTD |= 1 << p.Pin + } else { + avr.PORT.PORTB |= 1 << (p.Pin - 8) + } + } else { // clear bits + if p.Pin < 8 { + avr.PORT.PORTB &^= 1 << p.Pin + } else { + avr.PORT.PORTB &^= 1 << (p.Pin - 8) + } + } +} diff --git a/src/runtime/runtime_avr.go b/src/runtime/runtime_avr.go new file mode 100644 index 00000000..939595fb --- /dev/null +++ b/src/runtime/runtime_avr.go @@ -0,0 +1,109 @@ + +// +build avr + +package runtime + +import ( + "device/avr" +) + +const BOARD = "arduino" + +const Microsecond = 1 + +var currentTime uint64 + +func init() { + currentTime = 0 +} + +// Watchdog timer periods. These can be off by a large margin (hence the jump +// between 64ms and 125ms which is not an exact double), so don't rely on this +// for accurate time keeping. +const ( + WDT_PERIOD_16MS = iota + WDT_PERIOD_32MS + WDT_PERIOD_64MS + WDT_PERIOD_125MS + WDT_PERIOD_250MS + WDT_PERIOD_500MS + WDT_PERIOD_1S + WDT_PERIOD_2S +) + +func init() { + initUART() +} + +func initUART() { + // Initialize UART at 115200 baud when running at 16MHz. + avr.USART.UBRR0H = 0 + avr.USART.UBRR0L = 8 + avr.USART.UCSR0B = avr.UCSR0B_RXEN0 | avr.UCSR0B_TXEN0 // enable RX and TX + avr.USART.UCSR0C = avr.UCSR0C_UCSZ0 // 8-bits data +} + +func putchar(c byte) { + for (avr.USART.UCSR0A & avr.UCSR0A_UDRE0) == 0 { + // Wait until previous char has been sent. + } + avr.USART.UDR0 = avr.RegValue(c) // send char +} + +// Sleep by the given amount. +// +// TODO: not very accurate. Improve accuracy by calibrating on startup and every +// once in a while. +func sleep(d Duration) { + currentTime += uint64(d) + d /= 16384 // about 16ms + for d != 0 { + sleepWDT(WDT_PERIOD_16MS) + d -= 1 + } +} + +// Sleep for a given period. The period is defined by the WDT peripheral, and is +// on most chips (at least) 3 bits wide, in powers of two from 16ms to 2s +// (0=16ms, 1=32ms, 2=64ms...). Note that the WDT is not very accurate: it can +// be off by a large margin depending on temperature and supply voltage. +// +// TODO: disable more peripherals etc. to reduce sleep current. +func sleepWDT(period uint8) { + // Configure WDT + avr.Asm("cli") + avr.Asm("wdr") + // Start timed sequence. + avr.WDT.WDTCSR |= avr.WDTCSR_WDCE | avr.WDTCSR_WDE + // Enable WDT and set new timeout (0.5s) + avr.WDT.WDTCSR = avr.WDTCSR_WDIE | avr.RegValue(period) + avr.Asm("sei") + + // Set sleep mode to idle and enable sleep mode. + // Note: when using something other than idle, the UART won't work + // correctly. This needs to be fixed, though, so we can truly sleep. + avr.CPU.SMCR = (0 << 1) | avr.SMCR_SE + + // go to sleep + avr.Asm("sleep") + + // disable sleep + avr.CPU.SMCR = 0 +} + +func monotime() uint64 { + return currentTime +} + +func abort() { + avr.Asm("cli") + for { + sleepWDT(WDT_PERIOD_2S) + } +} + +// Align on a word boundary. +func align(ptr uintptr) uintptr { + // No alignment necessary on the AVR. + return ptr +} diff --git a/tgo.go b/tgo.go index 71d2e00f..80118386 100644 --- a/tgo.go +++ b/tgo.go @@ -1588,6 +1588,9 @@ func Compile(pkgName, runtimePath, outpath, target string, printIR bool) error { if target == "pca10040" { buildTags = append(buildTags, "nrf", "nrf52", "nrf52832") target = "armv7m-none-eabi" + } else if target == "arduino" { + buildTags = append(buildTags, "avr", "avr8", "atmega", "atmega328p") + target = "avr--" } c, err := NewCompiler(pkgName, target)