feather-stm32f405: add SPI support (#1377)
* machine/stm32f405: add SPI support
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ardnew
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родитель
431e51b8a0
коммит
9ad2315079
3 изменённых файлов: 136 добавлений и 42 удалений
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@ -178,6 +178,22 @@ const (
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SPI_SDO_PIN = SPI0_SDO_PIN //
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)
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var (
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SPI1 = SPI{
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Bus: stm32.SPI2,
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AltFuncSelector: stm32.AF5_SPI1_SPI2,
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}
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SPI2 = SPI{
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Bus: stm32.SPI3,
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AltFuncSelector: stm32.AF6_SPI3,
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}
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SPI3 = SPI{
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Bus: stm32.SPI1,
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AltFuncSelector: stm32.AF5_SPI1_SPI2,
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}
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SPI0 = SPI1
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)
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func initSPI() {}
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// -- I2C ----------------------------------------------------------------------
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@ -20,15 +20,42 @@ type SPIConfig struct {
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}
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// Configure is intended to setup the STM32 SPI1 interface.
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// Features still TODO:
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// - support SPI2 and SPI3
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// - allow setting data size to 16 bits?
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// - allow setting direction in HW for additional optimization?
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// - hardware SS pin?
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func (spi SPI) Configure(config SPIConfig) {
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// -- CONFIGURING THE SPI IN MASTER MODE --
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//
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// 1. Select the BR[2:0] bits to define the serial clock baud rate (see
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// SPI_CR1 register).
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// 2. Select the CPOL and CPHA bits to define one of the four relationships
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// between the data transfer and the serial clock (see Figure 248). This
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// step is not required when the TI mode is selected.
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// 3. Set the DFF bit to define 8- or 16-bit data frame format
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// 4. Configure the LSBFIRST bit in the SPI_CR1 register to define the frame
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// format. This step is not required when the TI mode is selected.
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// 5. If the NSS pin is required in input mode, in hardware mode, connect the
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// NSS pin to a high-level signal during the complete byte transmit
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// sequence. In NSS software mode, set the SSM and SSI bits in the SPI_CR1
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// register. If the NSS pin is required in output mode, the SSOE bit only
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// should be set. This step is not required when the TI mode is selected.
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// 6. Set the FRF bit in SPI_CR2 to select the TI protocol for serial
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// communications.
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// 7. The MSTR and SPE bits must be set (they remain set only if the NSS pin
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// is connected to a high-level signal).
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// disable SPI interface before any configuration changes
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spi.Bus.CR1.ClearBits(stm32.SPI_CR1_SPE)
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// enable clock for SPI
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enableAltFuncClock(unsafe.Pointer(spi.Bus))
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// init pins
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if config.SCK == 0 && config.SDO == 0 && config.SDI == 0 {
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config.SCK = SPI0_SCK_PIN
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config.SDO = SPI0_SDO_PIN
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config.SDI = SPI0_SDI_PIN
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}
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spi.configurePins(config)
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// Get SPI baud rate based on the bus speed it's attached to
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var conf uint32 = spi.getBaudRate(config)
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@ -39,61 +66,72 @@ func (spi SPI) Configure(config SPIConfig) {
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// set polarity and phase on the SPI interface
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switch config.Mode {
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case Mode0:
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conf &^= (1 << stm32.SPI_CR1_CPOL_Pos)
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conf &^= (1 << stm32.SPI_CR1_CPHA_Pos)
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case Mode1:
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conf &^= (1 << stm32.SPI_CR1_CPOL_Pos)
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conf |= (1 << stm32.SPI_CR1_CPHA_Pos)
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conf |= stm32.SPI_CR1_CPHA
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case Mode2:
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conf |= (1 << stm32.SPI_CR1_CPOL_Pos)
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conf &^= (1 << stm32.SPI_CR1_CPHA_Pos)
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conf |= stm32.SPI_CR1_CPOL
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case Mode3:
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conf |= (1 << stm32.SPI_CR1_CPOL_Pos)
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conf |= (1 << stm32.SPI_CR1_CPHA_Pos)
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default: // to mode 0
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conf &^= (1 << stm32.SPI_CR1_CPOL_Pos)
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conf &^= (1 << stm32.SPI_CR1_CPHA_Pos)
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conf |= stm32.SPI_CR1_CPOL
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conf |= stm32.SPI_CR1_CPHA
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}
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// set to SPI controller
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conf |= stm32.SPI_CR1_MSTR
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// configure as SPI master
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conf |= stm32.SPI_CR1_MSTR | stm32.SPI_CR1_SSI
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// disable MCU acting as SPI peripheral
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conf |= stm32.SPI_CR1_SSM | stm32.SPI_CR1_SSI
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// enable the SPI interface
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conf |= stm32.SPI_CR1_SPE
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// use software CS (GPIO) by default
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conf |= stm32.SPI_CR1_SSM
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// now set the configuration
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spi.Bus.CR1.Set(conf)
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// init pins
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if config.SCK == 0 && config.SDO == 0 && config.SDI == 0 {
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config.SCK = SPI0_SCK_PIN
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config.SDO = SPI0_SDO_PIN
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config.SDI = SPI0_SDI_PIN
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}
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spi.configurePins(config)
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// enable SPI interface
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spi.Bus.CR1.SetBits(stm32.SPI_CR1_SPE)
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spi.Bus.CR2.SetBits((conf & stm32.SPI_CR1_SSM_Msk) >> 16)
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}
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// Transfer writes/reads a single byte using the SPI interface.
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func (spi SPI) Transfer(w byte) (byte, error) {
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// Write data to be transmitted to the SPI data register
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// 1. Enable the SPI by setting the SPE bit to 1.
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// 2. Write the first data item to be transmitted into the SPI_DR register
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// (this clears the TXE flag).
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// 3. Wait until TXE=1 and write the second data item to be transmitted. Then
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// wait until RXNE=1 and read the SPI_DR to get the first received data
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// item (this clears the RXNE bit). Repeat this operation for each data
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// item to be transmitted/received until the n–1 received data.
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// 4. Wait until RXNE=1 and read the last received data.
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// 5. Wait until TXE=1 and then wait until BSY=0 before disabling the SPI.
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// put output word (8-bit) in data register (DR), which is parallel-loaded
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// into shift register, and shifted out on MOSI.
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spi.Bus.DR.Set(uint32(w))
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// Wait until transmit complete
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for !spi.Bus.SR.HasBits(stm32.SPI_SR_TXE) {
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}
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// Wait until receive complete
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// wait for SPI bus receive buffer not empty bit (RXNE) to be set.
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// warning: blocks forever until this condition is met.
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for !spi.Bus.SR.HasBits(stm32.SPI_SR_RXNE) {
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}
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// Wait until SPI is not busy
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// copy input word (8-bit) in data register (DR), which was shifted in on MISO
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// and parallel-loaded into register.
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data := byte(spi.Bus.DR.Get())
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// wait for SPI bus transmit buffer empty bit (TXE) to be set.
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// warning: blocks forever until this condition is met.
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for !spi.Bus.SR.HasBits(stm32.SPI_SR_TXE) {
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}
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// wait for SPI bus busy bit (BSY) to be clear to indicate synchronous
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// transfer complete. this will effectively prevent this Transfer() function
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// from being capable of maintaining high-bandwidth communication throughput,
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// but it will help guarantee stability on the bus.
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for spi.Bus.SR.HasBits(stm32.SPI_SR_BSY) {
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}
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// clear the overrun flag (only in full-duplex mode)
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if !spi.Bus.CR1.HasBits(stm32.SPI_CR1_RXONLY | stm32.SPI_CR1_BIDIMODE | stm32.SPI_CR1_BIDIOE) {
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spi.Bus.SR.Get()
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}
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// Return received data from SPI data register
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return byte(spi.Bus.DR.Get()), nil
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return data, nil
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}
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@ -6,6 +6,7 @@ package machine
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import (
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"device/stm32"
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"math/bits"
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"runtime/interrupt"
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)
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@ -46,8 +47,47 @@ type SPI struct {
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AltFuncSelector stm32.AltFunc
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}
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func (spi SPI) configurePins(config SPIConfig) {}
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func (spi SPI) getBaudRate(config SPIConfig) uint32 { return 0 }
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func (spi SPI) configurePins(config SPIConfig) {
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config.SCK.ConfigureAltFunc(PinConfig{Mode: PinModeSPICLK}, spi.AltFuncSelector)
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config.SDO.ConfigureAltFunc(PinConfig{Mode: PinModeSPISDO}, spi.AltFuncSelector)
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config.SDI.ConfigureAltFunc(PinConfig{Mode: PinModeSPISDI}, spi.AltFuncSelector)
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}
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func (spi SPI) getBaudRate(config SPIConfig) uint32 {
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var clock uint32
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switch spi.Bus {
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case stm32.SPI1:
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clock = CPUFrequency() / 2
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case stm32.SPI2, stm32.SPI3:
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clock = CPUFrequency() / 4
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}
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// limit requested frequency to bus frequency and min frequency (DIV256)
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freq := config.Frequency
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if min := clock / 256; freq < min {
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freq = min
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} else if freq > clock {
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freq = clock
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}
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// calculate the exact clock divisor (freq=clock/div -> div=clock/freq).
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// truncation is fine, since it produces a less-than-or-equal divisor, and
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// thus a greater-than-or-equal frequency.
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// divisors only come in consecutive powers of 2, so we can use log2 (or,
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// equivalently, bits.Len - 1) to convert to respective enum value.
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div := bits.Len32(clock/freq) - 1
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// but DIV1 (2^0) is not permitted, as the least divisor is DIV2 (2^1), so
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// subtract 1 from the log2 value, keeping a lower bound of 0
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if div < 0 {
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div = 0
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} else if div > 0 {
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div--
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}
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// finally, shift the enumerated value into position for SPI CR1
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return uint32(div) << stm32.SPI_CR1_BR_Pos
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}
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// -- I2C ----------------------------------------------------------------------
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