add basic UART handler
Этот коммит содержится в:
ardnew
Ron Evans
родитель
19d5e05e37
коммит
a9a6d0ee63
3 изменённых файлов: 79 добавлений и 25 удалений
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@ -2,6 +2,11 @@
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package machine
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import (
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"device/stm32"
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"runtime/interrupt"
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)
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const (
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NUM_DIGITAL_IO_PINS = 39
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NUM_ANALOG_IO_PINS = 7
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@ -113,7 +118,30 @@ const (
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UART_TX_PIN = UART0_TX_PIN //
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)
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func initUART() {}
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var (
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UART1 = UART{
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Buffer: NewRingBuffer(),
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Bus: stm32.USART3,
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AltFuncSelector: stm32.AF7_USART1_2_3,
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}
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UART2 = UART{
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Buffer: NewRingBuffer(),
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Bus: stm32.USART6,
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AltFuncSelector: stm32.AF8_USART4_5_6,
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}
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UART3 = UART{
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Buffer: NewRingBuffer(),
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Bus: stm32.USART1,
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AltFuncSelector: stm32.AF7_USART1_2_3,
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}
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UART0 = UART1
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)
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func initUART() {
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UART1.Interrupt = interrupt.New(stm32.IRQ_USART3, UART1.handleInterrupt)
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UART2.Interrupt = interrupt.New(stm32.IRQ_USART6, UART2.handleInterrupt)
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UART3.Interrupt = interrupt.New(stm32.IRQ_USART1, UART3.handleInterrupt)
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}
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// -- SPI ----------------------------------------------------------------------
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@ -22,8 +22,22 @@ type UART struct {
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AltFuncSelector stm32.AltFunc
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}
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func (uart UART) configurePins(config UARTConfig) {}
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func (uart UART) getBaudRateDivisor(baudRate uint32) uint32 { return 0 }
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func (uart UART) configurePins(config UARTConfig) {
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// enable the alternate functions on the TX and RX pins
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config.TX.ConfigureAltFunc(PinConfig{Mode: PinModeUARTTX}, uart.AltFuncSelector)
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config.RX.ConfigureAltFunc(PinConfig{Mode: PinModeUARTRX}, uart.AltFuncSelector)
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}
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func (uart UART) getBaudRateDivisor(baudRate uint32) uint32 {
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var clock uint32
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switch uart.Bus {
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case stm32.USART1, stm32.USART6:
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clock = CPUFrequency() / 2 // APB2 Frequency
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case stm32.USART2, stm32.USART3, stm32.UART4, stm32.UART5:
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clock = CPUFrequency() / 4 // APB1 Frequency
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}
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return clock / baudRate
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}
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// -- SPI ----------------------------------------------------------------------
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@ -1,10 +1,11 @@
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// +build stm32,stm32f4,stm32f405
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// +build stm32f405
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package runtime
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import (
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"device/arm"
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"device/stm32"
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"machine"
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"runtime/interrupt"
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"runtime/volatile"
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)
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@ -13,6 +14,7 @@ func init() {
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initOSC() // configure oscillators
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initCLK() // configure CPU, AHB, and APB bus clocks
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initTIM() // configure timers
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initCOM() // configure serial comm interfaces
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}
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const (
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@ -42,7 +44,8 @@ const (
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PLL_DIV_P = ((2 >> 1) - 1) << stm32.RCC_PLLCFGR_PLLP0_Pos
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PLL_DIV_Q = 7 << stm32.RCC_PLLCFGR_PLLQ0_Pos
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SYSCLK_SRC_PLL = 2 << stm32.RCC_CFGR_SW0_Pos
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SYSCLK_SRC_PLL = 2 << stm32.RCC_CFGR_SW0_Pos
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SYSCLK_STAT_PLL = 2 << stm32.RCC_CFGR_SWS0_Pos
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RCC_DIV_PCLK1 = 5 << stm32.RCC_CFGR_PPRE1_Pos // HCLK / 4
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RCC_DIV_PCLK2 = 4 << stm32.RCC_CFGR_PPRE2_Pos // HCLK / 2
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@ -52,22 +55,19 @@ const (
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)
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const (
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// +---------------------+---------------------------------------------------------------------------+
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// | | HCLK (MHz) |
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// | +------------------+------------------+------------------+------------------+
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// | Wait states (WS) | Voltage range | Voltage range | Voltage range | Voltage range |
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// | (LATENCY) | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
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// | | | | | Prefetch OFF |
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// +---------------------+------------------+------------------+------------------+------------------+
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// | 0 WS (1 CPU cycle) | 0 < HCLK ≤ 30 | 0 < HCLK ≤ 24 | 0 < HCLK ≤ 22 | 0 < HCLK ≤ 20 |
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// | 1 WS (2 CPU cycles) | 30 < HCLK ≤ 60 | 24 < HCLK ≤ 48 | 22 < HCLK ≤ 44 | 20 < HCLK ≤ 40 |
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// | 2 WS (3 CPU cycles) | 60 < HCLK ≤ 90 | 48 < HCLK ≤ 72 | 44 < HCLK ≤ 66 | 40 < HCLK ≤ 60 |
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// | 3 WS (4 CPU cycles) | 90 < HCLK ≤ 120 | 72 < HCLK ≤ 96 | 66 < HCLK ≤ 88 | 60 < HCLK ≤ 80 |
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// | 4 WS (5 CPU cycles) | 120 < HCLK ≤ 150 | 96 < HCLK ≤ 120 | 88 < HCLK ≤ 110 | 80 < HCLK ≤ 100 |
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// | 5 WS (6 CPU cycles) | 150 < HCLK ≤ 168 | 120 < HCLK ≤ 144 | 110 < HCLK ≤ 132 | 100 < HCLK ≤ 120 |
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// | 6 WS (7 CPU cycles) | | 144 < HCLK ≤ 168 | 132 < HCLK ≤ 154 | 120 < HCLK ≤ 140 |
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// | 7 WS (8 CPU cycles) | | | 154 < HCLK ≤ 168 | 140 < HCLK ≤ 160 |
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// +---------------------+------------------+------------------+------------------+------------------+
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// +-----------------------------------+
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// | Voltage range = 2.7V - 3.6V |
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// +----------------+------------------+
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// | Wait states | System Bus |
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// | (WS, LATENCY) | HCLK (MHz) |
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// +----------------+------------------+
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// | 0 WS, 1 cycle | 0 < HCLK ≤ 30 |
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// | 1 WS, 2 cycles | 30 < HCLK ≤ 60 |
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// | 2 WS, 3 cycles | 60 < HCLK ≤ 90 |
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// | 3 WS, 4 cycles | 90 < HCLK ≤ 120 |
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// | 4 WS, 5 cycles | 120 < HCLK ≤ 150 |
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// | 5 WS, 6 cycles | 150 < HCLK ≤ 168 |
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// +----------------+------------------+
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FLASH_LATENCY = 5 << stm32.FLASH_ACR_LATENCY_Pos // 5 WS (6 CPU cycles)
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// instruction cache, data cache, and prefetch
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@ -126,6 +126,8 @@ func initCLK() {
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// configure instruction/data caching, prefetch, and flash access wait states
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stm32.FLASH.ACR.Set(FLASH_OPTIONS | FLASH_LATENCY)
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for !stm32.FLASH.ACR.HasBits(FLASH_LATENCY) { // verify new wait states
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}
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// After a system reset, the HSI oscillator is selected as the system clock.
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// When a clock source is used directly or through PLL as the system clock, it
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@ -140,12 +142,14 @@ func initCLK() {
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// set CPU clock source to PLL
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stm32.RCC.CFGR.SetBits(SYSCLK_SRC_PLL)
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for !stm32.RCC.CFGR.HasBits(SYSCLK_SRC_PLL) {
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}
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// update PCKL1/2 and HCLK divisors
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stm32.RCC.CFGR.SetBits(RCC_DIV_PCLK1 | RCC_DIV_PCLK2 | RCC_DIV_HCLK)
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// verify system clock source is ready
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for !stm32.RCC.CFGR.HasBits(SYSCLK_STAT_PLL) {
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}
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// enable the CCM RAM clock
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stm32.RCC.AHB1ENR.SetBits(CLK_CCM_RAM)
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}
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@ -172,6 +176,12 @@ func initTIM() {
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tim7.Enable()
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}
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func initCOM() {
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if machine.NUM_UART_INTERFACES > 0 {
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machine.UART0.Configure(machine.UARTConfig{})
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}
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}
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var (
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// tick in milliseconds
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tickCount timeUnit
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@ -203,7 +213,7 @@ func timerSleep(ticks uint32) {
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timerWakeup.Set(0)
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stm32.TIM3.PSC.Set((PCLK1_FREQ_HZ*2)/10000 - 1) // 8399
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arr := (ticks / 100) - 1 // convert from microseconds to 0.1 ms
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arr := (ticks / 100) - 1 // microseconds to 0.1 ms
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if arr == 0 {
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arr = 1 // avoid blocking
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}
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@ -233,4 +243,6 @@ func handleTIM7(interrupt.Interrupt) {
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}
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}
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func putchar(c byte) {}
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func putchar(c byte) {
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machine.UART0.WriteByte(c)
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}
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