nucleol552ze: implementation with CLOCK, LED, and UART
Этот коммит содержится в:
Kenneth Bell
deadprogram
родитель
801bd2a7ff
коммит
af02c09b56
14 изменённых файлов: 682 добавлений и 5 удалений
2
Makefile
2
Makefile
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@ -341,6 +341,8 @@ smoketest:
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@$(MD5SUM) test.hex
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$(TINYGO) build -size short -o test.hex -target=nucleo-f722ze examples/blinky1
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@$(MD5SUM) test.hex
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$(TINYGO) build -size short -o test.hex -target=nucleo-l552ze examples/blinky1
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@$(MD5SUM) test.hex
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$(TINYGO) build -size short -o test.hex -target=p1am-100 examples/blinky1
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@$(MD5SUM) test.hex
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# test pwm
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45
src/machine/board_nucleol552ze.go
Обычный файл
45
src/machine/board_nucleol552ze.go
Обычный файл
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@ -0,0 +1,45 @@
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// +build nucleol552ze
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package machine
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import (
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"device/stm32"
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"runtime/interrupt"
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)
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const (
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LED = LED_BUILTIN
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LED_BUILTIN = LED_GREEN
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LED_GREEN = PC7
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LED_BLUE = PB7
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LED_RED = PA9
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)
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const (
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BUTTON = BUTTON_USER
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BUTTON_USER = PC13
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)
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// UART pins
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const (
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// PG7 and PG8 are connected to the ST-Link Virtual Com Port (VCP)
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UART_TX_PIN = PG7
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UART_RX_PIN = PG8
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UART_ALT_FN = 8 // GPIO_AF8_LPUART1
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)
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var (
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// LPUART1 is the hardware serial port connected to the onboard ST-LINK
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// debugger to be exposed as virtual COM port over USB on Nucleo boards.
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// Both UART0 and UART1 refer to LPUART1.
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UART0 = UART{
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Buffer: NewRingBuffer(),
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Bus: stm32.LPUART1,
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AltFuncSelector: UART_ALT_FN,
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}
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UART1 = &UART0
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)
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func init() {
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UART0.Interrupt = interrupt.New(stm32.IRQ_LPUART1, UART0.handleInterrupt)
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}
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@ -1,4 +1,4 @@
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// +build avr nrf sam stm32,!stm32f407,!stm32f7x2,!stm32l0 fe310 k210
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// +build avr nrf sam stm32,!stm32f407,!stm32f7x2,!stm32l5x2,!stm32l0 fe310 k210
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package machine
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@ -1,4 +1,4 @@
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// +build stm32,!stm32f103,!stm32f407,!stm32f7x2,!stm32l0
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// +build stm32,!stm32f103,!stm32f407,!stm32f7x2,!stm32l5x2,!stm32l0
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package machine
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62
src/machine/machine_stm32_l5_uart.go
Обычный файл
62
src/machine/machine_stm32_l5_uart.go
Обычный файл
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@ -0,0 +1,62 @@
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// +build stm32,stm32l5x2
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package machine
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// Peripheral abstraction layer for UARTs on the stm32 family.
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import (
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"device/stm32"
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"runtime/interrupt"
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"unsafe"
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)
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// Configure the UART.
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func (uart UART) Configure(config UARTConfig) {
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// Default baud rate to 115200.
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if config.BaudRate == 0 {
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config.BaudRate = 115200
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}
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// Set the GPIO pins to defaults if they're not set
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if config.TX == 0 && config.RX == 0 {
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config.TX = UART_TX_PIN
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config.RX = UART_RX_PIN
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}
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// Enable USART clock
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enableAltFuncClock(unsafe.Pointer(uart.Bus))
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uart.configurePins(config)
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// Set baud rate
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uart.SetBaudRate(config.BaudRate)
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// Enable USART port, tx, rx and rx interrupts
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uart.Bus.CR1.Set(stm32.USART_CR1_TE | stm32.USART_CR1_RE | stm32.USART_CR1_RXNEIE | stm32.USART_CR1_UE)
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// Enable RX IRQ
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uart.Interrupt.SetPriority(0xc0)
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uart.Interrupt.Enable()
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}
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// handleInterrupt should be called from the appropriate interrupt handler for
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// this UART instance.
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func (uart *UART) handleInterrupt(interrupt.Interrupt) {
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uart.Receive(byte((uart.Bus.RDR.Get() & 0xFF)))
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}
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// SetBaudRate sets the communication speed for the UART. Defer to chip-specific
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// routines for calculation
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func (uart UART) SetBaudRate(br uint32) {
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divider := uart.getBaudRateDivisor(br)
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uart.Bus.BRR.Set(divider)
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}
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// WriteByte writes a byte of data to the UART.
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func (uart UART) WriteByte(c byte) error {
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uart.Bus.TDR.Set(uint32(c))
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for !uart.Bus.ISR.HasBits(stm32.USART_ISR_TXE) {
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}
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return nil
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}
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@ -1,4 +1,4 @@
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// +build stm32,!stm32f7x2
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// +build stm32,!stm32f7x2,!stm32l5x2
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package machine
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@ -1,4 +1,4 @@
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// +build stm32,!stm32f7,!stm32l0
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// +build stm32,!stm32f7,!stm32l5x2,!stm32l0
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package machine
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253
src/machine/machine_stm32l5.go
Обычный файл
253
src/machine/machine_stm32l5.go
Обычный файл
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@ -0,0 +1,253 @@
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// +build stm32l5
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package machine
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// Peripheral abstraction layer for the stm32l5
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import (
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"device/stm32"
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"unsafe"
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)
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const (
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PA0 = portA + 0
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PA1 = portA + 1
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PA2 = portA + 2
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PA3 = portA + 3
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PA4 = portA + 4
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PA5 = portA + 5
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PA6 = portA + 6
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PA7 = portA + 7
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PA8 = portA + 8
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PA9 = portA + 9
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PA10 = portA + 10
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PA11 = portA + 11
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PA12 = portA + 12
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PA13 = portA + 13
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PA14 = portA + 14
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PA15 = portA + 15
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PB0 = portB + 0
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PB1 = portB + 1
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PB2 = portB + 2
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PB3 = portB + 3
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PB4 = portB + 4
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PB5 = portB + 5
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PB6 = portB + 6
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PB7 = portB + 7
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PB8 = portB + 8
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PB9 = portB + 9
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PB10 = portB + 10
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PB11 = portB + 11
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PB12 = portB + 12
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PB13 = portB + 13
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PB14 = portB + 14
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PB15 = portB + 15
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PC0 = portC + 0
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PC1 = portC + 1
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PC2 = portC + 2
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PC3 = portC + 3
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PC4 = portC + 4
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PC5 = portC + 5
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PC6 = portC + 6
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PC7 = portC + 7
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PC8 = portC + 8
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PC9 = portC + 9
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PC10 = portC + 10
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PC11 = portC + 11
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PC12 = portC + 12
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PC13 = portC + 13
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PC14 = portC + 14
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PC15 = portC + 15
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PD0 = portD + 0
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PD1 = portD + 1
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PD2 = portD + 2
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PD3 = portD + 3
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PD4 = portD + 4
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PD5 = portD + 5
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PD6 = portD + 6
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PD7 = portD + 7
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PD8 = portD + 8
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PD9 = portD + 9
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PD10 = portD + 10
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PD11 = portD + 11
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PD12 = portD + 12
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PD13 = portD + 13
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PD14 = portD + 14
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PD15 = portD + 15
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PE0 = portE + 0
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PE1 = portE + 1
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PE2 = portE + 2
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PE3 = portE + 3
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PE4 = portE + 4
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PE5 = portE + 5
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PE6 = portE + 6
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PE7 = portE + 7
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PE8 = portE + 8
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PE9 = portE + 9
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PE10 = portE + 10
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PE11 = portE + 11
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PE12 = portE + 12
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PE13 = portE + 13
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PE14 = portE + 14
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PE15 = portE + 15
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PF0 = portF + 0
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PF1 = portF + 1
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PF2 = portF + 2
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PF3 = portF + 3
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PF4 = portF + 4
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PF5 = portF + 5
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PF6 = portF + 6
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PF7 = portF + 7
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PF8 = portF + 8
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PF9 = portF + 9
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PF10 = portF + 10
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PF11 = portF + 11
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PF12 = portF + 12
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PF13 = portF + 13
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PF14 = portF + 14
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PF15 = portF + 15
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PG0 = portG + 0
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PG1 = portG + 1
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PG2 = portG + 2
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PG3 = portG + 3
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PG4 = portG + 4
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PG5 = portG + 5
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PG6 = portG + 6
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PG7 = portG + 7
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PG8 = portG + 8
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PG9 = portG + 9
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PG10 = portG + 10
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PG11 = portG + 11
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PG12 = portG + 12
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PG13 = portG + 13
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PG14 = portG + 14
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PG15 = portG + 15
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PH0 = portH + 0
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PH1 = portH + 1
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)
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func (p Pin) getPort() *stm32.GPIO_Type {
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switch p / 16 {
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case 0:
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return stm32.GPIOA
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case 1:
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return stm32.GPIOB
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case 2:
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return stm32.GPIOC
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case 3:
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return stm32.GPIOD
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case 4:
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return stm32.GPIOE
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case 5:
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return stm32.GPIOF
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case 6:
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return stm32.GPIOG
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case 7:
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return stm32.GPIOH
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default:
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panic("machine: unknown port")
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}
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}
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// enableClock enables the clock for this desired GPIO port.
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func (p Pin) enableClock() {
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switch p / 16 {
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case 0:
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stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOAEN)
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||||
case 1:
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||||
stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOBEN)
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case 2:
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stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOCEN)
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case 3:
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||||
stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIODEN)
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||||
case 4:
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||||
stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOEEN)
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||||
case 5:
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||||
stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOFEN)
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||||
case 6:
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||||
stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOGEN)
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||||
case 7:
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||||
stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOHEN)
|
||||
default:
|
||||
panic("machine: unknown port")
|
||||
}
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||||
}
|
||||
|
||||
// Enable peripheral clock
|
||||
func enableAltFuncClock(bus unsafe.Pointer) {
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||||
switch bus {
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||||
case unsafe.Pointer(stm32.DAC): // DAC interface clock enable
|
||||
stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_DAC1EN)
|
||||
case unsafe.Pointer(stm32.PWR): // Power interface clock enable
|
||||
stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_PWREN)
|
||||
case unsafe.Pointer(stm32.I2C3): // I2C3 clock enable
|
||||
stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_I2C3EN)
|
||||
case unsafe.Pointer(stm32.I2C2): // I2C2 clock enable
|
||||
stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_I2C2EN)
|
||||
case unsafe.Pointer(stm32.I2C1): // I2C1 clock enable
|
||||
stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_I2C1EN)
|
||||
case unsafe.Pointer(stm32.UART5): // UART5 clock enable
|
||||
stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_UART5EN)
|
||||
case unsafe.Pointer(stm32.UART4): // UART4 clock enable
|
||||
stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_UART4EN)
|
||||
case unsafe.Pointer(stm32.USART3): // USART3 clock enable
|
||||
stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_USART3EN)
|
||||
case unsafe.Pointer(stm32.USART2): // USART2 clock enable
|
||||
stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_USART2EN)
|
||||
case unsafe.Pointer(stm32.SPI3): // SPI3 clock enable
|
||||
stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_SP3EN)
|
||||
case unsafe.Pointer(stm32.SPI2): // SPI2 clock enable
|
||||
stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_SPI2EN)
|
||||
case unsafe.Pointer(stm32.WWDG): // Window watchdog clock enable
|
||||
stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_WWDGEN)
|
||||
case unsafe.Pointer(stm32.TIM7): // TIM7 clock enable
|
||||
stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM7EN)
|
||||
case unsafe.Pointer(stm32.TIM6): // TIM6 clock enable
|
||||
stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM6EN)
|
||||
case unsafe.Pointer(stm32.TIM5): // TIM5 clock enable
|
||||
stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM5EN)
|
||||
case unsafe.Pointer(stm32.TIM4): // TIM4 clock enable
|
||||
stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM4EN)
|
||||
case unsafe.Pointer(stm32.TIM3): // TIM3 clock enable
|
||||
stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM3EN)
|
||||
case unsafe.Pointer(stm32.TIM2): // TIM2 clock enable
|
||||
stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM2EN)
|
||||
|
||||
case unsafe.Pointer(stm32.UCPD1): // UCPD1 clock enable
|
||||
stm32.RCC.APB1ENR2.SetBits(stm32.RCC_APB1ENR2_UCPD1EN)
|
||||
case unsafe.Pointer(stm32.FDCAN1): // FDCAN1 clock enable
|
||||
stm32.RCC.APB1ENR2.SetBits(stm32.RCC_APB1ENR2_FDCAN1EN)
|
||||
case unsafe.Pointer(stm32.LPTIM3): // LPTIM3 clock enable
|
||||
stm32.RCC.APB1ENR2.SetBits(stm32.RCC_APB1ENR2_LPTIM3EN)
|
||||
case unsafe.Pointer(stm32.LPTIM2): // LPTIM2 clock enable
|
||||
stm32.RCC.APB1ENR2.SetBits(stm32.RCC_APB1ENR2_LPTIM2EN)
|
||||
case unsafe.Pointer(stm32.I2C4): // I2C4 clock enable
|
||||
stm32.RCC.APB1ENR2.SetBits(stm32.RCC_APB1ENR2_I2C4EN)
|
||||
case unsafe.Pointer(stm32.LPUART1): // LPUART1 clock enable
|
||||
stm32.RCC.APB1ENR2.SetBits(stm32.RCC_APB1ENR2_LPUART1EN)
|
||||
|
||||
case unsafe.Pointer(stm32.TIM17): // TIM17 clock enable
|
||||
stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM17EN)
|
||||
case unsafe.Pointer(stm32.TIM16): // TIM16 clock enable
|
||||
stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM16EN)
|
||||
case unsafe.Pointer(stm32.TIM15): // TIM15 clock enable
|
||||
stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM15EN)
|
||||
case unsafe.Pointer(stm32.SYSCFG): // System configuration controller clock enable
|
||||
stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SYSCFGEN)
|
||||
case unsafe.Pointer(stm32.SPI1): // SPI1 clock enable
|
||||
stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SPI1EN)
|
||||
case unsafe.Pointer(stm32.USART1): // USART1 clock enable
|
||||
stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_USART1EN)
|
||||
case unsafe.Pointer(stm32.TIM8): // TIM8 clock enable
|
||||
stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM8EN)
|
||||
case unsafe.Pointer(stm32.TIM1): // TIM1 clock enable
|
||||
stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM1EN)
|
||||
}
|
||||
}
|
||||
42
src/machine/machine_stm32l5x2.go
Обычный файл
42
src/machine/machine_stm32l5x2.go
Обычный файл
|
|
@ -0,0 +1,42 @@
|
|||
// +build stm32l5x2
|
||||
|
||||
package machine
|
||||
|
||||
// Peripheral abstraction layer for the stm32f407
|
||||
|
||||
import (
|
||||
"device/stm32"
|
||||
"runtime/interrupt"
|
||||
)
|
||||
|
||||
func CPUFrequency() uint32 {
|
||||
return 110000000
|
||||
}
|
||||
|
||||
//---------- UART related types and code
|
||||
|
||||
// UART representation
|
||||
type UART struct {
|
||||
Buffer *RingBuffer
|
||||
Bus *stm32.USART_Type
|
||||
Interrupt interrupt.Interrupt
|
||||
AltFuncSelector stm32.AltFunc
|
||||
}
|
||||
|
||||
// Configure the UART.
|
||||
func (uart UART) configurePins(config UARTConfig) {
|
||||
if config.RX.getPort() == stm32.GPIOG || config.TX.getPort() == stm32.GPIOG {
|
||||
// Enable VDDIO2 power supply, which is an independant power supply for the PGx pins
|
||||
stm32.PWR.CR2.SetBits(stm32.PWR_CR2_IOSV)
|
||||
}
|
||||
|
||||
// enable the alternate functions on the TX and RX pins
|
||||
config.TX.ConfigureAltFunc(PinConfig{Mode: PinModeUARTTX}, uart.AltFuncSelector)
|
||||
config.RX.ConfigureAltFunc(PinConfig{Mode: PinModeUARTRX}, uart.AltFuncSelector)
|
||||
}
|
||||
|
||||
// UART baudrate calc based on the bus and clockspeed
|
||||
// NOTE: keep this in sync with the runtime/runtime_stm32l5x2.go clock init code
|
||||
func (uart UART) getBaudRateDivisor(baudRate uint32) uint32 {
|
||||
return 256 * (CPUFrequency() / baudRate)
|
||||
}
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
// +build !baremetal sam stm32,!stm32f7x2 fe310 k210 atmega
|
||||
// +build !baremetal sam stm32,!stm32f7x2,!stm32l5x2 fe310 k210 atmega
|
||||
|
||||
package machine
|
||||
|
||||
|
|
|
|||
243
src/runtime/runtime_stm32l5x2.go
Обычный файл
243
src/runtime/runtime_stm32l5x2.go
Обычный файл
|
|
@ -0,0 +1,243 @@
|
|||
// +build stm32,stm32l5x2
|
||||
|
||||
package runtime
|
||||
|
||||
import (
|
||||
"device/arm"
|
||||
"device/stm32"
|
||||
"machine"
|
||||
"runtime/interrupt"
|
||||
"runtime/volatile"
|
||||
)
|
||||
|
||||
func init() {
|
||||
initCLK()
|
||||
initTIM15()
|
||||
machine.UART0.Configure(machine.UARTConfig{})
|
||||
initTIM16()
|
||||
}
|
||||
|
||||
func putchar(c byte) {
|
||||
machine.UART0.WriteByte(c)
|
||||
}
|
||||
|
||||
const (
|
||||
HSE_STARTUP_TIMEOUT = 0x0500
|
||||
PLL_M = 1
|
||||
PLL_N = 55
|
||||
PLL_P = 7 // RCC_PLLP_DIV7
|
||||
PLL_Q = 2 // RCC_PLLQ_DIV2
|
||||
PLL_R = 2 // RCC_PLLR_DIV2
|
||||
)
|
||||
|
||||
/*
|
||||
clock settings
|
||||
+-------------+-----------+
|
||||
| LSE | 32.768khz |
|
||||
| SYSCLK | 110mhz |
|
||||
| HCLK | 110mhz |
|
||||
| APB1(PCLK1) | 110mhz |
|
||||
| APB2(PCLK2) | 110mhz |
|
||||
+-------------+-----------+
|
||||
*/
|
||||
func initCLK() {
|
||||
|
||||
// PWR_CLK_ENABLE
|
||||
stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_PWREN)
|
||||
_ = stm32.RCC.APB1ENR1.Get()
|
||||
|
||||
// PWR_VOLTAGESCALING_CONFIG
|
||||
stm32.PWR.CR1.ReplaceBits(0, stm32.PWR_CR1_VOS_Msk, 0)
|
||||
_ = stm32.PWR.CR1.Get()
|
||||
|
||||
// Initialize the High-Speed External Oscillator
|
||||
initOsc()
|
||||
|
||||
// Set flash wait states (min 5 latency units) based on clock
|
||||
if (stm32.FLASH.ACR.Get() & 0xF) < 5 {
|
||||
stm32.FLASH.ACR.ReplaceBits(5, 0xF, 0)
|
||||
}
|
||||
|
||||
// Ensure HCLK does not exceed max during transition
|
||||
stm32.RCC.CFGR.ReplaceBits(8<<stm32.RCC_CFGR_HPRE_Pos, stm32.RCC_CFGR_HPRE_Msk, 0)
|
||||
|
||||
// Set SYSCLK source and wait
|
||||
// (3 = RCC_SYSCLKSOURCE_PLLCLK, 2=RCC_CFGR_SWS_Pos)
|
||||
stm32.RCC.CFGR.ReplaceBits(3, stm32.RCC_CFGR_SW_Msk, 0)
|
||||
for stm32.RCC.CFGR.Get()&(3<<2) != (3 << 2) {
|
||||
}
|
||||
|
||||
// Set HCLK
|
||||
// (0 = RCC_SYSCLKSOURCE_PLLCLK)
|
||||
stm32.RCC.CFGR.ReplaceBits(0, stm32.RCC_CFGR_HPRE_Msk, 0)
|
||||
|
||||
// Set flash wait states (max 5 latency units) based on clock
|
||||
if (stm32.FLASH.ACR.Get() & 0xF) > 5 {
|
||||
stm32.FLASH.ACR.ReplaceBits(5, 0xF, 0)
|
||||
}
|
||||
|
||||
// Set APB1 and APB2 clocks (0 = DIV1)
|
||||
stm32.RCC.CFGR.ReplaceBits(0, stm32.RCC_CFGR_PPRE1_Msk, 0)
|
||||
stm32.RCC.CFGR.ReplaceBits(0, stm32.RCC_CFGR_PPRE2_Msk, 0)
|
||||
}
|
||||
|
||||
func initOsc() {
|
||||
// Enable HSI, wait until ready
|
||||
stm32.RCC.CR.SetBits(stm32.RCC_CR_HSION)
|
||||
for !stm32.RCC.CR.HasBits(stm32.RCC_CR_HSIRDY) {
|
||||
}
|
||||
|
||||
// Disable Backup domain protection
|
||||
if !stm32.PWR.CR1.HasBits(stm32.PWR_CR1_DBP) {
|
||||
stm32.PWR.CR1.SetBits(stm32.PWR_CR1_DBP)
|
||||
for !stm32.PWR.CR1.HasBits(stm32.PWR_CR1_DBP) {
|
||||
}
|
||||
}
|
||||
|
||||
// Set LSE Drive to LOW
|
||||
stm32.RCC.BDCR.ReplaceBits(0, stm32.RCC_BDCR_LSEDRV_Msk, 0)
|
||||
|
||||
// Enable LSE, wait until ready
|
||||
stm32.RCC.BDCR.SetBits(stm32.RCC_BDCR_LSEON)
|
||||
for !stm32.RCC.BDCR.HasBits(stm32.RCC_BDCR_LSEON) {
|
||||
}
|
||||
|
||||
// Ensure LSESYS disabled
|
||||
stm32.RCC.BDCR.ClearBits(stm32.RCC_BDCR_LSESYSEN)
|
||||
for stm32.RCC.BDCR.HasBits(stm32.RCC_BDCR_LSESYSEN) {
|
||||
}
|
||||
|
||||
// Enable HSI48, wait until ready
|
||||
stm32.RCC.CRRCR.SetBits(stm32.RCC_CRRCR_HSI48ON)
|
||||
for !stm32.RCC.CRRCR.HasBits(stm32.RCC_CRRCR_HSI48ON) {
|
||||
}
|
||||
|
||||
// Disable the PLL, wait until disabled
|
||||
stm32.RCC.CR.ClearBits(stm32.RCC_CR_PLLON)
|
||||
for stm32.RCC.CR.HasBits(stm32.RCC_CR_PLLRDY) {
|
||||
}
|
||||
|
||||
// Configure the PLL
|
||||
stm32.RCC.PLLCFGR.ReplaceBits(
|
||||
(1)| // 1 = RCC_PLLSOURCE_MSI
|
||||
(PLL_M-1)<<stm32.RCC_PLLCFGR_PLLM_Pos|
|
||||
(PLL_N<<stm32.RCC_PLLCFGR_PLLN_Pos)|
|
||||
(((PLL_Q>>1)-1)<<stm32.RCC_PLLCFGR_PLLQ_Pos)|
|
||||
(((PLL_R>>1)-1)<<stm32.RCC_PLLCFGR_PLLR_Pos)|
|
||||
(PLL_P<<stm32.RCC_PLLCFGR_PLLPDIV_Pos),
|
||||
stm32.RCC_PLLCFGR_PLLSRC_Msk|stm32.RCC_PLLCFGR_PLLM_Msk|
|
||||
stm32.RCC_PLLCFGR_PLLN_Msk|stm32.RCC_PLLCFGR_PLLP_Msk|
|
||||
stm32.RCC_PLLCFGR_PLLR_Msk|stm32.RCC_PLLCFGR_PLLPDIV_Msk,
|
||||
0)
|
||||
|
||||
// Enable the PLL and PLL System Clock Output, wait until ready
|
||||
stm32.RCC.CR.SetBits(stm32.RCC_CR_PLLON)
|
||||
stm32.RCC.PLLCFGR.SetBits(stm32.RCC_PLLCFGR_PLLREN) // = RCC_PLL_SYSCLK
|
||||
for !stm32.RCC.CR.HasBits(stm32.RCC_CR_PLLRDY) {
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
var (
|
||||
// tick in milliseconds
|
||||
tickCount timeUnit
|
||||
)
|
||||
|
||||
var timerWakeup volatile.Register8
|
||||
|
||||
func ticksToNanoseconds(ticks timeUnit) int64 {
|
||||
return int64(ticks) * 1000
|
||||
}
|
||||
|
||||
func nanosecondsToTicks(ns int64) timeUnit {
|
||||
return timeUnit(ns / 1000)
|
||||
}
|
||||
|
||||
// Enable the TIM15 clock.(sleep count)
|
||||
func initTIM15() {
|
||||
stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM15EN)
|
||||
|
||||
intr := interrupt.New(stm32.IRQ_TIM15, handleTIM15)
|
||||
intr.SetPriority(0xc3)
|
||||
intr.Enable()
|
||||
}
|
||||
|
||||
// Enable the TIM16 clock.(tick count)
|
||||
func initTIM16() {
|
||||
stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM16EN)
|
||||
|
||||
// CK_INT = APB1 = 110mhz
|
||||
stm32.TIM16.PSC.Set(110000000/10000 - 1) // 110mhz to 10khz(0.1ms)
|
||||
stm32.TIM16.ARR.Set(10 - 1) // interrupt per 1ms
|
||||
|
||||
// Enable the hardware interrupt.
|
||||
stm32.TIM16.DIER.SetBits(stm32.TIM_DIER_UIE)
|
||||
|
||||
// Enable the timer.
|
||||
stm32.TIM16.CR1.SetBits(stm32.TIM_CR1_CEN)
|
||||
|
||||
intr := interrupt.New(stm32.IRQ_TIM16, handleTIM16)
|
||||
intr.SetPriority(0xc1)
|
||||
intr.Enable()
|
||||
}
|
||||
|
||||
const asyncScheduler = false
|
||||
|
||||
// sleepTicks should sleep for specific number of microseconds.
|
||||
func sleepTicks(d timeUnit) {
|
||||
timerSleep(uint32(d))
|
||||
}
|
||||
|
||||
// number of ticks (microseconds) since start.
|
||||
func ticks() timeUnit {
|
||||
// milliseconds to microseconds
|
||||
return tickCount * 1000
|
||||
}
|
||||
|
||||
// ticks are in microseconds
|
||||
func timerSleep(ticks uint32) {
|
||||
timerWakeup.Set(0)
|
||||
|
||||
// CK_INT = APB1 = 110mhz
|
||||
// prescale counter down from 110mhz to 10khz aka 0.1 ms frequency.
|
||||
stm32.TIM15.PSC.Set(110000000/10000 - 1)
|
||||
|
||||
// set duty aka duration
|
||||
arr := (ticks / 100) - 1 // convert from microseconds to 0.1 ms
|
||||
if arr == 0 {
|
||||
arr = 1 // avoid blocking
|
||||
}
|
||||
stm32.TIM15.ARR.Set(arr)
|
||||
|
||||
// Enable the hardware interrupt.
|
||||
stm32.TIM15.DIER.SetBits(stm32.TIM_DIER_UIE)
|
||||
|
||||
// Enable the timer.
|
||||
stm32.TIM15.CR1.SetBits(stm32.TIM_CR1_CEN)
|
||||
|
||||
// wait till timer wakes up
|
||||
for timerWakeup.Get() == 0 {
|
||||
arm.Asm("wfi")
|
||||
}
|
||||
}
|
||||
|
||||
func handleTIM15(interrupt.Interrupt) {
|
||||
if stm32.TIM15.SR.HasBits(stm32.TIM_SR_UIF) {
|
||||
// Disable the timer.
|
||||
stm32.TIM15.CR1.ClearBits(stm32.TIM_CR1_CEN)
|
||||
|
||||
// clear the update flag
|
||||
stm32.TIM15.SR.ClearBits(stm32.TIM_SR_UIF)
|
||||
|
||||
// timer was triggered
|
||||
timerWakeup.Set(1)
|
||||
}
|
||||
}
|
||||
|
||||
func handleTIM16(interrupt.Interrupt) {
|
||||
if stm32.TIM16.SR.HasBits(stm32.TIM_SR_UIF) {
|
||||
// clear the update flag
|
||||
stm32.TIM16.SR.ClearBits(stm32.TIM_SR_UIF)
|
||||
tickCount++
|
||||
}
|
||||
}
|
||||
9
targets/cortex-m33.json
Обычный файл
9
targets/cortex-m33.json
Обычный файл
|
|
@ -0,0 +1,9 @@
|
|||
{
|
||||
"inherits": ["cortex-m"],
|
||||
"llvm-target": "armv7m-none-eabi",
|
||||
"cflags": [
|
||||
"--target=armv7m-none-eabi",
|
||||
"-mfloat-abi=soft",
|
||||
"-Qunused-arguments"
|
||||
]
|
||||
}
|
||||
11
targets/nucleo-l552ze.json
Обычный файл
11
targets/nucleo-l552ze.json
Обычный файл
|
|
@ -0,0 +1,11 @@
|
|||
{
|
||||
"inherits": ["cortex-m33"],
|
||||
"build-tags": ["nucleol552ze", "stm32l552", "stm32l5x2", "stm32l5", "stm32"],
|
||||
"linkerscript": "targets/stm32l5x2xe.ld",
|
||||
"extra-files": [
|
||||
"src/device/stm32/stm32l552.s"
|
||||
],
|
||||
"flash-method": "openocd",
|
||||
"openocd-interface": "stlink-v2-1",
|
||||
"openocd-target": "stm32l5x"
|
||||
}
|
||||
10
targets/stm32l5x2xe.ld
Обычный файл
10
targets/stm32l5x2xe.ld
Обычный файл
|
|
@ -0,0 +1,10 @@
|
|||
|
||||
MEMORY
|
||||
{
|
||||
FLASH_TEXT (rx) : ORIGIN = 0x08000000, LENGTH = 512K
|
||||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 192K
|
||||
}
|
||||
|
||||
_stack_size = 4K;
|
||||
|
||||
INCLUDE "targets/arm.ld"
|
||||
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