From b258f3424b59736455290dc4257128cc4fa7e907 Mon Sep 17 00:00:00 2001 From: Ayke van Laethem Date: Fri, 10 Jan 2020 13:18:10 +0100 Subject: [PATCH] riscv: print exception PC and code This can be useful for debugging critical bugs in code. I haven't added human-readable exceptions (such as "illegal instruction" or "stack overflow") yet, they can be added when they happen in practice (to avoid increasing code size too much). --- src/runtime/runtime_fe310.go | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/src/runtime/runtime_fe310.go b/src/runtime/runtime_fe310.go index c3a10bf3..14a00563 100644 --- a/src/runtime/runtime_fe310.go +++ b/src/runtime/runtime_fe310.go @@ -69,8 +69,10 @@ func handleInterrupt() { riscv.MIE.ClearBits(1 << 7) // MTIE bit } } else { - // TODO: handle exceptions in a similar was as HardFault is handled on - // Cortex-M (by printing an error message with instruction address). + // Topmost bit is clear, so it is an exception of some sort. + // We could implement support for unsupported instructions here (such as + // misaligned loads). However, for now we'll just print a fatal error. + handleException(code) } } @@ -151,3 +153,17 @@ func sleepTicks(d timeUnit) { riscv.Asm("wfi") } } + +// handleException is called from the interrupt handler for any exception. +// Exceptions can be things like illegal instructions, invalid memory +// read/write, and similar issues. +func handleException(code uint) { + // For a list of exception codes, see: + // https://content.riscv.org/wp-content/uploads/2019/08/riscv-privileged-20190608-1.pdf#page=49 + print("fatal error: exception with mcause=") + print(code) + print(" pc=") + print(riscv.MEPC.Get()) + println() + abort() +}