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3 изменённых файлов: 319 добавлений и 2 удалений
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@ -237,6 +237,8 @@ var (
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}
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)
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// #==================================================================#
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// | SPI |
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// #===========#==========#===============#===========================#
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// | Interface | Hardware | Clock(Freq) | SDI/SDO/SCK/CS : Alt |
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// #===========#==========#===============#=================-=========#
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@ -261,6 +263,70 @@ const (
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SPI3_CS_PIN = D36
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)
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var (
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SPI0 = SPI1 // SPI0 is an alias of SPI1 (LPSPI4)
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SPI1 = &_SPI1
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_SPI1 = SPI{
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Bus: nxp.LPSPI4,
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muxSDI: muxSelect{ // D12 (PB1 [B0_01])
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mux: nxp.IOMUXC_LPSPI4_SDI_SELECT_INPUT_DAISY_GPIO_B0_01_ALT3,
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sel: &nxp.IOMUXC.LPSPI4_SDI_SELECT_INPUT,
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},
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muxSDO: muxSelect{ // D11 (PB2 [B0_02])
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mux: nxp.IOMUXC_LPSPI4_SDO_SELECT_INPUT_DAISY_GPIO_B0_02_ALT3,
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sel: &nxp.IOMUXC.LPSPI4_SDO_SELECT_INPUT,
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},
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muxSCK: muxSelect{ // D13 (PB3 [B0_03])
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mux: nxp.IOMUXC_LPSPI4_SCK_SELECT_INPUT_DAISY_GPIO_B0_03_ALT3,
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sel: &nxp.IOMUXC.LPSPI4_SCK_SELECT_INPUT,
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},
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muxCS: muxSelect{ // D10 (PB0 [B0_00])
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mux: nxp.IOMUXC_LPSPI4_PCS0_SELECT_INPUT_DAISY_GPIO_B0_00_ALT3,
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sel: &nxp.IOMUXC.LPSPI4_PCS0_SELECT_INPUT,
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},
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}
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SPI2 = &_SPI2
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_SPI2 = SPI{
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Bus: nxp.LPSPI3,
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muxSDI: muxSelect{ // D1 (PA2 [AD_B0_02])
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mux: nxp.IOMUXC_LPSPI3_SDI_SELECT_INPUT_DAISY_GPIO_AD_B0_02_ALT7,
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sel: &nxp.IOMUXC.LPSPI3_SDI_SELECT_INPUT,
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},
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muxSDO: muxSelect{ // D26 (PA30 [AD_B1_14])
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mux: nxp.IOMUXC_LPSPI3_SDO_SELECT_INPUT_DAISY_GPIO_AD_B1_14_ALT2,
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sel: &nxp.IOMUXC.LPSPI3_SDO_SELECT_INPUT,
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},
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muxSCK: muxSelect{ // D27 (PA31 [AD_B1_15])
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mux: nxp.IOMUXC_LPSPI3_SCK_SELECT_INPUT_DAISY_GPIO_AD_B1_15,
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sel: &nxp.IOMUXC.LPSPI3_SCK_SELECT_INPUT,
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},
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muxCS: muxSelect{ // D0 (PA3 [AD_B0_03])
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mux: nxp.IOMUXC_LPSPI3_PCS0_SELECT_INPUT_DAISY_GPIO_AD_B0_03_ALT7,
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sel: &nxp.IOMUXC.LPSPI3_PCS0_SELECT_INPUT,
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},
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}
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SPI3 = &_SPI3
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_SPI3 = SPI{
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Bus: nxp.LPSPI1,
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muxSDI: muxSelect{ // D34 (PC15 [SD_B0_03])
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mux: nxp.IOMUXC_LPSPI1_SDI_SELECT_INPUT_DAISY_GPIO_SD_B0_03_ALT4,
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sel: &nxp.IOMUXC.LPSPI1_SDI_SELECT_INPUT,
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},
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muxSDO: muxSelect{ // D35 (PC14 [SD_B0_02])
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mux: nxp.IOMUXC_LPSPI1_SDO_SELECT_INPUT_DAISY_GPIO_SD_B0_02_ALT4,
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sel: &nxp.IOMUXC.LPSPI1_SDO_SELECT_INPUT,
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},
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muxSCK: muxSelect{ // D37 (PC12 [SD_B0_00])
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mux: nxp.IOMUXC_LPSPI1_SCK_SELECT_INPUT_DAISY_GPIO_SD_B0_00_ALT4,
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sel: &nxp.IOMUXC.LPSPI1_SCK_SELECT_INPUT,
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},
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muxCS: muxSelect{ // D36 (PC13 [SD_B0_01])
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mux: nxp.IOMUXC_LPSPI1_PCS0_SELECT_INPUT_DAISY_GPIO_SD_B0_01_ALT4,
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sel: &nxp.IOMUXC.LPSPI1_PCS0_SELECT_INPUT,
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},
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}
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)
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// #====================================================#
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// | I2C |
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// #===========#==========#=============#===============#
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251
src/machine/machine_mimxrt1062_spi.go
Обычный файл
251
src/machine/machine_mimxrt1062_spi.go
Обычный файл
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@ -0,0 +1,251 @@
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// +build mimxrt1062
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package machine
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// SPI peripheral abstraction layer for the MIMXRT1062
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import (
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"device/nxp"
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"errors"
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"unsafe"
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)
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// SPIConfig is used to store config info for SPI.
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type SPIConfig struct {
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Frequency uint32
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SDI Pin
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SDO Pin
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SCK Pin
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CS Pin
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LSBFirst bool
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Mode uint8
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}
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func (c SPIConfig) getPins() (di, do, ck, cs Pin) {
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if 0 == c.SDI && 0 == c.SDO && 0 == c.SCK && 0 == c.CS {
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// default pins if none specified
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return SPI_SDI_PIN, SPI_SDO_PIN, SPI_SCK_PIN, SPI_CS_PIN
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}
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return c.SDI, c.SDO, c.SCK, c.CS
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}
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type SPI struct {
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Bus *nxp.LPSPI_Type
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// these hold the input selector ("daisy chain") values that select which pins
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// are connected to the LPSPI device, and should be defined where the SPI
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// instance is declared (e.g., in the board definition). see the godoc
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// comments on type muxSelect for more details.
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muxSDI, muxSDO, muxSCK, muxCS muxSelect
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// these are copied from SPIConfig, during (*SPI).Configure(SPIConfig), and
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// should be considered read-only for internal reference (i.e., modifying them
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// will have no desirable effect).
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sdi, sdo, sck, cs Pin
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frequency uint32
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// auxiliary state data used internally
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configured bool
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}
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const (
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statusTxDataRequest = nxp.LPSPI_SR_TDF // Transmit data flag
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statusRxDataReady = nxp.LPSPI_SR_RDF // Receive data flag
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statusWordComplete = nxp.LPSPI_SR_WCF // Word Complete flag
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statusFrameComplete = nxp.LPSPI_SR_FCF // Frame Complete flag
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statusTransferComplete = nxp.LPSPI_SR_TCF // Transfer Complete flag
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statusTransmitError = nxp.LPSPI_SR_TEF // Transmit Error flag (FIFO underrun)
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statusReceiveError = nxp.LPSPI_SR_REF // Receive Error flag (FIFO overrun)
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statusDataMatch = nxp.LPSPI_SR_DMF // Data Match flag
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statusModuleBusy = nxp.LPSPI_SR_MBF // Module Busy flag
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statusAll = nxp.LPSPI_SR_TDF | nxp.LPSPI_SR_RDF |
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nxp.LPSPI_SR_WCF | nxp.LPSPI_SR_FCF | nxp.LPSPI_SR_TCF | nxp.LPSPI_SR_TEF |
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nxp.LPSPI_SR_REF | nxp.LPSPI_SR_DMF | nxp.LPSPI_SR_MBF
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)
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var (
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errSPINotConfigured = errors.New("SPI interface is not yet configured")
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)
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// Configure is intended to setup an SPI interface for transmit/receive.
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func (spi *SPI) Configure(config SPIConfig) {
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const defaultSpiFreq = 4000000 // 4 MHz
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// init pins
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spi.sdi, spi.sdo, spi.sck, spi.cs = config.getPins()
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// configure the mux and pad control registers
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spi.sdi.Configure(PinConfig{Mode: PinModeSPISDI})
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spi.sdo.Configure(PinConfig{Mode: PinModeSPISDO})
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spi.sck.Configure(PinConfig{Mode: PinModeSPICLK})
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spi.cs.Configure(PinConfig{Mode: PinModeSPICS})
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// configure the mux input selector
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spi.muxSDI.connect()
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spi.muxSDO.connect()
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spi.muxSCK.connect()
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spi.muxCS.connect()
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// software reset of LPSPI state registers
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spi.Bus.CR.SetBits(nxp.LPSPI_CR_RST)
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// also reset FIFOs (not performed by software reset above)
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spi.Bus.CR.SetBits(nxp.LPSPI_CR_RRF | nxp.LPSPI_CR_RTF)
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spi.Bus.CR.Set(0)
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// set controller mode, and input data is sampled on delayed SCK edge
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spi.Bus.CFGR1.Set(nxp.LPSPI_CFGR1_MASTER | nxp.LPSPI_CFGR1_SAMPLE)
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spi.frequency = config.Frequency
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if 0 == spi.frequency {
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spi.frequency = defaultSpiFreq
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}
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// configure LPSPI clock divisor and CS assertion delays
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div := spi.getClockDivisor(config.Frequency)
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ccr := (div << nxp.LPSPI_CCR_SCKDIV_Pos) & nxp.LPSPI_CCR_SCKDIV_Msk
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ccr |= ((div / 2) << nxp.LPSPI_CCR_DBT_Pos) & nxp.LPSPI_CCR_DBT_Msk
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ccr |= ((div / 2) << nxp.LPSPI_CCR_PCSSCK_Pos) & nxp.LPSPI_CCR_PCSSCK_Msk
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spi.Bus.CCR.Set(ccr)
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// 8-bit frame size (words)
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tcr := uint32(7)
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if config.LSBFirst {
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tcr |= nxp.LPSPI_TCR_LSBF
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}
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// set polarity and phase
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switch config.Mode {
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case Mode1:
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tcr |= nxp.LPSPI_TCR_CPHA
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case Mode2:
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tcr |= nxp.LPSPI_TCR_CPOL
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case Mode3:
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tcr |= nxp.LPSPI_TCR_CPOL
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tcr |= nxp.LPSPI_TCR_CPHA
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}
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spi.Bus.TCR.Set(tcr)
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// clear FIFO water marks
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spi.setWatermark(0, 0)
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// enable LPSPI module
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spi.Bus.CR.Set(nxp.LPSPI_CR_MEN)
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spi.configured = true
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}
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// Transfer writes/reads a single byte using the SPI interface.
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func (spi *SPI) Transfer(w byte) (byte, error) {
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if !spi.configured {
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return 0, errSPINotConfigured
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}
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const readTryMax = 10000
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for spi.Bus.SR.HasBits(statusModuleBusy) {
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} // wait for SPI busy bit to clear
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_, txFIFOSize := spi.getFIFOSize()
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spi.flushFIFO(true, true)
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spi.Bus.SR.Set(statusAll) // clear all status flags (W1C)
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// enable LPSPI module
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spi.Bus.CR.Set(nxp.LPSPI_CR_MEN)
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// TODO: unnecessary since we just flushed the FIFO?
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for { // wait for TX FIFO to not be full
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if _, txFIFO := spi.getFIFOCount(); txFIFO < txFIFOSize {
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break
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}
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}
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// write out byte to TX FIFO
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spi.Bus.TDR.Set(uint32(w))
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// try to read from RX FIFO if anything exists
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didRead := false
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data := byte(0)
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for i := 0; !didRead && (i < readTryMax); i++ {
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rxFIFO, _ := spi.getFIFOCount()
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didRead = rxFIFO > 0
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if didRead {
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data = byte(spi.Bus.RDR.Get())
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}
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}
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// if nothing was read, then wait for transfer complete flag to decide when
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// we are finished
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if !didRead {
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for !spi.Bus.SR.HasBits(nxp.LPSPI_SR_TCF) {
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} // wait for all transfers complete flag to set
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}
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return data, nil
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}
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func (spi *SPI) isHardwareCSPin(pin Pin) bool {
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switch unsafe.Pointer(spi.Bus) {
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case unsafe.Pointer(nxp.LPSPI1):
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return SPI1_CS_PIN == pin
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case unsafe.Pointer(nxp.LPSPI2):
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return SPI2_CS_PIN == pin
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case unsafe.Pointer(nxp.LPSPI3):
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return SPI3_CS_PIN == pin
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}
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return false
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}
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func (spi *SPI) hasHardwareCSPin() bool {
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return spi.isHardwareCSPin(spi.cs)
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}
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// getClockDivisor finds the SPI prescalar that minimizes the error between
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// requested frequency and possible frequencies available with the LPSPI clock.
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// this routine is based on Teensyduino (libraries/SPI/SPI.cpp):
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// `void SPIClass::setClockDivider_noInline(uint32_t clk)`
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func (spi *SPI) getClockDivisor(freq uint32) uint32 {
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const clock = 132000000 // LPSPI root clock frequency (PLL2)
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d := uint32(clock)
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if freq > 0 {
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d /= freq
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}
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if d > 0 && clock/d > freq {
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d++
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}
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if d > 257 {
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return 255
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}
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if d > 2 {
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return d - 2
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}
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return 0
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}
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func (spi *SPI) getFIFOSize() (rx, tx uint32) {
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param := spi.Bus.PARAM.Get()
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return uint32(1) << ((param & nxp.LPSPI_PARAM_RXFIFO_Msk) >> nxp.LPSPI_PARAM_RXFIFO_Pos),
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uint32(1) << ((param & nxp.LPSPI_PARAM_TXFIFO_Msk) >> nxp.LPSPI_PARAM_TXFIFO_Pos)
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}
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func (spi *SPI) getFIFOCount() (rx, tx uint32) {
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fsr := spi.Bus.FSR.Get()
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return (fsr & nxp.LPSPI_FSR_RXCOUNT_Msk) >> nxp.LPSPI_FSR_RXCOUNT_Pos,
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(fsr & nxp.LPSPI_FSR_TXCOUNT_Msk) >> nxp.LPSPI_FSR_TXCOUNT_Pos
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}
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func (spi *SPI) flushFIFO(rx, tx bool) {
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var flush uint32
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if rx {
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flush |= nxp.LPSPI_CR_RRF
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}
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if tx {
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flush |= nxp.LPSPI_CR_RTF
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}
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spi.Bus.CR.SetBits(flush)
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}
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func (spi *SPI) setWatermark(rx, tx uint32) {
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spi.Bus.FCR.Set(((rx << nxp.LPSPI_FCR_RXWATER_Pos) & nxp.LPSPI_FCR_RXWATER_Msk) |
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((tx << nxp.LPSPI_FCR_TXWATER_Pos) & nxp.LPSPI_FCR_TXWATER_Msk))
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}
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@ -1,5 +1,5 @@
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//go:build !baremetal || (stm32 && !stm32f7x2 && !stm32l5x2) || fe310 || k210 || atmega
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// +build !baremetal stm32,!stm32f7x2,!stm32l5x2 fe310 k210 atmega
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//go:build !baremetal || (stm32 && !stm32f7x2 && !stm32l5x2) || fe310 || k210 || (nxp && !mk66f18) || atmega
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// +build !baremetal stm32,!stm32f7x2,!stm32l5x2 fe310 k210 nxp,!mk66f18 atmega
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package machine
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