Add support for nucleol432 board
LED and UART are working
Этот коммит содержится в:
Kenneth Bell
Ron Evans
родитель
dc981ce509
коммит
c7bd5405c3
12 изменённых файлов: 557 добавлений и 5 удалений
2
Makefile
2
Makefile
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@ -343,6 +343,8 @@ smoketest:
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@$(MD5SUM) test.hex
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$(TINYGO) build -size short -o test.hex -target=nucleo-l552ze examples/blinky1
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@$(MD5SUM) test.hex
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$(TINYGO) build -size short -o test.hex -target=nucleo-l432kc examples/blinky1
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@$(MD5SUM) test.hex
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$(TINYGO) build -size short -o test.hex -target=p1am-100 examples/blinky1
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@$(MD5SUM) test.hex
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# test pwm
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46
src/machine/board_nucleol432kc.go
Обычный файл
46
src/machine/board_nucleol432kc.go
Обычный файл
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@ -0,0 +1,46 @@
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// +build nucleol432kc
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package machine
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import (
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"device/stm32"
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"runtime/interrupt"
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)
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const (
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LED = LED_BUILTIN
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LED_BUILTIN = LED_GREEN
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LED_GREEN = PB3
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)
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// UART pins
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const (
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// PA2 and PA15 are connected to the ST-Link Virtual Com Port (VCP)
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UART_TX_PIN = PA2
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UART_RX_PIN = PA15
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)
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// I2C pins
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const (
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// PB6 and PB7 are mapped to CN4 pin 7 and CN4 pin 8 respectively with the
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// default solder bridge settings
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I2C0_SCL_PIN = PB6
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I2C0_SDA_PIN = PB7
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)
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var (
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// USART2 is the hardware serial port connected to the onboard ST-LINK
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// debugger to be exposed as virtual COM port over USB on Nucleo boards.
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// Both UART0 and UART1 refer to USART2.
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UART0 = UART{
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Buffer: NewRingBuffer(),
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Bus: stm32.USART2,
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TxAltFuncSelector: 7,
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RxAltFuncSelector: 3,
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}
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UART1 = &UART0
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)
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func init() {
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UART0.Interrupt = interrupt.New(stm32.IRQ_USART2, UART0.handleInterrupt)
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}
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@ -1,4 +1,4 @@
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// +build avr nrf sam stm32,!stm32f7x2,!stm32l5x2,!stm32l0 fe310 k210
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// +build avr nrf sam stm32,!stm32f7x2,!stm32l5x2,!stm32l0,!stm32l4x2 fe310 k210
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package machine
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@ -1,4 +1,4 @@
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// +build stm32,!stm32f7x2,!stm32l5x2,!stm32l0
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// +build stm32,!stm32f7x2,!stm32l5x2,!stm32l0,!stm32l4x2
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package machine
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@ -1,4 +1,4 @@
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// +build stm32,!stm32f7x2,!stm32l5x2
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// +build stm32,!stm32f7x2,!stm32l5x2,!stm32l4x2
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package machine
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184
src/machine/machine_stm32l4.go
Обычный файл
184
src/machine/machine_stm32l4.go
Обычный файл
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@ -0,0 +1,184 @@
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// +build stm32l4
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package machine
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import (
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"device/stm32"
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"unsafe"
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)
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// Peripheral abstraction layer for the stm32l4
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const (
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PA0 = portA + 0
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PA1 = portA + 1
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PA2 = portA + 2
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PA3 = portA + 3
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PA4 = portA + 4
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PA5 = portA + 5
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PA6 = portA + 6
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PA7 = portA + 7
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PA8 = portA + 8
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PA9 = portA + 9
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PA10 = portA + 10
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PA11 = portA + 11
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PA12 = portA + 12
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PA13 = portA + 13
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PA14 = portA + 14
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PA15 = portA + 15
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PB0 = portB + 0
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PB1 = portB + 1
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PB2 = portB + 2
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PB3 = portB + 3
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PB4 = portB + 4
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PB5 = portB + 5
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PB6 = portB + 6
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PB7 = portB + 7
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PB8 = portB + 8
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PB9 = portB + 9
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PB10 = portB + 10
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PB11 = portB + 11
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PB12 = portB + 12
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PB13 = portB + 13
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PB14 = portB + 14
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PB15 = portB + 15
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PC0 = portC + 0
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PC1 = portC + 1
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PC2 = portC + 2
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PC3 = portC + 3
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PC4 = portC + 4
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PC5 = portC + 5
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PC6 = portC + 6
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PC7 = portC + 7
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PC8 = portC + 8
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PC9 = portC + 9
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PC10 = portC + 10
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PC11 = portC + 11
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PC12 = portC + 12
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PC13 = portC + 13
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PC14 = portC + 14
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PC15 = portC + 15
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PD0 = portD + 0
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PD1 = portD + 1
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PD2 = portD + 2
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PD3 = portD + 3
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PD4 = portD + 4
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PD5 = portD + 5
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PD6 = portD + 6
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PD7 = portD + 7
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PD8 = portD + 8
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PD9 = portD + 9
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PD10 = portD + 10
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PD11 = portD + 11
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PD12 = portD + 12
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PD13 = portD + 13
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PD14 = portD + 14
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PD15 = portD + 15
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PE0 = portE + 0
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PE1 = portE + 1
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PE2 = portE + 2
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PE3 = portE + 3
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PE4 = portE + 4
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PE5 = portE + 5
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PE6 = portE + 6
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PE7 = portE + 7
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PE8 = portE + 8
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PE9 = portE + 9
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PE10 = portE + 10
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PE11 = portE + 11
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PE12 = portE + 12
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PE13 = portE + 13
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PE14 = portE + 14
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PE15 = portE + 15
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)
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func (p Pin) getPort() *stm32.GPIO_Type {
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switch p / 16 {
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case 0:
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return stm32.GPIOA
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case 1:
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return stm32.GPIOB
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case 2:
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return stm32.GPIOC
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case 3:
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return stm32.GPIOD
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case 4:
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return stm32.GPIOE
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default:
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panic("machine: unknown port")
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}
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}
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// enableClock enables the clock for this desired GPIO port.
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func (p Pin) enableClock() {
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switch p / 16 {
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case 0:
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stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOAEN)
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case 1:
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stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOBEN)
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case 2:
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stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOCEN)
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case 3:
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stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIODEN)
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case 4:
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stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOEEN)
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default:
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panic("machine: unknown port")
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}
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}
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// Enable peripheral clock
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func enableAltFuncClock(bus unsafe.Pointer) {
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switch bus {
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case unsafe.Pointer(stm32.PWR): // Power interface clock enable
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stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_PWREN)
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case unsafe.Pointer(stm32.I2C3): // I2C3 clock enable
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stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_I2C3EN)
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case unsafe.Pointer(stm32.I2C2): // I2C2 clock enable
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stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_I2C2EN)
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case unsafe.Pointer(stm32.I2C1): // I2C1 clock enable
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stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_I2C1EN)
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case unsafe.Pointer(stm32.UART4): // UART4 clock enable
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stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_UART4EN)
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case unsafe.Pointer(stm32.USART3): // USART3 clock enable
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stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_USART3EN)
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case unsafe.Pointer(stm32.USART2): // USART2 clock enable
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stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_USART2EN)
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case unsafe.Pointer(stm32.SPI3): // SPI3 clock enable
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stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_SPI3EN)
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case unsafe.Pointer(stm32.SPI2): // SPI2 clock enable
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stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_SPI2EN)
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case unsafe.Pointer(stm32.WWDG): // Window watchdog clock enable
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stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_WWDGEN)
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case unsafe.Pointer(stm32.TIM7): // TIM7 clock enable
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stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM7EN)
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case unsafe.Pointer(stm32.TIM6): // TIM6 clock enable
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stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM6EN)
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case unsafe.Pointer(stm32.TIM3): // TIM3 clock enable
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stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM3EN)
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case unsafe.Pointer(stm32.TIM2): // TIM2 clock enable
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stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM2EN)
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case unsafe.Pointer(stm32.LPTIM2): // LPTIM2 clock enable
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stm32.RCC.APB1ENR2.SetBits(stm32.RCC_APB1ENR2_LPTIM2EN)
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case unsafe.Pointer(stm32.I2C4): // I2C4 clock enable
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stm32.RCC.APB1ENR2.SetBits(stm32.RCC_APB1ENR2_I2C4EN)
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case unsafe.Pointer(stm32.LPUART1): // LPUART1 clock enable
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stm32.RCC.APB1ENR2.SetBits(stm32.RCC_APB1ENR2_LPUART1EN)
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case unsafe.Pointer(stm32.TIM16): // TIM16 clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM16EN)
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case unsafe.Pointer(stm32.TIM15): // TIM15 clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM15EN)
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case unsafe.Pointer(stm32.SYSCFG): // System configuration controller clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SYSCFGEN)
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case unsafe.Pointer(stm32.SPI1): // SPI1 clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SPI1EN)
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case unsafe.Pointer(stm32.USART1): // USART1 clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_USART1EN)
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case unsafe.Pointer(stm32.TIM1): // TIM1 clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM1EN)
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}
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}
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36
src/machine/machine_stm32l4x2.go
Обычный файл
36
src/machine/machine_stm32l4x2.go
Обычный файл
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@ -0,0 +1,36 @@
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// +build stm32l4x2
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package machine
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// Peripheral abstraction layer for the stm32l4x2
|
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import (
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"device/stm32"
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)
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func CPUFrequency() uint32 {
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return 80000000
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}
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//---------- UART related code
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// Configure the UART.
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func (uart *UART) configurePins(config UARTConfig) {
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// enable the alternate functions on the TX and RX pins
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config.TX.ConfigureAltFunc(PinConfig{Mode: PinModeUARTTX}, uart.TxAltFuncSelector)
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config.RX.ConfigureAltFunc(PinConfig{Mode: PinModeUARTRX}, uart.RxAltFuncSelector)
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}
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// UART baudrate calc based on the bus and clockspeed
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// NOTE: keep this in sync with the runtime/runtime_stm32l5x2.go clock init code
|
||||
func (uart *UART) getBaudRateDivisor(baudRate uint32) uint32 {
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return (CPUFrequency() / baudRate)
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||||
}
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||||
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// Register names vary by ST processor, these are for STM L5
|
||||
func (uart *UART) setRegisters() {
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uart.rxReg = &uart.Bus.RDR
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||||
uart.txReg = &uart.Bus.TDR
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||||
uart.statusReg = &uart.Bus.ISR
|
||||
uart.txEmptyFlag = stm32.USART_ISR_TXE
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||||
}
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||||
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@ -1,4 +1,4 @@
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// +build !baremetal stm32,!stm32f7x2,!stm32l5x2 fe310 k210 atmega
|
||||
// +build !baremetal stm32,!stm32f7x2,!stm32l5x2,!stm32l4x2 fe310 k210 atmega
|
||||
|
||||
package machine
|
||||
|
||||
|
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|
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262
src/runtime/runtime_stm32l4x2.go
Обычный файл
262
src/runtime/runtime_stm32l4x2.go
Обычный файл
|
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@ -0,0 +1,262 @@
|
|||
// +build stm32,stm32l4x2
|
||||
|
||||
package runtime
|
||||
|
||||
import (
|
||||
"device/stm32"
|
||||
"machine"
|
||||
)
|
||||
|
||||
/*
|
||||
clock settings
|
||||
+-------------+-----------+
|
||||
| LSE | 32.768khz |
|
||||
| SYSCLK | 80mhz |
|
||||
| HCLK | 80mhz |
|
||||
| APB1(PCLK1) | 80mhz |
|
||||
| APB2(PCLK2) | 80mhz |
|
||||
+-------------+-----------+
|
||||
*/
|
||||
const (
|
||||
HSE_STARTUP_TIMEOUT = 0x0500
|
||||
PLL_M = 1
|
||||
PLL_N = 40
|
||||
PLL_P = RCC_PLLP_DIV7
|
||||
PLL_Q = RCC_PLLQ_DIV2
|
||||
PLL_R = RCC_PLLR_DIV2
|
||||
|
||||
MSIRANGE = stm32.RCC_CR_MSIRANGE_Range4M
|
||||
|
||||
PWR_CR1_VOS_0 = 1 << stm32.PWR_CR1_VOS_Pos
|
||||
PWR_CR1_VOS_1 = 2 << stm32.PWR_CR1_VOS_Pos
|
||||
PWR_REGULATOR_VOLTAGE_SCALE1 = PWR_CR1_VOS_0
|
||||
PWR_REGULATOR_VOLTAGE_SCALE2 = PWR_CR1_VOS_1
|
||||
|
||||
FLASH_LATENCY_0 = 0
|
||||
FLASH_LATENCY_1 = 1
|
||||
FLASH_LATENCY_2 = 2
|
||||
FLASH_LATENCY_3 = 3
|
||||
FLASH_LATENCY_4 = 4
|
||||
|
||||
RCC_PLLP_DIV7 = 7
|
||||
RCC_PLLQ_DIV2 = 2
|
||||
RCC_PLLR_DIV2 = 2
|
||||
|
||||
RCC_CFGR_SWS_MSI = 0x0
|
||||
RCC_CFGR_SWS_PLL = 0xC
|
||||
|
||||
RCC_PLLSOURCE_MSI = 1
|
||||
|
||||
RCC_PLL_SYSCLK = stm32.RCC_PLLCFGR_PLLREN
|
||||
)
|
||||
|
||||
/*
|
||||
timer settings used for tick and sleep.
|
||||
|
||||
note: TICK_TIMER_FREQ and SLEEP_TIMER_FREQ are controlled by PLL / clock
|
||||
settings above, so must be kept in sync if the clock settings are changed.
|
||||
*/
|
||||
const (
|
||||
TICK_RATE = 1000 // 1 KHz
|
||||
TICK_TIMER_IRQ = stm32.IRQ_TIM1_UP_TIM16
|
||||
TICK_TIMER_FREQ = 80000000 // 80 MHz
|
||||
SLEEP_TIMER_IRQ = stm32.IRQ_TIM1_BRK_TIM15
|
||||
SLEEP_TIMER_FREQ = 80000000 // 84 MHz
|
||||
)
|
||||
|
||||
type arrtype = uint32
|
||||
|
||||
const asyncScheduler = false
|
||||
|
||||
func init() {
|
||||
initCLK()
|
||||
|
||||
initSleepTimer(&timerInfo{
|
||||
EnableRegister: &stm32.RCC.APB2ENR,
|
||||
EnableFlag: stm32.RCC_APB2ENR_TIM15EN,
|
||||
Device: stm32.TIM15,
|
||||
})
|
||||
|
||||
machine.UART0.Configure(machine.UARTConfig{})
|
||||
|
||||
initTickTimer(&timerInfo{
|
||||
EnableRegister: &stm32.RCC.APB2ENR,
|
||||
EnableFlag: stm32.RCC_APB2ENR_TIM16EN,
|
||||
Device: stm32.TIM16,
|
||||
})
|
||||
}
|
||||
|
||||
func putchar(c byte) {
|
||||
machine.UART0.WriteByte(c)
|
||||
}
|
||||
|
||||
func initCLK() {
|
||||
// PWR_CLK_ENABLE
|
||||
stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_PWREN)
|
||||
_ = stm32.RCC.APB1ENR1.Get()
|
||||
|
||||
// Disable Backup domain protection
|
||||
if !stm32.PWR.CR1.HasBits(stm32.PWR_CR1_DBP) {
|
||||
stm32.PWR.CR1.SetBits(stm32.PWR_CR1_DBP)
|
||||
for !stm32.PWR.CR1.HasBits(stm32.PWR_CR1_DBP) {
|
||||
}
|
||||
}
|
||||
|
||||
// Set LSE Drive to LOW
|
||||
stm32.RCC.BDCR.ReplaceBits(0, stm32.RCC_BDCR_LSEDRV_Msk, 0)
|
||||
|
||||
// Initialize the High-Speed External Oscillator
|
||||
initOsc()
|
||||
|
||||
// PWR_VOLTAGESCALING_CONFIG
|
||||
stm32.PWR.CR1.ReplaceBits(0, stm32.PWR_CR1_VOS_Msk, 0)
|
||||
_ = stm32.PWR.CR1.Get()
|
||||
|
||||
// Set flash wait states (min 5 latency units) based on clock
|
||||
if (stm32.FLASH.ACR.Get() & 0xF) < 5 {
|
||||
stm32.FLASH.ACR.ReplaceBits(5, 0xF, 0)
|
||||
}
|
||||
|
||||
// Ensure HCLK does not exceed max during transition
|
||||
stm32.RCC.CFGR.ReplaceBits(8<<stm32.RCC_CFGR_HPRE_Pos, stm32.RCC_CFGR_HPRE_Msk, 0)
|
||||
|
||||
// Set SYSCLK source and wait
|
||||
// (3 = RCC_SYSCLKSOURCE_PLLCLK, 2=RCC_CFGR_SWS_Pos)
|
||||
stm32.RCC.CFGR.ReplaceBits(3, stm32.RCC_CFGR_SW_Msk, 0)
|
||||
for stm32.RCC.CFGR.Get()&(3<<2) != (3 << 2) {
|
||||
}
|
||||
|
||||
// Set HCLK
|
||||
// (0 = RCC_SYSCLKSOURCE_PLLCLK)
|
||||
stm32.RCC.CFGR.ReplaceBits(0, stm32.RCC_CFGR_HPRE_Msk, 0)
|
||||
|
||||
// Set flash wait states (max 5 latency units) based on clock
|
||||
if (stm32.FLASH.ACR.Get() & 0xF) > 5 {
|
||||
stm32.FLASH.ACR.ReplaceBits(5, 0xF, 0)
|
||||
}
|
||||
|
||||
// Set APB1 and APB2 clocks (0 = DIV1)
|
||||
stm32.RCC.CFGR.ReplaceBits(0, stm32.RCC_CFGR_PPRE1_Msk, 0)
|
||||
stm32.RCC.CFGR.ReplaceBits(0, stm32.RCC_CFGR_PPRE2_Msk, 0)
|
||||
}
|
||||
|
||||
func initOsc() {
|
||||
sysclkSource := stm32.RCC.CFGR.Get() & stm32.RCC_CFGR_SWS_Msk
|
||||
pllConfig := stm32.RCC.PLLCFGR.Get() & stm32.RCC_PLLCFGR_PLLSRC_Msk
|
||||
|
||||
// Enable MSI, adjusting flash latency
|
||||
if sysclkSource == RCC_CFGR_SWS_MSI ||
|
||||
(sysclkSource == RCC_CFGR_SWS_PLL && pllConfig == RCC_PLLSOURCE_MSI) {
|
||||
if MSIRANGE > getMSIRange() {
|
||||
setFlashLatencyFromMSIRange(MSIRANGE)
|
||||
|
||||
setMSIFreq(MSIRANGE, 0)
|
||||
} else {
|
||||
setMSIFreq(MSIRANGE, 0)
|
||||
|
||||
if sysclkSource == RCC_CFGR_SWS_MSI {
|
||||
setFlashLatencyFromMSIRange(MSIRANGE)
|
||||
}
|
||||
}
|
||||
} else {
|
||||
stm32.RCC.CR.SetBits(stm32.RCC_CR_MSION)
|
||||
for !stm32.RCC.CR.HasBits(stm32.RCC_CR_MSIRDY) {
|
||||
}
|
||||
|
||||
setMSIFreq(MSIRANGE, 0)
|
||||
}
|
||||
|
||||
// Enable LSE, wait until ready
|
||||
stm32.RCC.BDCR.SetBits(stm32.RCC_BDCR_LSEON)
|
||||
for !stm32.RCC.BDCR.HasBits(stm32.RCC_BDCR_LSEON) {
|
||||
}
|
||||
|
||||
// Disable the PLL, wait until disabled
|
||||
stm32.RCC.CR.ClearBits(stm32.RCC_CR_PLLON)
|
||||
for stm32.RCC.CR.HasBits(stm32.RCC_CR_PLLRDY) {
|
||||
}
|
||||
|
||||
// Configure the PLL
|
||||
stm32.RCC.PLLCFGR.ReplaceBits(
|
||||
(1)| // 1 = RCC_PLLSOURCE_MSI
|
||||
(PLL_M-1)<<stm32.RCC_PLLCFGR_PLLM_Pos|
|
||||
(PLL_N<<stm32.RCC_PLLCFGR_PLLN_Pos)|
|
||||
(((PLL_Q>>1)-1)<<stm32.RCC_PLLCFGR_PLLQ_Pos)|
|
||||
(((PLL_R>>1)-1)<<stm32.RCC_PLLCFGR_PLLR_Pos)|
|
||||
(PLL_P<<stm32.RCC_PLLCFGR_PLLPDIV_Pos),
|
||||
stm32.RCC_PLLCFGR_PLLSRC_Msk|stm32.RCC_PLLCFGR_PLLM_Msk|
|
||||
stm32.RCC_PLLCFGR_PLLN_Msk|stm32.RCC_PLLCFGR_PLLP_Msk|
|
||||
stm32.RCC_PLLCFGR_PLLR_Msk|stm32.RCC_PLLCFGR_PLLPDIV_Msk,
|
||||
0)
|
||||
|
||||
// Enable the PLL and PLL System Clock Output, wait until ready
|
||||
stm32.RCC.CR.SetBits(stm32.RCC_CR_PLLON)
|
||||
stm32.RCC.PLLCFGR.SetBits(stm32.RCC_PLLCFGR_PLLREN) // = RCC_PLL_SYSCLK
|
||||
for !stm32.RCC.CR.HasBits(stm32.RCC_CR_PLLRDY) {
|
||||
}
|
||||
|
||||
// Enable system clock output
|
||||
stm32.RCC.PLLCFGR.SetBits(RCC_PLL_SYSCLK)
|
||||
}
|
||||
|
||||
func getMSIRange() uint32 {
|
||||
if stm32.RCC.CR.HasBits(stm32.RCC_CR_MSIRGSEL) {
|
||||
return (stm32.RCC.CR.Get() & stm32.RCC_CR_MSIRANGE_Msk) >> stm32.RCC_CR_MSIRANGE_Pos
|
||||
}
|
||||
|
||||
return (stm32.RCC.CSR.Get() & stm32.RCC_CSR_MSISRANGE_Msk) >> stm32.RCC_CSR_MSISRANGE_Pos
|
||||
}
|
||||
|
||||
func setMSIFreq(r uint32, calibration uint32) {
|
||||
stm32.RCC.CR.SetBits(stm32.RCC_CR_MSIRGSEL)
|
||||
stm32.RCC.CR.ReplaceBits(r<<stm32.RCC_CR_MSIRANGE_Pos, stm32.RCC_CR_MSIRANGE_Msk, 0)
|
||||
|
||||
stm32.RCC.ICSCR.ReplaceBits(calibration<<stm32.RCC_ICSCR_MSITRIM_Pos, stm32.RCC_ICSCR_MSITRIM_Msk, 0)
|
||||
}
|
||||
|
||||
func setFlashLatencyFromMSIRange(r uint32) {
|
||||
var vos uint32
|
||||
if pwrIsClkEnabled() {
|
||||
vos = pwrExGetVoltageRange()
|
||||
} else {
|
||||
pwrClkEnable()
|
||||
vos = pwrExGetVoltageRange()
|
||||
pwrClkDisable()
|
||||
}
|
||||
|
||||
latency := uint32(FLASH_LATENCY_0)
|
||||
if vos == PWR_REGULATOR_VOLTAGE_SCALE1 {
|
||||
if r > stm32.RCC_CR_MSIRANGE_Range16M {
|
||||
if r > stm32.RCC_CR_MSIRANGE_Range32M {
|
||||
latency = FLASH_LATENCY_2
|
||||
} else {
|
||||
latency = FLASH_LATENCY_1
|
||||
}
|
||||
}
|
||||
} else if r > stm32.RCC_CR_MSIRANGE_Range16M {
|
||||
latency = FLASH_LATENCY_3
|
||||
} else {
|
||||
if r == stm32.RCC_CR_MSIRANGE_Range16M {
|
||||
latency = FLASH_LATENCY_2
|
||||
} else if r == stm32.RCC_CR_MSIRANGE_Range8M {
|
||||
latency = FLASH_LATENCY_1
|
||||
}
|
||||
}
|
||||
|
||||
stm32.FLASH.ACR.ReplaceBits(latency, stm32.Flash_ACR_LATENCY_Msk, 0)
|
||||
}
|
||||
|
||||
func pwrIsClkEnabled() bool {
|
||||
return stm32.RCC.APB1ENR1.HasBits(stm32.RCC_APB1ENR1_PWREN)
|
||||
}
|
||||
|
||||
func pwrClkEnable() {
|
||||
stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_PWREN)
|
||||
}
|
||||
func pwrClkDisable() {
|
||||
stm32.RCC.APB1ENR1.ClearBits(stm32.RCC_APB1ENR1_PWREN)
|
||||
}
|
||||
|
||||
func pwrExGetVoltageRange() uint32 {
|
||||
return stm32.PWR.CR1.Get() & stm32.PWR_CR1_VOS_Msk
|
||||
}
|
||||
|
|
@ -3,6 +3,7 @@
|
|||
"llvm-target": "armv7em-none-eabi",
|
||||
"cflags": [
|
||||
"--target=armv7em-none-eabi",
|
||||
"-mfloat-abi=soft"
|
||||
"-mfloat-abi=soft",
|
||||
"-Qunused-arguments"
|
||||
]
|
||||
}
|
||||
|
|
|
|||
11
targets/nucleo-l432kc.json
Обычный файл
11
targets/nucleo-l432kc.json
Обычный файл
|
|
@ -0,0 +1,11 @@
|
|||
{
|
||||
"inherits": ["cortex-m4"],
|
||||
"build-tags": ["nucleol432kc", "stm32l432", "stm32l4x2", "stm32l4", "stm32"],
|
||||
"linkerscript": "targets/stm32l4x2.ld",
|
||||
"extra-files": [
|
||||
"src/device/stm32/stm32l4x2.s"
|
||||
],
|
||||
"flash-method": "openocd",
|
||||
"openocd-interface": "stlink-v2-1",
|
||||
"openocd-target": "stm32l4x"
|
||||
}
|
||||
10
targets/stm32l4x2.ld
Обычный файл
10
targets/stm32l4x2.ld
Обычный файл
|
|
@ -0,0 +1,10 @@
|
|||
|
||||
MEMORY
|
||||
{
|
||||
FLASH_TEXT (rx) : ORIGIN = 0x08000000, LENGTH = 256K
|
||||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K
|
||||
}
|
||||
|
||||
_stack_size = 4K;
|
||||
|
||||
INCLUDE "targets/arm.ld"
|
||||
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