machine/sam: Refactor all machine/runtime code to use new volatile package/API
Signed-off-by: Ron Evans <ron@hybridgroup.com>
Этот коммит содержится в:
Ron Evans
родитель
51c6b972bf
коммит
de032cddd2
9 изменённых файлов: 1422 добавлений и 753 удалений
2
Makefile
2
Makefile
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@ -50,7 +50,7 @@ gen-device-nrf:
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go fmt ./src/device/nrf
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gen-device-sam:
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./tools/gen-device-svd.py lib/cmsis-svd/data/Atmel/ src/device/sam/ --source=https://github.com/posborne/cmsis-svd/tree/master/data/Atmel
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./tools/gen-device-svd-vol.py lib/cmsis-svd/data/Atmel/ src/device/sam/ --source=https://github.com/posborne/cmsis-svd/tree/master/data/Atmel
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go fmt ./src/device/sam
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gen-device-stm32:
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Различия файлов не показаны, т.к. их слишком много
Показать различия
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@ -14,50 +14,50 @@ import (
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// Return the register and mask to enable a given GPIO pin. This can be used to
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// implement bit-banged drivers.
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func (p GPIO) PortMaskSet() (*uint32, uint32) {
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return (*uint32)(&sam.PORT.OUTSET0), 1 << p.Pin
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return &sam.PORT.OUTSET0.Reg, 1 << p.Pin
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}
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// Return the register and mask to disable a given port. This can be used to
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// implement bit-banged drivers.
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func (p GPIO) PortMaskClear() (*uint32, uint32) {
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return (*uint32)(&sam.PORT.OUTCLR0), 1 << p.Pin
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return &sam.PORT.OUTCLR0.Reg, 1 << p.Pin
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}
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// Set the pin to high or low.
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// Warning: only use this on an output pin!
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func (p GPIO) Set(high bool) {
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if high {
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sam.PORT.OUTSET0 = (1 << p.Pin)
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sam.PORT.OUTSET0.Set(1 << p.Pin)
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} else {
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sam.PORT.OUTCLR0 = (1 << p.Pin)
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sam.PORT.OUTCLR0.Set(1 << p.Pin)
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}
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}
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// Get returns the current value of a GPIO pin.
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func (p GPIO) Get() bool {
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return (sam.PORT.IN0>>p.Pin)&1 > 0
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return (sam.PORT.IN0.Get()>>p.Pin)&1 > 0
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}
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// Configure this pin with the given configuration.
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func (p GPIO) Configure(config GPIOConfig) {
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switch config.Mode {
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case GPIO_OUTPUT:
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sam.PORT.DIRSET0 = (1 << p.Pin)
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sam.PORT.DIRSET0.Set(1 << p.Pin)
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// output is also set to input enable so pin can read back its own value
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p.setPinCfg(sam.PORT_PINCFG0_INEN)
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case GPIO_INPUT:
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sam.PORT.DIRCLR0 = (1 << p.Pin)
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sam.PORT.DIRCLR0.Set(1 << p.Pin)
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p.setPinCfg(sam.PORT_PINCFG0_INEN)
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case GPIO_INPUT_PULLDOWN:
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sam.PORT.DIRCLR0 = (1 << p.Pin)
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sam.PORT.OUTCLR0 = (1 << p.Pin)
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sam.PORT.DIRCLR0.Set(1 << p.Pin)
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sam.PORT.OUTCLR0.Set(1 << p.Pin)
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p.setPinCfg(sam.PORT_PINCFG0_INEN | sam.PORT_PINCFG0_PULLEN)
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case GPIO_INPUT_PULLUP:
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sam.PORT.DIRCLR0 = (1 << p.Pin)
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sam.PORT.OUTSET0 = (1 << p.Pin)
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sam.PORT.DIRCLR0.Set(1 << p.Pin)
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sam.PORT.OUTSET0.Set(1 << p.Pin)
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p.setPinCfg(sam.PORT_PINCFG0_INEN | sam.PORT_PINCFG0_PULLEN)
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case GPIO_SERCOM:
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@ -114,223 +114,223 @@ func (p GPIO) Configure(config GPIOConfig) {
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}
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// getPMux returns the value for the correct PMUX register for this pin.
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func getPMux(p uint8) sam.RegValue8 {
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func getPMux(p uint8) uint8 {
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pin := p >> 1
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switch pin {
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case 0:
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return sam.PORT.PMUX0_0
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return sam.PORT.PMUX0_0.Get()
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case 1:
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return sam.PORT.PMUX0_1
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return sam.PORT.PMUX0_1.Get()
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case 2:
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return sam.PORT.PMUX0_2
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return sam.PORT.PMUX0_2.Get()
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case 3:
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return sam.PORT.PMUX0_3
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return sam.PORT.PMUX0_3.Get()
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case 4:
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return sam.PORT.PMUX0_4
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return sam.PORT.PMUX0_4.Get()
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case 5:
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return sam.PORT.PMUX0_5
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return sam.PORT.PMUX0_5.Get()
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case 6:
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return sam.PORT.PMUX0_6
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return sam.PORT.PMUX0_6.Get()
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case 7:
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return sam.PORT.PMUX0_7
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return sam.PORT.PMUX0_7.Get()
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case 8:
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return sam.PORT.PMUX0_8
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return sam.PORT.PMUX0_8.Get()
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case 9:
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return sam.PORT.PMUX0_9
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return sam.PORT.PMUX0_9.Get()
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case 10:
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return sam.PORT.PMUX0_10
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return sam.PORT.PMUX0_10.Get()
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case 11:
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return sam.PORT.PMUX0_11
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return sam.PORT.PMUX0_11.Get()
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case 12:
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return sam.PORT.PMUX0_12
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return sam.PORT.PMUX0_12.Get()
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case 13:
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return sam.PORT.PMUX0_13
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return sam.PORT.PMUX0_13.Get()
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case 14:
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return sam.PORT.PMUX0_14
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return sam.PORT.PMUX0_14.Get()
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case 15:
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return sam.PORT.PMUX0_15
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return sam.PORT.PMUX0_15.Get()
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default:
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return 0
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}
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}
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// setPMux sets the value for the correct PMUX register for this pin.
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func setPMux(p uint8, val sam.RegValue8) {
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func setPMux(p uint8, val uint8) {
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pin := p >> 1
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switch pin {
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case 0:
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sam.PORT.PMUX0_0 = val
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sam.PORT.PMUX0_0.Set(val)
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case 1:
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sam.PORT.PMUX0_1 = val
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sam.PORT.PMUX0_1.Set(val)
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case 2:
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sam.PORT.PMUX0_2 = val
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sam.PORT.PMUX0_2.Set(val)
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case 3:
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sam.PORT.PMUX0_3 = val
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sam.PORT.PMUX0_3.Set(val)
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case 4:
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sam.PORT.PMUX0_4 = val
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sam.PORT.PMUX0_4.Set(val)
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case 5:
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sam.PORT.PMUX0_5 = val
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sam.PORT.PMUX0_5.Set(val)
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case 6:
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sam.PORT.PMUX0_6 = val
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sam.PORT.PMUX0_6.Set(val)
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case 7:
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sam.PORT.PMUX0_7 = val
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sam.PORT.PMUX0_7.Set(val)
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case 8:
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sam.PORT.PMUX0_8 = val
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sam.PORT.PMUX0_8.Set(val)
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case 9:
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sam.PORT.PMUX0_9 = val
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sam.PORT.PMUX0_9.Set(val)
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case 10:
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sam.PORT.PMUX0_10 = val
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sam.PORT.PMUX0_10.Set(val)
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case 11:
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sam.PORT.PMUX0_11 = val
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sam.PORT.PMUX0_11.Set(val)
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case 12:
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sam.PORT.PMUX0_12 = val
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sam.PORT.PMUX0_12.Set(val)
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case 13:
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sam.PORT.PMUX0_13 = val
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sam.PORT.PMUX0_13.Set(val)
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case 14:
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sam.PORT.PMUX0_14 = val
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sam.PORT.PMUX0_14.Set(val)
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case 15:
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sam.PORT.PMUX0_15 = val
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sam.PORT.PMUX0_15.Set(val)
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}
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}
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// getPinCfg returns the value for the correct PINCFG register for this pin.
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func getPinCfg(p uint8) sam.RegValue8 {
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func getPinCfg(p uint8) uint8 {
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switch p {
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case 0:
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return sam.PORT.PINCFG0_0
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return sam.PORT.PINCFG0_0.Get()
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case 1:
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return sam.PORT.PINCFG0_1
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return sam.PORT.PINCFG0_1.Get()
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case 2:
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return sam.PORT.PINCFG0_2
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return sam.PORT.PINCFG0_2.Get()
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case 3:
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return sam.PORT.PINCFG0_3
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return sam.PORT.PINCFG0_3.Get()
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case 4:
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return sam.PORT.PINCFG0_4
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return sam.PORT.PINCFG0_4.Get()
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case 5:
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return sam.PORT.PINCFG0_5
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return sam.PORT.PINCFG0_5.Get()
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case 6:
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return sam.PORT.PINCFG0_6
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return sam.PORT.PINCFG0_6.Get()
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case 7:
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return sam.PORT.PINCFG0_7
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return sam.PORT.PINCFG0_7.Get()
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case 8:
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return sam.PORT.PINCFG0_8
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return sam.PORT.PINCFG0_8.Get()
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case 9:
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return sam.PORT.PINCFG0_9
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return sam.PORT.PINCFG0_9.Get()
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case 10:
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return sam.PORT.PINCFG0_10
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return sam.PORT.PINCFG0_10.Get()
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case 11:
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return sam.PORT.PINCFG0_11
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return sam.PORT.PINCFG0_11.Get()
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case 12:
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return sam.PORT.PINCFG0_12
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return sam.PORT.PINCFG0_12.Get()
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case 13:
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return sam.PORT.PINCFG0_13
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return sam.PORT.PINCFG0_13.Get()
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case 14:
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return sam.PORT.PINCFG0_14
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return sam.PORT.PINCFG0_14.Get()
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case 15:
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return sam.PORT.PINCFG0_15
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return sam.PORT.PINCFG0_15.Get()
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case 16:
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return sam.PORT.PINCFG0_16
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return sam.PORT.PINCFG0_16.Get()
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case 17:
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return sam.PORT.PINCFG0_17
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return sam.PORT.PINCFG0_17.Get()
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case 18:
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return sam.PORT.PINCFG0_18
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return sam.PORT.PINCFG0_18.Get()
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case 19:
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return sam.PORT.PINCFG0_19
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return sam.PORT.PINCFG0_19.Get()
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case 20:
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return sam.PORT.PINCFG0_20
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return sam.PORT.PINCFG0_20.Get()
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case 21:
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return sam.PORT.PINCFG0_21
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return sam.PORT.PINCFG0_21.Get()
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case 22:
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return sam.PORT.PINCFG0_22
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return sam.PORT.PINCFG0_22.Get()
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case 23:
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return sam.PORT.PINCFG0_23
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return sam.PORT.PINCFG0_23.Get()
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case 24:
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return sam.PORT.PINCFG0_24
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return sam.PORT.PINCFG0_24.Get()
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case 25:
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return sam.PORT.PINCFG0_25
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return sam.PORT.PINCFG0_25.Get()
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case 26:
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return sam.PORT.PINCFG0_26
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return sam.PORT.PINCFG0_26.Get()
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case 27:
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return sam.PORT.PINCFG0_27
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return sam.PORT.PINCFG0_27.Get()
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case 28:
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return sam.PORT.PINCFG0_28
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return sam.PORT.PINCFG0_28.Get()
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case 29:
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return sam.PORT.PINCFG0_29
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return sam.PORT.PINCFG0_29.Get()
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case 30:
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return sam.PORT.PINCFG0_30
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return sam.PORT.PINCFG0_30.Get()
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case 31:
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return sam.PORT.PINCFG0_31
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return sam.PORT.PINCFG0_31.Get()
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default:
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return 0
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}
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}
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// setPinCfg sets the value for the correct PINCFG register for this pin.
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func setPinCfg(p uint8, val sam.RegValue8) {
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func setPinCfg(p uint8, val uint8) {
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switch p {
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case 0:
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sam.PORT.PINCFG0_0 = val
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sam.PORT.PINCFG0_0.Set(val)
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case 1:
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sam.PORT.PINCFG0_1 = val
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sam.PORT.PINCFG0_1.Set(val)
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case 2:
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sam.PORT.PINCFG0_2 = val
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sam.PORT.PINCFG0_2.Set(val)
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case 3:
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sam.PORT.PINCFG0_3 = val
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sam.PORT.PINCFG0_3.Set(val)
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case 4:
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sam.PORT.PINCFG0_4 = val
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sam.PORT.PINCFG0_4.Set(val)
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case 5:
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sam.PORT.PINCFG0_5 = val
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sam.PORT.PINCFG0_5.Set(val)
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case 6:
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sam.PORT.PINCFG0_6 = val
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sam.PORT.PINCFG0_6.Set(val)
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case 7:
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||||
sam.PORT.PINCFG0_7 = val
|
||||
sam.PORT.PINCFG0_7.Set(val)
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case 8:
|
||||
sam.PORT.PINCFG0_8 = val
|
||||
sam.PORT.PINCFG0_8.Set(val)
|
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case 9:
|
||||
sam.PORT.PINCFG0_9 = val
|
||||
sam.PORT.PINCFG0_9.Set(val)
|
||||
case 10:
|
||||
sam.PORT.PINCFG0_10 = val
|
||||
sam.PORT.PINCFG0_10.Set(val)
|
||||
case 11:
|
||||
sam.PORT.PINCFG0_11 = val
|
||||
sam.PORT.PINCFG0_11.Set(val)
|
||||
case 12:
|
||||
sam.PORT.PINCFG0_12 = val
|
||||
sam.PORT.PINCFG0_12.Set(val)
|
||||
case 13:
|
||||
sam.PORT.PINCFG0_13 = val
|
||||
sam.PORT.PINCFG0_13.Set(val)
|
||||
case 14:
|
||||
sam.PORT.PINCFG0_14 = val
|
||||
sam.PORT.PINCFG0_14.Set(val)
|
||||
case 15:
|
||||
sam.PORT.PINCFG0_15 = val
|
||||
sam.PORT.PINCFG0_15.Set(val)
|
||||
case 16:
|
||||
sam.PORT.PINCFG0_16 = val
|
||||
sam.PORT.PINCFG0_16.Set(val)
|
||||
case 17:
|
||||
sam.PORT.PINCFG0_17 = val
|
||||
sam.PORT.PINCFG0_17.Set(val)
|
||||
case 18:
|
||||
sam.PORT.PINCFG0_18 = val
|
||||
sam.PORT.PINCFG0_18.Set(val)
|
||||
case 19:
|
||||
sam.PORT.PINCFG0_19 = val
|
||||
sam.PORT.PINCFG0_19.Set(val)
|
||||
case 20:
|
||||
sam.PORT.PINCFG0_20 = val
|
||||
sam.PORT.PINCFG0_20.Set(val)
|
||||
case 21:
|
||||
sam.PORT.PINCFG0_21 = val
|
||||
sam.PORT.PINCFG0_21.Set(val)
|
||||
case 22:
|
||||
sam.PORT.PINCFG0_22 = val
|
||||
sam.PORT.PINCFG0_22.Set(val)
|
||||
case 23:
|
||||
sam.PORT.PINCFG0_23 = val
|
||||
sam.PORT.PINCFG0_23.Set(val)
|
||||
case 24:
|
||||
sam.PORT.PINCFG0_24 = val
|
||||
sam.PORT.PINCFG0_24.Set(val)
|
||||
case 25:
|
||||
sam.PORT.PINCFG0_25 = val
|
||||
sam.PORT.PINCFG0_25.Set(val)
|
||||
case 26:
|
||||
sam.PORT.PINCFG0_26 = val
|
||||
sam.PORT.PINCFG0_26.Set(val)
|
||||
case 27:
|
||||
sam.PORT.PINCFG0_27 = val
|
||||
sam.PORT.PINCFG0_27.Set(val)
|
||||
case 28:
|
||||
sam.PORT.PINCFG0_28 = val
|
||||
sam.PORT.PINCFG0_28.Set(val)
|
||||
case 29:
|
||||
sam.PORT.PINCFG0_29 = val
|
||||
sam.PORT.PINCFG0_29.Set(val)
|
||||
case 30:
|
||||
sam.PORT.PINCFG0_30 = val
|
||||
sam.PORT.PINCFG0_30.Set(val)
|
||||
case 31:
|
||||
sam.PORT.PINCFG0_31 = val
|
||||
sam.PORT.PINCFG0_31.Set(val)
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -15,9 +15,9 @@ import (
|
|||
// implement bit-banged drivers.
|
||||
func (p GPIO) PortMaskSet() (*uint32, uint32) {
|
||||
if p.Pin < 32 {
|
||||
return (*uint32)(&sam.PORT.OUTSET0), 1 << p.Pin
|
||||
return &sam.PORT.OUTSET0.Reg, 1 << p.Pin
|
||||
} else {
|
||||
return (*uint32)(&sam.PORT.OUTSET1), 1 << (p.Pin - 32)
|
||||
return &sam.PORT.OUTSET1.Reg, 1 << (p.Pin - 32)
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -25,9 +25,9 @@ func (p GPIO) PortMaskSet() (*uint32, uint32) {
|
|||
// implement bit-banged drivers.
|
||||
func (p GPIO) PortMaskClear() (*uint32, uint32) {
|
||||
if p.Pin < 32 {
|
||||
return (*uint32)(&sam.PORT.OUTCLR0), 1 << p.Pin
|
||||
return &sam.PORT.OUTCLR0.Reg, 1 << p.Pin
|
||||
} else {
|
||||
return (*uint32)(&sam.PORT.OUTCLR1), 1 << (p.Pin - 32)
|
||||
return &sam.PORT.OUTCLR1.Reg, 1 << (p.Pin - 32)
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -36,15 +36,15 @@ func (p GPIO) PortMaskClear() (*uint32, uint32) {
|
|||
func (p GPIO) Set(high bool) {
|
||||
if p.Pin < 32 {
|
||||
if high {
|
||||
sam.PORT.OUTSET0 = (1 << p.Pin)
|
||||
sam.PORT.OUTSET0.Set(1 << p.Pin)
|
||||
} else {
|
||||
sam.PORT.OUTCLR0 = (1 << p.Pin)
|
||||
sam.PORT.OUTCLR0.Set(1 << p.Pin)
|
||||
}
|
||||
} else {
|
||||
if high {
|
||||
sam.PORT.OUTSET1 = (1 << (p.Pin - 32))
|
||||
sam.PORT.OUTSET1.Set(1 << (p.Pin - 32))
|
||||
} else {
|
||||
sam.PORT.OUTCLR1 = (1 << (p.Pin - 32))
|
||||
sam.PORT.OUTCLR1.Set(1 << (p.Pin - 32))
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -52,9 +52,9 @@ func (p GPIO) Set(high bool) {
|
|||
// Get returns the current value of a GPIO pin.
|
||||
func (p GPIO) Get() bool {
|
||||
if p.Pin < 32 {
|
||||
return (sam.PORT.IN0>>p.Pin)&1 > 0
|
||||
return (sam.PORT.IN0.Get()>>p.Pin)&1 > 0
|
||||
} else {
|
||||
return (sam.PORT.IN1>>(p.Pin-32))&1 > 0
|
||||
return (sam.PORT.IN1.Get()>>(p.Pin-32))&1 > 0
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -63,43 +63,43 @@ func (p GPIO) Configure(config GPIOConfig) {
|
|||
switch config.Mode {
|
||||
case GPIO_OUTPUT:
|
||||
if p.Pin < 32 {
|
||||
sam.PORT.DIRSET0 = (1 << p.Pin)
|
||||
sam.PORT.DIRSET0.Set(1 << p.Pin)
|
||||
// output is also set to input enable so pin can read back its own value
|
||||
p.setPinCfg(sam.PORT_PINCFG0_INEN)
|
||||
} else {
|
||||
sam.PORT.DIRSET1 = (1 << (p.Pin - 32))
|
||||
sam.PORT.DIRSET1.Set(1 << (p.Pin - 32))
|
||||
// output is also set to input enable so pin can read back its own value
|
||||
p.setPinCfg(sam.PORT_PINCFG0_INEN)
|
||||
}
|
||||
|
||||
case GPIO_INPUT:
|
||||
if p.Pin < 32 {
|
||||
sam.PORT.DIRCLR0 = (1 << p.Pin)
|
||||
sam.PORT.DIRCLR0.Set(1 << p.Pin)
|
||||
p.setPinCfg(sam.PORT_PINCFG0_INEN)
|
||||
} else {
|
||||
sam.PORT.DIRCLR1 = (1<<p.Pin - 32)
|
||||
sam.PORT.DIRCLR1.Set(1<<p.Pin - 32)
|
||||
p.setPinCfg(sam.PORT_PINCFG0_INEN)
|
||||
}
|
||||
|
||||
case GPIO_INPUT_PULLDOWN:
|
||||
if p.Pin < 32 {
|
||||
sam.PORT.DIRCLR0 = (1 << p.Pin)
|
||||
sam.PORT.OUTCLR0 = (1 << p.Pin)
|
||||
sam.PORT.DIRCLR0.Set(1 << p.Pin)
|
||||
sam.PORT.OUTCLR0.Set(1 << p.Pin)
|
||||
p.setPinCfg(sam.PORT_PINCFG0_INEN | sam.PORT_PINCFG0_PULLEN)
|
||||
} else {
|
||||
sam.PORT.DIRCLR1 = (1<<p.Pin - 32)
|
||||
sam.PORT.OUTCLR1 = (1<<p.Pin - 32)
|
||||
sam.PORT.DIRCLR1.Set(1<<p.Pin - 32)
|
||||
sam.PORT.OUTCLR1.Set(1<<p.Pin - 32)
|
||||
p.setPinCfg(sam.PORT_PINCFG0_INEN | sam.PORT_PINCFG0_PULLEN)
|
||||
}
|
||||
|
||||
case GPIO_INPUT_PULLUP:
|
||||
if p.Pin < 32 {
|
||||
sam.PORT.DIRCLR0 = (1 << p.Pin)
|
||||
sam.PORT.OUTSET0 = (1 << p.Pin)
|
||||
sam.PORT.DIRCLR0.Set(1 << p.Pin)
|
||||
sam.PORT.OUTSET0.Set(1 << p.Pin)
|
||||
p.setPinCfg(sam.PORT_PINCFG0_INEN | sam.PORT_PINCFG0_PULLEN)
|
||||
} else {
|
||||
sam.PORT.DIRCLR1 = (1<<p.Pin - 32)
|
||||
sam.PORT.OUTSET1 = (1<<p.Pin - 32)
|
||||
sam.PORT.DIRCLR1.Set(1<<p.Pin - 32)
|
||||
sam.PORT.OUTSET1.Set(1<<p.Pin - 32)
|
||||
p.setPinCfg(sam.PORT_PINCFG0_INEN | sam.PORT_PINCFG0_PULLEN)
|
||||
}
|
||||
|
||||
|
|
@ -157,415 +157,415 @@ func (p GPIO) Configure(config GPIOConfig) {
|
|||
}
|
||||
|
||||
// getPMux returns the value for the correct PMUX register for this pin.
|
||||
func getPMux(p uint8) sam.RegValue8 {
|
||||
func getPMux(p uint8) uint8 {
|
||||
pin := p >> 1
|
||||
switch pin {
|
||||
case 0:
|
||||
return sam.PORT.PMUX0_0
|
||||
return sam.PORT.PMUX0_0.Get()
|
||||
case 1:
|
||||
return sam.PORT.PMUX0_1
|
||||
return sam.PORT.PMUX0_1.Get()
|
||||
case 2:
|
||||
return sam.PORT.PMUX0_2
|
||||
return sam.PORT.PMUX0_2.Get()
|
||||
case 3:
|
||||
return sam.PORT.PMUX0_3
|
||||
return sam.PORT.PMUX0_3.Get()
|
||||
case 4:
|
||||
return sam.PORT.PMUX0_4
|
||||
return sam.PORT.PMUX0_4.Get()
|
||||
case 5:
|
||||
return sam.PORT.PMUX0_5
|
||||
return sam.PORT.PMUX0_5.Get()
|
||||
case 6:
|
||||
return sam.PORT.PMUX0_6
|
||||
return sam.PORT.PMUX0_6.Get()
|
||||
case 7:
|
||||
return sam.PORT.PMUX0_7
|
||||
return sam.PORT.PMUX0_7.Get()
|
||||
case 8:
|
||||
return sam.PORT.PMUX0_8
|
||||
return sam.PORT.PMUX0_8.Get()
|
||||
case 9:
|
||||
return sam.PORT.PMUX0_9
|
||||
return sam.PORT.PMUX0_9.Get()
|
||||
case 10:
|
||||
return sam.PORT.PMUX0_10
|
||||
return sam.PORT.PMUX0_10.Get()
|
||||
case 11:
|
||||
return sam.PORT.PMUX0_11
|
||||
return sam.PORT.PMUX0_11.Get()
|
||||
case 12:
|
||||
return sam.PORT.PMUX0_12
|
||||
return sam.PORT.PMUX0_12.Get()
|
||||
case 13:
|
||||
return sam.PORT.PMUX0_13
|
||||
return sam.PORT.PMUX0_13.Get()
|
||||
case 14:
|
||||
return sam.PORT.PMUX0_14
|
||||
return sam.PORT.PMUX0_14.Get()
|
||||
case 15:
|
||||
return sam.PORT.PMUX0_15
|
||||
return sam.PORT.PMUX0_15.Get()
|
||||
case 16:
|
||||
return sam.RegValue8(sam.PORT.PMUX1_0>>0) & 0xff
|
||||
return uint8(sam.PORT.PMUX1_0.Get()>>0) & 0xff
|
||||
case 17:
|
||||
return sam.RegValue8(sam.PORT.PMUX1_0>>8) & 0xff
|
||||
return uint8(sam.PORT.PMUX1_0.Get()>>8) & 0xff
|
||||
case 18:
|
||||
return sam.RegValue8(sam.PORT.PMUX1_0>>16) & 0xff
|
||||
return uint8(sam.PORT.PMUX1_0.Get()>>16) & 0xff
|
||||
case 19:
|
||||
return sam.RegValue8(sam.PORT.PMUX1_0>>24) & 0xff
|
||||
return uint8(sam.PORT.PMUX1_0.Get()>>24) & 0xff
|
||||
case 20:
|
||||
return sam.RegValue8(sam.PORT.PMUX1_4>>0) & 0xff
|
||||
return uint8(sam.PORT.PMUX1_4.Get()>>0) & 0xff
|
||||
case 21:
|
||||
return sam.RegValue8(sam.PORT.PMUX1_4>>8) & 0xff
|
||||
return uint8(sam.PORT.PMUX1_4.Get()>>8) & 0xff
|
||||
case 22:
|
||||
return sam.RegValue8(sam.PORT.PMUX1_4>>16) & 0xff
|
||||
return uint8(sam.PORT.PMUX1_4.Get()>>16) & 0xff
|
||||
case 23:
|
||||
return sam.RegValue8(sam.PORT.PMUX1_4>>24) & 0xff
|
||||
return uint8(sam.PORT.PMUX1_4.Get()>>24) & 0xff
|
||||
case 24:
|
||||
return sam.RegValue8(sam.PORT.PMUX1_8>>0) & 0xff
|
||||
return uint8(sam.PORT.PMUX1_8.Get()>>0) & 0xff
|
||||
case 25:
|
||||
return sam.RegValue8(sam.PORT.PMUX1_8>>8) & 0xff
|
||||
return uint8(sam.PORT.PMUX1_8.Get()>>8) & 0xff
|
||||
case 26:
|
||||
return sam.RegValue8(sam.PORT.PMUX1_8>>16) & 0xff
|
||||
return uint8(sam.PORT.PMUX1_8.Get()>>16) & 0xff
|
||||
case 27:
|
||||
return sam.RegValue8(sam.PORT.PMUX1_8>>24) & 0xff
|
||||
return uint8(sam.PORT.PMUX1_8.Get()>>24) & 0xff
|
||||
case 28:
|
||||
return sam.RegValue8(sam.PORT.PMUX1_12>>0) & 0xff
|
||||
return uint8(sam.PORT.PMUX1_12.Get()>>0) & 0xff
|
||||
case 29:
|
||||
return sam.RegValue8(sam.PORT.PMUX1_12>>8) & 0xff
|
||||
return uint8(sam.PORT.PMUX1_12.Get()>>8) & 0xff
|
||||
case 30:
|
||||
return sam.RegValue8(sam.PORT.PMUX1_12>>16) & 0xff
|
||||
return uint8(sam.PORT.PMUX1_12.Get()>>16) & 0xff
|
||||
case 31:
|
||||
return sam.RegValue8(sam.PORT.PMUX1_12>>24) & 0xff
|
||||
return uint8(sam.PORT.PMUX1_12.Get()>>24) & 0xff
|
||||
default:
|
||||
return 0
|
||||
}
|
||||
}
|
||||
|
||||
// setPMux sets the value for the correct PMUX register for this pin.
|
||||
func setPMux(p uint8, val sam.RegValue8) {
|
||||
func setPMux(p uint8, val uint8) {
|
||||
pin := p >> 1
|
||||
switch pin {
|
||||
case 0:
|
||||
sam.PORT.PMUX0_0 = val
|
||||
sam.PORT.PMUX0_0.Set(val)
|
||||
case 1:
|
||||
sam.PORT.PMUX0_1 = val
|
||||
sam.PORT.PMUX0_1.Set(val)
|
||||
case 2:
|
||||
sam.PORT.PMUX0_2 = val
|
||||
sam.PORT.PMUX0_2.Set(val)
|
||||
case 3:
|
||||
sam.PORT.PMUX0_3 = val
|
||||
sam.PORT.PMUX0_3.Set(val)
|
||||
case 4:
|
||||
sam.PORT.PMUX0_4 = val
|
||||
sam.PORT.PMUX0_4.Set(val)
|
||||
case 5:
|
||||
sam.PORT.PMUX0_5 = val
|
||||
sam.PORT.PMUX0_5.Set(val)
|
||||
case 6:
|
||||
sam.PORT.PMUX0_6 = val
|
||||
sam.PORT.PMUX0_6.Set(val)
|
||||
case 7:
|
||||
sam.PORT.PMUX0_7 = val
|
||||
sam.PORT.PMUX0_7.Set(val)
|
||||
case 8:
|
||||
sam.PORT.PMUX0_8 = val
|
||||
sam.PORT.PMUX0_8.Set(val)
|
||||
case 9:
|
||||
sam.PORT.PMUX0_9 = val
|
||||
sam.PORT.PMUX0_9.Set(val)
|
||||
case 10:
|
||||
sam.PORT.PMUX0_10 = val
|
||||
sam.PORT.PMUX0_10.Set(val)
|
||||
case 11:
|
||||
sam.PORT.PMUX0_11 = val
|
||||
sam.PORT.PMUX0_11.Set(val)
|
||||
case 12:
|
||||
sam.PORT.PMUX0_12 = val
|
||||
sam.PORT.PMUX0_12.Set(val)
|
||||
case 13:
|
||||
sam.PORT.PMUX0_13 = val
|
||||
sam.PORT.PMUX0_13.Set(val)
|
||||
case 14:
|
||||
sam.PORT.PMUX0_14 = val
|
||||
sam.PORT.PMUX0_14.Set(val)
|
||||
case 15:
|
||||
sam.PORT.PMUX0_15 = val
|
||||
sam.PORT.PMUX0_15.Set(val)
|
||||
case 16:
|
||||
sam.PORT.PMUX1_0 = (sam.PORT.PMUX1_0 &^ (0xff << 0)) | (sam.RegValue(val) << 0)
|
||||
sam.PORT.PMUX1_0.Set(sam.PORT.PMUX1_0.Get()&^(0xff<<0) | (uint32(val) << 0))
|
||||
case 17:
|
||||
sam.PORT.PMUX1_0 = (sam.PORT.PMUX1_0 &^ (0xff << 8)) | (sam.RegValue(val) << 8)
|
||||
sam.PORT.PMUX1_0.Set(sam.PORT.PMUX1_0.Get()&^(0xff<<8) | (uint32(val) << 8))
|
||||
case 18:
|
||||
sam.PORT.PMUX1_0 = (sam.PORT.PMUX1_0 &^ (0xff << 16)) | (sam.RegValue(val) << 16)
|
||||
sam.PORT.PMUX1_0.Set(sam.PORT.PMUX1_0.Get()&^(0xff<<16) | (uint32(val) << 16))
|
||||
case 19:
|
||||
sam.PORT.PMUX1_0 = (sam.PORT.PMUX1_0 &^ (0xff << 24)) | (sam.RegValue(val) << 24)
|
||||
sam.PORT.PMUX1_0.Set(sam.PORT.PMUX1_0.Get()&^(0xff<<24) | (uint32(val) << 24))
|
||||
case 20:
|
||||
sam.PORT.PMUX1_4 = (sam.PORT.PMUX1_4 &^ (0xff << 0)) | (sam.RegValue(val) << 0)
|
||||
sam.PORT.PMUX1_4.Set(sam.PORT.PMUX1_4.Get()&^(0xff<<0) | (uint32(val) << 0))
|
||||
case 21:
|
||||
sam.PORT.PMUX1_4 = (sam.PORT.PMUX1_4 &^ (0xff << 8)) | (sam.RegValue(val) << 8)
|
||||
sam.PORT.PMUX1_4.Set(sam.PORT.PMUX1_4.Get()&^(0xff<<8) | (uint32(val) << 8))
|
||||
case 22:
|
||||
sam.PORT.PMUX1_4 = (sam.PORT.PMUX1_4 &^ (0xff << 16)) | (sam.RegValue(val) << 16)
|
||||
sam.PORT.PMUX1_4.Set(sam.PORT.PMUX1_4.Get()&^(0xff<<16) | (uint32(val) << 16))
|
||||
case 23:
|
||||
sam.PORT.PMUX1_4 = (sam.PORT.PMUX1_4 &^ (0xff << 24)) | (sam.RegValue(val) << 24)
|
||||
sam.PORT.PMUX1_4.Set(sam.PORT.PMUX1_4.Get()&^(0xff<<24) | (uint32(val) << 24))
|
||||
case 24:
|
||||
sam.PORT.PMUX1_8 = (sam.PORT.PMUX1_8 &^ (0xff << 0)) | (sam.RegValue(val) << 0)
|
||||
sam.PORT.PMUX1_8.Set(sam.PORT.PMUX1_8.Get()&^(0xff<<0) | (uint32(val) << 0))
|
||||
case 25:
|
||||
sam.PORT.PMUX1_8 = (sam.PORT.PMUX1_8 &^ (0xff << 8)) | (sam.RegValue(val) << 8)
|
||||
sam.PORT.PMUX1_8.Set(sam.PORT.PMUX1_8.Get()&^(0xff<<8) | (uint32(val) << 8))
|
||||
case 26:
|
||||
sam.PORT.PMUX1_8 = (sam.PORT.PMUX1_8 &^ (0xff << 16)) | (sam.RegValue(val) << 16)
|
||||
sam.PORT.PMUX1_8.Set(sam.PORT.PMUX1_8.Get()&^(0xff<<16) | (uint32(val) << 16))
|
||||
case 27:
|
||||
sam.PORT.PMUX1_8 = (sam.PORT.PMUX1_8 &^ (0xff << 24)) | (sam.RegValue(val) << 24)
|
||||
sam.PORT.PMUX1_8.Set(sam.PORT.PMUX1_8.Get()&^(0xff<<24) | (uint32(val) << 24))
|
||||
case 28:
|
||||
sam.PORT.PMUX1_12 = (sam.PORT.PMUX1_12 &^ (0xff << 0)) | (sam.RegValue(val) << 0)
|
||||
sam.PORT.PMUX1_12.Set(sam.PORT.PMUX1_12.Get()&^(0xff<<0) | (uint32(val) << 0))
|
||||
case 29:
|
||||
sam.PORT.PMUX1_12 = (sam.PORT.PMUX1_12 &^ (0xff << 8)) | (sam.RegValue(val) << 8)
|
||||
sam.PORT.PMUX1_12.Set(sam.PORT.PMUX1_12.Get()&^(0xff<<8) | (uint32(val) << 8))
|
||||
case 30:
|
||||
sam.PORT.PMUX1_12 = (sam.PORT.PMUX1_12 &^ (0xff << 16)) | (sam.RegValue(val) << 16)
|
||||
sam.PORT.PMUX1_12.Set(sam.PORT.PMUX1_12.Get()&^(0xff<<16) | (uint32(val) << 16))
|
||||
case 31:
|
||||
sam.PORT.PMUX1_12 = (sam.PORT.PMUX1_12 &^ (0xff << 24)) | (sam.RegValue(val) << 24)
|
||||
sam.PORT.PMUX1_12.Set(sam.PORT.PMUX1_12.Get()&^(0xff<<24) | (uint32(val) << 24))
|
||||
}
|
||||
}
|
||||
|
||||
// getPinCfg returns the value for the correct PINCFG register for this pin.
|
||||
func getPinCfg(p uint8) sam.RegValue8 {
|
||||
func getPinCfg(p uint8) uint8 {
|
||||
switch p {
|
||||
case 0:
|
||||
return sam.PORT.PINCFG0_0
|
||||
return sam.PORT.PINCFG0_0.Get()
|
||||
case 1:
|
||||
return sam.PORT.PINCFG0_1
|
||||
return sam.PORT.PINCFG0_1.Get()
|
||||
case 2:
|
||||
return sam.PORT.PINCFG0_2
|
||||
return sam.PORT.PINCFG0_2.Get()
|
||||
case 3:
|
||||
return sam.PORT.PINCFG0_3
|
||||
return sam.PORT.PINCFG0_3.Get()
|
||||
case 4:
|
||||
return sam.PORT.PINCFG0_4
|
||||
return sam.PORT.PINCFG0_4.Get()
|
||||
case 5:
|
||||
return sam.PORT.PINCFG0_5
|
||||
return sam.PORT.PINCFG0_5.Get()
|
||||
case 6:
|
||||
return sam.PORT.PINCFG0_6
|
||||
return sam.PORT.PINCFG0_6.Get()
|
||||
case 7:
|
||||
return sam.PORT.PINCFG0_7
|
||||
return sam.PORT.PINCFG0_7.Get()
|
||||
case 8:
|
||||
return sam.PORT.PINCFG0_8
|
||||
return sam.PORT.PINCFG0_8.Get()
|
||||
case 9:
|
||||
return sam.PORT.PINCFG0_9
|
||||
return sam.PORT.PINCFG0_9.Get()
|
||||
case 10:
|
||||
return sam.PORT.PINCFG0_10
|
||||
return sam.PORT.PINCFG0_10.Get()
|
||||
case 11:
|
||||
return sam.PORT.PINCFG0_11
|
||||
return sam.PORT.PINCFG0_11.Get()
|
||||
case 12:
|
||||
return sam.PORT.PINCFG0_12
|
||||
return sam.PORT.PINCFG0_12.Get()
|
||||
case 13:
|
||||
return sam.PORT.PINCFG0_13
|
||||
return sam.PORT.PINCFG0_13.Get()
|
||||
case 14:
|
||||
return sam.PORT.PINCFG0_14
|
||||
return sam.PORT.PINCFG0_14.Get()
|
||||
case 15:
|
||||
return sam.PORT.PINCFG0_15
|
||||
return sam.PORT.PINCFG0_15.Get()
|
||||
case 16:
|
||||
return sam.PORT.PINCFG0_16
|
||||
return sam.PORT.PINCFG0_16.Get()
|
||||
case 17:
|
||||
return sam.PORT.PINCFG0_17
|
||||
return sam.PORT.PINCFG0_17.Get()
|
||||
case 18:
|
||||
return sam.PORT.PINCFG0_18
|
||||
return sam.PORT.PINCFG0_18.Get()
|
||||
case 19:
|
||||
return sam.PORT.PINCFG0_19
|
||||
return sam.PORT.PINCFG0_19.Get()
|
||||
case 20:
|
||||
return sam.PORT.PINCFG0_20
|
||||
return sam.PORT.PINCFG0_20.Get()
|
||||
case 21:
|
||||
return sam.PORT.PINCFG0_21
|
||||
return sam.PORT.PINCFG0_21.Get()
|
||||
case 22:
|
||||
return sam.PORT.PINCFG0_22
|
||||
return sam.PORT.PINCFG0_22.Get()
|
||||
case 23:
|
||||
return sam.PORT.PINCFG0_23
|
||||
return sam.PORT.PINCFG0_23.Get()
|
||||
case 24:
|
||||
return sam.PORT.PINCFG0_24
|
||||
return sam.PORT.PINCFG0_24.Get()
|
||||
case 25:
|
||||
return sam.PORT.PINCFG0_25
|
||||
return sam.PORT.PINCFG0_25.Get()
|
||||
case 26:
|
||||
return sam.PORT.PINCFG0_26
|
||||
return sam.PORT.PINCFG0_26.Get()
|
||||
case 27:
|
||||
return sam.PORT.PINCFG0_27
|
||||
return sam.PORT.PINCFG0_27.Get()
|
||||
case 28:
|
||||
return sam.PORT.PINCFG0_28
|
||||
return sam.PORT.PINCFG0_28.Get()
|
||||
case 29:
|
||||
return sam.PORT.PINCFG0_29
|
||||
return sam.PORT.PINCFG0_29.Get()
|
||||
case 30:
|
||||
return sam.PORT.PINCFG0_30
|
||||
return sam.PORT.PINCFG0_30.Get()
|
||||
case 31:
|
||||
return sam.PORT.PINCFG0_31
|
||||
return sam.PORT.PINCFG0_31.Get()
|
||||
case 32: // PB00
|
||||
return sam.RegValue8(sam.PORT.PINCFG1_0>>0) & 0xff
|
||||
return uint8(sam.PORT.PINCFG1_0.Get()>>0) & 0xff
|
||||
case 33: // PB01
|
||||
return sam.RegValue8(sam.PORT.PINCFG1_0>>8) & 0xff
|
||||
return uint8(sam.PORT.PINCFG1_0.Get()>>8) & 0xff
|
||||
case 34: // PB02
|
||||
return sam.RegValue8(sam.PORT.PINCFG1_0>>16) & 0xff
|
||||
return uint8(sam.PORT.PINCFG1_0.Get()>>16) & 0xff
|
||||
case 35: // PB03
|
||||
return sam.RegValue8(sam.PORT.PINCFG1_0>>24) & 0xff
|
||||
return uint8(sam.PORT.PINCFG1_0.Get()>>24) & 0xff
|
||||
case 37: // PB04
|
||||
return sam.RegValue8(sam.PORT.PINCFG1_4>>0) & 0xff
|
||||
return uint8(sam.PORT.PINCFG1_4.Get()>>0) & 0xff
|
||||
case 38: // PB05
|
||||
return sam.RegValue8(sam.PORT.PINCFG1_4>>8) & 0xff
|
||||
return uint8(sam.PORT.PINCFG1_4.Get()>>8) & 0xff
|
||||
case 39: // PB06
|
||||
return sam.RegValue8(sam.PORT.PINCFG1_4>>16) & 0xff
|
||||
return uint8(sam.PORT.PINCFG1_4.Get()>>16) & 0xff
|
||||
case 40: // PB07
|
||||
return sam.RegValue8(sam.PORT.PINCFG1_4>>24) & 0xff
|
||||
return uint8(sam.PORT.PINCFG1_4.Get()>>24) & 0xff
|
||||
case 41: // PB08
|
||||
return sam.RegValue8(sam.PORT.PINCFG1_8>>0) & 0xff
|
||||
return uint8(sam.PORT.PINCFG1_8.Get()>>0) & 0xff
|
||||
case 42: // PB09
|
||||
return sam.RegValue8(sam.PORT.PINCFG1_8>>8) & 0xff
|
||||
return uint8(sam.PORT.PINCFG1_8.Get()>>8) & 0xff
|
||||
case 43: // PB10
|
||||
return sam.RegValue8(sam.PORT.PINCFG1_8>>16) & 0xff
|
||||
return uint8(sam.PORT.PINCFG1_8.Get()>>16) & 0xff
|
||||
case 44: // PB11
|
||||
return sam.RegValue8(sam.PORT.PINCFG1_8>>24) & 0xff
|
||||
return uint8(sam.PORT.PINCFG1_8.Get()>>24) & 0xff
|
||||
case 45: // PB12
|
||||
return sam.RegValue8(sam.PORT.PINCFG1_12>>0) & 0xff
|
||||
return uint8(sam.PORT.PINCFG1_12.Get()>>0) & 0xff
|
||||
case 46: // PB13
|
||||
return sam.RegValue8(sam.PORT.PINCFG1_12>>8) & 0xff
|
||||
return uint8(sam.PORT.PINCFG1_12.Get()>>8) & 0xff
|
||||
case 47: // PB14
|
||||
return sam.RegValue8(sam.PORT.PINCFG1_12>>16) & 0xff
|
||||
return uint8(sam.PORT.PINCFG1_12.Get()>>16) & 0xff
|
||||
case 48: // PB15
|
||||
return sam.RegValue8(sam.PORT.PINCFG1_12>>24) & 0xff
|
||||
return uint8(sam.PORT.PINCFG1_12.Get()>>24) & 0xff
|
||||
case 49: // PB16
|
||||
return sam.RegValue8(sam.PORT.PINCFG1_16>>0) & 0xff
|
||||
return uint8(sam.PORT.PINCFG1_16.Get()>>0) & 0xff
|
||||
case 50: // PB17
|
||||
return sam.RegValue8(sam.PORT.PINCFG1_16>>8) & 0xff
|
||||
return uint8(sam.PORT.PINCFG1_16.Get()>>8) & 0xff
|
||||
case 51: // PB18
|
||||
return sam.RegValue8(sam.PORT.PINCFG1_16>>16) & 0xff
|
||||
return uint8(sam.PORT.PINCFG1_16.Get()>>16) & 0xff
|
||||
case 52: // PB19
|
||||
return sam.RegValue8(sam.PORT.PINCFG1_16>>24) & 0xff
|
||||
return uint8(sam.PORT.PINCFG1_16.Get()>>24) & 0xff
|
||||
case 53: // PB20
|
||||
return sam.RegValue8(sam.PORT.PINCFG1_20>>0) & 0xff
|
||||
return uint8(sam.PORT.PINCFG1_20.Get()>>0) & 0xff
|
||||
case 54: // PB21
|
||||
return sam.RegValue8(sam.PORT.PINCFG1_20>>8) & 0xff
|
||||
return uint8(sam.PORT.PINCFG1_20.Get()>>8) & 0xff
|
||||
case 55: // PB22
|
||||
return sam.RegValue8(sam.PORT.PINCFG1_20>>16) & 0xff
|
||||
return uint8(sam.PORT.PINCFG1_20.Get()>>16) & 0xff
|
||||
case 56: // PB23
|
||||
return sam.RegValue8(sam.PORT.PINCFG1_20>>24) & 0xff
|
||||
return uint8(sam.PORT.PINCFG1_20.Get()>>24) & 0xff
|
||||
case 57: // PB24
|
||||
return sam.RegValue8(sam.PORT.PINCFG1_24>>0) & 0xff
|
||||
return uint8(sam.PORT.PINCFG1_24.Get()>>0) & 0xff
|
||||
case 58: // PB25
|
||||
return sam.RegValue8(sam.PORT.PINCFG1_24>>8) & 0xff
|
||||
return uint8(sam.PORT.PINCFG1_24.Get()>>8) & 0xff
|
||||
case 59: // PB26
|
||||
return sam.RegValue8(sam.PORT.PINCFG1_24>>16) & 0xff
|
||||
return uint8(sam.PORT.PINCFG1_24.Get()>>16) & 0xff
|
||||
case 60: // PB27
|
||||
return sam.RegValue8(sam.PORT.PINCFG1_24>>24) & 0xff
|
||||
return uint8(sam.PORT.PINCFG1_24.Get()>>24) & 0xff
|
||||
case 61: // PB28
|
||||
return sam.RegValue8(sam.PORT.PINCFG1_28>>0) & 0xff
|
||||
return uint8(sam.PORT.PINCFG1_28.Get()>>0) & 0xff
|
||||
case 62: // PB29
|
||||
return sam.RegValue8(sam.PORT.PINCFG1_28>>8) & 0xff
|
||||
return uint8(sam.PORT.PINCFG1_28.Get()>>8) & 0xff
|
||||
case 63: // PB30
|
||||
return sam.RegValue8(sam.PORT.PINCFG1_28>>16) & 0xff
|
||||
return uint8(sam.PORT.PINCFG1_28.Get()>>16) & 0xff
|
||||
case 64: // PB31
|
||||
return sam.RegValue8(sam.PORT.PINCFG1_28>>24) & 0xff
|
||||
return uint8(sam.PORT.PINCFG1_28.Get()>>24) & 0xff
|
||||
default:
|
||||
return 0
|
||||
}
|
||||
}
|
||||
|
||||
// setPinCfg sets the value for the correct PINCFG register for this pin.
|
||||
func setPinCfg(p uint8, val sam.RegValue8) {
|
||||
func setPinCfg(p uint8, val uint8) {
|
||||
switch p {
|
||||
case 0:
|
||||
sam.PORT.PINCFG0_0 = val
|
||||
sam.PORT.PINCFG0_0.Set(val)
|
||||
case 1:
|
||||
sam.PORT.PINCFG0_1 = val
|
||||
sam.PORT.PINCFG0_1.Set(val)
|
||||
case 2:
|
||||
sam.PORT.PINCFG0_2 = val
|
||||
sam.PORT.PINCFG0_2.Set(val)
|
||||
case 3:
|
||||
sam.PORT.PINCFG0_3 = val
|
||||
sam.PORT.PINCFG0_3.Set(val)
|
||||
case 4:
|
||||
sam.PORT.PINCFG0_4 = val
|
||||
sam.PORT.PINCFG0_4.Set(val)
|
||||
case 5:
|
||||
sam.PORT.PINCFG0_5 = val
|
||||
sam.PORT.PINCFG0_5.Set(val)
|
||||
case 6:
|
||||
sam.PORT.PINCFG0_6 = val
|
||||
sam.PORT.PINCFG0_6.Set(val)
|
||||
case 7:
|
||||
sam.PORT.PINCFG0_7 = val
|
||||
sam.PORT.PINCFG0_7.Set(val)
|
||||
case 8:
|
||||
sam.PORT.PINCFG0_8 = val
|
||||
sam.PORT.PINCFG0_8.Set(val)
|
||||
case 9:
|
||||
sam.PORT.PINCFG0_9 = val
|
||||
sam.PORT.PINCFG0_9.Set(val)
|
||||
case 10:
|
||||
sam.PORT.PINCFG0_10 = val
|
||||
sam.PORT.PINCFG0_10.Set(val)
|
||||
case 11:
|
||||
sam.PORT.PINCFG0_11 = val
|
||||
sam.PORT.PINCFG0_11.Set(val)
|
||||
case 12:
|
||||
sam.PORT.PINCFG0_12 = val
|
||||
sam.PORT.PINCFG0_12.Set(val)
|
||||
case 13:
|
||||
sam.PORT.PINCFG0_13 = val
|
||||
sam.PORT.PINCFG0_13.Set(val)
|
||||
case 14:
|
||||
sam.PORT.PINCFG0_14 = val
|
||||
sam.PORT.PINCFG0_14.Set(val)
|
||||
case 15:
|
||||
sam.PORT.PINCFG0_15 = val
|
||||
sam.PORT.PINCFG0_15.Set(val)
|
||||
case 16:
|
||||
sam.PORT.PINCFG0_16 = val
|
||||
sam.PORT.PINCFG0_16.Set(val)
|
||||
case 17:
|
||||
sam.PORT.PINCFG0_17 = val
|
||||
sam.PORT.PINCFG0_17.Set(val)
|
||||
case 18:
|
||||
sam.PORT.PINCFG0_18 = val
|
||||
sam.PORT.PINCFG0_18.Set(val)
|
||||
case 19:
|
||||
sam.PORT.PINCFG0_19 = val
|
||||
sam.PORT.PINCFG0_19.Set(val)
|
||||
case 20:
|
||||
sam.PORT.PINCFG0_20 = val
|
||||
sam.PORT.PINCFG0_20.Set(val)
|
||||
case 21:
|
||||
sam.PORT.PINCFG0_21 = val
|
||||
sam.PORT.PINCFG0_21.Set(val)
|
||||
case 22:
|
||||
sam.PORT.PINCFG0_22 = val
|
||||
sam.PORT.PINCFG0_22.Set(val)
|
||||
case 23:
|
||||
sam.PORT.PINCFG0_23 = val
|
||||
sam.PORT.PINCFG0_23.Set(val)
|
||||
case 24:
|
||||
sam.PORT.PINCFG0_24 = val
|
||||
sam.PORT.PINCFG0_24.Set(val)
|
||||
case 25:
|
||||
sam.PORT.PINCFG0_25 = val
|
||||
sam.PORT.PINCFG0_25.Set(val)
|
||||
case 26:
|
||||
sam.PORT.PINCFG0_26 = val
|
||||
sam.PORT.PINCFG0_26.Set(val)
|
||||
case 27:
|
||||
sam.PORT.PINCFG0_27 = val
|
||||
sam.PORT.PINCFG0_27.Set(val)
|
||||
case 28:
|
||||
sam.PORT.PINCFG0_28 = val
|
||||
sam.PORT.PINCFG0_28.Set(val)
|
||||
case 29:
|
||||
sam.PORT.PINCFG0_29 = val
|
||||
sam.PORT.PINCFG0_29.Set(val)
|
||||
case 30:
|
||||
sam.PORT.PINCFG0_30 = val
|
||||
sam.PORT.PINCFG0_30.Set(val)
|
||||
case 31:
|
||||
sam.PORT.PINCFG0_31 = val
|
||||
sam.PORT.PINCFG0_31.Set(val)
|
||||
case 32: // PB00
|
||||
sam.PORT.PINCFG1_0 = (sam.PORT.PINCFG1_0 &^ (0xff << 0)) | (sam.RegValue(val) << 0)
|
||||
sam.PORT.PINCFG1_0.Set(sam.PORT.PINCFG1_0.Get()&^(0xff<<0) | (uint32(val) << 0))
|
||||
case 33: // PB01
|
||||
sam.PORT.PINCFG1_0 = (sam.PORT.PINCFG1_0 &^ (0xff << 8)) | (sam.RegValue(val) << 8)
|
||||
sam.PORT.PINCFG1_0.Set(sam.PORT.PINCFG1_0.Get()&^(0xff<<8) | (uint32(val) << 8))
|
||||
case 34: // PB02
|
||||
sam.PORT.PINCFG1_0 = (sam.PORT.PINCFG1_0 &^ (0xff << 16)) | (sam.RegValue(val) << 16)
|
||||
sam.PORT.PINCFG1_0.Set(sam.PORT.PINCFG1_0.Get()&^(0xff<<16) | (uint32(val) << 16))
|
||||
case 35: // PB03
|
||||
sam.PORT.PINCFG1_0 = (sam.PORT.PINCFG1_0 &^ (0xff << 24)) | (sam.RegValue(val) << 24)
|
||||
sam.PORT.PINCFG1_0.Set(sam.PORT.PINCFG1_0.Get()&^(0xff<<24) | (uint32(val) << 24))
|
||||
case 36: // PB04
|
||||
sam.PORT.PINCFG1_4 = (sam.PORT.PINCFG1_4 &^ (0xff << 0)) | (sam.RegValue(val) << 0)
|
||||
sam.PORT.PINCFG1_4.Set(sam.PORT.PINCFG1_4.Get()&^(0xff<<0) | (uint32(val) << 0))
|
||||
case 37: // PB05
|
||||
sam.PORT.PINCFG1_4 = (sam.PORT.PINCFG1_4 &^ (0xff << 8)) | (sam.RegValue(val) << 8)
|
||||
sam.PORT.PINCFG1_4.Set(sam.PORT.PINCFG1_4.Get()&^(0xff<<8) | (uint32(val) << 8))
|
||||
case 38: // PB06
|
||||
sam.PORT.PINCFG1_4 = (sam.PORT.PINCFG1_4 &^ (0xff << 16)) | (sam.RegValue(val) << 16)
|
||||
sam.PORT.PINCFG1_4.Set(sam.PORT.PINCFG1_4.Get()&^(0xff<<16) | (uint32(val) << 16))
|
||||
case 39: // PB07
|
||||
sam.PORT.PINCFG1_4 = (sam.PORT.PINCFG1_4 &^ (0xff << 24)) | (sam.RegValue(val) << 24)
|
||||
sam.PORT.PINCFG1_4.Set(sam.PORT.PINCFG1_4.Get()&^(0xff<<24) | (uint32(val) << 24))
|
||||
case 40: // PB08
|
||||
sam.PORT.PINCFG1_8 = (sam.PORT.PINCFG1_8 &^ (0xff << 0)) | (sam.RegValue(val) << 0)
|
||||
sam.PORT.PINCFG1_8.Set(sam.PORT.PINCFG1_8.Get()&^(0xff<<0) | (uint32(val) << 0))
|
||||
case 41: // PB09
|
||||
sam.PORT.PINCFG1_8 = (sam.PORT.PINCFG1_8 &^ (0xff << 8)) | (sam.RegValue(val) << 8)
|
||||
sam.PORT.PINCFG1_8.Set(sam.PORT.PINCFG1_8.Get()&^(0xff<<8) | (uint32(val) << 8))
|
||||
case 42: // PB10
|
||||
sam.PORT.PINCFG1_8 = (sam.PORT.PINCFG1_8 &^ (0xff << 16)) | (sam.RegValue(val) << 16)
|
||||
sam.PORT.PINCFG1_8.Set(sam.PORT.PINCFG1_8.Get()&^(0xff<<16) | (uint32(val) << 16))
|
||||
case 43: // PB11
|
||||
sam.PORT.PINCFG1_8 = (sam.PORT.PINCFG1_8 &^ (0xff << 24)) | (sam.RegValue(val) << 24)
|
||||
sam.PORT.PINCFG1_8.Set(sam.PORT.PINCFG1_8.Get()&^(0xff<<24) | (uint32(val) << 24))
|
||||
case 44: // PB12
|
||||
sam.PORT.PINCFG1_12 = (sam.PORT.PINCFG1_12 &^ (0xff << 0)) | (sam.RegValue(val) << 0)
|
||||
sam.PORT.PINCFG1_12.Set(sam.PORT.PINCFG1_12.Get()&^(0xff<<0) | (uint32(val) << 0))
|
||||
case 45: // PB13
|
||||
sam.PORT.PINCFG1_12 = (sam.PORT.PINCFG1_12 &^ (0xff << 8)) | (sam.RegValue(val) << 8)
|
||||
sam.PORT.PINCFG1_12.Set(sam.PORT.PINCFG1_12.Get()&^(0xff<<8) | (uint32(val) << 8))
|
||||
case 46: // PB14
|
||||
sam.PORT.PINCFG1_12 = (sam.PORT.PINCFG1_12 &^ (0xff << 16)) | (sam.RegValue(val) << 16)
|
||||
sam.PORT.PINCFG1_12.Set(sam.PORT.PINCFG1_12.Get()&^(0xff<<16) | (uint32(val) << 16))
|
||||
case 47: // PB15
|
||||
sam.PORT.PINCFG1_12 = (sam.PORT.PINCFG1_12 &^ (0xff << 24)) | (sam.RegValue(val) << 24)
|
||||
sam.PORT.PINCFG1_12.Set(sam.PORT.PINCFG1_12.Get()&^(0xff<<24) | (uint32(val) << 24))
|
||||
case 48: // PB16
|
||||
sam.PORT.PINCFG1_16 = (sam.PORT.PINCFG1_16 &^ (0xff << 0)) | (sam.RegValue(val) << 0)
|
||||
sam.PORT.PINCFG1_16.Set(sam.PORT.PINCFG1_16.Get()&^(0xff<<0) | (uint32(val) << 0))
|
||||
case 49: // PB17
|
||||
sam.PORT.PINCFG1_16 = (sam.PORT.PINCFG1_16 &^ (0xff << 8)) | (sam.RegValue(val) << 8)
|
||||
sam.PORT.PINCFG1_16.Set(sam.PORT.PINCFG1_16.Get()&^(0xff<<8) | (uint32(val) << 8))
|
||||
case 50: // PB18
|
||||
sam.PORT.PINCFG1_16 = (sam.PORT.PINCFG1_16 &^ (0xff << 16)) | (sam.RegValue(val) << 16)
|
||||
sam.PORT.PINCFG1_16.Set(sam.PORT.PINCFG1_16.Get()&^(0xff<<16) | (uint32(val) << 16))
|
||||
case 51: // PB19
|
||||
sam.PORT.PINCFG1_16 = (sam.PORT.PINCFG1_16 &^ (0xff << 24)) | (sam.RegValue(val) << 24)
|
||||
sam.PORT.PINCFG1_16.Set(sam.PORT.PINCFG1_16.Get()&^(0xff<<24) | (uint32(val) << 24))
|
||||
case 52: // PB20
|
||||
sam.PORT.PINCFG1_20 = (sam.PORT.PINCFG1_20 &^ (0xff << 0)) | (sam.RegValue(val) << 0)
|
||||
sam.PORT.PINCFG1_20.Set(sam.PORT.PINCFG1_20.Get()&^(0xff<<0) | (uint32(val) << 0))
|
||||
case 53: // PB21
|
||||
sam.PORT.PINCFG1_20 = (sam.PORT.PINCFG1_20 &^ (0xff << 8)) | (sam.RegValue(val) << 8)
|
||||
sam.PORT.PINCFG1_20.Set(sam.PORT.PINCFG1_20.Get()&^(0xff<<8) | (uint32(val) << 8))
|
||||
case 54: // PB22
|
||||
sam.PORT.PINCFG1_20 = (sam.PORT.PINCFG1_20 &^ (0xff << 16)) | (sam.RegValue(val) << 16)
|
||||
sam.PORT.PINCFG1_20.Set(sam.PORT.PINCFG1_20.Get()&^(0xff<<16) | (uint32(val) << 16))
|
||||
case 55: // PB23
|
||||
sam.PORT.PINCFG1_20 = (sam.PORT.PINCFG1_20 &^ (0xff << 24)) | (sam.RegValue(val) << 24)
|
||||
sam.PORT.PINCFG1_20.Set(sam.PORT.PINCFG1_20.Get()&^(0xff<<24) | (uint32(val) << 24))
|
||||
case 56: // PB24
|
||||
sam.PORT.PINCFG1_24 = (sam.PORT.PINCFG1_24 &^ (0xff << 0)) | (sam.RegValue(val) << 0)
|
||||
sam.PORT.PINCFG1_24.Set(sam.PORT.PINCFG1_24.Get()&^(0xff<<0) | (uint32(val) << 0))
|
||||
case 57: // PB25
|
||||
sam.PORT.PINCFG1_24 = (sam.PORT.PINCFG1_24 &^ (0xff << 8)) | (sam.RegValue(val) << 8)
|
||||
sam.PORT.PINCFG1_24.Set(sam.PORT.PINCFG1_24.Get()&^(0xff<<8) | (uint32(val) << 8))
|
||||
case 58: // PB26
|
||||
sam.PORT.PINCFG1_24 = (sam.PORT.PINCFG1_24 &^ (0xff << 16)) | (sam.RegValue(val) << 16)
|
||||
sam.PORT.PINCFG1_24.Set(sam.PORT.PINCFG1_24.Get()&^(0xff<<16) | (uint32(val) << 16))
|
||||
case 59: // PB27
|
||||
sam.PORT.PINCFG1_24 = (sam.PORT.PINCFG1_24 &^ (0xff << 24)) | (sam.RegValue(val) << 24)
|
||||
sam.PORT.PINCFG1_24.Set(sam.PORT.PINCFG1_24.Get()&^(0xff<<24) | (uint32(val) << 24))
|
||||
case 60: // PB28
|
||||
sam.PORT.PINCFG1_28 = (sam.PORT.PINCFG1_28 &^ (0xff << 0)) | (sam.RegValue(val) << 0)
|
||||
sam.PORT.PINCFG1_28.Set(sam.PORT.PINCFG1_28.Get()&^(0xff<<0) | (uint32(val) << 0))
|
||||
case 61: // PB29
|
||||
sam.PORT.PINCFG1_28 = (sam.PORT.PINCFG1_28 &^ (0xff << 8)) | (sam.RegValue(val) << 8)
|
||||
sam.PORT.PINCFG1_28.Set(sam.PORT.PINCFG1_28.Get()&^(0xff<<8) | (uint32(val) << 8))
|
||||
case 62: // PB30
|
||||
sam.PORT.PINCFG1_28 = (sam.PORT.PINCFG1_28 &^ (0xff << 16)) | (sam.RegValue(val) << 16)
|
||||
sam.PORT.PINCFG1_28.Set(sam.PORT.PINCFG1_28.Get()&^(0xff<<16) | (uint32(val) << 16))
|
||||
case 63: // PB31
|
||||
sam.PORT.PINCFG1_28 = (sam.PORT.PINCFG1_28 &^ (0xff << 24)) | (sam.RegValue(val) << 24)
|
||||
sam.PORT.PINCFG1_28.Set(sam.PORT.PINCFG1_28.Get()&^(0xff<<24) | (uint32(val) << 24))
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -484,11 +484,11 @@ const (
|
|||
// RoReg8 Reserved1[0x5];
|
||||
// } UsbDeviceDescBank;
|
||||
type usbDeviceDescBank struct {
|
||||
ADDR sam.RegValue
|
||||
PCKSIZE sam.RegValue
|
||||
EXTREG sam.RegValue16
|
||||
STATUS_BK sam.RegValue8
|
||||
_reserved [5]sam.RegValue8
|
||||
ADDR sam.Register32
|
||||
PCKSIZE sam.Register32
|
||||
EXTREG sam.Register16
|
||||
STATUS_BK sam.Register8
|
||||
_reserved [5]sam.Register8
|
||||
}
|
||||
|
||||
type usbDeviceDescriptor struct {
|
||||
|
|
|
|||
|
|
@ -36,12 +36,12 @@ func putchar(c byte) {
|
|||
|
||||
func initClocks() {
|
||||
// Set 1 Flash Wait State for 48MHz, required for 3.3V operation according to SAMD21 Datasheet
|
||||
sam.NVMCTRL.CTRLB |= (sam.NVMCTRL_CTRLB_RWS_HALF << sam.NVMCTRL_CTRLB_RWS_Pos)
|
||||
sam.NVMCTRL.CTRLB.SetBits(sam.NVMCTRL_CTRLB_RWS_HALF << sam.NVMCTRL_CTRLB_RWS_Pos)
|
||||
|
||||
// Turn on the digital interface clock
|
||||
sam.PM.APBAMASK |= sam.PM_APBAMASK_GCLK_
|
||||
sam.PM.APBAMASK.SetBits(sam.PM_APBAMASK_GCLK_)
|
||||
// turn off RTC
|
||||
sam.PM.APBAMASK &^= sam.PM_APBAMASK_RTC_
|
||||
sam.PM.APBAMASK.ClearBits(sam.PM_APBAMASK_RTC_)
|
||||
|
||||
// Enable OSC32K clock (Internal 32.768Hz oscillator).
|
||||
// This requires registers that are not included in the SVD file.
|
||||
|
|
@ -61,42 +61,42 @@ func initClocks() {
|
|||
// SYSCTRL_OSC32K_CALIB(calib) |
|
||||
// SYSCTRL_OSC32K_STARTUP(0x6u) |
|
||||
// SYSCTRL_OSC32K_EN32K | SYSCTRL_OSC32K_ENABLE;
|
||||
sam.SYSCTRL.OSC32K = sam.RegValue((calib << sam.SYSCTRL_OSC32K_CALIB_Pos) |
|
||||
sam.SYSCTRL.OSC32K.Set((calib << sam.SYSCTRL_OSC32K_CALIB_Pos) |
|
||||
(0x6 << sam.SYSCTRL_OSC32K_STARTUP_Pos) |
|
||||
sam.SYSCTRL_OSC32K_EN32K |
|
||||
sam.SYSCTRL_OSC32K_EN1K |
|
||||
sam.SYSCTRL_OSC32K_ENABLE)
|
||||
// Wait for oscillator stabilization
|
||||
for (sam.SYSCTRL.PCLKSR & sam.SYSCTRL_PCLKSR_OSC32KRDY) == 0 {
|
||||
for (sam.SYSCTRL.PCLKSR.Get() & sam.SYSCTRL_PCLKSR_OSC32KRDY) == 0 {
|
||||
}
|
||||
|
||||
// Software reset the module to ensure it is re-initialized correctly
|
||||
sam.GCLK.CTRL = sam.GCLK_CTRL_SWRST
|
||||
sam.GCLK.CTRL.Set(sam.GCLK_CTRL_SWRST)
|
||||
// Wait for reset to complete
|
||||
for (sam.GCLK.CTRL&sam.GCLK_CTRL_SWRST) > 0 && (sam.GCLK.STATUS&sam.GCLK_STATUS_SYNCBUSY) > 0 {
|
||||
for (sam.GCLK.CTRL.Get()&sam.GCLK_CTRL_SWRST) > 0 && (sam.GCLK.STATUS.Get()&sam.GCLK_STATUS_SYNCBUSY) > 0 {
|
||||
}
|
||||
|
||||
// Put OSC32K as source of Generic Clock Generator 1
|
||||
sam.GCLK.GENDIV = sam.RegValue((1 << sam.GCLK_GENDIV_ID_Pos) |
|
||||
sam.GCLK.GENDIV.Set((1 << sam.GCLK_GENDIV_ID_Pos) |
|
||||
(0 << sam.GCLK_GENDIV_DIV_Pos))
|
||||
waitForSync()
|
||||
|
||||
// GCLK_GENCTRL_ID(1) | GCLK_GENCTRL_SRC_OSC32K | GCLK_GENCTRL_GENEN;
|
||||
sam.GCLK.GENCTRL = sam.RegValue((1 << sam.GCLK_GENCTRL_ID_Pos) |
|
||||
sam.GCLK.GENCTRL.Set((1 << sam.GCLK_GENCTRL_ID_Pos) |
|
||||
(sam.GCLK_GENCTRL_SRC_OSC32K << sam.GCLK_GENCTRL_SRC_Pos) |
|
||||
sam.GCLK_GENCTRL_GENEN)
|
||||
waitForSync()
|
||||
|
||||
// Use Generic Clock Generator 1 as source for Generic Clock Multiplexer 0 (DFLL48M reference)
|
||||
sam.GCLK.CLKCTRL = sam.RegValue16((sam.GCLK_CLKCTRL_ID_DFLL48 << sam.GCLK_CLKCTRL_ID_Pos) |
|
||||
sam.GCLK.CLKCTRL.Set((sam.GCLK_CLKCTRL_ID_DFLL48 << sam.GCLK_CLKCTRL_ID_Pos) |
|
||||
(sam.GCLK_CLKCTRL_GEN_GCLK1 << sam.GCLK_CLKCTRL_GEN_Pos) |
|
||||
sam.GCLK_CLKCTRL_CLKEN)
|
||||
waitForSync()
|
||||
|
||||
// Remove the OnDemand mode, Bug http://avr32.icgroup.norway.atmel.com/bugzilla/show_bug.cgi?id=9905
|
||||
sam.SYSCTRL.DFLLCTRL = sam.SYSCTRL_DFLLCTRL_ENABLE
|
||||
sam.SYSCTRL.DFLLCTRL.Set(sam.SYSCTRL_DFLLCTRL_ENABLE)
|
||||
// Wait for ready
|
||||
for (sam.SYSCTRL.PCLKSR & sam.SYSCTRL_PCLKSR_DFLLRDY) == 0 {
|
||||
for (sam.SYSCTRL.PCLKSR.Get() & sam.SYSCTRL_PCLKSR_DFLLRDY) == 0 {
|
||||
}
|
||||
|
||||
// Handle DFLL calibration based on info learned from Arduino SAMD implementation,
|
||||
|
|
@ -110,107 +110,107 @@ func initClocks() {
|
|||
coarse = 0x1f
|
||||
}
|
||||
|
||||
sam.SYSCTRL.DFLLVAL |= sam.RegValue(coarse << sam.SYSCTRL_DFLLVAL_COARSE_Pos)
|
||||
sam.SYSCTRL.DFLLVAL |= (0x1ff << sam.SYSCTRL_DFLLVAL_FINE_Pos)
|
||||
sam.SYSCTRL.DFLLVAL.SetBits(coarse << sam.SYSCTRL_DFLLVAL_COARSE_Pos)
|
||||
sam.SYSCTRL.DFLLVAL.SetBits(0x1ff << sam.SYSCTRL_DFLLVAL_FINE_Pos)
|
||||
|
||||
// Write full configuration to DFLL control register
|
||||
// SYSCTRL_DFLLMUL_CSTEP( 0x1f / 4 ) | // Coarse step is 31, half of the max value
|
||||
// SYSCTRL_DFLLMUL_FSTEP( 10 ) |
|
||||
// SYSCTRL_DFLLMUL_MUL( (48000) ) ;
|
||||
sam.SYSCTRL.DFLLMUL = sam.RegValue(((31 / 4) << sam.SYSCTRL_DFLLMUL_CSTEP_Pos) |
|
||||
sam.SYSCTRL.DFLLMUL.Set(((31 / 4) << sam.SYSCTRL_DFLLMUL_CSTEP_Pos) |
|
||||
(10 << sam.SYSCTRL_DFLLMUL_FSTEP_Pos) |
|
||||
(48000 << sam.SYSCTRL_DFLLMUL_MUL_Pos))
|
||||
|
||||
// disable DFLL
|
||||
sam.SYSCTRL.DFLLCTRL = 0
|
||||
sam.SYSCTRL.DFLLCTRL.Set(0)
|
||||
waitForSync()
|
||||
|
||||
sam.SYSCTRL.DFLLCTRL |= sam.SYSCTRL_DFLLCTRL_MODE |
|
||||
sam.SYSCTRL.DFLLCTRL.SetBits(sam.SYSCTRL_DFLLCTRL_MODE |
|
||||
sam.SYSCTRL_DFLLCTRL_CCDIS |
|
||||
sam.SYSCTRL_DFLLCTRL_USBCRM |
|
||||
sam.SYSCTRL_DFLLCTRL_BPLCKC
|
||||
sam.SYSCTRL_DFLLCTRL_BPLCKC)
|
||||
// Wait for ready
|
||||
for (sam.SYSCTRL.PCLKSR & sam.SYSCTRL_PCLKSR_DFLLRDY) == 0 {
|
||||
for (sam.SYSCTRL.PCLKSR.Get() & sam.SYSCTRL_PCLKSR_DFLLRDY) == 0 {
|
||||
}
|
||||
|
||||
// Re-enable the DFLL
|
||||
sam.SYSCTRL.DFLLCTRL |= sam.SYSCTRL_DFLLCTRL_ENABLE
|
||||
sam.SYSCTRL.DFLLCTRL.SetBits(sam.SYSCTRL_DFLLCTRL_ENABLE)
|
||||
// Wait for ready
|
||||
for (sam.SYSCTRL.PCLKSR & sam.SYSCTRL_PCLKSR_DFLLRDY) == 0 {
|
||||
for (sam.SYSCTRL.PCLKSR.Get() & sam.SYSCTRL_PCLKSR_DFLLRDY) == 0 {
|
||||
}
|
||||
|
||||
// Switch Generic Clock Generator 0 to DFLL48M. CPU will run at 48MHz.
|
||||
sam.GCLK.GENDIV = sam.RegValue((0 << sam.GCLK_GENDIV_ID_Pos) |
|
||||
sam.GCLK.GENDIV.Set((0 << sam.GCLK_GENDIV_ID_Pos) |
|
||||
(0 << sam.GCLK_GENDIV_DIV_Pos))
|
||||
waitForSync()
|
||||
|
||||
sam.GCLK.GENCTRL = sam.RegValue((0 << sam.GCLK_GENCTRL_ID_Pos) |
|
||||
sam.GCLK.GENCTRL.Set((0 << sam.GCLK_GENCTRL_ID_Pos) |
|
||||
(sam.GCLK_GENCTRL_SRC_DFLL48M << sam.GCLK_GENCTRL_SRC_Pos) |
|
||||
sam.GCLK_GENCTRL_IDC |
|
||||
sam.GCLK_GENCTRL_GENEN)
|
||||
waitForSync()
|
||||
|
||||
// Modify PRESCaler value of OSC8M to have 8MHz
|
||||
sam.SYSCTRL.OSC8M |= (sam.SYSCTRL_OSC8M_PRESC_0 << sam.SYSCTRL_OSC8M_PRESC_Pos)
|
||||
sam.SYSCTRL.OSC8M &^= (1 << sam.SYSCTRL_OSC8M_ONDEMAND_Pos)
|
||||
sam.SYSCTRL.OSC8M.SetBits(sam.SYSCTRL_OSC8M_PRESC_0 << sam.SYSCTRL_OSC8M_PRESC_Pos)
|
||||
sam.SYSCTRL.OSC8M.ClearBits(1 << sam.SYSCTRL_OSC8M_ONDEMAND_Pos)
|
||||
// Wait for oscillator stabilization
|
||||
for (sam.SYSCTRL.PCLKSR & sam.SYSCTRL_PCLKSR_OSC8MRDY) == 0 {
|
||||
for (sam.SYSCTRL.PCLKSR.Get() & sam.SYSCTRL_PCLKSR_OSC8MRDY) == 0 {
|
||||
}
|
||||
|
||||
// Use OSC8M as source for Generic Clock Generator 3
|
||||
sam.GCLK.GENDIV = sam.RegValue((3 << sam.GCLK_GENDIV_ID_Pos))
|
||||
sam.GCLK.GENDIV.Set((3 << sam.GCLK_GENDIV_ID_Pos))
|
||||
waitForSync()
|
||||
|
||||
sam.GCLK.GENCTRL = sam.RegValue((3 << sam.GCLK_GENCTRL_ID_Pos) |
|
||||
sam.GCLK.GENCTRL.Set((3 << sam.GCLK_GENCTRL_ID_Pos) |
|
||||
(sam.GCLK_GENCTRL_SRC_OSC8M << sam.GCLK_GENCTRL_SRC_Pos) |
|
||||
sam.GCLK_GENCTRL_GENEN)
|
||||
waitForSync()
|
||||
|
||||
// Use OSC32K as source for Generic Clock Generator 2
|
||||
// OSC32K/1 -> GCLK2 at 32KHz
|
||||
sam.GCLK.GENDIV = sam.RegValue(2 << sam.GCLK_GENDIV_ID_Pos)
|
||||
sam.GCLK.GENDIV.Set(2 << sam.GCLK_GENDIV_ID_Pos)
|
||||
waitForSync()
|
||||
|
||||
sam.GCLK.GENCTRL = sam.RegValue((2 << sam.GCLK_GENCTRL_ID_Pos) |
|
||||
sam.GCLK.GENCTRL.Set((2 << sam.GCLK_GENCTRL_ID_Pos) |
|
||||
(sam.GCLK_GENCTRL_SRC_OSC32K << sam.GCLK_GENCTRL_SRC_Pos) |
|
||||
sam.GCLK_GENCTRL_GENEN)
|
||||
waitForSync()
|
||||
|
||||
// Use GCLK2 for RTC
|
||||
sam.GCLK.CLKCTRL = sam.RegValue16((sam.GCLK_CLKCTRL_ID_RTC << sam.GCLK_CLKCTRL_ID_Pos) |
|
||||
sam.GCLK.CLKCTRL.Set((sam.GCLK_CLKCTRL_ID_RTC << sam.GCLK_CLKCTRL_ID_Pos) |
|
||||
(sam.GCLK_CLKCTRL_GEN_GCLK2 << sam.GCLK_CLKCTRL_GEN_Pos) |
|
||||
sam.GCLK_CLKCTRL_CLKEN)
|
||||
waitForSync()
|
||||
|
||||
// Set the CPU, APBA, B, and C dividers
|
||||
sam.PM.CPUSEL = sam.PM_CPUSEL_CPUDIV_DIV1
|
||||
sam.PM.APBASEL = sam.PM_APBASEL_APBADIV_DIV1
|
||||
sam.PM.APBBSEL = sam.PM_APBBSEL_APBBDIV_DIV1
|
||||
sam.PM.APBCSEL = sam.PM_APBCSEL_APBCDIV_DIV1
|
||||
sam.PM.CPUSEL.Set(sam.PM_CPUSEL_CPUDIV_DIV1)
|
||||
sam.PM.APBASEL.Set(sam.PM_APBASEL_APBADIV_DIV1)
|
||||
sam.PM.APBBSEL.Set(sam.PM_APBBSEL_APBBDIV_DIV1)
|
||||
sam.PM.APBCSEL.Set(sam.PM_APBCSEL_APBCDIV_DIV1)
|
||||
|
||||
// Disable automatic NVM write operations
|
||||
sam.NVMCTRL.CTRLB |= sam.NVMCTRL_CTRLB_MANW
|
||||
sam.NVMCTRL.CTRLB.SetBits(sam.NVMCTRL_CTRLB_MANW)
|
||||
}
|
||||
|
||||
func initRTC() {
|
||||
// turn on digital interface clock
|
||||
sam.PM.APBAMASK |= sam.PM_APBAMASK_RTC_
|
||||
sam.PM.APBAMASK.SetBits(sam.PM_APBAMASK_RTC_)
|
||||
|
||||
// disable RTC
|
||||
sam.RTC_MODE0.CTRL = 0
|
||||
sam.RTC_MODE0.CTRL.Set(0)
|
||||
waitForSync()
|
||||
|
||||
// reset RTC
|
||||
sam.RTC_MODE0.CTRL |= sam.RTC_MODE0_CTRL_SWRST
|
||||
sam.RTC_MODE0.CTRL.SetBits(sam.RTC_MODE0_CTRL_SWRST)
|
||||
waitForSync()
|
||||
|
||||
// set Mode0 to 32-bit counter (mode 0) with prescaler 1 and GCLK2 is 32KHz/1
|
||||
sam.RTC_MODE0.CTRL = sam.RegValue16((sam.RTC_MODE0_CTRL_MODE_COUNT32 << sam.RTC_MODE0_CTRL_MODE_Pos) |
|
||||
sam.RTC_MODE0.CTRL.Set((sam.RTC_MODE0_CTRL_MODE_COUNT32 << sam.RTC_MODE0_CTRL_MODE_Pos) |
|
||||
(sam.RTC_MODE0_CTRL_PRESCALER_DIV1 << sam.RTC_MODE0_CTRL_PRESCALER_Pos))
|
||||
waitForSync()
|
||||
|
||||
// re-enable RTC
|
||||
sam.RTC_MODE0.CTRL |= sam.RTC_MODE0_CTRL_ENABLE
|
||||
sam.RTC_MODE0.CTRL.SetBits(sam.RTC_MODE0_CTRL_ENABLE)
|
||||
waitForSync()
|
||||
|
||||
arm.SetPriority(sam.IRQ_RTC, 0xc0)
|
||||
|
|
@ -218,7 +218,7 @@ func initRTC() {
|
|||
}
|
||||
|
||||
func waitForSync() {
|
||||
for (sam.GCLK.STATUS & sam.GCLK_STATUS_SYNCBUSY) > 0 {
|
||||
for (sam.GCLK.STATUS.Get() & sam.GCLK_STATUS_SYNCBUSY) > 0 {
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -250,11 +250,11 @@ func sleepTicks(d timeUnit) {
|
|||
// ticks returns number of microseconds since start.
|
||||
func ticks() timeUnit {
|
||||
// request read of count
|
||||
sam.RTC_MODE0.READREQ = sam.RTC_MODE0_READREQ_RREQ
|
||||
sam.RTC_MODE0.READREQ.Set(sam.RTC_MODE0_READREQ_RREQ)
|
||||
waitForSync()
|
||||
|
||||
rtcCounter := (uint64(sam.RTC_MODE0.COUNT) * 305) / 10 // each counter tick == 30.5us
|
||||
offset := (rtcCounter - timerLastCounter) // change since last measurement
|
||||
rtcCounter := (uint64(sam.RTC_MODE0.COUNT.Get()) * 305) / 10 // each counter tick == 30.5us
|
||||
offset := (rtcCounter - timerLastCounter) // change since last measurement
|
||||
timerLastCounter = rtcCounter
|
||||
timestamp += timeUnit(offset) // TODO: not precise
|
||||
return timestamp
|
||||
|
|
@ -269,16 +269,16 @@ func timerSleep(ticks uint32) {
|
|||
}
|
||||
|
||||
// request read of count
|
||||
sam.RTC_MODE0.READREQ = sam.RTC_MODE0_READREQ_RREQ
|
||||
sam.RTC_MODE0.READREQ.Set(sam.RTC_MODE0_READREQ_RREQ)
|
||||
waitForSync()
|
||||
|
||||
// set compare value
|
||||
cnt := sam.RTC_MODE0.COUNT
|
||||
sam.RTC_MODE0.COMP0 = sam.RegValue(uint32(cnt) + (ticks * 10 / 305)) // each counter tick == 30.5us
|
||||
cnt := sam.RTC_MODE0.COUNT.Get()
|
||||
sam.RTC_MODE0.COMP0.Set(uint32(cnt) + (ticks * 10 / 305)) // each counter tick == 30.5us
|
||||
waitForSync()
|
||||
|
||||
// enable IRQ for CMP0 compare
|
||||
sam.RTC_MODE0.INTENSET |= sam.RTC_MODE0_INTENSET_CMP0
|
||||
sam.RTC_MODE0.INTENSET.SetBits(sam.RTC_MODE0_INTENSET_CMP0)
|
||||
|
||||
for !timerWakeup {
|
||||
arm.Asm("wfi")
|
||||
|
|
@ -288,17 +288,17 @@ func timerSleep(ticks uint32) {
|
|||
//go:export RTC_IRQHandler
|
||||
func handleRTC() {
|
||||
// disable IRQ for CMP0 compare
|
||||
sam.RTC_MODE0.INTFLAG = sam.RTC_MODE0_INTENSET_CMP0
|
||||
sam.RTC_MODE0.INTFLAG.Set(sam.RTC_MODE0_INTENSET_CMP0)
|
||||
|
||||
timerWakeup = true
|
||||
}
|
||||
|
||||
func initUSBClock() {
|
||||
// Turn on clock for USB
|
||||
sam.PM.APBBMASK |= sam.PM_APBBMASK_USB_
|
||||
sam.PM.APBBMASK.SetBits(sam.PM_APBBMASK_USB_)
|
||||
|
||||
// Put Generic Clock Generator 0 as source for Generic Clock Multiplexer 6 (USB reference)
|
||||
sam.GCLK.CLKCTRL = sam.RegValue16((sam.GCLK_CLKCTRL_ID_USB << sam.GCLK_CLKCTRL_ID_Pos) |
|
||||
sam.GCLK.CLKCTRL.Set((sam.GCLK_CLKCTRL_ID_USB << sam.GCLK_CLKCTRL_ID_Pos) |
|
||||
(sam.GCLK_CLKCTRL_GEN_GCLK0 << sam.GCLK_CLKCTRL_GEN_Pos) |
|
||||
sam.GCLK_CLKCTRL_CLKEN)
|
||||
waitForSync()
|
||||
|
|
@ -306,10 +306,10 @@ func initUSBClock() {
|
|||
|
||||
func initADCClock() {
|
||||
// Turn on clock for ADC
|
||||
sam.PM.APBCMASK |= sam.PM_APBCMASK_ADC_
|
||||
sam.PM.APBCMASK.SetBits(sam.PM_APBCMASK_ADC_)
|
||||
|
||||
// Put Generic Clock Generator 0 as source for Generic Clock Multiplexer for ADC.
|
||||
sam.GCLK.CLKCTRL = sam.RegValue16((sam.GCLK_CLKCTRL_ID_ADC << sam.GCLK_CLKCTRL_ID_Pos) |
|
||||
sam.GCLK.CLKCTRL.Set((sam.GCLK_CLKCTRL_ID_ADC << sam.GCLK_CLKCTRL_ID_Pos) |
|
||||
(sam.GCLK_CLKCTRL_GEN_GCLK0 << sam.GCLK_CLKCTRL_GEN_Pos) |
|
||||
sam.GCLK_CLKCTRL_CLKEN)
|
||||
waitForSync()
|
||||
|
|
|
|||
|
|
@ -8,34 +8,34 @@ import (
|
|||
|
||||
func initSERCOMClocks() {
|
||||
// Turn on clock to SERCOM0 for UART0
|
||||
sam.PM.APBCMASK |= sam.PM_APBCMASK_SERCOM0_
|
||||
sam.PM.APBCMASK.SetBits(sam.PM_APBCMASK_SERCOM0_)
|
||||
|
||||
// Use GCLK0 for SERCOM0 aka UART0
|
||||
// GCLK_CLKCTRL_ID( clockId ) | // Generic Clock 0 (SERCOMx)
|
||||
// GCLK_CLKCTRL_GEN_GCLK0 | // Generic Clock Generator 0 is source
|
||||
// GCLK_CLKCTRL_CLKEN ;
|
||||
sam.GCLK.CLKCTRL = sam.RegValue16((sam.GCLK_CLKCTRL_ID_SERCOM0_CORE << sam.GCLK_CLKCTRL_ID_Pos) |
|
||||
sam.GCLK.CLKCTRL.Set((sam.GCLK_CLKCTRL_ID_SERCOM0_CORE << sam.GCLK_CLKCTRL_ID_Pos) |
|
||||
(sam.GCLK_CLKCTRL_GEN_GCLK0 << sam.GCLK_CLKCTRL_GEN_Pos) |
|
||||
sam.GCLK_CLKCTRL_CLKEN)
|
||||
waitForSync()
|
||||
|
||||
// Turn on clock to SERCOM1
|
||||
sam.PM.APBCMASK |= sam.PM_APBCMASK_SERCOM1_
|
||||
sam.GCLK.CLKCTRL = sam.RegValue16((sam.GCLK_CLKCTRL_ID_SERCOM1_CORE << sam.GCLK_CLKCTRL_ID_Pos) |
|
||||
sam.PM.APBCMASK.SetBits(sam.PM_APBCMASK_SERCOM1_)
|
||||
sam.GCLK.CLKCTRL.Set((sam.GCLK_CLKCTRL_ID_SERCOM1_CORE << sam.GCLK_CLKCTRL_ID_Pos) |
|
||||
(sam.GCLK_CLKCTRL_GEN_GCLK0 << sam.GCLK_CLKCTRL_GEN_Pos) |
|
||||
sam.GCLK_CLKCTRL_CLKEN)
|
||||
waitForSync()
|
||||
|
||||
// Turn on clock to SERCOM2
|
||||
sam.PM.APBCMASK |= sam.PM_APBCMASK_SERCOM2_
|
||||
sam.GCLK.CLKCTRL = sam.RegValue16((sam.GCLK_CLKCTRL_ID_SERCOM2_CORE << sam.GCLK_CLKCTRL_ID_Pos) |
|
||||
sam.PM.APBCMASK.SetBits(sam.PM_APBCMASK_SERCOM2_)
|
||||
sam.GCLK.CLKCTRL.Set((sam.GCLK_CLKCTRL_ID_SERCOM2_CORE << sam.GCLK_CLKCTRL_ID_Pos) |
|
||||
(sam.GCLK_CLKCTRL_GEN_GCLK0 << sam.GCLK_CLKCTRL_GEN_Pos) |
|
||||
sam.GCLK_CLKCTRL_CLKEN)
|
||||
waitForSync()
|
||||
|
||||
// Turn on clock to SERCOM3
|
||||
sam.PM.APBCMASK |= sam.PM_APBCMASK_SERCOM3_
|
||||
sam.GCLK.CLKCTRL = sam.RegValue16((sam.GCLK_CLKCTRL_ID_SERCOM3_CORE << sam.GCLK_CLKCTRL_ID_Pos) |
|
||||
sam.PM.APBCMASK.SetBits(sam.PM_APBCMASK_SERCOM3_)
|
||||
sam.GCLK.CLKCTRL.Set((sam.GCLK_CLKCTRL_ID_SERCOM3_CORE << sam.GCLK_CLKCTRL_ID_Pos) |
|
||||
(sam.GCLK_CLKCTRL_GEN_GCLK0 << sam.GCLK_CLKCTRL_GEN_Pos) |
|
||||
sam.GCLK_CLKCTRL_CLKEN)
|
||||
waitForSync()
|
||||
|
|
|
|||
|
|
@ -8,52 +8,52 @@ import (
|
|||
|
||||
func initSERCOMClocks() {
|
||||
// Turn on clock to SERCOM0 for UART0
|
||||
sam.PM.APBCMASK |= sam.PM_APBCMASK_SERCOM0_
|
||||
sam.PM.APBCMASK.SetBits(sam.PM_APBCMASK_SERCOM0_)
|
||||
|
||||
// Use GCLK0 for SERCOM0 aka UART0
|
||||
// GCLK_CLKCTRL_ID( clockId ) | // Generic Clock 0 (SERCOMx)
|
||||
// GCLK_CLKCTRL_GEN_GCLK0 | // Generic Clock Generator 0 is source
|
||||
// GCLK_CLKCTRL_CLKEN ;
|
||||
sam.GCLK.CLKCTRL = sam.RegValue16((sam.GCLK_CLKCTRL_ID_SERCOM0_CORE << sam.GCLK_CLKCTRL_ID_Pos) |
|
||||
sam.GCLK.CLKCTRL.Set((sam.GCLK_CLKCTRL_ID_SERCOM0_CORE << sam.GCLK_CLKCTRL_ID_Pos) |
|
||||
(sam.GCLK_CLKCTRL_GEN_GCLK0 << sam.GCLK_CLKCTRL_GEN_Pos) |
|
||||
sam.GCLK_CLKCTRL_CLKEN)
|
||||
waitForSync()
|
||||
|
||||
// Turn on clock to SERCOM1
|
||||
sam.PM.APBCMASK |= sam.PM_APBCMASK_SERCOM1_
|
||||
sam.GCLK.CLKCTRL = sam.RegValue16((sam.GCLK_CLKCTRL_ID_SERCOM1_CORE << sam.GCLK_CLKCTRL_ID_Pos) |
|
||||
sam.PM.APBCMASK.SetBits(sam.PM_APBCMASK_SERCOM1_)
|
||||
sam.GCLK.CLKCTRL.Set((sam.GCLK_CLKCTRL_ID_SERCOM1_CORE << sam.GCLK_CLKCTRL_ID_Pos) |
|
||||
(sam.GCLK_CLKCTRL_GEN_GCLK0 << sam.GCLK_CLKCTRL_GEN_Pos) |
|
||||
sam.GCLK_CLKCTRL_CLKEN)
|
||||
waitForSync()
|
||||
|
||||
// Turn on clock to SERCOM2
|
||||
sam.PM.APBCMASK |= sam.PM_APBCMASK_SERCOM2_
|
||||
sam.GCLK.CLKCTRL = sam.RegValue16((sam.GCLK_CLKCTRL_ID_SERCOM2_CORE << sam.GCLK_CLKCTRL_ID_Pos) |
|
||||
sam.PM.APBCMASK.SetBits(sam.PM_APBCMASK_SERCOM2_)
|
||||
sam.GCLK.CLKCTRL.Set((sam.GCLK_CLKCTRL_ID_SERCOM2_CORE << sam.GCLK_CLKCTRL_ID_Pos) |
|
||||
(sam.GCLK_CLKCTRL_GEN_GCLK0 << sam.GCLK_CLKCTRL_GEN_Pos) |
|
||||
sam.GCLK_CLKCTRL_CLKEN)
|
||||
waitForSync()
|
||||
|
||||
// Turn on clock to SERCOM3
|
||||
sam.PM.APBCMASK |= sam.PM_APBCMASK_SERCOM3_
|
||||
sam.GCLK.CLKCTRL = sam.RegValue16((sam.GCLK_CLKCTRL_ID_SERCOM3_CORE << sam.GCLK_CLKCTRL_ID_Pos) |
|
||||
sam.PM.APBCMASK.SetBits(sam.PM_APBCMASK_SERCOM3_)
|
||||
sam.GCLK.CLKCTRL.Set((sam.GCLK_CLKCTRL_ID_SERCOM3_CORE << sam.GCLK_CLKCTRL_ID_Pos) |
|
||||
(sam.GCLK_CLKCTRL_GEN_GCLK0 << sam.GCLK_CLKCTRL_GEN_Pos) |
|
||||
sam.GCLK_CLKCTRL_CLKEN)
|
||||
waitForSync()
|
||||
|
||||
// Turn on clock to SERCOM4
|
||||
sam.PM.APBCMASK |= sam.PM_APBCMASK_SERCOM4_
|
||||
sam.PM.APBCMASK.SetBits(sam.PM_APBCMASK_SERCOM4_)
|
||||
|
||||
// Use GCLK0 for SERCOM4
|
||||
sam.GCLK.CLKCTRL = sam.RegValue16((sam.GCLK_CLKCTRL_ID_SERCOM4_CORE << sam.GCLK_CLKCTRL_ID_Pos) |
|
||||
sam.GCLK.CLKCTRL.Set((sam.GCLK_CLKCTRL_ID_SERCOM4_CORE << sam.GCLK_CLKCTRL_ID_Pos) |
|
||||
(sam.GCLK_CLKCTRL_GEN_GCLK0 << sam.GCLK_CLKCTRL_GEN_Pos) |
|
||||
sam.GCLK_CLKCTRL_CLKEN)
|
||||
waitForSync()
|
||||
|
||||
// Turn on clock to SERCOM5
|
||||
sam.PM.APBCMASK |= sam.PM_APBCMASK_SERCOM5_
|
||||
sam.PM.APBCMASK.SetBits(sam.PM_APBCMASK_SERCOM5_)
|
||||
|
||||
// Use GCLK0 for SERCOM5
|
||||
sam.GCLK.CLKCTRL = sam.RegValue16((sam.GCLK_CLKCTRL_ID_SERCOM5_CORE << sam.GCLK_CLKCTRL_ID_Pos) |
|
||||
sam.GCLK.CLKCTRL.Set((sam.GCLK_CLKCTRL_ID_SERCOM5_CORE << sam.GCLK_CLKCTRL_ID_Pos) |
|
||||
(sam.GCLK_CLKCTRL_GEN_GCLK0 << sam.GCLK_CLKCTRL_GEN_Pos) |
|
||||
sam.GCLK_CLKCTRL_CLKEN)
|
||||
waitForSync()
|
||||
|
|
|
|||
692
tools/gen-device-svd-vol.py
Исполняемый файл
692
tools/gen-device-svd-vol.py
Исполняемый файл
|
|
@ -0,0 +1,692 @@
|
|||
#!/usr/bin/env python3
|
||||
|
||||
import sys
|
||||
import os
|
||||
from xml.etree import ElementTree
|
||||
from glob import glob
|
||||
from collections import OrderedDict
|
||||
import re
|
||||
import argparse
|
||||
|
||||
class Device:
|
||||
# dummy
|
||||
pass
|
||||
|
||||
def getText(element):
|
||||
if element is None:
|
||||
return "None"
|
||||
return ''.join(element.itertext())
|
||||
|
||||
def formatText(text):
|
||||
text = re.sub('[ \t\n]+', ' ', text) # Collapse whitespace (like in HTML)
|
||||
text = text.replace('\\n ', '\n')
|
||||
text = text.strip()
|
||||
return text
|
||||
|
||||
def readSVD(path, sourceURL):
|
||||
# Read ARM SVD files.
|
||||
device = Device()
|
||||
xml = ElementTree.parse(path)
|
||||
root = xml.getroot()
|
||||
deviceName = getText(root.find('name'))
|
||||
deviceDescription = getText(root.find('description')).strip()
|
||||
licenseTexts = root.findall('licenseText')
|
||||
if len(licenseTexts) == 0:
|
||||
licenseText = None
|
||||
elif len(licenseTexts) == 1:
|
||||
licenseText = formatText(getText(licenseTexts[0]))
|
||||
else:
|
||||
raise ValueError('multiple <licenseText> elements')
|
||||
|
||||
device.peripherals = []
|
||||
peripheralDict = {}
|
||||
groups = {}
|
||||
|
||||
interrupts = OrderedDict()
|
||||
|
||||
for periphEl in root.findall('./peripherals/peripheral'):
|
||||
name = getText(periphEl.find('name'))
|
||||
descriptionTags = periphEl.findall('description')
|
||||
description = ''
|
||||
if descriptionTags:
|
||||
description = formatText(getText(descriptionTags[0]))
|
||||
baseAddress = int(getText(periphEl.find('baseAddress')), 0)
|
||||
groupNameTags = periphEl.findall('groupName')
|
||||
groupName = None
|
||||
if groupNameTags:
|
||||
groupName = getText(groupNameTags[0])
|
||||
|
||||
interruptEls = periphEl.findall('interrupt')
|
||||
for interrupt in interruptEls:
|
||||
intrName = getText(interrupt.find('name'))
|
||||
intrIndex = int(getText(interrupt.find('value')))
|
||||
addInterrupt(interrupts, intrName, intrIndex, description)
|
||||
# As a convenience, also use the peripheral name as the interrupt
|
||||
# name. Only do that for the nrf for now, as the stm32 .svd files
|
||||
# don't always put interrupts in the correct peripheral...
|
||||
if len(interruptEls) == 1 and deviceName.startswith('nrf'):
|
||||
addInterrupt(interrupts, name, intrIndex, description)
|
||||
|
||||
if periphEl.get('derivedFrom') or groupName in groups:
|
||||
if periphEl.get('derivedFrom'):
|
||||
derivedFromName = periphEl.get('derivedFrom')
|
||||
derivedFrom = peripheralDict[derivedFromName]
|
||||
else:
|
||||
derivedFrom = groups[groupName]
|
||||
peripheral = {
|
||||
'name': name,
|
||||
'groupName': derivedFrom['groupName'],
|
||||
'description': description or derivedFrom['description'],
|
||||
'baseAddress': baseAddress,
|
||||
}
|
||||
device.peripherals.append(peripheral)
|
||||
peripheralDict[name] = peripheral
|
||||
if 'subtypes' in derivedFrom:
|
||||
for subtype in derivedFrom['subtypes']:
|
||||
subp = {
|
||||
'name': name + "_"+subtype['clusterName'],
|
||||
'groupName': subtype['groupName'],
|
||||
'description': subtype['description'],
|
||||
'baseAddress': baseAddress,
|
||||
}
|
||||
device.peripherals.append(subp)
|
||||
continue
|
||||
|
||||
peripheral = {
|
||||
'name': name,
|
||||
'groupName': groupName or name,
|
||||
'description': description,
|
||||
'baseAddress': baseAddress,
|
||||
'registers': [],
|
||||
'subtypes': [],
|
||||
}
|
||||
device.peripherals.append(peripheral)
|
||||
peripheralDict[name] = peripheral
|
||||
|
||||
if groupName and groupName not in groups:
|
||||
groups[groupName] = peripheral
|
||||
|
||||
regsEls = periphEl.findall('registers')
|
||||
if regsEls:
|
||||
if len(regsEls) != 1:
|
||||
raise ValueError('expected just one <registers> in a <peripheral>')
|
||||
for register in regsEls[0].findall('register'):
|
||||
peripheral['registers'].extend(parseRegister(groupName or name, register, baseAddress))
|
||||
for cluster in regsEls[0].findall('cluster'):
|
||||
clusterName = getText(cluster.find('name')).replace('[%s]', '')
|
||||
clusterDescription = getText(cluster.find('description'))
|
||||
clusterPrefix = clusterName + '_'
|
||||
clusterOffset = int(getText(cluster.find('addressOffset')), 0)
|
||||
if cluster.find('dim') is None:
|
||||
if clusterOffset is 0:
|
||||
# make this a separate peripheral
|
||||
cpRegisters = []
|
||||
for regEl in cluster.findall('register'):
|
||||
cpRegisters.extend(parseRegister(groupName, regEl, baseAddress, clusterName+"_"))
|
||||
cpRegisters.sort(key=lambda r: r['address'])
|
||||
clusterPeripheral = {
|
||||
'name': name+ "_" +clusterName,
|
||||
'groupName': groupName+ "_" +clusterName,
|
||||
'description': description+ " - " +clusterName,
|
||||
'clusterName': clusterName,
|
||||
'baseAddress': baseAddress,
|
||||
'registers': cpRegisters,
|
||||
}
|
||||
device.peripherals.append(clusterPeripheral)
|
||||
peripheral['subtypes'].append(clusterPeripheral)
|
||||
continue
|
||||
dim = None
|
||||
dimIncrement = None
|
||||
else:
|
||||
dim = int(getText(cluster.find('dim')))
|
||||
dimIncrement = int(getText(cluster.find('dimIncrement')), 0)
|
||||
clusterRegisters = []
|
||||
for regEl in cluster.findall('register'):
|
||||
clusterRegisters.extend(parseRegister(groupName or name, regEl, baseAddress + clusterOffset, clusterPrefix))
|
||||
clusterRegisters.sort(key=lambda r: r['address'])
|
||||
if dimIncrement is None:
|
||||
lastReg = clusterRegisters[-1]
|
||||
lastAddress = lastReg['address']
|
||||
if lastReg['array'] is not None:
|
||||
lastAddress = lastReg['address'] + lastReg['array'] * lastReg['elementsize']
|
||||
firstAddress = clusterRegisters[0]['address']
|
||||
dimIncrement = lastAddress - firstAddress
|
||||
peripheral['registers'].append({
|
||||
'name': clusterName,
|
||||
'address': baseAddress + clusterOffset,
|
||||
'description': clusterDescription,
|
||||
'registers': clusterRegisters,
|
||||
'array': dim,
|
||||
'elementsize': dimIncrement,
|
||||
})
|
||||
peripheral['registers'].sort(key=lambda r: r['address'])
|
||||
|
||||
device.interrupts = sorted(interrupts.values(), key=lambda v: v['index'])
|
||||
licenseBlock = ''
|
||||
if licenseText is not None:
|
||||
licenseBlock = '// ' + licenseText.replace('\n', '\n// ')
|
||||
licenseBlock = '\n'.join(map(str.rstrip, licenseBlock.split('\n'))) # strip trailing whitespace
|
||||
device.metadata = {
|
||||
'file': os.path.basename(path),
|
||||
'descriptorSource': sourceURL,
|
||||
'name': deviceName,
|
||||
'nameLower': deviceName.lower(),
|
||||
'description': deviceDescription,
|
||||
'licenseBlock': licenseBlock,
|
||||
}
|
||||
|
||||
return device
|
||||
|
||||
def addInterrupt(interrupts, intrName, intrIndex, description):
|
||||
if intrName in interrupts:
|
||||
if interrupts[intrName]['index'] != intrIndex:
|
||||
raise ValueError('interrupt with the same name has different indexes: %s (%d vs %d)'
|
||||
% (intrName, interrupts[intrName]['index'], intrIndex))
|
||||
if description not in interrupts[intrName]['description'].split(' // '):
|
||||
interrupts[intrName]['description'] += ' // ' + description
|
||||
else:
|
||||
interrupts[intrName] = {
|
||||
'name': intrName,
|
||||
'index': intrIndex,
|
||||
'description': description,
|
||||
}
|
||||
|
||||
def parseBitfields(groupName, regName, fieldsEls, bitfieldPrefix=''):
|
||||
fields = []
|
||||
if fieldsEls:
|
||||
for fieldEl in fieldsEls[0].findall('field'):
|
||||
fieldName = getText(fieldEl.find('name'))
|
||||
descrEls = fieldEl.findall('description')
|
||||
lsbTags = fieldEl.findall('lsb')
|
||||
if len(lsbTags) == 1:
|
||||
lsb = int(getText(lsbTags[0]))
|
||||
else:
|
||||
lsb = int(getText(fieldEl.find('bitOffset')))
|
||||
msbTags = fieldEl.findall('msb')
|
||||
if len(msbTags) == 1:
|
||||
msb = int(getText(msbTags[0]))
|
||||
else:
|
||||
msb = int(getText(fieldEl.find('bitWidth'))) + lsb - 1
|
||||
fields.append({
|
||||
'name': '{}_{}{}_{}_Pos'.format(groupName, bitfieldPrefix, regName, fieldName),
|
||||
'description': 'Position of %s field.' % fieldName,
|
||||
'value': lsb,
|
||||
})
|
||||
fields.append({
|
||||
'name': '{}_{}{}_{}_Msk'.format(groupName, bitfieldPrefix, regName, fieldName),
|
||||
'description': 'Bit mask of %s field.' % fieldName,
|
||||
'value': (0xffffffff >> (31 - (msb - lsb))) << lsb,
|
||||
})
|
||||
if lsb == msb: # single bit
|
||||
fields.append({
|
||||
'name': '{}_{}{}_{}'.format(groupName, bitfieldPrefix, regName, fieldName),
|
||||
'description': 'Bit %s.' % fieldName,
|
||||
'value': 1 << lsb,
|
||||
})
|
||||
for enumEl in fieldEl.findall('enumeratedValues/enumeratedValue'):
|
||||
enumName = getText(enumEl.find('name'))
|
||||
enumDescription = getText(enumEl.find('description'))
|
||||
enumValue = int(getText(enumEl.find('value')), 0)
|
||||
fields.append({
|
||||
'name': '{}_{}{}_{}_{}'.format(groupName, bitfieldPrefix, regName, fieldName, enumName),
|
||||
'description': enumDescription,
|
||||
'value': enumValue,
|
||||
})
|
||||
return fields
|
||||
|
||||
def parseRegister(groupName, regEl, baseAddress, bitfieldPrefix=''):
|
||||
regName = getText(regEl.find('name'))
|
||||
regDescription = getText(regEl.find('description'))
|
||||
offsetEls = regEl.findall('offset')
|
||||
if not offsetEls:
|
||||
offsetEls = regEl.findall('addressOffset')
|
||||
address = baseAddress + int(getText(offsetEls[0]), 0)
|
||||
|
||||
size = 4
|
||||
elSizes = regEl.findall('size')
|
||||
if elSizes:
|
||||
size = int(getText(elSizes[0]), 0) // 8
|
||||
|
||||
dimEls = regEl.findall('dim')
|
||||
fieldsEls = regEl.findall('fields')
|
||||
|
||||
array = None
|
||||
if dimEls:
|
||||
array = int(getText(dimEls[0]), 0)
|
||||
dimIncrement = int(getText(regEl.find('dimIncrement')), 0)
|
||||
if "[%s]" in regName:
|
||||
# just a normal array of registers
|
||||
regName = regName.replace('[%s]', '')
|
||||
elif "%s" in regName:
|
||||
# a "spaced array" of registers, special processing required
|
||||
# we need to generate a separate register for each "element"
|
||||
results = []
|
||||
for i in range(array):
|
||||
regAddress = address + (i * dimIncrement)
|
||||
results.append({
|
||||
'name': regName.replace('%s', str(i)),
|
||||
'address': regAddress,
|
||||
'description': regDescription.replace('\n', ' '),
|
||||
'bitfields': [],
|
||||
'array': None,
|
||||
'elementsize': size,
|
||||
})
|
||||
# set first result bitfield
|
||||
shortName = regName.replace('_%s', '').replace('%s', '')
|
||||
results[0]['bitfields'] = parseBitfields(groupName, shortName, fieldsEls, bitfieldPrefix)
|
||||
return results
|
||||
|
||||
return [{
|
||||
'name': regName,
|
||||
'address': address,
|
||||
'description': regDescription.replace('\n', ' '),
|
||||
'bitfields': parseBitfields(groupName, regName, fieldsEls, bitfieldPrefix),
|
||||
'array': array,
|
||||
'elementsize': size,
|
||||
}]
|
||||
|
||||
def writeGo(outdir, device):
|
||||
# The Go module for this device.
|
||||
out = open(outdir + '/' + device.metadata['nameLower'] + '.go', 'w')
|
||||
pkgName = os.path.basename(outdir.rstrip('/'))
|
||||
out.write('''\
|
||||
// Automatically generated file. DO NOT EDIT.
|
||||
// Generated by gen-device-svd.py from {file}, see {descriptorSource}
|
||||
|
||||
// +build {pkgName},{nameLower}
|
||||
|
||||
// {description}
|
||||
//
|
||||
{licenseBlock}
|
||||
package {pkgName}
|
||||
|
||||
import (
|
||||
"runtime/volatile"
|
||||
"unsafe"
|
||||
)
|
||||
|
||||
// Special types that causes loads/stores to be volatile (necessary for
|
||||
// memory-mapped registers).
|
||||
type Register8 struct {{
|
||||
Reg uint8
|
||||
}}
|
||||
|
||||
// Get returns the value in the register. It is the volatile equivalent of:
|
||||
//
|
||||
// *r.Reg
|
||||
//
|
||||
//go:inline
|
||||
func (r *Register8) Get() uint8 {{
|
||||
return volatile.LoadUint8(&r.Reg)
|
||||
}}
|
||||
|
||||
// Set updates the register value. It is the volatile equivalent of:
|
||||
//
|
||||
// *r.Reg = value
|
||||
//
|
||||
//go:inline
|
||||
func (r *Register8) Set(value uint8) {{
|
||||
volatile.StoreUint8(&r.Reg, value)
|
||||
}}
|
||||
|
||||
// SetBits reads the register, sets the given bits, and writes it back. It is
|
||||
// the volatile equivalent of:
|
||||
//
|
||||
// r.Reg |= value
|
||||
//
|
||||
//go:inline
|
||||
func (r *Register8) SetBits(value uint8) {{
|
||||
volatile.StoreUint8(&r.Reg, volatile.LoadUint8(&r.Reg) | value)
|
||||
}}
|
||||
|
||||
// ClearBits reads the register, clears the given bits, and writes it back. It
|
||||
// is the volatile equivalent of:
|
||||
//
|
||||
// r.Reg &^= value
|
||||
//
|
||||
//go:inline
|
||||
func (r *Register8) ClearBits(value uint8) {{
|
||||
volatile.StoreUint8(&r.Reg, volatile.LoadUint8(&r.Reg) &^ value)
|
||||
}}
|
||||
|
||||
type Register16 struct {{
|
||||
Reg uint16
|
||||
}}
|
||||
|
||||
// Get returns the value in the register. It is the volatile equivalent of:
|
||||
//
|
||||
// *r.Reg
|
||||
//
|
||||
//go:inline
|
||||
func (r *Register16) Get() uint16 {{
|
||||
return volatile.LoadUint16(&r.Reg)
|
||||
}}
|
||||
|
||||
// Set updates the register value. It is the volatile equivalent of:
|
||||
//
|
||||
// *r.Reg = value
|
||||
//
|
||||
//go:inline
|
||||
func (r *Register16) Set(value uint16) {{
|
||||
volatile.StoreUint16(&r.Reg, value)
|
||||
}}
|
||||
|
||||
// SetBits reads the register, sets the given bits, and writes it back. It is
|
||||
// the volatile equivalent of:
|
||||
//
|
||||
// r.Reg |= value
|
||||
//
|
||||
//go:inline
|
||||
func (r *Register16) SetBits(value uint16) {{
|
||||
volatile.StoreUint16(&r.Reg, volatile.LoadUint16(&r.Reg) | value)
|
||||
}}
|
||||
|
||||
// ClearBits reads the register, clears the given bits, and writes it back. It
|
||||
// is the volatile equivalent of:
|
||||
//
|
||||
// r.Reg &^= value
|
||||
//
|
||||
//go:inline
|
||||
func (r *Register16) ClearBits(value uint16) {{
|
||||
volatile.StoreUint16(&r.Reg, volatile.LoadUint16(&r.Reg) &^ value)
|
||||
}}
|
||||
|
||||
type Register32 struct {{
|
||||
Reg uint32
|
||||
}}
|
||||
|
||||
// Get returns the value in the register. It is the volatile equivalent of:
|
||||
//
|
||||
// *r.Reg
|
||||
//
|
||||
//go:inline
|
||||
func (r *Register32) Get() uint32 {{
|
||||
return volatile.LoadUint32(&r.Reg)
|
||||
}}
|
||||
|
||||
// Set updates the register value. It is the volatile equivalent of:
|
||||
//
|
||||
// *r.Reg = value
|
||||
//
|
||||
//go:inline
|
||||
func (r *Register32) Set(value uint32) {{
|
||||
volatile.StoreUint32(&r.Reg, value)
|
||||
}}
|
||||
|
||||
// SetBits reads the register, sets the given bits, and writes it back. It is
|
||||
// the volatile equivalent of:
|
||||
//
|
||||
// r.Reg |= value
|
||||
//
|
||||
//go:inline
|
||||
func (r *Register32) SetBits(value uint32) {{
|
||||
volatile.StoreUint32(&r.Reg, volatile.LoadUint32(&r.Reg) | value)
|
||||
}}
|
||||
|
||||
// ClearBits reads the register, clears the given bits, and writes it back. It
|
||||
// is the volatile equivalent of:
|
||||
//
|
||||
// r.Reg &^= value
|
||||
//
|
||||
//go:inline
|
||||
func (r *Register32) ClearBits(value uint32) {{
|
||||
volatile.StoreUint32(&r.Reg, volatile.LoadUint32(&r.Reg) &^ value)
|
||||
}}
|
||||
|
||||
// Some information about this device.
|
||||
const (
|
||||
DEVICE = "{name}"
|
||||
)
|
||||
'''.format(pkgName=pkgName, **device.metadata))
|
||||
|
||||
out.write('\n// Interrupt numbers\nconst (\n')
|
||||
for intr in device.interrupts:
|
||||
out.write('\tIRQ_{name} = {index} // {description}\n'.format(**intr))
|
||||
intrMax = max(map(lambda intr: intr['index'], device.interrupts))
|
||||
out.write('\tIRQ_max = {} // Highest interrupt number on this device.\n'.format(intrMax))
|
||||
out.write(')\n')
|
||||
|
||||
# Define actual peripheral pointers.
|
||||
out.write('\n// Peripherals.\nvar (\n')
|
||||
for peripheral in device.peripherals:
|
||||
out.write('\t{name} = (*{groupName}_Type)(unsafe.Pointer(uintptr(0x{baseAddress:x}))) // {description}\n'.format(**peripheral))
|
||||
out.write(')\n')
|
||||
|
||||
# Define peripheral struct types.
|
||||
for peripheral in device.peripherals:
|
||||
if 'registers' not in peripheral:
|
||||
# This peripheral was derived from another peripheral. No new type
|
||||
# needs to be defined for it.
|
||||
continue
|
||||
out.write('\n// {description}\ntype {groupName}_Type struct {{\n'.format(**peripheral))
|
||||
address = peripheral['baseAddress']
|
||||
padNumber = 0
|
||||
for register in peripheral['registers']:
|
||||
if address > register['address'] and 'registers' not in register :
|
||||
# In Nordic SVD files, these registers are deprecated or
|
||||
# duplicates, so can be ignored.
|
||||
#print('skip: %s.%s %s - %s %s' % (peripheral['name'], register['name'], address, register['address'], register['elementsize']))
|
||||
continue
|
||||
eSize = register['elementsize']
|
||||
if eSize == 4:
|
||||
regType = 'Register32'
|
||||
elif eSize == 2:
|
||||
regType = 'Register16'
|
||||
elif eSize == 1:
|
||||
regType = 'Register8'
|
||||
else:
|
||||
eSize = 4
|
||||
regType = 'Register32'
|
||||
|
||||
# insert padding, if needed
|
||||
if address < register['address']:
|
||||
bytesNeeded = register['address'] - address
|
||||
if bytesNeeded == 1:
|
||||
out.write('\t_padding{padNumber} {regType}\n'.format(padNumber=padNumber, regType='Register8'))
|
||||
elif bytesNeeded == 2:
|
||||
out.write('\t_padding{padNumber} {regType}\n'.format(padNumber=padNumber, regType='Register16'))
|
||||
else:
|
||||
numSkip = (register['address'] - address) // eSize
|
||||
if numSkip == 1:
|
||||
out.write('\t_padding{padNumber} {regType}\n'.format(padNumber=padNumber, regType=regType))
|
||||
else:
|
||||
out.write('\t_padding{padNumber} [{num}]{regType}\n'.format(padNumber=padNumber, num=numSkip, regType=regType))
|
||||
padNumber += 1
|
||||
address = register['address']
|
||||
|
||||
lastCluster = False
|
||||
if 'registers' in register:
|
||||
# This is a cluster, not a register. Create the cluster type.
|
||||
regType = 'struct {\n'
|
||||
subaddress = register['address']
|
||||
for subregister in register['registers']:
|
||||
if subregister['elementsize'] == 4:
|
||||
subregType = 'Register32'
|
||||
elif subregister['elementsize'] == 2:
|
||||
subregType = 'Register16'
|
||||
else:
|
||||
subregType = 'Register8'
|
||||
|
||||
if subregister['array']:
|
||||
subregType = '[{}]{}'.format(subregister['array'], subregType)
|
||||
if subaddress != subregister['address']:
|
||||
bytesNeeded = subregister['address'] - subaddress
|
||||
if bytesNeeded == 1:
|
||||
regType += '\t\t_padding{padNumber} {subregType}\n'.format(padNumber=padNumber, subregType='Register8')
|
||||
elif bytesNeeded == 2:
|
||||
regType += '\t\t_padding{padNumber} {subregType}\n'.format(padNumber=padNumber, subregType='Register16')
|
||||
else:
|
||||
numSkip = (subregister['address'] - subaddress)
|
||||
if numSkip < 1:
|
||||
continue
|
||||
elif numSkip == 1:
|
||||
regType += '\t\t_padding{padNumber} {subregType}\n'.format(padNumber=padNumber, subregType='Register8')
|
||||
else:
|
||||
regType += '\t\t_padding{padNumber} [{num}]{subregType}\n'.format(padNumber=padNumber, num=numSkip, subregType='Register8')
|
||||
padNumber += 1
|
||||
subaddress += bytesNeeded
|
||||
if subregister['array'] is not None:
|
||||
subaddress += subregister['elementsize'] * subregister['array']
|
||||
else:
|
||||
subaddress += subregister['elementsize']
|
||||
regType += '\t\t{name} {subregType}\n'.format(name=subregister['name'], subregType=subregType)
|
||||
if register['array'] is not None:
|
||||
if subaddress != register['address'] + register['elementsize']:
|
||||
numSkip = ((register['address'] + register['elementsize']) - subaddress) // 4
|
||||
if numSkip <= 1:
|
||||
regType += '\t\t_padding{padNumber} {subregType}\n'.format(padNumber=padNumber, subregType=subregType)
|
||||
else:
|
||||
regType += '\t\t_padding{padNumber} [{num}]{subregType}\n'.format(padNumber=padNumber, num=numSkip, subregType=subregType)
|
||||
else:
|
||||
lastCluster = True
|
||||
regType += '\t}'
|
||||
address = subaddress
|
||||
if register['array'] is not None:
|
||||
regType = '[{}]{}'.format(register['array'], regType)
|
||||
out.write('\t{name} {regType}\n'.format(name=register['name'], regType=regType))
|
||||
|
||||
# next address
|
||||
if lastCluster is True:
|
||||
lastCluster = False
|
||||
elif register['array'] is not None:
|
||||
address = register['address'] + register['elementsize'] * register['array']
|
||||
else:
|
||||
address = register['address'] + register['elementsize']
|
||||
out.write('}\n')
|
||||
|
||||
# Define bitfields.
|
||||
for peripheral in device.peripherals:
|
||||
if 'registers' not in peripheral:
|
||||
# This peripheral was derived from another peripheral. Bitfields are
|
||||
# already defined.
|
||||
continue
|
||||
out.write('\n// Bitfields for {name}: {description}\nconst('.format(**peripheral))
|
||||
for register in peripheral['registers']:
|
||||
if register.get('bitfields'):
|
||||
writeGoRegisterBitfields(out, register, register['name'])
|
||||
for subregister in register.get('registers', []):
|
||||
writeGoRegisterBitfields(out, subregister, register['name'] + '.' + subregister['name'])
|
||||
out.write(')\n')
|
||||
|
||||
def writeGoRegisterBitfields(out, register, name):
|
||||
out.write('\n\t// {}'.format(name))
|
||||
if register['description']:
|
||||
out.write(': {description}'.format(**register))
|
||||
out.write('\n')
|
||||
for bitfield in register['bitfields']:
|
||||
out.write('\t{name} = 0x{value:x}'.format(**bitfield))
|
||||
if bitfield['description']:
|
||||
out.write(' // {description}'.format(**bitfield))
|
||||
out.write('\n')
|
||||
|
||||
|
||||
def writeAsm(outdir, device):
|
||||
# The interrupt vector, which is hard to write directly in Go.
|
||||
out = open(outdir + '/' + device.metadata['nameLower'] + '.s', 'w')
|
||||
out.write('''\
|
||||
// Automatically generated file. DO NOT EDIT.
|
||||
// Generated by gen-device-svd.py from {file}, see {descriptorSource}
|
||||
|
||||
// {description}
|
||||
//
|
||||
{licenseBlock}
|
||||
|
||||
.syntax unified
|
||||
|
||||
// This is the default handler for interrupts, if triggered but not defined.
|
||||
.section .text.Default_Handler
|
||||
.global Default_Handler
|
||||
.type Default_Handler, %function
|
||||
Default_Handler:
|
||||
wfe
|
||||
b Default_Handler
|
||||
|
||||
// Avoid the need for repeated .weak and .set instructions.
|
||||
.macro IRQ handler
|
||||
.weak \\handler
|
||||
.set \\handler, Default_Handler
|
||||
.endm
|
||||
|
||||
// Must set the "a" flag on the section:
|
||||
// https://svnweb.freebsd.org/base/stable/11/sys/arm/arm/locore-v4.S?r1=321049&r2=321048&pathrev=321049
|
||||
// https://sourceware.org/binutils/docs/as/Section.html#ELF-Version
|
||||
.section .isr_vector, "a", %progbits
|
||||
.global __isr_vector
|
||||
// Interrupt vector as defined by Cortex-M, starting with the stack top.
|
||||
// On reset, SP is initialized with *0x0 and PC is loaded with *0x4, loading
|
||||
// _stack_top and Reset_Handler.
|
||||
.long _stack_top
|
||||
.long Reset_Handler
|
||||
.long NMI_Handler
|
||||
.long HardFault_Handler
|
||||
.long MemoryManagement_Handler
|
||||
.long BusFault_Handler
|
||||
.long UsageFault_Handler
|
||||
.long 0
|
||||
.long 0
|
||||
.long 0
|
||||
.long 0
|
||||
.long SVC_Handler
|
||||
.long DebugMon_Handler
|
||||
.long 0
|
||||
.long PendSV_Handler
|
||||
.long SysTick_Handler
|
||||
|
||||
// Extra interrupts for peripherals defined by the hardware vendor.
|
||||
'''.format(**device.metadata))
|
||||
num = 0
|
||||
for intr in device.interrupts:
|
||||
if intr['index'] == num - 1:
|
||||
continue
|
||||
if intr['index'] < num:
|
||||
raise ValueError('interrupt numbers are not sorted')
|
||||
while intr['index'] > num:
|
||||
out.write(' .long 0\n')
|
||||
num += 1
|
||||
num += 1
|
||||
out.write(' .long {name}_IRQHandler\n'.format(**intr))
|
||||
|
||||
out.write('''
|
||||
// Define default implementations for interrupts, redirecting to
|
||||
// Default_Handler when not implemented.
|
||||
IRQ NMI_Handler
|
||||
IRQ HardFault_Handler
|
||||
IRQ MemoryManagement_Handler
|
||||
IRQ BusFault_Handler
|
||||
IRQ UsageFault_Handler
|
||||
IRQ SVC_Handler
|
||||
IRQ DebugMon_Handler
|
||||
IRQ PendSV_Handler
|
||||
IRQ SysTick_Handler
|
||||
''')
|
||||
for intr in device.interrupts:
|
||||
out.write(' IRQ {name}_IRQHandler\n'.format(**intr))
|
||||
|
||||
def generate(indir, outdir, sourceURL):
|
||||
if not os.path.isdir(indir):
|
||||
print('cannot find input directory:', indir, file=sys.stderr)
|
||||
sys.exit(1)
|
||||
if not os.path.isdir(outdir):
|
||||
os.mkdir(outdir)
|
||||
infiles = glob(indir + '/*.svd')
|
||||
if not infiles:
|
||||
print('no .svd files found:', indir, file=sys.stderr)
|
||||
sys.exit(1)
|
||||
for filepath in sorted(infiles):
|
||||
print(filepath)
|
||||
device = readSVD(filepath, sourceURL)
|
||||
writeGo(outdir, device)
|
||||
writeAsm(outdir, device)
|
||||
|
||||
|
||||
if __name__ == '__main__':
|
||||
parser = argparse.ArgumentParser(description='Generate Go register descriptors and interrupt vectors from .svd files')
|
||||
parser.add_argument('indir', metavar='indir', type=str,
|
||||
help='input directory containing .svd files')
|
||||
parser.add_argument('outdir', metavar='outdir', type=str,
|
||||
help='output directory')
|
||||
parser.add_argument('--source', metavar='source', type=str,
|
||||
help='output directory',
|
||||
default='<unknown>')
|
||||
args = parser.parse_args()
|
||||
generate(args.indir, args.outdir, args.source)
|
||||
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