machine/atsamd51: pin method cleanup (#659)
* machine/samd51: pin method cleanups. - Use bit-math to select the group in Pin methods. - Move Pin methods to atsamd51. They are not chip-specific, they apply to the whole atsamd51 family. - Move the group/pin-id calculation into a helper method. - Add a Pin.Toggle() method.
Этот коммит содержится в:
Infinoid
Ron Evans
родитель
2f059ac91e
коммит
f7dde33842
2 изменённых файлов: 147 добавлений и 193 удалений
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@ -110,6 +110,153 @@ const (
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PB31 Pin = 63
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)
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// Return the register and mask to enable a given GPIO pin. This can be used to
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// implement bit-banged drivers.
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func (p Pin) PortMaskSet() (*uint32, uint32) {
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group, pin_in_group := p.getPinGrouping()
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return &sam.PORT.GROUP[group].OUTSET.Reg, 1 << pin_in_group
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}
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// Return the register and mask to disable a given port. This can be used to
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// implement bit-banged drivers.
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func (p Pin) PortMaskClear() (*uint32, uint32) {
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group, pin_in_group := p.getPinGrouping()
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return &sam.PORT.GROUP[group].OUTCLR.Reg, 1 << pin_in_group
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}
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// Set the pin to high or low.
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// Warning: only use this on an output pin!
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func (p Pin) Set(high bool) {
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group, pin_in_group := p.getPinGrouping()
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if high {
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sam.PORT.GROUP[group].OUTSET.Set(1 << pin_in_group)
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} else {
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sam.PORT.GROUP[group].OUTCLR.Set(1 << pin_in_group)
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}
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}
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// Get returns the current value of a GPIO pin.
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func (p Pin) Get() bool {
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group, pin_in_group := p.getPinGrouping()
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return (sam.PORT.GROUP[group].IN.Get()>>pin_in_group)&1 > 0
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}
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// Toggle switches an output pin from low to high or from high to low.
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// Warning: only use this on an output pin!
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func (p Pin) Toggle() {
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group, pin_in_group := p.getPinGrouping()
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sam.PORT.GROUP[group].OUTTGL.Set(1 << pin_in_group)
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}
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// Configure this pin with the given configuration.
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func (p Pin) Configure(config PinConfig) {
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group, pin_in_group := p.getPinGrouping()
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switch config.Mode {
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case PinOutput:
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sam.PORT.GROUP[group].DIRSET.Set(1 << pin_in_group)
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// output is also set to input enable so pin can read back its own value
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p.setPinCfg(sam.PORT_GROUP_PINCFG_INEN)
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case PinInput:
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sam.PORT.GROUP[group].DIRCLR.Set(1 << pin_in_group)
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p.setPinCfg(sam.PORT_GROUP_PINCFG_INEN)
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case PinInputPulldown:
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sam.PORT.GROUP[group].DIRCLR.Set(1 << pin_in_group)
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sam.PORT.GROUP[group].OUTCLR.Set(1 << pin_in_group)
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p.setPinCfg(sam.PORT_GROUP_PINCFG_INEN | sam.PORT_GROUP_PINCFG_PULLEN)
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case PinInputPullup:
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sam.PORT.GROUP[group].DIRCLR.Set(1 << pin_in_group)
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sam.PORT.GROUP[group].OUTSET.Set(1 << pin_in_group)
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p.setPinCfg(sam.PORT_GROUP_PINCFG_INEN | sam.PORT_GROUP_PINCFG_PULLEN)
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case PinSERCOM:
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if p&1 > 0 {
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// odd pin, so save the even pins
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val := p.getPMux() & sam.PORT_GROUP_PMUX_PMUXE_Msk
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p.setPMux(val | (uint8(PinSERCOM) << sam.PORT_GROUP_PMUX_PMUXO_Pos))
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} else {
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// even pin, so save the odd pins
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val := p.getPMux() & sam.PORT_GROUP_PMUX_PMUXO_Msk
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p.setPMux(val | (uint8(PinSERCOM) << sam.PORT_GROUP_PMUX_PMUXE_Pos))
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}
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// enable port config
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p.setPinCfg(sam.PORT_GROUP_PINCFG_PMUXEN | sam.PORT_GROUP_PINCFG_DRVSTR | sam.PORT_GROUP_PINCFG_INEN)
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case PinSERCOMAlt:
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if p&1 > 0 {
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// odd pin, so save the even pins
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val := p.getPMux() & sam.PORT_GROUP_PMUX_PMUXE_Msk
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p.setPMux(val | (uint8(PinSERCOMAlt) << sam.PORT_GROUP_PMUX_PMUXO_Pos))
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} else {
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// even pin, so save the odd pins
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val := p.getPMux() & sam.PORT_GROUP_PMUX_PMUXO_Msk
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p.setPMux(val | (uint8(PinSERCOMAlt) << sam.PORT_GROUP_PMUX_PMUXE_Pos))
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}
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// enable port config
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p.setPinCfg(sam.PORT_GROUP_PINCFG_PMUXEN | sam.PORT_GROUP_PINCFG_DRVSTR)
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case PinCom:
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if p&1 > 0 {
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// odd pin, so save the even pins
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val := p.getPMux() & sam.PORT_GROUP_PMUX_PMUXE_Msk
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p.setPMux(val | (uint8(PinCom) << sam.PORT_GROUP_PMUX_PMUXO_Pos))
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} else {
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// even pin, so save the odd pins
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val := p.getPMux() & sam.PORT_GROUP_PMUX_PMUXO_Msk
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p.setPMux(val | (uint8(PinCom) << sam.PORT_GROUP_PMUX_PMUXE_Pos))
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}
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// enable port config
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p.setPinCfg(sam.PORT_GROUP_PINCFG_PMUXEN)
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case PinAnalog:
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if p&1 > 0 {
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// odd pin, so save the even pins
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val := p.getPMux() & sam.PORT_GROUP_PMUX_PMUXE_Msk
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p.setPMux(val | (uint8(PinAnalog) << sam.PORT_GROUP_PMUX_PMUXO_Pos))
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} else {
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// even pin, so save the odd pins
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val := p.getPMux() & sam.PORT_GROUP_PMUX_PMUXO_Msk
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p.setPMux(val | (uint8(PinAnalog) << sam.PORT_GROUP_PMUX_PMUXE_Pos))
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}
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// enable port config
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p.setPinCfg(sam.PORT_GROUP_PINCFG_PMUXEN | sam.PORT_GROUP_PINCFG_DRVSTR)
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}
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}
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// getPMux returns the value for the correct PMUX register for this pin.
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func (p Pin) getPMux() uint8 {
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group, pin_in_group := p.getPinGrouping()
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return sam.PORT.GROUP[group].PMUX[pin_in_group>>1].Get()
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}
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// setPMux sets the value for the correct PMUX register for this pin.
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func (p Pin) setPMux(val uint8) {
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group, pin_in_group := p.getPinGrouping()
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sam.PORT.GROUP[group].PMUX[pin_in_group>>1].Set(val)
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}
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// getPinCfg returns the value for the correct PINCFG register for this pin.
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func (p Pin) getPinCfg() uint8 {
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group, pin_in_group := p.getPinGrouping()
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return sam.PORT.GROUP[group].PINCFG[pin_in_group].Get()
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}
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// setPinCfg sets the value for the correct PINCFG register for this pin.
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func (p Pin) setPinCfg(val uint8) {
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group, pin_in_group := p.getPinGrouping()
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sam.PORT.GROUP[group].PINCFG[pin_in_group].Set(val)
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}
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// getPinGrouping calculates the gpio group and pin id from the pin number.
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// Pins are split into groups of 32, and each group has its own set of
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// control registers.
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func (p Pin) getPinGrouping() (uint8, uint8) {
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group := uint8(p) >> 5
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pin_in_group := uint8(p) & 0x1f
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return group, pin_in_group
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}
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// InitADC initializes the ADC.
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func InitADC() {
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// ADC Bias Calibration
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@ -6,196 +6,3 @@
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// http://ww1.microchip.com/downloads/en/DeviceDoc/60001507C.pdf
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//
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package machine
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import (
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"device/sam"
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)
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// Return the register and mask to enable a given GPIO pin. This can be used to
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// implement bit-banged drivers.
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func (p Pin) PortMaskSet() (*uint32, uint32) {
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if p < 32 {
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return &sam.PORT.GROUP[0].OUTSET.Reg, 1 << uint8(p)
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} else {
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return &sam.PORT.GROUP[1].OUTSET.Reg, 1 << uint8(p-32)
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}
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}
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// Return the register and mask to disable a given port. This can be used to
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// implement bit-banged drivers.
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func (p Pin) PortMaskClear() (*uint32, uint32) {
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if p < 32 {
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return &sam.PORT.GROUP[0].OUTCLR.Reg, 1 << uint8(p)
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} else {
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return &sam.PORT.GROUP[1].OUTCLR.Reg, 1 << uint8(p-32)
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}
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}
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// Set the pin to high or low.
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// Warning: only use this on an output pin!
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func (p Pin) Set(high bool) {
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if p < 32 {
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if high {
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sam.PORT.GROUP[0].OUTSET.Set(1 << uint8(p))
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} else {
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sam.PORT.GROUP[0].OUTCLR.Set(1 << uint8(p))
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}
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} else {
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if high {
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sam.PORT.GROUP[1].OUTSET.Set(1 << uint8(p-32))
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} else {
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sam.PORT.GROUP[1].OUTCLR.Set(1 << uint8(p-32))
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}
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}
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}
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// Get returns the current value of a GPIO pin.
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func (p Pin) Get() bool {
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if p < 32 {
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return (sam.PORT.GROUP[0].IN.Get()>>uint8(p))&1 > 0
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} else {
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return (sam.PORT.GROUP[1].IN.Get()>>(uint8(p)-32))&1 > 0
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}
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}
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// Configure this pin with the given configuration.
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func (p Pin) Configure(config PinConfig) {
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switch config.Mode {
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case PinOutput:
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if p < 32 {
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sam.PORT.GROUP[0].DIRSET.Set(1 << uint8(p))
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// output is also set to input enable so pin can read back its own value
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p.setPinCfg(sam.PORT_GROUP_PINCFG_INEN)
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} else {
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sam.PORT.GROUP[1].DIRSET.Set(1 << uint8(p-32))
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// output is also set to input enable so pin can read back its own value
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p.setPinCfg(sam.PORT_GROUP_PINCFG_INEN)
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}
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case PinInput:
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if p < 32 {
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sam.PORT.GROUP[0].DIRCLR.Set(1 << uint8(p))
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p.setPinCfg(sam.PORT_GROUP_PINCFG_INEN)
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} else {
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sam.PORT.GROUP[1].DIRCLR.Set(1 << uint8(p-32))
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p.setPinCfg(sam.PORT_GROUP_PINCFG_INEN)
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}
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case PinInputPulldown:
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if p < 32 {
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sam.PORT.GROUP[0].DIRCLR.Set(1 << uint8(p))
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sam.PORT.GROUP[0].OUTCLR.Set(1 << uint8(p))
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p.setPinCfg(sam.PORT_GROUP_PINCFG_INEN | sam.PORT_GROUP_PINCFG_PULLEN)
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} else {
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sam.PORT.GROUP[1].DIRCLR.Set(1 << uint8(p-32))
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sam.PORT.GROUP[1].OUTCLR.Set(1 << uint8(p-32))
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p.setPinCfg(sam.PORT_GROUP_PINCFG_INEN | sam.PORT_GROUP_PINCFG_PULLEN)
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}
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case PinInputPullup:
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if p < 32 {
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sam.PORT.GROUP[0].DIRCLR.Set(1 << uint8(p))
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sam.PORT.GROUP[0].OUTSET.Set(1 << uint8(p))
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p.setPinCfg(sam.PORT_GROUP_PINCFG_INEN | sam.PORT_GROUP_PINCFG_PULLEN)
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} else {
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sam.PORT.GROUP[1].DIRCLR.Set(1 << uint8(p-32))
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sam.PORT.GROUP[1].OUTSET.Set(1 << uint8(p-32))
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p.setPinCfg(sam.PORT_GROUP_PINCFG_INEN | sam.PORT_GROUP_PINCFG_PULLEN)
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}
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case PinSERCOM:
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if p&1 > 0 {
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// odd pin, so save the even pins
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val := p.getPMux() & sam.PORT_GROUP_PMUX_PMUXE_Msk
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p.setPMux(val | (uint8(PinSERCOM) << sam.PORT_GROUP_PMUX_PMUXO_Pos))
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} else {
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// even pin, so save the odd pins
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val := p.getPMux() & sam.PORT_GROUP_PMUX_PMUXO_Msk
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p.setPMux(val | (uint8(PinSERCOM) << sam.PORT_GROUP_PMUX_PMUXE_Pos))
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}
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// enable port config
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p.setPinCfg(sam.PORT_GROUP_PINCFG_PMUXEN | sam.PORT_GROUP_PINCFG_DRVSTR | sam.PORT_GROUP_PINCFG_INEN)
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case PinSERCOMAlt:
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if p&1 > 0 {
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// odd pin, so save the even pins
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val := p.getPMux() & sam.PORT_GROUP_PMUX_PMUXE_Msk
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p.setPMux(val | (uint8(PinSERCOMAlt) << sam.PORT_GROUP_PMUX_PMUXO_Pos))
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} else {
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// even pin, so save the odd pins
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val := p.getPMux() & sam.PORT_GROUP_PMUX_PMUXO_Msk
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p.setPMux(val | (uint8(PinSERCOMAlt) << sam.PORT_GROUP_PMUX_PMUXE_Pos))
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}
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// enable port config
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p.setPinCfg(sam.PORT_GROUP_PINCFG_PMUXEN | sam.PORT_GROUP_PINCFG_DRVSTR)
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case PinCom:
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if p&1 > 0 {
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// odd pin, so save the even pins
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val := p.getPMux() & sam.PORT_GROUP_PMUX_PMUXE_Msk
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p.setPMux(val | (uint8(PinCom) << sam.PORT_GROUP_PMUX_PMUXO_Pos))
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} else {
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// even pin, so save the odd pins
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val := p.getPMux() & sam.PORT_GROUP_PMUX_PMUXO_Msk
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p.setPMux(val | (uint8(PinCom) << sam.PORT_GROUP_PMUX_PMUXE_Pos))
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}
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// enable port config
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p.setPinCfg(sam.PORT_GROUP_PINCFG_PMUXEN)
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case PinAnalog:
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if p&1 > 0 {
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// odd pin, so save the even pins
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val := p.getPMux() & sam.PORT_GROUP_PMUX_PMUXE_Msk
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p.setPMux(val | (uint8(PinAnalog) << sam.PORT_GROUP_PMUX_PMUXO_Pos))
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} else {
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// even pin, so save the odd pins
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val := p.getPMux() & sam.PORT_GROUP_PMUX_PMUXO_Msk
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p.setPMux(val | (uint8(PinAnalog) << sam.PORT_GROUP_PMUX_PMUXE_Pos))
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}
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// enable port config
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p.setPinCfg(sam.PORT_GROUP_PINCFG_PMUXEN | sam.PORT_GROUP_PINCFG_DRVSTR)
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}
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}
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// getPMux returns the value for the correct PMUX register for this pin.
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func (p Pin) getPMux() uint8 {
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switch {
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case p < 32:
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return sam.PORT.GROUP[0].PMUX[uint8(p)>>1].Get()
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case p >= 32 && p < 64:
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return sam.PORT.GROUP[1].PMUX[uint8(p-32)>>1].Get()
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default:
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return 0
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}
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}
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// setPMux sets the value for the correct PMUX register for this pin.
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func (p Pin) setPMux(val uint8) {
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switch {
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case p < 32:
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sam.PORT.GROUP[0].PMUX[uint8(p)>>1].Set(val)
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case p >= 32 && p < 64:
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sam.PORT.GROUP[1].PMUX[uint8(p-32)>>1].Set(val)
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}
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}
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// getPinCfg returns the value for the correct PINCFG register for this pin.
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func (p Pin) getPinCfg() uint8 {
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switch {
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case p < 32:
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return sam.PORT.GROUP[0].PINCFG[p].Get()
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case p >= 32 && p <= 64:
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return sam.PORT.GROUP[1].PINCFG[p-32].Get()
|
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default:
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return 0
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}
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}
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|
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// setPinCfg sets the value for the correct PINCFG register for this pin.
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||||
func (p Pin) setPinCfg(val uint8) {
|
||||
switch {
|
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case p < 32:
|
||||
sam.PORT.GROUP[0].PINCFG[p].Set(val)
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case p >= 32 && p <= 64:
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sam.PORT.GROUP[1].PINCFG[p-32].Set(val)
|
||||
}
|
||||
}
|
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|
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