diff --git a/src/device/nxp/clock_mimxrt1062.go b/src/device/nxp/clock_mimxrt1062.go new file mode 100644 index 00000000..a41e3f93 --- /dev/null +++ b/src/device/nxp/clock_mimxrt1062.go @@ -0,0 +1,841 @@ +// Hand created file. DO NOT DELETE. +// Type definitions, fields, and constants associated with various clocks and +// peripherals of the NXP MIMXRT1062. + +// +build nxp,mimxrt1062 + +package nxp + +import ( + "runtime/volatile" + "unsafe" +) + +type ( + Clock uint32 + Gate uint8 + ClockMode uint8 + + // PLL configuration for ARM + ClockConfigArmPll struct { + LoopDivider uint32 // PLL loop divider. Valid range for divider value: 54-108. Fout=Fin*LoopDivider/2. + Src uint8 // Pll clock source, reference _clock_pll_clk_src + } + + // PLL configuration for System + ClockConfigSysPll struct { + LoopDivider uint8 // PLL loop divider. Intended to be 1 (528M): 0 - Fout=Fref*20, 1 - Fout=Fref*22 + Numerator uint32 // 30 bit Numerator of fractional loop divider. + Denominator uint32 // 30 bit Denominator of fractional loop divider + Src uint8 // Pll clock source, reference _clock_pll_clk_src + SsStop uint16 // Stop value to get frequency change. + SsEnable uint8 // Enable spread spectrum modulation + SsStep uint16 // Step value to get frequency change step. + } + + // PLL configuration for USB + ClockConfigUsbPll struct { + Instance uint8 // USB PLL number (1 or 2) + LoopDivider uint8 // PLL loop divider: 0 - Fout=Fref*20, 1 - Fout=Fref*22 + Src uint8 // Pll clock source, reference _clock_pll_clk_src + } + + // PLL configuration for AUDIO + ClockConfigAudioPll struct { + LoopDivider uint8 // PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + PostDivider uint8 // Divider after the PLL, should only be 1, 2, 4, 8, 16. + Numerator uint32 // 30 bit Numerator of fractional loop divider. + Denominator uint32 // 30 bit Denominator of fractional loop divider + Src uint8 // Pll clock source, reference _clock_pll_clk_src + } + + // PLL configuration for VIDEO + ClockConfigVideoPll struct { + LoopDivider uint8 // PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + PostDivider uint8 // Divider after the PLL, should only be 1, 2, 4, 8, 16. + Numerator uint32 // 30 bit Numerator of fractional loop divider. + Denominator uint32 // 30 bit Denominator of fractional loop divider + Src uint8 // Pll clock source, reference _clock_pll_clk_src + } + + // PLL configuration for ENET + ClockConfigEnetPll struct { + EnableClkOutput bool // Power on and enable PLL clock output for ENET0. + EnableClkOutput25M bool // Power on and enable PLL clock output for ENET2. + LoopDivider uint8 // Controls the frequency of the ENET0 reference clock: b00=25MHz, b01=50MHz, b10=100MHz (not 50% duty cycle), b11=125MHz + Src uint8 // Pll clock source, reference _clock_pll_clk_src + EnableClkOutput1 bool // Power on and enable PLL clock output for ENET1. + LoopDivider1 uint8 // Controls the frequency of the ENET1 reference clock: b00 25MHz, b01 50MHz, b10 100MHz (not 50% duty cycle), b11 125MHz + } +) + +const ( + ModeClkRun ClockMode = 0 // Remain in run mode + ModeClkWait ClockMode = 1 // Transfer to wait mode + ModeClkStop ClockMode = 2 // Transfer to stop mode +) + +const ( + GateClkNotNeeded Gate = 0 // Clock is off during all modes + GateClkNeededRun Gate = 1 // Clock is on in run mode, but off in WAIT and STOP modes + GateClkNeededRunWait Gate = 3 // Clock is on during all modes, except STOP mode +) + +// Named oscillators +const ( + ClockCpu Clock = 0x0 // CPU clock + ClockAhb Clock = 0x1 // AHB clock + ClockSemc Clock = 0x2 // SEMC clock + ClockIpg Clock = 0x3 // IPG clock + ClockPer Clock = 0x4 // PER clock + ClockOsc Clock = 0x5 // OSC clock selected by PMU_LOWPWR_CTRL[OSC_SEL] + ClockRtc Clock = 0x6 // RTC clock (RTCCLK) + ClockArmPll Clock = 0x7 // ARMPLLCLK + ClockUsb1Pll Clock = 0x8 // USB1PLLCLK + ClockUsb1PllPfd0 Clock = 0x9 // USB1PLLPDF0CLK + ClockUsb1PllPfd1 Clock = 0xA // USB1PLLPFD1CLK + ClockUsb1PllPfd2 Clock = 0xB // USB1PLLPFD2CLK + ClockUsb1PllPfd3 Clock = 0xC // USB1PLLPFD3CLK + ClockUsb2Pll Clock = 0xD // USB2PLLCLK + ClockSysPll Clock = 0xE // SYSPLLCLK + ClockSysPllPfd0 Clock = 0xF // SYSPLLPDF0CLK + ClockSysPllPfd1 Clock = 0x10 // SYSPLLPFD1CLK + ClockSysPllPfd2 Clock = 0x11 // SYSPLLPFD2CLK + ClockSysPllPfd3 Clock = 0x12 // SYSPLLPFD3CLK + ClockEnetPll0 Clock = 0x13 // Enet PLLCLK ref_enetpll0 + ClockEnetPll1 Clock = 0x14 // Enet PLLCLK ref_enetpll1 + ClockEnetPll2 Clock = 0x15 // Enet PLLCLK ref_enetpll2 + ClockAudioPll Clock = 0x16 // Audio PLLCLK + ClockVideoPll Clock = 0x17 // Video PLLCLK +) + +// Named clocks of integrated peripherals +const ( + ClockIpAipsTz1 Clock = (0 << 8) | CCM_CCGR0_CG0_Pos // CCGR0, CG0 + ClockIpAipsTz2 Clock = (0 << 8) | CCM_CCGR0_CG1_Pos // CCGR0, CG1 + ClockIpMqs Clock = (0 << 8) | CCM_CCGR0_CG2_Pos // CCGR0, CG2 + ClockIpFlexSpiExsc Clock = (0 << 8) | CCM_CCGR0_CG3_Pos // CCGR0, CG3 + ClockIpSimMMain Clock = (0 << 8) | CCM_CCGR0_CG4_Pos // CCGR0, CG4 + ClockIpDcp Clock = (0 << 8) | CCM_CCGR0_CG5_Pos // CCGR0, CG5 + ClockIpLpuart3 Clock = (0 << 8) | CCM_CCGR0_CG6_Pos // CCGR0, CG6 + ClockIpCan1 Clock = (0 << 8) | CCM_CCGR0_CG7_Pos // CCGR0, CG7 + ClockIpCan1S Clock = (0 << 8) | CCM_CCGR0_CG8_Pos // CCGR0, CG8 + ClockIpCan2 Clock = (0 << 8) | CCM_CCGR0_CG9_Pos // CCGR0, CG9 + ClockIpCan2S Clock = (0 << 8) | CCM_CCGR0_CG10_Pos // CCGR0, CG10 + ClockIpTrace Clock = (0 << 8) | CCM_CCGR0_CG11_Pos // CCGR0, CG11 + ClockIpGpt2 Clock = (0 << 8) | CCM_CCGR0_CG12_Pos // CCGR0, CG12 + ClockIpGpt2S Clock = (0 << 8) | CCM_CCGR0_CG13_Pos // CCGR0, CG13 + ClockIpLpuart2 Clock = (0 << 8) | CCM_CCGR0_CG14_Pos // CCGR0, CG14 + ClockIpGpio2 Clock = (0 << 8) | CCM_CCGR0_CG15_Pos // CCGR0, CG15 + + ClockIpLpspi1 Clock = (1 << 8) | CCM_CCGR1_CG0_Pos // CCGR1, CG0 + ClockIpLpspi2 Clock = (1 << 8) | CCM_CCGR1_CG1_Pos // CCGR1, CG1 + ClockIpLpspi3 Clock = (1 << 8) | CCM_CCGR1_CG2_Pos // CCGR1, CG2 + ClockIpLpspi4 Clock = (1 << 8) | CCM_CCGR1_CG3_Pos // CCGR1, CG3 + ClockIpAdc2 Clock = (1 << 8) | CCM_CCGR1_CG4_Pos // CCGR1, CG4 + ClockIpEnet Clock = (1 << 8) | CCM_CCGR1_CG5_Pos // CCGR1, CG5 + ClockIpPit Clock = (1 << 8) | CCM_CCGR1_CG6_Pos // CCGR1, CG6 + ClockIpAoi2 Clock = (1 << 8) | CCM_CCGR1_CG7_Pos // CCGR1, CG7 + ClockIpAdc1 Clock = (1 << 8) | CCM_CCGR1_CG8_Pos // CCGR1, CG8 + ClockIpSemcExsc Clock = (1 << 8) | CCM_CCGR1_CG9_Pos // CCGR1, CG9 + ClockIpGpt1 Clock = (1 << 8) | CCM_CCGR1_CG10_Pos // CCGR1, CG10 + ClockIpGpt1S Clock = (1 << 8) | CCM_CCGR1_CG11_Pos // CCGR1, CG11 + ClockIpLpuart4 Clock = (1 << 8) | CCM_CCGR1_CG12_Pos // CCGR1, CG12 + ClockIpGpio1 Clock = (1 << 8) | CCM_CCGR1_CG13_Pos // CCGR1, CG13 + ClockIpCsu Clock = (1 << 8) | CCM_CCGR1_CG14_Pos // CCGR1, CG14 + ClockIpGpio5 Clock = (1 << 8) | CCM_CCGR1_CG15_Pos // CCGR1, CG15 + + ClockIpOcramExsc Clock = (2 << 8) | CCM_CCGR2_CG0_Pos // CCGR2, CG0 + ClockIpCsi Clock = (2 << 8) | CCM_CCGR2_CG1_Pos // CCGR2, CG1 + ClockIpIomuxcSnvs Clock = (2 << 8) | CCM_CCGR2_CG2_Pos // CCGR2, CG2 + ClockIpLpi2c1 Clock = (2 << 8) | CCM_CCGR2_CG3_Pos // CCGR2, CG3 + ClockIpLpi2c2 Clock = (2 << 8) | CCM_CCGR2_CG4_Pos // CCGR2, CG4 + ClockIpLpi2c3 Clock = (2 << 8) | CCM_CCGR2_CG5_Pos // CCGR2, CG5 + ClockIpOcotp Clock = (2 << 8) | CCM_CCGR2_CG6_Pos // CCGR2, CG6 + ClockIpXbar3 Clock = (2 << 8) | CCM_CCGR2_CG7_Pos // CCGR2, CG7 + ClockIpIpmux1 Clock = (2 << 8) | CCM_CCGR2_CG8_Pos // CCGR2, CG8 + ClockIpIpmux2 Clock = (2 << 8) | CCM_CCGR2_CG9_Pos // CCGR2, CG9 + ClockIpIpmux3 Clock = (2 << 8) | CCM_CCGR2_CG10_Pos // CCGR2, CG10 + ClockIpXbar1 Clock = (2 << 8) | CCM_CCGR2_CG11_Pos // CCGR2, CG11 + ClockIpXbar2 Clock = (2 << 8) | CCM_CCGR2_CG12_Pos // CCGR2, CG12 + ClockIpGpio3 Clock = (2 << 8) | CCM_CCGR2_CG13_Pos // CCGR2, CG13 + ClockIpLcd Clock = (2 << 8) | CCM_CCGR2_CG14_Pos // CCGR2, CG14 + ClockIpPxp Clock = (2 << 8) | CCM_CCGR2_CG15_Pos // CCGR2, CG15 + + ClockIpFlexio2 Clock = (3 << 8) | CCM_CCGR3_CG0_Pos // CCGR3, CG0 + ClockIpLpuart5 Clock = (3 << 8) | CCM_CCGR3_CG1_Pos // CCGR3, CG1 + ClockIpSemc Clock = (3 << 8) | CCM_CCGR3_CG2_Pos // CCGR3, CG2 + ClockIpLpuart6 Clock = (3 << 8) | CCM_CCGR3_CG3_Pos // CCGR3, CG3 + ClockIpAoi1 Clock = (3 << 8) | CCM_CCGR3_CG4_Pos // CCGR3, CG4 + ClockIpLcdPixel Clock = (3 << 8) | CCM_CCGR3_CG5_Pos // CCGR3, CG5 + ClockIpGpio4 Clock = (3 << 8) | CCM_CCGR3_CG6_Pos // CCGR3, CG6 + ClockIpEwm0 Clock = (3 << 8) | CCM_CCGR3_CG7_Pos // CCGR3, CG7 + ClockIpWdog1 Clock = (3 << 8) | CCM_CCGR3_CG8_Pos // CCGR3, CG8 + ClockIpFlexRam Clock = (3 << 8) | CCM_CCGR3_CG9_Pos // CCGR3, CG9 + ClockIpAcmp1 Clock = (3 << 8) | CCM_CCGR3_CG10_Pos // CCGR3, CG10 + ClockIpAcmp2 Clock = (3 << 8) | CCM_CCGR3_CG11_Pos // CCGR3, CG11 + ClockIpAcmp3 Clock = (3 << 8) | CCM_CCGR3_CG12_Pos // CCGR3, CG12 + ClockIpAcmp4 Clock = (3 << 8) | CCM_CCGR3_CG13_Pos // CCGR3, CG13 + ClockIpOcram Clock = (3 << 8) | CCM_CCGR3_CG14_Pos // CCGR3, CG14 + ClockIpIomuxcSnvsGpr Clock = (3 << 8) | CCM_CCGR3_CG15_Pos // CCGR3, CG15 + + ClockIpIomuxc Clock = (4 << 8) | CCM_CCGR4_CG1_Pos // CCGR4, CG1 + ClockIpIomuxcGpr Clock = (4 << 8) | CCM_CCGR4_CG2_Pos // CCGR4, CG2 + ClockIpBee Clock = (4 << 8) | CCM_CCGR4_CG3_Pos // CCGR4, CG3 + ClockIpSimM7 Clock = (4 << 8) | CCM_CCGR4_CG4_Pos // CCGR4, CG4 + ClockIpTsc Clock = (4 << 8) | CCM_CCGR4_CG5_Pos // CCGR4, CG5 + ClockIpSimM Clock = (4 << 8) | CCM_CCGR4_CG6_Pos // CCGR4, CG6 + ClockIpSimEms Clock = (4 << 8) | CCM_CCGR4_CG7_Pos // CCGR4, CG7 + ClockIpPwm1 Clock = (4 << 8) | CCM_CCGR4_CG8_Pos // CCGR4, CG8 + ClockIpPwm2 Clock = (4 << 8) | CCM_CCGR4_CG9_Pos // CCGR4, CG9 + ClockIpPwm3 Clock = (4 << 8) | CCM_CCGR4_CG10_Pos // CCGR4, CG10 + ClockIpPwm4 Clock = (4 << 8) | CCM_CCGR4_CG11_Pos // CCGR4, CG11 + ClockIpEnc1 Clock = (4 << 8) | CCM_CCGR4_CG12_Pos // CCGR4, CG12 + ClockIpEnc2 Clock = (4 << 8) | CCM_CCGR4_CG13_Pos // CCGR4, CG13 + ClockIpEnc3 Clock = (4 << 8) | CCM_CCGR4_CG14_Pos // CCGR4, CG14 + ClockIpEnc4 Clock = (4 << 8) | CCM_CCGR4_CG15_Pos // CCGR4, CG15 + + ClockIpRom Clock = (5 << 8) | CCM_CCGR5_CG0_Pos // CCGR5, CG0 + ClockIpFlexio1 Clock = (5 << 8) | CCM_CCGR5_CG1_Pos // CCGR5, CG1 + ClockIpWdog3 Clock = (5 << 8) | CCM_CCGR5_CG2_Pos // CCGR5, CG2 + ClockIpDma Clock = (5 << 8) | CCM_CCGR5_CG3_Pos // CCGR5, CG3 + ClockIpKpp Clock = (5 << 8) | CCM_CCGR5_CG4_Pos // CCGR5, CG4 + ClockIpWdog2 Clock = (5 << 8) | CCM_CCGR5_CG5_Pos // CCGR5, CG5 + ClockIpAipsTz4 Clock = (5 << 8) | CCM_CCGR5_CG6_Pos // CCGR5, CG6 + ClockIpSpdif Clock = (5 << 8) | CCM_CCGR5_CG7_Pos // CCGR5, CG7 + ClockIpSimMain Clock = (5 << 8) | CCM_CCGR5_CG8_Pos // CCGR5, CG8 + ClockIpSai1 Clock = (5 << 8) | CCM_CCGR5_CG9_Pos // CCGR5, CG9 + ClockIpSai2 Clock = (5 << 8) | CCM_CCGR5_CG10_Pos // CCGR5, CG10 + ClockIpSai3 Clock = (5 << 8) | CCM_CCGR5_CG11_Pos // CCGR5, CG11 + ClockIpLpuart1 Clock = (5 << 8) | CCM_CCGR5_CG12_Pos // CCGR5, CG12 + ClockIpLpuart7 Clock = (5 << 8) | CCM_CCGR5_CG13_Pos // CCGR5, CG13 + ClockIpSnvsHp Clock = (5 << 8) | CCM_CCGR5_CG14_Pos // CCGR5, CG14 + ClockIpSnvsLp Clock = (5 << 8) | CCM_CCGR5_CG15_Pos // CCGR5, CG15 + + ClockIpUsbOh3 Clock = (6 << 8) | CCM_CCGR6_CG0_Pos // CCGR6, CG0 + ClockIpUsdhc1 Clock = (6 << 8) | CCM_CCGR6_CG1_Pos // CCGR6, CG1 + ClockIpUsdhc2 Clock = (6 << 8) | CCM_CCGR6_CG2_Pos // CCGR6, CG2 + ClockIpDcdc Clock = (6 << 8) | CCM_CCGR6_CG3_Pos // CCGR6, CG3 + ClockIpIpmux4 Clock = (6 << 8) | CCM_CCGR6_CG4_Pos // CCGR6, CG4 + ClockIpFlexSpi Clock = (6 << 8) | CCM_CCGR6_CG5_Pos // CCGR6, CG5 + ClockIpTrng Clock = (6 << 8) | CCM_CCGR6_CG6_Pos // CCGR6, CG6 + ClockIpLpuart8 Clock = (6 << 8) | CCM_CCGR6_CG7_Pos // CCGR6, CG7 + ClockIpTimer4 Clock = (6 << 8) | CCM_CCGR6_CG8_Pos // CCGR6, CG8 + ClockIpAipsTz3 Clock = (6 << 8) | CCM_CCGR6_CG9_Pos // CCGR6, CG9 + ClockIpSimPer Clock = (6 << 8) | CCM_CCGR6_CG10_Pos // CCGR6, CG10 + ClockIpAnadig Clock = (6 << 8) | CCM_CCGR6_CG11_Pos // CCGR6, CG11 + ClockIpLpi2c4 Clock = (6 << 8) | CCM_CCGR6_CG12_Pos // CCGR6, CG12 + ClockIpTimer1 Clock = (6 << 8) | CCM_CCGR6_CG13_Pos // CCGR6, CG13 + ClockIpTimer2 Clock = (6 << 8) | CCM_CCGR6_CG14_Pos // CCGR6, CG14 + ClockIpTimer3 Clock = (6 << 8) | CCM_CCGR6_CG15_Pos // CCGR6, CG15 + + ClockIpEnet2 Clock = (7 << 8) | CCM_CCGR7_CG0_Pos // CCGR7, CG0 + ClockIpFlexSpi2 Clock = (7 << 8) | CCM_CCGR7_CG1_Pos // CCGR7, CG1 + ClockIpAxbsL Clock = (7 << 8) | CCM_CCGR7_CG2_Pos // CCGR7, CG2 + ClockIpCan3 Clock = (7 << 8) | CCM_CCGR7_CG3_Pos // CCGR7, CG3 + ClockIpCan3S Clock = (7 << 8) | CCM_CCGR7_CG4_Pos // CCGR7, CG4 + ClockIpAipsLite Clock = (7 << 8) | CCM_CCGR7_CG5_Pos // CCGR7, CG5 + ClockIpFlexio3 Clock = (7 << 8) | CCM_CCGR7_CG6_Pos // CCGR7, CG6 +) + +// PLL name +const ( + ClockPllArm Clock = ((offPllArm & 0xFFF) << 16) | CCM_ANALOG_PLL_ARM_ENABLE_Pos // PLL ARM + ClockPllSys Clock = ((offPllSys & 0xFFF) << 16) | CCM_ANALOG_PLL_SYS_ENABLE_Pos // PLL SYS + ClockPllUsb1 Clock = ((offPllUsb1 & 0xFFF) << 16) | CCM_ANALOG_PLL_USB1_ENABLE_Pos // PLL USB1 + ClockPllAudio Clock = ((offPllAudio & 0xFFF) << 16) | CCM_ANALOG_PLL_AUDIO_ENABLE_Pos // PLL Audio + ClockPllVideo Clock = ((offPllVideo & 0xFFF) << 16) | CCM_ANALOG_PLL_VIDEO_ENABLE_Pos // PLL Video + ClockPllEnet Clock = ((offPllEnet & 0xFFF) << 16) | CCM_ANALOG_PLL_ENET_ENABLE_Pos // PLL Enet0 + ClockPllEnet2 Clock = ((offPllEnet & 0xFFF) << 16) | CCM_ANALOG_PLL_ENET_ENET2_REF_EN_Pos // PLL Enet1 + ClockPllEnet25M Clock = ((offPllEnet & 0xFFF) << 16) | CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_Pos // PLL Enet2 + ClockPllUsb2 Clock = ((offPllUsb2 & 0xFFF) << 16) | CCM_ANALOG_PLL_USB2_ENABLE_Pos // PLL USB2 +) + +// PLL PFD name +const ( + ClockPfd0 Clock = 0 // PLL PFD0 + ClockPfd1 Clock = 1 // PLL PFD1 + ClockPfd2 Clock = 2 // PLL PFD2 + ClockPfd3 Clock = 3 // PLL PFD3 +) + +const ( + MuxIpPll3Sw Clock = (offCCSR & 0xFF) | (CCM_CCSR_PLL3_SW_CLK_SEL_Pos << 8) | (((CCM_CCSR_PLL3_SW_CLK_SEL_Msk >> CCM_CCSR_PLL3_SW_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // pll3_sw_clk mux name + MuxIpPeriph Clock = (offCBCDR & 0xFF) | (CCM_CBCDR_PERIPH_CLK_SEL_Pos << 8) | (((CCM_CBCDR_PERIPH_CLK_SEL_Msk >> CCM_CBCDR_PERIPH_CLK_SEL_Pos) & 0x1FFF) << 13) | (CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_Pos << 26) // periph mux name + MuxIpSemcAlt Clock = (offCBCDR & 0xFF) | (CCM_CBCDR_SEMC_ALT_CLK_SEL_Pos << 8) | (((CCM_CBCDR_SEMC_ALT_CLK_SEL_Msk >> CCM_CBCDR_SEMC_ALT_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // semc mux name + MuxIpSemc Clock = (offCBCDR & 0xFF) | (CCM_CBCDR_SEMC_CLK_SEL_Pos << 8) | (((CCM_CBCDR_SEMC_CLK_SEL_Msk >> CCM_CBCDR_SEMC_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // semc mux name + MuxIpPrePeriph Clock = (offCBCMR & 0xFF) | (CCM_CBCMR_PRE_PERIPH_CLK_SEL_Pos << 8) | (((CCM_CBCMR_PRE_PERIPH_CLK_SEL_Msk >> CCM_CBCMR_PRE_PERIPH_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // pre-periph mux name + MuxIpTrace Clock = (offCBCMR & 0xFF) | (CCM_CBCMR_TRACE_CLK_SEL_Pos << 8) | (((CCM_CBCMR_TRACE_CLK_SEL_Msk >> CCM_CBCMR_TRACE_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // trace mux name + MuxIpPeriphClk2 Clock = (offCBCMR & 0xFF) | (CCM_CBCMR_PERIPH_CLK2_SEL_Pos << 8) | (((CCM_CBCMR_PERIPH_CLK2_SEL_Msk >> CCM_CBCMR_PERIPH_CLK2_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // periph clock2 mux name + MuxIpFlexSpi2 Clock = (offCBCMR & 0xFF) | (CCM_CBCMR_FLEXSPI2_CLK_SEL_Pos << 8) | (((CCM_CBCMR_FLEXSPI2_CLK_SEL_Msk >> CCM_CBCMR_FLEXSPI2_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // flexspi2 mux name + MuxIpLpspi Clock = (offCBCMR & 0xFF) | (CCM_CBCMR_LPSPI_CLK_SEL_Pos << 8) | (((CCM_CBCMR_LPSPI_CLK_SEL_Msk >> CCM_CBCMR_LPSPI_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // lpspi mux name + MuxIpFlexSpi Clock = (offCSCMR1 & 0xFF) | (CCM_CSCMR1_FLEXSPI_CLK_SEL_Pos << 8) | (((CCM_CSCMR1_FLEXSPI_CLK_SEL_Msk >> CCM_CSCMR1_FLEXSPI_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // flexspi mux name + MuxIpUsdhc2 Clock = (offCSCMR1 & 0xFF) | (CCM_CSCMR1_USDHC2_CLK_SEL_Pos << 8) | (((CCM_CSCMR1_USDHC2_CLK_SEL_Msk >> CCM_CSCMR1_USDHC2_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // usdhc2 mux name + MuxIpUsdhc1 Clock = (offCSCMR1 & 0xFF) | (CCM_CSCMR1_USDHC1_CLK_SEL_Pos << 8) | (((CCM_CSCMR1_USDHC1_CLK_SEL_Msk >> CCM_CSCMR1_USDHC1_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // usdhc1 mux name + MuxIpSai3 Clock = (offCSCMR1 & 0xFF) | (CCM_CSCMR1_SAI3_CLK_SEL_Pos << 8) | (((CCM_CSCMR1_SAI3_CLK_SEL_Msk >> CCM_CSCMR1_SAI3_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // sai3 mux name + MuxIpSai2 Clock = (offCSCMR1 & 0xFF) | (CCM_CSCMR1_SAI2_CLK_SEL_Pos << 8) | (((CCM_CSCMR1_SAI2_CLK_SEL_Msk >> CCM_CSCMR1_SAI2_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // sai2 mux name + MuxIpSai1 Clock = (offCSCMR1 & 0xFF) | (CCM_CSCMR1_SAI1_CLK_SEL_Pos << 8) | (((CCM_CSCMR1_SAI1_CLK_SEL_Msk >> CCM_CSCMR1_SAI1_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // sai1 mux name + MuxIpPerclk Clock = (offCSCMR1 & 0xFF) | (CCM_CSCMR1_PERCLK_CLK_SEL_Pos << 8) | (((CCM_CSCMR1_PERCLK_CLK_SEL_Msk >> CCM_CSCMR1_PERCLK_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // perclk mux name + MuxIpFlexio2 Clock = (offCSCMR2 & 0xFF) | (CCM_CSCMR2_FLEXIO2_CLK_SEL_Pos << 8) | (((CCM_CSCMR2_FLEXIO2_CLK_SEL_Msk >> CCM_CSCMR2_FLEXIO2_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // flexio2 mux name + MuxIpCan Clock = (offCSCMR2 & 0xFF) | (CCM_CSCMR2_CAN_CLK_SEL_Pos << 8) | (((CCM_CSCMR2_CAN_CLK_SEL_Msk >> CCM_CSCMR2_CAN_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // can mux name + MuxIpUart Clock = (offCSCDR1 & 0xFF) | (CCM_CSCDR1_UART_CLK_SEL_Pos << 8) | (((CCM_CSCDR1_UART_CLK_SEL_Msk >> CCM_CSCDR1_UART_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // uart mux name + MuxIpSpdif Clock = (offCDCDR & 0xFF) | (CCM_CDCDR_SPDIF0_CLK_SEL_Pos << 8) | (((CCM_CDCDR_SPDIF0_CLK_SEL_Msk >> CCM_CDCDR_SPDIF0_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // spdif mux name + MuxIpFlexio1 Clock = (offCDCDR & 0xFF) | (CCM_CDCDR_FLEXIO1_CLK_SEL_Pos << 8) | (((CCM_CDCDR_FLEXIO1_CLK_SEL_Msk >> CCM_CDCDR_FLEXIO1_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // flexio1 mux name + MuxIpLpi2c Clock = (offCSCDR2 & 0xFF) | (CCM_CSCDR2_LPI2C_CLK_SEL_Pos << 8) | (((CCM_CSCDR2_LPI2C_CLK_SEL_Msk >> CCM_CSCDR2_LPI2C_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // lpi2c mux name + MuxIpLcdifPre Clock = (offCSCDR2 & 0xFF) | (CCM_CSCDR2_LCDIF_PRE_CLK_SEL_Pos << 8) | (((CCM_CSCDR2_LCDIF_PRE_CLK_SEL_Msk >> CCM_CSCDR2_LCDIF_PRE_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // lcdif pre mux name + MuxIpCsi Clock = (offCSCDR3 & 0xFF) | (CCM_CSCDR3_CSI_CLK_SEL_Pos << 8) | (((CCM_CSCDR3_CSI_CLK_SEL_Msk >> CCM_CSCDR3_CSI_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // csi mux name +) + +const ( + DivIpArm Clock = (offCACRR & 0xFF) | (CCM_CACRR_ARM_PODF_Pos << 8) | (((CCM_CACRR_ARM_PODF_Msk >> CCM_CACRR_ARM_PODF_Pos) & 0x1FFF) << 13) | (CCM_CDHIPR_ARM_PODF_BUSY_Pos << 26) // core div name + DivIpPeriphClk2 Clock = (offCBCDR & 0xFF) | (CCM_CBCDR_PERIPH_CLK2_PODF_Pos << 8) | (((CCM_CBCDR_PERIPH_CLK2_PODF_Msk >> CCM_CBCDR_PERIPH_CLK2_PODF_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // periph clock2 div name + DivIpSemc Clock = (offCBCDR & 0xFF) | (CCM_CBCDR_SEMC_PODF_Pos << 8) | (((CCM_CBCDR_SEMC_PODF_Msk >> CCM_CBCDR_SEMC_PODF_Pos) & 0x1FFF) << 13) | (CCM_CDHIPR_SEMC_PODF_BUSY_Pos << 26) // semc div name + DivIpAhb Clock = (offCBCDR & 0xFF) | (CCM_CBCDR_AHB_PODF_Pos << 8) | (((CCM_CBCDR_AHB_PODF_Msk >> CCM_CBCDR_AHB_PODF_Pos) & 0x1FFF) << 13) | (CCM_CDHIPR_AHB_PODF_BUSY_Pos << 26) // ahb div name + DivIpIpg Clock = (offCBCDR & 0xFF) | (CCM_CBCDR_IPG_PODF_Pos << 8) | (((CCM_CBCDR_IPG_PODF_Msk >> CCM_CBCDR_IPG_PODF_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // ipg div name + DivIpFlexSpi2 Clock = (offCBCMR & 0xFF) | (CCM_CBCMR_FLEXSPI2_PODF_Pos << 8) | (((CCM_CBCMR_FLEXSPI2_PODF_Msk >> CCM_CBCMR_FLEXSPI2_PODF_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // flexspi2 div name + DivIpLpspi Clock = (offCBCMR & 0xFF) | (CCM_CBCMR_LPSPI_PODF_Pos << 8) | (((CCM_CBCMR_LPSPI_PODF_Msk >> CCM_CBCMR_LPSPI_PODF_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // lpspi div name + DivIpLcdif Clock = (offCBCMR & 0xFF) | (CCM_CBCMR_LCDIF_PODF_Pos << 8) | (((CCM_CBCMR_LCDIF_PODF_Msk >> CCM_CBCMR_LCDIF_PODF_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // lcdif div name + DivIpFlexSpi Clock = (offCSCMR1 & 0xFF) | (CCM_CSCMR1_FLEXSPI_PODF_Pos << 8) | (((CCM_CSCMR1_FLEXSPI_PODF_Msk >> CCM_CSCMR1_FLEXSPI_PODF_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // flexspi div name + DivIpPerclk Clock = (offCSCMR1 & 0xFF) | (CCM_CSCMR1_PERCLK_PODF_Pos << 8) | (((CCM_CSCMR1_PERCLK_PODF_Msk >> CCM_CSCMR1_PERCLK_PODF_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // perclk div name + DivIpCan Clock = (offCSCMR2 & 0xFF) | (CCM_CSCMR2_CAN_CLK_PODF_Pos << 8) | (((CCM_CSCMR2_CAN_CLK_PODF_Msk >> CCM_CSCMR2_CAN_CLK_PODF_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // can div name + DivIpTrace Clock = (offCSCDR1 & 0xFF) | (CCM_CSCDR1_TRACE_PODF_Pos << 8) | (((CCM_CSCDR1_TRACE_PODF_Msk >> CCM_CSCDR1_TRACE_PODF_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // trace div name + DivIpUsdhc2 Clock = (offCSCDR1 & 0xFF) | (CCM_CSCDR1_USDHC2_PODF_Pos << 8) | (((CCM_CSCDR1_USDHC2_PODF_Msk >> CCM_CSCDR1_USDHC2_PODF_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // usdhc2 div name + DivIpUsdhc1 Clock = (offCSCDR1 & 0xFF) | (CCM_CSCDR1_USDHC1_PODF_Pos << 8) | (((CCM_CSCDR1_USDHC1_PODF_Msk >> CCM_CSCDR1_USDHC1_PODF_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // usdhc1 div name + DivIpUart Clock = (offCSCDR1 & 0xFF) | (CCM_CSCDR1_UART_CLK_PODF_Pos << 8) | (((CCM_CSCDR1_UART_CLK_PODF_Msk >> CCM_CSCDR1_UART_CLK_PODF_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // uart div name + DivIpFlexio2 Clock = (offCS1CDR & 0xFF) | (CCM_CS1CDR_FLEXIO2_CLK_PODF_Pos << 8) | (((CCM_CS1CDR_FLEXIO2_CLK_PODF_Msk >> CCM_CS1CDR_FLEXIO2_CLK_PODF_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // flexio2 pre div name + DivIpSai3Pre Clock = (offCS1CDR & 0xFF) | (CCM_CS1CDR_SAI3_CLK_PRED_Pos << 8) | (((CCM_CS1CDR_SAI3_CLK_PRED_Msk >> CCM_CS1CDR_SAI3_CLK_PRED_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // sai3 pre div name + DivIpSai3 Clock = (offCS1CDR & 0xFF) | (CCM_CS1CDR_SAI3_CLK_PODF_Pos << 8) | (((CCM_CS1CDR_SAI3_CLK_PODF_Msk >> CCM_CS1CDR_SAI3_CLK_PODF_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // sai3 div name + DivIpFlexio2Pre Clock = (offCS1CDR & 0xFF) | (CCM_CS1CDR_FLEXIO2_CLK_PRED_Pos << 8) | (((CCM_CS1CDR_FLEXIO2_CLK_PRED_Msk >> CCM_CS1CDR_FLEXIO2_CLK_PRED_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // sai3 pre div name + DivIpSai1Pre Clock = (offCS1CDR & 0xFF) | (CCM_CS1CDR_SAI1_CLK_PRED_Pos << 8) | (((CCM_CS1CDR_SAI1_CLK_PRED_Msk >> CCM_CS1CDR_SAI1_CLK_PRED_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // sai1 pre div name + DivIpSai1 Clock = (offCS1CDR & 0xFF) | (CCM_CS1CDR_SAI1_CLK_PODF_Pos << 8) | (((CCM_CS1CDR_SAI1_CLK_PODF_Msk >> CCM_CS1CDR_SAI1_CLK_PODF_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // sai1 div name + DivIpSai2Pre Clock = (offCS2CDR & 0xFF) | (CCM_CS2CDR_SAI2_CLK_PRED_Pos << 8) | (((CCM_CS2CDR_SAI2_CLK_PRED_Msk >> CCM_CS2CDR_SAI2_CLK_PRED_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // sai2 pre div name + DivIpSai2 Clock = (offCS2CDR & 0xFF) | (CCM_CS2CDR_SAI2_CLK_PODF_Pos << 8) | (((CCM_CS2CDR_SAI2_CLK_PODF_Msk >> CCM_CS2CDR_SAI2_CLK_PODF_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // sai2 div name + DivIpSpdif0Pre Clock = (offCDCDR & 0xFF) | (CCM_CDCDR_SPDIF0_CLK_PRED_Pos << 8) | (((CCM_CDCDR_SPDIF0_CLK_PRED_Msk >> CCM_CDCDR_SPDIF0_CLK_PRED_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // spdif pre div name + DivIpSpdif0 Clock = (offCDCDR & 0xFF) | (CCM_CDCDR_SPDIF0_CLK_PODF_Pos << 8) | (((CCM_CDCDR_SPDIF0_CLK_PODF_Msk >> CCM_CDCDR_SPDIF0_CLK_PODF_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // spdif div name + DivIpFlexio1Pre Clock = (offCDCDR & 0xFF) | (CCM_CDCDR_FLEXIO1_CLK_PRED_Pos << 8) | (((CCM_CDCDR_FLEXIO1_CLK_PRED_Msk >> CCM_CDCDR_FLEXIO1_CLK_PRED_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // flexio1 pre div name + DivIpFlexio1 Clock = (offCDCDR & 0xFF) | (CCM_CDCDR_FLEXIO1_CLK_PODF_Pos << 8) | (((CCM_CDCDR_FLEXIO1_CLK_PODF_Msk >> CCM_CDCDR_FLEXIO1_CLK_PODF_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // flexio1 div name + DivIpLpi2c Clock = (offCSCDR2 & 0xFF) | (CCM_CSCDR2_LPI2C_CLK_PODF_Pos << 8) | (((CCM_CSCDR2_LPI2C_CLK_PODF_Msk >> CCM_CSCDR2_LPI2C_CLK_PODF_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // lpi2c div name + DivIpLcdifPre Clock = (offCSCDR2 & 0xFF) | (CCM_CSCDR2_LCDIF_PRED_Pos << 8) | (((CCM_CSCDR2_LCDIF_PRED_Msk >> CCM_CSCDR2_LCDIF_PRED_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // lcdif pre div name + DivIpCsi Clock = (offCSCDR3 & 0xFF) | (CCM_CSCDR3_CSI_PODF_Pos << 8) | (((CCM_CSCDR3_CSI_PODF_Msk >> CCM_CSCDR3_CSI_PODF_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // csi div name +) + +// Selected clock offsets +const ( + offCCSR = 0x0C + offCBCDR = 0x14 + offCBCMR = 0x18 + offCSCMR1 = 0x1C + offCSCMR2 = 0x20 + offCSCDR1 = 0x24 + offCDCDR = 0x30 + offCSCDR2 = 0x38 + offCSCDR3 = 0x3C + offCACRR = 0x10 + offCS1CDR = 0x28 + offCS2CDR = 0x2C + + offPllArm = 0x00 + offPllSys = 0x30 + offPllUsb1 = 0x10 + offPllAudio = 0x70 + offPllVideo = 0xA0 + offPllEnet = 0xE0 + offPllUsb2 = 0x20 + + noBusyWait = 0x20 +) + +// analog pll definition +const ( + pllBypassPos = 16 + pllBypassClkSrcMsk = 0xC000 + pllBypassClkSrcPos = 14 +) + +// PLL clock source, bypass cloco source also +const ( + pllSrc24M = 0 // Pll clock source 24M + pllSrcClkPN = 1 // Pll clock source CLK1_P and CLK1_N +) + +// Set configures the run mode of the MCU. +func (m ClockMode) Set() { + CCM.CLPCR.Set((CCM.CLPCR.Get() & ^uint32(CCM_CLPCR_LPM_Msk)) | + ((uint32(m) << CCM_CLPCR_LPM_Pos) & CCM_CLPCR_LPM_Msk)) +} + +// Enable activates or deactivates the clock gate of receiver Clock clk. +func (clk Clock) Enable(enable bool) { + if enable { + clk.control(GateClkNeededRunWait) + } else { + clk.control(GateClkNotNeeded) + } +} + +// Mux selects a clock source for the mux of the receiver Clock clk. +func (clk Clock) Mux(mux uint32) { clk.ccm(mux) } + +// Div configures the prescalar divisor of the receiver Clock clk. +func (clk Clock) Div(div uint32) { clk.ccm(div) } + +// getCCGR returns the CCM clock gating register for the receiver clk. +func (clk Clock) getCCGR() *volatile.Register32 { + switch clk >> 8 { + case 0: + return &CCM.CCGR0 + case 1: + return &CCM.CCGR1 + case 2: + return &CCM.CCGR2 + case 3: + return &CCM.CCGR3 + case 4: + return &CCM.CCGR4 + case 5: + return &CCM.CCGR5 + case 6: + return &CCM.CCGR6 + case 7: + return &CCM.CCGR7 + default: + panic("nxp: invalid clock") + } +} + +// control enables or disables the receiver clk using its gating register. +func (clk Clock) control(value Gate) { + reg := clk.getCCGR() + shift := clk & 0x1F + reg.Set((reg.Get() & ^(3 << shift)) | (uint32(value) << shift)) +} + +func (clk Clock) ccm(value uint32) { + const ccmBase = 0x400fc000 + reg := (*volatile.Register32)(unsafe.Pointer(uintptr(ccmBase + (uint32(clk) & 0xFF)))) + msk := ((uint32(clk) >> 13) & 0x1FFF) << ((uint32(clk) >> 8) & 0x1F) + pos := (uint32(clk) >> 8) & 0x1F + bsy := (uint32(clk) >> 26) & 0x3F + reg.Set((reg.Get() & ^uint32(msk)) | ((value << pos) & msk)) + if bsy < noBusyWait { + for CCM.CDHIPR.HasBits(1 << bsy) { + } + } +} + +// GetFreq returns the calculated frequency of the receiver clock clk. +func (clk Clock) GetFreq() uint32 { + switch clk { + case ClockCpu, ClockAhb: + return getAhbFreq() + case ClockSemc: + return getSemcFreq() + case ClockIpg: + return getIpgFreq() + case ClockPer: + return getPerClkFreq() + case ClockOsc: + return getOscFreq() + case ClockRtc: + return getRtcFreq() + case ClockArmPll: + return ClockPllArm.getPllFreq() + case ClockUsb1Pll: + return ClockPllUsb1.getPllFreq() + case ClockUsb1PllPfd0: + return ClockPfd0.getUsb1PfdFreq() + case ClockUsb1PllPfd1: + return ClockPfd1.getUsb1PfdFreq() + case ClockUsb1PllPfd2: + return ClockPfd2.getUsb1PfdFreq() + case ClockUsb1PllPfd3: + return ClockPfd3.getUsb1PfdFreq() + case ClockUsb2Pll: + return ClockPllUsb2.getPllFreq() + case ClockSysPll: + return ClockPllSys.getPllFreq() + case ClockSysPllPfd0: + return ClockPfd0.getSysPfdFreq() + case ClockSysPllPfd1: + return ClockPfd1.getSysPfdFreq() + case ClockSysPllPfd2: + return ClockPfd2.getSysPfdFreq() + case ClockSysPllPfd3: + return ClockPfd3.getSysPfdFreq() + case ClockEnetPll0: + return ClockPllEnet.getPllFreq() + case ClockEnetPll1: + return ClockPllEnet2.getPllFreq() + case ClockEnetPll2: + return ClockPllEnet25M.getPllFreq() + case ClockAudioPll: + return ClockPllAudio.getPllFreq() + case ClockVideoPll: + return ClockPllVideo.getPllFreq() + default: + panic("nxp: invalid clock") + } +} + +// getOscFreq returns the XTAL OSC clock frequency +func getOscFreq() uint32 { + return 24000000 // 24 MHz +} + +// getRtcFreq returns the RTC clock frequency +func getRtcFreq() uint32 { + return 32768 // 32.768 kHz +} + +func ccmCbcmrPeriphClk2Sel(n uint32) uint32 { + return (n << CCM_CBCMR_PERIPH_CLK2_SEL_Pos) & CCM_CBCMR_PERIPH_CLK2_SEL_Msk +} + +func ccmCbcmrPrePeriphClkSel(n uint32) uint32 { + return (n << CCM_CBCMR_PRE_PERIPH_CLK_SEL_Pos) & CCM_CBCMR_PRE_PERIPH_CLK_SEL_Msk +} + +// getPeriphClkFreq returns the PERIPH clock frequency +func getPeriphClkFreq() uint32 { + freq := uint32(0) + if CCM.CBCDR.HasBits(CCM_CBCDR_PERIPH_CLK_SEL_Msk) { + // Periph_clk2_clk -> Periph_clk + switch CCM.CBCMR.Get() & CCM_CBCMR_PERIPH_CLK2_SEL_Msk { + case ccmCbcmrPeriphClk2Sel(0): + // Pll3_sw_clk -> Periph_clk2_clk -> Periph_clk + freq = ClockPllUsb1.getPllFreq() + case ccmCbcmrPeriphClk2Sel(1): + // Osc_clk -> Periph_clk2_clk -> Periph_clk + freq = getOscFreq() + case ccmCbcmrPeriphClk2Sel(2): + freq = ClockPllSys.getPllFreq() + case ccmCbcmrPeriphClk2Sel(3): + freq = 0 + } + freq /= ((CCM.CBCDR.Get() & CCM_CBCDR_PERIPH_CLK2_PODF_Msk) >> CCM_CBCDR_PERIPH_CLK2_PODF_Pos) + 1 + } else { + // Pre_Periph_clk -> Periph_clk + switch CCM.CBCMR.Get() & CCM_CBCMR_PRE_PERIPH_CLK_SEL_Msk { + case ccmCbcmrPrePeriphClkSel(0): + // PLL2 -> Pre_Periph_clk -> Periph_clk + freq = ClockPllSys.getPllFreq() + case ccmCbcmrPrePeriphClkSel(1): + // PLL2 PFD2 -> Pre_Periph_clk -> Periph_clk + freq = ClockPfd2.getSysPfdFreq() + case ccmCbcmrPrePeriphClkSel(2): + // PLL2 PFD0 -> Pre_Periph_clk -> Periph_clk + freq = ClockPfd0.getSysPfdFreq() + case ccmCbcmrPrePeriphClkSel(3): + // PLL1 divided(/2) -> Pre_Periph_clk -> Periph_clk + freq = ClockPllArm.getPllFreq() / (((CCM.CACRR.Get() & CCM_CACRR_ARM_PODF_Msk) >> CCM_CACRR_ARM_PODF_Pos) + 1) + } + } + return freq +} + +// getAhbFreq returns the AHB clock frequency +func getAhbFreq() uint32 { + return getPeriphClkFreq() / (((CCM.CBCDR.Get() & CCM_CBCDR_AHB_PODF_Msk) >> CCM_CBCDR_AHB_PODF_Pos) + 1) +} + +// getSemcFreq returns the SEMC clock frequency +func getSemcFreq() uint32 { + + freq := uint32(0) + + if CCM.CBCDR.HasBits(CCM_CBCDR_SEMC_CLK_SEL_Msk) { + // SEMC alternative clock -> SEMC Clock + + if CCM.CBCDR.HasBits(CCM_CBCDR_SEMC_ALT_CLK_SEL_Msk) { + // PLL3 PFD1 -> SEMC alternative clock -> SEMC Clock + freq = ClockPfd1.getUsb1PfdFreq() + } else { + // PLL2 PFD2 -> SEMC alternative clock -> SEMC Clock + freq = ClockPfd2.getSysPfdFreq() + } + } else { + // Periph_clk -> SEMC Clock + freq = getPeriphClkFreq() + } + + freq /= ((CCM.CBCDR.Get() & CCM_CBCDR_SEMC_PODF_Msk) >> CCM_CBCDR_SEMC_PODF_Pos) + 1 + + return freq +} + +// getIpgFreq returns the IPG clock frequency +func getIpgFreq() uint32 { + return getAhbFreq() / (((CCM.CBCDR.Get() & CCM_CBCDR_IPG_PODF_Msk) >> CCM_CBCDR_IPG_PODF_Pos) + 1) +} + +// getPerClkFreq returns the PER clock frequency +func getPerClkFreq() uint32 { + freq := uint32(0) + if CCM.CSCMR1.HasBits(CCM_CSCMR1_PERCLK_CLK_SEL_Msk) { + // Osc_clk -> PER Cloc + freq = getOscFreq() + } else { + // Periph_clk -> AHB Clock -> IPG Clock -> PER Clock + freq = getIpgFreq() + } + return freq/((CCM.CSCMR1.Get()&CCM_CSCMR1_PERCLK_PODF_Msk)>> + CCM_CSCMR1_PERCLK_PODF_Pos) + 1 +} + +// getPllFreq returns the clock frequency of the receiver (PLL) clock clk +func (clk Clock) getPllFreq() uint32 { + enetRefClkFreq := []uint32{ + 25000000, // 25 MHz + 50000000, // 50 MHz + 100000000, // 100 MHz + 125000000, // 125 MHz + } + // check if PLL is enabled + if !clk.isPllEnabled() { + return 0 + } + // get pll reference clock + freq := clk.getBypassFreq() + // check if pll is bypassed + if clk.isPllBypassed() { + return freq + } + switch clk { + case ClockPllArm: + freq *= (CCM_ANALOG.PLL_ARM.Get() & CCM_ANALOG_PLL_ARM_DIV_SELECT_Msk) >> CCM_ANALOG_PLL_ARM_DIV_SELECT_Pos + freq >>= 1 + case ClockPllSys: + // PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). + fFreq := float64(freq) * float64(CCM_ANALOG.PLL_SYS_NUM.Get()) + fFreq /= float64(CCM_ANALOG.PLL_SYS_DENOM.Get()) + if CCM_ANALOG.PLL_SYS.HasBits(CCM_ANALOG_PLL_SYS_DIV_SELECT_Msk) { + freq *= 22 + } else { + freq *= 20 + } + freq += uint32(fFreq) + case ClockPllUsb1: + if CCM_ANALOG.PLL_USB1.HasBits(CCM_ANALOG_PLL_USB1_DIV_SELECT_Msk) { + freq *= 22 + } else { + freq *= 20 + } + case ClockPllEnet: + divSelect := (CCM_ANALOG.PLL_ENET.Get() & CCM_ANALOG_PLL_ENET_DIV_SELECT_Msk) >> CCM_ANALOG_PLL_ENET_DIV_SELECT_Pos + freq = enetRefClkFreq[divSelect] + case ClockPllEnet2: + divSelect := (CCM_ANALOG.PLL_ENET.Get() & CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_Msk) >> CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_Pos + freq = enetRefClkFreq[divSelect] + case ClockPllEnet25M: + // ref_enetpll1 if fixed at 25MHz. + freq = 25000000 + case ClockPllUsb2: + if CCM_ANALOG.PLL_USB2.HasBits(CCM_ANALOG_PLL_USB2_DIV_SELECT_Msk) { + freq *= 22 + } else { + freq *= 20 + } + default: + freq = 0 + } + return freq +} + +// getSysPfdFreq returns current system PLL PFD output frequency +func (clk Clock) getSysPfdFreq() uint32 { + freq := ClockPllSys.getPllFreq() + switch clk { + case ClockPfd0: + freq /= (CCM_ANALOG.PFD_528.Get() & CCM_ANALOG_PFD_528_PFD0_FRAC_Msk) >> CCM_ANALOG_PFD_528_PFD0_FRAC_Pos + case ClockPfd1: + freq /= (CCM_ANALOG.PFD_528.Get() & CCM_ANALOG_PFD_528_PFD1_FRAC_Msk) >> CCM_ANALOG_PFD_528_PFD1_FRAC_Pos + case ClockPfd2: + freq /= (CCM_ANALOG.PFD_528.Get() & CCM_ANALOG_PFD_528_PFD2_FRAC_Msk) >> CCM_ANALOG_PFD_528_PFD2_FRAC_Pos + case ClockPfd3: + freq /= (CCM_ANALOG.PFD_528.Get() & CCM_ANALOG_PFD_528_PFD3_FRAC_Msk) >> CCM_ANALOG_PFD_528_PFD3_FRAC_Pos + default: + freq = 0 + } + return freq * 18 +} + +// getUsb1PfdFreq returns current USB1 PLL PFD output frequency +func (clk Clock) getUsb1PfdFreq() uint32 { + freq := ClockPllUsb1.getPllFreq() + switch clk { + case ClockPfd0: + freq /= (CCM_ANALOG.PFD_480.Get() & CCM_ANALOG_PFD_480_PFD0_FRAC_Msk) >> CCM_ANALOG_PFD_480_PFD0_FRAC_Pos + case ClockPfd1: + freq /= (CCM_ANALOG.PFD_480.Get() & CCM_ANALOG_PFD_480_PFD1_FRAC_Msk) >> CCM_ANALOG_PFD_480_PFD1_FRAC_Pos + case ClockPfd2: + freq /= (CCM_ANALOG.PFD_480.Get() & CCM_ANALOG_PFD_480_PFD2_FRAC_Msk) >> CCM_ANALOG_PFD_480_PFD2_FRAC_Pos + case ClockPfd3: + freq /= (CCM_ANALOG.PFD_480.Get() & CCM_ANALOG_PFD_480_PFD3_FRAC_Msk) >> CCM_ANALOG_PFD_480_PFD3_FRAC_Pos + default: + freq = 0 + } + return freq * 18 +} + +func setSysPfd(value ...uint32) { + for i, val := range value { + pfd528 := CCM_ANALOG.PFD_528.Get() & + ^((CCM_ANALOG_PFD_528_PFD0_CLKGATE_Msk | CCM_ANALOG_PFD_528_PFD0_FRAC_Msk) << (8 * uint32(i))) + frac := (val << CCM_ANALOG_PFD_528_PFD0_FRAC_Pos) & CCM_ANALOG_PFD_528_PFD0_FRAC_Msk + // disable the clock output first + CCM_ANALOG.PFD_528.Set(pfd528 | (CCM_ANALOG_PFD_528_PFD0_CLKGATE_Msk << (8 * uint32(i)))) + // set the new value and enable output + CCM_ANALOG.PFD_528.Set(pfd528 | (frac << (8 * uint32(i)))) + } +} + +func setUsb1Pfd(value ...uint32) { + for i, val := range value { + pfd480 := CCM_ANALOG.PFD_480.Get() & + ^((CCM_ANALOG_PFD_480_PFD0_CLKGATE_Msk | CCM_ANALOG_PFD_480_PFD0_FRAC_Msk) << (8 * uint32(i))) + frac := (val << CCM_ANALOG_PFD_480_PFD0_FRAC_Pos) & CCM_ANALOG_PFD_480_PFD0_FRAC_Msk + // disable the clock output first + CCM_ANALOG.PFD_480.Set(pfd480 | (CCM_ANALOG_PFD_480_PFD0_CLKGATE_Msk << (8 * uint32(i)))) + // set the new value and enable output + CCM_ANALOG.PFD_480.Set(pfd480 | (frac << (8 * uint32(i)))) + } +} + +func (clk Clock) isPllEnabled() bool { + const ccmAnalogBase = 0x400d8000 + addr := ccmAnalogBase + ((uint32(clk) >> 16) & 0xFFF) + pos := uint32(1 << (uint32(clk) & 0x1F)) + return ((*volatile.Register32)(unsafe.Pointer(uintptr(addr)))).HasBits(pos) +} + +func (clk Clock) isPllBypassed() bool { + const ccmAnalogBase = 0x400d8000 + addr := ccmAnalogBase + ((uint32(clk) >> 16) & 0xFFF) + pos := uint32(1 << pllBypassPos) + return ((*volatile.Register32)(unsafe.Pointer(uintptr(addr)))).HasBits(pos) +} + +func (clk Clock) getBypassFreq() uint32 { + const ccmAnalogBase = 0x400d8000 + addr := ccmAnalogBase + ((uint32(clk) >> 16) & 0xFFF) + src := (((*volatile.Register32)(unsafe.Pointer(uintptr(addr)))).Get() & + pllBypassClkSrcMsk) >> pllBypassClkSrcPos + if src == uint32(pllSrc24M) { + return getOscFreq() + } + return 0 +} + +func (clk Clock) bypass(bypass bool) { + const ccmAnalogBase = 0x400d8000 + if bypass { + addr := ccmAnalogBase + ((uint32(clk) >> 16) & 0xFFF) + 4 + ((*volatile.Register32)(unsafe.Pointer(uintptr(addr)))).Set(1 << pllBypassPos) + } else { + addr := ccmAnalogBase + ((uint32(clk) >> 16) & 0xFFF) + 8 + ((*volatile.Register32)(unsafe.Pointer(uintptr(addr)))).Set(1 << pllBypassPos) + } +} + +func (cfg ClockConfigArmPll) Configure() { + + // bypass PLL first + src := (uint32(cfg.Src) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_Pos) & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_Msk + CCM_ANALOG.PLL_ARM.Set( + (CCM_ANALOG.PLL_ARM.Get() & ^uint32(CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_Msk)) | + CCM_ANALOG_PLL_ARM_BYPASS_Msk | src) + + sel := (cfg.LoopDivider << CCM_ANALOG_PLL_ARM_DIV_SELECT_Pos) & CCM_ANALOG_PLL_ARM_DIV_SELECT_Msk + CCM_ANALOG.PLL_ARM.Set( + (CCM_ANALOG.PLL_ARM.Get() & ^uint32(CCM_ANALOG_PLL_ARM_DIV_SELECT_Msk|CCM_ANALOG_PLL_ARM_POWERDOWN_Msk)) | + CCM_ANALOG_PLL_ARM_ENABLE_Msk | sel) + + for !CCM_ANALOG.PLL_ARM.HasBits(CCM_ANALOG_PLL_ARM_LOCK_Msk) { + } + + // disable bypass + CCM_ANALOG.PLL_ARM.ClearBits(CCM_ANALOG_PLL_ARM_BYPASS_Msk) +} + +func (cfg ClockConfigSysPll) Configure(pfd ...uint32) { + + // bypass PLL first + src := (uint32(cfg.Src) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_Pos) & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_Msk + CCM_ANALOG.PLL_SYS.Set( + (CCM_ANALOG.PLL_SYS.Get() & ^uint32(CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_Msk)) | + CCM_ANALOG_PLL_SYS_BYPASS_Msk | src) + + sel := (uint32(cfg.LoopDivider) << CCM_ANALOG_PLL_SYS_DIV_SELECT_Pos) & CCM_ANALOG_PLL_SYS_DIV_SELECT_Msk + CCM_ANALOG.PLL_SYS.Set( + (CCM_ANALOG.PLL_SYS.Get() & ^uint32(CCM_ANALOG_PLL_SYS_DIV_SELECT_Msk|CCM_ANALOG_PLL_SYS_POWERDOWN_Msk)) | + CCM_ANALOG_PLL_SYS_ENABLE_Msk | sel) + + // initialize the fractional mode + CCM_ANALOG.PLL_SYS_NUM.Set((cfg.Numerator << CCM_ANALOG_PLL_SYS_NUM_A_Pos) & CCM_ANALOG_PLL_SYS_NUM_A_Msk) + CCM_ANALOG.PLL_SYS_DENOM.Set((cfg.Denominator << CCM_ANALOG_PLL_SYS_DENOM_B_Pos) & CCM_ANALOG_PLL_SYS_DENOM_B_Msk) + + // initialize the spread spectrum mode + inc := (uint32(cfg.SsStep) << CCM_ANALOG_PLL_SYS_SS_STEP_Pos) & CCM_ANALOG_PLL_SYS_SS_STEP_Msk + enb := (uint32(cfg.SsEnable) << CCM_ANALOG_PLL_SYS_SS_ENABLE_Pos) & CCM_ANALOG_PLL_SYS_SS_ENABLE_Msk + stp := (uint32(cfg.SsStop) << CCM_ANALOG_PLL_SYS_SS_STOP_Pos) & CCM_ANALOG_PLL_SYS_SS_STOP_Msk + CCM_ANALOG.PLL_SYS_SS.Set(inc | enb | stp) + + for !CCM_ANALOG.PLL_SYS.HasBits(CCM_ANALOG_PLL_SYS_LOCK_Msk) { + } + + // disable bypass + CCM_ANALOG.PLL_SYS.ClearBits(CCM_ANALOG_PLL_SYS_BYPASS_Msk) + + // update PFDs after update + setSysPfd(pfd...) +} + +func (cfg ClockConfigUsbPll) Configure(pfd ...uint32) { + + switch cfg.Instance { + case 1: + + // bypass PLL first + src := (uint32(cfg.Src) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_Pos) & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_Msk + CCM_ANALOG.PLL_USB1.Set( + (CCM_ANALOG.PLL_USB1.Get() & ^uint32(CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_Msk)) | + CCM_ANALOG_PLL_USB1_BYPASS_Msk | src) + + sel := uint32((cfg.LoopDivider << CCM_ANALOG_PLL_USB1_DIV_SELECT_Pos) & CCM_ANALOG_PLL_USB1_DIV_SELECT_Msk) + CCM_ANALOG.PLL_USB1_SET.Set( + (CCM_ANALOG.PLL_USB1.Get() & ^uint32(CCM_ANALOG_PLL_USB1_DIV_SELECT_Msk)) | + CCM_ANALOG_PLL_USB1_ENABLE_Msk | CCM_ANALOG_PLL_USB1_POWER_Msk | + CCM_ANALOG_PLL_USB1_EN_USB_CLKS_Msk | sel) + + for !CCM_ANALOG.PLL_USB1.HasBits(CCM_ANALOG_PLL_USB1_LOCK_Msk) { + } + + // disable bypass + CCM_ANALOG.PLL_USB1_CLR.Set(CCM_ANALOG_PLL_USB1_BYPASS_Msk) + + // update PFDs after update + setUsb1Pfd(pfd...) + + case 2: + // bypass PLL first + src := (uint32(cfg.Src) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_Pos) & CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_Msk + CCM_ANALOG.PLL_USB2.Set( + (CCM_ANALOG.PLL_USB2.Get() & ^uint32(CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_Msk)) | + CCM_ANALOG_PLL_USB2_BYPASS_Msk | src) + + sel := uint32((cfg.LoopDivider << CCM_ANALOG_PLL_USB2_DIV_SELECT_Pos) & CCM_ANALOG_PLL_USB2_DIV_SELECT_Msk) + CCM_ANALOG.PLL_USB2.Set( + (CCM_ANALOG.PLL_USB2.Get() & ^uint32(CCM_ANALOG_PLL_USB2_DIV_SELECT_Msk)) | + CCM_ANALOG_PLL_USB2_ENABLE_Msk | CCM_ANALOG_PLL_USB2_POWER_Msk | + CCM_ANALOG_PLL_USB2_EN_USB_CLKS_Msk | sel) + + for !CCM_ANALOG.PLL_USB2.HasBits(CCM_ANALOG_PLL_USB2_LOCK_Msk) { + } + + // disable bypass + CCM_ANALOG.PLL_USB2.ClearBits(CCM_ANALOG_PLL_USB2_BYPASS_Msk) + + default: + panic("nxp: invalid USB PLL") + } +} diff --git a/src/device/nxp/hardfault.go b/src/device/nxp/hardfault.go new file mode 100644 index 00000000..dbcd0a96 --- /dev/null +++ b/src/device/nxp/hardfault.go @@ -0,0 +1,29 @@ +// Hand created file. DO NOT DELETE. +// Hardfault aliases for definitions that have inconsistent naming (which are +// auto-generated by gen-device-svd.go) among devices in package nxp. + +// +build nxp,!mimxrt1062 + +package nxp + +const ( + HardFault_CFSR_IACCVIOL = SystemControl_CFSR_IACCVIOL + HardFault_CFSR_DACCVIOL = SystemControl_CFSR_DACCVIOL + HardFault_CFSR_MUNSTKERR = SystemControl_CFSR_MUNSTKERR + HardFault_CFSR_MSTKERR = SystemControl_CFSR_MSTKERR + HardFault_CFSR_MLSPERR = SystemControl_CFSR_MLSPERR + HardFault_CFSR_IBUSERR = SystemControl_CFSR_IBUSERR + HardFault_CFSR_PRECISERR = SystemControl_CFSR_PRECISERR + HardFault_CFSR_IMPRECISERR = SystemControl_CFSR_IMPRECISERR + HardFault_CFSR_UNSTKERR = SystemControl_CFSR_UNSTKERR + HardFault_CFSR_STKERR = SystemControl_CFSR_STKERR + HardFault_CFSR_LSPERR = SystemControl_CFSR_LSPERR + HardFault_CFSR_UNDEFINSTR = SystemControl_CFSR_UNDEFINSTR + HardFault_CFSR_INVSTATE = SystemControl_CFSR_INVSTATE + HardFault_CFSR_INVPC = SystemControl_CFSR_INVPC + HardFault_CFSR_NOCP = SystemControl_CFSR_NOCP + HardFault_CFSR_UNALIGNED = SystemControl_CFSR_UNALIGNED + HardFault_CFSR_DIVBYZERO = SystemControl_CFSR_DIVBYZERO + HardFault_CFSR_MMARVALID = SystemControl_CFSR_MMARVALID + HardFault_CFSR_BFARVALID = SystemControl_CFSR_BFARVALID +) diff --git a/src/device/nxp/hardfault_mimxrt1062.go b/src/device/nxp/hardfault_mimxrt1062.go new file mode 100644 index 00000000..c11ff565 --- /dev/null +++ b/src/device/nxp/hardfault_mimxrt1062.go @@ -0,0 +1,29 @@ +// Hand created file. DO NOT DELETE. +// Hardfault aliases for definitions that have inconsistent naming (which are +// auto-generated by gen-device-svd.go) among devices in package nxp. + +// +build nxp,mimxrt1062 + +package nxp + +const ( + HardFault_CFSR_IACCVIOL = SCB_CFSR_IACCVIOL + HardFault_CFSR_DACCVIOL = SCB_CFSR_DACCVIOL + HardFault_CFSR_MUNSTKERR = SCB_CFSR_MUNSTKERR + HardFault_CFSR_MSTKERR = SCB_CFSR_MSTKERR + HardFault_CFSR_MLSPERR = SCB_CFSR_MLSPERR + HardFault_CFSR_IBUSERR = SCB_CFSR_IBUSERR + HardFault_CFSR_PRECISERR = SCB_CFSR_PRECISERR + HardFault_CFSR_IMPRECISERR = SCB_CFSR_IMPRECISERR + HardFault_CFSR_UNSTKERR = SCB_CFSR_UNSTKERR + HardFault_CFSR_STKERR = SCB_CFSR_STKERR + HardFault_CFSR_LSPERR = SCB_CFSR_LSPERR + HardFault_CFSR_UNDEFINSTR = SCB_CFSR_UNDEFINSTR + HardFault_CFSR_INVSTATE = SCB_CFSR_INVSTATE + HardFault_CFSR_INVPC = SCB_CFSR_INVPC + HardFault_CFSR_NOCP = SCB_CFSR_NOCP + HardFault_CFSR_UNALIGNED = SCB_CFSR_UNALIGNED + HardFault_CFSR_DIVBYZERO = SCB_CFSR_DIVBYZERO + HardFault_CFSR_MMARVALID = SCB_CFSR_MMARVALID + HardFault_CFSR_BFARVALID = SCB_CFSR_BFARVALID +) diff --git a/src/device/nxp/mpu_mimxrt1062.go b/src/device/nxp/mpu_mimxrt1062.go new file mode 100644 index 00000000..d5b0f8a7 --- /dev/null +++ b/src/device/nxp/mpu_mimxrt1062.go @@ -0,0 +1,294 @@ +// Hand created file. DO NOT DELETE. +// Type definitions, fields, and constants associated with the MPU peripheral +// of the NXP MIMXRT1062. + +// +build nxp,mimxrt1062 + +package nxp + +import ( + "device/arm" + "runtime/volatile" + "unsafe" +) + +type MPU_Type struct { + TYPE volatile.Register32 // 0x000 (R/ ) - MPU Type Register + CTRL volatile.Register32 // 0x004 (R/W) - MPU Control Register + RNR volatile.Register32 // 0x008 (R/W) - MPU Region RNRber Register + RBAR volatile.Register32 // 0x00C (R/W) - MPU Region Base Address Register + RASR volatile.Register32 // 0x010 (R/W) - MPU Region Attribute and Size Register + RBAR_A1 volatile.Register32 // 0x014 (R/W) - MPU Alias 1 Region Base Address Register + RASR_A1 volatile.Register32 // 0x018 (R/W) - MPU Alias 1 Region Attribute and Size Register + RBAR_A2 volatile.Register32 // 0x01C (R/W) - MPU Alias 2 Region Base Address Register + RASR_A2 volatile.Register32 // 0x020 (R/W) - MPU Alias 2 Region Attribute and Size Register + RBAR_A3 volatile.Register32 // 0x024 (R/W) - MPU Alias 3 Region Base Address Register + RASR_A3 volatile.Register32 // 0x028 (R/W) - MPU Alias 3 Region Attribute and Size Register +} + +var MPU = (*MPU_Type)(unsafe.Pointer(uintptr(0xe000ed90))) + +type ( + RegionSize uint32 + AccessPerms uint32 + Extension uint32 +) + +// MPU Type Register Definitions +const ( + MPU_TYPE_IREGION_Pos = 16 // MPU TYPE: IREGION Position + MPU_TYPE_IREGION_Msk = 0xFF << MPU_TYPE_IREGION_Pos // MPU TYPE: IREGION Mask + MPU_TYPE_DREGION_Pos = 8 // MPU TYPE: DREGION Position + MPU_TYPE_DREGION_Msk = 0xFF << MPU_TYPE_DREGION_Pos // MPU TYPE: DREGION Mask + MPU_TYPE_SEPARATE_Pos = 0 // MPU TYPE: SEPARATE Position + MPU_TYPE_SEPARATE_Msk = 1 // MPU TYPE: SEPARATE Mask +) + +// MPU Control Register Definitions +const ( + MPU_CTRL_PRIVDEFENA_Pos = 2 // MPU CTRL: PRIVDEFENA Position + MPU_CTRL_PRIVDEFENA_Msk = 1 << MPU_CTRL_PRIVDEFENA_Pos // MPU CTRL: PRIVDEFENA Mask + MPU_CTRL_HFNMIENA_Pos = 1 // MPU CTRL: HFNMIENA Position + MPU_CTRL_HFNMIENA_Msk = 1 << MPU_CTRL_HFNMIENA_Pos // MPU CTRL: HFNMIENA Mask + MPU_CTRL_ENABLE_Pos = 0 // MPU CTRL: ENABLE Position + MPU_CTRL_ENABLE_Msk = 1 // MPU CTRL: ENABLE Mask +) + +// MPU Region Number Register Definitions +const ( + MPU_RNR_REGION_Pos = 0 // MPU RNR: REGION Position + MPU_RNR_REGION_Msk = 0xFF // MPU RNR: REGION Mask +) + +// MPU Region Base Address Register Definitions +const ( + MPU_RBAR_ADDR_Pos = 5 // MPU RBAR: ADDR Position + MPU_RBAR_ADDR_Msk = 0x7FFFFFF << MPU_RBAR_ADDR_Pos // MPU RBAR: ADDR Mask + MPU_RBAR_VALID_Pos = 4 // MPU RBAR: VALID Position + MPU_RBAR_VALID_Msk = 1 << MPU_RBAR_VALID_Pos // MPU RBAR: VALID Mask + MPU_RBAR_REGION_Pos = 0 // MPU RBAR: REGION Position + MPU_RBAR_REGION_Msk = 0xF // MPU RBAR: REGION Mask +) + +// MPU Region Attribute and Size Register Definitions +const ( + MPU_RASR_ATTRS_Pos = 16 // MPU RASR: MPU Region Attribute field Position + MPU_RASR_ATTRS_Msk = 0xFFFF << MPU_RASR_ATTRS_Pos // MPU RASR: MPU Region Attribute field Mask + MPU_RASR_XN_Pos = 28 // MPU RASR: ATTRS.XN Position + MPU_RASR_XN_Msk = 1 << MPU_RASR_XN_Pos // MPU RASR: ATTRS.XN Mask + MPU_RASR_AP_Pos = 24 // MPU RASR: ATTRS.AP Position + MPU_RASR_AP_Msk = 0x7 << MPU_RASR_AP_Pos // MPU RASR: ATTRS.AP Mask + MPU_RASR_TEX_Pos = 19 // MPU RASR: ATTRS.TEX Position + MPU_RASR_TEX_Msk = 0x7 << MPU_RASR_TEX_Pos // MPU RASR: ATTRS.TEX Mask + MPU_RASR_S_Pos = 18 // MPU RASR: ATTRS.S Position + MPU_RASR_S_Msk = 1 << MPU_RASR_S_Pos // MPU RASR: ATTRS.S Mask + MPU_RASR_C_Pos = 17 // MPU RASR: ATTRS.C Position + MPU_RASR_C_Msk = 1 << MPU_RASR_C_Pos // MPU RASR: ATTRS.C Mask + MPU_RASR_B_Pos = 16 // MPU RASR: ATTRS.B Position + MPU_RASR_B_Msk = 1 << MPU_RASR_B_Pos // MPU RASR: ATTRS.B Mask + MPU_RASR_SRD_Pos = 8 // MPU RASR: Sub-Region Disable Position + MPU_RASR_SRD_Msk = 0xFF << MPU_RASR_SRD_Pos // MPU RASR: Sub-Region Disable Mask + MPU_RASR_SIZE_Pos = 1 // MPU RASR: Region Size Field Position + MPU_RASR_SIZE_Msk = 0x1F << MPU_RASR_SIZE_Pos // MPU RASR: Region Size Field Mask + MPU_RASR_ENABLE_Pos = 0 // MPU RASR: Region enable bit Position + MPU_RASR_ENABLE_Msk = 1 // MPU RASR: Region enable bit Disable Mask +) + +const ( + SCB_DCISW_WAY_Pos = 30 // SCB DCISW: Way Position + SCB_DCISW_WAY_Msk = 3 << SCB_DCISW_WAY_Pos // SCB DCISW: Way Mask + SCB_DCISW_SET_Pos = 5 // SCB DCISW: Set Position + SCB_DCISW_SET_Msk = 0x1FF << SCB_DCISW_SET_Pos // SCB DCISW: Set Mask +) + +const ( + SCB_DCCISW_WAY_Pos = 30 // SCB DCCISW: Way Position + SCB_DCCISW_WAY_Msk = 3 << SCB_DCCISW_WAY_Pos // SCB DCCISW: Way Mask + SCB_DCCISW_SET_Pos = 5 // SCB DCCISW: Set Position + SCB_DCCISW_SET_Msk = 0x1FF << SCB_DCCISW_SET_Pos // SCB DCCISW: Set Mask +) + +const ( + RGNSZ_32B RegionSize = 0x04 // MPU Region Size 32 Bytes + RGNSZ_64B RegionSize = 0x05 // MPU Region Size 64 Bytes + RGNSZ_128B RegionSize = 0x06 // MPU Region Size 128 Bytes + RGNSZ_256B RegionSize = 0x07 // MPU Region Size 256 Bytes + RGNSZ_512B RegionSize = 0x08 // MPU Region Size 512 Bytes + RGNSZ_1KB RegionSize = 0x09 // MPU Region Size 1 KByte + RGNSZ_2KB RegionSize = 0x0A // MPU Region Size 2 KBytes + RGNSZ_4KB RegionSize = 0x0B // MPU Region Size 4 KBytes + RGNSZ_8KB RegionSize = 0x0C // MPU Region Size 8 KBytes + RGNSZ_16KB RegionSize = 0x0D // MPU Region Size 16 KBytes + RGNSZ_32KB RegionSize = 0x0E // MPU Region Size 32 KBytes + RGNSZ_64KB RegionSize = 0x0F // MPU Region Size 64 KBytes + RGNSZ_128KB RegionSize = 0x10 // MPU Region Size 128 KBytes + RGNSZ_256KB RegionSize = 0x11 // MPU Region Size 256 KBytes + RGNSZ_512KB RegionSize = 0x12 // MPU Region Size 512 KBytes + RGNSZ_1MB RegionSize = 0x13 // MPU Region Size 1 MByte + RGNSZ_2MB RegionSize = 0x14 // MPU Region Size 2 MBytes + RGNSZ_4MB RegionSize = 0x15 // MPU Region Size 4 MBytes + RGNSZ_8MB RegionSize = 0x16 // MPU Region Size 8 MBytes + RGNSZ_16MB RegionSize = 0x17 // MPU Region Size 16 MBytes + RGNSZ_32MB RegionSize = 0x18 // MPU Region Size 32 MBytes + RGNSZ_64MB RegionSize = 0x19 // MPU Region Size 64 MBytes + RGNSZ_128MB RegionSize = 0x1A // MPU Region Size 128 MBytes + RGNSZ_256MB RegionSize = 0x1B // MPU Region Size 256 MBytes + RGNSZ_512MB RegionSize = 0x1C // MPU Region Size 512 MBytes + RGNSZ_1GB RegionSize = 0x1D // MPU Region Size 1 GByte + RGNSZ_2GB RegionSize = 0x1E // MPU Region Size 2 GBytes + RGNSZ_4GB RegionSize = 0x1F // MPU Region Size 4 GBytes +) + +const ( + PERM_NONE AccessPerms = 0 // MPU Access Permission no access + PERM_PRIV AccessPerms = 1 // MPU Access Permission privileged access only + PERM_URO AccessPerms = 2 // MPU Access Permission unprivileged access read-only + PERM_FULL AccessPerms = 3 // MPU Access Permission full access + PERM_PRO AccessPerms = 5 // MPU Access Permission privileged access read-only + PERM_RO AccessPerms = 6 // MPU Access Permission read-only access +) + +const ( + EXTN_NORMAL Extension = 0 + EXTN_DEVICE Extension = 2 +) + +func (mpu *MPU_Type) Enable(enable bool) { + if enable { + mpu.CTRL.Set(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_ENABLE_Msk) + SystemControl.SHCSR.SetBits(SCB_SHCSR_MEMFAULTENA_Msk) + arm.AsmFull(` + dsb 0xF + isb 0xF + `, nil) + EnableDcache(true) + EnableIcache(true) + } else { + EnableIcache(false) + EnableDcache(false) + arm.AsmFull(` + dmb 0xF + `, nil) + SystemControl.SHCSR.ClearBits(SCB_SHCSR_MEMFAULTENA_Msk) + mpu.CTRL.ClearBits(MPU_CTRL_ENABLE_Msk) + } +} + +// MPU Region Base Address Register value +func (mpu *MPU_Type) SetRBAR(region uint32, baseAddress uint32) { + mpu.RBAR.Set((baseAddress & MPU_RBAR_ADDR_Msk) | + (region & MPU_RBAR_REGION_Msk) | MPU_RBAR_VALID_Msk) +} + +// MPU Region Attribute and Size Register value +func (mpu *MPU_Type) SetRASR(size RegionSize, access AccessPerms, ext Extension, exec, share, cache, buffer, disable bool) { + boolBit := func(b bool) uint32 { + if b { + return 1 + } + return 0 + } + attr := ((uint32(ext) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | + ((boolBit(share) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | + ((boolBit(cache) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | + ((boolBit(buffer) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) + mpu.RASR.Set(((boolBit(!exec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | + ((uint32(access) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | + (attr & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)) | + ((boolBit(disable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | + ((uint32(size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | + MPU_RASR_ENABLE_Msk) +} + +func EnableIcache(enable bool) { + if enable != SystemControl.CCR.HasBits(SCB_CCR_IC_Msk) { + if enable { + arm.AsmFull(` + dsb 0xF + isb 0xF + `, nil) + SystemControl.ICIALLU.Set(0) + arm.AsmFull(` + dsb 0xF + isb 0xF + `, nil) + SystemControl.CCR.SetBits(SCB_CCR_IC_Msk) + arm.AsmFull(` + dsb 0xF + isb 0xF + `, nil) + } else { + arm.AsmFull(` + dsb 0xF + isb 0xF + `, nil) + SystemControl.CCR.ClearBits(SCB_CCR_IC_Msk) + SystemControl.ICIALLU.Set(0) + arm.AsmFull(` + dsb 0xF + isb 0xF + `, nil) + } + } +} + +func EnableDcache(enable bool) { + if enable != SystemControl.CCR.HasBits(SCB_CCR_DC_Msk) { + if enable { + SystemControl.CSSELR.Set(0) + arm.AsmFull(` + dsb 0xF + `, nil) + ccsidr := SystemControl.CCSIDR.Get() + sets := (ccsidr & SCB_CCSIDR_NUMSETS_Msk) >> SCB_CCSIDR_NUMSETS_Pos + for sets != 0 { + ways := (ccsidr & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos + for ways != 0 { + SystemControl.DCISW.Set( + ((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)) + ways-- + } + sets-- + } + arm.AsmFull(` + dsb 0xF + `, nil) + SystemControl.CCR.SetBits(SCB_CCR_DC_Msk) + arm.AsmFull(` + dsb 0xF + isb 0xF + `, nil) + } else { + var ( + ccsidr volatile.Register32 + sets volatile.Register32 + ways volatile.Register32 + ) + SystemControl.CSSELR.Set(0) + arm.AsmFull(` + dsb 0xF + `, nil) + SystemControl.CCR.ClearBits(SCB_CCR_DC_Msk) + arm.AsmFull(` + dsb 0xF + `, nil) + ccsidr.Set(SystemControl.CCSIDR.Get()) + sets.Set((ccsidr.Get() & SCB_CCSIDR_NUMSETS_Msk) >> SCB_CCSIDR_NUMSETS_Pos) + for sets.Get() != 0 { + ways.Set((ccsidr.Get() & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) + for ways.Get() != 0 { + SystemControl.DCCISW.Set( + ((sets.Get() << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways.Get() << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)) + ways.Set(ways.Get() - 1) + } + sets.Set(sets.Get() - 1) + } + arm.AsmFull(` + dsb 0xF + isb 0xF + `, nil) + } + } +} diff --git a/src/runtime/runtime_cortexm_hardfault_config.go b/src/runtime/runtime_cortexm_hardfault_config.go deleted file mode 100644 index 3667f221..00000000 --- a/src/runtime/runtime_cortexm_hardfault_config.go +++ /dev/null @@ -1,27 +0,0 @@ -// +build nxp,!mimxrt1062 - -package runtime - -import "device/nxp" - -const ( - CFSR_IACCVIOL = nxp.SystemControl_CFSR_IACCVIOL - CFSR_DACCVIOL = nxp.SystemControl_CFSR_DACCVIOL - CFSR_MUNSTKERR = nxp.SystemControl_CFSR_MUNSTKERR - CFSR_MSTKERR = nxp.SystemControl_CFSR_MSTKERR - CFSR_MLSPERR = nxp.SystemControl_CFSR_MLSPERR - CFSR_IBUSERR = nxp.SystemControl_CFSR_IBUSERR - CFSR_PRECISERR = nxp.SystemControl_CFSR_PRECISERR - CFSR_IMPRECISERR = nxp.SystemControl_CFSR_IMPRECISERR - CFSR_UNSTKERR = nxp.SystemControl_CFSR_UNSTKERR - CFSR_STKERR = nxp.SystemControl_CFSR_STKERR - CFSR_LSPERR = nxp.SystemControl_CFSR_LSPERR - CFSR_UNDEFINSTR = nxp.SystemControl_CFSR_UNDEFINSTR - CFSR_INVSTATE = nxp.SystemControl_CFSR_INVSTATE - CFSR_INVPC = nxp.SystemControl_CFSR_INVPC - CFSR_NOCP = nxp.SystemControl_CFSR_NOCP - CFSR_UNALIGNED = nxp.SystemControl_CFSR_UNALIGNED - CFSR_DIVBYZERO = nxp.SystemControl_CFSR_DIVBYZERO - CFSR_MMARVALID = nxp.SystemControl_CFSR_MMARVALID - CFSR_BFARVALID = nxp.SystemControl_CFSR_BFARVALID -) diff --git a/src/runtime/runtime_cortexm_hardfault_config_mimxrt1062.go b/src/runtime/runtime_cortexm_hardfault_config_mimxrt1062.go deleted file mode 100644 index 230b1cfd..00000000 --- a/src/runtime/runtime_cortexm_hardfault_config_mimxrt1062.go +++ /dev/null @@ -1,27 +0,0 @@ -// +build nxp,mimxrt1062 - -package runtime - -import "device/nxp" - -const ( - CFSR_IACCVIOL = nxp.SCB_CFSR_IACCVIOL - CFSR_DACCVIOL = nxp.SCB_CFSR_DACCVIOL - CFSR_MUNSTKERR = nxp.SCB_CFSR_MUNSTKERR - CFSR_MSTKERR = nxp.SCB_CFSR_MSTKERR - CFSR_MLSPERR = nxp.SCB_CFSR_MLSPERR - CFSR_IBUSERR = nxp.SCB_CFSR_IBUSERR - CFSR_PRECISERR = nxp.SCB_CFSR_PRECISERR - CFSR_IMPRECISERR = nxp.SCB_CFSR_IMPRECISERR - CFSR_UNSTKERR = nxp.SCB_CFSR_UNSTKERR - CFSR_STKERR = nxp.SCB_CFSR_STKERR - CFSR_LSPERR = nxp.SCB_CFSR_LSPERR - CFSR_UNDEFINSTR = nxp.SCB_CFSR_UNDEFINSTR - CFSR_INVSTATE = nxp.SCB_CFSR_INVSTATE - CFSR_INVPC = nxp.SCB_CFSR_INVPC - CFSR_NOCP = nxp.SCB_CFSR_NOCP - CFSR_UNALIGNED = nxp.SCB_CFSR_UNALIGNED - CFSR_DIVBYZERO = nxp.SCB_CFSR_DIVBYZERO - CFSR_MMARVALID = nxp.SCB_CFSR_MMARVALID - CFSR_BFARVALID = nxp.SCB_CFSR_BFARVALID -) diff --git a/src/runtime/runtime_cortexm_hardfault_debug.go b/src/runtime/runtime_cortexm_hardfault_debug.go index 6aca3a26..7260da33 100644 --- a/src/runtime/runtime_cortexm_hardfault_debug.go +++ b/src/runtime/runtime_cortexm_hardfault_debug.go @@ -8,11 +8,15 @@ import ( ) const ( - SystemControl_CFSR_KnownFault = CFSR_IACCVIOL | CFSR_DACCVIOL | - CFSR_MUNSTKERR | CFSR_MSTKERR | CFSR_MLSPERR | CFSR_IBUSERR | - CFSR_PRECISERR | CFSR_IMPRECISERR | CFSR_UNSTKERR | CFSR_STKERR | - CFSR_LSPERR | CFSR_UNDEFINSTR | CFSR_INVSTATE | CFSR_INVPC | CFSR_NOCP | - CFSR_UNALIGNED | CFSR_DIVBYZERO + SystemControl_CFSR_KnownFault = nxp.HardFault_CFSR_IACCVIOL | + nxp.HardFault_CFSR_DACCVIOL | nxp.HardFault_CFSR_MUNSTKERR | + nxp.HardFault_CFSR_MSTKERR | nxp.HardFault_CFSR_MLSPERR | + nxp.HardFault_CFSR_IBUSERR | nxp.HardFault_CFSR_PRECISERR | + nxp.HardFault_CFSR_IMPRECISERR | nxp.HardFault_CFSR_UNSTKERR | + nxp.HardFault_CFSR_STKERR | nxp.HardFault_CFSR_LSPERR | + nxp.HardFault_CFSR_UNDEFINSTR | nxp.HardFault_CFSR_INVSTATE | + nxp.HardFault_CFSR_INVPC | nxp.HardFault_CFSR_NOCP | + nxp.HardFault_CFSR_UNALIGNED | nxp.HardFault_CFSR_DIVBYZERO ) // See runtime_cortexm_hardfault.go @@ -108,7 +112,9 @@ func handleHardFault(sp *interruptStack) { // GetFaultStatus reads the System Control Block Configurable Fault Status // Register and returns it as a FaultStatus. -func GetFaultStatus() FaultStatus { return FaultStatus(nxp.SystemControl.CFSR.Get()) } +func GetFaultStatus() FaultStatus { + return FaultStatus(nxp.SystemControl.CFSR.Get()) +} type FaultStatus uint32 type MemFaultStatus uint32 @@ -120,7 +126,9 @@ func (fs FaultStatus) Bus() BusFaultStatus { return BusFaultStatus(fs) } func (fs FaultStatus) Usage() UsageFaultStatus { return UsageFaultStatus(fs) } // Unknown returns true if the cause of the fault is not know -func (fs FaultStatus) Unknown() bool { return fs&SystemControl_CFSR_KnownFault == 0 } +func (fs FaultStatus) Unknown() bool { + return fs&SystemControl_CFSR_KnownFault == 0 +} // InstructionAccessViolation: the processor attempted an instruction fetch from // a location that does not permit execution @@ -132,7 +140,7 @@ func (fs FaultStatus) Unknown() bool { return fs&SystemControl_CFSR_KnownFault = // the faulting instruction. The processor has not written a fault address to // the MMAR." func (fs MemFaultStatus) InstructionAccessViolation() bool { - return fs&CFSR_IACCVIOL != 0 + return fs&nxp.HardFault_CFSR_IACCVIOL != 0 } // DataAccessViolation: the processor attempted a load or store at a location @@ -141,7 +149,9 @@ func (fs MemFaultStatus) InstructionAccessViolation() bool { // "When this bit is 1, the PC value stacked for the exception return points to // the faulting instruction. The processor has loaded the MMAR with the address // of the attempted access." -func (fs MemFaultStatus) DataAccessViolation() bool { return fs&CFSR_DACCVIOL != 0 } +func (fs MemFaultStatus) DataAccessViolation() bool { + return fs&nxp.HardFault_CFSR_DACCVIOL != 0 +} // WhileUnstackingException: unstack for an exception return has caused one or // more access violations @@ -151,7 +161,7 @@ func (fs MemFaultStatus) DataAccessViolation() bool { return fs&CFSR_DACCVIOL != // the SP from the failing return, and has not performed a new save. The // processor has not written a fault address to the MMAR." func (fs MemFaultStatus) WhileUnstackingException() bool { - return fs&CFSR_MUNSTKERR != 0 + return fs&nxp.HardFault_CFSR_MUNSTKERR != 0 } // WileStackingException: stacking for an exception entry has caused one or more @@ -160,11 +170,15 @@ func (fs MemFaultStatus) WhileUnstackingException() bool { // "When this bit is 1, the SP is still adjusted but the values in the context // area on the stack might be incorrect. The processor has not written a fault // address to the MMAR." -func (fs MemFaultStatus) WileStackingException() bool { return fs&CFSR_MSTKERR != 0 } +func (fs MemFaultStatus) WileStackingException() bool { + return fs&nxp.HardFault_CFSR_MSTKERR != 0 +} // DuringFPLazyStatePres: A MemManage fault occurred during floating-point lazy // state preservation -func (fs MemFaultStatus) DuringFPLazyStatePres() bool { return fs&CFSR_MLSPERR != 0 } +func (fs MemFaultStatus) DuringFPLazyStatePres() bool { + return fs&nxp.HardFault_CFSR_MLSPERR != 0 +} // InstructionBusError: instruction bus error // @@ -174,11 +188,15 @@ func (fs MemFaultStatus) DuringFPLazyStatePres() bool { return fs&CFSR_MLSPERR ! // // When the processor sets this bit is 1, it does not write a fault address to // the BFAR." -func (fs BusFaultStatus) InstructionBusError() bool { return fs&CFSR_IBUSERR != 0 } +func (fs BusFaultStatus) InstructionBusError() bool { + return fs&nxp.HardFault_CFSR_IBUSERR != 0 +} // PreciseDataBusError: a data bus error has occurred, and the PC value stacked // for the exception return points to the instruction that caused the fault -func (fs BusFaultStatus) PreciseDataBusError() bool { return fs&CFSR_PRECISERR != 0 } +func (fs BusFaultStatus) PreciseDataBusError() bool { + return fs&nxp.HardFault_CFSR_PRECISERR != 0 +} // ImpreciseDataBusError: a data bus error has occurred, but the return address // in the stack frame is not related to the instruction that caused the error @@ -193,7 +211,7 @@ func (fs BusFaultStatus) PreciseDataBusError() bool { return fs&CFSR_PRECISERR ! // enters the handler for the imprecise BusFault, the handler detects both // IMPRECISERR set to 1 and one of the precise fault status bits set to 1." func (fs BusFaultStatus) ImpreciseDataBusError() bool { - return fs&CFSR_IMPRECISERR != 0 + return fs&nxp.HardFault_CFSR_IMPRECISERR != 0 } // WhileUnstackingException: unstack for an exception return has caused one or @@ -204,7 +222,7 @@ func (fs BusFaultStatus) ImpreciseDataBusError() bool { // does not adjust the SP from the failing return, does not performed a new // save, and does not write a fault address to the BFAR." func (fs BusFaultStatus) WhileUnstackingException() bool { - return fs&CFSR_UNSTKERR != 0 + return fs&nxp.HardFault_CFSR_UNSTKERR != 0 } // WhileStackingException: stacking for an exception entry has caused one or @@ -213,11 +231,15 @@ func (fs BusFaultStatus) WhileUnstackingException() bool { // "When the processor sets this bit to 1, the SP is still adjusted but the // values in the context area on the stack might be incorrect. The processor // does not write a fault address to the BFAR." -func (fs BusFaultStatus) WhileStackingException() bool { return fs&CFSR_STKERR != 0 } +func (fs BusFaultStatus) WhileStackingException() bool { + return fs&nxp.HardFault_CFSR_STKERR != 0 +} // DuringFPLazyStatePres: A bus fault occurred during floating-point lazy state // preservation -func (fs BusFaultStatus) DuringFPLazyStatePres() bool { return fs&CFSR_LSPERR != 0 } +func (fs BusFaultStatus) DuringFPLazyStatePres() bool { + return fs&nxp.HardFault_CFSR_LSPERR != 0 +} // UndefinedInstruction: the processor has attempted to execute an undefined // instruction @@ -227,7 +249,7 @@ func (fs BusFaultStatus) DuringFPLazyStatePres() bool { return fs&CFSR_LSPERR != // // An undefined instruction is an instruction that the processor cannot decode." func (fs UsageFaultStatus) UndefinedInstruction() bool { - return fs&CFSR_UNDEFINSTR != 0 + return fs&nxp.HardFault_CFSR_UNDEFINSTR != 0 } // IllegalUseOfEPSR: the processor has attempted to execute an instruction that @@ -237,19 +259,23 @@ func (fs UsageFaultStatus) UndefinedInstruction() bool { // points to the instruction that attempted the illegal use of the EPSR. // // This bit is not set to 1 if an undefined instruction uses the EPSR." -func (fs UsageFaultStatus) IllegalUseOfEPSR() bool { return fs&CFSR_INVSTATE != 0 } +func (fs UsageFaultStatus) IllegalUseOfEPSR() bool { + return fs&nxp.HardFault_CFSR_INVSTATE != 0 +} // IllegalExceptionReturn: the processor has attempted an illegal load of // EXC_RETURN to the PC // // "When this bit is set to 1, the PC value stacked for the exception return // points to the instruction that tried to perform the illegal load of the PC." -func (fs UsageFaultStatus) IllegalExceptionReturn() bool { return fs&CFSR_INVPC != 0 } +func (fs UsageFaultStatus) IllegalExceptionReturn() bool { + return fs&nxp.HardFault_CFSR_INVPC != 0 +} // AttemptedToAccessCoprocessor: the processor has attempted to access a // coprocessor func (fs UsageFaultStatus) AttemptedToAccessCoprocessor() bool { - return fs&CFSR_NOCP != 0 + return fs&nxp.HardFault_CFSR_NOCP != 0 } // UnalignedMemoryAccess: the processor has made an unaligned memory access @@ -260,7 +286,7 @@ func (fs UsageFaultStatus) AttemptedToAccessCoprocessor() bool { // Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of // the setting of UNALIGN_TRP." func (fs UsageFaultStatus) UnalignedMemoryAccess() bool { - return fs&CFSR_UNALIGNED != 0 + return fs&nxp.HardFault_CFSR_UNALIGNED != 0 } // DivideByZero: the processor has executed an SDIV or UDIV instruction with a @@ -271,7 +297,9 @@ func (fs UsageFaultStatus) UnalignedMemoryAccess() bool { // // Enable trapping of divide by zero by setting the DIV_0_TRP bit in the CCR to // 1." -func (fs UsageFaultStatus) DivideByZero() bool { return fs&CFSR_DIVBYZERO != 0 } +func (fs UsageFaultStatus) DivideByZero() bool { + return fs&nxp.HardFault_CFSR_DIVBYZERO != 0 +} // Address returns the MemManage Fault Address Register if the fault status // indicates the address is valid. @@ -281,7 +309,7 @@ func (fs UsageFaultStatus) DivideByZero() bool { return fs&CFSR_DIVBYZERO != 0 } // problems on return to a stacked active MemManage fault handler whose MMAR // value has been overwritten." func (fs MemFaultStatus) Address() (uintptr, bool) { - if fs&CFSR_MMARVALID == 0 { + if fs&nxp.HardFault_CFSR_MMARVALID == 0 { return 0, false } else { return uintptr(nxp.SystemControl.MMFAR.Get()), true @@ -300,7 +328,7 @@ func (fs MemFaultStatus) Address() (uintptr, bool) { // returning to a stacked active BusFault handler whose BFAR value has been // overwritten."" func (fs BusFaultStatus) Address() (uintptr, bool) { - if fs&CFSR_BFARVALID == 0 { + if fs&nxp.HardFault_CFSR_BFARVALID == 0 { return 0, false } else { return uintptr(nxp.SystemControl.BFAR.Get()), true diff --git a/src/runtime/runtime_mimxrt1062.go b/src/runtime/runtime_mimxrt1062.go index 147c4aad..1f30a0aa 100644 --- a/src/runtime/runtime_mimxrt1062.go +++ b/src/runtime/runtime_mimxrt1062.go @@ -5,6 +5,7 @@ package runtime import ( "device/arm" "device/nxp" + "math/bits" "unsafe" ) @@ -46,21 +47,37 @@ func main() { abort() } +func getRamSizeConfig(itcmKB, dtcmKB uint32) uint32 { + const minKB, disabled = uint32(4), uint32(0) + if itcmKB < minKB { + itcmKB = disabled + } + if dtcmKB < minKB { + dtcmKB = disabled + } + itcmKB = uint32(bits.Len(uint(itcmKB))) << nxp.IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_Pos + dtcmKB = uint32(bits.Len(uint(dtcmKB))) << nxp.IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_Pos + return (itcmKB & nxp.IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_Msk) | + (dtcmKB & nxp.IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_Msk) +} + func initSystem() { - // configure SRAM capacity + // configure SRAM capacity (512K for both ITCM and DTCM) ramc := uintptr(unsafe.Pointer(&_flexram_cfg)) nxp.IOMUXC_GPR.GPR17.Set(uint32(ramc)) nxp.IOMUXC_GPR.GPR16.Set(0x00200007) - nxp.IOMUXC_GPR.GPR14.Set(0x00AA0000) + nxp.IOMUXC_GPR.GPR14.Set(getRamSizeConfig(512, 512)) - // use bandgap-based bias currents for best performance (Page 1175) [Teensyduino] - nxp.PMU.MISC0_SET.Set(1 << 3) + // from Teensyduino + nxp.PMU.MISC0_SET.Set(nxp.PMU_MISC0_REFTOP_SELFBIASOFF) // install vector table (TODO: initialize interrupt/exception table?) vtor := uintptr(unsafe.Pointer(&_svectors)) nxp.SystemControl.VTOR.Set(uint32(vtor)) + const wdogUpdateKey = 0xD928C520 + // disable watchdog powerdown counter nxp.WDOG1.WMCR.ClearBits(nxp.WDOG_WMCR_PDE_Msk) nxp.WDOG2.WMCR.ClearBits(nxp.WDOG_WMCR_PDE_Msk) @@ -73,10 +90,10 @@ func initSystem() { nxp.WDOG2.WCR.ClearBits(nxp.WDOG_WCR_WDE_Msk) } if nxp.RTWDOG.CS.HasBits(nxp.RTWDOG_CS_CMD32EN_Msk) { - nxp.RTWDOG.CNT.Set(0xD928C520) // 0xD928C520 is the update key + nxp.RTWDOG.CNT.Set(wdogUpdateKey) } else { - nxp.RTWDOG.CNT.Set(0xC520) - nxp.RTWDOG.CNT.Set(0xD928) + nxp.RTWDOG.CNT.Set((wdogUpdateKey >> 0) & 0xFFFF) + nxp.RTWDOG.CNT.Set((wdogUpdateKey >> 16) & 0xFFFF) } nxp.RTWDOG.TOVAL.Set(0xFFFF) nxp.RTWDOG.CS.Set((nxp.RTWDOG.CS.Get() & ^uint32(nxp.RTWDOG_CS_EN_Msk)) | nxp.RTWDOG_CS_UPDATE_Msk) @@ -85,7 +102,9 @@ func initSystem() { func initPeripherals() { // enable FPU - set CP10, CP11 full access - nxp.SystemControl.CPACR.SetBits((3 << (10 * 2)) | (3 << (11 * 2))) + nxp.SystemControl.CPACR.SetBits( + ((nxp.SCB_CPACR_CP10_CP10_3 << nxp.SCB_CPACR_CP10_Pos) & nxp.SCB_CPACR_CP10_Msk) | + ((nxp.SCB_CPACR_CP11_CP11_3 << nxp.SCB_CPACR_CP11_Pos) & nxp.SCB_CPACR_CP11_Msk)) enableTimerClocks() // activate GPT/PIT clock gates initSysTick() // enable SysTick diff --git a/src/runtime/runtime_mimxrt1062_clock.go b/src/runtime/runtime_mimxrt1062_clock.go index 949870e8..92a6fe05 100644 --- a/src/runtime/runtime_mimxrt1062_clock.go +++ b/src/runtime/runtime_mimxrt1062_clock.go @@ -4,8 +4,6 @@ package runtime import ( "device/nxp" - "runtime/volatile" - "unsafe" ) // Core, bus, and peripheral clock frequencies (Hz) @@ -37,6 +35,36 @@ const ( USDHC2_FREQ = 198000000 // 198 MHz ) +var ( + ArmPllConfig = nxp.ClockConfigArmPll{ + LoopDivider: 100, // PLL loop divider, Fout = Fin * 50 + Src: 0, // Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N + } + SysPllConfig = nxp.ClockConfigSysPll{ + LoopDivider: 1, // PLL loop divider, Fout = Fin * ( 20 + LoopDivider*2 + Numerator / Denominator ) + Numerator: 0, // 30 bit Numerator of fractional loop divider + Denominator: 1, // 30 bit Denominator of fractional loop divider + Src: 0, // Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N + } + Usb1PllConfig = nxp.ClockConfigUsbPll{ + Instance: 1, // USB PLL Instance + LoopDivider: 0, // PLL loop divider, Fout = Fin * 20 + Src: 0, // Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N + } + Usb2PllConfig = nxp.ClockConfigUsbPll{ + Instance: 2, // USB PLL Instance + LoopDivider: 0, // PLL loop divider, Fout = Fin * 20 + Src: 0, // Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N + } + VideoPllConfig = nxp.ClockConfigVideoPll{ + LoopDivider: 31, // PLL loop divider, Fout = Fin * ( LoopDivider + Numerator / Denominator ) + PostDivider: 8, // Divider after PLL + Numerator: 0, // 30 bit Numerator of fractional loop divider, Fout = Fin * ( LoopDivider + Numerator / Denominator ) + Denominator: 1, // 30 bit Denominator of fractional loop divider, Fout = Fin * ( LoopDivider + Numerator / Denominator ) + Src: 0, // Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N + } +) + // Note about OSC_FREQ from Teensyduino (cores/teensy4/startup.c): // // | ARM SysTick is used for most Ardiuno timing functions, delay(), millis(), @@ -50,13 +78,14 @@ const ( // initClocks configures the core, buses, and all peripherals' clock source mux // and dividers for runtime. The clock gates for individual peripherals are all -// disabled prior to configuration and must be enabled afterwards using function -// `enableClocks()`. +// disabled prior to configuration and must be enabled afterwards using one of +// these `enable*Clocks()` functions or the respective peripheral clocks' +// `Enable()` method from the "device/nxp" package. func initClocks() { // disable low-power mode so that __WFI doesn't lock up at runtime. // see: Using the MIMXRT1060/4-EVK with MCUXpresso IDE v10.3.x (v1.0.2, // 2019MAR01), chapter 14 - modeClkRun.set() + nxp.ModeClkRun.Set() // enable 1MHz clock output nxp.XTALOSC24M.OSC_CONFIG2.SetBits(nxp.XTALOSC24M_OSC_CONFIG2_ENABLE_1M_Msk) @@ -83,8 +112,8 @@ func initClocks() { ((127 << nxp.CCM_CCR_OSCNT_Pos) & nxp.CCM_CCR_OSCNT_Msk)) // set PERIPH2_CLK and PERIPH to provide stable clock before PLLs initialed - muxIpPeriphClk2.mux(1) // PERIPH_CLK2 select OSC24M - muxIpPeriph.mux(1) // PERIPH select PERIPH_CLK2 + nxp.MuxIpPeriphClk2.Mux(1) // PERIPH_CLK2 select OSC24M + nxp.MuxIpPeriph.Mux(1) // PERIPH select PERIPH_CLK2 // set VDD_SOC to 1.275V, necessary to config AHB to 600 MHz nxp.DCDC.REG3.Set((nxp.DCDC.REG3.Get() & ^uint32(nxp.DCDC_REG3_TRG_Msk)) | @@ -95,164 +124,164 @@ func initClocks() { } // -------------------------------------------------------------------- AHB -- - divIpAhb.div(0) // divide AHB_PODF (DIV1) + nxp.DivIpAhb.Div(0) // divide AHB_PODF (DIV1) // -------------------------------------------------------------------- ADC -- - clkIpAdc1.enable(false) // disable ADC clock gates - clkIpAdc2.enable(false) // ~ + nxp.ClockIpAdc1.Enable(false) // disable ADC clock gates + nxp.ClockIpAdc2.Enable(false) // ~ // ------------------------------------------------------------------- XBAR -- - clkIpXbar1.enable(false) // disable XBAR clock gates - clkIpXbar2.enable(false) // ~ - clkIpXbar3.enable(false) // ~ + nxp.ClockIpXbar1.Enable(false) // disable XBAR clock gates + nxp.ClockIpXbar2.Enable(false) // ~ + nxp.ClockIpXbar3.Enable(false) // ~ // ---------------------------------------------------------------- ARM/IPG -- - divIpIpg.div(3) // divide IPG_PODF (DIV4) - divIpArm.div(1) // divide ARM_PODF (DIV2) - divIpPeriphClk2.div(0) // divide PERIPH_CLK2_PODF (DIV1) + nxp.DivIpIpg.Div(3) // divide IPG_PODF (DIV4) + nxp.DivIpArm.Div(1) // divide ARM_PODF (DIV2) + nxp.DivIpPeriphClk2.Div(0) // divide PERIPH_CLK2_PODF (DIV1) // ---------------------------------------------------------------- GPT/PIT -- - clkIpGpt1.enable(false) // disable GPT/PIT clock gates - clkIpGpt1S.enable(false) // ~ - clkIpGpt2.enable(false) // ~ - clkIpGpt2S.enable(false) // ~ - clkIpPit.enable(false) // ~ + nxp.ClockIpGpt1.Enable(false) // disable GPT/PIT clock gates + nxp.ClockIpGpt1S.Enable(false) // ~ + nxp.ClockIpGpt2.Enable(false) // ~ + nxp.ClockIpGpt2S.Enable(false) // ~ + nxp.ClockIpPit.Enable(false) // ~ // -------------------------------------------------------------------- PER -- - divIpPerclk.div(0) // divide PERCLK_PODF (DIV1) + nxp.DivIpPerclk.Div(0) // divide PERCLK_PODF (DIV1) // ------------------------------------------------------------------ USDHC -- - clkIpUsdhc1.enable(false) // disable USDHC1 clock gate - divIpUsdhc1.div(1) // divide USDHC1_PODF (DIV2) - muxIpUsdhc1.mux(1) // USDHC1 select PLL2_PFD0 - clkIpUsdhc2.enable(false) // disable USDHC2 clock gate - divIpUsdhc2.div(1) // divide USDHC2_PODF (DIV2) - muxIpUsdhc2.mux(1) // USDHC2 select PLL2_PFD0 + nxp.ClockIpUsdhc1.Enable(false) // disable USDHC1 clock gate + nxp.DivIpUsdhc1.Div(1) // divide USDHC1_PODF (DIV2) + nxp.MuxIpUsdhc1.Mux(1) // USDHC1 select PLL2_PFD0 + nxp.ClockIpUsdhc2.Enable(false) // disable USDHC2 clock gate + nxp.DivIpUsdhc2.Div(1) // divide USDHC2_PODF (DIV2) + nxp.MuxIpUsdhc2.Mux(1) // USDHC2 select PLL2_PFD0 // ------------------------------------------------------------------- SEMC -- - clkIpSemc.enable(false) // disable SEMC clock gate - divIpSemc.div(1) // divide SEMC_PODF (DIV2) - muxIpSemcAlt.mux(0) // SEMC_ALT select PLL2_PFD2 - muxIpSemc.mux(1) // SEMC select SEMC_ALT + nxp.ClockIpSemc.Enable(false) // disable SEMC clock gate + nxp.DivIpSemc.Div(1) // divide SEMC_PODF (DIV2) + nxp.MuxIpSemcAlt.Mux(0) // SEMC_ALT select PLL2_PFD2 + nxp.MuxIpSemc.Mux(1) // SEMC select SEMC_ALT // ---------------------------------------------------------------- FLEXSPI -- if false { // TODO: external flash is on this bus, configured via DCD block - clkIpFlexSpi.enable(false) // disable FLEXSPI clock gate - divIpFlexSpi.div(0) // divide FLEXSPI_PODF (DIV1) - muxIpFlexSpi.mux(2) // FLEXSPI select PLL2_PFD2 + nxp.ClockIpFlexSpi.Enable(false) // disable FLEXSPI clock gate + nxp.DivIpFlexSpi.Div(0) // divide FLEXSPI_PODF (DIV1) + nxp.MuxIpFlexSpi.Mux(2) // FLEXSPI select PLL2_PFD2 } - clkIpFlexSpi2.enable(false) // disable FLEXSPI2 clock gate - divIpFlexSpi2.div(0) // divide FLEXSPI2_PODF (DIV1) - muxIpFlexSpi2.mux(0) // FLEXSPI2 select PLL2_PFD2 + nxp.ClockIpFlexSpi2.Enable(false) // disable FLEXSPI2 clock gate + nxp.DivIpFlexSpi2.Div(0) // divide FLEXSPI2_PODF (DIV1) + nxp.MuxIpFlexSpi2.Mux(0) // FLEXSPI2 select PLL2_PFD2 // -------------------------------------------------------------------- CSI -- - clkIpCsi.enable(false) // disable CSI clock gate - divIpCsi.div(1) // divide CSI_PODF (DIV2) - muxIpCsi.mux(0) // CSI select OSC24M + nxp.ClockIpCsi.Enable(false) // disable CSI clock gate + nxp.DivIpCsi.Div(1) // divide CSI_PODF (DIV2) + nxp.MuxIpCsi.Mux(0) // CSI select OSC24M // ------------------------------------------------------------------ LPSPI -- - clkIpLpspi1.enable(false) // disable LPSPI clock gate - clkIpLpspi2.enable(false) // ~ - clkIpLpspi3.enable(false) // ~ - clkIpLpspi4.enable(false) // ~ - divIpLpspi.div(3) // divide LPSPI_PODF (DIV4) - muxIpLpspi.mux(2) // LPSPI select PLL2 + nxp.ClockIpLpspi1.Enable(false) // disable LPSPI clock gate + nxp.ClockIpLpspi2.Enable(false) // ~ + nxp.ClockIpLpspi3.Enable(false) // ~ + nxp.ClockIpLpspi4.Enable(false) // ~ + nxp.DivIpLpspi.Div(3) // divide LPSPI_PODF (DIV4) + nxp.MuxIpLpspi.Mux(2) // LPSPI select PLL2 // ------------------------------------------------------------------ TRACE -- - clkIpTrace.enable(false) // disable TRACE clock gate - divIpTrace.div(3) // divide TRACE_PODF (DIV4) - muxIpTrace.mux(0) // TRACE select PLL2_MAIN + nxp.ClockIpTrace.Enable(false) // disable TRACE clock gate + nxp.DivIpTrace.Div(3) // divide TRACE_PODF (DIV4) + nxp.MuxIpTrace.Mux(0) // TRACE select PLL2_MAIN // -------------------------------------------------------------------- SAI -- - clkIpSai1.enable(false) // disable SAI1 clock gate - divIpSai1Pre.div(3) // divide SAI1_CLK_PRED (DIV4) - divIpSai1.div(1) // divide SAI1_CLK_PODF (DIV2) - muxIpSai1.mux(0) // SAI1 select PLL3_PFD2 - clkIpSai2.enable(false) // disable SAI2 clock gate - divIpSai2Pre.div(3) // divide SAI2_CLK_PRED (DIV4) - divIpSai2.div(1) // divide SAI2_CLK_PODF (DIV2) - muxIpSai2.mux(0) // SAI2 select PLL3_PFD2 - clkIpSai3.enable(false) // disable SAI3 clock gate - divIpSai3Pre.div(3) // divide SAI3_CLK_PRED (DIV4) - divIpSai3.div(1) // divide SAI3_CLK_PODF (DIV2) - muxIpSai3.mux(0) // SAI3 select PLL3_PFD2 + nxp.ClockIpSai1.Enable(false) // disable SAI1 clock gate + nxp.DivIpSai1Pre.Div(3) // divide SAI1_CLK_PRED (DIV4) + nxp.DivIpSai1.Div(1) // divide SAI1_CLK_PODF (DIV2) + nxp.MuxIpSai1.Mux(0) // SAI1 select PLL3_PFD2 + nxp.ClockIpSai2.Enable(false) // disable SAI2 clock gate + nxp.DivIpSai2Pre.Div(3) // divide SAI2_CLK_PRED (DIV4) + nxp.DivIpSai2.Div(1) // divide SAI2_CLK_PODF (DIV2) + nxp.MuxIpSai2.Mux(0) // SAI2 select PLL3_PFD2 + nxp.ClockIpSai3.Enable(false) // disable SAI3 clock gate + nxp.DivIpSai3Pre.Div(3) // divide SAI3_CLK_PRED (DIV4) + nxp.DivIpSai3.Div(1) // divide SAI3_CLK_PODF (DIV2) + nxp.MuxIpSai3.Mux(0) // SAI3 select PLL3_PFD2 // ------------------------------------------------------------------ LPI2C -- - clkIpLpi2c1.enable(false) // disable LPI2C clock gate - clkIpLpi2c2.enable(false) // ~ - clkIpLpi2c3.enable(false) // ~ - divIpLpi2c.div(0) // divide LPI2C_CLK_PODF (DIV1) - muxIpLpi2c.mux(0) // LPI2C select PLL3_SW_60M + nxp.ClockIpLpi2c1.Enable(false) // disable LPI2C clock gate + nxp.ClockIpLpi2c2.Enable(false) // ~ + nxp.ClockIpLpi2c3.Enable(false) // ~ + nxp.DivIpLpi2c.Div(0) // divide LPI2C_CLK_PODF (DIV1) + nxp.MuxIpLpi2c.Mux(0) // LPI2C select PLL3_SW_60M // -------------------------------------------------------------------- CAN -- - clkIpCan1.enable(false) // disable CAN clock gate - clkIpCan2.enable(false) // ~ - clkIpCan3.enable(false) // ~ - clkIpCan1S.enable(false) // ~ - clkIpCan2S.enable(false) // ~ - clkIpCan3S.enable(false) // ~ - divIpCan.div(1) // divide CAN_CLK_PODF (DIV2) - muxIpCan.mux(2) // CAN select PLL3_SW_80M + nxp.ClockIpCan1.Enable(false) // disable CAN clock gate + nxp.ClockIpCan2.Enable(false) // ~ + nxp.ClockIpCan3.Enable(false) // ~ + nxp.ClockIpCan1S.Enable(false) // ~ + nxp.ClockIpCan2S.Enable(false) // ~ + nxp.ClockIpCan3S.Enable(false) // ~ + nxp.DivIpCan.Div(1) // divide CAN_CLK_PODF (DIV2) + nxp.MuxIpCan.Mux(2) // CAN select PLL3_SW_80M // ------------------------------------------------------------------- UART -- - clkIpLpuart1.enable(false) // disable UART clock gate - clkIpLpuart2.enable(false) // ~ - clkIpLpuart3.enable(false) // ~ - clkIpLpuart4.enable(false) // ~ - clkIpLpuart5.enable(false) // ~ - clkIpLpuart6.enable(false) // ~ - clkIpLpuart7.enable(false) // ~ - clkIpLpuart8.enable(false) // ~ - divIpUart.div(0) // divide UART_CLK_PODF (DIV1) - muxIpUart.mux(1) // UART select OSC + nxp.ClockIpLpuart1.Enable(false) // disable UART clock gate + nxp.ClockIpLpuart2.Enable(false) // ~ + nxp.ClockIpLpuart3.Enable(false) // ~ + nxp.ClockIpLpuart4.Enable(false) // ~ + nxp.ClockIpLpuart5.Enable(false) // ~ + nxp.ClockIpLpuart6.Enable(false) // ~ + nxp.ClockIpLpuart7.Enable(false) // ~ + nxp.ClockIpLpuart8.Enable(false) // ~ + nxp.DivIpUart.Div(0) // divide UART_CLK_PODF (DIV1) + nxp.MuxIpUart.Mux(1) // UART select OSC // -------------------------------------------------------------------- LCD -- - clkIpLcdPixel.enable(false) // disable LCDIF clock gate - divIpLcdifPre.div(1) // divide LCDIF_PRED (DIV2) - divIpLcdif.div(3) // divide LCDIF_CLK_PODF (DIV4) - muxIpLcdifPre.mux(5) // LCDIF_PRE select PLL3_PFD1 + nxp.ClockIpLcdPixel.Enable(false) // disable LCDIF clock gate + nxp.DivIpLcdifPre.Div(1) // divide LCDIF_PRED (DIV2) + nxp.DivIpLcdif.Div(3) // divide LCDIF_CLK_PODF (DIV4) + nxp.MuxIpLcdifPre.Mux(5) // LCDIF_PRE select PLL3_PFD1 // ------------------------------------------------------------------ SPDIF -- - clkIpSpdif.enable(false) // disable SPDIF clock gate - divIpSpdif0Pre.div(1) // divide SPDIF0_CLK_PRED (DIV2) - divIpSpdif0.div(7) // divide SPDIF0_CLK_PODF (DIV8) - muxIpSpdif.mux(3) // SPDIF select PLL3_SW + nxp.ClockIpSpdif.Enable(false) // disable SPDIF clock gate + nxp.DivIpSpdif0Pre.Div(1) // divide SPDIF0_CLK_PRED (DIV2) + nxp.DivIpSpdif0.Div(7) // divide SPDIF0_CLK_PODF (DIV8) + nxp.MuxIpSpdif.Mux(3) // SPDIF select PLL3_SW // ----------------------------------------------------------------- FLEXIO -- - clkIpFlexio1.enable(false) // disable FLEXIO1 clock gate - divIpFlexio1Pre.div(1) // divide FLEXIO1_CLK_PRED (DIV2) - divIpFlexio1.div(7) // divide FLEXIO1_CLK_PODF (DIV8) - muxIpFlexio1.mux(3) // FLEXIO1 select PLL3_SW - clkIpFlexio2.enable(false) // enable FLEXIO2 clock gate - divIpFlexio2Pre.div(1) // divide FLEXIO2_CLK_PRED (DIV2) - divIpFlexio2.div(7) // divide FLEXIO2_CLK_PODF (DIV8) - muxIpFlexio2.mux(3) // FLEXIO2 select PLL3_SW + nxp.ClockIpFlexio1.Enable(false) // disable FLEXIO1 clock gate + nxp.DivIpFlexio1Pre.Div(1) // divide FLEXIO1_CLK_PRED (DIV2) + nxp.DivIpFlexio1.Div(7) // divide FLEXIO1_CLK_PODF (DIV8) + nxp.MuxIpFlexio1.Mux(3) // FLEXIO1 select PLL3_SW + nxp.ClockIpFlexio2.Enable(false) // enable FLEXIO2 clock gate + nxp.DivIpFlexio2Pre.Div(1) // divide FLEXIO2_CLK_PRED (DIV2) + nxp.DivIpFlexio2.Div(7) // divide FLEXIO2_CLK_PODF (DIV8) + nxp.MuxIpFlexio2.Mux(3) // FLEXIO2 select PLL3_SW // ---------------------------------------------------------------- PLL/PFD -- - muxIpPll3Sw.mux(0) // PLL3_SW select PLL3_MAIN + nxp.MuxIpPll3Sw.Mux(0) // PLL3_SW select PLL3_MAIN - armPllConfig.configure() // init ARM PLL + ArmPllConfig.Configure() // init ARM PLL // SYS PLL (PLL2) @ 528 MHz // PFD0 = 396 MHz -> USDHC1/USDHC2(DIV2)=198 MHz // PFD1 = 594 MHz -> (currently unused) // PFD2 = 327.72 MHz -> SEMC(DIV2)=163.86 MHz, FlexSPI/FlexSPI2=327.72 MHz // PFD3 = 454.73 MHz -> (currently unused) - sysPllConfig.configure(24, 16, 29, 16) // init SYS PLL and PFDs + SysPllConfig.Configure(24, 16, 29, 16) // init SYS PLL and PFDs // USB1 PLL (PLL3) @ 480 MHz // PFD0 -> (currently unused) // PFD1 -> (currently unused) // PFD2 -> (currently unused) // PFD3 -> (currently unused) - usb1PllConfig.configure() // init USB1 PLL and PFDs - usb2PllConfig.configure() // init USB2 PLL + Usb1PllConfig.Configure() // init USB1 PLL and PFDs + Usb2PllConfig.Configure() // init USB2 PLL // --------------------------------------------------------------- ARM CORE -- - muxIpPrePeriph.mux(3) // PRE_PERIPH select ARM_PLL - muxIpPeriph.mux(0) // PERIPH select PRE_PERIPH - muxIpPeriphClk2.mux(1) // PERIPH_CLK2 select OSC - muxIpPerclk.mux(1) // PERCLK select OSC + nxp.MuxIpPrePeriph.Mux(3) // PRE_PERIPH select ARM_PLL + nxp.MuxIpPeriph.Mux(0) // PERIPH select PRE_PERIPH + nxp.MuxIpPeriphClk2.Mux(1) // PERIPH_CLK2 select OSC + nxp.MuxIpPerclk.Mux(1) // PERCLK select OSC // ------------------------------------------------------------------- LVDS -- // set LVDS1 clock source @@ -278,965 +307,94 @@ func initClocks() { nxp.CCM.CCOSR.SetBits(nxp.CCM_CCOSR_CLKO2_EN_Msk) // enable CLK_OUT2 // ----------------------------------------------------------------- IOMUXC -- - clkIpIomuxcGpr.enable(false) // disable IOMUXC_GPR clock gate - clkIpIomuxc.enable(false) // disable IOMUXC clock gate + nxp.ClockIpIomuxcGpr.Enable(false) // disable IOMUXC_GPR clock gate + nxp.ClockIpIomuxc.Enable(false) // disable IOMUXC clock gate // set GPT1 High frequency reference clock source nxp.IOMUXC_GPR.GPR5.ClearBits(nxp.IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_Msk) // set GPT2 High frequency reference clock source nxp.IOMUXC_GPR.GPR5.ClearBits(nxp.IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_Msk) // ------------------------------------------------------------------- GPIO -- - clkIpGpio1.enable(false) // disable GPIO clock gates - clkIpGpio2.enable(false) // ~ - clkIpGpio3.enable(false) // ~ - clkIpGpio4.enable(false) // ~ + nxp.ClockIpGpio1.Enable(false) // disable GPIO clock gates + nxp.ClockIpGpio2.Enable(false) // ~ + nxp.ClockIpGpio3.Enable(false) // ~ + nxp.ClockIpGpio4.Enable(false) // ~ } func enableTimerClocks() { // ---------------------------------------------------------------- GPT/PIT -- - clkIpGpt1.enable(true) // enable GPT/PIT clock gates - clkIpGpt1S.enable(true) // ~ - clkIpGpt2.enable(true) // ~ - clkIpGpt2S.enable(true) // ~ - clkIpPit.enable(true) // ~ + nxp.ClockIpGpt1.Enable(true) // enable GPT/PIT clock gates + nxp.ClockIpGpt1S.Enable(true) // ~ + nxp.ClockIpGpt2.Enable(true) // ~ + nxp.ClockIpGpt2S.Enable(true) // ~ + nxp.ClockIpPit.Enable(true) // ~ } func enablePinClocks() { // ----------------------------------------------------------------- IOMUXC -- - clkIpIomuxcGpr.enable(true) // enable IOMUXC clock gates - clkIpIomuxc.enable(true) // ~ + nxp.ClockIpIomuxcGpr.Enable(true) // enable IOMUXC clock gates + nxp.ClockIpIomuxc.Enable(true) // ~ // ------------------------------------------------------------------- GPIO -- - clkIpGpio1.enable(true) // enable GPIO clock gates - clkIpGpio2.enable(true) // ~ - clkIpGpio3.enable(true) // ~ - clkIpGpio4.enable(true) // ~ + nxp.ClockIpGpio1.Enable(true) // enable GPIO clock gates + nxp.ClockIpGpio2.Enable(true) // ~ + nxp.ClockIpGpio3.Enable(true) // ~ + nxp.ClockIpGpio4.Enable(true) // ~ } -// enableClocks enables the clock gates for peripherals used by this runtime. func enablePeripheralClocks() { // -------------------------------------------------------------------- ADC -- - clkIpAdc1.enable(true) // enable ADC clock gates - clkIpAdc2.enable(true) // ~ + nxp.ClockIpAdc1.Enable(true) // enable ADC clock gates + nxp.ClockIpAdc2.Enable(true) // ~ // ------------------------------------------------------------------- XBAR -- - clkIpXbar1.enable(true) // enable XBAR clock gates - clkIpXbar2.enable(true) // ~ - clkIpXbar3.enable(true) // ~ + nxp.ClockIpXbar1.Enable(true) // enable XBAR clock gates + nxp.ClockIpXbar2.Enable(true) // ~ + nxp.ClockIpXbar3.Enable(true) // ~ // ------------------------------------------------------------------ USDHC -- - clkIpUsdhc1.enable(true) // enable USDHC clock gates - clkIpUsdhc2.enable(true) // ~ + nxp.ClockIpUsdhc1.Enable(true) // enable USDHC clock gates + nxp.ClockIpUsdhc2.Enable(true) // ~ // ------------------------------------------------------------------- SEMC -- - clkIpSemc.enable(true) // enable SEMC clock gate + nxp.ClockIpSemc.Enable(true) // enable SEMC clock gate // ---------------------------------------------------------------- FLEXSPI -- - clkIpFlexSpi2.enable(true) // enable FLEXSPI2 clock gate + nxp.ClockIpFlexSpi2.Enable(true) // enable FLEXSPI2 clock gate // ------------------------------------------------------------------ LPSPI -- - clkIpLpspi1.enable(true) // enable LPSPI clock gate - clkIpLpspi2.enable(true) // ~ - clkIpLpspi3.enable(true) // ~ - clkIpLpspi4.enable(true) // ~ + nxp.ClockIpLpspi1.Enable(true) // enable LPSPI clock gate + nxp.ClockIpLpspi2.Enable(true) // ~ + nxp.ClockIpLpspi3.Enable(true) // ~ + nxp.ClockIpLpspi4.Enable(true) // ~ // ------------------------------------------------------------------ LPI2C -- - clkIpLpi2c1.enable(true) // enable LPI2C clock gate - clkIpLpi2c2.enable(true) // ~ - clkIpLpi2c3.enable(true) // ~ + nxp.ClockIpLpi2c1.Enable(true) // enable LPI2C clock gate + nxp.ClockIpLpi2c2.Enable(true) // ~ + nxp.ClockIpLpi2c3.Enable(true) // ~ // -------------------------------------------------------------------- CAN -- - clkIpCan1.enable(true) // enable CAN clock gate - clkIpCan2.enable(true) // ~ - clkIpCan3.enable(true) // ~ - clkIpCan1S.enable(true) // ~ - clkIpCan2S.enable(true) // ~ - clkIpCan3S.enable(true) // ~ + nxp.ClockIpCan1.Enable(true) // enable CAN clock gate + nxp.ClockIpCan2.Enable(true) // ~ + nxp.ClockIpCan3.Enable(true) // ~ + nxp.ClockIpCan1S.Enable(true) // ~ + nxp.ClockIpCan2S.Enable(true) // ~ + nxp.ClockIpCan3S.Enable(true) // ~ // ------------------------------------------------------------------- UART -- - clkIpLpuart1.enable(true) // enable UART clock gate - clkIpLpuart2.enable(true) // ~ - clkIpLpuart3.enable(true) // ~ - clkIpLpuart4.enable(true) // ~ - clkIpLpuart5.enable(true) // ~ - clkIpLpuart6.enable(true) // ~ - clkIpLpuart7.enable(true) // ~ - clkIpLpuart8.enable(true) // ~ + nxp.ClockIpLpuart1.Enable(true) // enable UART clock gate + nxp.ClockIpLpuart2.Enable(true) // ~ + nxp.ClockIpLpuart3.Enable(true) // ~ + nxp.ClockIpLpuart4.Enable(true) // ~ + nxp.ClockIpLpuart5.Enable(true) // ~ + nxp.ClockIpLpuart6.Enable(true) // ~ + nxp.ClockIpLpuart7.Enable(true) // ~ + nxp.ClockIpLpuart8.Enable(true) // ~ // ----------------------------------------------------------------- FLEXIO -- - clkIpFlexio1.enable(true) // enable FLEXIO clock gates - clkIpFlexio2.enable(true) // ~ + nxp.ClockIpFlexio1.Enable(true) // enable FLEXIO clock gates + nxp.ClockIpFlexio2.Enable(true) // ~ } - -type clock uint32 - -// Named oscillators -const ( - clkCpu clock = 0x0 // CPU clock - clkAhb clock = 0x1 // AHB clock - clkSemc clock = 0x2 // SEMC clock - clkIpg clock = 0x3 // IPG clock - clkPer clock = 0x4 // PER clock - clkOsc clock = 0x5 // OSC clock selected by PMU_LOWPWR_CTRL[OSC_SEL] - clkRtc clock = 0x6 // RTC clock (RTCCLK) - clkArmPll clock = 0x7 // ARMPLLCLK - clkUsb1Pll clock = 0x8 // USB1PLLCLK - clkUsb1PllPfd0 clock = 0x9 // USB1PLLPDF0CLK - clkUsb1PllPfd1 clock = 0xA // USB1PLLPFD1CLK - clkUsb1PllPfd2 clock = 0xB // USB1PLLPFD2CLK - clkUsb1PllPfd3 clock = 0xC // USB1PLLPFD3CLK - clkUsb2Pll clock = 0xD // USB2PLLCLK - clkSysPll clock = 0xE // SYSPLLCLK - clkSysPllPfd0 clock = 0xF // SYSPLLPDF0CLK - clkSysPllPfd1 clock = 0x10 // SYSPLLPFD1CLK - clkSysPllPfd2 clock = 0x11 // SYSPLLPFD2CLK - clkSysPllPfd3 clock = 0x12 // SYSPLLPFD3CLK - clkEnetPll0 clock = 0x13 // Enet PLLCLK ref_enetpll0 - clkEnetPll1 clock = 0x14 // Enet PLLCLK ref_enetpll1 - clkEnetPll2 clock = 0x15 // Enet PLLCLK ref_enetpll2 - clkAudioPll clock = 0x16 // Audio PLLCLK - clkVideoPll clock = 0x17 // Video PLLCLK -) - -// Named clocks of integrated peripherals -const ( - clkIpAipsTz1 clock = (0 << 8) | nxp.CCM_CCGR0_CG0_Pos // CCGR0, CG0 - clkIpAipsTz2 clock = (0 << 8) | nxp.CCM_CCGR0_CG1_Pos // CCGR0, CG1 - clkIpMqs clock = (0 << 8) | nxp.CCM_CCGR0_CG2_Pos // CCGR0, CG2 - clkIpFlexSpiExsc clock = (0 << 8) | nxp.CCM_CCGR0_CG3_Pos // CCGR0, CG3 - clkIpSimMMain clock = (0 << 8) | nxp.CCM_CCGR0_CG4_Pos // CCGR0, CG4 - clkIpDcp clock = (0 << 8) | nxp.CCM_CCGR0_CG5_Pos // CCGR0, CG5 - clkIpLpuart3 clock = (0 << 8) | nxp.CCM_CCGR0_CG6_Pos // CCGR0, CG6 - clkIpCan1 clock = (0 << 8) | nxp.CCM_CCGR0_CG7_Pos // CCGR0, CG7 - clkIpCan1S clock = (0 << 8) | nxp.CCM_CCGR0_CG8_Pos // CCGR0, CG8 - clkIpCan2 clock = (0 << 8) | nxp.CCM_CCGR0_CG9_Pos // CCGR0, CG9 - clkIpCan2S clock = (0 << 8) | nxp.CCM_CCGR0_CG10_Pos // CCGR0, CG10 - clkIpTrace clock = (0 << 8) | nxp.CCM_CCGR0_CG11_Pos // CCGR0, CG11 - clkIpGpt2 clock = (0 << 8) | nxp.CCM_CCGR0_CG12_Pos // CCGR0, CG12 - clkIpGpt2S clock = (0 << 8) | nxp.CCM_CCGR0_CG13_Pos // CCGR0, CG13 - clkIpLpuart2 clock = (0 << 8) | nxp.CCM_CCGR0_CG14_Pos // CCGR0, CG14 - clkIpGpio2 clock = (0 << 8) | nxp.CCM_CCGR0_CG15_Pos // CCGR0, CG15 - - clkIpLpspi1 clock = (1 << 8) | nxp.CCM_CCGR1_CG0_Pos // CCGR1, CG0 - clkIpLpspi2 clock = (1 << 8) | nxp.CCM_CCGR1_CG1_Pos // CCGR1, CG1 - clkIpLpspi3 clock = (1 << 8) | nxp.CCM_CCGR1_CG2_Pos // CCGR1, CG2 - clkIpLpspi4 clock = (1 << 8) | nxp.CCM_CCGR1_CG3_Pos // CCGR1, CG3 - clkIpAdc2 clock = (1 << 8) | nxp.CCM_CCGR1_CG4_Pos // CCGR1, CG4 - clkIpEnet clock = (1 << 8) | nxp.CCM_CCGR1_CG5_Pos // CCGR1, CG5 - clkIpPit clock = (1 << 8) | nxp.CCM_CCGR1_CG6_Pos // CCGR1, CG6 - clkIpAoi2 clock = (1 << 8) | nxp.CCM_CCGR1_CG7_Pos // CCGR1, CG7 - clkIpAdc1 clock = (1 << 8) | nxp.CCM_CCGR1_CG8_Pos // CCGR1, CG8 - clkIpSemcExsc clock = (1 << 8) | nxp.CCM_CCGR1_CG9_Pos // CCGR1, CG9 - clkIpGpt1 clock = (1 << 8) | nxp.CCM_CCGR1_CG10_Pos // CCGR1, CG10 - clkIpGpt1S clock = (1 << 8) | nxp.CCM_CCGR1_CG11_Pos // CCGR1, CG11 - clkIpLpuart4 clock = (1 << 8) | nxp.CCM_CCGR1_CG12_Pos // CCGR1, CG12 - clkIpGpio1 clock = (1 << 8) | nxp.CCM_CCGR1_CG13_Pos // CCGR1, CG13 - clkIpCsu clock = (1 << 8) | nxp.CCM_CCGR1_CG14_Pos // CCGR1, CG14 - clkIpGpio5 clock = (1 << 8) | nxp.CCM_CCGR1_CG15_Pos // CCGR1, CG15 - - clkIpOcramExsc clock = (2 << 8) | nxp.CCM_CCGR2_CG0_Pos // CCGR2, CG0 - clkIpCsi clock = (2 << 8) | nxp.CCM_CCGR2_CG1_Pos // CCGR2, CG1 - clkIpIomuxcSnvs clock = (2 << 8) | nxp.CCM_CCGR2_CG2_Pos // CCGR2, CG2 - clkIpLpi2c1 clock = (2 << 8) | nxp.CCM_CCGR2_CG3_Pos // CCGR2, CG3 - clkIpLpi2c2 clock = (2 << 8) | nxp.CCM_CCGR2_CG4_Pos // CCGR2, CG4 - clkIpLpi2c3 clock = (2 << 8) | nxp.CCM_CCGR2_CG5_Pos // CCGR2, CG5 - clkIpOcotp clock = (2 << 8) | nxp.CCM_CCGR2_CG6_Pos // CCGR2, CG6 - clkIpXbar3 clock = (2 << 8) | nxp.CCM_CCGR2_CG7_Pos // CCGR2, CG7 - clkIpIpmux1 clock = (2 << 8) | nxp.CCM_CCGR2_CG8_Pos // CCGR2, CG8 - clkIpIpmux2 clock = (2 << 8) | nxp.CCM_CCGR2_CG9_Pos // CCGR2, CG9 - clkIpIpmux3 clock = (2 << 8) | nxp.CCM_CCGR2_CG10_Pos // CCGR2, CG10 - clkIpXbar1 clock = (2 << 8) | nxp.CCM_CCGR2_CG11_Pos // CCGR2, CG11 - clkIpXbar2 clock = (2 << 8) | nxp.CCM_CCGR2_CG12_Pos // CCGR2, CG12 - clkIpGpio3 clock = (2 << 8) | nxp.CCM_CCGR2_CG13_Pos // CCGR2, CG13 - clkIpLcd clock = (2 << 8) | nxp.CCM_CCGR2_CG14_Pos // CCGR2, CG14 - clkIpPxp clock = (2 << 8) | nxp.CCM_CCGR2_CG15_Pos // CCGR2, CG15 - - clkIpFlexio2 clock = (3 << 8) | nxp.CCM_CCGR3_CG0_Pos // CCGR3, CG0 - clkIpLpuart5 clock = (3 << 8) | nxp.CCM_CCGR3_CG1_Pos // CCGR3, CG1 - clkIpSemc clock = (3 << 8) | nxp.CCM_CCGR3_CG2_Pos // CCGR3, CG2 - clkIpLpuart6 clock = (3 << 8) | nxp.CCM_CCGR3_CG3_Pos // CCGR3, CG3 - clkIpAoi1 clock = (3 << 8) | nxp.CCM_CCGR3_CG4_Pos // CCGR3, CG4 - clkIpLcdPixel clock = (3 << 8) | nxp.CCM_CCGR3_CG5_Pos // CCGR3, CG5 - clkIpGpio4 clock = (3 << 8) | nxp.CCM_CCGR3_CG6_Pos // CCGR3, CG6 - clkIpEwm0 clock = (3 << 8) | nxp.CCM_CCGR3_CG7_Pos // CCGR3, CG7 - clkIpWdog1 clock = (3 << 8) | nxp.CCM_CCGR3_CG8_Pos // CCGR3, CG8 - clkIpFlexRam clock = (3 << 8) | nxp.CCM_CCGR3_CG9_Pos // CCGR3, CG9 - clkIpAcmp1 clock = (3 << 8) | nxp.CCM_CCGR3_CG10_Pos // CCGR3, CG10 - clkIpAcmp2 clock = (3 << 8) | nxp.CCM_CCGR3_CG11_Pos // CCGR3, CG11 - clkIpAcmp3 clock = (3 << 8) | nxp.CCM_CCGR3_CG12_Pos // CCGR3, CG12 - clkIpAcmp4 clock = (3 << 8) | nxp.CCM_CCGR3_CG13_Pos // CCGR3, CG13 - clkIpOcram clock = (3 << 8) | nxp.CCM_CCGR3_CG14_Pos // CCGR3, CG14 - clkIpIomuxcSnvsGpr clock = (3 << 8) | nxp.CCM_CCGR3_CG15_Pos // CCGR3, CG15 - - clkIpIomuxc clock = (4 << 8) | nxp.CCM_CCGR4_CG1_Pos // CCGR4, CG1 - clkIpIomuxcGpr clock = (4 << 8) | nxp.CCM_CCGR4_CG2_Pos // CCGR4, CG2 - clkIpBee clock = (4 << 8) | nxp.CCM_CCGR4_CG3_Pos // CCGR4, CG3 - clkIpSimM7 clock = (4 << 8) | nxp.CCM_CCGR4_CG4_Pos // CCGR4, CG4 - clkIpTsc clock = (4 << 8) | nxp.CCM_CCGR4_CG5_Pos // CCGR4, CG5 - clkIpSimM clock = (4 << 8) | nxp.CCM_CCGR4_CG6_Pos // CCGR4, CG6 - clkIpSimEms clock = (4 << 8) | nxp.CCM_CCGR4_CG7_Pos // CCGR4, CG7 - clkIpPwm1 clock = (4 << 8) | nxp.CCM_CCGR4_CG8_Pos // CCGR4, CG8 - clkIpPwm2 clock = (4 << 8) | nxp.CCM_CCGR4_CG9_Pos // CCGR4, CG9 - clkIpPwm3 clock = (4 << 8) | nxp.CCM_CCGR4_CG10_Pos // CCGR4, CG10 - clkIpPwm4 clock = (4 << 8) | nxp.CCM_CCGR4_CG11_Pos // CCGR4, CG11 - clkIpEnc1 clock = (4 << 8) | nxp.CCM_CCGR4_CG12_Pos // CCGR4, CG12 - clkIpEnc2 clock = (4 << 8) | nxp.CCM_CCGR4_CG13_Pos // CCGR4, CG13 - clkIpEnc3 clock = (4 << 8) | nxp.CCM_CCGR4_CG14_Pos // CCGR4, CG14 - clkIpEnc4 clock = (4 << 8) | nxp.CCM_CCGR4_CG15_Pos // CCGR4, CG15 - - clkIpRom clock = (5 << 8) | nxp.CCM_CCGR5_CG0_Pos // CCGR5, CG0 - clkIpFlexio1 clock = (5 << 8) | nxp.CCM_CCGR5_CG1_Pos // CCGR5, CG1 - clkIpWdog3 clock = (5 << 8) | nxp.CCM_CCGR5_CG2_Pos // CCGR5, CG2 - clkIpDma clock = (5 << 8) | nxp.CCM_CCGR5_CG3_Pos // CCGR5, CG3 - clkIpKpp clock = (5 << 8) | nxp.CCM_CCGR5_CG4_Pos // CCGR5, CG4 - clkIpWdog2 clock = (5 << 8) | nxp.CCM_CCGR5_CG5_Pos // CCGR5, CG5 - clkIpAipsTz4 clock = (5 << 8) | nxp.CCM_CCGR5_CG6_Pos // CCGR5, CG6 - clkIpSpdif clock = (5 << 8) | nxp.CCM_CCGR5_CG7_Pos // CCGR5, CG7 - clkIpSimMain clock = (5 << 8) | nxp.CCM_CCGR5_CG8_Pos // CCGR5, CG8 - clkIpSai1 clock = (5 << 8) | nxp.CCM_CCGR5_CG9_Pos // CCGR5, CG9 - clkIpSai2 clock = (5 << 8) | nxp.CCM_CCGR5_CG10_Pos // CCGR5, CG10 - clkIpSai3 clock = (5 << 8) | nxp.CCM_CCGR5_CG11_Pos // CCGR5, CG11 - clkIpLpuart1 clock = (5 << 8) | nxp.CCM_CCGR5_CG12_Pos // CCGR5, CG12 - clkIpLpuart7 clock = (5 << 8) | nxp.CCM_CCGR5_CG13_Pos // CCGR5, CG13 - clkIpSnvsHp clock = (5 << 8) | nxp.CCM_CCGR5_CG14_Pos // CCGR5, CG14 - clkIpSnvsLp clock = (5 << 8) | nxp.CCM_CCGR5_CG15_Pos // CCGR5, CG15 - - clkIpUsbOh3 clock = (6 << 8) | nxp.CCM_CCGR6_CG0_Pos // CCGR6, CG0 - clkIpUsdhc1 clock = (6 << 8) | nxp.CCM_CCGR6_CG1_Pos // CCGR6, CG1 - clkIpUsdhc2 clock = (6 << 8) | nxp.CCM_CCGR6_CG2_Pos // CCGR6, CG2 - clkIpDcdc clock = (6 << 8) | nxp.CCM_CCGR6_CG3_Pos // CCGR6, CG3 - clkIpIpmux4 clock = (6 << 8) | nxp.CCM_CCGR6_CG4_Pos // CCGR6, CG4 - clkIpFlexSpi clock = (6 << 8) | nxp.CCM_CCGR6_CG5_Pos // CCGR6, CG5 - clkIpTrng clock = (6 << 8) | nxp.CCM_CCGR6_CG6_Pos // CCGR6, CG6 - clkIpLpuart8 clock = (6 << 8) | nxp.CCM_CCGR6_CG7_Pos // CCGR6, CG7 - clkIpTimer4 clock = (6 << 8) | nxp.CCM_CCGR6_CG8_Pos // CCGR6, CG8 - clkIpAipsTz3 clock = (6 << 8) | nxp.CCM_CCGR6_CG9_Pos // CCGR6, CG9 - clkIpSimPer clock = (6 << 8) | nxp.CCM_CCGR6_CG10_Pos // CCGR6, CG10 - clkIpAnadig clock = (6 << 8) | nxp.CCM_CCGR6_CG11_Pos // CCGR6, CG11 - clkIpLpi2c4 clock = (6 << 8) | nxp.CCM_CCGR6_CG12_Pos // CCGR6, CG12 - clkIpTimer1 clock = (6 << 8) | nxp.CCM_CCGR6_CG13_Pos // CCGR6, CG13 - clkIpTimer2 clock = (6 << 8) | nxp.CCM_CCGR6_CG14_Pos // CCGR6, CG14 - clkIpTimer3 clock = (6 << 8) | nxp.CCM_CCGR6_CG15_Pos // CCGR6, CG15 - - clkIpEnet2 clock = (7 << 8) | nxp.CCM_CCGR7_CG0_Pos // CCGR7, CG0 - clkIpFlexSpi2 clock = (7 << 8) | nxp.CCM_CCGR7_CG1_Pos // CCGR7, CG1 - clkIpAxbsL clock = (7 << 8) | nxp.CCM_CCGR7_CG2_Pos // CCGR7, CG2 - clkIpCan3 clock = (7 << 8) | nxp.CCM_CCGR7_CG3_Pos // CCGR7, CG3 - clkIpCan3S clock = (7 << 8) | nxp.CCM_CCGR7_CG4_Pos // CCGR7, CG4 - clkIpAipsLite clock = (7 << 8) | nxp.CCM_CCGR7_CG5_Pos // CCGR7, CG5 - clkIpFlexio3 clock = (7 << 8) | nxp.CCM_CCGR7_CG6_Pos // CCGR7, CG6 -) - -// Selected clock offsets -const ( - offCCSR = 0x0C - offCBCDR = 0x14 - offCBCMR = 0x18 - offCSCMR1 = 0x1C - offCSCMR2 = 0x20 - offCSCDR1 = 0x24 - offCDCDR = 0x30 - offCSCDR2 = 0x38 - offCSCDR3 = 0x3C - offCACRR = 0x10 - offCS1CDR = 0x28 - offCS2CDR = 0x2C - - offPllArm = 0x00 - offPllSys = 0x30 - offPllUsb1 = 0x10 - offPllAudio = 0x70 - offPllVideo = 0xA0 - offPllEnet = 0xE0 - offPllUsb2 = 0x20 - - noBusyWait = 0x20 -) - -// analog pll definition -const ( - pllBypassPos = 16 - pllBypassClkSrcMsk = 0xC000 - pllBypassClkSrcPos = 14 -) - -// getFreq returns the calculated frequency of the receiver clock clk. -func (clk clock) getFreq() uint32 { - switch clk { - case clkCpu, clkAhb: - return getAhbFreq() - case clkSemc: - return getSemcFreq() - case clkIpg: - return getIpgFreq() - case clkPer: - return getPerClkFreq() - case clkOsc: - return getOscFreq() - case clkRtc: - return getRtcFreq() - case clkArmPll: - return clkPllArm.getPllFreq() - case clkUsb1Pll: - return clkPllUsb1.getPllFreq() - case clkUsb1PllPfd0: - return clkPfd0.getUsb1PfdFreq() - case clkUsb1PllPfd1: - return clkPfd1.getUsb1PfdFreq() - case clkUsb1PllPfd2: - return clkPfd2.getUsb1PfdFreq() - case clkUsb1PllPfd3: - return clkPfd3.getUsb1PfdFreq() - case clkUsb2Pll: - return clkPllUsb2.getPllFreq() - case clkSysPll: - return clkPllSys.getPllFreq() - case clkSysPllPfd0: - return clkPfd0.getSysPfdFreq() - case clkSysPllPfd1: - return clkPfd1.getSysPfdFreq() - case clkSysPllPfd2: - return clkPfd2.getSysPfdFreq() - case clkSysPllPfd3: - return clkPfd3.getSysPfdFreq() - case clkEnetPll0: - return clkPllEnet.getPllFreq() - case clkEnetPll1: - return clkPllEnet2.getPllFreq() - case clkEnetPll2: - return clkPllEnet25M.getPllFreq() - case clkAudioPll: - return clkPllAudio.getPllFreq() - case clkVideoPll: - return clkPllVideo.getPllFreq() - default: - panic("runtime: invalid clock") - } -} - -// getOscFreq returns the XTAL OSC clock frequency -func getOscFreq() uint32 { - return 24000000 // 24 MHz -} - -// getRtcFreq returns the RTC clock frequency -func getRtcFreq() uint32 { - return 32768 // 32.768 kHz -} - -func ccmCbcmrPeriphClk2Sel(n uint32) uint32 { - return (n << nxp.CCM_CBCMR_PERIPH_CLK2_SEL_Pos) & nxp.CCM_CBCMR_PERIPH_CLK2_SEL_Msk -} - -func ccmCbcmrPrePeriphClkSel(n uint32) uint32 { - return (n << nxp.CCM_CBCMR_PRE_PERIPH_CLK_SEL_Pos) & nxp.CCM_CBCMR_PRE_PERIPH_CLK_SEL_Msk -} - -// getPeriphClkFreq returns the PERIPH clock frequency -func getPeriphClkFreq() uint32 { - freq := uint32(0) - if nxp.CCM.CBCDR.HasBits(nxp.CCM_CBCDR_PERIPH_CLK_SEL_Msk) { - // Periph_clk2_clk -> Periph_clk - switch nxp.CCM.CBCMR.Get() & nxp.CCM_CBCMR_PERIPH_CLK2_SEL_Msk { - case ccmCbcmrPeriphClk2Sel(0): - // Pll3_sw_clk -> Periph_clk2_clk -> Periph_clk - freq = clkPllUsb1.getPllFreq() - case ccmCbcmrPeriphClk2Sel(1): - // Osc_clk -> Periph_clk2_clk -> Periph_clk - freq = getOscFreq() - case ccmCbcmrPeriphClk2Sel(2): - freq = clkPllSys.getPllFreq() - case ccmCbcmrPeriphClk2Sel(3): - freq = 0 - } - freq /= ((nxp.CCM.CBCDR.Get() & nxp.CCM_CBCDR_PERIPH_CLK2_PODF_Msk) >> nxp.CCM_CBCDR_PERIPH_CLK2_PODF_Pos) + 1 - } else { - // Pre_Periph_clk -> Periph_clk - switch nxp.CCM.CBCMR.Get() & nxp.CCM_CBCMR_PRE_PERIPH_CLK_SEL_Msk { - case ccmCbcmrPrePeriphClkSel(0): - // PLL2 -> Pre_Periph_clk -> Periph_clk - freq = clkPllSys.getPllFreq() - case ccmCbcmrPrePeriphClkSel(1): - // PLL2 PFD2 -> Pre_Periph_clk -> Periph_clk - freq = clkPfd2.getSysPfdFreq() - case ccmCbcmrPrePeriphClkSel(2): - // PLL2 PFD0 -> Pre_Periph_clk -> Periph_clk - freq = clkPfd0.getSysPfdFreq() - case ccmCbcmrPrePeriphClkSel(3): - // PLL1 divided(/2) -> Pre_Periph_clk -> Periph_clk - freq = clkPllArm.getPllFreq() / (((nxp.CCM.CACRR.Get() & nxp.CCM_CACRR_ARM_PODF_Msk) >> nxp.CCM_CACRR_ARM_PODF_Pos) + 1) - } - } - return freq -} - -// getAhbFreq returns the AHB clock frequency -func getAhbFreq() uint32 { - return getPeriphClkFreq() / (((nxp.CCM.CBCDR.Get() & nxp.CCM_CBCDR_AHB_PODF_Msk) >> nxp.CCM_CBCDR_AHB_PODF_Pos) + 1) -} - -// getSemcFreq returns the SEMC clock frequency -func getSemcFreq() uint32 { - - freq := uint32(0) - - if nxp.CCM.CBCDR.HasBits(nxp.CCM_CBCDR_SEMC_CLK_SEL_Msk) { - // SEMC alternative clock -> SEMC Clock - - if nxp.CCM.CBCDR.HasBits(nxp.CCM_CBCDR_SEMC_ALT_CLK_SEL_Msk) { - // PLL3 PFD1 -> SEMC alternative clock -> SEMC Clock - freq = clkPfd1.getUsb1PfdFreq() - } else { - // PLL2 PFD2 -> SEMC alternative clock -> SEMC Clock - freq = clkPfd2.getSysPfdFreq() - } - } else { - // Periph_clk -> SEMC Clock - freq = getPeriphClkFreq() - } - - freq /= ((nxp.CCM.CBCDR.Get() & nxp.CCM_CBCDR_SEMC_PODF_Msk) >> nxp.CCM_CBCDR_SEMC_PODF_Pos) + 1 - - return freq -} - -// getIpgFreq returns the IPG clock frequency -func getIpgFreq() uint32 { - return getAhbFreq() / (((nxp.CCM.CBCDR.Get() & nxp.CCM_CBCDR_IPG_PODF_Msk) >> nxp.CCM_CBCDR_IPG_PODF_Pos) + 1) -} - -// getPerClkFreq returns the PER clock frequency -func getPerClkFreq() uint32 { - freq := uint32(0) - if nxp.CCM.CSCMR1.HasBits(nxp.CCM_CSCMR1_PERCLK_CLK_SEL_Msk) { - // Osc_clk -> PER Cloc - freq = getOscFreq() - } else { - // Periph_clk -> AHB Clock -> IPG Clock -> PER Clock - freq = getIpgFreq() - } - return freq/((nxp.CCM.CSCMR1.Get()&nxp.CCM_CSCMR1_PERCLK_PODF_Msk)>> - nxp.CCM_CSCMR1_PERCLK_PODF_Pos) + 1 -} - -// getPllFreq returns the clock frequency of the receiver (PLL) clock clk -func (clk clock) getPllFreq() uint32 { - enetRefClkFreq := []uint32{ - 25000000, // 25 MHz - 50000000, // 50 MHz - 100000000, // 100 MHz - 125000000, // 125 MHz - } - // check if PLL is enabled - if !clk.isPllEnabled() { - return 0 - } - // get pll reference clock - freq := clk.getBypassFreq() - // check if pll is bypassed - if clk.isPllBypassed() { - return freq - } - switch clk { - case clkPllArm: - freq *= (nxp.CCM_ANALOG.PLL_ARM.Get() & nxp.CCM_ANALOG_PLL_ARM_DIV_SELECT_Msk) >> nxp.CCM_ANALOG_PLL_ARM_DIV_SELECT_Pos - freq >>= 1 - case clkPllSys: - // PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). - fFreq := float64(freq) * float64(nxp.CCM_ANALOG.PLL_SYS_NUM.Get()) - fFreq /= float64(nxp.CCM_ANALOG.PLL_SYS_DENOM.Get()) - if nxp.CCM_ANALOG.PLL_SYS.HasBits(nxp.CCM_ANALOG_PLL_SYS_DIV_SELECT_Msk) { - freq *= 22 - } else { - freq *= 20 - } - freq += uint32(fFreq) - case clkPllUsb1: - if nxp.CCM_ANALOG.PLL_USB1.HasBits(nxp.CCM_ANALOG_PLL_USB1_DIV_SELECT_Msk) { - freq *= 22 - } else { - freq *= 20 - } - case clkPllEnet: - divSelect := (nxp.CCM_ANALOG.PLL_ENET.Get() & nxp.CCM_ANALOG_PLL_ENET_DIV_SELECT_Msk) >> nxp.CCM_ANALOG_PLL_ENET_DIV_SELECT_Pos - freq = enetRefClkFreq[divSelect] - case clkPllEnet2: - divSelect := (nxp.CCM_ANALOG.PLL_ENET.Get() & nxp.CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_Msk) >> nxp.CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_Pos - freq = enetRefClkFreq[divSelect] - case clkPllEnet25M: - // ref_enetpll1 if fixed at 25MHz. - freq = 25000000 - case clkPllUsb2: - if nxp.CCM_ANALOG.PLL_USB2.HasBits(nxp.CCM_ANALOG_PLL_USB2_DIV_SELECT_Msk) { - freq *= 22 - } else { - freq *= 20 - } - default: - freq = 0 - } - return freq -} - -// getSysPfdFreq returns current system PLL PFD output frequency -func (clk clock) getSysPfdFreq() uint32 { - freq := clkPllSys.getPllFreq() - switch clk { - case clkPfd0: - freq /= (nxp.CCM_ANALOG.PFD_528.Get() & nxp.CCM_ANALOG_PFD_528_PFD0_FRAC_Msk) >> nxp.CCM_ANALOG_PFD_528_PFD0_FRAC_Pos - case clkPfd1: - freq /= (nxp.CCM_ANALOG.PFD_528.Get() & nxp.CCM_ANALOG_PFD_528_PFD1_FRAC_Msk) >> nxp.CCM_ANALOG_PFD_528_PFD1_FRAC_Pos - case clkPfd2: - freq /= (nxp.CCM_ANALOG.PFD_528.Get() & nxp.CCM_ANALOG_PFD_528_PFD2_FRAC_Msk) >> nxp.CCM_ANALOG_PFD_528_PFD2_FRAC_Pos - case clkPfd3: - freq /= (nxp.CCM_ANALOG.PFD_528.Get() & nxp.CCM_ANALOG_PFD_528_PFD3_FRAC_Msk) >> nxp.CCM_ANALOG_PFD_528_PFD3_FRAC_Pos - default: - freq = 0 - } - return freq * 18 -} - -// getUsb1PfdFreq returns current USB1 PLL PFD output frequency -func (clk clock) getUsb1PfdFreq() uint32 { - freq := clkPllUsb1.getPllFreq() - switch clk { - case clkPfd0: - freq /= (nxp.CCM_ANALOG.PFD_480.Get() & nxp.CCM_ANALOG_PFD_480_PFD0_FRAC_Msk) >> nxp.CCM_ANALOG_PFD_480_PFD0_FRAC_Pos - case clkPfd1: - freq /= (nxp.CCM_ANALOG.PFD_480.Get() & nxp.CCM_ANALOG_PFD_480_PFD1_FRAC_Msk) >> nxp.CCM_ANALOG_PFD_480_PFD1_FRAC_Pos - case clkPfd2: - freq /= (nxp.CCM_ANALOG.PFD_480.Get() & nxp.CCM_ANALOG_PFD_480_PFD2_FRAC_Msk) >> nxp.CCM_ANALOG_PFD_480_PFD2_FRAC_Pos - case clkPfd3: - freq /= (nxp.CCM_ANALOG.PFD_480.Get() & nxp.CCM_ANALOG_PFD_480_PFD3_FRAC_Msk) >> nxp.CCM_ANALOG_PFD_480_PFD3_FRAC_Pos - default: - freq = 0 - } - return freq * 18 -} - -// getCCGR returns the CCM clock gating register for the receiver clk. -func (clk clock) getCCGR() *volatile.Register32 { - switch clk >> 8 { - case 0: - return &nxp.CCM.CCGR0 - case 1: - return &nxp.CCM.CCGR1 - case 2: - return &nxp.CCM.CCGR2 - case 3: - return &nxp.CCM.CCGR3 - case 4: - return &nxp.CCM.CCGR4 - case 5: - return &nxp.CCM.CCGR5 - case 6: - return &nxp.CCM.CCGR6 - case 7: - return &nxp.CCM.CCGR7 - default: - panic("runtime: invalid clock") - } -} - -// control enables or disables the receiver clk using its gating register. -func (clk clock) control(value gate) { - reg := clk.getCCGR() - shift := clk & 0x1F - reg.Set((reg.Get() & ^(3 << shift)) | (uint32(value) << shift)) -} - -func (clk clock) enable(enable bool) { - if enable { - clk.control(gateClkNeededRunWait) - } else { - clk.control(gateClkNotNeeded) - } -} - -func (clk clock) mux(mux uint32) { clk.ccm(mux) } -func (clk clock) div(div uint32) { clk.ccm(div) } - -func (clk clock) ccm(value uint32) { - const ccmBase = 0x400fc000 - reg := (*volatile.Register32)(unsafe.Pointer(uintptr(ccmBase + (uint32(clk) & 0xFF)))) - msk := ((uint32(clk) >> 13) & 0x1FFF) << ((uint32(clk) >> 8) & 0x1F) - pos := (uint32(clk) >> 8) & 0x1F - bsy := (uint32(clk) >> 26) & 0x3F - reg.Set((reg.Get() & ^uint32(msk)) | ((value << pos) & msk)) - if bsy < noBusyWait { - for nxp.CCM.CDHIPR.HasBits(1 << bsy) { - } - } -} - -func setSysPfd(value ...uint32) { - for i, val := range value { - pfd528 := nxp.CCM_ANALOG.PFD_528.Get() & - ^((nxp.CCM_ANALOG_PFD_528_PFD0_CLKGATE_Msk | nxp.CCM_ANALOG_PFD_528_PFD0_FRAC_Msk) << (8 * uint32(i))) - frac := (val << nxp.CCM_ANALOG_PFD_528_PFD0_FRAC_Pos) & nxp.CCM_ANALOG_PFD_528_PFD0_FRAC_Msk - // disable the clock output first - nxp.CCM_ANALOG.PFD_528.Set(pfd528 | (nxp.CCM_ANALOG_PFD_528_PFD0_CLKGATE_Msk << (8 * uint32(i)))) - // set the new value and enable output - nxp.CCM_ANALOG.PFD_528.Set(pfd528 | (frac << (8 * uint32(i)))) - } -} - -func setUsb1Pfd(value ...uint32) { - for i, val := range value { - pfd480 := nxp.CCM_ANALOG.PFD_480.Get() & - ^((nxp.CCM_ANALOG_PFD_480_PFD0_CLKGATE_Msk | nxp.CCM_ANALOG_PFD_480_PFD0_FRAC_Msk) << (8 * uint32(i))) - frac := (val << nxp.CCM_ANALOG_PFD_480_PFD0_FRAC_Pos) & nxp.CCM_ANALOG_PFD_480_PFD0_FRAC_Msk - // disable the clock output first - nxp.CCM_ANALOG.PFD_480.Set(pfd480 | (nxp.CCM_ANALOG_PFD_480_PFD0_CLKGATE_Msk << (8 * uint32(i)))) - // set the new value and enable output - nxp.CCM_ANALOG.PFD_480.Set(pfd480 | (frac << (8 * uint32(i)))) - } -} - -func (clk clock) isPllEnabled() bool { - const ccmAnalogBase = 0x400d8000 - addr := ccmAnalogBase + ((uint32(clk) >> 16) & 0xFFF) - pos := uint32(1 << (uint32(clk) & 0x1F)) - return ((*volatile.Register32)(unsafe.Pointer(uintptr(addr)))).HasBits(pos) -} - -func (clk clock) isPllBypassed() bool { - const ccmAnalogBase = 0x400d8000 - addr := ccmAnalogBase + ((uint32(clk) >> 16) & 0xFFF) - pos := uint32(1 << pllBypassPos) - return ((*volatile.Register32)(unsafe.Pointer(uintptr(addr)))).HasBits(pos) -} - -func (clk clock) getBypassFreq() uint32 { - const ccmAnalogBase = 0x400d8000 - addr := ccmAnalogBase + ((uint32(clk) >> 16) & 0xFFF) - src := (((*volatile.Register32)(unsafe.Pointer(uintptr(addr)))).Get() & - pllBypassClkSrcMsk) >> pllBypassClkSrcPos - if src == uint32(pllSrc24M) { - return getOscFreq() - } - return 0 -} - -func (clk clock) bypass(bypass bool) { - const ccmAnalogBase = 0x400d8000 - if bypass { - addr := ccmAnalogBase + ((uint32(clk) >> 16) & 0xFFF) + 4 - ((*volatile.Register32)(unsafe.Pointer(uintptr(addr)))).Set(1 << pllBypassPos) - } else { - addr := ccmAnalogBase + ((uint32(clk) >> 16) & 0xFFF) + 8 - ((*volatile.Register32)(unsafe.Pointer(uintptr(addr)))).Set(1 << pllBypassPos) - } -} - -const ( - oscRc = 0 // On chip OSC - oscXtal = 1 // 24M Xtal OSC -) - -type gate uint8 - -const ( - gateClkNotNeeded gate = 0 // Clock is off during all modes - gateClkNeededRun gate = 1 // Clock is on in run mode, but off in WAIT and STOP modes - gateClkNeededRunWait gate = 3 // Clock is on during all modes, except STOP mode -) - -type clockMode uint8 - -const ( - modeClkRun clockMode = 0 // Remain in run mode - modeClkWait clockMode = 1 // Transfer to wait mode - modeClkStop clockMode = 2 // Transfer to stop mode -) - -func (m clockMode) set() { - nxp.CCM.CLPCR.Set((nxp.CCM.CLPCR.Get() & ^uint32(nxp.CCM_CLPCR_LPM_Msk)) | - ((uint32(m) << nxp.CCM_CLPCR_LPM_Pos) & nxp.CCM_CLPCR_LPM_Msk)) -} - -const ( - muxIpPll3Sw clock = (offCCSR & 0xFF) | (nxp.CCM_CCSR_PLL3_SW_CLK_SEL_Pos << 8) | (((nxp.CCM_CCSR_PLL3_SW_CLK_SEL_Msk >> nxp.CCM_CCSR_PLL3_SW_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // pll3_sw_clk mux name - muxIpPeriph clock = (offCBCDR & 0xFF) | (nxp.CCM_CBCDR_PERIPH_CLK_SEL_Pos << 8) | (((nxp.CCM_CBCDR_PERIPH_CLK_SEL_Msk >> nxp.CCM_CBCDR_PERIPH_CLK_SEL_Pos) & 0x1FFF) << 13) | (nxp.CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_Pos << 26) // periph mux name - muxIpSemcAlt clock = (offCBCDR & 0xFF) | (nxp.CCM_CBCDR_SEMC_ALT_CLK_SEL_Pos << 8) | (((nxp.CCM_CBCDR_SEMC_ALT_CLK_SEL_Msk >> nxp.CCM_CBCDR_SEMC_ALT_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // semc mux name - muxIpSemc clock = (offCBCDR & 0xFF) | (nxp.CCM_CBCDR_SEMC_CLK_SEL_Pos << 8) | (((nxp.CCM_CBCDR_SEMC_CLK_SEL_Msk >> nxp.CCM_CBCDR_SEMC_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // semc mux name - muxIpPrePeriph clock = (offCBCMR & 0xFF) | (nxp.CCM_CBCMR_PRE_PERIPH_CLK_SEL_Pos << 8) | (((nxp.CCM_CBCMR_PRE_PERIPH_CLK_SEL_Msk >> nxp.CCM_CBCMR_PRE_PERIPH_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // pre-periph mux name - muxIpTrace clock = (offCBCMR & 0xFF) | (nxp.CCM_CBCMR_TRACE_CLK_SEL_Pos << 8) | (((nxp.CCM_CBCMR_TRACE_CLK_SEL_Msk >> nxp.CCM_CBCMR_TRACE_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // trace mux name - muxIpPeriphClk2 clock = (offCBCMR & 0xFF) | (nxp.CCM_CBCMR_PERIPH_CLK2_SEL_Pos << 8) | (((nxp.CCM_CBCMR_PERIPH_CLK2_SEL_Msk >> nxp.CCM_CBCMR_PERIPH_CLK2_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // periph clock2 mux name - muxIpFlexSpi2 clock = (offCBCMR & 0xFF) | (nxp.CCM_CBCMR_FLEXSPI2_CLK_SEL_Pos << 8) | (((nxp.CCM_CBCMR_FLEXSPI2_CLK_SEL_Msk >> nxp.CCM_CBCMR_FLEXSPI2_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // flexspi2 mux name - muxIpLpspi clock = (offCBCMR & 0xFF) | (nxp.CCM_CBCMR_LPSPI_CLK_SEL_Pos << 8) | (((nxp.CCM_CBCMR_LPSPI_CLK_SEL_Msk >> nxp.CCM_CBCMR_LPSPI_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // lpspi mux name - muxIpFlexSpi clock = (offCSCMR1 & 0xFF) | (nxp.CCM_CSCMR1_FLEXSPI_CLK_SEL_Pos << 8) | (((nxp.CCM_CSCMR1_FLEXSPI_CLK_SEL_Msk >> nxp.CCM_CSCMR1_FLEXSPI_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // flexspi mux name - muxIpUsdhc2 clock = (offCSCMR1 & 0xFF) | (nxp.CCM_CSCMR1_USDHC2_CLK_SEL_Pos << 8) | (((nxp.CCM_CSCMR1_USDHC2_CLK_SEL_Msk >> nxp.CCM_CSCMR1_USDHC2_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // usdhc2 mux name - muxIpUsdhc1 clock = (offCSCMR1 & 0xFF) | (nxp.CCM_CSCMR1_USDHC1_CLK_SEL_Pos << 8) | (((nxp.CCM_CSCMR1_USDHC1_CLK_SEL_Msk >> nxp.CCM_CSCMR1_USDHC1_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // usdhc1 mux name - muxIpSai3 clock = (offCSCMR1 & 0xFF) | (nxp.CCM_CSCMR1_SAI3_CLK_SEL_Pos << 8) | (((nxp.CCM_CSCMR1_SAI3_CLK_SEL_Msk >> nxp.CCM_CSCMR1_SAI3_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // sai3 mux name - muxIpSai2 clock = (offCSCMR1 & 0xFF) | (nxp.CCM_CSCMR1_SAI2_CLK_SEL_Pos << 8) | (((nxp.CCM_CSCMR1_SAI2_CLK_SEL_Msk >> nxp.CCM_CSCMR1_SAI2_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // sai2 mux name - muxIpSai1 clock = (offCSCMR1 & 0xFF) | (nxp.CCM_CSCMR1_SAI1_CLK_SEL_Pos << 8) | (((nxp.CCM_CSCMR1_SAI1_CLK_SEL_Msk >> nxp.CCM_CSCMR1_SAI1_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // sai1 mux name - muxIpPerclk clock = (offCSCMR1 & 0xFF) | (nxp.CCM_CSCMR1_PERCLK_CLK_SEL_Pos << 8) | (((nxp.CCM_CSCMR1_PERCLK_CLK_SEL_Msk >> nxp.CCM_CSCMR1_PERCLK_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // perclk mux name - muxIpFlexio2 clock = (offCSCMR2 & 0xFF) | (nxp.CCM_CSCMR2_FLEXIO2_CLK_SEL_Pos << 8) | (((nxp.CCM_CSCMR2_FLEXIO2_CLK_SEL_Msk >> nxp.CCM_CSCMR2_FLEXIO2_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // flexio2 mux name - muxIpCan clock = (offCSCMR2 & 0xFF) | (nxp.CCM_CSCMR2_CAN_CLK_SEL_Pos << 8) | (((nxp.CCM_CSCMR2_CAN_CLK_SEL_Msk >> nxp.CCM_CSCMR2_CAN_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // can mux name - muxIpUart clock = (offCSCDR1 & 0xFF) | (nxp.CCM_CSCDR1_UART_CLK_SEL_Pos << 8) | (((nxp.CCM_CSCDR1_UART_CLK_SEL_Msk >> nxp.CCM_CSCDR1_UART_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // uart mux name - muxIpSpdif clock = (offCDCDR & 0xFF) | (nxp.CCM_CDCDR_SPDIF0_CLK_SEL_Pos << 8) | (((nxp.CCM_CDCDR_SPDIF0_CLK_SEL_Msk >> nxp.CCM_CDCDR_SPDIF0_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // spdif mux name - muxIpFlexio1 clock = (offCDCDR & 0xFF) | (nxp.CCM_CDCDR_FLEXIO1_CLK_SEL_Pos << 8) | (((nxp.CCM_CDCDR_FLEXIO1_CLK_SEL_Msk >> nxp.CCM_CDCDR_FLEXIO1_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // flexio1 mux name - muxIpLpi2c clock = (offCSCDR2 & 0xFF) | (nxp.CCM_CSCDR2_LPI2C_CLK_SEL_Pos << 8) | (((nxp.CCM_CSCDR2_LPI2C_CLK_SEL_Msk >> nxp.CCM_CSCDR2_LPI2C_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // lpi2c mux name - muxIpLcdifPre clock = (offCSCDR2 & 0xFF) | (nxp.CCM_CSCDR2_LCDIF_PRE_CLK_SEL_Pos << 8) | (((nxp.CCM_CSCDR2_LCDIF_PRE_CLK_SEL_Msk >> nxp.CCM_CSCDR2_LCDIF_PRE_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // lcdif pre mux name - muxIpCsi clock = (offCSCDR3 & 0xFF) | (nxp.CCM_CSCDR3_CSI_CLK_SEL_Pos << 8) | (((nxp.CCM_CSCDR3_CSI_CLK_SEL_Msk >> nxp.CCM_CSCDR3_CSI_CLK_SEL_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // csi mux name -) - -const ( - divIpArm clock = (offCACRR & 0xFF) | (nxp.CCM_CACRR_ARM_PODF_Pos << 8) | (((nxp.CCM_CACRR_ARM_PODF_Msk >> nxp.CCM_CACRR_ARM_PODF_Pos) & 0x1FFF) << 13) | (nxp.CCM_CDHIPR_ARM_PODF_BUSY_Pos << 26) // core div name - divIpPeriphClk2 clock = (offCBCDR & 0xFF) | (nxp.CCM_CBCDR_PERIPH_CLK2_PODF_Pos << 8) | (((nxp.CCM_CBCDR_PERIPH_CLK2_PODF_Msk >> nxp.CCM_CBCDR_PERIPH_CLK2_PODF_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // periph clock2 div name - divIpSemc clock = (offCBCDR & 0xFF) | (nxp.CCM_CBCDR_SEMC_PODF_Pos << 8) | (((nxp.CCM_CBCDR_SEMC_PODF_Msk >> nxp.CCM_CBCDR_SEMC_PODF_Pos) & 0x1FFF) << 13) | (nxp.CCM_CDHIPR_SEMC_PODF_BUSY_Pos << 26) // semc div name - divIpAhb clock = (offCBCDR & 0xFF) | (nxp.CCM_CBCDR_AHB_PODF_Pos << 8) | (((nxp.CCM_CBCDR_AHB_PODF_Msk >> nxp.CCM_CBCDR_AHB_PODF_Pos) & 0x1FFF) << 13) | (nxp.CCM_CDHIPR_AHB_PODF_BUSY_Pos << 26) // ahb div name - divIpIpg clock = (offCBCDR & 0xFF) | (nxp.CCM_CBCDR_IPG_PODF_Pos << 8) | (((nxp.CCM_CBCDR_IPG_PODF_Msk >> nxp.CCM_CBCDR_IPG_PODF_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // ipg div name - divIpFlexSpi2 clock = (offCBCMR & 0xFF) | (nxp.CCM_CBCMR_FLEXSPI2_PODF_Pos << 8) | (((nxp.CCM_CBCMR_FLEXSPI2_PODF_Msk >> nxp.CCM_CBCMR_FLEXSPI2_PODF_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // flexspi2 div name - divIpLpspi clock = (offCBCMR & 0xFF) | (nxp.CCM_CBCMR_LPSPI_PODF_Pos << 8) | (((nxp.CCM_CBCMR_LPSPI_PODF_Msk >> nxp.CCM_CBCMR_LPSPI_PODF_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // lpspi div name - divIpLcdif clock = (offCBCMR & 0xFF) | (nxp.CCM_CBCMR_LCDIF_PODF_Pos << 8) | (((nxp.CCM_CBCMR_LCDIF_PODF_Msk >> nxp.CCM_CBCMR_LCDIF_PODF_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // lcdif div name - divIpFlexSpi clock = (offCSCMR1 & 0xFF) | (nxp.CCM_CSCMR1_FLEXSPI_PODF_Pos << 8) | (((nxp.CCM_CSCMR1_FLEXSPI_PODF_Msk >> nxp.CCM_CSCMR1_FLEXSPI_PODF_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // flexspi div name - divIpPerclk clock = (offCSCMR1 & 0xFF) | (nxp.CCM_CSCMR1_PERCLK_PODF_Pos << 8) | (((nxp.CCM_CSCMR1_PERCLK_PODF_Msk >> nxp.CCM_CSCMR1_PERCLK_PODF_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // perclk div name - divIpCan clock = (offCSCMR2 & 0xFF) | (nxp.CCM_CSCMR2_CAN_CLK_PODF_Pos << 8) | (((nxp.CCM_CSCMR2_CAN_CLK_PODF_Msk >> nxp.CCM_CSCMR2_CAN_CLK_PODF_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // can div name - divIpTrace clock = (offCSCDR1 & 0xFF) | (nxp.CCM_CSCDR1_TRACE_PODF_Pos << 8) | (((nxp.CCM_CSCDR1_TRACE_PODF_Msk >> nxp.CCM_CSCDR1_TRACE_PODF_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // trace div name - divIpUsdhc2 clock = (offCSCDR1 & 0xFF) | (nxp.CCM_CSCDR1_USDHC2_PODF_Pos << 8) | (((nxp.CCM_CSCDR1_USDHC2_PODF_Msk >> nxp.CCM_CSCDR1_USDHC2_PODF_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // usdhc2 div name - divIpUsdhc1 clock = (offCSCDR1 & 0xFF) | (nxp.CCM_CSCDR1_USDHC1_PODF_Pos << 8) | (((nxp.CCM_CSCDR1_USDHC1_PODF_Msk >> nxp.CCM_CSCDR1_USDHC1_PODF_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // usdhc1 div name - divIpUart clock = (offCSCDR1 & 0xFF) | (nxp.CCM_CSCDR1_UART_CLK_PODF_Pos << 8) | (((nxp.CCM_CSCDR1_UART_CLK_PODF_Msk >> nxp.CCM_CSCDR1_UART_CLK_PODF_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // uart div name - divIpFlexio2 clock = (offCS1CDR & 0xFF) | (nxp.CCM_CS1CDR_FLEXIO2_CLK_PODF_Pos << 8) | (((nxp.CCM_CS1CDR_FLEXIO2_CLK_PODF_Msk >> nxp.CCM_CS1CDR_FLEXIO2_CLK_PODF_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // flexio2 pre div name - divIpSai3Pre clock = (offCS1CDR & 0xFF) | (nxp.CCM_CS1CDR_SAI3_CLK_PRED_Pos << 8) | (((nxp.CCM_CS1CDR_SAI3_CLK_PRED_Msk >> nxp.CCM_CS1CDR_SAI3_CLK_PRED_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // sai3 pre div name - divIpSai3 clock = (offCS1CDR & 0xFF) | (nxp.CCM_CS1CDR_SAI3_CLK_PODF_Pos << 8) | (((nxp.CCM_CS1CDR_SAI3_CLK_PODF_Msk >> nxp.CCM_CS1CDR_SAI3_CLK_PODF_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // sai3 div name - divIpFlexio2Pre clock = (offCS1CDR & 0xFF) | (nxp.CCM_CS1CDR_FLEXIO2_CLK_PRED_Pos << 8) | (((nxp.CCM_CS1CDR_FLEXIO2_CLK_PRED_Msk >> nxp.CCM_CS1CDR_FLEXIO2_CLK_PRED_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // sai3 pre div name - divIpSai1Pre clock = (offCS1CDR & 0xFF) | (nxp.CCM_CS1CDR_SAI1_CLK_PRED_Pos << 8) | (((nxp.CCM_CS1CDR_SAI1_CLK_PRED_Msk >> nxp.CCM_CS1CDR_SAI1_CLK_PRED_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // sai1 pre div name - divIpSai1 clock = (offCS1CDR & 0xFF) | (nxp.CCM_CS1CDR_SAI1_CLK_PODF_Pos << 8) | (((nxp.CCM_CS1CDR_SAI1_CLK_PODF_Msk >> nxp.CCM_CS1CDR_SAI1_CLK_PODF_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // sai1 div name - divIpSai2Pre clock = (offCS2CDR & 0xFF) | (nxp.CCM_CS2CDR_SAI2_CLK_PRED_Pos << 8) | (((nxp.CCM_CS2CDR_SAI2_CLK_PRED_Msk >> nxp.CCM_CS2CDR_SAI2_CLK_PRED_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // sai2 pre div name - divIpSai2 clock = (offCS2CDR & 0xFF) | (nxp.CCM_CS2CDR_SAI2_CLK_PODF_Pos << 8) | (((nxp.CCM_CS2CDR_SAI2_CLK_PODF_Msk >> nxp.CCM_CS2CDR_SAI2_CLK_PODF_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // sai2 div name - divIpSpdif0Pre clock = (offCDCDR & 0xFF) | (nxp.CCM_CDCDR_SPDIF0_CLK_PRED_Pos << 8) | (((nxp.CCM_CDCDR_SPDIF0_CLK_PRED_Msk >> nxp.CCM_CDCDR_SPDIF0_CLK_PRED_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // spdif pre div name - divIpSpdif0 clock = (offCDCDR & 0xFF) | (nxp.CCM_CDCDR_SPDIF0_CLK_PODF_Pos << 8) | (((nxp.CCM_CDCDR_SPDIF0_CLK_PODF_Msk >> nxp.CCM_CDCDR_SPDIF0_CLK_PODF_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // spdif div name - divIpFlexio1Pre clock = (offCDCDR & 0xFF) | (nxp.CCM_CDCDR_FLEXIO1_CLK_PRED_Pos << 8) | (((nxp.CCM_CDCDR_FLEXIO1_CLK_PRED_Msk >> nxp.CCM_CDCDR_FLEXIO1_CLK_PRED_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // flexio1 pre div name - divIpFlexio1 clock = (offCDCDR & 0xFF) | (nxp.CCM_CDCDR_FLEXIO1_CLK_PODF_Pos << 8) | (((nxp.CCM_CDCDR_FLEXIO1_CLK_PODF_Msk >> nxp.CCM_CDCDR_FLEXIO1_CLK_PODF_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // flexio1 div name - divIpLpi2c clock = (offCSCDR2 & 0xFF) | (nxp.CCM_CSCDR2_LPI2C_CLK_PODF_Pos << 8) | (((nxp.CCM_CSCDR2_LPI2C_CLK_PODF_Msk >> nxp.CCM_CSCDR2_LPI2C_CLK_PODF_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // lpi2c div name - divIpLcdifPre clock = (offCSCDR2 & 0xFF) | (nxp.CCM_CSCDR2_LCDIF_PRED_Pos << 8) | (((nxp.CCM_CSCDR2_LCDIF_PRED_Msk >> nxp.CCM_CSCDR2_LCDIF_PRED_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // lcdif pre div name - divIpCsi clock = (offCSCDR3 & 0xFF) | (nxp.CCM_CSCDR3_CSI_PODF_Pos << 8) | (((nxp.CCM_CSCDR3_CSI_PODF_Msk >> nxp.CCM_CSCDR3_CSI_PODF_Pos) & 0x1FFF) << 13) | (noBusyWait << 26) // csi div name -) - -// USB clock source -const ( - usbSrc480M = 0 // Use 480M - usbSrcUnused = 0xFFFFFFFF // Used when the function does not care the clock source -) - -// Source of the USB HS PHY -const ( - usbhsPhy480M = 0 // Use 480M -) - -// PLL clock source, bypass cloco source also -const ( - pllSrc24M = 0 // Pll clock source 24M - pllSrcClkPN = 1 // Pll clock source CLK1_P and CLK1_N -) - -// PLL configuration for ARM -type clockConfigArmPll struct { - loopDivider uint32 // PLL loop divider. Valid range for divider value: 54-108. Fout=Fin*loopDivider/2. - src uint8 // Pll clock source, reference _clock_pll_clk_src -} - -func (cfg clockConfigArmPll) configure() { - - // bypass PLL first - src := (uint32(cfg.src) << nxp.CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_Pos) & nxp.CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_Msk - nxp.CCM_ANALOG.PLL_ARM.Set( - (nxp.CCM_ANALOG.PLL_ARM.Get() & ^uint32(nxp.CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_Msk)) | - nxp.CCM_ANALOG_PLL_ARM_BYPASS_Msk | src) - - sel := (cfg.loopDivider << nxp.CCM_ANALOG_PLL_ARM_DIV_SELECT_Pos) & nxp.CCM_ANALOG_PLL_ARM_DIV_SELECT_Msk - nxp.CCM_ANALOG.PLL_ARM.Set( - (nxp.CCM_ANALOG.PLL_ARM.Get() & ^uint32(nxp.CCM_ANALOG_PLL_ARM_DIV_SELECT_Msk|nxp.CCM_ANALOG_PLL_ARM_POWERDOWN_Msk)) | - nxp.CCM_ANALOG_PLL_ARM_ENABLE_Msk | sel) - - for !nxp.CCM_ANALOG.PLL_ARM.HasBits(nxp.CCM_ANALOG_PLL_ARM_LOCK_Msk) { - } - - // disable bypass - nxp.CCM_ANALOG.PLL_ARM.ClearBits(nxp.CCM_ANALOG_PLL_ARM_BYPASS_Msk) -} - -// PLL configuration for System -type clockConfigSysPll struct { - loopDivider uint8 // PLL loop divider. Intended to be 1 (528M): 0 - Fout=Fref*20, 1 - Fout=Fref*22 - numerator uint32 // 30 bit numerator of fractional loop divider. - denominator uint32 // 30 bit denominator of fractional loop divider - src uint8 // Pll clock source, reference _clock_pll_clk_src - ssStop uint16 // Stop value to get frequency change. - ssEnable uint8 // Enable spread spectrum modulation - ssStep uint16 // Step value to get frequency change step. -} - -func (cfg clockConfigSysPll) configure(pfd ...uint32) { - - // bypass PLL first - src := (uint32(cfg.src) << nxp.CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_Pos) & nxp.CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_Msk - nxp.CCM_ANALOG.PLL_SYS.Set( - (nxp.CCM_ANALOG.PLL_SYS.Get() & ^uint32(nxp.CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_Msk)) | - nxp.CCM_ANALOG_PLL_SYS_BYPASS_Msk | src) - - sel := (uint32(cfg.loopDivider) << nxp.CCM_ANALOG_PLL_SYS_DIV_SELECT_Pos) & nxp.CCM_ANALOG_PLL_SYS_DIV_SELECT_Msk - nxp.CCM_ANALOG.PLL_SYS.Set( - (nxp.CCM_ANALOG.PLL_SYS.Get() & ^uint32(nxp.CCM_ANALOG_PLL_SYS_DIV_SELECT_Msk|nxp.CCM_ANALOG_PLL_SYS_POWERDOWN_Msk)) | - nxp.CCM_ANALOG_PLL_SYS_ENABLE_Msk | sel) - - // initialize the fractional mode - nxp.CCM_ANALOG.PLL_SYS_NUM.Set((cfg.numerator << nxp.CCM_ANALOG_PLL_SYS_NUM_A_Pos) & nxp.CCM_ANALOG_PLL_SYS_NUM_A_Msk) - nxp.CCM_ANALOG.PLL_SYS_DENOM.Set((cfg.denominator << nxp.CCM_ANALOG_PLL_SYS_DENOM_B_Pos) & nxp.CCM_ANALOG_PLL_SYS_DENOM_B_Msk) - - // initialize the spread spectrum mode - inc := (uint32(cfg.ssStep) << nxp.CCM_ANALOG_PLL_SYS_SS_STEP_Pos) & nxp.CCM_ANALOG_PLL_SYS_SS_STEP_Msk - enb := (uint32(cfg.ssEnable) << nxp.CCM_ANALOG_PLL_SYS_SS_ENABLE_Pos) & nxp.CCM_ANALOG_PLL_SYS_SS_ENABLE_Msk - stp := (uint32(cfg.ssStop) << nxp.CCM_ANALOG_PLL_SYS_SS_STOP_Pos) & nxp.CCM_ANALOG_PLL_SYS_SS_STOP_Msk - nxp.CCM_ANALOG.PLL_SYS_SS.Set(inc | enb | stp) - - for !nxp.CCM_ANALOG.PLL_SYS.HasBits(nxp.CCM_ANALOG_PLL_SYS_LOCK_Msk) { - } - - // disable bypass - nxp.CCM_ANALOG.PLL_SYS.ClearBits(nxp.CCM_ANALOG_PLL_SYS_BYPASS_Msk) - - // update PFDs after update - setSysPfd(pfd...) -} - -// PLL configuration for USB -type clockConfigUsbPll struct { - instance uint8 // USB PLL number (1 or 2) - loopDivider uint8 // PLL loop divider: 0 - Fout=Fref*20, 1 - Fout=Fref*22 - src uint8 // Pll clock source, reference _clock_pll_clk_src -} - -func (cfg clockConfigUsbPll) configure(pfd ...uint32) { - - switch cfg.instance { - case 1: - - // bypass PLL first - src := (uint32(cfg.src) << nxp.CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_Pos) & nxp.CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_Msk - nxp.CCM_ANALOG.PLL_USB1.Set( - (nxp.CCM_ANALOG.PLL_USB1.Get() & ^uint32(nxp.CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_Msk)) | - nxp.CCM_ANALOG_PLL_USB1_BYPASS_Msk | src) - - sel := uint32((cfg.loopDivider << nxp.CCM_ANALOG_PLL_USB1_DIV_SELECT_Pos) & nxp.CCM_ANALOG_PLL_USB1_DIV_SELECT_Msk) - nxp.CCM_ANALOG.PLL_USB1_SET.Set( - (nxp.CCM_ANALOG.PLL_USB1.Get() & ^uint32(nxp.CCM_ANALOG_PLL_USB1_DIV_SELECT_Msk)) | - nxp.CCM_ANALOG_PLL_USB1_ENABLE_Msk | nxp.CCM_ANALOG_PLL_USB1_POWER_Msk | - nxp.CCM_ANALOG_PLL_USB1_EN_USB_CLKS_Msk | sel) - - for !nxp.CCM_ANALOG.PLL_USB1.HasBits(nxp.CCM_ANALOG_PLL_USB1_LOCK_Msk) { - } - - // disable bypass - nxp.CCM_ANALOG.PLL_USB1_CLR.Set(nxp.CCM_ANALOG_PLL_USB1_BYPASS_Msk) - - // update PFDs after update - setUsb1Pfd(pfd...) - - case 2: - // bypass PLL first - src := (uint32(cfg.src) << nxp.CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_Pos) & nxp.CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_Msk - nxp.CCM_ANALOG.PLL_USB2.Set( - (nxp.CCM_ANALOG.PLL_USB2.Get() & ^uint32(nxp.CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_Msk)) | - nxp.CCM_ANALOG_PLL_USB2_BYPASS_Msk | src) - - sel := uint32((cfg.loopDivider << nxp.CCM_ANALOG_PLL_USB2_DIV_SELECT_Pos) & nxp.CCM_ANALOG_PLL_USB2_DIV_SELECT_Msk) - nxp.CCM_ANALOG.PLL_USB2.Set( - (nxp.CCM_ANALOG.PLL_USB2.Get() & ^uint32(nxp.CCM_ANALOG_PLL_USB2_DIV_SELECT_Msk)) | - nxp.CCM_ANALOG_PLL_USB2_ENABLE_Msk | nxp.CCM_ANALOG_PLL_USB2_POWER_Msk | - nxp.CCM_ANALOG_PLL_USB2_EN_USB_CLKS_Msk | sel) - - for !nxp.CCM_ANALOG.PLL_USB2.HasBits(nxp.CCM_ANALOG_PLL_USB2_LOCK_Msk) { - } - - // disable bypass - nxp.CCM_ANALOG.PLL_USB2.ClearBits(nxp.CCM_ANALOG_PLL_USB2_BYPASS_Msk) - - default: - panic("runtime: invalid USB PLL") - } -} - -// PLL configuration for AUDIO -type clockConfigAudioPll struct { - loopDivider uint8 // PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. - postDivider uint8 // Divider after the PLL, should only be 1, 2, 4, 8, 16. - numerator uint32 // 30 bit numerator of fractional loop divider. - denominator uint32 // 30 bit denominator of fractional loop divider - src uint8 // Pll clock source, reference _clock_pll_clk_src -} - -// PLL configuration for VIDEO -type clockConfigVideoPll struct { - loopDivider uint8 // PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. - postDivider uint8 // Divider after the PLL, should only be 1, 2, 4, 8, 16. - numerator uint32 // 30 bit numerator of fractional loop divider. - denominator uint32 // 30 bit denominator of fractional loop divider - src uint8 // Pll clock source, reference _clock_pll_clk_src -} - -// PLL configuration for ENET -type clockConfigEnetPll struct { - enableClkOutput bool // Power on and enable PLL clock output for ENET0. - enableClkOutput25M bool // Power on and enable PLL clock output for ENET2. - loopDivider uint8 // Controls the frequency of the ENET0 reference clock: b00=25MHz, b01=50MHz, b10=100MHz (not 50% duty cycle), b11=125MHz - src uint8 // Pll clock source, reference _clock_pll_clk_src - enableClkOutput1 bool // Power on and enable PLL clock output for ENET1. - loopDivider1 uint8 // Controls the frequency of the ENET1 reference clock: b00 25MHz, b01 50MHz, b10 100MHz (not 50% duty cycle), b11 125MHz -} - -// PLL name -const ( - clkPllArm clock = ((offPllArm & 0xFFF) << 16) | nxp.CCM_ANALOG_PLL_ARM_ENABLE_Pos // PLL ARM - clkPllSys clock = ((offPllSys & 0xFFF) << 16) | nxp.CCM_ANALOG_PLL_SYS_ENABLE_Pos // PLL SYS - clkPllUsb1 clock = ((offPllUsb1 & 0xFFF) << 16) | nxp.CCM_ANALOG_PLL_USB1_ENABLE_Pos // PLL USB1 - clkPllAudio clock = ((offPllAudio & 0xFFF) << 16) | nxp.CCM_ANALOG_PLL_AUDIO_ENABLE_Pos // PLL Audio - clkPllVideo clock = ((offPllVideo & 0xFFF) << 16) | nxp.CCM_ANALOG_PLL_VIDEO_ENABLE_Pos // PLL Video - clkPllEnet clock = ((offPllEnet & 0xFFF) << 16) | nxp.CCM_ANALOG_PLL_ENET_ENABLE_Pos // PLL Enet0 - clkPllEnet2 clock = ((offPllEnet & 0xFFF) << 16) | nxp.CCM_ANALOG_PLL_ENET_ENET2_REF_EN_Pos // PLL Enet1 - clkPllEnet25M clock = ((offPllEnet & 0xFFF) << 16) | nxp.CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_Pos // PLL Enet2 - clkPllUsb2 clock = ((offPllUsb2 & 0xFFF) << 16) | nxp.CCM_ANALOG_PLL_USB2_ENABLE_Pos // PLL USB2 -) - -// PLL PFD name -const ( - clkPfd0 clock = 0 // PLL PFD0 - clkPfd1 clock = 1 // PLL PFD1 - clkPfd2 clock = 2 // PLL PFD2 - clkPfd3 clock = 3 // PLL PFD3 -) - -var ( - armPllConfig = clockConfigArmPll{ - loopDivider: 100, // PLL loop divider, Fout = Fin * 50 - src: 0, // Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N - } - sysPllConfig = clockConfigSysPll{ - loopDivider: 1, // PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) - numerator: 0, // 30 bit numerator of fractional loop divider - denominator: 1, // 30 bit denominator of fractional loop divider - src: 0, // Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N - } - usb1PllConfig = clockConfigUsbPll{ - instance: 1, // USB PLL instance - loopDivider: 0, // PLL loop divider, Fout = Fin * 20 - src: 0, // Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N - } - usb2PllConfig = clockConfigUsbPll{ - instance: 2, // USB PLL instance - loopDivider: 0, // PLL loop divider, Fout = Fin * 20 - src: 0, // Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N - } - videoPllConfig = clockConfigVideoPll{ - loopDivider: 31, // PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) - postDivider: 8, // Divider after PLL - numerator: 0, // 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) - denominator: 1, // 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) - src: 0, // Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N - } -) diff --git a/src/runtime/runtime_mimxrt1062_mpu.go b/src/runtime/runtime_mimxrt1062_mpu.go index c71bb67a..58297047 100644 --- a/src/runtime/runtime_mimxrt1062_mpu.go +++ b/src/runtime/runtime_mimxrt1062_mpu.go @@ -3,35 +3,12 @@ package runtime import ( - "device/arm" "device/nxp" - "runtime/volatile" - "unsafe" ) -type MPU_Type struct { - TYPE volatile.Register32 // 0x000 (R/ ) - MPU Type Register - CTRL volatile.Register32 // 0x004 (R/W) - MPU Control Register - RNR volatile.Register32 // 0x008 (R/W) - MPU Region RNRber Register - RBAR volatile.Register32 // 0x00C (R/W) - MPU Region Base Address Register - RASR volatile.Register32 // 0x010 (R/W) - MPU Region Attribute and Size Register - RBAR_A1 volatile.Register32 // 0x014 (R/W) - MPU Alias 1 Region Base Address Register - RASR_A1 volatile.Register32 // 0x018 (R/W) - MPU Alias 1 Region Attribute and Size Register - RBAR_A2 volatile.Register32 // 0x01C (R/W) - MPU Alias 2 Region Base Address Register - RASR_A2 volatile.Register32 // 0x020 (R/W) - MPU Alias 2 Region Attribute and Size Register - RBAR_A3 volatile.Register32 // 0x024 (R/W) - MPU Alias 3 Region Base Address Register - RASR_A3 volatile.Register32 // 0x028 (R/W) - MPU Alias 3 Region Attribute and Size Register -} - -var MPU = (*MPU_Type)(unsafe.Pointer(uintptr(0xe000ed90))) - func initCache() { - MPU.initialize() -} -func (mpu *MPU_Type) initialize() { - - mpu.enable(false) + nxp.MPU.Enable(false) // -------------------------------------------------------- OVERLAY REGIONS -- @@ -40,310 +17,45 @@ func (mpu *MPU_Type) initialize() { // [0] Default {OVERLAY}: // 4 GiB, -access, @device, -exec, -share, -cache, -buffer, -subregion - mpu.setRBAR(0, 0x00000000) - mpu.setRASR(rs4GB, apNone, exDevice, false, false, false, false, false) + nxp.MPU.SetRBAR(0, 0x00000000) + nxp.MPU.SetRASR(nxp.RGNSZ_4GB, nxp.PERM_NONE, nxp.EXTN_DEVICE, false, false, false, false, false) // [1] Peripherals {OVERLAY}: // 64 MiB, +ACCESS, @device, +EXEC, -share, -cache, -buffer, -subregion - mpu.setRBAR(1, 0x40000000) - mpu.setRASR(rs64MB, apFull, exDevice, true, false, false, false, false) + nxp.MPU.SetRBAR(1, 0x40000000) + nxp.MPU.SetRASR(nxp.RGNSZ_64MB, nxp.PERM_FULL, nxp.EXTN_DEVICE, true, false, false, false, false) // [2] RAM {OVERLAY}: // 1 GiB, +ACCESS, @device, +EXEC, -share, -cache, -buffer, -subregion - mpu.setRBAR(2, 0x00000000) - mpu.setRASR(rs1GB, apFull, exDevice, true, false, false, false, false) + nxp.MPU.SetRBAR(2, 0x00000000) + nxp.MPU.SetRASR(nxp.RGNSZ_1GB, nxp.PERM_FULL, nxp.EXTN_DEVICE, true, false, false, false, false) // ----------------------------------------------------- PERIPHERAL REGIONS -- // [3] ITCM: // 512 KiB, +ACCESS, #NORMAL, +EXEC, -share, -cache, -buffer, -subregion - mpu.setRBAR(3, 0x00000000) - mpu.setRASR(rs512KB, apFull, exNormal, true, false, false, false, false) + nxp.MPU.SetRBAR(3, 0x00000000) + nxp.MPU.SetRASR(nxp.RGNSZ_512KB, nxp.PERM_FULL, nxp.EXTN_NORMAL, true, false, false, false, false) // [4] DTCM: // 512 KiB, +ACCESS, #NORMAL, +EXEC, -share, -cache, -buffer, -subregion - mpu.setRBAR(4, 0x20000000) - mpu.setRASR(rs512KB, apFull, exNormal, true, false, false, false, false) + nxp.MPU.SetRBAR(4, 0x20000000) + nxp.MPU.SetRASR(nxp.RGNSZ_512KB, nxp.PERM_FULL, nxp.EXTN_NORMAL, true, false, false, false, false) // [5] RAM (AXI): // 512 KiB, +ACCESS, #NORMAL, +EXEC, -share, +CACHE, +BUFFER, -subregion - mpu.setRBAR(5, 0x20200000) - mpu.setRASR(rs512KB, apFull, exNormal, true, false, true, true, false) + nxp.MPU.SetRBAR(5, 0x20200000) + nxp.MPU.SetRASR(nxp.RGNSZ_512KB, nxp.PERM_FULL, nxp.EXTN_NORMAL, true, false, true, true, false) // [6] FlexSPI: // 512 MiB, +ACCESS, #NORMAL, +EXEC, -share, +CACHE, +BUFFER, -subregion - mpu.setRBAR(6, 0x70000000) - mpu.setRASR(rs512MB, apFull, exNormal, true, false, true, true, false) + nxp.MPU.SetRBAR(6, 0x70000000) + nxp.MPU.SetRASR(nxp.RGNSZ_512MB, nxp.PERM_FULL, nxp.EXTN_NORMAL, true, false, true, true, false) // [7] QSPI flash: // 2 MiB, +ACCESS, #NORMAL, +EXEC, -share, +CACHE, +BUFFER, -subregion - mpu.setRBAR(7, 0x60000000) - mpu.setRASR(rs2MB, apFull, exNormal, true, false, true, true, false) + nxp.MPU.SetRBAR(7, 0x60000000) + nxp.MPU.SetRASR(nxp.RGNSZ_2MB, nxp.PERM_FULL, nxp.EXTN_NORMAL, true, false, true, true, false) - mpu.enable(true) -} - -// MPU Type Register Definitions -const ( - MPU_TYPE_IREGION_Pos = 16 // MPU TYPE: IREGION Position - MPU_TYPE_IREGION_Msk = 0xFF << MPU_TYPE_IREGION_Pos // MPU TYPE: IREGION Mask - MPU_TYPE_DREGION_Pos = 8 // MPU TYPE: DREGION Position - MPU_TYPE_DREGION_Msk = 0xFF << MPU_TYPE_DREGION_Pos // MPU TYPE: DREGION Mask - MPU_TYPE_SEPARATE_Pos = 0 // MPU TYPE: SEPARATE Position - MPU_TYPE_SEPARATE_Msk = 1 // MPU TYPE: SEPARATE Mask -) - -// MPU Control Register Definitions -const ( - MPU_CTRL_PRIVDEFENA_Pos = 2 // MPU CTRL: PRIVDEFENA Position - MPU_CTRL_PRIVDEFENA_Msk = 1 << MPU_CTRL_PRIVDEFENA_Pos // MPU CTRL: PRIVDEFENA Mask - MPU_CTRL_HFNMIENA_Pos = 1 // MPU CTRL: HFNMIENA Position - MPU_CTRL_HFNMIENA_Msk = 1 << MPU_CTRL_HFNMIENA_Pos // MPU CTRL: HFNMIENA Mask - MPU_CTRL_ENABLE_Pos = 0 // MPU CTRL: ENABLE Position - MPU_CTRL_ENABLE_Msk = 1 // MPU CTRL: ENABLE Mask -) - -// MPU Region Number Register Definitions -const ( - MPU_RNR_REGION_Pos = 0 // MPU RNR: REGION Position - MPU_RNR_REGION_Msk = 0xFF // MPU RNR: REGION Mask -) - -// MPU Region Base Address Register Definitions -const ( - MPU_RBAR_ADDR_Pos = 5 // MPU RBAR: ADDR Position - MPU_RBAR_ADDR_Msk = 0x7FFFFFF << MPU_RBAR_ADDR_Pos // MPU RBAR: ADDR Mask - MPU_RBAR_VALID_Pos = 4 // MPU RBAR: VALID Position - MPU_RBAR_VALID_Msk = 1 << MPU_RBAR_VALID_Pos // MPU RBAR: VALID Mask - MPU_RBAR_REGION_Pos = 0 // MPU RBAR: REGION Position - MPU_RBAR_REGION_Msk = 0xF // MPU RBAR: REGION Mask -) - -// MPU Region Attribute and Size Register Definitions -const ( - MPU_RASR_ATTRS_Pos = 16 // MPU RASR: MPU Region Attribute field Position - MPU_RASR_ATTRS_Msk = 0xFFFF << MPU_RASR_ATTRS_Pos // MPU RASR: MPU Region Attribute field Mask - MPU_RASR_XN_Pos = 28 // MPU RASR: ATTRS.XN Position - MPU_RASR_XN_Msk = 1 << MPU_RASR_XN_Pos // MPU RASR: ATTRS.XN Mask - MPU_RASR_AP_Pos = 24 // MPU RASR: ATTRS.AP Position - MPU_RASR_AP_Msk = 0x7 << MPU_RASR_AP_Pos // MPU RASR: ATTRS.AP Mask - MPU_RASR_TEX_Pos = 19 // MPU RASR: ATTRS.TEX Position - MPU_RASR_TEX_Msk = 0x7 << MPU_RASR_TEX_Pos // MPU RASR: ATTRS.TEX Mask - MPU_RASR_S_Pos = 18 // MPU RASR: ATTRS.S Position - MPU_RASR_S_Msk = 1 << MPU_RASR_S_Pos // MPU RASR: ATTRS.S Mask - MPU_RASR_C_Pos = 17 // MPU RASR: ATTRS.C Position - MPU_RASR_C_Msk = 1 << MPU_RASR_C_Pos // MPU RASR: ATTRS.C Mask - MPU_RASR_B_Pos = 16 // MPU RASR: ATTRS.B Position - MPU_RASR_B_Msk = 1 << MPU_RASR_B_Pos // MPU RASR: ATTRS.B Mask - MPU_RASR_SRD_Pos = 8 // MPU RASR: Sub-Region Disable Position - MPU_RASR_SRD_Msk = 0xFF << MPU_RASR_SRD_Pos // MPU RASR: Sub-Region Disable Mask - MPU_RASR_SIZE_Pos = 1 // MPU RASR: Region Size Field Position - MPU_RASR_SIZE_Msk = 0x1F << MPU_RASR_SIZE_Pos // MPU RASR: Region Size Field Mask - MPU_RASR_ENABLE_Pos = 0 // MPU RASR: Region enable bit Position - MPU_RASR_ENABLE_Msk = 1 // MPU RASR: Region enable bit Disable Mask -) - -const ( - SCB_DCISW_WAY_Pos = 30 // SCB DCISW: Way Position - SCB_DCISW_WAY_Msk = 3 << SCB_DCISW_WAY_Pos // SCB DCISW: Way Mask - SCB_DCISW_SET_Pos = 5 // SCB DCISW: Set Position - SCB_DCISW_SET_Msk = 0x1FF << SCB_DCISW_SET_Pos // SCB DCISW: Set Mask -) - -const ( - SCB_DCCISW_WAY_Pos = 30 // SCB DCCISW: Way Position - SCB_DCCISW_WAY_Msk = 3 << SCB_DCCISW_WAY_Pos // SCB DCCISW: Way Mask - SCB_DCCISW_SET_Pos = 5 // SCB DCCISW: Set Position - SCB_DCCISW_SET_Msk = 0x1FF << SCB_DCCISW_SET_Pos // SCB DCCISW: Set Mask -) - -type regionSize uint32 - -const ( - rs32B regionSize = 0x04 // MPU Region Size 32 Bytes - rs64B regionSize = 0x05 // MPU Region Size 64 Bytes - rs128B regionSize = 0x06 // MPU Region Size 128 Bytes - rs256B regionSize = 0x07 // MPU Region Size 256 Bytes - rs512B regionSize = 0x08 // MPU Region Size 512 Bytes - rs1KB regionSize = 0x09 // MPU Region Size 1 KByte - rs2KB regionSize = 0x0A // MPU Region Size 2 KBytes - rs4KB regionSize = 0x0B // MPU Region Size 4 KBytes - rs8KB regionSize = 0x0C // MPU Region Size 8 KBytes - rs16KB regionSize = 0x0D // MPU Region Size 16 KBytes - rs32KB regionSize = 0x0E // MPU Region Size 32 KBytes - rs64KB regionSize = 0x0F // MPU Region Size 64 KBytes - rs128KB regionSize = 0x10 // MPU Region Size 128 KBytes - rs256KB regionSize = 0x11 // MPU Region Size 256 KBytes - rs512KB regionSize = 0x12 // MPU Region Size 512 KBytes - rs1MB regionSize = 0x13 // MPU Region Size 1 MByte - rs2MB regionSize = 0x14 // MPU Region Size 2 MBytes - rs4MB regionSize = 0x15 // MPU Region Size 4 MBytes - rs8MB regionSize = 0x16 // MPU Region Size 8 MBytes - rs16MB regionSize = 0x17 // MPU Region Size 16 MBytes - rs32MB regionSize = 0x18 // MPU Region Size 32 MBytes - rs64MB regionSize = 0x19 // MPU Region Size 64 MBytes - rs128MB regionSize = 0x1A // MPU Region Size 128 MBytes - rs256MB regionSize = 0x1B // MPU Region Size 256 MBytes - rs512MB regionSize = 0x1C // MPU Region Size 512 MBytes - rs1GB regionSize = 0x1D // MPU Region Size 1 GByte - rs2GB regionSize = 0x1E // MPU Region Size 2 GBytes - rs4GB regionSize = 0x1F // MPU Region Size 4 GBytes -) - -type accessPerms uint32 - -const ( - apNone accessPerms = 0 // MPU Access Permission no access - apPriv accessPerms = 1 // MPU Access Permission privileged access only - apURO accessPerms = 2 // MPU Access Permission unprivileged access read-only - apFull accessPerms = 3 // MPU Access Permission full access - apPRO accessPerms = 5 // MPU Access Permission privileged access read-only - apRO accessPerms = 6 // MPU Access Permission read-only access -) - -type extension uint32 - -const ( - exNormal extension = 0 - exDevice extension = 2 -) - -func (mpu *MPU_Type) enable(enable bool) { - if enable { - mpu.CTRL.Set(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_ENABLE_Msk) - nxp.SystemControl.SHCSR.SetBits(nxp.SCB_SHCSR_MEMFAULTENA_Msk) - arm.AsmFull(` - dsb 0xF - isb 0xF - `, nil) - enableDcache(true) - enableIcache(true) - } else { - enableIcache(false) - enableDcache(false) - arm.AsmFull(` - dmb 0xF - `, nil) - nxp.SystemControl.SHCSR.ClearBits(nxp.SCB_SHCSR_MEMFAULTENA_Msk) - mpu.CTRL.ClearBits(MPU_CTRL_ENABLE_Msk) - } -} - -// MPU Region Base Address Register value -func (mpu *MPU_Type) setRBAR(region uint32, baseAddress uint32) { - mpu.RBAR.Set((baseAddress & MPU_RBAR_ADDR_Msk) | - (region & MPU_RBAR_REGION_Msk) | MPU_RBAR_VALID_Msk) -} - -// MPU Region Attribute and Size Register value -func (mpu *MPU_Type) setRASR(size regionSize, access accessPerms, ext extension, exec, share, cache, buffer, disable bool) { - boolBit := func(b bool) uint32 { - if b { - return 1 - } - return 0 - } - attr := ((uint32(ext) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | - ((boolBit(share) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | - ((boolBit(cache) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | - ((boolBit(buffer) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) - mpu.RASR.Set(((boolBit(!exec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | - ((uint32(access) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | - (attr & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)) | - ((boolBit(disable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | - ((uint32(size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | - MPU_RASR_ENABLE_Msk) -} - -func enableIcache(enable bool) { - if enable != nxp.SystemControl.CCR.HasBits(nxp.SCB_CCR_IC_Msk) { - if enable { - arm.AsmFull(` - dsb 0xF - isb 0xF - `, nil) - nxp.SystemControl.ICIALLU.Set(0) - arm.AsmFull(` - dsb 0xF - isb 0xF - `, nil) - nxp.SystemControl.CCR.SetBits(nxp.SCB_CCR_IC_Msk) - arm.AsmFull(` - dsb 0xF - isb 0xF - `, nil) - } else { - arm.AsmFull(` - dsb 0xF - isb 0xF - `, nil) - nxp.SystemControl.CCR.ClearBits(nxp.SCB_CCR_IC_Msk) - nxp.SystemControl.ICIALLU.Set(0) - arm.AsmFull(` - dsb 0xF - isb 0xF - `, nil) - } - } -} - -func enableDcache(enable bool) { - if enable != nxp.SystemControl.CCR.HasBits(nxp.SCB_CCR_DC_Msk) { - if enable { - nxp.SystemControl.CSSELR.Set(0) - arm.AsmFull(` - dsb 0xF - `, nil) - ccsidr := nxp.SystemControl.CCSIDR.Get() - sets := (ccsidr & nxp.SCB_CCSIDR_NUMSETS_Msk) >> nxp.SCB_CCSIDR_NUMSETS_Pos - for sets != 0 { - ways := (ccsidr & nxp.SCB_CCSIDR_ASSOCIATIVITY_Msk) >> nxp.SCB_CCSIDR_ASSOCIATIVITY_Pos - for ways != 0 { - nxp.SystemControl.DCISW.Set( - ((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)) - ways-- - } - sets-- - } - arm.AsmFull(` - dsb 0xF - `, nil) - nxp.SystemControl.CCR.SetBits(nxp.SCB_CCR_DC_Msk) - arm.AsmFull(` - dsb 0xF - isb 0xF - `, nil) - } else { - var ( - ccsidr volatile.Register32 - sets volatile.Register32 - ways volatile.Register32 - ) - nxp.SystemControl.CSSELR.Set(0) - arm.AsmFull(` - dsb 0xF - `, nil) - nxp.SystemControl.CCR.ClearBits(nxp.SCB_CCR_DC_Msk) - arm.AsmFull(` - dsb 0xF - `, nil) - ccsidr.Set(nxp.SystemControl.CCSIDR.Get()) - sets.Set((ccsidr.Get() & nxp.SCB_CCSIDR_NUMSETS_Msk) >> nxp.SCB_CCSIDR_NUMSETS_Pos) - for sets.Get() != 0 { - ways.Set((ccsidr.Get() & nxp.SCB_CCSIDR_ASSOCIATIVITY_Msk) >> nxp.SCB_CCSIDR_ASSOCIATIVITY_Pos) - for ways.Get() != 0 { - nxp.SystemControl.DCCISW.Set( - ((sets.Get() << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways.Get() << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)) - ways.Set(ways.Get() - 1) - } - sets.Set(sets.Get() - 1) - } - arm.AsmFull(` - dsb 0xF - isb 0xF - `, nil) - } - } + nxp.MPU.Enable(true) }