Граф коммитов

8 коммитов

Автор SHA1 Сообщение Дата
Ayke van Laethem
c7413837aa riscv: align the heap to 16 bytes
This may be expected by the ABI. In particular, it means that stacks
allocated on the heap will be 16-byte aligned.
2021-10-05 05:52:03 +02:00
Yannis Huber
0b94e486c1 maixbit: changes according to feedback 2020-07-08 00:21:59 +02:00
Yannis Huber
75bcbbe6d8 riscv: align stack and data sections to 8 bytes
Alignment on 4 bytes can cause load/store address misalignment
exceptions when loading/storing 64bit values on the stack.
2020-07-08 00:21:59 +02:00
Ayke van Laethem
b9cdfd9e9a riscv: add bare-bones interrupt support
This commit adds support for timer interrupts, replacing the busy loop
that was used before. It is perhaps the most simple interrupt to
implement and should serve as the basis for further interrupt support in
RISC-V.
2020-01-10 08:04:13 +01:00
Ayke van Laethem
d441f0152f riscv: use LLVM tools instead of GNU toolchain
Now that we use LLVM 9, RISC-V support in LLVM has far fewer bugs and we
can avoid the GNU toolchain.

  * replace GNU linker with lld
  * replace GCC with clang

Additionally, RISC-V was promoted to stable so it can be enabled by
default in CI.
2019-12-07 16:27:10 +01:00
Ayke van Laethem
2f932a9eee riscv: fix heap corruption
The .sdata and .sbss sections are created by the compiler, but were not
present in the linker script. That means that the linker put them after
all other data/bss section, which happens to be where the heap also
resides.

This commit adds the .sdata and .sbss sections to the linker script,
which gets the blinky examples to work again on RISC-V.
2019-12-05 20:27:28 +01:00
Ayke van Laethem
c6255e4d0a targets: explicitly mark the stack as NOLOAD
This prevents it from being of type PROGBITS in lld 9, it should always
be NOBITS. It should fix the following error in lld 9:

    ROM segments are non-contiguous
2019-11-12 17:10:13 +01:00
Ayke van Laethem
ffa38b183b all: add HiFive1 rev B board with RISC-V architecture
This page has been a big help in adding support for this new chip:
https://wiki.osdev.org/HiFive-1_Bare_Bones
2019-07-07 14:03:24 +02:00