Ayke van Laethem
af00e218a8
riscv: implement 32-bit atomic operations
...
This is necessary to support the ESP32-C3, which lacks the A (atomic)
extension and thus requires these 32-bit atomic operations.
With this commit, flashing ./testdata/atomic.go to the ESP32-C3 works
correctly and produces the expected output on the serial console.
2021-10-04 21:27:00 +02:00
Yannis Huber
5ff76aacab
runtime: reuse common code between 32 and 64-bit RISC-V
2020-07-08 00:21:59 +02:00
Yannis Huber
dfab1aa717
maixbit (uart): serial is working with echo example
2020-07-08 00:21:59 +02:00
Jaden Weiss
a4f3457747
runtime: make channels work in interrupts
2020-07-04 08:34:39 +02:00
Ayke van Laethem
fed433c046
compiler: add support for atomic operations
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This also implements DisableInterrupts/EnableInterrupts for RISC-V, as
those operations were needed to implement a few libcalls.
2020-05-28 15:11:46 +02:00
Ayke van Laethem
6389e45d99
all: replace ReadRegister with AsmFull inline assembly
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This makes AsmFull more powerful (by supporting return values) and
avoids a compiler builtin.
2020-04-29 18:25:16 +02:00
Ayke van Laethem
ffa38b183b
all: add HiFive1 rev B board with RISC-V architecture
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This page has been a big help in adding support for this new chip:
https://wiki.osdev.org/HiFive-1_Bare_Bones
2019-07-07 14:03:24 +02:00
