Ayke van Laethem
ad022ef23d
riscv: add support for compiler-rt
...
This gets all the tests to compile and many of them to pass. There are
some issues left, but those are probably unrelated to compiler-rt.
2019-12-14 12:48:21 +01:00
Ayke van Laethem
8f9419a35d
targets: add hifive1-qemu for testing RISC-V bare metal in QEMU
...
Most tests don't pass yet, so can't add this test to the standard tests,
yet.
2019-12-07 16:47:40 +01:00
Ayke van Laethem
d441f0152f
riscv: use LLVM tools instead of GNU toolchain
...
Now that we use LLVM 9, RISC-V support in LLVM has far fewer bugs and we
can avoid the GNU toolchain.
* replace GNU linker with lld
* replace GCC with clang
Additionally, RISC-V was promoted to stable so it can be enabled by
default in CI.
2019-12-07 16:27:10 +01:00
Ayke van Laethem
54169c714f
all: use baremetal build tag
...
This simplifies adding more baremetal targets, like a GameBoy Advance,
or baremetal x86 for unikernels.
2019-08-04 17:12:07 +02:00
Ayke van Laethem
ffa38b183b
all: add HiFive1 rev B board with RISC-V architecture
...
This page has been a big help in adding support for this new chip:
https://wiki.osdev.org/HiFive-1_Bare_Bones
2019-07-07 14:03:24 +02:00
