Ayke van Laethem
|
b31d241388
|
riscv: use MSTATUS.MIE bit instead of MIE to disable interrupts
This should behave the same but is compatible with the ESP32-C3 which
lacks the MIE CSR (but does have the MSTATUS CSR).
|
2021-10-04 21:27:00 +02:00 |
|
Ayke van Laethem
|
fed433c046
|
compiler: add support for atomic operations
This also implements DisableInterrupts/EnableInterrupts for RISC-V, as
those operations were needed to implement a few libcalls.
|
2020-05-28 15:11:46 +02:00 |
|
Ayke van Laethem
|
6389e45d99
|
all: replace ReadRegister with AsmFull inline assembly
This makes AsmFull more powerful (by supporting return values) and
avoids a compiler builtin.
|
2020-04-29 18:25:16 +02:00 |
|
Ayke van Laethem
|
ffa38b183b
|
all: add HiFive1 rev B board with RISC-V architecture
This page has been a big help in adding support for this new chip:
https://wiki.osdev.org/HiFive-1_Bare_Bones
|
2019-07-07 14:03:24 +02:00 |
|