Граф коммитов

61 коммит

Автор SHA1 Сообщение Дата
Ayke van Laethem
f79e66ac2e cortexm: disable FPU on Cortex-M4
On some boards the FPU is already enabled on startup, probably as part
of the bootloader. On other chips it was enabled as part of the runtime
startup code. In all these cases, enabling the FPU is currently
unsupported: the automatic stack sizing of goroutines assumes that the
processor won't need to reserve space for FPU registers. Enabling the
FPU therefore can lead to a stack overflow.

This commit either removes the code that enables the FPU, or simply
disables it in startup code. A future change should fully enable the FPU
so that operations on float32 can be performed by the FPU instead of in
software, greatly speeding up such code.
2021-04-24 18:41:40 +02:00
sago35
bd212cc000 atsame54: add initial support for atsame54-xpro 2021-04-15 15:43:37 +02:00
Ayke van Laethem
154c7c691b stm32: use stm32-rs SVDs which are of much higher quality
This commit changes the number of wait states for the stm32f103 chip to
2 instead of 4. This gets it back in line with the datasheet, but it
also has the side effect of breaking I2C. Therefore, another (seemingly
unrelated) change is needed: the i2cTimeout constant must be increased
to a higher value to adjust to the lower flash wait states - presumably
because the lower number of wait states allows the chip to run code
faster.
2021-01-09 21:45:07 +01:00
Ayke van Laethem
ae92ea149c esp32: enable the FPU
This allows working with float32 values, for example it allows
testdata/float.go to work correctly (assuming an Xtensa backend bug is
fixed, see https://github.com/espressif/llvm-project/issues/41).
2020-12-11 12:11:46 +01:00
Ayke van Laethem
caf35cfc41 esp32: implement task based scheduler
This has been a *lot* of work, trying to understand the Xtensa windowed
registers ABI. But in the end I managed to come up with a very simple
implementation that so far seems to work very well.

I tested this with both blinky examples (with blinky2 slightly edited)
and ./testdata/coroutines.go to verify that it actually works.
Most development happened on the ESP32 QEMU fork from Espressif
(https://github.com/espressif/qemu/wiki) but I also verified that it
works on a real ESP32.
2020-12-05 09:02:11 +01:00
ardnew
30bee3afef add better fault identification for Cortex-M3/M33/M4/M7 hardfault handlers, add fault description registers to SCB_Type 2020-11-11 18:34:47 +01:00
ardnew
19a0270303 teensy40: refactor to remove unnecessary code and constants 2020-11-11 18:34:47 +01:00
ardnew
f93b28057a mimxrt1062: move device-specific files to "device/nxp" package 2020-11-11 18:34:47 +01:00
Lucas Teske
c2bfe6bc8d arm64: Add support for system calls (SVC) 2020-10-03 20:07:51 +02:00
Ayke van Laethem
2ce17a1892 esp8266: add support for this chip
Many thanks to cnlohr for the nosdk8266 project:
    https://github.com/cnlohr/nosdk8266
2020-09-09 19:17:11 +02:00
ardnew
7f829fe153
machine/stm32f4: refactor common code and add new build tag stm32f4 (#1332)
* machine/STM32F4: break out STM32F4 machine with new build tag
2020-09-01 11:31:41 +02:00
Ayke van Laethem
3ee47a9c1b esp: add support for the Espressif ESP32 chip
This is only very minimal support. More support (such as tinygo flash,
or peripheral access) should be added in later commits, to keep this one
focused.

Importantly, this commit changes the LLVM repo from llvm/llvm-project to
tinygo-org/llvm-project. This provides a little bit of versioning in
case something changes in the Espressif fork. If we want to upgrade to
LLVM 11 it's easy to switch back to llvm/llvm-project until Espressif
has updated their fork.
2020-08-31 09:02:23 +02:00
deadprogram
83252448b0 device/atsamd51x: add all remaining bitfield values for PCHCTRLm Mapping
Signed-off-by: deadprogram <ron@hybridgroup.com>
2020-08-30 09:27:17 +02:00
deadprogram
222977a642 runtime/atsamd51x: use PCHCTRL_GCLK_SERCOMX_SLOW for setting clocks on all SERCOM ports
Signed-off-by: deadprogram <ron@hybridgroup.com>
2020-08-30 09:27:17 +02:00
deadprogram
58565fa46d machine/atsamd51x,runtime/atsamd51x: fixes needed for full support for all PWM pins. Also adds some useful constants to clarify peripheral clock usage
Signed-off-by: deadprogram <ron@hybridgroup.com>
2020-08-30 09:27:17 +02:00
Ayke van Laethem
a21a039ac7 arm: automatically determine stack sizes
This is a big change that will determine the stack size for many
goroutines automatically. Functions that aren't recursive and don't call
function pointers can in many cases have an automatically determined
worst case stack size. This is useful, as the stack size is usually much
lower than the previous hardcoded default of 1024 bytes: somewhere
around 200-500 bytes is common.

A side effect of this change is that the default stack sizes (including
the stack size for other architectures such as AVR) can now be changed
in the config JSON file, making it tunable per application.
2020-08-27 19:23:22 +02:00
Ayke van Laethem
d606315515 builder: try to determine stack size information at compile time
For now, this is just an extra flag that can be used to print stack
frame information, but this is intended to provide a way to determine
stack sizes for goroutines at compile time in many cases.

Stack sizes are often somewhere around 350 bytes so are in fact not all
that big usually. Once this can be determined at compile time in many
cases, it is possible to use this information when available and as a
result increase the fallback stack size if the size cannot be determined
at compile time. This should reduce stack overflows while at the same
time reducing RAM consumption in many cases.

Interesting output for testdata/channel.go:

    function                                 stack usage (in bytes)
    Reset_Handler                            332
    .Lcommand-line-arguments.fastreceiver    220
    .Lcommand-line-arguments.fastsender      192
    .Lcommand-line-arguments.iterator        192
    .Lcommand-line-arguments.main$1          184
    .Lcommand-line-arguments.main$2          200
    .Lcommand-line-arguments.main$3          200
    .Lcommand-line-arguments.main$4          328
    .Lcommand-line-arguments.receive         176
    .Lcommand-line-arguments.selectDeadlock  72
    .Lcommand-line-arguments.selectNoOp      72
    .Lcommand-line-arguments.send            184
    .Lcommand-line-arguments.sendComplex     192
    .Lcommand-line-arguments.sender          192
    .Lruntime.run$1                          548

This shows that the stack size (if these numbers are correct) can in
fact be determined automatically in many cases, especially for small
goroutines. One of the great things about Go is lightweight goroutines,
and reducing stack sizes is very important to make goroutines
lightweight on microcontrollers.
2020-07-11 14:47:43 +02:00
Ethan Reesor
59218cd784 Working on NXP/Teensy support 2020-07-08 21:58:15 +02:00
Yannis Huber
7ed7e6cb11 risc-v: disable linker relaxations during gp init 2020-07-08 01:58:12 +02:00
Yannis Huber
0b94e486c1 maixbit: changes according to feedback 2020-07-08 00:21:59 +02:00
Yannis Huber
43a66b39cc riscv: refactor assembly files to support RV64 and F extension 2020-07-08 00:21:59 +02:00
Yannis Huber
ccc604d2e0 riscv: fix offset in 64bit scheduler
Also keep common start.S file for 64 and 32 bit architectures.
2020-07-08 00:21:59 +02:00
Yannis Huber
dfab1aa717 maixbit (uart): serial is working with echo example 2020-07-08 00:21:59 +02:00
Jaden Weiss
81c723db1a device/arm: do not mask fault handlers in critical sections 2020-06-22 00:08:14 +02:00
Ayke van Laethem
e2bf7bbb49 device: add new cross-arch Asm and AsmFull functions
This is necessary to avoid a circular dependency between the device/avr
and runtime/interrupts package in the next commit.

It may be worth replacing existing calls like device/arm.Asm to
device.Asm, to have a single place where these are defined.
2020-06-14 14:44:22 -04:00
Ayke van Laethem
fed433c046 compiler: add support for atomic operations
This also implements DisableInterrupts/EnableInterrupts for RISC-V, as
those operations were needed to implement a few libcalls.
2020-05-28 15:11:46 +02:00
Ayke van Laethem
23e88bfb15 arm: allow nesting in DisableInterrupts and EnableInterrupts
This finally fixes a TODO left in the code.
2020-04-29 18:25:16 +02:00
Ayke van Laethem
6389e45d99 all: replace ReadRegister with AsmFull inline assembly
This makes AsmFull more powerful (by supporting return values) and
avoids a compiler builtin.
2020-04-29 18:25:16 +02:00
Ayke van Laethem
b8f5627c9f machine: move errors.New calls to globals
Calling errors.New in an error path causes a heap allocation at an
already unfortunate moment. It is more efficient to create these error
values in globals and return these constant globals. If these errors are
not used (because the related code was optimized out), the globals will
also be optimized out.
2020-04-07 13:24:26 +02:00
GeoffThomas
b4dddfe439 stm32 add SPI for stm32f4 2020-03-25 16:24:19 +01:00
gwtnz
c8a4994feb
stm32f4: refactor GPIO, in prep for adding SPI, I2C, PWM etc 2020-03-07 15:34:42 +01:00
Ayke van Laethem
b9cdfd9e9a riscv: add bare-bones interrupt support
This commit adds support for timer interrupts, replacing the busy loop
that was used before. It is perhaps the most simple interrupt to
implement and should serve as the basis for further interrupt support in
RISC-V.
2020-01-10 08:04:13 +01:00
Ayke van Laethem
360923abbf compiler,riscv: implement CSR operations as intrinsics
CSR operations must be implemented in assembly. The easiest way to
implement them is with some custom intrinsics in the compiler.
2020-01-10 08:04:13 +01:00
Ayke van Laethem
08f01ba3ff riscv: improve startup assembly
Now that we've switched to LLVM 9, we don't need a workaround anymore
for the 'la' pseudo-instruction.
2019-12-24 19:00:22 +01:00
Ayke van Laethem
cf32607306 tools: rewrite gen-device-svd in Go
This should make it more maintainable. Another big advantage that
generation time (including gofmt) is now 3 times faster. No real attempt
at refactoring has been made, that will need to be done at a later time.
2019-12-14 22:27:45 +01:00
Ayke van Laethem
b884db81ea cortexm: move SemihostingCall impl to the right asm file
This is the more correct location. The targets/cortex-m.s file is really
just for qemu, not for Cortex-M in general.
2019-11-01 16:25:41 +01:00
Infinoid
6b1faeb882 device/arm: add system timer registers (#654)
* device/arm: add system timer registers
Add SYST registers and bit definitions to device/arm.
Add a setup function.
Add an example that uses it to blink an LED.
2019-10-24 21:17:06 +02:00
Ron Evans
69aaea44a0 machine/atsamd21: Add support for bootloader reset/programming and correct error in receiving endpoint 0 data for CDC Set Line Coding changes, implementing system reset on switch to 1200 baud connection speed with DTR false.
Signed-off-by: Ron Evans <ron@hybridgroup.com>
2019-09-14 16:18:30 +02:00
Ron Evans
6c1abfe047 device/arm: add support for System Control Block (SCB) registers and SystemReset() function
Signed-off-by: Ron Evans <ron@hybridgroup.com>
2019-09-14 16:18:30 +02:00
Ayke van Laethem
ffa38b183b all: add HiFive1 rev B board with RISC-V architecture
This page has been a big help in adding support for this new chip:
https://wiki.osdev.org/HiFive-1_Bare_Bones
2019-07-07 14:03:24 +02:00
Ayke van Laethem
e67506ee68 arm: update to avoid //go:volatile
This change results in changes to all smoketests for Cortex-M based
chips: they get a bit smaller (32-48 bytes). I'm not sure why but
probably because the inliner made a different inlining decision. There
was a similar effect when files generated from SVD files switched to the
new volatile types so it's probably harmless.
2019-06-06 19:46:49 +02:00
Ayke van Laethem
ba85c82fbb arm: print an error when a HardFault occurs
This is very useful for debugging. It differentiates between a stack
overflow and other errors (because it's easy to see when a stack
overflow occurs) and prints the old stack pointer and program counter if
available.
2019-05-20 11:39:17 +02:00
Ayke van Laethem
714d98354c arm: provide intrinsics to disable/enable interrupts 2019-02-23 18:52:49 +01:00
Ron Evans
dccfae485c
machine/stm32f103xx: support for SPI interface
Signed-off-by: Ron Evans <ron@hybridgroup.com>
2018-12-31 14:59:07 +01:00
Ron Evans
f71e1bcf03
machine/stm32f103xx: implementation of RTC/TIM based timers
Signed-off-by: Ron Evans <ron@hybridgroup.com>
2018-12-31 14:39:05 +01:00
Ron Evans
47b667a4b8
machine/stm32: add support for stm32f103xx UART
Signed-off-by: Ron Evans <ron@hybridgroup.com>
2018-12-18 17:17:18 +01:00
Ayke van Laethem
e42289ce61
arm: add SVCAll with 0 arguments
Some very basic system calls may have no arguments at all.
2018-12-03 20:13:29 +01:00
Ayke van Laethem
99daa7b38f
arm: implement setting interrupt priorities 2018-12-03 13:50:38 +01:00
Ayke van Laethem
d887d645f7
arm: implement SVCall
The SVCall function call is lowered to an inline "svc" instruction. The
first parameter *must* be a constant number.
2018-11-21 17:06:56 +01:00
Ayke van Laethem
27fc397e21
arm: implement arm.ReadRegister
This pseudo-function reads the contents of the specified register, for
example "sp".
2018-11-18 18:40:36 +01:00