f4b4dd8d62
This is based on @Nerzal's #1398 PR, but is a bit of a refactor and expansion to support all the Atmega based chips present in tinygo.
138 строки
2,4 КиБ
Go
138 строки
2,4 КиБ
Go
// +build avr,atmega2560
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package machine
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import (
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"device/avr"
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"runtime/volatile"
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)
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const irq_USART0_RX = avr.IRQ_USART0_RX
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const (
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portA Pin = iota * 8
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portB
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portC
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portD
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portE
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portF
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portG
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portH
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portJ
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portK
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portL
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)
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const (
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PA0 = portA + 0
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PA1 = portA + 1
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PA2 = portA + 2
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PA3 = portA + 3
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PA4 = portA + 4
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PA5 = portA + 5
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PA6 = portA + 6
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PA7 = portA + 7
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PB0 = portB + 0
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PB1 = portB + 1
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PB2 = portB + 2
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PB3 = portB + 3
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PB4 = portB + 4
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PB5 = portB + 5
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PB6 = portB + 6
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PB7 = portB + 7
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PC0 = portC + 0
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PC1 = portC + 1
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PC2 = portC + 2
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PC3 = portC + 3
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PC4 = portC + 4
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PC5 = portC + 5
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PC6 = portC + 6
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PC7 = portC + 7
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PD0 = portD + 0
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PD1 = portD + 1
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PD2 = portD + 2
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PD3 = portD + 3
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PD7 = portD + 7
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PE0 = portE + 0
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PE1 = portE + 1
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PE3 = portE + 3
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PE4 = portE + 4
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PE5 = portE + 5
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PE6 = portE + 6
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PF0 = portF + 0
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PF1 = portF + 1
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PF2 = portF + 2
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PF3 = portF + 3
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PF4 = portF + 4
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PF5 = portF + 5
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PF6 = portF + 6
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PF7 = portF + 7
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PG0 = portG + 0
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PG1 = portG + 1
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PG2 = portG + 2
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PG5 = portG + 5
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PH0 = portH + 0
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PH1 = portH + 1
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PH3 = portH + 3
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PH4 = portH + 4
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PH5 = portH + 5
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PH6 = portH + 6
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PJ0 = portJ + 0
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PJ1 = portJ + 1
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PK0 = portK + 0
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PK1 = portK + 1
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PK2 = portK + 2
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PK3 = portK + 3
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PK4 = portH + 4
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PK5 = portH + 5
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PK6 = portH + 6
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PK7 = portH + 7
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PL0 = portL + 0
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PL1 = portL + 1
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PL2 = portL + 2
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PL3 = portL + 3
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PL4 = portL + 4
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PL5 = portL + 5
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PL6 = portL + 6
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PL7 = portL + 7
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)
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// getPortMask returns the PORTx register and mask for the pin.
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func (p Pin) getPortMask() (*volatile.Register8, uint8) {
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switch {
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case p >= PA0 && p <= PA7:
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return avr.PORTA, 1 << uint8(p-portA)
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case p >= PB0 && p <= PB7:
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return avr.PORTB, 1 << uint8(p-portB)
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case p >= PC0 && p <= PC7:
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return avr.PORTC, 1 << uint8(p-portC)
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case p >= PD0 && p <= PD7:
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return avr.PORTD, 1 << uint8(p-portD)
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case p >= PE0 && p <= PE6:
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return avr.PORTE, 1 << uint8(p-portE)
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case p >= PF0 && p <= PF7:
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return avr.PORTF, 1 << uint8(p-portF)
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case p >= PG0 && p <= PG5:
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return avr.PORTG, 1 << uint8(p-portG)
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case p >= PH0 && p <= PH6:
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return avr.PORTH, 1 << uint8(p-portH)
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case p >= PJ0 && p <= PJ1:
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return avr.PORTJ, 1 << uint8(p-portJ)
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case p >= PK0 && p <= PK7:
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return avr.PORTK, 1 << uint8(p-portK)
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case p >= PL0 && p <= PL7:
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return avr.PORTL, 1 << uint8(p-portL)
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default:
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return avr.PORTA, 255
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}
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}
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// SPI configuration
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var SPI0 = SPI{
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spcr: avr.SPCR,
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spdr: avr.SPDR,
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spsr: avr.SPSR,
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sck: PB1,
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sdo: PB2,
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sdi: PB3,
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cs: PB0}
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