2f1f8fb075
It is always implemented exactly the same way (as an uint8) so there is no reason to implement it in each target separately. This also makes it easier to add some documentation to it.
329 строки
7,6 КиБ
Go
329 строки
7,6 КиБ
Go
// +build fe310
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package machine
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import (
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"device/sifive"
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"runtime/interrupt"
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"unsafe"
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)
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func CPUFrequency() uint32 {
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return 16000000
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}
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const (
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PinInput PinMode = iota
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PinOutput
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PinPWM
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PinSPI
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PinI2C = PinSPI
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)
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// Configure this pin with the given configuration.
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func (p Pin) Configure(config PinConfig) {
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sifive.GPIO0.INPUT_EN.SetBits(1 << uint8(p))
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switch config.Mode {
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case PinOutput:
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sifive.GPIO0.OUTPUT_EN.SetBits(1 << uint8(p))
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case PinPWM:
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sifive.GPIO0.IOF_EN.SetBits(1 << uint8(p))
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sifive.GPIO0.IOF_SEL.SetBits(1 << uint8(p))
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case PinSPI:
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sifive.GPIO0.IOF_EN.SetBits(1 << uint8(p))
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sifive.GPIO0.IOF_SEL.ClearBits(1 << uint8(p))
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}
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}
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// Set the pin to high or low.
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func (p Pin) Set(high bool) {
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if high {
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sifive.GPIO0.PORT.SetBits(1 << uint8(p))
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} else {
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sifive.GPIO0.PORT.ClearBits(1 << uint8(p))
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}
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}
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// Get returns the current value of a GPIO pin.
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func (p Pin) Get() bool {
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val := sifive.GPIO0.VALUE.Get() & (1 << uint8(p))
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return (val > 0)
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}
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type UART struct {
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Bus *sifive.UART_Type
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Buffer *RingBuffer
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}
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var (
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UART0 = UART{Bus: sifive.UART0, Buffer: NewRingBuffer()}
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)
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func (uart UART) Configure(config UARTConfig) {
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// Assuming a 16Mhz Crystal (which is Y1 on the HiFive1), the divisor for a
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// 115200 baud rate is 138.
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sifive.UART0.DIV.Set(138)
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sifive.UART0.TXCTRL.Set(sifive.UART_TXCTRL_ENABLE)
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sifive.UART0.RXCTRL.Set(sifive.UART_RXCTRL_ENABLE)
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sifive.UART0.IE.Set(sifive.UART_IE_RXWM) // enable the receive interrupt (only)
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intr := interrupt.New(sifive.IRQ_UART0, UART0.handleInterrupt)
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intr.SetPriority(5)
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intr.Enable()
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}
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func (uart *UART) handleInterrupt(interrupt.Interrupt) {
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rxdata := uart.Bus.RXDATA.Get()
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c := byte(rxdata)
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if uint32(c) != rxdata {
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// The rxdata has other bits set than just the low 8 bits. This probably
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// means that the 'empty' flag is set, which indicates there is no data
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// to be read and the byte is garbage. Ignore this byte.
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return
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}
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uart.Receive(c)
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}
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func (uart UART) WriteByte(c byte) {
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for sifive.UART0.TXDATA.Get()&sifive.UART_TXDATA_FULL != 0 {
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}
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sifive.UART0.TXDATA.Set(uint32(c))
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}
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// SPI on the FE310. The normal SPI0 is actually a quad-SPI meant for flash, so it is best
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// to use SPI1 or SPI2 port for most applications.
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type SPI struct {
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Bus *sifive.QSPI_Type
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}
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// SPIConfig is used to store config info for SPI.
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type SPIConfig struct {
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Frequency uint32
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SCK Pin
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SDO Pin
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SDI Pin
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LSBFirst bool
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Mode uint8
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}
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// Configure is intended to setup the SPI interface.
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func (spi SPI) Configure(config SPIConfig) error {
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// Use default pins if not set.
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if config.SCK == 0 && config.SDO == 0 && config.SDI == 0 {
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config.SCK = SPI0_SCK_PIN
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config.SDO = SPI0_SDO_PIN
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config.SDI = SPI0_SDI_PIN
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}
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// enable pins for SPI
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config.SCK.Configure(PinConfig{Mode: PinSPI})
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config.SDO.Configure(PinConfig{Mode: PinSPI})
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config.SDI.Configure(PinConfig{Mode: PinSPI})
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// set default frequency
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if config.Frequency == 0 {
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config.Frequency = 4000000 // 4MHz
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}
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// div = (SPI_CFG(dev)->f_sys / (2 * frequency)) - 1;
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div := CPUFrequency()/(2*config.Frequency) - 1
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spi.Bus.DIV.Set(div)
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// set mode
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switch config.Mode {
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case 0:
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spi.Bus.MODE.ClearBits(sifive.QSPI_MODE_PHASE)
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spi.Bus.MODE.ClearBits(sifive.QSPI_MODE_POLARITY)
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case 1:
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spi.Bus.MODE.SetBits(sifive.QSPI_MODE_PHASE)
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spi.Bus.MODE.ClearBits(sifive.QSPI_MODE_POLARITY)
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case 2:
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spi.Bus.MODE.ClearBits(sifive.QSPI_MODE_PHASE)
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spi.Bus.MODE.SetBits(sifive.QSPI_MODE_POLARITY)
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case 3:
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spi.Bus.MODE.SetBits(sifive.QSPI_MODE_PHASE | sifive.QSPI_MODE_POLARITY)
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default: // to mode 0
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spi.Bus.MODE.ClearBits(sifive.QSPI_MODE_PHASE)
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spi.Bus.MODE.ClearBits(sifive.QSPI_MODE_POLARITY)
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}
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// frame length
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spi.Bus.FMT.SetBits(8 << sifive.QSPI_FMT_LENGTH_Pos)
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// Set single line operation, by clearing all bits
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spi.Bus.FMT.ClearBits(sifive.QSPI_FMT_PROTOCOL_Msk)
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// set bit transfer order
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if config.LSBFirst {
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spi.Bus.FMT.SetBits(sifive.QSPI_FMT_ENDIAN)
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} else {
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spi.Bus.FMT.ClearBits(sifive.QSPI_FMT_ENDIAN)
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}
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return nil
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}
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// Transfer writes/reads a single byte using the SPI interface.
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func (spi SPI) Transfer(w byte) (byte, error) {
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// wait for tx ready
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for spi.Bus.TXDATA.HasBits(sifive.QSPI_TXDATA_FULL) {
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}
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// write data
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spi.Bus.TXDATA.Set(uint32(w))
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// wait until receive has data
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data := spi.Bus.RXDATA.Get()
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for data&sifive.QSPI_RXDATA_EMPTY > 0 {
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data = spi.Bus.RXDATA.Get()
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}
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// return data
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return byte(data), nil
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}
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// I2C on the FE310-G002.
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type I2C struct {
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Bus sifive.I2C_Type
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}
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var (
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I2C0 = (*I2C)(unsafe.Pointer(sifive.I2C0))
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)
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// I2CConfig is used to store config info for I2C.
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type I2CConfig struct {
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Frequency uint32
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SCL Pin
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SDA Pin
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}
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// Configure is intended to setup the I2C interface.
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func (i2c *I2C) Configure(config I2CConfig) error {
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var i2cClockFrequency uint32 = 32000000
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if config.Frequency == 0 {
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config.Frequency = TWI_FREQ_100KHZ
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}
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if config.SDA == 0 && config.SCL == 0 {
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config.SDA = I2C0_SDA_PIN
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config.SCL = I2C0_SCL_PIN
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}
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var prescaler = i2cClockFrequency/(5*config.Frequency) - 1
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// disable controller before setting the prescale registers
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i2c.Bus.CTR.ClearBits(sifive.I2C_CTR_EN)
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// set prescaler registers
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i2c.Bus.PRER_LO.Set(uint32(prescaler & 0xff))
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i2c.Bus.PRER_HI.Set(uint32((prescaler >> 8) & 0xff))
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// enable controller
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i2c.Bus.CTR.SetBits(sifive.I2C_CTR_EN)
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config.SDA.Configure(PinConfig{Mode: PinI2C})
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config.SCL.Configure(PinConfig{Mode: PinI2C})
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return nil
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}
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// Tx does a single I2C transaction at the specified address.
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// It clocks out the given address, writes the bytes in w, reads back len(r)
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// bytes and stores them in r, and generates a stop condition on the bus.
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func (i2c *I2C) Tx(addr uint16, w, r []byte) error {
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var err error
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if len(w) != 0 {
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// send start/address for write
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i2c.sendAddress(addr, true)
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// ACK received (0: ACK, 1: NACK)
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if i2c.Bus.CR_SR.HasBits(sifive.I2C_SR_RX_ACK) {
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return errI2CAckExpected
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}
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// write data
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for _, b := range w {
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err = i2c.writeByte(b)
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if err != nil {
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return err
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}
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}
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}
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if len(r) != 0 {
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// send start/address for read
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i2c.sendAddress(addr, false)
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// ACK received (0: ACK, 1: NACK)
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if i2c.Bus.CR_SR.HasBits(sifive.I2C_SR_RX_ACK) {
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return errI2CAckExpected
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}
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// read first byte
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r[0] = i2c.readByte()
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for i := 1; i < len(r); i++ {
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// send an ACK
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i2c.Bus.CR_SR.Set(^uint32(sifive.I2C_CR_ACK))
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// read data and send the ACK
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r[i] = i2c.readByte()
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}
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// send NACK to end transmission
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i2c.Bus.CR_SR.Set(sifive.I2C_CR_ACK)
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}
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// generate stop condition
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i2c.Bus.CR_SR.Set(sifive.I2C_CR_STO)
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return nil
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}
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// Writes a single byte to the I2C bus.
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func (i2c *I2C) writeByte(data byte) error {
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// Send data byte
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i2c.Bus.TXR_RXR.Set(uint32(data))
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i2c.Bus.CR_SR.Set(sifive.I2C_CR_WR)
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// wait until transmission complete
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for i2c.Bus.CR_SR.HasBits(sifive.I2C_SR_TIP) {
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}
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// ACK received (0: ACK, 1: NACK)
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if i2c.Bus.CR_SR.HasBits(sifive.I2C_SR_RX_ACK) {
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return errI2CAckExpected
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}
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return nil
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}
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// Reads a single byte from the I2C bus.
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func (i2c *I2C) readByte() byte {
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i2c.Bus.CR_SR.Set(sifive.I2C_CR_RD)
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// wait until transmission complete
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for i2c.Bus.CR_SR.HasBits(sifive.I2C_SR_TIP) {
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}
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return byte(i2c.Bus.TXR_RXR.Get())
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}
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// Sends the address and start signal.
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func (i2c *I2C) sendAddress(address uint16, write bool) error {
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data := (address << 1)
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if !write {
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data |= 1 // set read flag in transmit register
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}
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// write address to transmit register
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i2c.Bus.TXR_RXR.Set(uint32(data))
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// generate start condition
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i2c.Bus.CR_SR.Set((sifive.I2C_CR_STA | sifive.I2C_CR_WR))
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// wait until transmission complete
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for i2c.Bus.CR_SR.HasBits(sifive.I2C_SR_TIP) {
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}
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return nil
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}
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