3f89fa0bee
This chip can run so much faster! Let's update the default frequency. Also, change the UART implementation to be more fexible regarding the clock frequency.
153 строки
4,3 КиБ
Go
153 строки
4,3 КиБ
Go
// +build fe310
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// This file implements target-specific things for the FE310 chip as used in the
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// HiFive1.
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package runtime
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import (
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"machine"
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"unsafe"
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"device/riscv"
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"device/sifive"
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"runtime/volatile"
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)
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type timeUnit int64
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func postinit() {}
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//export main
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func main() {
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// Zero the PLIC enable bits on startup: they are not zeroed at reset.
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sifive.PLIC.ENABLE[0].Set(0)
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sifive.PLIC.ENABLE[1].Set(0)
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// Zero the threshold value to allow all priorities of interrupts.
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sifive.PLIC.THRESHOLD.Set(0)
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// Set the interrupt address.
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// Note that this address must be aligned specially, otherwise the MODE bits
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// of MTVEC won't be zero.
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riscv.MTVEC.Set(uintptr(unsafe.Pointer(&handleInterruptASM)))
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// Reset the MIE register and enable external interrupts.
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// It must be reset here because it not zeroed at startup.
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riscv.MIE.Set(1 << 11) // bit 11 is for machine external interrupts
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// Enable global interrupts now that they've been set up.
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riscv.MSTATUS.SetBits(1 << 3) // MIE
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preinit()
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initPeripherals()
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run()
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exit(0)
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}
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//go:extern handleInterruptASM
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var handleInterruptASM [0]uintptr
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//export handleInterrupt
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func handleInterrupt() {
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cause := riscv.MCAUSE.Get()
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code := uint(cause &^ (1 << 31))
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if cause&(1<<31) != 0 {
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// Topmost bit is set, which means that it is an interrupt.
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switch code {
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case 7: // Machine timer interrupt
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// Signal timeout.
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timerWakeup.Set(1)
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// Disable the timer, to avoid triggering the interrupt right after
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// this interrupt returns.
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riscv.MIE.ClearBits(1 << 7) // MTIE bit
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case 11: // Machine external interrupt
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// Claim this interrupt.
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id := sifive.PLIC.CLAIM.Get()
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// Call the interrupt handler, if any is registered for this ID.
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callInterruptHandler(int(id))
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// Complete this interrupt.
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sifive.PLIC.CLAIM.Set(id)
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}
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} else {
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// Topmost bit is clear, so it is an exception of some sort.
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// We could implement support for unsupported instructions here (such as
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// misaligned loads). However, for now we'll just print a fatal error.
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handleException(code)
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}
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}
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// initPeripherals configures periperhals the way the runtime expects them.
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func initPeripherals() {
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// Configure PLL to output 320MHz.
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// R=2: divide 16MHz to 8MHz
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// F=80: multiply 8MHz by 80 to get 640MHz (80/2-1=39)
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// Q=2: divide 640MHz by 2 to get 320MHz
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// This makes the main CPU run at 320MHz.
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sifive.PRCI.PLLCFG.Set(sifive.PRCI_PLLCFG_PLLR_R2<<sifive.PRCI_PLLCFG_PLLR_Pos | 39<<sifive.PRCI_PLLCFG_PLLF_Pos | sifive.PRCI_PLLCFG_PLLQ_Q2<<sifive.PRCI_PLLCFG_PLLQ_Pos | sifive.PRCI_PLLCFG_SEL | sifive.PRCI_PLLCFG_REFSEL)
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// Turn off HFROSC to save power
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sifive.PRCI.HFROSCCFG.ClearBits(sifive.PRCI_HFROSCCFG_ENABLE)
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// Enable the RTC.
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sifive.RTC.RTCCFG.Set(sifive.RTC_RTCCFG_ENALWAYS)
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// Configure the UART.
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machine.Serial.Configure(machine.UARTConfig{})
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}
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func putchar(c byte) {
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machine.Serial.WriteByte(c)
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}
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var timerWakeup volatile.Register8
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func ticks() timeUnit {
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// Combining the low bits and the high bits yields a time span of over 270
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// years without counter rollover.
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highBits := sifive.CLINT.MTIMEH.Get()
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for {
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lowBits := sifive.CLINT.MTIME.Get()
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newHighBits := sifive.CLINT.MTIMEH.Get()
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if newHighBits == highBits {
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// High bits stayed the same.
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return timeUnit(lowBits) | (timeUnit(highBits) << 32)
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}
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// Retry, because there was a rollover in the low bits (happening every
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// 1.5 days).
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highBits = newHighBits
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}
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}
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func sleepTicks(d timeUnit) {
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target := uint64(ticks() + d)
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sifive.CLINT.MTIMECMPH.Set(uint32(target >> 32))
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sifive.CLINT.MTIMECMP.Set(uint32(target))
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riscv.MIE.SetBits(1 << 7) // MTIE
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for {
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if timerWakeup.Get() != 0 {
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timerWakeup.Set(0)
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// Disable timer.
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break
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}
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riscv.Asm("wfi")
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}
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}
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// handleException is called from the interrupt handler for any exception.
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// Exceptions can be things like illegal instructions, invalid memory
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// read/write, and similar issues.
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func handleException(code uint) {
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// For a list of exception codes, see:
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// https://content.riscv.org/wp-content/uploads/2019/08/riscv-privileged-20190608-1.pdf#page=49
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print("fatal error: exception with mcause=")
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print(code)
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print(" pc=")
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print(riscv.MEPC.Get())
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println()
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abort()
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}
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// callInterruptHandler is a compiler-generated function that calls the
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// appropriate interrupt handler for the given interrupt ID.
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func callInterruptHandler(id int)
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