77ec9b6369
Do it all at once in preparation for Go 1.18 support. To make this commit, I've simply modified the `fmt-check` Makefile target to rewrite files instead of listing the differences. So this is a fully mechanical change, it should not have introduced any errors.
44 строки
1,6 КиБ
Go
44 строки
1,6 КиБ
Go
//go:build sam && atsame51 && atsame51j19
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// +build sam,atsame51,atsame51j19
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package runtime
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import (
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"device/sam"
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)
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func initSERCOMClocks() {
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// Turn on clock to SERCOM0 for UART0
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sam.MCLK.APBAMASK.SetBits(sam.MCLK_APBAMASK_SERCOM0_)
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sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM0_CORE].Set((sam.GCLK_PCHCTRL_GEN_GCLK1 << sam.GCLK_PCHCTRL_GEN_Pos) |
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sam.GCLK_PCHCTRL_CHEN)
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// sets the "slow" clock shared by all SERCOM
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sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOMX_SLOW].Set((sam.GCLK_PCHCTRL_GEN_GCLK1 << sam.GCLK_PCHCTRL_GEN_Pos) |
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sam.GCLK_PCHCTRL_CHEN)
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// Turn on clock to SERCOM1
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sam.MCLK.APBAMASK.SetBits(sam.MCLK_APBAMASK_SERCOM1_)
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sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM1_CORE].Set((sam.GCLK_PCHCTRL_GEN_GCLK1 << sam.GCLK_PCHCTRL_GEN_Pos) |
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sam.GCLK_PCHCTRL_CHEN)
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// Turn on clock to SERCOM2
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sam.MCLK.APBBMASK.SetBits(sam.MCLK_APBBMASK_SERCOM2_)
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sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM2_CORE].Set((sam.GCLK_PCHCTRL_GEN_GCLK1 << sam.GCLK_PCHCTRL_GEN_Pos) |
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sam.GCLK_PCHCTRL_CHEN)
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// Turn on clock to SERCOM3
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sam.MCLK.APBBMASK.SetBits(sam.MCLK_APBBMASK_SERCOM3_)
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sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM3_CORE].Set((sam.GCLK_PCHCTRL_GEN_GCLK1 << sam.GCLK_PCHCTRL_GEN_Pos) |
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sam.GCLK_PCHCTRL_CHEN)
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// Turn on clock to SERCOM4
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sam.MCLK.APBDMASK.SetBits(sam.MCLK_APBDMASK_SERCOM4_)
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sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM4_CORE].Set((sam.GCLK_PCHCTRL_GEN_GCLK1 << sam.GCLK_PCHCTRL_GEN_Pos) |
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sam.GCLK_PCHCTRL_CHEN)
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// Turn on clock to SERCOM5
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sam.MCLK.APBDMASK.SetBits(sam.MCLK_APBDMASK_SERCOM5_)
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sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_SERCOM5_CORE].Set((sam.GCLK_PCHCTRL_GEN_GCLK1 << sam.GCLK_PCHCTRL_GEN_Pos) |
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sam.GCLK_PCHCTRL_CHEN)
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}
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