tinygo/src/device/avr/at90pwm161.go

// Automatically generated file. DO NOT EDIT.
// Generated by gen-device.py from AT90PWM161.atdf, see http://packs.download.atmel.com/

// +build avr,at90pwm161

// Device information for the AT90PWM161.
//
package avr

// Magic type name for the compiler.
type __reg uint8

// Export this magic type name.
type RegValue = __reg

// Some information about this device.
const (
	DEVICE = "AT90PWM161"
	ARCH   = "AVR8"
	FAMILY = "megaAVR"
)

// Interrupts
const (
	IRQ_RESET         = 0  // External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset
	IRQ_PSC2_CAPT     = 1  // PSC2 Capture Event
	IRQ_PSC2_EC       = 2  // PSC2 End Cycle
	IRQ_PSC2_EEC      = 3  // PSC2 End Of Enhanced Cycle
	IRQ_PSC0_CAPT     = 4  // PSC0 Capture Event
	IRQ_PSC0_EC       = 5  // PSC0 End Cycle
	IRQ_PSC0_EEC      = 6  // PSC0 End Of Enhanced Cycle
	IRQ_ANALOG_COMP_1 = 7  // Analog Comparator 1
	IRQ_ANALOG_COMP_2 = 8  // Analog Comparator 2
	IRQ_ANALOG_COMP_3 = 9  // Analog Comparator 3
	IRQ_INT0          = 10 // External Interrupt Request 0
	IRQ_TIMER1_CAPT   = 11 // Timer/Counter1 Capture Event
	IRQ_TIMER1_OVF    = 12 // Timer/Counter1 Overflow
	IRQ_ADC           = 13 // ADC Conversion Complete
	IRQ_INT1          = 14 // External Interrupt Request 1
	IRQ_SPI_STC       = 15 // SPI Serial Transfer Complet
	IRQ_INT2          = 16 // External Interrupt Request 2
	IRQ_WDT           = 17 // Watchdog Timeout Interrupt
	IRQ_EE_READY      = 18 // EEPROM Ready
	IRQ_SPM_READY     = 19 // Store Program Memory Read
	IRQ_max           = 19 // Highest interrupt number on this device.
)

// Peripherals
var (
	// Fuses
	FUSE = struct {
		EXTENDED __reg
		HIGH     __reg
		LOW      __reg
	}{
		EXTENDED: 0x2,
		HIGH:     0x1,
		LOW:      0x0,
	}

	// Lockbits
	LOCKBIT = struct {
		LOCKBIT __reg
	}{
		LOCKBIT: 0x0,
	}

	// I/O Port
	PORT = struct {
		PORTB __reg
		DDRB  __reg
		PINB  __reg
		PORTD __reg
		DDRD  __reg
		PIND  __reg
		PORTE __reg
		DDRE  __reg
		PINE  __reg
	}{
		PORTB: 0x25, // Port B Data Register
		DDRB:  0x24, // Port B Data Direction Register
		PINB:  0x23, // Port B Input Pins
		PORTD: 0x2b, // Port D Data Register
		DDRD:  0x2a, // Port D Data Direction Register
		PIND:  0x29, // Port D Input Pins
		PORTE: 0x2e, // Port E Data Register
		DDRE:  0x2d, // Port E Data Direction Register
		PINE:  0x2c, // Port E Input Pins
	}

	// Digital-to-Analog Converter
	DAC = struct {
		DACH  __reg
		DACL  __reg
		DACON __reg
	}{
		DACH:  0x59, // DAC Data Register High Byte
		DACL:  0x58, // DAC Data Register Low Byte
		DACON: 0x76, // DAC Control Register
	}

	// Serial Peripheral Interface
	SPI = struct {
		SPCR __reg
		SPSR __reg
		SPDR __reg
	}{
		SPCR: 0x37, // SPI Control Register
		SPSR: 0x38, // SPI Status Register
		SPDR: 0x56, // SPI Data Register
	}

	// Watchdog Timer
	WDT = struct {
		WDTCSR __reg
	}{
		WDTCSR: 0x82, // Watchdog Timer Control Register
	}

	// External Interrupts
	EXINT = struct {
		EICRA __reg
		EIMSK __reg
		EIFR  __reg
	}{
		EICRA: 0x89, // External Interrupt Control Register A
		EIMSK: 0x41, // External Interrupt Mask Register
		EIFR:  0x40, // External Interrupt Flag Register
	}

	// Analog-to-Digital Converter
	ADC = struct {
		ADMUX   __reg
		ADCSRA  __reg
		ADCL    __reg
		ADCH    __reg
		ADCSRB  __reg
		DIDR0   __reg
		DIDR1   __reg
		AMP0CSR __reg
	}{
		ADMUX:   0x28, // The ADC multiplexer Selection Register
		ADCSRA:  0x26, // The ADC Control and Status register
		ADCL:    0x4c, // ADC Data Register  Bytes
		ADCH:    0x4c, // ADC Data Register  Bytes
		ADCSRB:  0x27, // ADC Control and Status Register B
		DIDR0:   0x77, // Digital Input Disable Register 0
		DIDR1:   0x78, // Digital Input Disable Register 0
		AMP0CSR: 0x79,
	}

	// Analog Comparator
	AC = struct {
		AC3CON  __reg
		AC1CON  __reg
		AC2CON  __reg
		ACSR    __reg
		AC3ECON __reg
		AC2ECON __reg
		AC1ECON __reg
	}{
		AC3CON:  0x7f, // Analog Comparator3 Control Register
		AC1CON:  0x7d, // Analog Comparator 1 Control Register
		AC2CON:  0x7e, // Analog Comparator 2 Control Register
		ACSR:    0x20, // Analog Comparator Status Register
		AC3ECON: 0x7c,
		AC2ECON: 0x7b,
		AC1ECON: 0x7a,
	}

	// CPU Registers
	CPU = struct {
		SREG    __reg
		SPL     __reg
		SPH     __reg
		MCUCR   __reg
		MCUSR   __reg
		OSCCAL  __reg
		CLKPR   __reg
		SMCR    __reg
		GPIOR2  __reg
		GPIOR1  __reg
		GPIOR0  __reg
		PLLCSR  __reg
		PRR     __reg
		CLKCSR  __reg
		CLKSELR __reg
		BGCCR   __reg
		BGCRR   __reg
	}{
		SREG:    0x5f, // Status Register
		SPL:     0x5d, // Stack Pointer
		SPH:     0x5d, // Stack Pointer
		MCUCR:   0x55, // MCU Control Register
		MCUSR:   0x54, // MCU Status Register
		OSCCAL:  0x88, // Oscillator Calibration Value
		CLKPR:   0x83,
		SMCR:    0x53, // Sleep Mode Control Register
		GPIOR2:  0x3b, // General Purpose IO Register 2
		GPIOR1:  0x3a, // General Purpose IO Register 1
		GPIOR0:  0x39, // General Purpose IO Register 0
		PLLCSR:  0x87, // PLL Control And Status Register
		PRR:     0x86, // Power Reduction Register
		CLKCSR:  0x84,
		CLKSELR: 0x85,
		BGCCR:   0x81, // BandGap Current Calibration Register
		BGCRR:   0x80, // BandGap Resistor Calibration Register
	}

	// EEPROM
	EEPROM = struct {
		EEARL __reg
		EEARH __reg
		EEDR  __reg
		EECR  __reg
	}{
		EEARL: 0x3e, // EEPROM Read/Write Access  Bytes
		EEARH: 0x3e, // EEPROM Read/Write Access  Bytes
		EEDR:  0x3d, // EEPROM Data Register
		EECR:  0x3c, // EEPROM Control Register
	}

	// Power Stage Controller
	PSC = struct {
		PICR0L  __reg
		PICR0H  __reg
		PFRC0B  __reg
		PFRC0A  __reg
		PCTL0   __reg
		PCNF0   __reg
		OCR0RBL __reg
		OCR0RBH __reg
		OCR0SBL __reg
		OCR0SBH __reg
		OCR0RAL __reg
		OCR0RAH __reg
		OCR0SAL __reg
		OCR0SAH __reg
		PSOC0   __reg
		PIM0    __reg
		PIFR0   __reg
		PICR2H  __reg
		PICR2L  __reg
		PFRC2B  __reg
		PFRC2A  __reg
		PCTL2   __reg
		PCNF2   __reg
		PCNFE2  __reg
		OCR2RBL __reg
		OCR2RBH __reg
		OCR2SBL __reg
		OCR2SBH __reg
		OCR2RAL __reg
		OCR2RAH __reg
		OCR2SAL __reg
		OCR2SAH __reg
		POM2    __reg
		PSOC2   __reg
		PIM2    __reg
		PIFR2   __reg
		PASDLY2 __reg
	}{
		PICR0L:  0x68, // PSC 0 Input Capture Register
		PICR0H:  0x68, // PSC 0 Input Capture Register
		PFRC0B:  0x63, // PSC 0 Input B Control
		PFRC0A:  0x62, // PSC 0 Input A Control
		PCTL0:   0x32, // PSC 0 Control Register
		PCNF0:   0x31, // PSC 0 Configuration Register
		OCR0RBL: 0x44, // Output Compare RB Register
		OCR0RBH: 0x44, // Output Compare RB Register
		OCR0SBL: 0x42, // Output Compare SB Register
		OCR0SBH: 0x42, // Output Compare SB Register
		OCR0RAL: 0x4a, // Output Compare RA Register
		OCR0RAH: 0x4a, // Output Compare RA Register
		OCR0SAL: 0x60, // Output Compare SA Register
		OCR0SAH: 0x60, // Output Compare SA Register
		PSOC0:   0x6a, // PSC0 Synchro and Output Configuration
		PIM0:    0x2f, // PSC0 Interrupt Mask Register
		PIFR0:   0x30, // PSC0 Interrupt Flag Register
		PICR2H:  0x6d, // PSC 2 Input Capture Register High
		PICR2L:  0x6c, // PSC 2 Input Capture Register Low
		PFRC2B:  0x67, // PSC 2 Input B Control
		PFRC2A:  0x66, // PSC 2 Input B Control
		PCTL2:   0x36, // PSC 2 Control Register
		PCNF2:   0x35, // PSC 2 Configuration Register
		PCNFE2:  0x70, // PSC 2 Enhanced Configuration Register
		OCR2RBL: 0x48, // Output Compare RB Register
		OCR2RBH: 0x48, // Output Compare RB Register
		OCR2SBL: 0x46, // Output Compare SB Register
		OCR2SBH: 0x46, // Output Compare SB Register
		OCR2RAL: 0x4e, // Output Compare RA Register
		OCR2RAH: 0x4e, // Output Compare RA Register
		OCR2SAL: 0x64, // Output Compare SA Register
		OCR2SAH: 0x64, // Output Compare SA Register
		POM2:    0x6f, // PSC 2 Output Matrix
		PSOC2:   0x6e, // PSC2 Synchro and Output Configuration
		PIM2:    0x33, // PSC2 Interrupt Mask Register
		PIFR2:   0x34, // PSC2 Interrupt Flag Register
		PASDLY2: 0x71, // Analog Synchronization Delay Register
	}

	// Timer/Counter, 16-bit
	TC16 = struct {
		TIMSK1 __reg
		TIFR1  __reg
		TCCR1B __reg
		TCNT1L __reg
		TCNT1H __reg
		ICR1L  __reg
		ICR1H  __reg
	}{
		TIMSK1: 0x21, // Timer/Counter Interrupt Mask Register
		TIFR1:  0x22, // Timer/Counter Interrupt Flag register
		TCCR1B: 0x8a, // Timer/Counter1 Control Register B
		TCNT1L: 0x5a, // Timer/Counter1  Bytes
		TCNT1H: 0x5a, // Timer/Counter1  Bytes
		ICR1L:  0x8c, // Timer/Counter1 Input Capture Register  Bytes
		ICR1H:  0x8c, // Timer/Counter1 Input Capture Register  Bytes
	}

	// Bootloader
	BOOT_LOAD = struct {
		SPMCSR __reg
	}{
		SPMCSR: 0x57, // Store Program Memory Control Register
	}
)

// Bitfields for FUSE: Fuses
const (
	// EXTENDED
	EXTENDED_PSC2RB   = 0x80 // PSC2 Reset Behavior
	EXTENDED_PSC2RBA  = 0x40 // PSC2 Reset Behavior for 22 and 23
	EXTENDED_PSC0RB   = 0x20 // PSC0 Reset Behavior
	EXTENDED_PSCRV    = 0x10 // PSC Reset Value
	EXTENDED_PSCINRB  = 0x8  // PSC2 and PSC0 input Reset Behavior
	EXTENDED_BODLEVEL = 0x7  // Brown-out Detector Trigger Level

	// HIGH
	HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PE0 as I/O pin)
	HIGH_DWEN     = 0x40 // Debug Wire enable
	HIGH_SPIEN    = 0x20 // Serial program downloading (SPI) enabled
	HIGH_WDTON    = 0x10 // Watch-dog Timer always on
	HIGH_EESAVE   = 0x8  // Preserve EEPROM through the Chip Erase cycle
	HIGH_BOOTSZ   = 0x6  // Select Boot Size
	HIGH_BOOTRST  = 0x1  // Select Reset Vector

	// LOW
	LOW_CKDIV8    = 0x80 // Divide clock by 8 internally
	LOW_CKOUT     = 0x40 // Clock output on PORTD1
	LOW_SUT_CKSEL = 0x3f // Select Clock Source
)

// Bitfields for LOCKBIT: Lockbits
const (
	// LOCKBIT
	LOCKBIT_LB   = 0x3  // Memory Lock
	LOCKBIT_BLB0 = 0xc  // Boot Loader Protection Mode
	LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode
)

// Bitfields for DAC: Digital-to-Analog Converter
const (
	// DACH: DAC Data Register High Byte
	DACH_DACH = 0xff // DAC Data Register High Byte Bits

	// DACL: DAC Data Register Low Byte
	DACL_DACL = 0xff // DAC Data Register Low Byte Bits

	// DACON: DAC Control Register
	DACON_DAATE = 0x80 // DAC Auto Trigger Enable Bit
	DACON_DATS  = 0x70 // DAC Trigger Selection Bits
	DACON_DALA  = 0x4  // DAC Left Adjust
	DACON_DAEN  = 0x1  // DAC Enable Bit
)

// Bitfields for SPI: Serial Peripheral Interface
const (
	// SPCR: SPI Control Register
	SPCR_SPIE = 0x80 // SPI Interrupt Enable
	SPCR_SPE  = 0x40 // SPI Enable
	SPCR_DORD = 0x20 // Data Order
	SPCR_MSTR = 0x10 // Master/Slave Select
	SPCR_CPOL = 0x8  // Clock polarity
	SPCR_CPHA = 0x4  // Clock Phase
	SPCR_SPR  = 0x3  // SPI Clock Rate Selects

	// SPSR: SPI Status Register
	SPSR_SPIF  = 0x80 // SPI Interrupt Flag
	SPSR_WCOL  = 0x40 // Write Collision Flag
	SPSR_SPI2X = 0x1  // Double SPI Speed Bit
)

// Bitfields for WDT: Watchdog Timer
const (
	// WDTCSR: Watchdog Timer Control Register
	WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag
	WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable
	WDTCSR_WDP  = 0x27 // Watchdog Timer Prescaler Bits
	WDTCSR_WDCE = 0x10 // Watchdog Change Enable
	WDTCSR_WDE  = 0x8  // Watch Dog Enable
)

// Bitfields for EXINT: External Interrupts
const (
	// EICRA: External Interrupt Control Register A
	EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit
	EICRA_ISC1 = 0xc  // External Interrupt Sense Control Bit
	EICRA_ISC0 = 0x3  // External Interrupt Sense Control Bit

	// EIMSK: External Interrupt Mask Register
	EIMSK_INT = 0x7 // External Interrupt Request 2 Enable

	// EIFR: External Interrupt Flag Register
	EIFR_INTF = 0x7 // External Interrupt Flags
)

// Bitfields for ADC: Analog-to-Digital Converter
const (
	// ADMUX: The ADC multiplexer Selection Register
	ADMUX_REFS  = 0xc0 // Reference Selection Bits
	ADMUX_ADLAR = 0x20 // Left Adjust Result
	ADMUX_MUX   = 0xf  // Analog Channel and Gain Selection Bits

	// ADCSRA: The ADC Control and Status register
	ADCSRA_ADEN  = 0x80 // ADC Enable
	ADCSRA_ADSC  = 0x40 // ADC Start Conversion
	ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable
	ADCSRA_ADIF  = 0x10 // ADC Interrupt Flag
	ADCSRA_ADIE  = 0x8  // ADC Interrupt Enable
	ADCSRA_ADPS  = 0x7  // ADC  Prescaler Select Bits

	// ADCSRB: ADC Control and Status Register B
	ADCSRB_ADHSM   = 0x80 // ADC High Speed Mode
	ADCSRB_ADNCDIS = 0x40 // ADC Noise Canceller Disable
	ADCSRB_ADSSEN  = 0x10 // ADC Single Shot Enable on PSC's Synchronisation Signals
	ADCSRB_ADTS    = 0xf  // ADC Auto Trigger Sources

	// DIDR0: Digital Input Disable Register 0
	DIDR0_ADC7D = 0x80
	DIDR0_ADC6D = 0x40 // ADC7 Digital input Disable
	DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable
	DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable
	DIDR0_ADC3D = 0x8  // ADC3 Digital input Disable
	DIDR0_ADC2D = 0x4  // ADC2 Digital input Disable
	DIDR0_ADC1D = 0x2  // ADC1 Digital input Disable
	DIDR0_ADC0D = 0x1  // ADC0 Digital input Disable

	// DIDR1: Digital Input Disable Register 0
	DIDR1_ACMP1MD  = 0x8
	DIDR1_AMP0POSD = 0x4
	DIDR1_ADC10D   = 0x2
	DIDR1_ADC9D    = 0x1

	// AMP0CSR
	AMP0CSR_AMP0EN = 0x80
	AMP0CSR_AMP0IS = 0x40
	AMP0CSR_AMP0G  = 0x30
	AMP0CSR_AMP0GS = 0x8
	AMP0CSR_AMP0TS = 0x3
)

// Bitfields for AC: Analog Comparator
const (
	// AC3CON: Analog Comparator3 Control Register
	AC3CON_AC3EN  = 0x80 // Analog Comparator3 Enable Bit
	AC3CON_AC3IE  = 0x40 // Analog Comparator 3 Interrupt Enable Bit
	AC3CON_AC3IS  = 0x30 // Analog Comparator 3  Interrupt Select Bit
	AC3CON_AC3OEA = 0x8  // Analog Comparator 3 Alternate Output Enable
	AC3CON_AC3M   = 0x7  // Analog Comparator 3 Multiplexer Register

	// AC1CON: Analog Comparator 1 Control Register
	AC1CON_AC1EN = 0x80 // Analog Comparator 1 Enable Bit
	AC1CON_AC1IE = 0x40 // Analog Comparator 1 Interrupt Enable Bit
	AC1CON_AC1IS = 0x30 // Analog Comparator 1  Interrupt Select Bit
	AC1CON_AC1M  = 0x7  // Analog Comparator 1 Multiplexer Register

	// AC2CON: Analog Comparator 2 Control Register
	AC2CON_AC2EN = 0x80 // Analog Comparator 2 Enable Bit
	AC2CON_AC2IE = 0x40 // Analog Comparator 2 Interrupt Enable Bit
	AC2CON_AC2IS = 0x30 // Analog Comparator 2  Interrupt Select Bit
	AC2CON_AC2M  = 0x7  // Analog Comparator 2 Multiplexer Register

	// ACSR: Analog Comparator Status Register
	ACSR_AC3IF = 0x80 // Analog Comparator 3 Interrupt Flag Bit
	ACSR_AC2IF = 0x40 // Analog Comparator 2 Interrupt Flag Bit
	ACSR_AC1IF = 0x20 // Analog Comparator 1  Interrupt Flag Bit
	ACSR_AC3O  = 0x8  // Analog Comparator 3 Output Bit
	ACSR_AC2O  = 0x4  // Analog Comparator 2 Output Bit
	ACSR_AC1O  = 0x2  // Analog Comparator 1 Output Bit

	// AC3ECON
	AC3ECON_AC3OI = 0x20 // Analog Comparator Ouput Invert
	AC3ECON_AC3OE = 0x10 // Analog Comparator Ouput Enable
	AC3ECON_AC3H  = 0x7  // Analog Comparator Hysteresis Select

	// AC2ECON
	AC2ECON_AC2OI = 0x20 // Analog Comparator Ouput Invert
	AC2ECON_AC2OE = 0x10 // Analog Comparator Ouput Enable
	AC2ECON_AC2H  = 0x7  // Analog Comparator Hysteresis Select

	// AC1ECON
	AC1ECON_AC1OI  = 0x20 // Analog Comparator Ouput Invert
	AC1ECON_AC1OE  = 0x10 // Analog Comparator Ouput Enable
	AC1ECON_AC1ICE = 0x8  // Analog Comparator Interrupt Capture Enable
	AC1ECON_AC1H   = 0x7  // Analog Comparator Hysteresis Select
)

// Bitfields for CPU: CPU Registers
const (
	// SREG: Status Register
	SREG_I = 0x80 // Global Interrupt Enable
	SREG_T = 0x40 // Bit Copy Storage
	SREG_H = 0x20 // Half Carry Flag
	SREG_S = 0x10 // Sign Bit
	SREG_V = 0x8  // Two's Complement Overflow Flag
	SREG_N = 0x4  // Negative Flag
	SREG_Z = 0x2  // Zero Flag
	SREG_C = 0x1  // Carry Flag

	// MCUCR: MCU Control Register
	MCUCR_PUD    = 0x10 // Pull-up disable
	MCUCR_RSTDIS = 0x8  // Reset Pin Disable
	MCUCR_CKRC81 = 0x4  // Frequency Selection of the Calibrated RC Oscillator
	MCUCR_IVSEL  = 0x2  // Interrupt Vector Select
	MCUCR_IVCE   = 0x1  // Interrupt Vector Change Enable

	// MCUSR: MCU Status Register
	MCUSR_WDRF  = 0x8 // Watchdog Reset Flag
	MCUSR_BORF  = 0x4 // Brown-out Reset Flag
	MCUSR_EXTRF = 0x2 // External Reset Flag
	MCUSR_PORF  = 0x1 // Power-on reset flag

	// OSCCAL: Oscillator Calibration Value
	OSCCAL_OSCCAL = 0xff // Oscillator Calibration

	// CLKPR
	CLKPR_CLKPCE = 0x80
	CLKPR_CLKPS  = 0xf

	// SMCR: Sleep Mode Control Register
	SMCR_SM = 0xe // Sleep Mode Select bits
	SMCR_SE = 0x1 // Sleep Enable

	// GPIOR2: General Purpose IO Register 2
	GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis

	// GPIOR1: General Purpose IO Register 1
	GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis

	// GPIOR0: General Purpose IO Register 0
	GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7
	GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6
	GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5
	GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4
	GPIOR0_GPIOR03 = 0x8  // General Purpose IO Register 0 bit 3
	GPIOR0_GPIOR02 = 0x4  // General Purpose IO Register 0 bit 2
	GPIOR0_GPIOR01 = 0x2  // General Purpose IO Register 0 bit 1
	GPIOR0_GPIOR00 = 0x1  // General Purpose IO Register 0 bit 0

	// PLLCSR: PLL Control And Status Register
	PLLCSR_PLLF  = 0x3c
	PLLCSR_PLLE  = 0x2 // PLL Enable
	PLLCSR_PLOCK = 0x1 // PLL Lock Detector

	// PRR: Power Reduction Register
	PRR_PRPSC2 = 0x80 // Power Reduction PSC2
	PRR_PRPSCR = 0x20 // Power Reduction PSC0
	PRR_PRTIM1 = 0x10 // Power Reduction Timer/Counter1
	PRR_PRSPI  = 0x4  // Power Reduction Serial Peripheral Interface
	PRR_PRADC  = 0x1  // Power Reduction ADC

	// CLKCSR
	CLKCSR_CLKCCE = 0x80 // Clock Control Change Enable
	CLKCSR_CLKRDY = 0x10 // Clock Ready Flag
	CLKCSR_CLKC   = 0xf  // Clock Control

	// CLKSELR
	CLKSELR_COUT  = 0x40 // Clock OUT
	CLKSELR_CSUT  = 0x30 // Clock Start up Time
	CLKSELR_CKSEL = 0xf  // Clock Source Select

	// BGCCR: BandGap Current Calibration Register
	BGCCR_BGCC = 0xf

	// BGCRR: BandGap Resistor Calibration Register
	BGCRR_BGCR = 0xf
)

// Bitfields for EEPROM: EEPROM
const (
	// EECR: EEPROM Control Register
	EECR_NVMBSY = 0x80 // None Volatile Busy Memory Busy
	EECR_EEPAGE = 0x40 // EEPROM Page Access
	EECR_EEPM   = 0x30 // EEPROM Programming Mode
	EECR_EERIE  = 0x8  // EEPROM Ready Interrupt Enable
	EECR_EEMWE  = 0x4  // EEPROM Master Write Enable
	EECR_EEWE   = 0x2  // EEPROM Write Enable
	EECR_EERE   = 0x1  // EEPROM Read Enable
)

// Bitfields for PSC: Power Stage Controller
const (
	// PFRC0B: PSC 0 Input B Control
	PFRC0B_PCAE0B  = 0x80 // PSC 0 Capture Enable Input Part B
	PFRC0B_PISEL0B = 0x40 // PSC 0 Input Select for Part B
	PFRC0B_PELEV0B = 0x20 // PSC 0 Edge Level Selector on Input Part B
	PFRC0B_PFLTE0B = 0x10 // PSC 0 Filter Enable on Input Part B
	PFRC0B_PRFM0B  = 0xf  // PSC 0 Retrigger and Fault Mode for Part B

	// PFRC0A: PSC 0 Input A Control
	PFRC0A_PCAE0A  = 0x80 // PSC 0 Capture Enable Input Part A
	PFRC0A_PISEL0A = 0x40 // PSC 0 Input Select for Part A
	PFRC0A_PELEV0A = 0x20 // PSC 0 Edge Level Selector on Input Part A
	PFRC0A_PFLTE0A = 0x10 // PSC 0 Filter Enable on Input Part A
	PFRC0A_PRFM0A  = 0xf  // PSC 0 Retrigger and Fault Mode for Part A

	// PCTL0: PSC 0 Control Register
	PCTL0_PPRE0  = 0xc0 // PSC 0 Prescaler Selects
	PCTL0_PBFM0  = 0x24 // PSC 0 Balance Flank Width Modulation
	PCTL0_PAOC0B = 0x10 // PSC 0 Asynchronous Output Control B
	PCTL0_PAOC0A = 0x8  // PSC 0 Asynchronous Output Control A
	PCTL0_PCCYC0 = 0x2  // PSC0 Complete Cycle
	PCTL0_PRUN0  = 0x1  // PSC 0 Run

	// PCNF0: PSC 0 Configuration Register
	PCNF0_PFIFTY0  = 0x80 // PSC 0 Fifty
	PCNF0_PALOCK0  = 0x40 // PSC 0 Autolock
	PCNF0_PLOCK0   = 0x20 // PSC 0 Lock
	PCNF0_PMODE0   = 0x18 // PSC 0 Mode
	PCNF0_POP0     = 0x4  // PSC 0 Output Polarity
	PCNF0_PCLKSEL0 = 0x2  // PSC 0 Input Clock Select

	// PSOC0: PSC0 Synchro and Output Configuration
	PSOC0_PISEL0A1 = 0x80 // PSC Input Select
	PSOC0_PISEL0B1 = 0x40 // PSC Input Select
	PSOC0_PSYNC0   = 0x30 // Synchronisation out for ADC selection
	PSOC0_POEN0B   = 0x4  // PSCOUT01 Output Enable
	PSOC0_POEN0A   = 0x1  // PSCOUT00 Output Enable

	// PIM0: PSC0 Interrupt Mask Register
	PIM0_PEVE0B  = 0x10 // External Event B Interrupt Enable
	PIM0_PEVE0A  = 0x8  // External Event A Interrupt Enable
	PIM0_PEOEPE0 = 0x2  // End of Enhanced Cycle Enable
	PIM0_PEOPE0  = 0x1  // End of Cycle Interrupt Enable

	// PIFR0: PSC0 Interrupt Flag Register
	PIFR0_POAC0B = 0x80 // PSC 0 Output A Activity
	PIFR0_POAC0A = 0x40 // PSC 0 Output A Activity
	PIFR0_PEV0B  = 0x10 // External Event B Interrupt
	PIFR0_PEV0A  = 0x8  // External Event A Interrupt
	PIFR0_PRN0   = 0x6  // Ramp Number
	PIFR0_PEOP0  = 0x1  // End of PSC0 Interrupt

	// PICR2H: PSC 2 Input Capture Register High
	PICR2H_PCST2  = 0x80 // PSC 2 Capture Software Trigger Bit
	PICR2H_PICR21 = 0xc
	PICR2H_PICR2  = 0x3

	// PFRC2B: PSC 2 Input B Control
	PFRC2B_PCAE2B  = 0x80 // PSC 2 Capture Enable Input Part B
	PFRC2B_PISEL2B = 0x40 // PSC 2 Input Select for Part B
	PFRC2B_PELEV2B = 0x20 // PSC 2 Edge Level Selector on Input Part B
	PFRC2B_PFLTE2B = 0x10 // PSC 2 Filter Enable on Input Part B
	PFRC2B_PRFM2B  = 0xf  // PSC 2 Retrigger and Fault Mode for Part B

	// PFRC2A: PSC 2 Input B Control
	PFRC2A_PCAE2A  = 0x80 // PSC 2 Capture Enable Input Part A
	PFRC2A_PISEL2A = 0x40 // PSC 2 Input Select for Part A
	PFRC2A_PELEV2A = 0x20 // PSC 2 Edge Level Selector on Input Part A
	PFRC2A_PFLTE2A = 0x10 // PSC 2 Filter Enable on Input Part A
	PFRC2A_PRFM2A  = 0xf  // PSC 2 Retrigger and Fault Mode for Part A

	// PCTL2: PSC 2 Control Register
	PCTL2_PPRE2  = 0xc0 // PSC 2 Prescaler Selects
	PCTL2_PBFM2  = 0x20 // Balance Flank Width Modulation
	PCTL2_PAOC2B = 0x10 // PSC 2 Asynchronous Output Control B
	PCTL2_PAOC2A = 0x8  // PSC 2 Asynchronous Output Control A
	PCTL2_PARUN2 = 0x4  // PSC2 Auto Run
	PCTL2_PCCYC2 = 0x2  // PSC2 Complete Cycle
	PCTL2_PRUN2  = 0x1  // PSC 2 Run

	// PCNF2: PSC 2 Configuration Register
	PCNF2_PFIFTY2  = 0x80 // PSC 2 Fifty
	PCNF2_PALOCK2  = 0x40 // PSC 2 Autolock
	PCNF2_PLOCK2   = 0x20 // PSC 2 Lock
	PCNF2_PMODE2   = 0x18 // PSC 2 Mode
	PCNF2_POP2     = 0x4  // PSC 2 Output Polarity
	PCNF2_PCLKSEL2 = 0x2  // PSC 2 Input Clock Select
	PCNF2_POME2    = 0x1  // PSC 2 Output Matrix Enable

	// PCNFE2: PSC 2 Enhanced Configuration Register
	PCNFE2_PASDLK2  = 0xe0
	PCNFE2_PBFM21   = 0x10
	PCNFE2_PELEV2A1 = 0x8
	PCNFE2_PELEV2B1 = 0x4
	PCNFE2_PISEL2A1 = 0x2
	PCNFE2_PISEL2B1 = 0x1

	// POM2: PSC 2 Output Matrix
	POM2_POMV2B = 0xf0 // Output Matrix Output B Ramps
	POM2_POMV2A = 0xf  // Output Matrix Output A Ramps

	// PSOC2: PSC2 Synchro and Output Configuration
	PSOC2_POS2   = 0xc0 // PSC 2 Output 23 Select
	PSOC2_PSYNC2 = 0x30 // Synchronization Out for ADC Selection
	PSOC2_POEN2D = 0x8  // PSCOUT23 Output Enable
	PSOC2_POEN2B = 0x4  // PSCOUT21 Output Enable
	PSOC2_POEN2C = 0x2  // PSCOUT22 Output Enable
	PSOC2_POEN2A = 0x1  // PSCOUT20 Output Enable

	// PIM2: PSC2 Interrupt Mask Register
	PIM2_PSEIE2  = 0x20 // PSC 2 Synchro Error Interrupt Enable
	PIM2_PEVE2B  = 0x10 // External Event B Interrupt Enable
	PIM2_PEVE2A  = 0x8  // External Event A Interrupt Enable
	PIM2_PEOEPE2 = 0x2  // End of Enhanced Cycle Interrupt Enable
	PIM2_PEOPE2  = 0x1  // End of Cycle Interrupt Enable

	// PIFR2: PSC2 Interrupt Flag Register
	PIFR2_POAC2B = 0x80 // PSC 2 Output A Activity
	PIFR2_POAC2A = 0x40 // PSC 2 Output A Activity
	PIFR2_PSEI2  = 0x20 // PSC 2 Synchro Error Interrupt
	PIFR2_PEV2B  = 0x10 // External Event B Interrupt
	PIFR2_PEV2A  = 0x8  // External Event A Interrupt
	PIFR2_PRN2   = 0x6  // Ramp Number
	PIFR2_PEOP2  = 0x1  // End of PSC2 Interrupt
)

// Bitfields for TC16: Timer/Counter, 16-bit
const (
	// TIMSK1: Timer/Counter Interrupt Mask Register
	TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable
	TIMSK1_TOIE1 = 0x1  // Timer/Counter1 Overflow Interrupt Enable

	// TIFR1: Timer/Counter Interrupt Flag register
	TIFR1_ICF1 = 0x20 // Input Capture Flag 1
	TIFR1_TOV1 = 0x1  // Timer/Counter1 Overflow Flag

	// TCCR1B: Timer/Counter1 Control Register B
	TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler
	TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select
	TCCR1B_WGM13 = 0x10 // Waveform Generation Mode
	TCCR1B_CS1   = 0x7  // Prescaler source of Timer/Counter 1
)

// Bitfields for BOOT_LOAD: Bootloader
const (
	// SPMCSR: Store Program Memory Control Register
	SPMCSR_SPMIE  = 0x80 // SPM Interrupt Enable
	SPMCSR_RWWSB  = 0x40 // Read While Write Section Busy
	SPMCSR_SIGRD  = 0x20 // Signature Row Read
	SPMCSR_RWWSRE = 0x10 // Read While Write section read enable
	SPMCSR_BLBSET = 0x8  // Boot Lock Bit Set
	SPMCSR_PGWRT  = 0x4  // Page Write
	SPMCSR_PGERS  = 0x2  // Page Erase
	SPMCSR_SPMEN  = 0x1  // Store Program Memory Enable
)