546 строки
15 КиБ
Go
546 строки
15 КиБ
Go
//go:build stm32l4
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// +build stm32l4
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package machine
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import (
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"device/stm32"
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"runtime/interrupt"
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"runtime/volatile"
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"unsafe"
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)
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// Peripheral abstraction layer for the stm32l4
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const (
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AF0_SYSTEM = 0
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AF1_TIM1_2_LPTIM1 = 1
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AF2_TIM1_2 = 2
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AF3_USART2 = 3
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AF4_I2C1_2_3 = 4
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AF5_SPI1_2 = 5
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AF6_SPI3 = 6
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AF7_USART1_2_3 = 7
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AF8_LPUART1 = 8
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AF9_CAN1_TSC = 9
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AF10_USB_QUADSPI = 10
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AF12_COMP1_2_SWPMI1 = 12
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AF13_SAI1 = 13
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AF14_TIM2_15_16_LPTIM2 = 14
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AF15_EVENTOUT = 15
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)
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const (
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PA0 = portA + 0
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PA1 = portA + 1
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PA2 = portA + 2
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PA3 = portA + 3
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PA4 = portA + 4
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PA5 = portA + 5
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PA6 = portA + 6
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PA7 = portA + 7
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PA8 = portA + 8
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PA9 = portA + 9
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PA10 = portA + 10
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PA11 = portA + 11
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PA12 = portA + 12
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PA13 = portA + 13
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PA14 = portA + 14
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PA15 = portA + 15
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PB0 = portB + 0
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PB1 = portB + 1
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PB2 = portB + 2
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PB3 = portB + 3
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PB4 = portB + 4
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PB5 = portB + 5
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PB6 = portB + 6
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PB7 = portB + 7
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PB8 = portB + 8
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PB9 = portB + 9
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PB10 = portB + 10
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PB11 = portB + 11
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PB12 = portB + 12
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PB13 = portB + 13
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PB14 = portB + 14
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PB15 = portB + 15
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PC0 = portC + 0
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PC1 = portC + 1
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PC2 = portC + 2
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PC3 = portC + 3
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PC4 = portC + 4
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PC5 = portC + 5
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PC6 = portC + 6
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PC7 = portC + 7
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PC8 = portC + 8
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PC9 = portC + 9
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PC10 = portC + 10
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PC11 = portC + 11
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PC12 = portC + 12
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PC13 = portC + 13
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PC14 = portC + 14
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PC15 = portC + 15
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PD0 = portD + 0
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PD1 = portD + 1
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PD2 = portD + 2
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PD3 = portD + 3
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PD4 = portD + 4
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PD5 = portD + 5
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PD6 = portD + 6
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PD7 = portD + 7
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PD8 = portD + 8
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PD9 = portD + 9
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PD10 = portD + 10
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PD11 = portD + 11
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PD12 = portD + 12
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PD13 = portD + 13
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PD14 = portD + 14
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PD15 = portD + 15
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PE0 = portE + 0
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PE1 = portE + 1
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PE2 = portE + 2
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PE3 = portE + 3
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PE4 = portE + 4
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PE5 = portE + 5
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PE6 = portE + 6
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PE7 = portE + 7
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PE8 = portE + 8
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PE9 = portE + 9
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PE10 = portE + 10
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PE11 = portE + 11
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PE12 = portE + 12
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PE13 = portE + 13
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PE14 = portE + 14
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PE15 = portE + 15
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)
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// IRQs are defined here as they vary in the SVDs, but do have consistent mapping
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// to Timer Interrupts.
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const (
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irq_TIM1_BRK_TIM15 = 24
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irq_TIM1_UP_TIM16 = 25
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irq_TIM1_TRG_COM_TIM17 = 26
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irq_TIM1_CC = 27
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irq_TIM2 = 28
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irq_TIM3 = 29
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irq_TIM4 = 30
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irq_TIM5 = 50
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irq_TIM6 = 54
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irq_TIM7 = 55
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irq_TIM8_BRK = 43
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irq_TIM8_UP = 44
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irq_TIM8_TRG_COM = 45
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irq_TIM8_CC = 46
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)
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func (p Pin) getPort() *stm32.GPIO_Type {
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switch p / 16 {
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case 0:
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return stm32.GPIOA
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case 1:
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return stm32.GPIOB
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case 2:
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return stm32.GPIOC
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case 3:
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return stm32.GPIOD
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case 4:
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return stm32.GPIOE
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default:
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panic("machine: unknown port")
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}
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}
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// enableClock enables the clock for this desired GPIO port.
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func (p Pin) enableClock() {
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switch p / 16 {
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case 0:
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stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOAEN)
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case 1:
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stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOBEN)
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case 2:
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stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOCEN)
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case 3:
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stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIODEN)
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case 4:
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stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_GPIOEEN)
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default:
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panic("machine: unknown port")
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}
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}
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// Enable peripheral clock
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func enableAltFuncClock(bus unsafe.Pointer) {
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switch bus {
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case unsafe.Pointer(stm32.PWR): // Power interface clock enable
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stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_PWREN)
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case unsafe.Pointer(stm32.I2C3): // I2C3 clock enable
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stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_I2C3EN)
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case unsafe.Pointer(stm32.I2C2): // I2C2 clock enable
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stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_I2C2EN)
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case unsafe.Pointer(stm32.I2C1): // I2C1 clock enable
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stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_I2C1EN)
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case unsafe.Pointer(stm32.UART4): // UART4 clock enable
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stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_UART4EN)
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case unsafe.Pointer(stm32.USART3): // USART3 clock enable
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stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_USART3EN)
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case unsafe.Pointer(stm32.USART2): // USART2 clock enable
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stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_USART2EN)
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case unsafe.Pointer(stm32.SPI3): // SPI3 clock enable
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stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_SPI3EN)
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case unsafe.Pointer(stm32.SPI2): // SPI2 clock enable
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stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_SPI2EN)
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case unsafe.Pointer(stm32.WWDG): // Window watchdog clock enable
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stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_WWDGEN)
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case unsafe.Pointer(stm32.TIM7): // TIM7 clock enable
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stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM7EN)
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case unsafe.Pointer(stm32.TIM6): // TIM6 clock enable
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stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM6EN)
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case unsafe.Pointer(stm32.TIM3): // TIM3 clock enable
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stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM3EN)
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case unsafe.Pointer(stm32.TIM2): // TIM2 clock enable
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stm32.RCC.APB1ENR1.SetBits(stm32.RCC_APB1ENR1_TIM2EN)
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case unsafe.Pointer(stm32.LPTIM2): // LPTIM2 clock enable
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stm32.RCC.APB1ENR2.SetBits(stm32.RCC_APB1ENR2_LPTIM2EN)
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case unsafe.Pointer(stm32.LPUART1): // LPUART1 clock enable
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stm32.RCC.APB1ENR2.SetBits(stm32.RCC_APB1ENR2_LPUART1EN)
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case unsafe.Pointer(stm32.TIM16): // TIM16 clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM16EN)
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case unsafe.Pointer(stm32.TIM15): // TIM15 clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM15EN)
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case unsafe.Pointer(stm32.SYSCFG): // System configuration controller clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SYSCFGEN)
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case unsafe.Pointer(stm32.SPI1): // SPI1 clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SPI1EN)
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case unsafe.Pointer(stm32.USART1): // USART1 clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_USART1EN)
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case unsafe.Pointer(stm32.TIM1): // TIM1 clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM1EN)
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}
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}
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func handlePinInterrupt(pin uint8) {
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if stm32.EXTI.PR1.HasBits(1 << pin) {
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// Writing 1 to the pending register clears the
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// pending flag for that bit
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stm32.EXTI.PR1.Set(1 << pin)
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callback := pinCallbacks[pin]
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if callback != nil {
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callback(interruptPins[pin])
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}
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}
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}
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func (p Pin) registerInterrupt() interrupt.Interrupt {
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pin := uint8(p) % 16
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switch pin {
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case 0:
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return interrupt.New(stm32.IRQ_EXTI0, func(interrupt.Interrupt) { handlePinInterrupt(0) })
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case 1:
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return interrupt.New(stm32.IRQ_EXTI1, func(interrupt.Interrupt) { handlePinInterrupt(1) })
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case 2:
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return interrupt.New(stm32.IRQ_EXTI2, func(interrupt.Interrupt) { handlePinInterrupt(2) })
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case 3:
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return interrupt.New(stm32.IRQ_EXTI3, func(interrupt.Interrupt) { handlePinInterrupt(3) })
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case 4:
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return interrupt.New(stm32.IRQ_EXTI4, func(interrupt.Interrupt) { handlePinInterrupt(4) })
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case 5:
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return interrupt.New(stm32.IRQ_EXTI9_5, func(interrupt.Interrupt) { handlePinInterrupt(5) })
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case 6:
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return interrupt.New(stm32.IRQ_EXTI9_5, func(interrupt.Interrupt) { handlePinInterrupt(6) })
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case 7:
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return interrupt.New(stm32.IRQ_EXTI9_5, func(interrupt.Interrupt) { handlePinInterrupt(7) })
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case 8:
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return interrupt.New(stm32.IRQ_EXTI9_5, func(interrupt.Interrupt) { handlePinInterrupt(8) })
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case 9:
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return interrupt.New(stm32.IRQ_EXTI9_5, func(interrupt.Interrupt) { handlePinInterrupt(9) })
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case 10:
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return interrupt.New(stm32.IRQ_EXTI15_10, func(interrupt.Interrupt) { handlePinInterrupt(10) })
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case 11:
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return interrupt.New(stm32.IRQ_EXTI15_10, func(interrupt.Interrupt) { handlePinInterrupt(11) })
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case 12:
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return interrupt.New(stm32.IRQ_EXTI15_10, func(interrupt.Interrupt) { handlePinInterrupt(12) })
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case 13:
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return interrupt.New(stm32.IRQ_EXTI15_10, func(interrupt.Interrupt) { handlePinInterrupt(13) })
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case 14:
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return interrupt.New(stm32.IRQ_EXTI15_10, func(interrupt.Interrupt) { handlePinInterrupt(14) })
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case 15:
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return interrupt.New(stm32.IRQ_EXTI15_10, func(interrupt.Interrupt) { handlePinInterrupt(15) })
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}
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return interrupt.Interrupt{}
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}
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//---------- UART related code
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// Configure the UART.
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func (uart *UART) configurePins(config UARTConfig) {
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// enable the alternate functions on the TX and RX pins
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config.TX.ConfigureAltFunc(PinConfig{Mode: PinModeUARTTX}, uart.TxAltFuncSelector)
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config.RX.ConfigureAltFunc(PinConfig{Mode: PinModeUARTRX}, uart.RxAltFuncSelector)
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}
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// UART baudrate calc based on the bus and clockspeed
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// NOTE: keep this in sync with the runtime/runtime_stm32l5x2.go clock init code
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func (uart *UART) getBaudRateDivisor(baudRate uint32) uint32 {
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return (CPUFrequency() / baudRate)
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}
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// Register names vary by ST processor, these are for STM L5
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func (uart *UART) setRegisters() {
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uart.rxReg = &uart.Bus.RDR
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uart.txReg = &uart.Bus.TDR
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uart.statusReg = &uart.Bus.ISR
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uart.txEmptyFlag = stm32.USART_ISR_TXE
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}
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//---------- SPI related types and code
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// SPI on the STM32Fxxx using MODER / alternate function pins
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type SPI struct {
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Bus *stm32.SPI_Type
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AltFuncSelector uint8
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}
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func (spi SPI) config8Bits() {
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// Set rx threshold to 8-bits, so RXNE flag is set for 1 byte
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// (common STM32 SPI implementation does 8-bit transfers only)
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spi.Bus.CR2.SetBits(stm32.SPI_CR2_FRXTH)
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}
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// Set baud rate for SPI
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func (spi SPI) getBaudRate(config SPIConfig) uint32 {
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var conf uint32
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// Default
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if config.Frequency == 0 {
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config.Frequency = 4e6
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}
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localFrequency := config.Frequency
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// set frequency dependent on PCLK prescaler. Since these are rather weird
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// speeds due to the CPU freqency, pick a range up to that frquency for
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// clients to use more human-understandable numbers, e.g. nearest 100KHz
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// These are based on 80MHz peripheral clock frquency
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switch {
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case localFrequency < 312500:
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conf = stm32.SPI_CR1_BR_Div256
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case localFrequency < 625000:
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conf = stm32.SPI_CR1_BR_Div128
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case localFrequency < 1250000:
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conf = stm32.SPI_CR1_BR_Div64
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case localFrequency < 2500000:
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conf = stm32.SPI_CR1_BR_Div32
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case localFrequency < 5000000:
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conf = stm32.SPI_CR1_BR_Div16
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case localFrequency < 10000000:
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conf = stm32.SPI_CR1_BR_Div8
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// NOTE: many SPI components won't operate reliably (or at all) above 10MHz
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// Check the datasheet of the part
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case localFrequency < 20000000:
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conf = stm32.SPI_CR1_BR_Div4
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case localFrequency < 40000000:
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conf = stm32.SPI_CR1_BR_Div2
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default:
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// None of the specific baudrates were selected; choose the lowest speed
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conf = stm32.SPI_CR1_BR_Div256
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}
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return conf << stm32.SPI_CR1_BR_Pos
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}
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// Configure SPI pins for input output and clock
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func (spi SPI) configurePins(config SPIConfig) {
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config.SCK.ConfigureAltFunc(PinConfig{Mode: PinModeSPICLK}, spi.AltFuncSelector)
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config.SDO.ConfigureAltFunc(PinConfig{Mode: PinModeSPISDO}, spi.AltFuncSelector)
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config.SDI.ConfigureAltFunc(PinConfig{Mode: PinModeSPISDI}, spi.AltFuncSelector)
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}
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//---------- Timer related code
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var (
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TIM1 = TIM{
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EnableRegister: &stm32.RCC.APB2ENR,
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EnableFlag: stm32.RCC_APB2ENR_TIM1EN,
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Device: stm32.TIM1,
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Channels: [4]TimerChannel{
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TimerChannel{Pins: []PinFunction{
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{PA8, AF1_TIM1_2_LPTIM1},
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}},
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TimerChannel{Pins: []PinFunction{
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{PA9, AF1_TIM1_2_LPTIM1},
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}},
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TimerChannel{Pins: []PinFunction{
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{PA10, AF1_TIM1_2_LPTIM1},
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}},
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TimerChannel{Pins: []PinFunction{
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{PA11, AF1_TIM1_2_LPTIM1},
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}},
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},
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busFreq: APB2_TIM_FREQ,
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}
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TIM2 = TIM{
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EnableRegister: &stm32.RCC.APB1ENR1,
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EnableFlag: stm32.RCC_APB1ENR1_TIM2EN,
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Device: stm32.TIM2,
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Channels: [4]TimerChannel{
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TimerChannel{Pins: []PinFunction{
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{PA0, AF1_TIM1_2_LPTIM1},
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{PA5, AF1_TIM1_2_LPTIM1},
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{PA15, AF1_TIM1_2_LPTIM1},
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}},
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TimerChannel{Pins: []PinFunction{
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{PA1, AF1_TIM1_2_LPTIM1},
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{PB3, AF1_TIM1_2_LPTIM1},
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}},
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TimerChannel{Pins: []PinFunction{
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{PA2, AF1_TIM1_2_LPTIM1},
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}},
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TimerChannel{Pins: []PinFunction{
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{PA3, AF1_TIM1_2_LPTIM1},
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}},
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},
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busFreq: APB1_TIM_FREQ,
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}
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TIM3 = TIM{
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EnableRegister: &stm32.RCC.APB1ENR1,
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EnableFlag: stm32.RCC_APB1ENR1_TIM3EN,
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Device: stm32.TIM3,
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Channels: [4]TimerChannel{
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TimerChannel{Pins: []PinFunction{}},
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TimerChannel{Pins: []PinFunction{}},
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TimerChannel{Pins: []PinFunction{}},
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TimerChannel{Pins: []PinFunction{}},
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},
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busFreq: APB1_TIM_FREQ,
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}
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TIM6 = TIM{
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EnableRegister: &stm32.RCC.APB1ENR1,
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EnableFlag: stm32.RCC_APB1ENR1_TIM6EN,
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Device: stm32.TIM6,
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Channels: [4]TimerChannel{
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TimerChannel{Pins: []PinFunction{}},
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TimerChannel{Pins: []PinFunction{}},
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TimerChannel{Pins: []PinFunction{}},
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TimerChannel{Pins: []PinFunction{}},
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},
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busFreq: APB1_TIM_FREQ,
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}
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TIM7 = TIM{
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EnableRegister: &stm32.RCC.APB1ENR1,
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EnableFlag: stm32.RCC_APB1ENR1_TIM7EN,
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Device: stm32.TIM7,
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Channels: [4]TimerChannel{
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TimerChannel{Pins: []PinFunction{}},
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TimerChannel{Pins: []PinFunction{}},
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TimerChannel{Pins: []PinFunction{}},
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TimerChannel{Pins: []PinFunction{}},
|
|
},
|
|
busFreq: APB1_TIM_FREQ,
|
|
}
|
|
|
|
TIM15 = TIM{
|
|
EnableRegister: &stm32.RCC.APB2ENR,
|
|
EnableFlag: stm32.RCC_APB2ENR_TIM15EN,
|
|
Device: stm32.TIM15,
|
|
Channels: [4]TimerChannel{
|
|
TimerChannel{Pins: []PinFunction{
|
|
{PA2, AF14_TIM2_15_16_LPTIM2},
|
|
}},
|
|
TimerChannel{Pins: []PinFunction{
|
|
{PA3, AF14_TIM2_15_16_LPTIM2},
|
|
}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
},
|
|
busFreq: APB2_TIM_FREQ,
|
|
}
|
|
|
|
TIM16 = TIM{
|
|
EnableRegister: &stm32.RCC.APB2ENR,
|
|
EnableFlag: stm32.RCC_APB2ENR_TIM16EN,
|
|
Device: stm32.TIM16,
|
|
Channels: [4]TimerChannel{
|
|
TimerChannel{Pins: []PinFunction{
|
|
{PA6, AF14_TIM2_15_16_LPTIM2},
|
|
}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
},
|
|
busFreq: APB2_TIM_FREQ,
|
|
}
|
|
)
|
|
|
|
func (t *TIM) registerUPInterrupt() interrupt.Interrupt {
|
|
switch t {
|
|
case &TIM1:
|
|
return interrupt.New(irq_TIM1_UP_TIM16, TIM1.handleUPInterrupt)
|
|
case &TIM2:
|
|
return interrupt.New(irq_TIM2, TIM2.handleUPInterrupt)
|
|
case &TIM3:
|
|
return interrupt.New(irq_TIM3, TIM3.handleUPInterrupt)
|
|
case &TIM6:
|
|
return interrupt.New(irq_TIM6, TIM6.handleUPInterrupt)
|
|
case &TIM7:
|
|
return interrupt.New(irq_TIM7, TIM7.handleUPInterrupt)
|
|
case &TIM15:
|
|
return interrupt.New(irq_TIM1_BRK_TIM15, TIM15.handleUPInterrupt)
|
|
case &TIM16:
|
|
return interrupt.New(irq_TIM1_UP_TIM16, TIM16.handleUPInterrupt)
|
|
}
|
|
|
|
return interrupt.Interrupt{}
|
|
}
|
|
|
|
func (t *TIM) registerOCInterrupt() interrupt.Interrupt {
|
|
switch t {
|
|
case &TIM1:
|
|
return interrupt.New(irq_TIM1_CC, TIM1.handleUPInterrupt)
|
|
case &TIM2:
|
|
return interrupt.New(irq_TIM2, TIM2.handleOCInterrupt)
|
|
case &TIM3:
|
|
return interrupt.New(irq_TIM3, TIM3.handleOCInterrupt)
|
|
case &TIM6:
|
|
return interrupt.New(irq_TIM6, TIM6.handleOCInterrupt)
|
|
case &TIM7:
|
|
return interrupt.New(irq_TIM7, TIM7.handleOCInterrupt)
|
|
case &TIM15:
|
|
return interrupt.New(irq_TIM1_BRK_TIM15, TIM15.handleOCInterrupt)
|
|
case &TIM16:
|
|
return interrupt.New(irq_TIM1_UP_TIM16, TIM16.handleOCInterrupt)
|
|
}
|
|
|
|
return interrupt.Interrupt{}
|
|
}
|
|
|
|
func (t *TIM) enableMainOutput() {
|
|
// nothing to do - no BDTR register
|
|
}
|
|
|
|
type arrtype = uint32
|
|
type arrRegType = volatile.Register32
|
|
|
|
const (
|
|
ARR_MAX = 0x10000
|
|
PSC_MAX = 0x10000
|
|
)
|
|
|
|
func initRNG() {
|
|
stm32.RCC.CRRCR.SetBits(stm32.RCC_CRRCR_HSI48ON)
|
|
for !stm32.RCC.CRRCR.HasBits(stm32.RCC_CRRCR_HSI48RDY) {
|
|
}
|
|
|
|
stm32.RCC.AHB2ENR.SetBits(stm32.RCC_AHB2ENR_RNGEN)
|
|
stm32.RNG.CR.SetBits(stm32.RNG_CR_RNGEN)
|
|
}
|