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tinygo/src/device/avr/at90pwm216.go
Ayke van Laethem 90fb0ee4eb
Add AVR support 
This requires support in LLVM, as AVR support is still experimental. For
example, in bindings/go/build.sh, add
-DLLVM_EXPERIMENTAL_TARGETS_TO_BUILD=AVR to cmake_flags.
2018-06-07 18:35:54 +02:00

934 строки
30 КиБ
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// Automatically generated file. DO NOT EDIT.
// Generated by gen-device.py from AT90PWM216.atdf, see http://packs.download.atmel.com/
// +build avr,at90pwm216
// Device information for the AT90PWM216.
//
package avr
// Magic type name for the compiler.
type __reg uint8
// Export this magic type name.
type RegValue = __reg
// Some information about this device.
const (
DEVICE = "AT90PWM216"
ARCH = "AVR8"
FAMILY = "megaAVR"
)
// Interrupts
const (
IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset
IRQ_PSC2_CAPT = 1 // PSC2 Capture Event
IRQ_PSC2_EC = 2 // PSC2 End Cycle
IRQ_PSC1_CAPT = 3 // PSC1 Capture Event
IRQ_PSC1_EC = 4 // PSC1 End Cycle
IRQ_PSC0_CAPT = 5 // PSC0 Capture Event
IRQ_PSC0_EC = 6 // PSC0 End Cycle
IRQ_ANALOG_COMP_0 = 7 // Analog Comparator 0
IRQ_ANALOG_COMP_1 = 8 // Analog Comparator 1
IRQ_ANALOG_COMP_2 = 9 // Analog Comparator 2
IRQ_INT0 = 10 // External Interrupt Request 0
IRQ_TIMER1_CAPT = 11 // Timer/Counter1 Capture Event
IRQ_TIMER1_COMPA = 12 // Timer/Counter1 Compare Match A
IRQ_TIMER1_COMPB = 13 // Timer/Counter Compare Match B
IRQ_RESERVED15 = 14 //
IRQ_TIMER1_OVF = 15 // Timer/Counter1 Overflow
IRQ_TIMER0_COMP_A = 16 // Timer/Counter0 Compare Match A
IRQ_TIMER0_OVF = 17 // Timer/Counter0 Overflow
IRQ_ADC = 18 // ADC Conversion Complete
IRQ_INT1 = 19 // External Interrupt Request 1
IRQ_SPI_STC = 20 // SPI Serial Transfer Complete
IRQ_USART_RX = 21 // USART, Rx Complete
IRQ_USART_UDRE = 22 // USART Data Register Empty
IRQ_USART_TX = 23 // USART, Tx Complete
IRQ_INT2 = 24 // External Interrupt Request 2
IRQ_WDT = 25 // Watchdog Timeout Interrupt
IRQ_EE_READY = 26 // EEPROM Ready
IRQ_TIMER0_COMPB = 27 // Timer Counter 0 Compare Match B
IRQ_INT3 = 28 // External Interrupt Request 3
IRQ_RESERVED30 = 29 //
IRQ_RESERVED31 = 30 //
IRQ_SPM_READY = 31 // Store Program Memory Read
IRQ_max = 31 // Highest interrupt number on this device.
)
// Peripherals
var (
// Fuses
FUSE = struct {
EXTENDED __reg
HIGH __reg
LOW __reg
}{
EXTENDED: 0x2,
HIGH: 0x1,
LOW: 0x0,
}
// Lockbits
LOCKBIT = struct {
LOCKBIT __reg
}{
LOCKBIT: 0x0,
}
// I/O Port
PORT = struct {
PORTB __reg
DDRB __reg
PINB __reg
PORTD __reg
DDRD __reg
PIND __reg
PORTE __reg
DDRE __reg
PINE __reg
}{
PORTB: 0x25, // Port B Data Register
DDRB: 0x24, // Port B Data Direction Register
PINB: 0x23, // Port B Input Pins
PORTD: 0x2b, // Port D Data Register
DDRD: 0x2a, // Port D Data Direction Register
PIND: 0x29, // Port D Input Pins
PORTE: 0x2e, // Port E Data Register
DDRE: 0x2d, // Port E Data Direction Register
PINE: 0x2c, // Port E Input Pins
}
// Bootloader
BOOT_LOAD = struct {
SPMCSR __reg
}{
SPMCSR: 0x57, // Store Program Memory Control Register
}
// Extended USART
EUSART = struct {
EUDR __reg
EUCSRA __reg
EUCSRB __reg
EUCSRC __reg
MUBRRH __reg
MUBRRL __reg
}{
EUDR: 0xce, // EUSART I/O Data Register
EUCSRA: 0xc8, // EUSART Control and Status Register A
EUCSRB: 0xc9, // EUSART Control Register B
EUCSRC: 0xca, // EUSART Status Register C
MUBRRH: 0xcd, // Manchester Receiver Baud Rate Register High Byte
MUBRRL: 0xcc, // Manchester Receiver Baud Rate Register Low Byte
}
// Analog Comparator
AC = struct {
AC0CON __reg
AC1CON __reg
AC2CON __reg
ACSR __reg
}{
AC0CON: 0xad, // Analog Comparator 0 Control Register
AC1CON: 0xae, // Analog Comparator 1 Control Register
AC2CON: 0xaf, // Analog Comparator 2 Control Register
ACSR: 0x50, // Analog Comparator Status Register
}
// Digital-to-Analog Converter
DAC = struct {
DACL __reg
DACH __reg
DACON __reg
}{
DACL: 0xab, // DAC Data Register Bytes
DACH: 0xab, // DAC Data Register Bytes
DACON: 0xaa, // DAC Control Register
}
// CPU Registers
CPU = struct {
SREG __reg
SPL __reg
SPH __reg
MCUCR __reg
MCUSR __reg
OSCCAL __reg
CLKPR __reg
SMCR __reg
GPIOR3 __reg
GPIOR2 __reg
GPIOR1 __reg
GPIOR0 __reg
PLLCSR __reg
PRR __reg
}{
SREG: 0x5f, // Status Register
SPL: 0x5d, // Stack Pointer
SPH: 0x5d, // Stack Pointer
MCUCR: 0x55, // MCU Control Register
MCUSR: 0x54, // MCU Status Register
OSCCAL: 0x66, // Oscillator Calibration Value
CLKPR: 0x61,
SMCR: 0x53, // Sleep Mode Control Register
GPIOR3: 0x3b, // General Purpose IO Register 3
GPIOR2: 0x3a, // General Purpose IO Register 2
GPIOR1: 0x39, // General Purpose IO Register 1
GPIOR0: 0x3e, // General Purpose IO Register 0
PLLCSR: 0x49, // PLL Control And Status Register
PRR: 0x64, // Power Reduction Register
}
// Timer/Counter, 8-bit
TC8 = struct {
TIMSK0 __reg
TIFR0 __reg
TCCR0A __reg
TCCR0B __reg
TCNT0 __reg
OCR0A __reg
OCR0B __reg
}{
TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register
TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register
TCCR0A: 0x44, // Timer/Counter Control Register A
TCCR0B: 0x45, // Timer/Counter Control Register B
TCNT0: 0x46, // Timer/Counter0
OCR0A: 0x47, // Timer/Counter0 Output Compare Register
OCR0B: 0x48, // Timer/Counter0 Output Compare Register
}
// Timer/Counter, 16-bit
TC16 = struct {
TIMSK1 __reg
TIFR1 __reg
TCCR1A __reg
TCCR1B __reg
TCCR1C __reg
TCNT1L __reg
TCNT1H __reg
OCR1AL __reg
OCR1AH __reg
OCR1BL __reg
OCR1BH __reg
ICR1L __reg
ICR1H __reg
}{
TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register
TIFR1: 0x36, // Timer/Counter Interrupt Flag register
TCCR1A: 0x80, // Timer/Counter1 Control Register A
TCCR1B: 0x81, // Timer/Counter1 Control Register B
TCCR1C: 0x82, // Timer/Counter1 Control Register C
TCNT1L: 0x84, // Timer/Counter1 Bytes
TCNT1H: 0x84, // Timer/Counter1 Bytes
OCR1AL: 0x88, // Timer/Counter1 Output Compare Register Bytes
OCR1AH: 0x88, // Timer/Counter1 Output Compare Register Bytes
OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register Bytes
OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register Bytes
ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes
ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes
}
// Analog-to-Digital Converter
ADC = struct {
ADMUX __reg
ADCSRA __reg
ADCL __reg
ADCH __reg
ADCSRB __reg
DIDR0 __reg
DIDR1 __reg
AMP0CSR __reg
AMP1CSR __reg
}{
ADMUX: 0x7c, // The ADC multiplexer Selection Register
ADCSRA: 0x7a, // The ADC Control and Status register
ADCL: 0x78, // ADC Data Register Bytes
ADCH: 0x78, // ADC Data Register Bytes
ADCSRB: 0x7b, // ADC Control and Status Register B
DIDR0: 0x7e, // Digital Input Disable Register 0
DIDR1: 0x7f, // Digital Input Disable Register 1
AMP0CSR: 0x76,
AMP1CSR: 0x77,
}
// USART
USART = struct {
UDR __reg
UCSRA __reg
UCSRB __reg
UCSRC __reg
UBRRH __reg
UBRRL __reg
}{
UDR: 0xc6, // USART I/O Data Register
UCSRA: 0xc0, // USART Control and Status register A
UCSRB: 0xc1, // USART Control an Status register B
UCSRC: 0xc2, // USART Control an Status register C
UBRRH: 0xc5, // USART Baud Rate Register High Byte
UBRRL: 0xc4, // USART Baud Rate Register Low Byte
}
// Serial Peripheral Interface
SPI = struct {
SPCR __reg
SPSR __reg
SPDR __reg
}{
SPCR: 0x4c, // SPI Control Register
SPSR: 0x4d, // SPI Status Register
SPDR: 0x4e, // SPI Data Register
}
// Watchdog Timer
WDT = struct {
WDTCSR __reg
}{
WDTCSR: 0x60, // Watchdog Timer Control Register
}
// External Interrupts
EXINT = struct {
EICRA __reg
EIMSK __reg
EIFR __reg
}{
EICRA: 0x69, // External Interrupt Control Register A
EIMSK: 0x3d, // External Interrupt Mask Register
EIFR: 0x3c, // External Interrupt Flag Register
}
// EEPROM
EEPROM = struct {
EEARL __reg
EEARH __reg
EEDR __reg
EECR __reg
}{
EEARL: 0x41, // EEPROM Read/Write Access Bytes
EEARH: 0x41, // EEPROM Read/Write Access Bytes
EEDR: 0x40, // EEPROM Data Register
EECR: 0x3f, // EEPROM Control Register
}
// Power Stage Controller
PSC = struct {
PICR0L __reg
PICR0H __reg
PFRC0B __reg
PFRC0A __reg
PCTL0 __reg
PCNF0 __reg
OCR0RBL __reg
OCR0RBH __reg
OCR0SBL __reg
OCR0SBH __reg
OCR0RAL __reg
OCR0RAH __reg
OCR0SAL __reg
OCR0SAH __reg
PSOC0 __reg
PIM0 __reg
PIFR0 __reg
PICR2L __reg
PICR2H __reg
PFRC2B __reg
PFRC2A __reg
PCTL2 __reg
PCNF2 __reg
OCR2RBL __reg
OCR2RBH __reg
OCR2SBL __reg
OCR2SBH __reg
OCR2RAL __reg
OCR2RAH __reg
OCR2SAL __reg
OCR2SAH __reg
POM2 __reg
PSOC2 __reg
PIM2 __reg
PIFR2 __reg
}{
PICR0L: 0xde, // PSC 0 Input Capture Register
PICR0H: 0xde, // PSC 0 Input Capture Register
PFRC0B: 0xdd, // PSC 0 Input B Control
PFRC0A: 0xdc, // PSC 0 Input A Control
PCTL0: 0xdb, // PSC 0 Control Register
PCNF0: 0xda, // PSC 0 Configuration Register
OCR0RBL: 0xd8, // Output Compare RB Register
OCR0RBH: 0xd8, // Output Compare RB Register
OCR0SBL: 0xd6, // Output Compare SB Register
OCR0SBH: 0xd6, // Output Compare SB Register
OCR0RAL: 0xd4, // Output Compare RA Register
OCR0RAH: 0xd4, // Output Compare RA Register
OCR0SAL: 0xd2, // Output Compare SA Register
OCR0SAH: 0xd2, // Output Compare SA Register
PSOC0: 0xd0, // PSC0 Synchro and Output Configuration
PIM0: 0xa1, // PSC0 Interrupt Mask Register
PIFR0: 0xa0, // PSC0 Interrupt Flag Register
PICR2L: 0xfe, // PSC 2 Input Capture Register
PICR2H: 0xfe, // PSC 2 Input Capture Register
PFRC2B: 0xfd, // PSC 2 Input B Control
PFRC2A: 0xfc, // PSC 2 Input B Control
PCTL2: 0xfb, // PSC 2 Control Register
PCNF2: 0xfa, // PSC 2 Configuration Register
OCR2RBL: 0xf8, // Output Compare RB Register
OCR2RBH: 0xf8, // Output Compare RB Register
OCR2SBL: 0xf6, // Output Compare SB Register
OCR2SBH: 0xf6, // Output Compare SB Register
OCR2RAL: 0xf4, // Output Compare RA Register
OCR2RAH: 0xf4, // Output Compare RA Register
OCR2SAL: 0xf2, // Output Compare SA Register
OCR2SAH: 0xf2, // Output Compare SA Register
POM2: 0xf1, // PSC 2 Output Matrix
PSOC2: 0xf0, // PSC2 Synchro and Output Configuration
PIM2: 0xa5, // PSC2 Interrupt Mask Register
PIFR2: 0xa4, // PSC2 Interrupt Flag Register
}
)
// Bitfields for FUSE: Fuses
const (
// EXTENDED
EXTENDED_PSC2RB = 0x80 // PSC2 Reset Behavior
EXTENDED_PSC1RB = 0x40 // PSC1 Reset Behavior
EXTENDED_PSC0RB = 0x20 // PSC0 Reset Behavior
EXTENDED_PSCRV = 0x10 // PSCOUT Reset Value
EXTENDED_BOOTSZ = 0x6 // Select Boot Size
EXTENDED_BOOTRST = 0x1 // Select Reset Vector
// HIGH
HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PC6 as i/o pin)
HIGH_DWEN = 0x40 // Debug Wire enable
HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled
HIGH_WDTON = 0x10 // Watch-dog Timer always on
HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle
HIGH_BODLEVEL = 0x7 // Brown-out Detector Trigger Level
// LOW
LOW_CKDIV8 = 0x80 // Divide clock by 8 internally
LOW_CKOUT = 0x40 // Clock output on PORTB0
LOW_SUT_CKSEL = 0x3f // Select Clock Source
)
// Bitfields for LOCKBIT: Lockbits
const (
// LOCKBIT
LOCKBIT_LB = 0x3 // Memory Lock
LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode
LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode
)
// Bitfields for BOOT_LOAD: Bootloader
const (
// SPMCSR: Store Program Memory Control Register
SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable
SPMCSR_RWWSB = 0x40 // Read While Write Section Busy
SPMCSR_RWWSRE = 0x10 // Read While Write section read enable
SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set
SPMCSR_PGWRT = 0x4 // Page Write
SPMCSR_PGERS = 0x2 // Page Erase
SPMCSR_SPMEN = 0x1 // Store Program Memory Enable
)
// Bitfields for EUSART: Extended USART
const (
// EUCSRA: EUSART Control and Status Register A
EUCSRA_UTxS = 0xf0 // EUSART Control and Status Register A Bits
EUCSRA_URxS = 0xf // EUSART Control and Status Register A Bits
// EUCSRB: EUSART Control Register B
EUCSRB_EUSART = 0x10 // EUSART Enable Bit
EUCSRB_EUSBS = 0x8 // EUSBS Enable Bit
EUCSRB_EMCH = 0x2 // Manchester Mode Bit
EUCSRB_BODR = 0x1 // Order Bit
// EUCSRC: EUSART Status Register C
EUCSRC_FEM = 0x8 // Frame Error Manchester Bit
EUCSRC_F1617 = 0x4 // F1617 Bit
EUCSRC_STP = 0x3 // Stop Bits
// MUBRRH: Manchester Receiver Baud Rate Register High Byte
MUBRRH_MUBRR = 0xff // Manchester Receiver Baud Rate Register Bits
// MUBRRL: Manchester Receiver Baud Rate Register Low Byte
MUBRRL_MUBRR = 0xff // Manchester Receiver Baud Rate Register Bits
)
// Bitfields for AC: Analog Comparator
const (
// AC0CON: Analog Comparator 0 Control Register
AC0CON_AC0EN = 0x80 // Analog Comparator 0 Enable Bit
AC0CON_AC0IE = 0x40 // Analog Comparator 0 Interrupt Enable Bit
AC0CON_AC0IS = 0x30 // Analog Comparator 0 Interrupt Select Bit
AC0CON_AC0M = 0x7 // Analog Comparator 0 Multiplexer Register
// AC1CON: Analog Comparator 1 Control Register
AC1CON_AC1EN = 0x80 // Analog Comparator 1 Enable Bit
AC1CON_AC1IE = 0x40 // Analog Comparator 1 Interrupt Enable Bit
AC1CON_AC1IS = 0x30 // Analog Comparator 1 Interrupt Select Bit
AC1CON_AC1ICE = 0x8 // Analog Comparator 1 Interrupt Capture Enable Bit
AC1CON_AC1M = 0x7 // Analog Comparator 1 Multiplexer Register
// AC2CON: Analog Comparator 2 Control Register
AC2CON_AC2EN = 0x80 // Analog Comparator 2 Enable Bit
AC2CON_AC2IE = 0x40 // Analog Comparator 2 Interrupt Enable Bit
AC2CON_AC2IS = 0x30 // Analog Comparator 2 Interrupt Select Bit
AC2CON_AC2M = 0x7 // Analog Comparator 2 Multiplexer Register
// ACSR: Analog Comparator Status Register
ACSR_ACCKDIV = 0x80 // Analog Comparator Clock Divider
ACSR_AC2IF = 0x40 // Analog Comparator 2 Interrupt Flag Bit
ACSR_AC1IF = 0x20 // Analog Comparator 1 Interrupt Flag Bit
ACSR_AC0IF = 0x10 // Analog Comparator 0 Interrupt Flag Bit
ACSR_AC2O = 0x4 // Analog Comparator 2 Output Bit
ACSR_AC1O = 0x2 // Analog Comparator 1 Output Bit
ACSR_AC0O = 0x1 // Analog Comparator 0 Output Bit
)
// Bitfields for DAC: Digital-to-Analog Converter
const (
// DACL: DAC Data Register Bytes
// DACH: DAC Data Register Bytes
DAC_DAC = 0xffff // DAC Data Register Bits
// DACON: DAC Control Register
DACON_DAATE = 0x80 // DAC Auto Trigger Enable Bit
DACON_DATS = 0x70 // DAC Trigger Selection Bits
DACON_DALA = 0x4 // DAC Left Adjust
DACON_DAOE = 0x2 // DAC Output Enable
DACON_DAEN = 0x1 // DAC Enable Bit
)
// Bitfields for CPU: CPU Registers
const (
// SREG: Status Register
SREG_I = 0x80 // Global Interrupt Enable
SREG_T = 0x40 // Bit Copy Storage
SREG_H = 0x20 // Half Carry Flag
SREG_S = 0x10 // Sign Bit
SREG_V = 0x8 // Two's Complement Overflow Flag
SREG_N = 0x4 // Negative Flag
SREG_Z = 0x2 // Zero Flag
SREG_C = 0x1 // Carry Flag
// MCUCR: MCU Control Register
MCUCR_SPIPS = 0x80 // SPI Pin Select
MCUCR_PUD = 0x10 // Pull-up disable
MCUCR_IVSEL = 0x2 // Interrupt Vector Select
MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable
// MCUSR: MCU Status Register
MCUSR_WDRF = 0x8 // Watchdog Reset Flag
MCUSR_BORF = 0x4 // Brown-out Reset Flag
MCUSR_EXTRF = 0x2 // External Reset Flag
MCUSR_PORF = 0x1 // Power-on reset flag
// OSCCAL: Oscillator Calibration Value
OSCCAL_OSCCAL = 0xff // Oscillator Calibration
// CLKPR
CLKPR_CLKPCE = 0x80
CLKPR_CLKPS = 0xf
// SMCR: Sleep Mode Control Register
SMCR_SM = 0xe // Sleep Mode Select bits
SMCR_SE = 0x1 // Sleep Enable
// GPIOR3: General Purpose IO Register 3
GPIOR3_GPIOR = 0xff // General Purpose IO Register 3 bis
// GPIOR2: General Purpose IO Register 2
GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis
// GPIOR1: General Purpose IO Register 1
GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis
// GPIOR0: General Purpose IO Register 0
GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7
GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6
GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5
GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4
GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3
GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2
GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1
GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0
// PLLCSR: PLL Control And Status Register
PLLCSR_PLLF = 0x4 // PLL Factor
PLLCSR_PLLE = 0x2 // PLL Enable
PLLCSR_PLOCK = 0x1 // PLL Lock Detector
// PRR: Power Reduction Register
PRR_PRPSC2 = 0x80 // Power Reduction PSC2
PRR_PRPSC1 = 0x40 // Power Reduction PSC1
PRR_PRPSC0 = 0x20 // Power Reduction PSC0
PRR_PRTIM1 = 0x10 // Power Reduction Timer/Counter1
PRR_PRTIM0 = 0x8 // Power Reduction Timer/Counter0
PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface
PRR_PRUSART0 = 0x2 // Power Reduction USART
PRR_PRADC = 0x1 // Power Reduction ADC
)
// Bitfields for TC8: Timer/Counter, 8-bit
const (
// TIMSK0: Timer/Counter0 Interrupt Mask Register
TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable
TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable
TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable
// TIFR0: Timer/Counter0 Interrupt Flag register
TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B
TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A
TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag
// TCCR0A: Timer/Counter Control Register A
TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode
TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm
TCCR0A_WGM0 = 0x3 // Waveform Generation Mode
// TCCR0B: Timer/Counter Control Register B
TCCR0B_FOC0A = 0x80 // Force Output Compare A
TCCR0B_FOC0B = 0x40 // Force Output Compare B
TCCR0B_WGM02 = 0x8
TCCR0B_CS0 = 0x7 // Clock Select
// TCNT0: Timer/Counter0
TCNT0_TCNT0 = 0xff // Timer Counter 0 value
// OCR0A: Timer/Counter0 Output Compare Register
OCR0A_OCR0A = 0xff // Output Compare A value
// OCR0B: Timer/Counter0 Output Compare Register
OCR0B_OCR0B = 0xff // Output Compare B value
)
// Bitfields for TC16: Timer/Counter, 16-bit
const (
// TIMSK1: Timer/Counter Interrupt Mask Register
TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable
TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output CompareB Match Interrupt Enable
TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output CompareA Match Interrupt Enable
TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable
// TIFR1: Timer/Counter Interrupt Flag register
TIFR1_ICF1 = 0x20 // Input Capture Flag 1
TIFR1_OCF1B = 0x4 // Output Compare Flag 1B
TIFR1_OCF1A = 0x2 // Output Compare Flag 1A
TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag
// TCCR1A: Timer/Counter1 Control Register A
TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits
TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits
TCCR1A_WGM1 = 0x3 // Waveform Generation Mode
// TCCR1B: Timer/Counter1 Control Register B
TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler
TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select
TCCR1B_WGM1 = 0x18 // Waveform Generation Mode
TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1
// TCCR1C: Timer/Counter1 Control Register C
TCCR1C_FOC1A = 0x80
TCCR1C_FOC1B = 0x40
// TCNT1L: Timer/Counter1 Bytes
// TCNT1H: Timer/Counter1 Bytes
TCNT1_TCNT1 = 0xffff // Timer/Counter1
// OCR1AL: Timer/Counter1 Output Compare Register Bytes
// OCR1AH: Timer/Counter1 Output Compare Register Bytes
OCR1A_OCR1A = 0xffff // Timer/Counter1 Output Compare A Register
// OCR1BL: Timer/Counter1 Output Compare Register Bytes
// OCR1BH: Timer/Counter1 Output Compare Register Bytes
OCR1B_OCR1B = 0xffff // Timer/Counter1 Output Compare B Register
// ICR1L: Timer/Counter1 Input Capture Register Bytes
// ICR1H: Timer/Counter1 Input Capture Register Bytes
ICR1_ICR1 = 0xffff // Timer/Counter Input Capture
)
// Bitfields for ADC: Analog-to-Digital Converter
const (
// ADMUX: The ADC multiplexer Selection Register
ADMUX_REFS = 0xc0 // Reference Selection Bits
ADMUX_ADLAR = 0x20 // Left Adjust Result
ADMUX_MUX = 0xf // Analog Channel and Gain Selection Bits
// ADCSRA: The ADC Control and Status register
ADCSRA_ADEN = 0x80 // ADC Enable
ADCSRA_ADSC = 0x40 // ADC Start Conversion
ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable
ADCSRA_ADIF = 0x10 // ADC Interrupt Flag
ADCSRA_ADIE = 0x8 // ADC Interrupt Enable
ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits
// ADCSRB: ADC Control and Status Register B
ADCSRB_ADHSM = 0x80 // ADC High Speed Mode
ADCSRB_ADTS3 = 0x8 // ADC Auto Trigger Source Selection 3
ADCSRB_ADTS2 = 0x4 // ADC Auto Trigger Source Selection 2
ADCSRB_ADTS1 = 0x2 // ADC Auto Trigger Source Selection 1
ADCSRB_ADTS0 = 0x1 // ADC Auto Trigger Source Selection 0
// DIDR0: Digital Input Disable Register 0
DIDR0_ADC7D = 0x80
DIDR0_ADC6D = 0x40
DIDR0_ADC5D = 0x20
DIDR0_ADC4D = 0x10
DIDR0_ADC3D = 0x8
DIDR0_ADC2D = 0x4
DIDR0_ADC1D = 0x2
DIDR0_ADC0D = 0x1
// DIDR1: Digital Input Disable Register 1
DIDR1_ACMP0D = 0x20
DIDR1_AMP0PD = 0x10
DIDR1_AMP0ND = 0x8
DIDR1_ADC10D = 0x4
DIDR1_ADC9D = 0x2
DIDR1_ADC8D = 0x1
// AMP0CSR
AMP0CSR_AMP0EN = 0x80
AMP0CSR_AMP0IS = 0x40
AMP0CSR_AMP0G = 0x30
AMP0CSR_AMP0TS = 0x3
// AMP1CSR
AMP1CSR_AMP1EN = 0x80
AMP1CSR_AMP1IS = 0x40
AMP1CSR_AMP1G = 0x30
AMP1CSR_AMP1TS = 0x3
)
// Bitfields for USART: USART
const (
// UCSRA: USART Control and Status register A
UCSRA_RXC = 0x80 // USART Receive Complete
UCSRA_TXC = 0x40 // USART Transmitt Complete
UCSRA_UDRE = 0x20 // USART Data Register Empty
UCSRA_FE = 0x10 // Framing Error
UCSRA_DOR = 0x8 // Data Overrun
UCSRA_UPE = 0x4 // USART Parity Error
UCSRA_U2X = 0x2 // Double USART Transmission Bit
UCSRA_MPCM = 0x1 // Multi-processor Communication Mode
// UCSRB: USART Control an Status register B
UCSRB_RXCIE = 0x80 // RX Complete Interrupt Enable
UCSRB_TXCIE = 0x40 // TX Complete Interrupt Enable
UCSRB_UDRIE = 0x20 // USART Data Register Empty Interrupt Enable
UCSRB_RXEN = 0x10 // Receiver Enable
UCSRB_TXEN = 0x8 // Transmitter Enable
UCSRB_UCSZ2 = 0x4 // Character Size
UCSRB_RXB8 = 0x2 // Receive Data Bit 8
UCSRB_TXB8 = 0x1 // Transmit Data Bit 8
// UCSRC: USART Control an Status register C
UCSRC_UMSEL0 = 0x40 // USART Mode Select
UCSRC_UPM = 0x30 // Parity Mode Bits
UCSRC_USBS = 0x8 // Stop Bit Select
UCSRC_UCSZ = 0x6 // Character Size Bits
UCSRC_UCPOL = 0x1 // Clock Polarity
// UBRRH: USART Baud Rate Register High Byte
UBRRH_UBRR = 0xf // USART Baud Rate Register Bits
// UBRRL: USART Baud Rate Register Low Byte
UBRRL_UBRR = 0xff // USART Baud Rate Register bits
)
// Bitfields for SPI: Serial Peripheral Interface
const (
// SPCR: SPI Control Register
SPCR_SPIE = 0x80 // SPI Interrupt Enable
SPCR_SPE = 0x40 // SPI Enable
SPCR_DORD = 0x20 // Data Order
SPCR_MSTR = 0x10 // Master/Slave Select
SPCR_CPOL = 0x8 // Clock polarity
SPCR_CPHA = 0x4 // Clock Phase
SPCR_SPR = 0x3 // SPI Clock Rate Selects
// SPSR: SPI Status Register
SPSR_SPIF = 0x80 // SPI Interrupt Flag
SPSR_WCOL = 0x40 // Write Collision Flag
SPSR_SPI2X = 0x1 // Double SPI Speed Bit
// SPDR: SPI Data Register
SPDR_SPD = 0xff // SPI Data
)
// Bitfields for WDT: Watchdog Timer
const (
// WDTCSR: Watchdog Timer Control Register
WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag
WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable
WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits
WDTCSR_WDCE = 0x10 // Watchdog Change Enable
WDTCSR_WDE = 0x8 // Watch Dog Enable
)
// Bitfields for EXINT: External Interrupts
const (
// EICRA: External Interrupt Control Register A
EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit
EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit
EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit
EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit
// EIMSK: External Interrupt Mask Register
EIMSK_INT = 0xf // External Interrupt Mask
// EIFR: External Interrupt Flag Register
EIFR_INTF = 0xf // External Interrupt Flags
)
// Bitfields for EEPROM: EEPROM
const (
// EEARL: EEPROM Read/Write Access Bytes
// EEARH: EEPROM Read/Write Access Bytes
EEAR_EEAR = 0xfff // EEPROM Address bytes
// EEDR: EEPROM Data Register
EEDR_EEDR = 0xff // EEPROM Data Bits
// EECR: EEPROM Control Register
EECR_EEPM = 0x30 // EEPROM Programming Mode
EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable
EECR_EEMWE = 0x4 // EEPROM Master Write Enable
EECR_EEWE = 0x2 // EEPROM Write Enable
EECR_EERE = 0x1 // EEPROM Read Enable
)
// Bitfields for PSC: Power Stage Controller
const (
// PICR0L: PSC 0 Input Capture Register
// PICR0H: PSC 0 Input Capture Register
PICR0_PCST0 = 0x8000 // PSC 0 Input Capture Software Trig
PICR0_PICR0 = 0xfff // PSC 0 Input Capture Bytes
// PFRC0B: PSC 0 Input B Control
PFRC0B_PCAE0B = 0x80 // PSC 0 Capture Enable Input Part B
PFRC0B_PISEL0B = 0x40 // PSC 0 Input Select for Part B
PFRC0B_PELEV0B = 0x20 // PSC 0 Edge Level Selector on Input Part B
PFRC0B_PFLTE0B = 0x10 // PSC 0 Filter Enable on Input Part B
PFRC0B_PRFM0B = 0xf // PSC 0 Retrigger and Fault Mode for Part B
// PFRC0A: PSC 0 Input A Control
PFRC0A_PCAE0A = 0x80 // PSC 0 Capture Enable Input Part A
PFRC0A_PISEL0A = 0x40 // PSC 0 Input Select for Part A
PFRC0A_PELEV0A = 0x20 // PSC 0 Edge Level Selector on Input Part A
PFRC0A_PFLTE0A = 0x10 // PSC 0 Filter Enable on Input Part A
PFRC0A_PRFM0A = 0xf // PSC 0 Retrigger and Fault Mode for Part A
// PCTL0: PSC 0 Control Register
PCTL0_PPRE0 = 0xc0 // PSC 0 Prescaler Selects
PCTL0_PBFM0 = 0x20 // PSC 0 Balance Flank Width Modulation
PCTL0_PAOC0B = 0x10 // PSC 0 Asynchronous Output Control B
PCTL0_PAOC0A = 0x8 // PSC 0 Asynchronous Output Control A
PCTL0_PARUN0 = 0x4 // PSC0 Auto Run
PCTL0_PCCYC0 = 0x2 // PSC0 Complete Cycle
PCTL0_PRUN0 = 0x1 // PSC 0 Run
// PCNF0: PSC 0 Configuration Register
PCNF0_PFIFTY0 = 0x80 // PSC 0 Fifty
PCNF0_PALOCK0 = 0x40 // PSC 0 Autolock
PCNF0_PLOCK0 = 0x20 // PSC 0 Lock
PCNF0_PMODE0 = 0x18 // PSC 0 Mode
PCNF0_POP0 = 0x4 // PSC 0 Output Polarity
PCNF0_PCLKSEL0 = 0x2 // PSC 0 Input Clock Select
// PSOC0: PSC0 Synchro and Output Configuration
PSOC0_PSYNC0 = 0x30 // Synchronization Out for ADC Selection
PSOC0_POEN0B = 0x4 // PSCOUT01 Output Enable
PSOC0_POEN0A = 0x1 // PSCOUT00 Output Enable
// PIM0: PSC0 Interrupt Mask Register
PIM0_PSEIE0 = 0x20 // PSC 0 Synchro Error Interrupt Enable
PIM0_PEVE0B = 0x10 // External Event B Interrupt Enable
PIM0_PEVE0A = 0x8 // External Event A Interrupt Enable
PIM0_PEOPE0 = 0x1 // End of Cycle Interrupt Enable
// PIFR0: PSC0 Interrupt Flag Register
PIFR0_POAC0B = 0x80 // PSC 0 Output A Activity
PIFR0_POAC0A = 0x40 // PSC 0 Output A Activity
PIFR0_PSEI0 = 0x20 // PSC 0 Synchro Error Interrupt
PIFR0_PEV0B = 0x10 // External Event B Interrupt
PIFR0_PEV0A = 0x8 // External Event A Interrupt
PIFR0_PRN0 = 0x6 // Ramp Number
PIFR0_PEOP0 = 0x1 // End of PSC0 Interrupt
// PICR2L: PSC 2 Input Capture Register
// PICR2H: PSC 2 Input Capture Register
PICR2_PCST2 = 0x8000 // PSC 2 Input Capture Software Trig
PICR2_PICR2 = 0xfff // PSC 2 Input Capture Bytes
// PFRC2B: PSC 2 Input B Control
PFRC2B_PCAE2B = 0x80 // PSC 2 Capture Enable Input Part B
PFRC2B_PISEL2B = 0x40 // PSC 2 Input Select for Part B
PFRC2B_PELEV2B = 0x20 // PSC 2 Edge Level Selector on Input Part B
PFRC2B_PFLTE2B = 0x10 // PSC 2 Filter Enable on Input Part B
PFRC2B_PRFM2B = 0xf // PSC 2 Retrigger and Fault Mode for Part B
// PFRC2A: PSC 2 Input B Control
PFRC2A_PCAE2A = 0x80 // PSC 2 Capture Enable Input Part A
PFRC2A_PISEL2A = 0x40 // PSC 2 Input Select for Part A
PFRC2A_PELEV2A = 0x20 // PSC 2 Edge Level Selector on Input Part A
PFRC2A_PFLTE2A = 0x10 // PSC 2 Filter Enable on Input Part A
PFRC2A_PRFM2A = 0xf // PSC 2 Retrigger and Fault Mode for Part A
// PCTL2: PSC 2 Control Register
PCTL2_PPRE2 = 0xc0 // PSC 2 Prescaler Selects
PCTL2_PBFM2 = 0x20 // Balance Flank Width Modulation
PCTL2_PAOC2B = 0x10 // PSC 2 Asynchronous Output Control B
PCTL2_PAOC2A = 0x8 // PSC 2 Asynchronous Output Control A
PCTL2_PARUN2 = 0x4 // PSC2 Auto Run
PCTL2_PCCYC2 = 0x2 // PSC2 Complete Cycle
PCTL2_PRUN2 = 0x1 // PSC 2 Run
// PCNF2: PSC 2 Configuration Register
PCNF2_PFIFTY2 = 0x80 // PSC 2 Fifty
PCNF2_PALOCK2 = 0x40 // PSC 2 Autolock
PCNF2_PLOCK2 = 0x20 // PSC 2 Lock
PCNF2_PMODE2 = 0x18 // PSC 2 Mode
PCNF2_POP2 = 0x4 // PSC 2 Output Polarity
PCNF2_PCLKSEL2 = 0x2 // PSC 2 Input Clock Select
PCNF2_POME2 = 0x1 // PSC 2 Output Matrix Enable
// POM2: PSC 2 Output Matrix
POM2_POMV2B = 0xf0 // Output Matrix Output B Ramps
POM2_POMV2A = 0xf // Output Matrix Output A Ramps
// PSOC2: PSC2 Synchro and Output Configuration
PSOC2_POS2 = 0xc0 // PSC 2 Output 23 Select
PSOC2_PSYNC2 = 0x30 // Synchronization Out for ADC Selection
PSOC2_POEN2D = 0x8 // PSCOUT23 Output Enable
PSOC2_POEN2B = 0x4 // PSCOUT21 Output Enable
PSOC2_POEN2C = 0x2 // PSCOUT22 Output Enable
PSOC2_POEN2A = 0x1 // PSCOUT20 Output Enable
// PIM2: PSC2 Interrupt Mask Register
PIM2_PSEIE2 = 0x20 // PSC 2 Synchro Error Interrupt Enable
PIM2_PEVE2B = 0x10 // External Event B Interrupt Enable
PIM2_PEVE2A = 0x8 // External Event A Interrupt Enable
PIM2_PEOPE2 = 0x1 // End of Cycle Interrupt Enable
// PIFR2: PSC2 Interrupt Flag Register
PIFR2_POAC2B = 0x80 // PSC 2 Output A Activity
PIFR2_POAC2A = 0x40 // PSC 2 Output A Activity
PIFR2_PSEI2 = 0x20 // PSC 2 Synchro Error Interrupt
PIFR2_PEV2B = 0x10 // External Event B Interrupt
PIFR2_PEV2A = 0x8 // External Event A Interrupt
PIFR2_PRN2 = 0x6 // Ramp Number
PIFR2_PEOP2 = 0x1 // End of PSC2 Interrupt
)
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