90fb0ee4eb
This requires support in LLVM, as AVR support is still experimental. For example, in bindings/go/build.sh, add -DLLVM_EXPERIMENTAL_TARGETS_TO_BUILD=AVR to cmake_flags.
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796 строки
26 КиБ
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// Automatically generated file. DO NOT EDIT.
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// Generated by gen-device.py from ATmega16HVBrevB.atdf, see http://packs.download.atmel.com/
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// +build avr,atmega16hvbrevb
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// Device information for the ATmega16HVBrevB.
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//
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package avr
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// Magic type name for the compiler.
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type __reg uint8
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// Export this magic type name.
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type RegValue = __reg
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// Some information about this device.
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const (
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DEVICE = "ATmega16HVBrevB"
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ARCH = "AVR8"
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FAMILY = "megaAVR"
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)
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// Interrupts
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const (
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IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset
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IRQ_BPINT = 1 // Battery Protection Interrupt
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IRQ_VREGMON = 2 // Voltage regulator monitor interrupt
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IRQ_INT0 = 3 // External Interrupt Request 0
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IRQ_INT1 = 4 // External Interrupt Request 1
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IRQ_INT2 = 5 // External Interrupt Request 2
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IRQ_INT3 = 6 // External Interrupt Request 3
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IRQ_PCINT0 = 7 // Pin Change Interrupt 0
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IRQ_PCINT1 = 8 // Pin Change Interrupt 1
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IRQ_WDT = 9 // Watchdog Timeout Interrupt
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IRQ_BGSCD = 10 // Bandgap Buffer Short Circuit Detected
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IRQ_CHDET = 11 // Charger Detect
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IRQ_TIMER1_IC = 12 // Timer 1 Input capture
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IRQ_TIMER1_COMPA = 13 // Timer 1 Compare Match A
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IRQ_TIMER1_COMPB = 14 // Timer 1 Compare Match B
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IRQ_TIMER1_OVF = 15 // Timer 1 overflow
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IRQ_TIMER0_IC = 16 // Timer 0 Input Capture
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IRQ_TIMER0_COMPA = 17 // Timer 0 Comapre Match A
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IRQ_TIMER0_COMPB = 18 // Timer 0 Compare Match B
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IRQ_TIMER0_OVF = 19 // Timer 0 Overflow
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IRQ_TWIBUSCD = 20 // Two-Wire Bus Connect/Disconnect
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IRQ_TWI = 21 // Two-Wire Serial Interface
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IRQ_SPI_STC = 22 // SPI Serial transfer complete
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IRQ_VADC = 23 // Voltage ADC Conversion Complete
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IRQ_CCADC_CONV = 24 // Coulomb Counter ADC Conversion Complete
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IRQ_CCADC_REG_CUR = 25 // Coloumb Counter ADC Regular Current
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IRQ_CCADC_ACC = 26 // Coloumb Counter ADC Accumulator
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IRQ_EE_READY = 27 // EEPROM Ready
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IRQ_SPM = 28 // SPM Ready
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IRQ_max = 28 // Highest interrupt number on this device.
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)
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// Peripherals
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var (
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// Fuses
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FUSE = struct {
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LOW __reg
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HIGH __reg
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}{
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LOW: 0x0,
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HIGH: 0x1,
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}
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// Lockbits
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LOCKBIT = struct {
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LOCKBIT __reg
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}{
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LOCKBIT: 0x0,
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}
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// Analog-to-Digital Converter
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ADC = struct {
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VADMUX __reg
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VADCL __reg
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VADCH __reg
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VADCSR __reg
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}{
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VADMUX: 0x7c, // The VADC multiplexer Selection Register
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VADCL: 0x78, // VADC Data Register Bytes
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VADCH: 0x78, // VADC Data Register Bytes
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VADCSR: 0x7a, // The VADC Control and Status register
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}
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// Watchdog Timer
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WDT = struct {
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WDTCSR __reg
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}{
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WDTCSR: 0x60, // Watchdog Timer Control Register
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}
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// FET Control
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FET = struct {
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FCSR __reg
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}{
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FCSR: 0xf0, // FET Control and Status Register
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}
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// Serial Peripheral Interface
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SPI = struct {
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SPCR __reg
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SPSR __reg
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SPDR __reg
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}{
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SPCR: 0x4c, // SPI Control Register
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SPSR: 0x4d, // SPI Status Register
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SPDR: 0x4e, // SPI Data Register
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}
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// EEPROM
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EEPROM = struct {
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EEARL __reg
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EEARH __reg
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EEDR __reg
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EECR __reg
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}{
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EEARL: 0x41, // EEPROM Read/Write Access
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EEARH: 0x41, // EEPROM Read/Write Access
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EEDR: 0x40, // EEPROM Data Register
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EECR: 0x3f, // EEPROM Control Register
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}
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// Coulomb Counter
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COULOMB_COUNTER = struct {
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CADCSRA __reg
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CADCSRB __reg
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CADCSRC __reg
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CADICL __reg
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CADICH __reg
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CADAC3 __reg
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CADAC2 __reg
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CADAC1 __reg
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CADAC0 __reg
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CADRCC __reg
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CADRDC __reg
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}{
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CADCSRA: 0xe6, // CC-ADC Control and Status Register A
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CADCSRB: 0xe7, // CC-ADC Control and Status Register B
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CADCSRC: 0xe8, // CC-ADC Control and Status Register C
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CADICL: 0xe4, // CC-ADC Instantaneous Current
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CADICH: 0xe4, // CC-ADC Instantaneous Current
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CADAC3: 0xe3, // ADC Accumulate Current
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CADAC2: 0xe2, // ADC Accumulate Current
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CADAC1: 0xe1, // ADC Accumulate Current
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CADAC0: 0xe0, // ADC Accumulate Current
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CADRCC: 0xe9, // CC-ADC Regular Charge Current
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CADRDC: 0xea, // CC-ADC Regular Discharge Current
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}
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// Two Wire Serial Interface
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TWI = struct {
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TWBCSR __reg
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TWAMR __reg
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TWBR __reg
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TWCR __reg
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TWSR __reg
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TWDR __reg
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TWAR __reg
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}{
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TWBCSR: 0xbe, // TWI Bus Control and Status Register
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TWAMR: 0xbd, // TWI (Slave) Address Mask Register
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TWBR: 0xb8, // TWI Bit Rate register
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TWCR: 0xbc, // TWI Control Register
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TWSR: 0xb9, // TWI Status Register
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TWDR: 0xbb, // TWI Data register
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TWAR: 0xba, // TWI (Slave) Address register
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}
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// External Interrupts
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EXINT = struct {
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EICRA __reg
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EIMSK __reg
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EIFR __reg
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PCICR __reg
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PCIFR __reg
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PCMSK1 __reg
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PCMSK0 __reg
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}{
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EICRA: 0x69, // External Interrupt Control Register
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EIMSK: 0x3d, // External Interrupt Mask Register
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EIFR: 0x3c, // External Interrupt Flag Register
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PCICR: 0x68, // Pin Change Interrupt Control Register
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PCIFR: 0x3b, // Pin Change Interrupt Flag Register
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PCMSK1: 0x6c, // Pin Change Enable Mask Register 1
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PCMSK0: 0x6b, // Pin Change Enable Mask Register 0
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}
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// Timer/Counter, 16-bit
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TC16 = struct {
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TCCR1B __reg
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TCCR1A __reg
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TCNT1L __reg
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TCNT1H __reg
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OCR1A __reg
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OCR1B __reg
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TIMSK1 __reg
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TIFR1 __reg
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TCCR0B __reg
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TCCR0A __reg
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TCNT0L __reg
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TCNT0H __reg
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OCR0A __reg
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OCR0B __reg
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TIMSK0 __reg
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TIFR0 __reg
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}{
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TCCR1B: 0x81, // Timer/Counter1 Control Register B
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TCCR1A: 0x80, // Timer/Counter 1 Control Register A
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TCNT1L: 0x84, // Timer Counter 1 Bytes
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TCNT1H: 0x84, // Timer Counter 1 Bytes
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OCR1A: 0x88, // Output Compare Register 1A
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OCR1B: 0x89, // Output Compare Register B
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TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register
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TIFR1: 0x36, // Timer/Counter Interrupt Flag register
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TCCR0B: 0x45, // Timer/Counter0 Control Register B
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TCCR0A: 0x44, // Timer/Counter 0 Control Register A
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TCNT0L: 0x46, // Timer Counter 0 Bytes
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TCNT0H: 0x46, // Timer Counter 0 Bytes
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OCR0A: 0x48, // Output Compare Register 0A
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OCR0B: 0x49, // Output Compare Register B
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TIMSK0: 0x6e, // Timer/Counter Interrupt Mask Register
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TIFR0: 0x35, // Timer/Counter Interrupt Flag register
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}
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// Cell Balancing
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CELL_BALANCING = struct {
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CBCR __reg
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}{
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CBCR: 0xf1, // Cell Balancing Control Register
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}
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// Battery Protection
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BATTERY_PROTECTION = struct {
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BPPLR __reg
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BPCR __reg
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BPHCTR __reg
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BPOCTR __reg
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BPSCTR __reg
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BPCHCD __reg
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BPDHCD __reg
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BPCOCD __reg
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BPDOCD __reg
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BPSCD __reg
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BPIFR __reg
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BPIMSK __reg
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}{
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BPPLR: 0xfe, // Battery Protection Parameter Lock Register
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BPCR: 0xfd, // Battery Protection Control Register
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BPHCTR: 0xfc, // Battery Protection Short-current Timing Register
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BPOCTR: 0xfb, // Battery Protection Over-current Timing Register
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BPSCTR: 0xfa, // Battery Protection Short-current Timing Register
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BPCHCD: 0xf9, // Battery Protection Charge-High-current Detection Level Register
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BPDHCD: 0xf8, // Battery Protection Discharge-High-current Detection Level Register
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BPCOCD: 0xf7, // Battery Protection Charge-Over-current Detection Level Register
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BPDOCD: 0xf6, // Battery Protection Discharge-Over-current Detection Level Register
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BPSCD: 0xf5, // Battery Protection Short-Circuit Detection Level Register
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BPIFR: 0xf3, // Battery Protection Interrupt Flag Register
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BPIMSK: 0xf2, // Battery Protection Interrupt Mask Register
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}
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// Charger Detect
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CHARGER_DETECT = struct {
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CHGDCSR __reg
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}{
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CHGDCSR: 0xd4, // Charger Detect Control and Status Register
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}
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// Voltage Regulator
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VOLTAGE_REGULATOR = struct {
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ROCR __reg
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}{
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ROCR: 0xc8, // Regulator Operating Condition Register
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}
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// Bandgap
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BANDGAP = struct {
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BGCSR __reg
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BGCRR __reg
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BGCCR __reg
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}{
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BGCSR: 0xd2, // Bandgap Control and Status Register
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BGCRR: 0xd1, // Bandgap Calibration of Resistor Ladder
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BGCCR: 0xd0, // Bandgap Calibration Register
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}
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// CPU Registers
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CPU = struct {
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SREG __reg
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SPL __reg
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SPH __reg
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MCUCR __reg
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MCUSR __reg
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FOSCCAL __reg
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OSICSR __reg
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SMCR __reg
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GPIOR2 __reg
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GPIOR1 __reg
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GPIOR0 __reg
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DIDR0 __reg
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PRR0 __reg
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CLKPR __reg
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}{
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SREG: 0x5f, // Status Register
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SPL: 0x5d, // Stack Pointer
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SPH: 0x5d, // Stack Pointer
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MCUCR: 0x55, // MCU Control Register
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MCUSR: 0x54, // MCU Status Register
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FOSCCAL: 0x66, // Fast Oscillator Calibration Value
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OSICSR: 0x37, // Oscillator Sampling Interface Control and Status Register
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SMCR: 0x53, // Sleep Mode Control Register
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GPIOR2: 0x4b, // General Purpose IO Register 2
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GPIOR1: 0x4a, // General Purpose IO Register 1
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GPIOR0: 0x3e, // General Purpose IO Register 0
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DIDR0: 0x7e, // Digital Input Disable Register
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PRR0: 0x64, // Power Reduction Register 0
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CLKPR: 0x61, // Clock Prescale Register
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}
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// I/O Port
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PORT = struct {
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PORTA __reg
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DDRA __reg
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PINA __reg
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PORTB __reg
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DDRB __reg
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PINB __reg
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PORTC __reg
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PINC __reg
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}{
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PORTA: 0x22, // Port A Data Register
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DDRA: 0x21, // Port A Data Direction Register
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PINA: 0x20, // Port A Input Pins
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PORTB: 0x25, // Port B Data Register
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DDRB: 0x24, // Port B Data Direction Register
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PINB: 0x23, // Port B Input Pins
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PORTC: 0x28, // Port C Data Register
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PINC: 0x26, // Port C Input Pins
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}
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// Bootloader
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BOOT_LOAD = struct {
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SPMCSR __reg
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}{
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SPMCSR: 0x57, // Store Program Memory Control and Status Register
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}
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)
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// Bitfields for FUSE: Fuses
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const (
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// LOW
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LOW_WDTON = 0x80 // Watch-dog Timer always on
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LOW_EESAVE = 0x40 // Preserve EEPROM through the Chip Erase cycle
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LOW_SPIEN = 0x20 // Serial program downloading (SPI) enabled
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LOW_SUT = 0x1c // Select start-up time
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LOW_OSCSEL = 0x3 // Oscillator select
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// HIGH
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HIGH_DUVRDINIT = 0x10 // DUVR mode on
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HIGH_DWEN = 0x8 // Debug Wire enable
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HIGH_BOOTSZ = 0x6 // Select Boot Size
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HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled
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)
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// Bitfields for LOCKBIT: Lockbits
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const (
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// LOCKBIT
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LOCKBIT_LB = 0x3 // Memory Lock
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LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode
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LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode
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)
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// Bitfields for ADC: Analog-to-Digital Converter
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const (
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// VADMUX: The VADC multiplexer Selection Register
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VADMUX_VADMUX = 0xf // Analog Channel and Gain Selection Bits
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// VADCL: VADC Data Register Bytes
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// VADCH: VADC Data Register Bytes
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VADC_VADC = 0xfff // VADC Data bits
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// VADCSR: The VADC Control and Status register
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VADCSR_VADEN = 0x8 // VADC Enable
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VADCSR_VADSC = 0x4 // VADC Satrt Conversion
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VADCSR_VADCCIF = 0x2 // VADC Conversion Complete Interrupt Flag
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VADCSR_VADCCIE = 0x1 // VADC Conversion Complete Interrupt Enable
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)
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// Bitfields for WDT: Watchdog Timer
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const (
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// WDTCSR: Watchdog Timer Control Register
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WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag
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WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable
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WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits
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WDTCSR_WDCE = 0x10 // Watchdog Change Enable
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WDTCSR_WDE = 0x8 // Watch Dog Enable
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)
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// Bitfields for FET: FET Control
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const (
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// FCSR: FET Control and Status Register
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FCSR_DUVRD = 0x8 // Deep Under-Voltage Recovery Disable
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FCSR_CPS = 0x4 // Current Protection Status
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FCSR_DFE = 0x2 // Discharge FET Enable
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FCSR_CFE = 0x1 // Charge FET Enable
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)
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// Bitfields for SPI: Serial Peripheral Interface
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const (
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// SPCR: SPI Control Register
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SPCR_SPIE = 0x80 // SPI Interrupt Enable
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SPCR_SPE = 0x40 // SPI Enable
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SPCR_DORD = 0x20 // Data Order
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SPCR_MSTR = 0x10 // Master/Slave Select
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SPCR_CPOL = 0x8 // Clock polarity
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SPCR_CPHA = 0x4 // Clock Phase
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SPCR_SPR = 0x3 // SPI Clock Rate Selects
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// SPSR: SPI Status Register
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SPSR_SPIF = 0x80 // SPI Interrupt Flag
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SPSR_WCOL = 0x40 // Write Collision Flag
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SPSR_SPI2X = 0x1 // Double SPI Speed Bit
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// SPDR: SPI Data Register
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SPDR_SPDR = 0xff // SPI Data bits
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)
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// Bitfields for EEPROM: EEPROM
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const (
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// EEARL: EEPROM Read/Write Access
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// EEARH: EEPROM Read/Write Access
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EEAR_EEAR = 0x3ff // EEPROM Address bits
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// EEDR: EEPROM Data Register
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EEDR_EEDR = 0xff // EEPROM Data bits
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// EECR: EEPROM Control Register
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EECR_EEPM = 0x30
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EECR_EERIE = 0x8 // EEProm Ready Interrupt Enable
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EECR_EEMPE = 0x4 // EEPROM Master Write Enable
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EECR_EEPE = 0x2 // EEPROM Write Enable
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EECR_EERE = 0x1 // EEPROM Read Enable
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)
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// Bitfields for COULOMB_COUNTER: Coulomb Counter
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const (
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// CADCSRA: CC-ADC Control and Status Register A
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CADCSRA_CADEN = 0x80 // When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled.
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CADCSRA_CADPOL = 0x40
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CADCSRA_CADUB = 0x20 // CC_ADC Update Busy
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CADCSRA_CADAS = 0x18 // CC_ADC Accumulate Current Select Bits
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CADCSRA_CADSI = 0x6 // The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.
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CADCSRA_CADSE = 0x1 // When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode.
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// CADCSRB: CC-ADC Control and Status Register B
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CADCSRB_CADACIE = 0x40
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CADCSRB_CADRCIE = 0x20 // Regular Current Interrupt Enable
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CADCSRB_CADICIE = 0x10 // CAD Instantenous Current Interrupt Enable
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CADCSRB_CADACIF = 0x4 // CC-ADC Accumulate Current Interrupt Flag
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CADCSRB_CADRCIF = 0x2 // CC-ADC Accumulate Current Interrupt Flag
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CADCSRB_CADICIF = 0x1 // CC-ADC Instantaneous Current Interrupt Flag
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// CADCSRC: CC-ADC Control and Status Register C
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CADCSRC_CADVSE = 0x1 // CC-ADC Voltage Scaling Enable
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// CADICL: CC-ADC Instantaneous Current
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// CADICH: CC-ADC Instantaneous Current
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CADIC_CADIC = 0xffff // CC-ADC Instantaneous Current
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// CADAC3: ADC Accumulate Current
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CADAC3_CADAC = 0xff // ADC accumulate current bits
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// CADAC2: ADC Accumulate Current
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CADAC2_CADAC = 0xff // ADC accumulate current bits
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// CADAC1: ADC Accumulate Current
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CADAC1_CADAC = 0xfc // ADC accumulate current bits
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CADAC1_CADAC0 = 0x3 // ADC accumulate current bits
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// CADAC0: ADC Accumulate Current
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CADAC0_CADAC0 = 0xff // ADC accumulate current bits
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// CADRCC: CC-ADC Regular Charge Current
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CADRCC_CADRCC = 0xff // CC-ADC Regular Charge Current
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// CADRDC: CC-ADC Regular Discharge Current
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CADRDC_CADRDC = 0xff // CC-ADC Regular Discharge Current
|
|
)
|
|
|
|
// Bitfields for TWI: Two Wire Serial Interface
|
|
const (
|
|
// TWBCSR: TWI Bus Control and Status Register
|
|
TWBCSR_TWBCIF = 0x80 // TWI Bus Connect/Disconnect Interrupt Flag
|
|
TWBCSR_TWBCIE = 0x40 // TWI Bus Connect/Disconnect Interrupt Enable
|
|
TWBCSR_TWBDT = 0x6 // TWI Bus Disconnect Time-out Period
|
|
TWBCSR_TWBCIP = 0x1 // TWI Bus Connect/Disconnect Interrupt Polarity
|
|
|
|
// TWAMR: TWI (Slave) Address Mask Register
|
|
TWAMR_TWAM = 0xfe
|
|
|
|
// TWBR: TWI Bit Rate register
|
|
TWBR_TWBR = 0xff // TWI Bit Rate bits
|
|
|
|
// TWCR: TWI Control Register
|
|
TWCR_TWINT = 0x80 // TWI Interrupt Flag
|
|
TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit
|
|
TWCR_TWSTA = 0x20 // TWI Start Condition Bit
|
|
TWCR_TWSTO = 0x10 // TWI Stop Condition Bit
|
|
TWCR_TWWC = 0x8 // TWI Write Collition Flag
|
|
TWCR_TWEN = 0x4 // TWI Enable Bit
|
|
TWCR_TWIE = 0x1 // TWI Interrupt Enable
|
|
|
|
// TWSR: TWI Status Register
|
|
TWSR_TWS = 0xf8 // TWI Status
|
|
TWSR_TWPS = 0x3 // TWI Prescaler
|
|
|
|
// TWDR: TWI Data register
|
|
TWDR_TWD = 0xff // TWI Data Bits
|
|
|
|
// TWAR: TWI (Slave) Address register
|
|
TWAR_TWA = 0xfe // TWI (Slave) Address register Bits
|
|
TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit
|
|
)
|
|
|
|
// Bitfields for EXINT: External Interrupts
|
|
const (
|
|
// EICRA: External Interrupt Control Register
|
|
EICRA_ISC3 = 0xc0 // External Interrupt Sense Control 3 Bits
|
|
EICRA_ISC2 = 0x30 // External Interrupt Sense Control 2 Bits
|
|
EICRA_ISC1 = 0xc // External Interrupt Sense Control 1 Bits
|
|
EICRA_ISC0 = 0x3 // External Interrupt Sense Control 0 Bits
|
|
|
|
// EIMSK: External Interrupt Mask Register
|
|
EIMSK_INT = 0xf // External Interrupt Request 3 Enable
|
|
|
|
// EIFR: External Interrupt Flag Register
|
|
EIFR_INTF = 0xf // External Interrupt Flags
|
|
|
|
// PCICR: Pin Change Interrupt Control Register
|
|
PCICR_PCIE = 0x3 // Pin Change Interrupt Enables
|
|
|
|
// PCIFR: Pin Change Interrupt Flag Register
|
|
PCIFR_PCIF = 0x3 // Pin Change Interrupt Flags
|
|
|
|
// PCMSK1: Pin Change Enable Mask Register 1
|
|
PCMSK1_PCINT = 0xff // Pin Change Enable Mask
|
|
|
|
// PCMSK0: Pin Change Enable Mask Register 0
|
|
PCMSK0_PCINT = 0xf // Pin Change Enable Mask
|
|
)
|
|
|
|
// Bitfields for TC16: Timer/Counter, 16-bit
|
|
const (
|
|
// TCCR1B: Timer/Counter1 Control Register B
|
|
TCCR1B_CS = 0x7 // Clock Select1 bis
|
|
|
|
// TCCR1A: Timer/Counter 1 Control Register A
|
|
TCCR1A_TCW1 = 0x80 // Timer/Counter Width
|
|
TCCR1A_ICEN1 = 0x40 // Input Capture Mode Enable
|
|
TCCR1A_ICNC1 = 0x20 // Input Capture Noise Canceler
|
|
TCCR1A_ICES1 = 0x10 // Input Capture Edge Select
|
|
TCCR1A_ICS1 = 0x8 // Input Capture Select
|
|
TCCR1A_WGM10 = 0x1 // Waveform Generation Mode
|
|
|
|
// TCNT1L: Timer Counter 1 Bytes
|
|
|
|
// TCNT1H: Timer Counter 1 Bytes
|
|
TCNT1_TCNT1 = 0xffff // Timer Counter 1 bits
|
|
|
|
// OCR1A: Output Compare Register 1A
|
|
OCR1A_OCR1A = 0xff // Output Compare 1 A bits
|
|
|
|
// OCR1B: Output Compare Register B
|
|
OCR1B_OCR1B = 0xff // Output Compare 1 B bits
|
|
|
|
// TIMSK1: Timer/Counter Interrupt Mask Register
|
|
TIMSK1_ICIE1 = 0x8 // Timer/Counter n Input Capture Interrupt Enable
|
|
TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Interrupt Enable
|
|
TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Interrupt Enable
|
|
TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable
|
|
|
|
// TIFR1: Timer/Counter Interrupt Flag register
|
|
TIFR1_ICF1 = 0x8 // Timer/Counter 1 Input Capture Flag
|
|
TIFR1_OCF1B = 0x4 // Timer/Counter1 Output Compare Flag B
|
|
TIFR1_OCF1A = 0x2 // Timer/Counter1 Output Compare Flag A
|
|
TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag
|
|
|
|
// TCCR0B: Timer/Counter0 Control Register B
|
|
TCCR0B_CS02 = 0x4 // Clock Select0 bit 2
|
|
TCCR0B_CS01 = 0x2 // Clock Select0 bit 1
|
|
TCCR0B_CS00 = 0x1 // Clock Select0 bit 0
|
|
|
|
// TCCR0A: Timer/Counter 0 Control Register A
|
|
TCCR0A_TCW0 = 0x80 // Timer/Counter Width
|
|
TCCR0A_ICEN0 = 0x40 // Input Capture Mode Enable
|
|
TCCR0A_ICNC0 = 0x20 // Input Capture Noise Canceler
|
|
TCCR0A_ICES0 = 0x10 // Input Capture Edge Select
|
|
TCCR0A_ICS0 = 0x8 // Input Capture Select
|
|
TCCR0A_WGM00 = 0x1 // Waveform Generation Mode
|
|
|
|
// TCNT0L: Timer Counter 0 Bytes
|
|
|
|
// TCNT0H: Timer Counter 0 Bytes
|
|
TCNT0_TCNT0 = 0xffff // Timer Counter 0 bits
|
|
|
|
// OCR0A: Output Compare Register 0A
|
|
OCR0A_OCR0A = 0xff // Output Compare 0 A bits
|
|
|
|
// OCR0B: Output Compare Register B
|
|
OCR0B_OCR0B = 0xff // Output Compare 0 B bits
|
|
|
|
// TIMSK0: Timer/Counter Interrupt Mask Register
|
|
TIMSK0_ICIE0 = 0x8 // Timer/Counter n Input Capture Interrupt Enable
|
|
TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare B Interrupt Enable
|
|
TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare A Interrupt Enable
|
|
TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable
|
|
|
|
// TIFR0: Timer/Counter Interrupt Flag register
|
|
TIFR0_ICF0 = 0x8 // Timer/Counter 0 Input Capture Flag
|
|
TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag B
|
|
TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag A
|
|
TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag
|
|
)
|
|
|
|
// Bitfields for CELL_BALANCING: Cell Balancing
|
|
const (
|
|
// CBCR: Cell Balancing Control Register
|
|
CBCR_CBE = 0xf // Cell Balancing Enables
|
|
)
|
|
|
|
// Bitfields for BATTERY_PROTECTION: Battery Protection
|
|
const (
|
|
// BPPLR: Battery Protection Parameter Lock Register
|
|
BPPLR_BPPLE = 0x2 // Battery Protection Parameter Lock Enable
|
|
BPPLR_BPPL = 0x1 // Battery Protection Parameter Lock
|
|
|
|
// BPCR: Battery Protection Control Register
|
|
BPCR_EPID = 0x20 // External Protection Input Disable
|
|
BPCR_SCD = 0x10 // Short Circuit Protection Disabled
|
|
BPCR_DOCD = 0x8 // Discharge Over-current Protection Disabled
|
|
BPCR_COCD = 0x4 // Charge Over-current Protection Disabled
|
|
BPCR_DHCD = 0x2 // Discharge High-current Protection Disable
|
|
BPCR_CHCD = 0x1 // Charge High-current Protection Disable
|
|
|
|
// BPHCTR: Battery Protection Short-current Timing Register
|
|
BPHCTR_HCPT = 0x3f // Battery Protection Short-current Timing bits
|
|
|
|
// BPOCTR: Battery Protection Over-current Timing Register
|
|
BPOCTR_OCPT = 0x3f // Battery Protection Over-current Timing bits
|
|
|
|
// BPSCTR: Battery Protection Short-current Timing Register
|
|
BPSCTR_SCPT = 0x7f // Battery Protection Short-current Timing bits
|
|
|
|
// BPCHCD: Battery Protection Charge-High-current Detection Level Register
|
|
BPCHCD_CHCDL = 0xff // Battery Protection Charge-High-current Detection Level bits
|
|
|
|
// BPDHCD: Battery Protection Discharge-High-current Detection Level Register
|
|
BPDHCD_DHCDL = 0xff // Battery Protection Discharge-High-current Detection Level bits
|
|
|
|
// BPCOCD: Battery Protection Charge-Over-current Detection Level Register
|
|
BPCOCD_COCDL = 0xff // Battery Protection Charge-Over-current Detection Level bits
|
|
|
|
// BPDOCD: Battery Protection Discharge-Over-current Detection Level Register
|
|
BPDOCD_DOCDL = 0xff // Battery Protection Discharge-Over-current Detection Level bits
|
|
|
|
// BPSCD: Battery Protection Short-Circuit Detection Level Register
|
|
BPSCD_SCDL = 0xff // Battery Protection Short-Circuit Detection Level Register bits
|
|
|
|
// BPIFR: Battery Protection Interrupt Flag Register
|
|
BPIFR_SCIF = 0x10 // Short-circuit Protection Activated Interrupt Flag
|
|
BPIFR_DOCIF = 0x8 // Discharge Over-current Protection Activated Interrupt Flag
|
|
BPIFR_COCIF = 0x4 // Charge Over-current Protection Activated Interrupt Flag
|
|
BPIFR_DHCIF = 0x2 // Disharge High-current Protection Activated Interrupt
|
|
BPIFR_CHCIF = 0x1 // Charge High-current Protection Activated Interrupt
|
|
|
|
// BPIMSK: Battery Protection Interrupt Mask Register
|
|
BPIMSK_SCIE = 0x10 // Short-circuit Protection Activated Interrupt Enable
|
|
BPIMSK_DOCIE = 0x8 // Discharge Over-current Protection Activated Interrupt Enable
|
|
BPIMSK_COCIE = 0x4 // Charge Over-current Protection Activated Interrupt Enable
|
|
BPIMSK_DHCIE = 0x2 // Discharger High-current Protection Activated Interrupt
|
|
BPIMSK_CHCIE = 0x1 // Charger High-current Protection Activated Interrupt
|
|
)
|
|
|
|
// Bitfields for CHARGER_DETECT: Charger Detect
|
|
const (
|
|
// CHGDCSR: Charger Detect Control and Status Register
|
|
CHGDCSR_BATTPVL = 0x10 // BATT Pin Voltage Level
|
|
CHGDCSR_CHGDISC = 0xc // Charger Detect Interrupt Sense Control
|
|
CHGDCSR_CHGDIF = 0x2 // Charger Detect Interrupt Flag
|
|
CHGDCSR_CHGDIE = 0x1 // Charger Detect Interrupt Enable
|
|
)
|
|
|
|
// Bitfields for VOLTAGE_REGULATOR: Voltage Regulator
|
|
const (
|
|
// ROCR: Regulator Operating Condition Register
|
|
ROCR_ROCS = 0x80 // ROC Status
|
|
ROCR_ROCD = 0x10 // ROC Disable
|
|
ROCR_ROCWIF = 0x2 // ROC Warning Interrupt Flag
|
|
ROCR_ROCWIE = 0x1 // ROC Warning Interrupt Enable
|
|
)
|
|
|
|
// Bitfields for BANDGAP: Bandgap
|
|
const (
|
|
// BGCSR: Bandgap Control and Status Register
|
|
BGCSR_BGD = 0x20 // Bandgap Disable
|
|
BGCSR_BGSCDE = 0x10 // Bandgap Short Circuit Detection Enabled
|
|
BGCSR_BGSCDIF = 0x2 // Bandgap Short Circuit Detection Interrupt Flag
|
|
BGCSR_BGSCDIE = 0x1 // Bandgap Short Circuit Detection Interrupt Enable
|
|
|
|
// BGCRR: Bandgap Calibration of Resistor Ladder
|
|
BGCRR_BGCR = 0xff // Bandgap Calibration of Resistor Ladder Bits
|
|
|
|
// BGCCR: Bandgap Calibration Register
|
|
BGCCR_BGCC = 0x3f // BG Calibration of PTAT Current Bits
|
|
)
|
|
|
|
// Bitfields for CPU: CPU Registers
|
|
const (
|
|
// SREG: Status Register
|
|
SREG_I = 0x80 // Global Interrupt Enable
|
|
SREG_T = 0x40 // Bit Copy Storage
|
|
SREG_H = 0x20 // Half Carry Flag
|
|
SREG_S = 0x10 // Sign Bit
|
|
SREG_V = 0x8 // Two's Complement Overflow Flag
|
|
SREG_N = 0x4 // Negative Flag
|
|
SREG_Z = 0x2 // Zero Flag
|
|
SREG_C = 0x1 // Carry Flag
|
|
|
|
// MCUCR: MCU Control Register
|
|
MCUCR_CKOE = 0x20 // Clock Output Enable
|
|
MCUCR_PUD = 0x10 // Pull-up disable
|
|
MCUCR_IVSEL = 0x2 // Interrupt Vector Select
|
|
MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable
|
|
|
|
// MCUSR: MCU Status Register
|
|
MCUSR_OCDRF = 0x10 // OCD Reset Flag
|
|
MCUSR_WDRF = 0x8 // Watchdog Reset Flag
|
|
MCUSR_BODRF = 0x4 // Brown-out Reset Flag
|
|
MCUSR_EXTRF = 0x2 // External Reset Flag
|
|
MCUSR_PORF = 0x1 // Power-on reset flag
|
|
|
|
// FOSCCAL: Fast Oscillator Calibration Value
|
|
FOSCCAL_FCAL = 0xff // Fast Oscillator Calibration Value
|
|
|
|
// OSICSR: Oscillator Sampling Interface Control and Status Register
|
|
OSICSR_OSISEL0 = 0x10 // Oscillator Sampling Interface Select 0
|
|
OSICSR_OSIST = 0x2 // Oscillator Sampling Interface Status
|
|
OSICSR_OSIEN = 0x1 // Oscillator Sampling Interface Enable
|
|
|
|
// SMCR: Sleep Mode Control Register
|
|
SMCR_SM = 0xe // Sleep Mode Select bits
|
|
SMCR_SE = 0x1 // Sleep Enable
|
|
|
|
// GPIOR2: General Purpose IO Register 2
|
|
GPIOR2_GPIOR2 = 0xff // General Purpose IO bits
|
|
|
|
// GPIOR1: General Purpose IO Register 1
|
|
GPIOR1_GPIOR1 = 0xff // General Purpose IO bits
|
|
|
|
// GPIOR0: General Purpose IO Register 0
|
|
GPIOR0_GPIOR0 = 0xff // General Purpose IO bits
|
|
|
|
// DIDR0: Digital Input Disable Register
|
|
DIDR0_PA1DID = 0x2 // When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.
|
|
DIDR0_PA0DID = 0x1 // When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.
|
|
|
|
// PRR0: Power Reduction Register 0
|
|
PRR0_PRTWI = 0x40 // Power Reduction TWI
|
|
PRR0_PRVRM = 0x20 // Power Reduction Voltage Regulator Monitor
|
|
PRR0_PRSPI = 0x8 // Power reduction SPI
|
|
PRR0_PRTIM1 = 0x4 // Power Reduction Timer/Counter1
|
|
PRR0_PRTIM0 = 0x2 // Power Reduction Timer/Counter0
|
|
PRR0_PRVADC = 0x1 // Power Reduction V-ADC
|
|
|
|
// CLKPR: Clock Prescale Register
|
|
CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable
|
|
CLKPR_CLKPS = 0x3 // Clock Prescaler Select Bits
|
|
)
|
|
|
|
// Bitfields for BOOT_LOAD: Bootloader
|
|
const (
|
|
// SPMCSR: Store Program Memory Control and Status Register
|
|
SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable
|
|
SPMCSR_RWWSB = 0x40 // Read-While-Write Section Busy
|
|
SPMCSR_SIGRD = 0x20 // Signature Row Read
|
|
SPMCSR_RWWSRE = 0x10 // Read-While-Write Section Read Enable
|
|
SPMCSR_LBSET = 0x8 // Lock Bit Set
|
|
SPMCSR_PGWRT = 0x4 // Page Write
|
|
SPMCSR_PGERS = 0x2 // Page Erase
|
|
SPMCSR_SPMEN = 0x1 // Store Program Memory Enable
|
|
)
|