359 строки
9 КиБ
Go
359 строки
9 КиБ
Go
//go:build sam && atsamd21 && atsamd21e18
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// Peripheral abstraction layer for the atsamd21.
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//
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// Datasheet:
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// http://ww1.microchip.com/downloads/en/DeviceDoc/SAMD21-Family-DataSheet-DS40001882D.pdf
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package machine
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import (
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"device/sam"
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"runtime/interrupt"
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)
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var (
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sercomUSART0 = UART{Buffer: NewRingBuffer(), Bus: sam.SERCOM0_USART, SERCOM: 0}
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sercomUSART1 = UART{Buffer: NewRingBuffer(), Bus: sam.SERCOM1_USART, SERCOM: 1}
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sercomUSART2 = UART{Buffer: NewRingBuffer(), Bus: sam.SERCOM2_USART, SERCOM: 2}
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sercomUSART3 = UART{Buffer: NewRingBuffer(), Bus: sam.SERCOM3_USART, SERCOM: 3}
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sercomI2CM0 = &I2C{Bus: sam.SERCOM0_I2CM, SERCOM: 0}
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sercomI2CM1 = &I2C{Bus: sam.SERCOM1_I2CM, SERCOM: 1}
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sercomI2CM2 = &I2C{Bus: sam.SERCOM2_I2CM, SERCOM: 2}
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sercomI2CM3 = &I2C{Bus: sam.SERCOM3_I2CM, SERCOM: 3}
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sercomSPIM0 = SPI{Bus: sam.SERCOM0_SPI, SERCOM: 0}
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sercomSPIM1 = SPI{Bus: sam.SERCOM1_SPI, SERCOM: 1}
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sercomSPIM2 = SPI{Bus: sam.SERCOM2_SPI, SERCOM: 2}
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sercomSPIM3 = SPI{Bus: sam.SERCOM3_SPI, SERCOM: 3}
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)
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func init() {
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sercomUSART0.Interrupt = interrupt.New(sam.IRQ_SERCOM0, sercomUSART0.handleInterrupt)
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sercomUSART1.Interrupt = interrupt.New(sam.IRQ_SERCOM1, sercomUSART1.handleInterrupt)
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sercomUSART2.Interrupt = interrupt.New(sam.IRQ_SERCOM2, sercomUSART2.handleInterrupt)
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sercomUSART3.Interrupt = interrupt.New(sam.IRQ_SERCOM3, sercomUSART3.handleInterrupt)
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}
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// Return the register and mask to enable a given GPIO pin. This can be used to
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// implement bit-banged drivers.
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func (p Pin) PortMaskSet() (*uint32, uint32) {
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return &sam.PORT.OUTSET0.Reg, 1 << uint8(p)
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}
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// Return the register and mask to disable a given port. This can be used to
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// implement bit-banged drivers.
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func (p Pin) PortMaskClear() (*uint32, uint32) {
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return &sam.PORT.OUTCLR0.Reg, 1 << uint8(p)
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}
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// Set the pin to high or low.
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// Warning: only use this on an output pin!
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func (p Pin) Set(high bool) {
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if high {
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sam.PORT.OUTSET0.Set(1 << uint8(p))
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} else {
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sam.PORT.OUTCLR0.Set(1 << uint8(p))
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}
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}
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// Get returns the current value of a GPIO pin when configured as an input or as
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// an output.
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func (p Pin) Get() bool {
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return (sam.PORT.IN0.Get()>>uint8(p))&1 > 0
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}
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// Configure this pin with the given configuration.
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func (p Pin) Configure(config PinConfig) {
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switch config.Mode {
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case PinOutput:
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sam.PORT.DIRSET0.Set(1 << uint8(p))
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// output is also set to input enable so pin can read back its own value
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p.setPinCfg(sam.PORT_PINCFG0_INEN)
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case PinInput:
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sam.PORT.DIRCLR0.Set(1 << uint8(p))
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p.setPinCfg(sam.PORT_PINCFG0_INEN)
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case PinInputPulldown:
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sam.PORT.DIRCLR0.Set(1 << uint8(p))
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sam.PORT.OUTCLR0.Set(1 << uint8(p))
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p.setPinCfg(sam.PORT_PINCFG0_INEN | sam.PORT_PINCFG0_PULLEN)
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case PinInputPullup:
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sam.PORT.DIRCLR0.Set(1 << uint8(p))
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sam.PORT.OUTSET0.Set(1 << uint8(p))
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p.setPinCfg(sam.PORT_PINCFG0_INEN | sam.PORT_PINCFG0_PULLEN)
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case PinSERCOM:
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if uint8(p)&1 > 0 {
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// odd pin, so save the even pins
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val := p.getPMux() & sam.PORT_PMUX0_PMUXE_Msk
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p.setPMux(val | (uint8(PinSERCOM) << sam.PORT_PMUX0_PMUXO_Pos))
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} else {
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// even pin, so save the odd pins
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val := p.getPMux() & sam.PORT_PMUX0_PMUXO_Msk
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p.setPMux(val | (uint8(PinSERCOM) << sam.PORT_PMUX0_PMUXE_Pos))
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}
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// enable port config
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p.setPinCfg(sam.PORT_PINCFG0_PMUXEN | sam.PORT_PINCFG0_DRVSTR | sam.PORT_PINCFG0_INEN)
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case PinSERCOMAlt:
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if uint8(p)&1 > 0 {
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// odd pin, so save the even pins
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val := p.getPMux() & sam.PORT_PMUX0_PMUXE_Msk
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p.setPMux(val | (uint8(PinSERCOMAlt) << sam.PORT_PMUX0_PMUXO_Pos))
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} else {
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// even pin, so save the odd pins
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val := p.getPMux() & sam.PORT_PMUX0_PMUXO_Msk
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p.setPMux(val | (uint8(PinSERCOMAlt) << sam.PORT_PMUX0_PMUXE_Pos))
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}
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// enable port config
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p.setPinCfg(sam.PORT_PINCFG0_PMUXEN | sam.PORT_PINCFG0_DRVSTR)
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case PinCom:
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if uint8(p)&1 > 0 {
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// odd pin, so save the even pins
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val := p.getPMux() & sam.PORT_PMUX0_PMUXE_Msk
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p.setPMux(val | (uint8(PinCom) << sam.PORT_PMUX0_PMUXO_Pos))
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} else {
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// even pin, so save the odd pins
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val := p.getPMux() & sam.PORT_PMUX0_PMUXO_Msk
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p.setPMux(val | (uint8(PinCom) << sam.PORT_PMUX0_PMUXE_Pos))
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}
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// enable port config
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p.setPinCfg(sam.PORT_PINCFG0_PMUXEN)
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case PinAnalog:
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if uint8(p)&1 > 0 {
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// odd pin, so save the even pins
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val := p.getPMux() & sam.PORT_PMUX0_PMUXE_Msk
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p.setPMux(val | (uint8(PinAnalog) << sam.PORT_PMUX0_PMUXO_Pos))
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} else {
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// even pin, so save the odd pins
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val := p.getPMux() & sam.PORT_PMUX0_PMUXO_Msk
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p.setPMux(val | (uint8(PinAnalog) << sam.PORT_PMUX0_PMUXE_Pos))
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}
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// enable port config
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p.setPinCfg(sam.PORT_PINCFG0_PMUXEN | sam.PORT_PINCFG0_DRVSTR)
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}
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}
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// getPMux returns the value for the correct PMUX register for this pin.
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func (p Pin) getPMux() uint8 {
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switch p >> 1 {
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case 0:
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return sam.PORT.PMUX0_0.Get()
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case 1:
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return sam.PORT.PMUX0_1.Get()
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case 2:
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return sam.PORT.PMUX0_2.Get()
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case 3:
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return sam.PORT.PMUX0_3.Get()
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case 4:
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return sam.PORT.PMUX0_4.Get()
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case 5:
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return sam.PORT.PMUX0_5.Get()
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case 6:
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return sam.PORT.PMUX0_6.Get()
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case 7:
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return sam.PORT.PMUX0_7.Get()
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case 8:
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return sam.PORT.PMUX0_8.Get()
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case 9:
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return sam.PORT.PMUX0_9.Get()
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case 10:
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return sam.PORT.PMUX0_10.Get()
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case 11:
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return sam.PORT.PMUX0_11.Get()
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case 12:
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return sam.PORT.PMUX0_12.Get()
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case 13:
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return sam.PORT.PMUX0_13.Get()
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case 14:
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return sam.PORT.PMUX0_14.Get()
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case 15:
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return sam.PORT.PMUX0_15.Get()
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default:
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return 0
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}
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}
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// setPMux sets the value for the correct PMUX register for this pin.
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func (p Pin) setPMux(val uint8) {
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switch p >> 1 {
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case 0:
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sam.PORT.PMUX0_0.Set(val)
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case 1:
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sam.PORT.PMUX0_1.Set(val)
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case 2:
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sam.PORT.PMUX0_2.Set(val)
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case 3:
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sam.PORT.PMUX0_3.Set(val)
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case 4:
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sam.PORT.PMUX0_4.Set(val)
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case 5:
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sam.PORT.PMUX0_5.Set(val)
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case 6:
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sam.PORT.PMUX0_6.Set(val)
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case 7:
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sam.PORT.PMUX0_7.Set(val)
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case 8:
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sam.PORT.PMUX0_8.Set(val)
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case 9:
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sam.PORT.PMUX0_9.Set(val)
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case 10:
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sam.PORT.PMUX0_10.Set(val)
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case 11:
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sam.PORT.PMUX0_11.Set(val)
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case 12:
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sam.PORT.PMUX0_12.Set(val)
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case 13:
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sam.PORT.PMUX0_13.Set(val)
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case 14:
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sam.PORT.PMUX0_14.Set(val)
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case 15:
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sam.PORT.PMUX0_15.Set(val)
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}
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}
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// getPinCfg returns the value for the correct PINCFG register for this pin.
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func (p Pin) getPinCfg() uint8 {
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switch p {
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case 0:
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return sam.PORT.PINCFG0_0.Get()
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case 1:
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return sam.PORT.PINCFG0_1.Get()
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case 2:
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return sam.PORT.PINCFG0_2.Get()
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case 3:
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return sam.PORT.PINCFG0_3.Get()
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case 4:
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return sam.PORT.PINCFG0_4.Get()
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case 5:
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return sam.PORT.PINCFG0_5.Get()
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case 6:
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return sam.PORT.PINCFG0_6.Get()
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case 7:
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return sam.PORT.PINCFG0_7.Get()
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case 8:
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return sam.PORT.PINCFG0_8.Get()
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case 9:
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return sam.PORT.PINCFG0_9.Get()
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case 10:
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return sam.PORT.PINCFG0_10.Get()
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case 11:
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return sam.PORT.PINCFG0_11.Get()
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case 12:
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return sam.PORT.PINCFG0_12.Get()
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case 13:
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return sam.PORT.PINCFG0_13.Get()
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case 14:
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return sam.PORT.PINCFG0_14.Get()
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case 15:
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return sam.PORT.PINCFG0_15.Get()
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case 16:
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return sam.PORT.PINCFG0_16.Get()
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case 17:
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return sam.PORT.PINCFG0_17.Get()
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case 18:
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return sam.PORT.PINCFG0_18.Get()
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case 19:
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return sam.PORT.PINCFG0_19.Get()
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case 20:
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return sam.PORT.PINCFG0_20.Get()
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case 21:
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return sam.PORT.PINCFG0_21.Get()
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case 22:
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return sam.PORT.PINCFG0_22.Get()
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case 23:
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return sam.PORT.PINCFG0_23.Get()
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case 24:
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return sam.PORT.PINCFG0_24.Get()
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case 25:
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return sam.PORT.PINCFG0_25.Get()
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case 26:
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return sam.PORT.PINCFG0_26.Get()
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case 27:
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return sam.PORT.PINCFG0_27.Get()
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case 28:
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return sam.PORT.PINCFG0_28.Get()
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case 29:
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return sam.PORT.PINCFG0_29.Get()
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case 30:
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return sam.PORT.PINCFG0_30.Get()
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case 31:
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return sam.PORT.PINCFG0_31.Get()
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default:
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return 0
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}
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}
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// setPinCfg sets the value for the correct PINCFG register for this pin.
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func (p Pin) setPinCfg(val uint8) {
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switch p {
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case 0:
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sam.PORT.PINCFG0_0.Set(val)
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case 1:
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sam.PORT.PINCFG0_1.Set(val)
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case 2:
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sam.PORT.PINCFG0_2.Set(val)
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case 3:
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sam.PORT.PINCFG0_3.Set(val)
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case 4:
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sam.PORT.PINCFG0_4.Set(val)
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case 5:
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sam.PORT.PINCFG0_5.Set(val)
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case 6:
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sam.PORT.PINCFG0_6.Set(val)
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case 7:
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sam.PORT.PINCFG0_7.Set(val)
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case 8:
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sam.PORT.PINCFG0_8.Set(val)
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case 9:
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sam.PORT.PINCFG0_9.Set(val)
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case 10:
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sam.PORT.PINCFG0_10.Set(val)
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case 11:
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sam.PORT.PINCFG0_11.Set(val)
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case 12:
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sam.PORT.PINCFG0_12.Set(val)
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case 13:
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sam.PORT.PINCFG0_13.Set(val)
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case 14:
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sam.PORT.PINCFG0_14.Set(val)
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case 15:
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sam.PORT.PINCFG0_15.Set(val)
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case 16:
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sam.PORT.PINCFG0_16.Set(val)
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case 17:
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sam.PORT.PINCFG0_17.Set(val)
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case 18:
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sam.PORT.PINCFG0_18.Set(val)
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case 19:
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sam.PORT.PINCFG0_19.Set(val)
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case 20:
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sam.PORT.PINCFG0_20.Set(val)
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case 21:
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sam.PORT.PINCFG0_21.Set(val)
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case 22:
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sam.PORT.PINCFG0_22.Set(val)
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case 23:
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sam.PORT.PINCFG0_23.Set(val)
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case 24:
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sam.PORT.PINCFG0_24.Set(val)
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case 25:
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sam.PORT.PINCFG0_25.Set(val)
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case 26:
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sam.PORT.PINCFG0_26.Set(val)
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case 27:
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sam.PORT.PINCFG0_27.Set(val)
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case 28:
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sam.PORT.PINCFG0_28.Set(val)
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case 29:
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sam.PORT.PINCFG0_29.Set(val)
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case 30:
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sam.PORT.PINCFG0_30.Set(val)
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case 31:
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sam.PORT.PINCFG0_31.Set(val)
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}
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}
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