c84c625585
There was exactly one change in the output of the smoke tests: examples/test. However, it still runs just fine on a PCA10040.
314 строки
9,4 КиБ
Go
314 строки
9,4 КиБ
Go
// +build sam,atsamd21
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package runtime
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import (
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"device/arm"
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"device/sam"
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"machine"
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"runtime/volatile"
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"unsafe"
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)
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type timeUnit int64
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//go:export Reset_Handler
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func main() {
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preinit()
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initAll()
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callMain()
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abort()
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}
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func init() {
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initClocks()
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initRTC()
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initSERCOMClocks()
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initUSBClock()
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initADCClock()
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// connect to USB CDC interface
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machine.UART0.Configure(machine.UARTConfig{})
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}
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func putchar(c byte) {
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machine.UART0.WriteByte(c)
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}
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func initClocks() {
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// Set 1 Flash Wait State for 48MHz, required for 3.3V operation according to SAMD21 Datasheet
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sam.NVMCTRL.CTRLB.SetBits(sam.NVMCTRL_CTRLB_RWS_HALF << sam.NVMCTRL_CTRLB_RWS_Pos)
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// Turn on the digital interface clock
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sam.PM.APBAMASK.SetBits(sam.PM_APBAMASK_GCLK_)
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// turn off RTC
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sam.PM.APBAMASK.ClearBits(sam.PM_APBAMASK_RTC_)
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// Enable OSC32K clock (Internal 32.768Hz oscillator).
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// This requires registers that are not included in the SVD file.
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// This is from samd21g18a.h and nvmctrl.h:
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//
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// #define NVMCTRL_OTP4 0x00806020
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//
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// #define SYSCTRL_FUSES_OSC32K_CAL_ADDR (NVMCTRL_OTP4 + 4)
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// #define SYSCTRL_FUSES_OSC32K_CAL_Pos 6 /** (NVMCTRL_OTP4) OSC32K Calibration */
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// #define SYSCTRL_FUSES_OSC32K_CAL_Msk (0x7Fu << SYSCTRL_FUSES_OSC32K_CAL_Pos)
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// #define SYSCTRL_FUSES_OSC32K_CAL(value) ((SYSCTRL_FUSES_OSC32K_CAL_Msk & ((value) << SYSCTRL_FUSES_OSC32K_CAL_Pos)))
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// u32_t fuse = *(u32_t *)FUSES_OSC32K_CAL_ADDR;
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// u32_t calib = (fuse & FUSES_OSC32K_CAL_Msk) >> FUSES_OSC32K_CAL_Pos;
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fuse := *(*uint32)(unsafe.Pointer(uintptr(0x00806020) + 4))
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calib := (fuse & uint32(0x7f<<6)) >> 6
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// SYSCTRL_OSC32K_CALIB(calib) |
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// SYSCTRL_OSC32K_STARTUP(0x6u) |
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// SYSCTRL_OSC32K_EN32K | SYSCTRL_OSC32K_ENABLE;
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sam.SYSCTRL.OSC32K.Set((calib << sam.SYSCTRL_OSC32K_CALIB_Pos) |
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(0x6 << sam.SYSCTRL_OSC32K_STARTUP_Pos) |
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sam.SYSCTRL_OSC32K_EN32K |
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sam.SYSCTRL_OSC32K_EN1K |
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sam.SYSCTRL_OSC32K_ENABLE)
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// Wait for oscillator stabilization
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for !sam.SYSCTRL.PCLKSR.HasBits(sam.SYSCTRL_PCLKSR_OSC32KRDY) {
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}
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// Software reset the module to ensure it is re-initialized correctly
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sam.GCLK.CTRL.Set(sam.GCLK_CTRL_SWRST)
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// Wait for reset to complete
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for sam.GCLK.CTRL.HasBits(sam.GCLK_CTRL_SWRST) && sam.GCLK.STATUS.HasBits(sam.GCLK_STATUS_SYNCBUSY) {
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}
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// Put OSC32K as source of Generic Clock Generator 1
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sam.GCLK.GENDIV.Set((1 << sam.GCLK_GENDIV_ID_Pos) |
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(0 << sam.GCLK_GENDIV_DIV_Pos))
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waitForSync()
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// GCLK_GENCTRL_ID(1) | GCLK_GENCTRL_SRC_OSC32K | GCLK_GENCTRL_GENEN;
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sam.GCLK.GENCTRL.Set((1 << sam.GCLK_GENCTRL_ID_Pos) |
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(sam.GCLK_GENCTRL_SRC_OSC32K << sam.GCLK_GENCTRL_SRC_Pos) |
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sam.GCLK_GENCTRL_GENEN)
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waitForSync()
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// Use Generic Clock Generator 1 as source for Generic Clock Multiplexer 0 (DFLL48M reference)
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sam.GCLK.CLKCTRL.Set((sam.GCLK_CLKCTRL_ID_DFLL48 << sam.GCLK_CLKCTRL_ID_Pos) |
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(sam.GCLK_CLKCTRL_GEN_GCLK1 << sam.GCLK_CLKCTRL_GEN_Pos) |
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sam.GCLK_CLKCTRL_CLKEN)
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waitForSync()
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// Remove the OnDemand mode, Bug http://avr32.icgroup.norway.atmel.com/bugzilla/show_bug.cgi?id=9905
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sam.SYSCTRL.DFLLCTRL.Set(sam.SYSCTRL_DFLLCTRL_ENABLE)
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// Wait for ready
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for !sam.SYSCTRL.PCLKSR.HasBits(sam.SYSCTRL_PCLKSR_DFLLRDY) {
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}
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// Handle DFLL calibration based on info learned from Arduino SAMD implementation,
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// using value stored in fuse.
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// #define SYSCTRL_FUSES_DFLL48M_COARSE_CAL_ADDR (NVMCTRL_OTP4 + 4)
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// #define SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Pos 26 /**< \brief (NVMCTRL_OTP4) DFLL48M Coarse Calibration */
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// #define SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Msk (0x3Fu << SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Pos)
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// #define SYSCTRL_FUSES_DFLL48M_COARSE_CAL(value) ((SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Msk & ((value) << SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Pos)))
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coarse := (fuse >> 26) & 0x3F
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if coarse == 0x3f {
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coarse = 0x1f
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}
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sam.SYSCTRL.DFLLVAL.SetBits(coarse << sam.SYSCTRL_DFLLVAL_COARSE_Pos)
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sam.SYSCTRL.DFLLVAL.SetBits(0x1ff << sam.SYSCTRL_DFLLVAL_FINE_Pos)
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// Write full configuration to DFLL control register
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// SYSCTRL_DFLLMUL_CSTEP( 0x1f / 4 ) | // Coarse step is 31, half of the max value
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// SYSCTRL_DFLLMUL_FSTEP( 10 ) |
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// SYSCTRL_DFLLMUL_MUL( (48000) ) ;
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sam.SYSCTRL.DFLLMUL.Set(((31 / 4) << sam.SYSCTRL_DFLLMUL_CSTEP_Pos) |
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(10 << sam.SYSCTRL_DFLLMUL_FSTEP_Pos) |
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(48000 << sam.SYSCTRL_DFLLMUL_MUL_Pos))
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// disable DFLL
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sam.SYSCTRL.DFLLCTRL.Set(0)
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waitForSync()
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sam.SYSCTRL.DFLLCTRL.SetBits(sam.SYSCTRL_DFLLCTRL_MODE |
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sam.SYSCTRL_DFLLCTRL_CCDIS |
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sam.SYSCTRL_DFLLCTRL_USBCRM |
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sam.SYSCTRL_DFLLCTRL_BPLCKC)
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// Wait for ready
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for !sam.SYSCTRL.PCLKSR.HasBits(sam.SYSCTRL_PCLKSR_DFLLRDY) {
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}
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// Re-enable the DFLL
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sam.SYSCTRL.DFLLCTRL.SetBits(sam.SYSCTRL_DFLLCTRL_ENABLE)
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// Wait for ready
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for !sam.SYSCTRL.PCLKSR.HasBits(sam.SYSCTRL_PCLKSR_DFLLRDY) {
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}
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// Switch Generic Clock Generator 0 to DFLL48M. CPU will run at 48MHz.
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sam.GCLK.GENDIV.Set((0 << sam.GCLK_GENDIV_ID_Pos) |
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(0 << sam.GCLK_GENDIV_DIV_Pos))
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waitForSync()
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sam.GCLK.GENCTRL.Set((0 << sam.GCLK_GENCTRL_ID_Pos) |
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(sam.GCLK_GENCTRL_SRC_DFLL48M << sam.GCLK_GENCTRL_SRC_Pos) |
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sam.GCLK_GENCTRL_IDC |
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sam.GCLK_GENCTRL_GENEN)
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waitForSync()
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// Modify PRESCaler value of OSC8M to have 8MHz
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sam.SYSCTRL.OSC8M.SetBits(sam.SYSCTRL_OSC8M_PRESC_0 << sam.SYSCTRL_OSC8M_PRESC_Pos)
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sam.SYSCTRL.OSC8M.ClearBits(1 << sam.SYSCTRL_OSC8M_ONDEMAND_Pos)
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// Wait for oscillator stabilization
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for !sam.SYSCTRL.PCLKSR.HasBits(sam.SYSCTRL_PCLKSR_OSC8MRDY) {
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}
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// Use OSC8M as source for Generic Clock Generator 3
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sam.GCLK.GENDIV.Set((3 << sam.GCLK_GENDIV_ID_Pos))
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waitForSync()
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sam.GCLK.GENCTRL.Set((3 << sam.GCLK_GENCTRL_ID_Pos) |
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(sam.GCLK_GENCTRL_SRC_OSC8M << sam.GCLK_GENCTRL_SRC_Pos) |
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sam.GCLK_GENCTRL_GENEN)
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waitForSync()
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// Use OSC32K as source for Generic Clock Generator 2
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// OSC32K/1 -> GCLK2 at 32KHz
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sam.GCLK.GENDIV.Set(2 << sam.GCLK_GENDIV_ID_Pos)
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waitForSync()
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sam.GCLK.GENCTRL.Set((2 << sam.GCLK_GENCTRL_ID_Pos) |
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(sam.GCLK_GENCTRL_SRC_OSC32K << sam.GCLK_GENCTRL_SRC_Pos) |
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sam.GCLK_GENCTRL_GENEN)
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waitForSync()
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// Use GCLK2 for RTC
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sam.GCLK.CLKCTRL.Set((sam.GCLK_CLKCTRL_ID_RTC << sam.GCLK_CLKCTRL_ID_Pos) |
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(sam.GCLK_CLKCTRL_GEN_GCLK2 << sam.GCLK_CLKCTRL_GEN_Pos) |
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sam.GCLK_CLKCTRL_CLKEN)
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waitForSync()
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// Set the CPU, APBA, B, and C dividers
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sam.PM.CPUSEL.Set(sam.PM_CPUSEL_CPUDIV_DIV1)
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sam.PM.APBASEL.Set(sam.PM_APBASEL_APBADIV_DIV1)
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sam.PM.APBBSEL.Set(sam.PM_APBBSEL_APBBDIV_DIV1)
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sam.PM.APBCSEL.Set(sam.PM_APBCSEL_APBCDIV_DIV1)
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// Disable automatic NVM write operations
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sam.NVMCTRL.CTRLB.SetBits(sam.NVMCTRL_CTRLB_MANW)
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}
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func initRTC() {
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// turn on digital interface clock
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sam.PM.APBAMASK.SetBits(sam.PM_APBAMASK_RTC_)
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// disable RTC
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sam.RTC_MODE0.CTRL.Set(0)
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waitForSync()
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// reset RTC
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sam.RTC_MODE0.CTRL.SetBits(sam.RTC_MODE0_CTRL_SWRST)
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waitForSync()
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// set Mode0 to 32-bit counter (mode 0) with prescaler 1 and GCLK2 is 32KHz/1
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sam.RTC_MODE0.CTRL.Set((sam.RTC_MODE0_CTRL_MODE_COUNT32 << sam.RTC_MODE0_CTRL_MODE_Pos) |
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(sam.RTC_MODE0_CTRL_PRESCALER_DIV1 << sam.RTC_MODE0_CTRL_PRESCALER_Pos))
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waitForSync()
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// re-enable RTC
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sam.RTC_MODE0.CTRL.SetBits(sam.RTC_MODE0_CTRL_ENABLE)
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waitForSync()
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arm.SetPriority(sam.IRQ_RTC, 0xc0)
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arm.EnableIRQ(sam.IRQ_RTC)
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}
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func waitForSync() {
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for sam.GCLK.STATUS.HasBits(sam.GCLK_STATUS_SYNCBUSY) {
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}
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}
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// treat all ticks params coming from runtime as being in microseconds
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const tickMicros = 1000
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var (
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timestamp timeUnit // ticks since boottime
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timerLastCounter uint64
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)
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var timerWakeup volatile.Register8
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const asyncScheduler = false
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// sleepTicks should sleep for d number of microseconds.
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func sleepTicks(d timeUnit) {
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for d != 0 {
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ticks() // update timestamp
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ticks := uint32(d)
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timerSleep(ticks)
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d -= timeUnit(ticks)
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}
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}
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// ticks returns number of microseconds since start.
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func ticks() timeUnit {
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// request read of count
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sam.RTC_MODE0.READREQ.Set(sam.RTC_MODE0_READREQ_RREQ)
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waitForSync()
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rtcCounter := (uint64(sam.RTC_MODE0.COUNT.Get()) * 305) / 10 // each counter tick == 30.5us
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offset := (rtcCounter - timerLastCounter) // change since last measurement
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timerLastCounter = rtcCounter
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timestamp += timeUnit(offset) // TODO: not precise
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return timestamp
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}
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// ticks are in microseconds
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func timerSleep(ticks uint32) {
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timerWakeup.Set(0)
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if ticks < 30 {
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// have to have at least one clock count
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ticks = 30
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}
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// request read of count
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sam.RTC_MODE0.READREQ.Set(sam.RTC_MODE0_READREQ_RREQ)
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waitForSync()
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// set compare value
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cnt := sam.RTC_MODE0.COUNT.Get()
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sam.RTC_MODE0.COMP0.Set(uint32(cnt) + (ticks * 10 / 305)) // each counter tick == 30.5us
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waitForSync()
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// enable IRQ for CMP0 compare
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sam.RTC_MODE0.INTENSET.SetBits(sam.RTC_MODE0_INTENSET_CMP0)
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for timerWakeup.Get() == 0 {
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arm.Asm("wfi")
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}
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}
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//go:export RTC_IRQHandler
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func handleRTC() {
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// disable IRQ for CMP0 compare
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sam.RTC_MODE0.INTFLAG.Set(sam.RTC_MODE0_INTENSET_CMP0)
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timerWakeup.Set(1)
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}
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func initUSBClock() {
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// Turn on clock for USB
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sam.PM.APBBMASK.SetBits(sam.PM_APBBMASK_USB_)
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// Put Generic Clock Generator 0 as source for Generic Clock Multiplexer 6 (USB reference)
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sam.GCLK.CLKCTRL.Set((sam.GCLK_CLKCTRL_ID_USB << sam.GCLK_CLKCTRL_ID_Pos) |
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(sam.GCLK_CLKCTRL_GEN_GCLK0 << sam.GCLK_CLKCTRL_GEN_Pos) |
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sam.GCLK_CLKCTRL_CLKEN)
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waitForSync()
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}
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func initADCClock() {
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// Turn on clock for ADC
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sam.PM.APBCMASK.SetBits(sam.PM_APBCMASK_ADC_)
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// Put Generic Clock Generator 0 as source for Generic Clock Multiplexer for ADC.
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sam.GCLK.CLKCTRL.Set((sam.GCLK_CLKCTRL_ID_ADC << sam.GCLK_CLKCTRL_ID_Pos) |
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(sam.GCLK_CLKCTRL_GEN_GCLK0 << sam.GCLK_CLKCTRL_GEN_Pos) |
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sam.GCLK_CLKCTRL_CLKEN)
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waitForSync()
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}
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