253 строки
7,3 КиБ
Go
253 строки
7,3 КиБ
Go
//go:build rp2040
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package machine
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import (
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"device/arm"
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"device/rp"
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"runtime/volatile"
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"unsafe"
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)
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func CPUFrequency() uint32 {
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return 125 * MHz
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}
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// Returns the period of a clock cycle for the raspberry pi pico in nanoseconds.
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// Used in PWM API.
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func cpuPeriod() uint32 {
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return 1e9 / CPUFrequency()
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}
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// clockIndex identifies a hardware clock
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type clockIndex uint8
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const (
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clkGPOUT0 clockIndex = iota // GPIO Muxing 0
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clkGPOUT1 // GPIO Muxing 1
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clkGPOUT2 // GPIO Muxing 2
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clkGPOUT3 // GPIO Muxing 3
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clkRef // Watchdog and timers reference clock
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clkSys // Processors, bus fabric, memory, memory mapped registers
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clkPeri // Peripheral clock for UART and SPI
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clkUSB // USB clock
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clkADC // ADC clock
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clkRTC // Real time clock
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numClocks
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)
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type clockType struct {
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ctrl volatile.Register32
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div volatile.Register32
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selected volatile.Register32
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}
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type fc struct {
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refKHz volatile.Register32
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minKHz volatile.Register32
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maxKHz volatile.Register32
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delay volatile.Register32
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interval volatile.Register32
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src volatile.Register32
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status volatile.Register32
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result volatile.Register32
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}
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type clocksType struct {
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clk [numClocks]clockType
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resus struct {
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ctrl volatile.Register32
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status volatile.Register32
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}
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fc0 fc
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wakeEN0 volatile.Register32
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wakeEN1 volatile.Register32
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sleepEN0 volatile.Register32
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sleepEN1 volatile.Register32
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enabled0 volatile.Register32
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enabled1 volatile.Register32
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intR volatile.Register32
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intE volatile.Register32
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intF volatile.Register32
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intS volatile.Register32
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}
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var clocks = (*clocksType)(unsafe.Pointer(rp.CLOCKS))
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var configuredFreq [numClocks]uint32
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type clock struct {
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*clockType
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cix clockIndex
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}
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// clock returns the clock identified by cix.
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func (clks *clocksType) clock(cix clockIndex) clock {
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return clock{
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&clks.clk[cix],
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cix,
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}
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}
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// hasGlitchlessMux returns true if clock contains a glitchless multiplexer.
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//
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// Clock muxing consists of two components:
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//
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// A glitchless mux, which can be switched freely, but whose inputs must be
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// free-running.
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//
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// An auxiliary (glitchy) mux, whose output glitches when switched, but has
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// no constraints on its inputs.
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//
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// Not all clocks have both types of mux.
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func (clk *clock) hasGlitchlessMux() bool {
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return clk.cix == clkSys || clk.cix == clkRef
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}
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// configure configures the clock by selecting the main clock source src
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// and the auxiliary clock source auxsrc
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// and finally setting the clock frequency to freq
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// given the input clock source frequency srcFreq.
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func (clk *clock) configure(src, auxsrc, srcFreq, freq uint32) {
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if freq > srcFreq {
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panic("clock frequency cannot be greater than source frequency")
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}
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// Div register is 24.8 int.frac divider so multiply by 2^8 (left shift by 8)
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div := uint32((uint64(srcFreq) << 8) / uint64(freq))
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// If increasing divisor, set divisor before source. Otherwise set source
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// before divisor. This avoids a momentary overspeed when e.g. switching
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// to a faster source and increasing divisor to compensate.
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if div > clk.div.Get() {
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clk.div.Set(div)
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}
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// If switching a glitchless slice (ref or sys) to an aux source, switch
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// away from aux *first* to avoid passing glitches when changing aux mux.
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// Assume (!!!) glitchless source 0 is no faster than the aux source.
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if clk.hasGlitchlessMux() && src == rp.CLOCKS_CLK_SYS_CTRL_SRC_CLKSRC_CLK_SYS_AUX {
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clk.ctrl.ClearBits(rp.CLOCKS_CLK_REF_CTRL_SRC_Msk)
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for !clk.selected.HasBits(1) {
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}
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} else
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// If no glitchless mux, cleanly stop the clock to avoid glitches
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// propagating when changing aux mux. Note it would be a really bad idea
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// to do this on one of the glitchless clocks (clkSys, clkRef).
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{
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// Disable clock. On clkRef and clkSys this does nothing,
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// all other clocks have the ENABLE bit in the same position.
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clk.ctrl.ClearBits(rp.CLOCKS_CLK_GPOUT0_CTRL_ENABLE_Msk)
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if configuredFreq[clk.cix] > 0 {
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// Delay for 3 cycles of the target clock, for ENABLE propagation.
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// Note XOSC_COUNT is not helpful here because XOSC is not
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// necessarily running, nor is timer... so, 3 cycles per loop:
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delayCyc := configuredFreq[clkSys]/configuredFreq[clk.cix] + 1
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for delayCyc != 0 {
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// This could be done more efficiently but TinyGo inline
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// assembly is not yet capable enough to express that. In the
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// meantime, this forces at least 3 cycles per loop.
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delayCyc--
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arm.Asm("nop\nnop\nnop")
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}
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}
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}
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// Set aux mux first, and then glitchless mux if this clock has one.
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clk.ctrl.ReplaceBits(auxsrc<<rp.CLOCKS_CLK_SYS_CTRL_AUXSRC_Pos,
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rp.CLOCKS_CLK_SYS_CTRL_AUXSRC_Msk, 0)
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if clk.hasGlitchlessMux() {
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clk.ctrl.ReplaceBits(src<<rp.CLOCKS_CLK_REF_CTRL_SRC_Pos,
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rp.CLOCKS_CLK_REF_CTRL_SRC_Msk, 0)
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for !clk.selected.HasBits(1 << src) {
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}
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}
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// Enable clock. On clkRef and clkSys this does nothing,
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// all other clocks have the ENABLE bit in the same position.
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clk.ctrl.SetBits(rp.CLOCKS_CLK_GPOUT0_CTRL_ENABLE)
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// Now that the source is configured, we can trust that the user-supplied
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// divisor is a safe value.
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clk.div.Set(div)
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// Store the configured frequency
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configuredFreq[clk.cix] = freq
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}
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// init initializes the clock hardware.
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//
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// Must be called before any other clock function.
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func (clks *clocksType) init() {
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// Start the watchdog tick
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watchdog.startTick(xoscFreq)
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// Disable resus that may be enabled from previous software
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clks.resus.ctrl.Set(0)
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// Enable the xosc
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xosc.init()
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// Before we touch PLLs, switch sys and ref cleanly away from their aux sources.
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clks.clk[clkSys].ctrl.ClearBits(rp.CLOCKS_CLK_SYS_CTRL_SRC_Msk)
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for !clks.clk[clkSys].selected.HasBits(0x1) {
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}
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clks.clk[clkRef].ctrl.ClearBits(rp.CLOCKS_CLK_REF_CTRL_SRC_Msk)
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for !clks.clk[clkRef].selected.HasBits(0x1) {
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}
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// Configure PLLs
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// REF FBDIV VCO POSTDIV
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// pllSys: 12 / 1 = 12MHz * 125 = 1500MHZ / 6 / 2 = 125MHz
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// pllUSB: 12 / 1 = 12MHz * 40 = 480 MHz / 5 / 2 = 48MHz
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pllSys.init(1, 1500*MHz, 6, 2)
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pllUSB.init(1, 480*MHz, 5, 2)
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// Configure clocks
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// clkRef = xosc (12MHz) / 1 = 12MHz
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clkref := clks.clock(clkRef)
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clkref.configure(rp.CLOCKS_CLK_REF_CTRL_SRC_XOSC_CLKSRC,
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0, // No aux mux
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12*MHz,
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12*MHz)
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// clkSys = pllSys (125MHz) / 1 = 125MHz
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clksys := clks.clock(clkSys)
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clksys.configure(rp.CLOCKS_CLK_SYS_CTRL_SRC_CLKSRC_CLK_SYS_AUX,
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rp.CLOCKS_CLK_SYS_CTRL_AUXSRC_CLKSRC_PLL_SYS,
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125*MHz,
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125*MHz)
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// clkUSB = pllUSB (48MHz) / 1 = 48MHz
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clkusb := clks.clock(clkUSB)
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clkusb.configure(0, // No GLMUX
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rp.CLOCKS_CLK_USB_CTRL_AUXSRC_CLKSRC_PLL_USB,
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48*MHz,
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48*MHz)
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// clkADC = pllUSB (48MHZ) / 1 = 48MHz
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clkadc := clks.clock(clkADC)
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clkadc.configure(0, // No GLMUX
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rp.CLOCKS_CLK_ADC_CTRL_AUXSRC_CLKSRC_PLL_USB,
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48*MHz,
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48*MHz)
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// clkRTC = pllUSB (48MHz) / 1024 = 46875Hz
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clkrtc := clks.clock(clkRTC)
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clkrtc.configure(0, // No GLMUX
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rp.CLOCKS_CLK_RTC_CTRL_AUXSRC_CLKSRC_PLL_USB,
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48*MHz,
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46875)
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// clkPeri = clkSys. Used as reference clock for Peripherals.
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// No dividers so just select and enable.
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// Normally choose clkSys or clkUSB.
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clkperi := clks.clock(clkPeri)
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clkperi.configure(0,
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rp.CLOCKS_CLK_PERI_CTRL_AUXSRC_CLK_SYS,
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125*MHz,
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125*MHz)
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}
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