77ec9b6369
Do it all at once in preparation for Go 1.18 support. To make this commit, I've simply modified the `fmt-check` Makefile target to rewrite files instead of listing the differences. So this is a fully mechanical change, it should not have introduced any errors.
359 строки
11 КиБ
Go
359 строки
11 КиБ
Go
//go:build (sam && atsamd51) || (sam && atsame5x)
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// +build sam,atsamd51 sam,atsame5x
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package runtime
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import (
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"device/arm"
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"device/sam"
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"machine"
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"runtime/interrupt"
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"runtime/volatile"
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)
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type timeUnit int64
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//export Reset_Handler
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func main() {
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arm.SCB.CPACR.Set(0) // disable FPU if it is enabled
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preinit()
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run()
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exit(0)
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}
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func init() {
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initClocks()
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initRTC()
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initSERCOMClocks()
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initUSBClock()
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initADCClock()
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// connect to USB CDC interface
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machine.Serial.Configure(machine.UARTConfig{})
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}
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func putchar(c byte) {
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machine.Serial.WriteByte(c)
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}
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func initClocks() {
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// set flash wait state
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sam.NVMCTRL.CTRLA.SetBits(0 << sam.NVMCTRL_CTRLA_RWS_Pos)
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// software reset
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sam.GCLK.CTRLA.SetBits(sam.GCLK_CTRLA_SWRST)
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for sam.GCLK.SYNCBUSY.HasBits(sam.GCLK_SYNCBUSY_SWRST) {
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}
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// Set OSCULP32K as source of Generic Clock Generator 3
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// GCLK->GENCTRL[GENERIC_CLOCK_GENERATOR_XOSC32K].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_OSCULP32K) | GCLK_GENCTRL_GENEN; //generic clock gen 3
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sam.GCLK.GENCTRL[3].Set((sam.GCLK_GENCTRL_SRC_OSCULP32K << sam.GCLK_GENCTRL_SRC_Pos) |
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sam.GCLK_GENCTRL_GENEN)
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for sam.GCLK.SYNCBUSY.HasBits(sam.GCLK_SYNCBUSY_GENCTRL_GCLK3) {
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}
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// Set OSCULP32K as source of Generic Clock Generator 0
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sam.GCLK.GENCTRL[0].Set((sam.GCLK_GENCTRL_SRC_OSCULP32K << sam.GCLK_GENCTRL_SRC_Pos) |
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sam.GCLK_GENCTRL_GENEN)
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for sam.GCLK.SYNCBUSY.HasBits(sam.GCLK_SYNCBUSY_GENCTRL_GCLK0) {
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}
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// Enable DFLL48M clock
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sam.OSCCTRL.DFLLCTRLA.Set(0)
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sam.OSCCTRL.DFLLMUL.Set((0x1 << sam.OSCCTRL_DFLLMUL_CSTEP_Pos) |
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(0x1 << sam.OSCCTRL_DFLLMUL_FSTEP_Pos) |
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(0x0 << sam.OSCCTRL_DFLLMUL_MUL_Pos))
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for sam.OSCCTRL.DFLLSYNC.HasBits(sam.OSCCTRL_DFLLSYNC_DFLLMUL) {
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}
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sam.OSCCTRL.DFLLCTRLB.Set(0)
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for sam.OSCCTRL.DFLLSYNC.HasBits(sam.OSCCTRL_DFLLSYNC_DFLLCTRLB) {
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}
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sam.OSCCTRL.DFLLCTRLA.SetBits(sam.OSCCTRL_DFLLCTRLA_ENABLE)
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for sam.OSCCTRL.DFLLSYNC.HasBits(sam.OSCCTRL_DFLLSYNC_ENABLE) {
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}
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sam.OSCCTRL.DFLLVAL.Set(sam.OSCCTRL.DFLLVAL.Get())
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for sam.OSCCTRL.DFLLSYNC.HasBits(sam.OSCCTRL_DFLLSYNC_DFLLVAL) {
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}
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sam.OSCCTRL.DFLLCTRLB.Set(sam.OSCCTRL_DFLLCTRLB_WAITLOCK |
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sam.OSCCTRL_DFLLCTRLB_CCDIS |
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sam.OSCCTRL_DFLLCTRLB_USBCRM)
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for !sam.OSCCTRL.STATUS.HasBits(sam.OSCCTRL_STATUS_DFLLRDY) {
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}
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// set GCLK7 to run at 2MHz, using DFLL48M as clock source
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// GCLK7 = 48MHz / 24 = 2MHz
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sam.GCLK.GENCTRL[7].Set((sam.GCLK_GENCTRL_SRC_DFLL << sam.GCLK_GENCTRL_SRC_Pos) |
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(24 << sam.GCLK_GENCTRL_DIV_Pos) |
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sam.GCLK_GENCTRL_GENEN)
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for sam.GCLK.SYNCBUSY.HasBits(sam.GCLK_SYNCBUSY_GENCTRL_GCLK7) {
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}
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// Set up the PLLs
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// Set PLL0 to run at 120MHz, using GCLK7 as clock source
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sam.GCLK.PCHCTRL[1].Set(sam.GCLK_PCHCTRL_CHEN |
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(sam.GCLK_PCHCTRL_GEN_GCLK7 << sam.GCLK_PCHCTRL_GEN_Pos))
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// multiplier = 59 + 1 + (0/32) = 60
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// PLL0 = 2MHz * 60 = 120MHz
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sam.OSCCTRL.DPLL[0].DPLLRATIO.Set((0x0 << sam.OSCCTRL_DPLL_DPLLRATIO_LDRFRAC_Pos) |
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(59 << sam.OSCCTRL_DPLL_DPLLRATIO_LDR_Pos))
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for sam.OSCCTRL.DPLL[0].DPLLSYNCBUSY.HasBits(sam.OSCCTRL_DPLL_DPLLSYNCBUSY_DPLLRATIO) {
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}
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// MUST USE LBYPASS DUE TO BUG IN REV A OF SAMD51, via Adafruit lib.
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sam.OSCCTRL.DPLL[0].DPLLCTRLB.Set((sam.OSCCTRL_DPLL_DPLLCTRLB_REFCLK_GCLK << sam.OSCCTRL_DPLL_DPLLCTRLB_REFCLK_Pos) |
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sam.OSCCTRL_DPLL_DPLLCTRLB_LBYPASS)
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sam.OSCCTRL.DPLL[0].DPLLCTRLA.Set(sam.OSCCTRL_DPLL_DPLLCTRLA_ENABLE)
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for !sam.OSCCTRL.DPLL[0].DPLLSTATUS.HasBits(sam.OSCCTRL_DPLL_DPLLSTATUS_CLKRDY) ||
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!sam.OSCCTRL.DPLL[0].DPLLSTATUS.HasBits(sam.OSCCTRL_DPLL_DPLLSTATUS_LOCK) {
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}
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// Set PLL1 to run at 100MHz, using GCLK7 as clock source
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sam.GCLK.PCHCTRL[2].Set(sam.GCLK_PCHCTRL_CHEN |
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(sam.GCLK_PCHCTRL_GEN_GCLK7 << sam.GCLK_PCHCTRL_GEN_Pos))
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// multiplier = 49 + 1 + (0/32) = 50
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// PLL1 = 2MHz * 50 = 100MHz
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sam.OSCCTRL.DPLL[1].DPLLRATIO.Set((0x0 << sam.OSCCTRL_DPLL_DPLLRATIO_LDRFRAC_Pos) |
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(49 << sam.OSCCTRL_DPLL_DPLLRATIO_LDR_Pos))
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for sam.OSCCTRL.DPLL[1].DPLLSYNCBUSY.HasBits(sam.OSCCTRL_DPLL_DPLLSYNCBUSY_DPLLRATIO) {
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}
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// // MUST USE LBYPASS DUE TO BUG IN REV A OF SAMD51
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sam.OSCCTRL.DPLL[1].DPLLCTRLB.Set((sam.OSCCTRL_DPLL_DPLLCTRLB_REFCLK_GCLK << sam.OSCCTRL_DPLL_DPLLCTRLB_REFCLK_Pos) |
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sam.OSCCTRL_DPLL_DPLLCTRLB_LBYPASS)
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sam.OSCCTRL.DPLL[1].DPLLCTRLA.Set(sam.OSCCTRL_DPLL_DPLLCTRLA_ENABLE)
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// for !sam.OSCCTRL.DPLLSTATUS1.HasBits(sam.OSCCTRL_DPLLSTATUS_CLKRDY) ||
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// !sam.OSCCTRL.DPLLSTATUS1.HasBits(sam.OSCCTRL_DPLLSTATUS_LOCK) {
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// }
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// Set up the peripheral clocks
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// Set 48MHZ CLOCK FOR USB
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sam.GCLK.GENCTRL[1].Set((sam.GCLK_GENCTRL_SRC_DFLL << sam.GCLK_GENCTRL_SRC_Pos) |
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sam.GCLK_GENCTRL_IDC |
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sam.GCLK_GENCTRL_GENEN)
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for sam.GCLK.SYNCBUSY.HasBits(sam.GCLK_SYNCBUSY_GENCTRL_GCLK1) {
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}
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// // Set 100MHZ CLOCK FOR OTHER PERIPHERALS
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// sam.GCLK.GENCTRL2.Set((sam.GCLK_GENCTRL_SRC_DPLL1 << sam.GCLK_GENCTRL_SRC_Pos) |
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// sam.GCLK_GENCTRL_IDC |
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// sam.GCLK_GENCTRL_GENEN)
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// for sam.GCLK.SYNCBUSY.HasBits(sam.GCLK_SYNCBUSY_GENCTRL2) {
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// }
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// // Set 12MHZ CLOCK FOR DAC
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sam.GCLK.GENCTRL[4].Set((sam.GCLK_GENCTRL_SRC_DFLL << sam.GCLK_GENCTRL_SRC_Pos) |
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sam.GCLK_GENCTRL_IDC |
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(4 << sam.GCLK_GENCTRL_DIVSEL_Pos) |
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sam.GCLK_GENCTRL_GENEN)
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for sam.GCLK.SYNCBUSY.HasBits(sam.GCLK_SYNCBUSY_GENCTRL_GCLK4) {
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}
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// // Set up main clock
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sam.GCLK.GENCTRL[0].Set((sam.GCLK_GENCTRL_SRC_DPLL0 << sam.GCLK_GENCTRL_SRC_Pos) |
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sam.GCLK_GENCTRL_IDC |
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sam.GCLK_GENCTRL_GENEN)
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for sam.GCLK.SYNCBUSY.HasBits(sam.GCLK_SYNCBUSY_GENCTRL_GCLK0) {
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}
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sam.MCLK.CPUDIV.Set(sam.MCLK_CPUDIV_DIV_DIV1)
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// Use the LDO regulator by default
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sam.SUPC.VREG.ClearBits(sam.SUPC_VREG_SEL)
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// Start up the "Debug Watchpoint and Trace" unit, so that we can use
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// it's 32bit cycle counter for timing.
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//CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
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//DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
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}
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func initRTC() {
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// turn on digital interface clock
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sam.MCLK.APBAMASK.SetBits(sam.MCLK_APBAMASK_RTC_)
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// disable RTC
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sam.RTC_MODE0.CTRLA.ClearBits(sam.RTC_MODE0_CTRLA_ENABLE)
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//sam.RTC_MODE0.CTRLA.Set(0)
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for sam.RTC_MODE0.SYNCBUSY.HasBits(sam.RTC_MODE0_SYNCBUSY_ENABLE) {
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}
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// reset RTC
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sam.RTC_MODE0.CTRLA.SetBits(sam.RTC_MODE0_CTRLA_SWRST)
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for sam.RTC_MODE0.SYNCBUSY.HasBits(sam.RTC_MODE0_SYNCBUSY_SWRST) {
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}
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// set to use ulp 32k oscillator
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sam.OSC32KCTRL.OSCULP32K.SetBits(sam.OSC32KCTRL_OSCULP32K_EN32K)
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sam.OSC32KCTRL.RTCCTRL.Set(sam.OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K)
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// set Mode0 to 32-bit counter (mode 0) with prescaler 1 and GCLK2 is 32KHz/1
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sam.RTC_MODE0.CTRLA.Set((sam.RTC_MODE0_CTRLA_MODE_COUNT32 << sam.RTC_MODE0_CTRLA_MODE_Pos) |
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(sam.RTC_MODE0_CTRLA_PRESCALER_DIV1 << sam.RTC_MODE0_CTRLA_PRESCALER_Pos) |
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(sam.RTC_MODE0_CTRLA_COUNTSYNC))
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// re-enable RTC
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sam.RTC_MODE0.CTRLA.SetBits(sam.RTC_MODE0_CTRLA_ENABLE)
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for sam.RTC_MODE0.SYNCBUSY.HasBits(sam.RTC_MODE0_SYNCBUSY_ENABLE) {
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}
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irq := interrupt.New(sam.IRQ_RTC, func(interrupt.Interrupt) {
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flags := sam.RTC_MODE0.INTFLAG.Get()
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if flags&sam.RTC_MODE0_INTENSET_CMP0 != 0 {
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// The timer (for a sleep) has expired.
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timerWakeup.Set(1)
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}
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if flags&sam.RTC_MODE0_INTENSET_OVF != 0 {
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// The 32-bit RTC timer has overflowed.
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rtcOverflows.Set(rtcOverflows.Get() + 1)
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}
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// Mark this interrupt has handled for CMP0 and OVF.
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sam.RTC_MODE0.INTFLAG.Set(sam.RTC_MODE0_INTENSET_CMP0 | sam.RTC_MODE0_INTENSET_OVF)
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})
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sam.RTC_MODE0.INTENSET.Set(sam.RTC_MODE0_INTENSET_OVF)
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irq.SetPriority(0xc0)
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irq.Enable()
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}
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func waitForSync() {
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for sam.RTC_MODE0.SYNCBUSY.HasBits(sam.RTC_MODE0_SYNCBUSY_COUNT) {
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}
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}
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var rtcOverflows volatile.Register32 // number of times the RTC wrapped around
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var timerWakeup volatile.Register8
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// ticksToNanoseconds converts RTC ticks (at 32768Hz) to nanoseconds.
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func ticksToNanoseconds(ticks timeUnit) int64 {
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// The following calculation is actually the following, but with both sides
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// reduced to reduce the risk of overflow:
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// ticks * 1e9 / 32768
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return int64(ticks) * 1953125 / 64
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}
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// nanosecondsToTicks converts nanoseconds to RTC ticks (running at 32768Hz).
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func nanosecondsToTicks(ns int64) timeUnit {
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// The following calculation is actually the following, but with both sides
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// reduced to reduce the risk of overflow:
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// ns * 32768 / 1e9
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return timeUnit(ns * 64 / 1953125)
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}
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// sleepTicks should sleep for d number of microseconds.
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func sleepTicks(d timeUnit) {
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for d != 0 {
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ticks := uint32(d)
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if !timerSleep(ticks) {
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return
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}
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d -= timeUnit(ticks)
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}
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}
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// ticks returns the elapsed time since reset.
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func ticks() timeUnit {
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// For some ways of capturing the time atomically, see this thread:
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// https://www.eevblog.com/forum/microcontrollers/correct-timing-by-timer-overflow-count/msg749617/#msg749617
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// Here, instead of re-reading the counter register if an overflow has been
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// detected, we simply try again because that results in smaller code.
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for {
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mask := interrupt.Disable()
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counter := readRTC()
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overflows := rtcOverflows.Get()
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hasOverflow := sam.RTC_MODE0.INTFLAG.Get()&sam.RTC_MODE0_INTENSET_OVF != 0
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interrupt.Restore(mask)
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if hasOverflow {
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// There was an overflow while trying to capture the timer.
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// Try again.
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continue
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}
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// This is a 32-bit timer, so the number of timer overflows forms the
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// upper 32 bits of this timer.
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return timeUnit(overflows)<<32 + timeUnit(counter)
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}
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}
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func readRTC() uint32 {
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waitForSync()
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return sam.RTC_MODE0.COUNT.Get()
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}
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// ticks are in microseconds
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// Returns true if the timer completed.
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// Returns false if another interrupt occured which requires an early return to scheduler.
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func timerSleep(ticks uint32) bool {
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timerWakeup.Set(0)
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if ticks < 8 {
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// due to delay waiting for the register value to sync, the minimum sleep value
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// for the SAMD51 is 260us.
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// For related info for SAMD21, see:
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// https://community.atmel.com/comment/2507091#comment-2507091
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ticks = 8
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}
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// request read of count
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waitForSync()
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// set compare value
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cnt := sam.RTC_MODE0.COUNT.Get()
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sam.RTC_MODE0.COMP[0].Set(uint32(cnt) + ticks)
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// enable IRQ for CMP0 compare
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sam.RTC_MODE0.INTENSET.Set(sam.RTC_MODE0_INTENSET_CMP0)
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wait:
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waitForEvents()
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if timerWakeup.Get() != 0 {
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return true
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}
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if hasScheduler {
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// The interurpt may have awoken a goroutine, so bail out early.
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// Disable IRQ for CMP0 compare.
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sam.RTC_MODE0.INTENCLR.Set(sam.RTC_MODE0_INTENSET_CMP0)
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return false
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} else {
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// This is running without a scheduler.
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// The application expects this to sleep the whole time.
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goto wait
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}
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}
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func initUSBClock() {
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// Turn on clock(s) for USB
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//MCLK->APBBMASK.reg |= MCLK_APBBMASK_USB;
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//MCLK->AHBMASK.reg |= MCLK_AHBMASK_USB;
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sam.MCLK.APBBMASK.SetBits(sam.MCLK_APBBMASK_USB_)
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sam.MCLK.AHBMASK.SetBits(sam.MCLK_AHBMASK_USB_)
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// Put Generic Clock Generator 1 as source for USB
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//GCLK->PCHCTRL[USB_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK1_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
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sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_USB].Set((sam.GCLK_PCHCTRL_GEN_GCLK1 << sam.GCLK_PCHCTRL_GEN_Pos) |
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sam.GCLK_PCHCTRL_CHEN)
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}
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func initADCClock() {
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// Turn on clocks for ADC0/ADC1.
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sam.MCLK.APBDMASK.SetBits(sam.MCLK_APBDMASK_ADC0_)
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sam.MCLK.APBDMASK.SetBits(sam.MCLK_APBDMASK_ADC1_)
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// Put Generic Clock Generator 1 as source for ADC0 and ADC1.
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sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_ADC0].Set((sam.GCLK_PCHCTRL_GEN_GCLK1 << sam.GCLK_PCHCTRL_GEN_Pos) |
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sam.GCLK_PCHCTRL_CHEN)
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sam.GCLK.PCHCTRL[sam.PCHCTRL_GCLK_ADC1].Set((sam.GCLK_PCHCTRL_GEN_GCLK1 << sam.GCLK_PCHCTRL_GEN_Pos) |
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sam.GCLK_PCHCTRL_CHEN)
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}
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func waitForEvents() {
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arm.Asm("wfe")
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}
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