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tinygo/src/device/avr/atmega644rfr2.go
Ayke van Laethem 90fb0ee4eb
Add AVR support 
This requires support in LLVM, as AVR support is still experimental. For
example, in bindings/go/build.sh, add
-DLLVM_EXPERIMENTAL_TARGETS_TO_BUILD=AVR to cmake_flags.
2018-06-07 18:35:54 +02:00

1760 строки
70 КиБ
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Исходный Авторство История

// Automatically generated file. DO NOT EDIT.
// Generated by gen-device.py from ATmega644RFR2.atdf, see http://packs.download.atmel.com/
// +build avr,atmega644rfr2
// Device information for the ATmega644RFR2.
//
package avr
// Magic type name for the compiler.
type __reg uint8
// Export this magic type name.
type RegValue = __reg
// Some information about this device.
const (
DEVICE = "ATmega644RFR2"
ARCH = "AVR8"
FAMILY = "megaAVR"
)
// Interrupts
const (
IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet.
IRQ_INT0 = 1 // External Interrupt Request 0
IRQ_INT1 = 2 // External Interrupt Request 1
IRQ_INT2 = 3 // External Interrupt Request 2
IRQ_INT3 = 4 // External Interrupt Request 3
IRQ_INT4 = 5 // External Interrupt Request 4
IRQ_INT5 = 6 // External Interrupt Request 5
IRQ_INT6 = 7 // External Interrupt Request 6
IRQ_INT7 = 8 // External Interrupt Request 7
IRQ_PCINT0 = 9 // Pin Change Interrupt Request 0
IRQ_PCINT1 = 10 // Pin Change Interrupt Request 1
IRQ_PCINT2 = 11 // Pin Change Interrupt Request 2
IRQ_WDT = 12 // Watchdog Time-out Interrupt
IRQ_TIMER2_COMPA = 13 // Timer/Counter2 Compare Match A
IRQ_TIMER2_COMPB = 14 // Timer/Counter2 Compare Match B
IRQ_TIMER2_OVF = 15 // Timer/Counter2 Overflow
IRQ_TIMER1_CAPT = 16 // Timer/Counter1 Capture Event
IRQ_TIMER1_COMPA = 17 // Timer/Counter1 Compare Match A
IRQ_TIMER1_COMPB = 18 // Timer/Counter1 Compare Match B
IRQ_TIMER1_COMPC = 19 // Timer/Counter1 Compare Match C
IRQ_TIMER1_OVF = 20 // Timer/Counter1 Overflow
IRQ_TIMER0_COMPA = 21 // Timer/Counter0 Compare Match A
IRQ_TIMER0_COMPB = 22 // Timer/Counter0 Compare Match B
IRQ_TIMER0_OVF = 23 // Timer/Counter0 Overflow
IRQ_SPI_STC = 24 // SPI Serial Transfer Complete
IRQ_USART0_RX = 25 // USART0, Rx Complete
IRQ_USART0_UDRE = 26 // USART0 Data register Empty
IRQ_USART0_TX = 27 // USART0, Tx Complete
IRQ_ANALOG_COMP = 28 // Analog Comparator
IRQ_ADC = 29 // ADC Conversion Complete
IRQ_EE_READY = 30 // EEPROM Ready
IRQ_TIMER3_CAPT = 31 // Timer/Counter3 Capture Event
IRQ_TIMER3_COMPA = 32 // Timer/Counter3 Compare Match A
IRQ_TIMER3_COMPB = 33 // Timer/Counter3 Compare Match B
IRQ_TIMER3_COMPC = 34 // Timer/Counter3 Compare Match C
IRQ_TIMER3_OVF = 35 // Timer/Counter3 Overflow
IRQ_USART1_RX = 36 // USART1, Rx Complete
IRQ_USART1_UDRE = 37 // USART1 Data register Empty
IRQ_USART1_TX = 38 // USART1, Tx Complete
IRQ_TWI = 39 // 2-wire Serial Interface
IRQ_SPM_READY = 40 // Store Program Memory Read
IRQ_TIMER4_CAPT = 41 // Timer/Counter4 Capture Event
IRQ_TIMER4_COMPA = 42 // Timer/Counter4 Compare Match A
IRQ_TIMER4_COMPB = 43 // Timer/Counter4 Compare Match B
IRQ_TIMER4_COMPC = 44 // Timer/Counter4 Compare Match C
IRQ_TIMER4_OVF = 45 // Timer/Counter4 Overflow
IRQ_TIMER5_CAPT = 46 // Timer/Counter5 Capture Event
IRQ_TIMER5_COMPA = 47 // Timer/Counter5 Compare Match A
IRQ_TIMER5_COMPB = 48 // Timer/Counter5 Compare Match B
IRQ_TIMER5_COMPC = 49 // Timer/Counter5 Compare Match C
IRQ_TIMER5_OVF = 50 // Timer/Counter5 Overflow
IRQ_TRX24_PLL_LOCK = 57 // TRX24 - PLL lock interrupt
IRQ_TRX24_PLL_UNLOCK = 58 // TRX24 - PLL unlock interrupt
IRQ_TRX24_RX_START = 59 // TRX24 - Receive start interrupt
IRQ_TRX24_RX_END = 60 // TRX24 - RX_END interrupt
IRQ_TRX24_CCA_ED_DONE = 61 // TRX24 - CCA/ED done interrupt
IRQ_TRX24_XAH_AMI = 62 // TRX24 - XAH - AMI
IRQ_TRX24_TX_END = 63 // TRX24 - TX_END interrupt
IRQ_TRX24_AWAKE = 64 // TRX24 AWAKE - tranceiver is reaching state TRX_OFF
IRQ_SCNT_CMP1 = 65 // Symbol counter - compare match 1 interrupt
IRQ_SCNT_CMP2 = 66 // Symbol counter - compare match 2 interrupt
IRQ_SCNT_CMP3 = 67 // Symbol counter - compare match 3 interrupt
IRQ_SCNT_OVFL = 68 // Symbol counter - overflow interrupt
IRQ_SCNT_BACKOFF = 69 // Symbol counter - backoff interrupt
IRQ_AES_READY = 70 // AES engine ready interrupt
IRQ_BAT_LOW = 71 // Battery monitor indicates supply voltage below threshold
IRQ_TRX24_TX_START = 72 // TRX24 TX start interrupt
IRQ_TRX24_AMI0 = 73 // Address match interrupt of address filter 0
IRQ_TRX24_AMI1 = 74 // Address match interrupt of address filter 1
IRQ_TRX24_AMI2 = 75 // Address match interrupt of address filter 2
IRQ_TRX24_AMI3 = 76 // Address match interrupt of address filter 3
IRQ_max = 76 // Highest interrupt number on this device.
)
// Peripherals
var (
// Fuses
FUSE = struct {
EXTENDED __reg
HIGH __reg
LOW __reg
}{
EXTENDED: 0x2,
HIGH: 0x1,
LOW: 0x0,
}
// Lockbits
LOCKBIT = struct {
LOCKBIT __reg
}{
LOCKBIT: 0x0,
}
// Analog Comparator
AC = struct {
ACSR __reg
DIDR1 __reg
}{
ACSR: 0x50, // Analog Comparator Control And Status Register
DIDR1: 0x7f, // Digital Input Disable Register 1
}
// USART
USART = struct {
UDR0 __reg
UBRR0L __reg
UBRR0H __reg
UDR1 __reg
UBRR1L __reg
UBRR1H __reg
}{
UDR0: 0xc6, // USART0 I/O Data Register
UBRR0L: 0xc4, // USART0 Baud Rate Register Bytes
UBRR0H: 0xc4, // USART0 Baud Rate Register Bytes
UDR1: 0xce, // USART1 I/O Data Register
UBRR1L: 0xcc, // USART1 Baud Rate Register Bytes
UBRR1H: 0xcc, // USART1 Baud Rate Register Bytes
}
// Two Wire Serial Interface
TWI = struct {
TWAMR __reg
TWBR __reg
TWCR __reg
TWSR __reg
TWDR __reg
TWAR __reg
}{
TWAMR: 0xbd, // TWI (Slave) Address Mask Register
TWBR: 0xb8, // TWI Bit Rate Register
TWCR: 0xbc, // TWI Control Register
TWSR: 0xb9, // TWI Status Register
TWDR: 0xbb, // TWI Data Register
TWAR: 0xba, // TWI (Slave) Address Register
}
// Serial Peripheral Interface
SPI = struct {
SPCR __reg
SPSR __reg
SPDR __reg
}{
SPCR: 0x4c, // SPI Control Register
SPSR: 0x4d, // SPI Status Register
SPDR: 0x4e, // SPI Data Register
}
// I/O Port
PORT = struct {
PORTA __reg
DDRA __reg
PINA __reg
PORTB __reg
DDRB __reg
PINB __reg
PORTC __reg
DDRC __reg
PINC __reg
PORTD __reg
DDRD __reg
PIND __reg
PORTE __reg
DDRE __reg
PINE __reg
PORTF __reg
DDRF __reg
PINF __reg
PORTG __reg
DDRG __reg
PING __reg
}{
PORTA: 0x22, // Port A Data Register
DDRA: 0x21, // Port A Data Direction Register
PINA: 0x20, // Port A Input Pins Address
PORTB: 0x25, // Port B Data Register
DDRB: 0x24, // Port B Data Direction Register
PINB: 0x23, // Port B Input Pins Address
PORTC: 0x28, // Port C Data Register
DDRC: 0x27, // Port C Data Direction Register
PINC: 0x26, // Port C Input Pins Address
PORTD: 0x2b, // Port D Data Register
DDRD: 0x2a, // Port D Data Direction Register
PIND: 0x29, // Port D Input Pins Address
PORTE: 0x2e, // Port E Data Register
DDRE: 0x2d, // Port E Data Direction Register
PINE: 0x2c, // Port E Input Pins Address
PORTF: 0x31, // Port F Data Register
DDRF: 0x30, // Port F Data Direction Register
PINF: 0x2f, // Port F Input Pins Address
PORTG: 0x34, // Port G Data Register
DDRG: 0x33, // Port G Data Direction Register
PING: 0x32, // Port G Input Pins Address
}
// Timer/Counter, 8-bit
TC8 = struct {
OCR0B __reg
OCR0A __reg
TCNT0 __reg
TCCR0B __reg
TCCR0A __reg
TIMSK0 __reg
TIFR0 __reg
}{
OCR0B: 0x48, // Timer/Counter0 Output Compare Register B
OCR0A: 0x47, // Timer/Counter0 Output Compare Register
TCNT0: 0x46, // Timer/Counter0 Register
TCCR0B: 0x45, // Timer/Counter0 Control Register B
TCCR0A: 0x44, // Timer/Counter0 Control Register A
TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register
TIFR0: 0x35, // Timer/Counter0 Interrupt Flag Register
}
// Timer/Counter, 8-bit Async
TC8_ASYNC = struct {
TIMSK2 __reg
TIFR2 __reg
TCCR2A __reg
TCCR2B __reg
TCNT2 __reg
OCR2B __reg
OCR2A __reg
ASSR __reg
}{
TIMSK2: 0x70, // Timer/Counter Interrupt Mask register
TIFR2: 0x37, // Timer/Counter Interrupt Flag Register
TCCR2A: 0xb0, // Timer/Counter2 Control Register A
TCCR2B: 0xb1, // Timer/Counter2 Control Register B
TCNT2: 0xb2, // Timer/Counter2
OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B
OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A
ASSR: 0xb6, // Asynchronous Status Register
}
// Watchdog Timer
WDT = struct {
WDTCSR __reg
}{
WDTCSR: 0x60, // Watchdog Timer Control Register
}
// Timer/Counter, 16-bit
TC16 = struct {
TCCR5A __reg
TCCR5B __reg
TCCR5C __reg
TCNT5L __reg
TCNT5H __reg
OCR5AL __reg
OCR5AH __reg
OCR5BL __reg
OCR5BH __reg
OCR5CL __reg
OCR5CH __reg
ICR5L __reg
ICR5H __reg
TIMSK5 __reg
TIFR5 __reg
TCCR4A __reg
TCCR4B __reg
TCCR4C __reg
TCNT4L __reg
TCNT4H __reg
OCR4AL __reg
OCR4AH __reg
OCR4BL __reg
OCR4BH __reg
OCR4CL __reg
OCR4CH __reg
ICR4L __reg
ICR4H __reg
TIMSK4 __reg
TIFR4 __reg
TCCR3A __reg
TCCR3B __reg
TCCR3C __reg
TCNT3L __reg
TCNT3H __reg
OCR3AL __reg
OCR3AH __reg
OCR3BL __reg
OCR3BH __reg
OCR3CL __reg
OCR3CH __reg
ICR3L __reg
ICR3H __reg
TIMSK3 __reg
TIFR3 __reg
TCCR1A __reg
TCCR1B __reg
TCCR1C __reg
TCNT1L __reg
TCNT1H __reg
OCR1AL __reg
OCR1AH __reg
OCR1BL __reg
OCR1BH __reg
OCR1CL __reg
OCR1CH __reg
ICR1L __reg
ICR1H __reg
TIMSK1 __reg
TIFR1 __reg
}{
TCCR5A: 0x120, // Timer/Counter5 Control Register A
TCCR5B: 0x121, // Timer/Counter5 Control Register B
TCCR5C: 0x122, // Timer/Counter5 Control Register C
TCNT5L: 0x124, // Timer/Counter5 Bytes
TCNT5H: 0x124, // Timer/Counter5 Bytes
OCR5AL: 0x128, // Timer/Counter5 Output Compare Register A Bytes
OCR5AH: 0x128, // Timer/Counter5 Output Compare Register A Bytes
OCR5BL: 0x12a, // Timer/Counter5 Output Compare Register B Bytes
OCR5BH: 0x12a, // Timer/Counter5 Output Compare Register B Bytes
OCR5CL: 0x12c, // Timer/Counter5 Output Compare Register C Bytes
OCR5CH: 0x12c, // Timer/Counter5 Output Compare Register C Bytes
ICR5L: 0x126, // Timer/Counter5 Input Capture Register Bytes
ICR5H: 0x126, // Timer/Counter5 Input Capture Register Bytes
TIMSK5: 0x73, // Timer/Counter5 Interrupt Mask Register
TIFR5: 0x3a, // Timer/Counter5 Interrupt Flag Register
TCCR4A: 0xa0, // Timer/Counter4 Control Register A
TCCR4B: 0xa1, // Timer/Counter4 Control Register B
TCCR4C: 0xa2, // Timer/Counter4 Control Register C
TCNT4L: 0xa4, // Timer/Counter4 Bytes
TCNT4H: 0xa4, // Timer/Counter4 Bytes
OCR4AL: 0xa8, // Timer/Counter4 Output Compare Register A Bytes
OCR4AH: 0xa8, // Timer/Counter4 Output Compare Register A Bytes
OCR4BL: 0xaa, // Timer/Counter4 Output Compare Register B Bytes
OCR4BH: 0xaa, // Timer/Counter4 Output Compare Register B Bytes
OCR4CL: 0xac, // Timer/Counter4 Output Compare Register C Bytes
OCR4CH: 0xac, // Timer/Counter4 Output Compare Register C Bytes
ICR4L: 0xa6, // Timer/Counter4 Input Capture Register Bytes
ICR4H: 0xa6, // Timer/Counter4 Input Capture Register Bytes
TIMSK4: 0x72, // Timer/Counter4 Interrupt Mask Register
TIFR4: 0x39, // Timer/Counter4 Interrupt Flag Register
TCCR3A: 0x90, // Timer/Counter3 Control Register A
TCCR3B: 0x91, // Timer/Counter3 Control Register B
TCCR3C: 0x92, // Timer/Counter3 Control Register C
TCNT3L: 0x94, // Timer/Counter3 Bytes
TCNT3H: 0x94, // Timer/Counter3 Bytes
OCR3AL: 0x98, // Timer/Counter3 Output Compare Register A Bytes
OCR3AH: 0x98, // Timer/Counter3 Output Compare Register A Bytes
OCR3BL: 0x9a, // Timer/Counter3 Output Compare Register B Bytes
OCR3BH: 0x9a, // Timer/Counter3 Output Compare Register B Bytes
OCR3CL: 0x9c, // Timer/Counter3 Output Compare Register C Bytes
OCR3CH: 0x9c, // Timer/Counter3 Output Compare Register C Bytes
ICR3L: 0x96, // Timer/Counter3 Input Capture Register Bytes
ICR3H: 0x96, // Timer/Counter3 Input Capture Register Bytes
TIMSK3: 0x71, // Timer/Counter3 Interrupt Mask Register
TIFR3: 0x38, // Timer/Counter3 Interrupt Flag Register
TCCR1A: 0x80, // Timer/Counter1 Control Register A
TCCR1B: 0x81, // Timer/Counter1 Control Register B
TCCR1C: 0x82, // Timer/Counter1 Control Register C
TCNT1L: 0x84, // Timer/Counter1 Bytes
TCNT1H: 0x84, // Timer/Counter1 Bytes
OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes
OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes
OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes
OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes
OCR1CL: 0x8c, // Timer/Counter1 Output Compare Register C Bytes
OCR1CH: 0x8c, // Timer/Counter1 Output Compare Register C Bytes
ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes
ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes
TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register
TIFR1: 0x36, // Timer/Counter1 Interrupt Flag Register
}
// Low-Power 2.4 GHz Transceiver
TRX24 = struct {
PARCR __reg
MAFSA0L __reg
MAFSA0H __reg
MAFPA0L __reg
MAFPA0H __reg
MAFSA1L __reg
MAFSA1H __reg
MAFPA1L __reg
MAFPA1H __reg
MAFSA2L __reg
MAFSA2H __reg
MAFPA2L __reg
MAFPA2H __reg
MAFSA3L __reg
MAFSA3H __reg
MAFPA3L __reg
MAFPA3H __reg
MAFCR0 __reg
MAFCR1 __reg
AES_CTRL __reg
AES_STATUS __reg
AES_STATE __reg
AES_KEY __reg
TRX_STATUS __reg
TRX_STATE __reg
TRX_CTRL_0 __reg
TRX_CTRL_1 __reg
PHY_TX_PWR __reg
PHY_RSSI __reg
PHY_ED_LEVEL __reg
PHY_CC_CCA __reg
CCA_THRES __reg
RX_CTRL __reg
SFD_VALUE __reg
TRX_CTRL_2 __reg
ANT_DIV __reg
IRQ_MASK __reg
IRQ_STATUS __reg
IRQ_MASK1 __reg
IRQ_STATUS1 __reg
VREG_CTRL __reg
BATMON __reg
XOSC_CTRL __reg
CC_CTRL_0 __reg
CC_CTRL_1 __reg
RX_SYN __reg
TRX_RPC __reg
XAH_CTRL_1 __reg
FTN_CTRL __reg
PLL_CF __reg
PLL_DCU __reg
PART_NUM __reg
VERSION_NUM __reg
MAN_ID_0 __reg
MAN_ID_1 __reg
SHORT_ADDR_0 __reg
SHORT_ADDR_1 __reg
PAN_ID_0 __reg
PAN_ID_1 __reg
IEEE_ADDR_0 __reg
IEEE_ADDR_1 __reg
IEEE_ADDR_2 __reg
IEEE_ADDR_3 __reg
IEEE_ADDR_4 __reg
IEEE_ADDR_5 __reg
IEEE_ADDR_6 __reg
IEEE_ADDR_7 __reg
XAH_CTRL_0 __reg
CSMA_SEED_0 __reg
CSMA_SEED_1 __reg
CSMA_BE __reg
TST_CTRL_DIGI __reg
TST_RX_LENGTH __reg
TRXFBST __reg
TRXFBEND __reg
}{
PARCR: 0x138, // Power Amplifier Ramp up/down Control Register
MAFSA0L: 0x10e, // Transceiver MAC Short Address Register for Frame Filter 0 (Low Byte)
MAFSA0H: 0x10f, // Transceiver MAC Short Address Register for Frame Filter 0 (High Byte)
MAFPA0L: 0x110, // Transceiver Personal Area Network ID Register for Frame Filter 0 (Low Byte)
MAFPA0H: 0x111, // Transceiver Personal Area Network ID Register for Frame Filter 0 (High Byte)
MAFSA1L: 0x112, // Transceiver MAC Short Address Register for Frame Filter 1 (Low Byte)
MAFSA1H: 0x113, // Transceiver MAC Short Address Register for Frame Filter 1 (High Byte)
MAFPA1L: 0x114, // Transceiver Personal Area Network ID Register for Frame Filter 1 (Low Byte)
MAFPA1H: 0x115, // Transceiver Personal Area Network ID Register for Frame Filter 1 (High Byte)
MAFSA2L: 0x116, // Transceiver MAC Short Address Register for Frame Filter 2 (Low Byte)
MAFSA2H: 0x117, // Transceiver MAC Short Address Register for Frame Filter 2 (High Byte)
MAFPA2L: 0x118, // Transceiver Personal Area Network ID Register for Frame Filter 2 (Low Byte)
MAFPA2H: 0x119, // Transceiver Personal Area Network ID Register for Frame Filter 2 (High Byte)
MAFSA3L: 0x11a, // Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte)
MAFSA3H: 0x11b, // Transceiver MAC Short Address Register for Frame Filter 3 (High Byte)
MAFPA3L: 0x11c, // Transceiver Personal Area Network ID Register for Frame Filter 3 (Low Byte)
MAFPA3H: 0x11d, // Transceiver Personal Area Network ID Register for Frame Filter 3 (High Byte)
MAFCR0: 0x10c, // Multiple Address Filter Configuration Register 0
MAFCR1: 0x10d, // Multiple Address Filter Configuration Register 1
AES_CTRL: 0x13c, // AES Control Register
AES_STATUS: 0x13d, // AES Status Register
AES_STATE: 0x13e, // AES Plain and Cipher Text Buffer Register
AES_KEY: 0x13f, // AES Encryption and Decryption Key Buffer Register
TRX_STATUS: 0x141, // Transceiver Status Register
TRX_STATE: 0x142, // Transceiver State Control Register
TRX_CTRL_0: 0x143, // Reserved
TRX_CTRL_1: 0x144, // Transceiver Control Register 1
PHY_TX_PWR: 0x145, // Transceiver Transmit Power Control Register
PHY_RSSI: 0x146, // Receiver Signal Strength Indicator Register
PHY_ED_LEVEL: 0x147, // Transceiver Energy Detection Level Register
PHY_CC_CCA: 0x148, // Transceiver Clear Channel Assessment (CCA) Control Register
CCA_THRES: 0x149, // Transceiver CCA Threshold Setting Register
RX_CTRL: 0x14a, // Transceiver Receive Control Register
SFD_VALUE: 0x14b, // Start of Frame Delimiter Value Register
TRX_CTRL_2: 0x14c, // Transceiver Control Register 2
ANT_DIV: 0x14d, // Antenna Diversity Control Register
IRQ_MASK: 0x14e, // Transceiver Interrupt Enable Register
IRQ_STATUS: 0x14f, // Transceiver Interrupt Status Register
IRQ_MASK1: 0xbe, // Transceiver Interrupt Enable Register 1
IRQ_STATUS1: 0xbf, // Transceiver Interrupt Status Register 1
VREG_CTRL: 0x150, // Voltage Regulator Control and Status Register
BATMON: 0x151, // Battery Monitor Control and Status Register
XOSC_CTRL: 0x152, // Crystal Oscillator Control Register
CC_CTRL_0: 0x153, // Channel Control Register 0
CC_CTRL_1: 0x154, // Channel Control Register 1
RX_SYN: 0x155, // Transceiver Receiver Sensitivity Control Register
TRX_RPC: 0x156, // Transceiver Reduced Power Consumption Control
XAH_CTRL_1: 0x157, // Transceiver Acknowledgment Frame Control Register 1
FTN_CTRL: 0x158, // Transceiver Filter Tuning Control Register
PLL_CF: 0x15a, // Transceiver Center Frequency Calibration Control Register
PLL_DCU: 0x15b, // Transceiver Delay Cell Calibration Control Register
PART_NUM: 0x15c, // Device Identification Register (Part Number)
VERSION_NUM: 0x15d, // Device Identification Register (Version Number)
MAN_ID_0: 0x15e, // Device Identification Register (Manufacture ID Low Byte)
MAN_ID_1: 0x15f, // Device Identification Register (Manufacture ID High Byte)
SHORT_ADDR_0: 0x160, // Transceiver MAC Short Address Register (Low Byte)
SHORT_ADDR_1: 0x161, // Transceiver MAC Short Address Register (High Byte)
PAN_ID_0: 0x162, // Transceiver Personal Area Network ID Register (Low Byte)
PAN_ID_1: 0x163, // Transceiver Personal Area Network ID Register (High Byte)
IEEE_ADDR_0: 0x164, // Transceiver MAC IEEE Address Register 0
IEEE_ADDR_1: 0x165, // Transceiver MAC IEEE Address Register 1
IEEE_ADDR_2: 0x166, // Transceiver MAC IEEE Address Register 2
IEEE_ADDR_3: 0x167, // Transceiver MAC IEEE Address Register 3
IEEE_ADDR_4: 0x168, // Transceiver MAC IEEE Address Register 4
IEEE_ADDR_5: 0x169, // Transceiver MAC IEEE Address Register 5
IEEE_ADDR_6: 0x16a, // Transceiver MAC IEEE Address Register 6
IEEE_ADDR_7: 0x16b, // Transceiver MAC IEEE Address Register 7
XAH_CTRL_0: 0x16c, // Transceiver Extended Operating Mode Control Register
CSMA_SEED_0: 0x16d, // Transceiver CSMA-CA Random Number Generator Seed Register
CSMA_SEED_1: 0x16e, // Transceiver Acknowledgment Frame Control Register 2
CSMA_BE: 0x16f, // Transceiver CSMA-CA Back-off Exponent Control Register
TST_CTRL_DIGI: 0x176, // Transceiver Digital Test Control Register
TST_RX_LENGTH: 0x17b, // Transceiver Received Frame Length Register
TRXFBST: 0x180, // Start of frame buffer
TRXFBEND: 0x1ff, // End of frame buffer
}
// MAC Symbol Counter
SYMCNT = struct {
SCTSTRHH __reg
SCTSTRHL __reg
SCTSTRLH __reg
SCTSTRLL __reg
SCOCR1HH __reg
SCOCR1HL __reg
SCOCR1LH __reg
SCOCR1LL __reg
SCOCR2HH __reg
SCOCR2HL __reg
SCOCR2LH __reg
SCOCR2LL __reg
SCOCR3HH __reg
SCOCR3HL __reg
SCOCR3LH __reg
SCOCR3LL __reg
SCTSRHH __reg
SCTSRHL __reg
SCTSRLH __reg
SCTSRLL __reg
SCBTSRHH __reg
SCBTSRHL __reg
SCBTSRLH __reg
SCBTSRLL __reg
SCCNTHH __reg
SCCNTHL __reg
SCCNTLH __reg
SCCNTLL __reg
SCIRQS __reg
SCIRQM __reg
SCSR __reg
SCCR1 __reg
SCCR0 __reg
SCCSR __reg
SCRSTRHH __reg
SCRSTRHL __reg
SCRSTRLH __reg
SCRSTRLL __reg
}{
SCTSTRHH: 0xfc, // Symbol Counter Transmit Frame Timestamp Register HH-Byte
SCTSTRHL: 0xfb, // Symbol Counter Transmit Frame Timestamp Register HL-Byte
SCTSTRLH: 0xfa, // Symbol Counter Transmit Frame Timestamp Register LH-Byte
SCTSTRLL: 0xf9, // Symbol Counter Transmit Frame Timestamp Register LL-Byte
SCOCR1HH: 0xf8, // Symbol Counter Output Compare Register 1 HH-Byte
SCOCR1HL: 0xf7, // Symbol Counter Output Compare Register 1 HL-Byte
SCOCR1LH: 0xf6, // Symbol Counter Output Compare Register 1 LH-Byte
SCOCR1LL: 0xf5, // Symbol Counter Output Compare Register 1 LL-Byte
SCOCR2HH: 0xf4, // Symbol Counter Output Compare Register 2 HH-Byte
SCOCR2HL: 0xf3, // Symbol Counter Output Compare Register 2 HL-Byte
SCOCR2LH: 0xf2, // Symbol Counter Output Compare Register 2 LH-Byte
SCOCR2LL: 0xf1, // Symbol Counter Output Compare Register 2 LL-Byte
SCOCR3HH: 0xf0, // Symbol Counter Output Compare Register 3 HH-Byte
SCOCR3HL: 0xef, // Symbol Counter Output Compare Register 3 HL-Byte
SCOCR3LH: 0xee, // Symbol Counter Output Compare Register 3 LH-Byte
SCOCR3LL: 0xed, // Symbol Counter Output Compare Register 3 LL-Byte
SCTSRHH: 0xec, // Symbol Counter Frame Timestamp Register HH-Byte
SCTSRHL: 0xeb, // Symbol Counter Frame Timestamp Register HL-Byte
SCTSRLH: 0xea, // Symbol Counter Frame Timestamp Register LH-Byte
SCTSRLL: 0xe9, // Symbol Counter Frame Timestamp Register LL-Byte
SCBTSRHH: 0xe8, // Symbol Counter Beacon Timestamp Register HH-Byte
SCBTSRHL: 0xe7, // Symbol Counter Beacon Timestamp Register HL-Byte
SCBTSRLH: 0xe6, // Symbol Counter Beacon Timestamp Register LH-Byte
SCBTSRLL: 0xe5, // Symbol Counter Beacon Timestamp Register LL-Byte
SCCNTHH: 0xe4, // Symbol Counter Register HH-Byte
SCCNTHL: 0xe3, // Symbol Counter Register HL-Byte
SCCNTLH: 0xe2, // Symbol Counter Register LH-Byte
SCCNTLL: 0xe1, // Symbol Counter Register LL-Byte
SCIRQS: 0xe0, // Symbol Counter Interrupt Status Register
SCIRQM: 0xdf, // Symbol Counter Interrupt Mask Register
SCSR: 0xde, // Symbol Counter Status Register
SCCR1: 0xdd, // Symbol Counter Control Register 1
SCCR0: 0xdc, // Symbol Counter Control Register 0
SCCSR: 0xdb, // Symbol Counter Compare Source Register
SCRSTRHH: 0xda, // Symbol Counter Received Frame Timestamp Register HH-Byte
SCRSTRHL: 0xd9, // Symbol Counter Received Frame Timestamp Register HL-Byte
SCRSTRLH: 0xd8, // Symbol Counter Received Frame Timestamp Register LH-Byte
SCRSTRLL: 0xd7, // Symbol Counter Received Frame Timestamp Register LL-Byte
}
// EEPROM
EEPROM = struct {
EEARL __reg
EEARH __reg
EEDR __reg
EECR __reg
}{
EEARL: 0x41, // EEPROM Address Register Bytes
EEARH: 0x41, // EEPROM Address Register Bytes
EEDR: 0x40, // EEPROM Data Register
EECR: 0x3f, // EEPROM Control Register
}
// JTAG Interface
JTAG = struct {
OCDR __reg
}{
OCDR: 0x51, // On-Chip Debug Register
}
// External Interrupts
EXINT = struct {
EICRA __reg
EICRB __reg
EIMSK __reg
EIFR __reg
PCMSK2 __reg
PCMSK1 __reg
PCMSK0 __reg
PCIFR __reg
PCICR __reg
}{
EICRA: 0x69, // External Interrupt Control Register A
EICRB: 0x6a, // External Interrupt Control Register B
EIMSK: 0x3d, // External Interrupt Mask Register
EIFR: 0x3c, // External Interrupt Flag Register
PCMSK2: 0x6d, // Pin Change Mask Register 2
PCMSK1: 0x6c, // Pin Change Mask Register 1
PCMSK0: 0x6b, // Pin Change Mask Register 0
PCIFR: 0x3b, // Pin Change Interrupt Flag Register
PCICR: 0x68, // Pin Change Interrupt Control Register
}
// Analog-to-Digital Converter
ADC = struct {
ADMUX __reg
ADCL __reg
ADCH __reg
ADCSRA __reg
ADCSRC __reg
DIDR2 __reg
DIDR0 __reg
}{
ADMUX: 0x7c, // The ADC Multiplexer Selection Register
ADCL: 0x78, // ADC Data Register Bytes
ADCH: 0x78, // ADC Data Register Bytes
ADCSRA: 0x7a, // The ADC Control and Status Register A
ADCSRC: 0x77, // The ADC Control and Status Register C
DIDR2: 0x7d, // Digital Input Disable Register 2
DIDR0: 0x7e, // Digital Input Disable Register 0
}
// Bootloader
BOOT_LOAD = struct {
SPMCSR __reg
}{
SPMCSR: 0x57, // Store Program Memory Control Register
}
// CPU Registers
CPU = struct {
SREG __reg
SPL __reg
SPH __reg
OSCCAL __reg
CLKPR __reg
SMCR __reg
GPIOR2 __reg
GPIOR1 __reg
GPIOR0 __reg
PRR2 __reg
PRR1 __reg
PRR0 __reg
}{
SREG: 0x5f, // Status Register
SPL: 0x5d, // Stack Pointer
SPH: 0x5d, // Stack Pointer
OSCCAL: 0x66, // Oscillator Calibration Value
CLKPR: 0x61, // Clock Prescale Register
SMCR: 0x53, // Sleep Mode Control Register
GPIOR2: 0x4b, // General Purpose I/O Register 2
GPIOR1: 0x4a, // General Purpose IO Register 1
GPIOR0: 0x3e, // General Purpose IO Register 0
PRR2: 0x63, // Power Reduction Register 2
PRR1: 0x65, // Power Reduction Register 1
PRR0: 0x64, // Power Reduction Register0
}
// FLASH Controller
FLASH = struct {
NEMCR __reg
BGCR __reg
}{
NEMCR: 0x75, // Flash Extended-Mode Control-Register
BGCR: 0x67, // Reference Voltage Calibration Register
}
// Power Controller
PWRCTRL = struct {
TRXPR __reg
DRTRAM0 __reg
DRTRAM1 __reg
DRTRAM2 __reg
DRTRAM3 __reg
LLDRL __reg
LLDRH __reg
LLCR __reg
DPDS0 __reg
DPDS1 __reg
}{
TRXPR: 0x139, // Transceiver Pin Register
DRTRAM0: 0x135, // Data Retention Configuration Register #0
DRTRAM1: 0x134, // Data Retention Configuration Register #1
DRTRAM2: 0x133, // Data Retention Configuration Register #2
DRTRAM3: 0x132, // Data Retention Configuration Register #3
LLDRL: 0x130, // Low Leakage Voltage Regulator Data Register (Low-Byte)
LLDRH: 0x131, // Low Leakage Voltage Regulator Data Register (High-Byte)
LLCR: 0x12f, // Low Leakage Voltage Regulator Control Register
DPDS0: 0x136, // Port Driver Strength Register 0
DPDS1: 0x137, // Port Driver Strength Register 1
}
)
// Bitfields for FUSE: Fuses
const (
// EXTENDED
EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level
// HIGH
HIGH_OCDEN = 0x80 // On-Chip Debug Enabled
HIGH_JTAGEN = 0x40 // JTAG Interface Enabled
HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled
HIGH_WDTON = 0x10 // Watchdog timer always on
HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle
HIGH_BOOTSZ = 0x6 // Select Boot Size
HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled
// LOW
LOW_CKDIV8 = 0x80 // Divide clock by 8 internally
LOW_CKOUT = 0x40 // Clock output on PORTE7
LOW_CKSEL_SUT = 0x3f // Select Clock Source : Start-up time
)
// Bitfields for LOCKBIT: Lockbits
const (
// LOCKBIT
LOCKBIT_LB = 0x3 // Memory Lock
LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode
LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode
)
// Bitfields for AC: Analog Comparator
const (
// ACSR: Analog Comparator Control And Status Register
ACSR_ACD = 0x80 // Analog Comparator Disable
ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select
ACSR_ACO = 0x20 // Analog Compare Output
ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag
ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable
ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable
ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select
// DIDR1: Digital Input Disable Register 1
DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable
DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable
)
// Bitfields for TWI: Two Wire Serial Interface
const (
// TWAMR: TWI (Slave) Address Mask Register
TWAMR_TWAM = 0xfe // TWI Address Mask
TWAMR_Res = 0x1 // Reserved Bit
// TWCR: TWI Control Register
TWCR_TWINT = 0x80 // TWI Interrupt Flag
TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit
TWCR_TWSTA = 0x20 // TWI START Condition Bit
TWCR_TWSTO = 0x10 // TWI STOP Condition Bit
TWCR_TWWC = 0x8 // TWI Write Collision Flag
TWCR_TWEN = 0x4 // TWI Enable Bit
TWCR_Res = 0x2 // Reserved Bit
TWCR_TWIE = 0x1 // TWI Interrupt Enable
// TWSR: TWI Status Register
TWSR_TWS = 0xf8 // TWI Status
TWSR_Res = 0x4 // Reserved Bit
TWSR_TWPS = 0x3 // TWI Prescaler Bits
// TWAR: TWI (Slave) Address Register
TWAR_TWA = 0xfe // TWI (Slave) Address
TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit
)
// Bitfields for SPI: Serial Peripheral Interface
const (
// SPCR: SPI Control Register
SPCR_SPIE = 0x80 // SPI Interrupt Enable
SPCR_SPE = 0x40 // SPI Enable
SPCR_DORD = 0x20 // Data Order
SPCR_MSTR = 0x10 // Master/Slave Select
SPCR_CPOL = 0x8 // Clock polarity
SPCR_CPHA = 0x4 // Clock Phase
SPCR_SPR = 0x3 // SPI Clock Rate Select 1 and 0
// SPSR: SPI Status Register
SPSR_SPIF = 0x80 // SPI Interrupt Flag
SPSR_WCOL = 0x40 // Write Collision Flag
SPSR_SPI2X = 0x1 // Double SPI Speed Bit
)
// Bitfields for TC8: Timer/Counter, 8-bit
const (
// TCCR0B: Timer/Counter0 Control Register B
TCCR0B_FOC0A = 0x80 // Force Output Compare A
TCCR0B_FOC0B = 0x40 // Force Output Compare B
TCCR0B_Res = 0x30 // Reserved Bit
TCCR0B_WGM02 = 0x8
TCCR0B_CS0 = 0x7 // Clock Select
// TCCR0A: Timer/Counter0 Control Register A
TCCR0A_COM0A = 0xc0 // Compare Match Output A Mode
TCCR0A_COM0B = 0x30 // Compare Match Output B Mode
TCCR0A_Res = 0xc // Reserved Bit
TCCR0A_WGM0 = 0x3 // Waveform Generation Mode
// TIMSK0: Timer/Counter0 Interrupt Mask Register
TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable
TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable
TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable
// TIFR0: Timer/Counter0 Interrupt Flag Register
TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare B Match Flag
TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare A Match Flag
TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag
)
// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async
const (
// TIMSK2: Timer/Counter Interrupt Mask register
TIMSK2_Res = 0xf8 // Reserved Bit
TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable
TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable
TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable
// TIFR2: Timer/Counter Interrupt Flag Register
TIFR2_Res = 0xf8 // Reserved Bit
TIFR2_OCF2B = 0x4 // Output Compare Flag 2 B
TIFR2_OCF2A = 0x2 // Output Compare Flag 2 A
TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag
// TCCR2A: Timer/Counter2 Control Register A
TCCR2A_COM2A = 0xc0 // Compare Match Output A Mode
TCCR2A_COM2B = 0x30 // Compare Match Output B Mode
TCCR2A_WGM2 = 0x3 // Waveform Generation Mode
// TCCR2B: Timer/Counter2 Control Register B
TCCR2B_FOC2A = 0x80 // Force Output Compare A
TCCR2B_FOC2B = 0x40 // Force Output Compare B
TCCR2B_WGM22 = 0x8 // Waveform Generation Mode
TCCR2B_CS2 = 0x7 // Clock Select
// ASSR: Asynchronous Status Register
ASSR_EXCLKAMR = 0x80 // Enable External Clock Input for AMR
ASSR_EXCLK = 0x40 // Enable External Clock Input
ASSR_AS2 = 0x20 // Timer/Counter2 Asynchronous Mode
ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy
ASSR_OCR2AUB = 0x8 // Timer/Counter2 Output Compare Register A Update Busy
ASSR_OCR2BUB = 0x4 // Timer/Counter2 Output Compare Register B Update Busy
ASSR_TCR2AUB = 0x2 // Timer/Counter2 Control Register A Update Busy
ASSR_TCR2BUB = 0x1 // Timer/Counter2 Control Register B Update Busy
)
// Bitfields for WDT: Watchdog Timer
const (
// WDTCSR: Watchdog Timer Control Register
WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag
WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable
WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits
WDTCSR_WDCE = 0x10 // Watchdog Change Enable
WDTCSR_WDE = 0x8 // Watch Dog Enable
)
// Bitfields for TC16: Timer/Counter, 16-bit
const (
// TCCR5A: Timer/Counter5 Control Register A
TCCR5A_COM5A = 0xc0 // Compare Output Mode for Channel A
TCCR5A_COM5B = 0x30 // Compare Output Mode for Channel B
TCCR5A_COM5C = 0xc // Compare Output Mode for Channel C
TCCR5A_WGM5 = 0x3 // Waveform Generation Mode
// TCCR5B: Timer/Counter5 Control Register B
TCCR5B_ICNC5 = 0x80 // Input Capture 5 Noise Canceller
TCCR5B_ICES5 = 0x40 // Input Capture 5 Edge Select
TCCR5B_Res = 0x20 // Reserved Bit
TCCR5B_WGM5 = 0x18 // Waveform Generation Mode
TCCR5B_CS5 = 0x7 // Clock Select
// TCCR5C: Timer/Counter5 Control Register C
TCCR5C_FOC5A = 0x80 // Force Output Compare for Channel A
TCCR5C_FOC5B = 0x40 // Force Output Compare for Channel B
TCCR5C_FOC5C = 0x20 // Force Output Compare for Channel C
// TIMSK5: Timer/Counter5 Interrupt Mask Register
TIMSK5_ICIE5 = 0x20 // Timer/Counter5 Input Capture Interrupt Enable
TIMSK5_OCIE5C = 0x8 // Timer/Counter5 Output Compare C Match Interrupt Enable
TIMSK5_OCIE5B = 0x4 // Timer/Counter5 Output Compare B Match Interrupt Enable
TIMSK5_OCIE5A = 0x2 // Timer/Counter5 Output Compare A Match Interrupt Enable
TIMSK5_TOIE5 = 0x1 // Timer/Counter5 Overflow Interrupt Enable
// TIFR5: Timer/Counter5 Interrupt Flag Register
TIFR5_ICF5 = 0x20 // Timer/Counter5 Input Capture Flag
TIFR5_OCF5C = 0x8 // Timer/Counter5 Output Compare C Match Flag
TIFR5_OCF5B = 0x4 // Timer/Counter5 Output Compare B Match Flag
TIFR5_OCF5A = 0x2 // Timer/Counter5 Output Compare A Match Flag
TIFR5_TOV5 = 0x1 // Timer/Counter5 Overflow Flag
// TCCR4A: Timer/Counter4 Control Register A
TCCR4A_COM4A = 0xc0 // Compare Output Mode for Channel A
TCCR4A_COM4B = 0x30 // Compare Output Mode for Channel B
TCCR4A_COM4C = 0xc // Compare Output Mode for Channel C
TCCR4A_WGM4 = 0x3 // Waveform Generation Mode
// TCCR4B: Timer/Counter4 Control Register B
TCCR4B_ICNC4 = 0x80 // Input Capture 4 Noise Canceller
TCCR4B_ICES4 = 0x40 // Input Capture 4 Edge Select
TCCR4B_Res = 0x20 // Reserved Bit
TCCR4B_WGM4 = 0x18 // Waveform Generation Mode
TCCR4B_CS4 = 0x7 // Clock Select
// TCCR4C: Timer/Counter4 Control Register C
TCCR4C_FOC4A = 0x80 // Force Output Compare for Channel A
TCCR4C_FOC4B = 0x40 // Force Output Compare for Channel B
TCCR4C_FOC4C = 0x20 // Force Output Compare for Channel C
// TIMSK4: Timer/Counter4 Interrupt Mask Register
TIMSK4_ICIE4 = 0x20 // Timer/Counter4 Input Capture Interrupt Enable
TIMSK4_OCIE4C = 0x8 // Timer/Counter4 Output Compare C Match Interrupt Enable
TIMSK4_OCIE4B = 0x4 // Timer/Counter4 Output Compare B Match Interrupt Enable
TIMSK4_OCIE4A = 0x2 // Timer/Counter4 Output Compare A Match Interrupt Enable
TIMSK4_TOIE4 = 0x1 // Timer/Counter4 Overflow Interrupt Enable
// TIFR4: Timer/Counter4 Interrupt Flag Register
TIFR4_ICF4 = 0x20 // Timer/Counter4 Input Capture Flag
TIFR4_OCF4C = 0x8 // Timer/Counter4 Output Compare C Match Flag
TIFR4_OCF4B = 0x4 // Timer/Counter4 Output Compare B Match Flag
TIFR4_OCF4A = 0x2 // Timer/Counter4 Output Compare A Match Flag
TIFR4_TOV4 = 0x1 // Timer/Counter4 Overflow Flag
// TCCR3A: Timer/Counter3 Control Register A
TCCR3A_COM3A = 0xc0 // Compare Output Mode for Channel A
TCCR3A_COM3B = 0x30 // Compare Output Mode for Channel B
TCCR3A_COM3C = 0xc // Compare Output Mode for Channel C
TCCR3A_WGM3 = 0x3 // Waveform Generation Mode
// TCCR3B: Timer/Counter3 Control Register B
TCCR3B_ICNC3 = 0x80 // Input Capture 3 Noise Canceller
TCCR3B_ICES3 = 0x40 // Input Capture 3 Edge Select
TCCR3B_Res = 0x20 // Reserved Bit
TCCR3B_WGM3 = 0x18 // Waveform Generation Mode
TCCR3B_CS3 = 0x7 // Clock Select
// TCCR3C: Timer/Counter3 Control Register C
TCCR3C_FOC3A = 0x80 // Force Output Compare for Channel A
TCCR3C_FOC3B = 0x40 // Force Output Compare for Channel B
TCCR3C_FOC3C = 0x20 // Force Output Compare for Channel C
// TIMSK3: Timer/Counter3 Interrupt Mask Register
TIMSK3_ICIE3 = 0x20 // Timer/Counter3 Input Capture Interrupt Enable
TIMSK3_OCIE3C = 0x8 // Timer/Counter3 Output Compare C Match Interrupt Enable
TIMSK3_OCIE3B = 0x4 // Timer/Counter3 Output Compare B Match Interrupt Enable
TIMSK3_OCIE3A = 0x2 // Timer/Counter3 Output Compare A Match Interrupt Enable
TIMSK3_TOIE3 = 0x1 // Timer/Counter3 Overflow Interrupt Enable
// TIFR3: Timer/Counter3 Interrupt Flag Register
TIFR3_ICF3 = 0x20 // Timer/Counter3 Input Capture Flag
TIFR3_OCF3C = 0x8 // Timer/Counter3 Output Compare C Match Flag
TIFR3_OCF3B = 0x4 // Timer/Counter3 Output Compare B Match Flag
TIFR3_OCF3A = 0x2 // Timer/Counter3 Output Compare A Match Flag
TIFR3_TOV3 = 0x1 // Timer/Counter3 Overflow Flag
// TCCR1A: Timer/Counter1 Control Register A
TCCR1A_COM1A = 0xc0 // Compare Output Mode for Channel A
TCCR1A_COM1B = 0x30 // Compare Output Mode for Channel B
TCCR1A_COM1C = 0xc // Compare Output Mode for Channel C
TCCR1A_WGM1 = 0x3 // Waveform Generation Mode
// TCCR1B: Timer/Counter1 Control Register B
TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceller
TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select
TCCR1B_Res = 0x20 // Reserved Bit
TCCR1B_WGM1 = 0x18 // Waveform Generation Mode
TCCR1B_CS1 = 0x7 // Clock Select
// TCCR1C: Timer/Counter1 Control Register C
TCCR1C_FOC1A = 0x80 // Force Output Compare for Channel A
TCCR1C_FOC1B = 0x40 // Force Output Compare for Channel B
TCCR1C_FOC1C = 0x20 // Force Output Compare for Channel C
// TIMSK1: Timer/Counter1 Interrupt Mask Register
TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable
TIMSK1_OCIE1C = 0x8 // Timer/Counter1 Output Compare C Match Interrupt Enable
TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable
TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable
TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable
// TIFR1: Timer/Counter1 Interrupt Flag Register
TIFR1_ICF1 = 0x20 // Timer/Counter1 Input Capture Flag
TIFR1_OCF1C = 0x8 // Timer/Counter1 Output Compare C Match Flag
TIFR1_OCF1B = 0x4 // Timer/Counter1 Output Compare B Match Flag
TIFR1_OCF1A = 0x2 // Timer/Counter1 Output Compare A Match Flag
TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag
)
// Bitfields for TRX24: Low-Power 2.4 GHz Transceiver
const (
// PARCR: Power Amplifier Ramp up/down Control Register
PARCR_PALTD = 0xe0 // ext. PA Ramp Down Lead Time
PARCR_PALTU = 0x1c // ext. PA Ramp Up Lead Time
PARCR_PARDFI = 0x2 // Power Amplifier Ramp Down Frequency Inversion
PARCR_PARUFI = 0x1 // Power Amplifier Ramp Up Frequency Inversion
// MAFSA0L: Transceiver MAC Short Address Register for Frame Filter 0 (Low Byte)
MAFSA0L_MAFSA0L = 0xff // MAC Short Address low Byte for Frame Filter 0
// MAFSA0H: Transceiver MAC Short Address Register for Frame Filter 0 (High Byte)
MAFSA0H_MAFSA0H = 0xff // MAC Short Address high Byte for Frame Filter 0
// MAFPA0L: Transceiver Personal Area Network ID Register for Frame Filter 0 (Low Byte)
MAFPA0L_MAFPA0L = 0xff // MAC Personal Area Network ID low Byte for Frame Filter 0
// MAFPA0H: Transceiver Personal Area Network ID Register for Frame Filter 0 (High Byte)
MAFPA0H_MAFPA0H = 0xff // MAC Personal Area Network ID high Byte for Frame Filter 0
// MAFSA1L: Transceiver MAC Short Address Register for Frame Filter 1 (Low Byte)
MAFSA1L_MAFSA1L = 0xff // MAC Short Address low Byte for Frame Filter 1
// MAFSA1H: Transceiver MAC Short Address Register for Frame Filter 1 (High Byte)
MAFSA1H_MAFSA1H = 0xff // MAC Short Address high Byte for Frame Filter 1
// MAFPA1L: Transceiver Personal Area Network ID Register for Frame Filter 1 (Low Byte)
MAFPA1L_MAFPA1L = 0xff // MAC Personal Area Network ID low Byte for Frame Filter 1
// MAFPA1H: Transceiver Personal Area Network ID Register for Frame Filter 1 (High Byte)
MAFPA1H_MAFPA1H = 0xff // MAC Personal Area Network ID high Byte for Frame Filter 1
// MAFSA2L: Transceiver MAC Short Address Register for Frame Filter 2 (Low Byte)
MAFSA2L_MAFSA2L = 0xff // MAC Short Address low Byte for Frame Filter 2
// MAFSA2H: Transceiver MAC Short Address Register for Frame Filter 2 (High Byte)
MAFSA2H_MAFSA2H = 0xff // MAC Short Address high Byte for Frame Filter 2
// MAFPA2L: Transceiver Personal Area Network ID Register for Frame Filter 2 (Low Byte)
MAFPA2L_MAFPA2L = 0xff // MAC Personal Area Network ID low Byte for Frame Filter 2
// MAFPA2H: Transceiver Personal Area Network ID Register for Frame Filter 2 (High Byte)
MAFPA2H_MAFPA2H = 0xff // MAC Personal Area Network ID high Byte for Frame Filter 2
// MAFSA3L: Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte)
MAFSA3L_MAFSA3L = 0xff // MAC Short Address low Byte for Frame Filter 3
// MAFSA3H: Transceiver MAC Short Address Register for Frame Filter 3 (High Byte)
MAFSA3H_MAFSA3H = 0xff // MAC Short Address high Byte for Frame Filter 3
// MAFPA3L: Transceiver Personal Area Network ID Register for Frame Filter 3 (Low Byte)
MAFPA3L_MAFPA3L = 0xff // MAC Personal Area Network ID low Byte for Frame Filter 3
// MAFPA3H: Transceiver Personal Area Network ID Register for Frame Filter 3 (High Byte)
MAFPA3H_MAFPA3H = 0xff // MAC Personal Area Network ID high Byte for Frame Filter 3
// MAFCR0: Multiple Address Filter Configuration Register 0
MAFCR0_Res = 0xf0 // Reserved Bit
MAFCR0_MAF3EN = 0x8 // Multiple Address Filter 3 Enable
MAFCR0_MAF2EN = 0x4 // Multiple Address Filter 2 Enable
MAFCR0_MAF1EN = 0x2 // Multiple Address Filter 1 Enable
MAFCR0_MAF0EN = 0x1 // Multiple Address Filter 0 Enable
// MAFCR1: Multiple Address Filter Configuration Register 1
MAFCR1_AACK_3_SET_PD = 0x80 // Set Data Pending bit for address filter 3.
MAFCR1_AACK_3_I_AM_COORD = 0x40 // Enable PAN Coordinator mode for address filter 3.
MAFCR1_AACK_2_SET_PD = 0x20 // Set Data Pending bit for address filter 2.
MAFCR1_AACK_2_I_AM_COORD = 0x10 // Enable PAN Coordinator mode for address filter 2.
MAFCR1_AACK_1_SET_PD = 0x8 // Set Data Pending bit for address filter 1.
MAFCR1_AACK_1_I_AM_COORD = 0x4 // Enable PAN Coordinator mode for address filter 1.
MAFCR1_AACK_0_SET_PD = 0x2 // Set Data Pending bit for address filter 0.
MAFCR1_AACK_0_I_AM_COORD = 0x1 // Enable PAN Coordinator mode for address filter 0.
// AES_CTRL: AES Control Register
AES_CTRL_AES_REQUEST = 0x80 // Request AES Operation.
AES_CTRL_AES_MODE = 0x20 // Set AES Operation Mode
AES_CTRL_AES_DIR = 0x8 // Set AES Operation Direction
AES_CTRL_AES_IM = 0x4 // AES Interrupt Enable
// AES_STATUS: AES Status Register
AES_STATUS_AES_ER = 0x80 // AES Operation Finished with Error
AES_STATUS_AES_DONE = 0x1 // AES Operation Finished with Success
// AES_STATE: AES Plain and Cipher Text Buffer Register
AES_STATE_AES_STATE = 0xff // AES Plain and Cipher Text Buffer
// AES_KEY: AES Encryption and Decryption Key Buffer Register
AES_KEY_AES_KEY = 0xff // AES Encryption/Decryption Key Buffer
// TRX_STATUS: Transceiver Status Register
TRX_STATUS_CCA_DONE = 0x80 // CCA Algorithm Status
TRX_STATUS_CCA_STATUS = 0x40 // CCA Status Result
TRX_STATUS_TST_STATUS = 0x20 // Test mode status
TRX_STATUS_TRX_STATUS = 0x1f // Transceiver Main Status
// TRX_STATE: Transceiver State Control Register
TRX_STATE_TRAC_STATUS = 0xe0 // Transaction Status
TRX_STATE_TRX_CMD = 0x1f // State Control Command
// TRX_CTRL_0: Reserved
TRX_CTRL_0_Res7 = 0x80 // Reserved
TRX_CTRL_0_PMU_EN = 0x40 // Enable Phase Measurement Unit
TRX_CTRL_0_PMU_START = 0x20 // Start of Phase Measurement Unit
TRX_CTRL_0_PMU_IF_INV = 0x10 // PMU IF Inverse
// TRX_CTRL_1: Transceiver Control Register 1
TRX_CTRL_1_PA_EXT_EN = 0x80 // External PA support enable
TRX_CTRL_1_IRQ_2_EXT_EN = 0x40 // Connect Frame Start IRQ to TC1
TRX_CTRL_1_TX_AUTO_CRC_ON = 0x20 // Enable Automatic CRC Calculation
TRX_CTRL_1_PLL_TX_FLT = 0x10 // Enable PLL TX filter
// PHY_TX_PWR: Transceiver Transmit Power Control Register
PHY_TX_PWR_TX_PWR = 0xf // Transmit Power Setting
// PHY_RSSI: Receiver Signal Strength Indicator Register
PHY_RSSI_RX_CRC_VALID = 0x80 // Received Frame CRC Status
PHY_RSSI_RND_VALUE = 0x60 // Random Value
PHY_RSSI_RSSI = 0x1f // Receiver Signal Strength Indicator
// PHY_ED_LEVEL: Transceiver Energy Detection Level Register
PHY_ED_LEVEL_ED_LEVEL = 0xff // Energy Detection Level
// PHY_CC_CCA: Transceiver Clear Channel Assessment (CCA) Control Register
PHY_CC_CCA_CCA_REQUEST = 0x80 // Manual CCA Measurement Request
PHY_CC_CCA_CCA_MODE = 0x60 // Select CCA Measurement Mode
PHY_CC_CCA_CHANNEL = 0x1f // RX/TX Channel Selection
// CCA_THRES: Transceiver CCA Threshold Setting Register
CCA_THRES_CCA_CS_THRES = 0xf0 // CS Threshold Level for CCA Measurement
CCA_THRES_CCA_ED_THRES = 0xf // ED Threshold Level for CCA Measurement
// RX_CTRL: Transceiver Receive Control Register
RX_CTRL_PDT_THRES = 0xf // Receiver Sensitivity Control
// SFD_VALUE: Start of Frame Delimiter Value Register
SFD_VALUE_SFD_VALUE = 0xff // Start of Frame Delimiter Value
// TRX_CTRL_2: Transceiver Control Register 2
TRX_CTRL_2_RX_SAFE_MODE = 0x80 // RX Safe Mode
TRX_CTRL_2_OQPSK_DATA_RATE = 0x3 // Data Rate Selection
// ANT_DIV: Antenna Diversity Control Register
ANT_DIV_ANT_SEL = 0x80 // Antenna Diversity Antenna Status
ANT_DIV_ANT_DIV_EN = 0x8 // Enable Antenna Diversity
ANT_DIV_ANT_EXT_SW_EN = 0x4 // Enable External Antenna Switch Control
ANT_DIV_ANT_CTRL = 0x3 // Static Antenna Diversity Switch Control
// IRQ_MASK: Transceiver Interrupt Enable Register
IRQ_MASK_AWAKE_EN = 0x80 // Awake Interrupt Enable
IRQ_MASK_TX_END_EN = 0x40 // TX_END Interrupt Enable
IRQ_MASK_AMI_EN = 0x20 // Address Match Interrupt Enable
IRQ_MASK_CCA_ED_DONE_EN = 0x10 // End of ED Measurement Interrupt Enable
IRQ_MASK_RX_END_EN = 0x8 // RX_END Interrupt Enable
IRQ_MASK_RX_START_EN = 0x4 // RX_START Interrupt Enable
IRQ_MASK_PLL_UNLOCK_EN = 0x2 // PLL Unlock Interrupt Enable
IRQ_MASK_PLL_LOCK_EN = 0x1 // PLL Lock Interrupt Enable
// IRQ_STATUS: Transceiver Interrupt Status Register
IRQ_STATUS_AWAKE = 0x80 // Awake Interrupt Status
IRQ_STATUS_TX_END = 0x40 // TX_END Interrupt Status
IRQ_STATUS_AMI = 0x20 // Address Match Interrupt Status
IRQ_STATUS_CCA_ED_DONE = 0x10 // End of ED Measurement Interrupt Status
IRQ_STATUS_RX_END = 0x8 // RX_END Interrupt Status
IRQ_STATUS_RX_START = 0x4 // RX_START Interrupt Status
IRQ_STATUS_PLL_UNLOCK = 0x2 // PLL Unlock Interrupt Status
IRQ_STATUS_PLL_LOCK = 0x1 // PLL Lock Interrupt Status
// IRQ_MASK1: Transceiver Interrupt Enable Register 1
IRQ_MASK1_Res = 0xe0 // Reserved Bit
IRQ_MASK1_MAF_3_AMI_EN = 0x10 // Address Match Interrupt enable Address filter 3
IRQ_MASK1_MAF_2_AMI_EN = 0x8 // Address Match Interrupt enable Address filter 2
IRQ_MASK1_MAF_1_AMI_EN = 0x4 // Address Match Interrupt enable Address filter 1
IRQ_MASK1_MAF_0_AMI_EN = 0x2 // Address Match Interrupt enable Address filter 0
IRQ_MASK1_TX_START_EN = 0x1 // Transmit Start Interrupt enable
// IRQ_STATUS1: Transceiver Interrupt Status Register 1
IRQ_STATUS1_Res = 0xe0 // Reserved Bit
IRQ_STATUS1_MAF_3_AMI = 0x10 // Address Match Interrupt Status Address filter 3
IRQ_STATUS1_MAF_2_AMI = 0x8 // Address Match Interrupt Status Address filter 2
IRQ_STATUS1_MAF_1_AMI = 0x4 // Address Match Interrupt Status Address filter 1
IRQ_STATUS1_MAF_0_AMI = 0x2 // Address Match Interrupt Status Address filter 0
IRQ_STATUS1_TX_START = 0x1 // Transmit Start Interrupt Status
// VREG_CTRL: Voltage Regulator Control and Status Register
VREG_CTRL_AVREG_EXT = 0x80 // Use External AVDD Regulator
VREG_CTRL_AVDD_OK = 0x40 // AVDD Supply Voltage Valid
VREG_CTRL_DVREG_EXT = 0x8 // Use External DVDD Regulator
VREG_CTRL_DVDD_OK = 0x4 // DVDD Supply Voltage Valid
// BATMON: Battery Monitor Control and Status Register
BATMON_BAT_LOW = 0x80 // Battery Monitor Interrupt Status
BATMON_BAT_LOW_EN = 0x40 // Battery Monitor Interrupt Enable
BATMON_BATMON_OK = 0x20 // Battery Monitor Status
BATMON_BATMON_HR = 0x10 // Battery Monitor Voltage Range
BATMON_BATMON_VTH = 0xf // Battery Monitor Threshold Voltage
// XOSC_CTRL: Crystal Oscillator Control Register
XOSC_CTRL_XTAL_MODE = 0xf0 // Crystal Oscillator Operating Mode
XOSC_CTRL_XTAL_TRIM = 0xf // Crystal Oscillator Load Capacitance Trimming
// CC_CTRL_0: Channel Control Register 0
CC_CTRL_0_CC_NUMBER = 0xff // Channel Number
// CC_CTRL_1: Channel Control Register 1
CC_CTRL_1_CC_BAND = 0xf // Channel Band
// RX_SYN: Transceiver Receiver Sensitivity Control Register
RX_SYN_RX_PDT_DIS = 0x80 // Prevent Frame Reception
RX_SYN_RX_OVERRIDE = 0x40 // Receiver Override Function
RX_SYN_RX_PDT_LEVEL = 0xf // Reduce Receiver Sensitivity
// TRX_RPC: Transceiver Reduced Power Consumption Control
TRX_RPC_RX_RPC_CTRL = 0xc0 // Smart Receiving Mode Timing
TRX_RPC_RX_RPC_EN = 0x20 // Reciver Smart Receiving Mode Enable
TRX_RPC_PDT_RPC_EN = 0x10 // Smart Receiving Mode Reduced Sensitivity Enable
TRX_RPC_PLL_RPC_EN = 0x8 // PLL Smart Receiving Mode Enable
TRX_RPC_Res0 = 0x4 // Reserved
TRX_RPC_IPAN_RPC_EN = 0x2 // Smart Receiving Mode IPAN Handling Enable
TRX_RPC_XAH_RPC_EN = 0x1 // Smart Receiving in Extended Operating Modes Enable
// XAH_CTRL_1: Transceiver Acknowledgment Frame Control Register 1
XAH_CTRL_1_AACK_FLTR_RES_FT = 0x20 // Filter Reserved Frames
XAH_CTRL_1_AACK_UPLD_RES_FT = 0x10 // Process Reserved Frames
XAH_CTRL_1_AACK_ACK_TIME = 0x4 // Reduce Acknowledgment Time
XAH_CTRL_1_AACK_PROM_MODE = 0x2 // Enable Promiscuous Mode
// FTN_CTRL: Transceiver Filter Tuning Control Register
FTN_CTRL_FTN_START = 0x80 // Start Calibration Loop of Filter Tuning Network
// PLL_CF: Transceiver Center Frequency Calibration Control Register
PLL_CF_PLL_CF_START = 0x80 // Start Center Frequency Calibration
// PLL_DCU: Transceiver Delay Cell Calibration Control Register
PLL_DCU_PLL_DCU_START = 0x80 // Start Delay Cell Calibration
// PART_NUM: Device Identification Register (Part Number)
PART_NUM_PART_NUM = 0xff // Part Number
// VERSION_NUM: Device Identification Register (Version Number)
VERSION_NUM_VERSION_NUM = 0xff // Version Number
// MAN_ID_0: Device Identification Register (Manufacture ID Low Byte)
MAN_ID_0_MAN_ID_07 = 0x80 // Manufacturer ID (Low Byte)
MAN_ID_0_MAN_ID_06 = 0x40 // Manufacturer ID (Low Byte)
MAN_ID_0_MAN_ID_05 = 0x20 // Manufacturer ID (Low Byte)
MAN_ID_0_MAN_ID_04 = 0x10 // Manufacturer ID (Low Byte)
MAN_ID_0_MAN_ID_03 = 0x8 // Manufacturer ID (Low Byte)
MAN_ID_0_MAN_ID_02 = 0x4 // Manufacturer ID (Low Byte)
MAN_ID_0_MAN_ID_01 = 0x2 // Manufacturer ID (Low Byte)
MAN_ID_0_MAN_ID_00 = 0x1 // Manufacturer ID (Low Byte)
// MAN_ID_1: Device Identification Register (Manufacture ID High Byte)
MAN_ID_1_MAN_ID_ = 0xff // Manufacturer ID (High Byte)
// SHORT_ADDR_0: Transceiver MAC Short Address Register (Low Byte)
SHORT_ADDR_0_SHORT_ADDR_07 = 0x80 // MAC Short Address
SHORT_ADDR_0_SHORT_ADDR_06 = 0x40 // MAC Short Address
SHORT_ADDR_0_SHORT_ADDR_05 = 0x20 // MAC Short Address
SHORT_ADDR_0_SHORT_ADDR_04 = 0x10 // MAC Short Address
SHORT_ADDR_0_SHORT_ADDR_03 = 0x8 // MAC Short Address
SHORT_ADDR_0_SHORT_ADDR_02 = 0x4 // MAC Short Address
SHORT_ADDR_0_SHORT_ADDR_01 = 0x2 // MAC Short Address
SHORT_ADDR_0_SHORT_ADDR_00 = 0x1 // MAC Short Address
// SHORT_ADDR_1: Transceiver MAC Short Address Register (High Byte)
SHORT_ADDR_1_SHORT_ADDR_ = 0xff // MAC Short Address
// PAN_ID_0: Transceiver Personal Area Network ID Register (Low Byte)
PAN_ID_0_PAN_ID_07 = 0x80 // MAC Personal Area Network ID
PAN_ID_0_PAN_ID_06 = 0x40 // MAC Personal Area Network ID
PAN_ID_0_PAN_ID_05 = 0x20 // MAC Personal Area Network ID
PAN_ID_0_PAN_ID_04 = 0x10 // MAC Personal Area Network ID
PAN_ID_0_PAN_ID_03 = 0x8 // MAC Personal Area Network ID
PAN_ID_0_PAN_ID_02 = 0x4 // MAC Personal Area Network ID
PAN_ID_0_PAN_ID_01 = 0x2 // MAC Personal Area Network ID
PAN_ID_0_PAN_ID_00 = 0x1 // MAC Personal Area Network ID
// PAN_ID_1: Transceiver Personal Area Network ID Register (High Byte)
PAN_ID_1_PAN_ID_ = 0xff // MAC Personal Area Network ID
// IEEE_ADDR_0: Transceiver MAC IEEE Address Register 0
IEEE_ADDR_0_IEEE_ADDR_07 = 0x80 // MAC IEEE Address
IEEE_ADDR_0_IEEE_ADDR_06 = 0x40 // MAC IEEE Address
IEEE_ADDR_0_IEEE_ADDR_05 = 0x20 // MAC IEEE Address
IEEE_ADDR_0_IEEE_ADDR_04 = 0x10 // MAC IEEE Address
IEEE_ADDR_0_IEEE_ADDR_03 = 0x8 // MAC IEEE Address
IEEE_ADDR_0_IEEE_ADDR_02 = 0x4 // MAC IEEE Address
IEEE_ADDR_0_IEEE_ADDR_01 = 0x2 // MAC IEEE Address
IEEE_ADDR_0_IEEE_ADDR_00 = 0x1 // MAC IEEE Address
// IEEE_ADDR_1: Transceiver MAC IEEE Address Register 1
IEEE_ADDR_1_IEEE_ADDR_ = 0xff // MAC IEEE Address
// IEEE_ADDR_2: Transceiver MAC IEEE Address Register 2
IEEE_ADDR_2_IEEE_ADDR_ = 0xff // MAC IEEE Address
// IEEE_ADDR_3: Transceiver MAC IEEE Address Register 3
IEEE_ADDR_3_IEEE_ADDR_ = 0xff // MAC IEEE Address
// IEEE_ADDR_4: Transceiver MAC IEEE Address Register 4
IEEE_ADDR_4_IEEE_ADDR_ = 0xff // MAC IEEE Address
// IEEE_ADDR_5: Transceiver MAC IEEE Address Register 5
IEEE_ADDR_5_IEEE_ADDR_ = 0xff // MAC IEEE Address
// IEEE_ADDR_6: Transceiver MAC IEEE Address Register 6
IEEE_ADDR_6_IEEE_ADDR_ = 0xff // MAC IEEE Address
// IEEE_ADDR_7: Transceiver MAC IEEE Address Register 7
IEEE_ADDR_7_IEEE_ADDR_ = 0xff // MAC IEEE Address
// XAH_CTRL_0: Transceiver Extended Operating Mode Control Register
XAH_CTRL_0_MAX_FRAME_RETRIES = 0xf0 // Maximum Number of Frame Re-transmission Attempts
XAH_CTRL_0_MAX_CSMA_RETRIES = 0xe // Maximum Number of CSMA-CA Procedure Repetition Attempts
XAH_CTRL_0_SLOTTED_OPERATION = 0x1 // Set Slotted Acknowledgment
// CSMA_SEED_0: Transceiver CSMA-CA Random Number Generator Seed Register
CSMA_SEED_0_CSMA_SEED_07 = 0x80 // Seed Value for CSMA Random Number Generator
CSMA_SEED_0_CSMA_SEED_06 = 0x40 // Seed Value for CSMA Random Number Generator
CSMA_SEED_0_CSMA_SEED_05 = 0x20 // Seed Value for CSMA Random Number Generator
CSMA_SEED_0_CSMA_SEED_04 = 0x10 // Seed Value for CSMA Random Number Generator
CSMA_SEED_0_CSMA_SEED_03 = 0x8 // Seed Value for CSMA Random Number Generator
CSMA_SEED_0_CSMA_SEED_02 = 0x4 // Seed Value for CSMA Random Number Generator
CSMA_SEED_0_CSMA_SEED_01 = 0x2 // Seed Value for CSMA Random Number Generator
CSMA_SEED_0_CSMA_SEED_00 = 0x1 // Seed Value for CSMA Random Number Generator
// CSMA_SEED_1: Transceiver Acknowledgment Frame Control Register 2
CSMA_SEED_1_AACK_FVN_MODE = 0xc0 // Acknowledgment Frame Filter Mode
CSMA_SEED_1_AACK_SET_PD = 0x20 // Set Frame Pending Sub-field
CSMA_SEED_1_AACK_DIS_ACK = 0x10 // Disable Acknowledgment Frame Transmission
CSMA_SEED_1_AACK_I_AM_COORD = 0x8 // Set Personal Area Network Coordinator
CSMA_SEED_1_CSMA_SEED_1 = 0x7 // Seed Value for CSMA Random Number Generator
// CSMA_BE: Transceiver CSMA-CA Back-off Exponent Control Register
CSMA_BE_MAX_BE = 0xf0 // Maximum Back-off Exponent
CSMA_BE_MIN_BE = 0xf // Minimum Back-off Exponent
// TST_CTRL_DIGI: Transceiver Digital Test Control Register
TST_CTRL_DIGI_TST_CTRL_DIG = 0xf // Digital Test Controller Register
// TST_RX_LENGTH: Transceiver Received Frame Length Register
TST_RX_LENGTH_RX_LENGTH = 0xff // Received Frame Length
)
// Bitfields for SYMCNT: MAC Symbol Counter
const (
// SCTSTRHH: Symbol Counter Transmit Frame Timestamp Register HH-Byte
SCTSTRHH_SCTSTRHH = 0xff // Symbol Counter Transmit Frame Timestamp Register HH-Byte
// SCTSTRHL: Symbol Counter Transmit Frame Timestamp Register HL-Byte
SCTSTRHL_SCTSTRHL = 0xff // Symbol Counter Transmit Frame Timestamp Register HL-Byte
// SCTSTRLH: Symbol Counter Transmit Frame Timestamp Register LH-Byte
SCTSTRLH_SCTSTRLH = 0xff // Symbol Counter Transmit Frame Timestamp Register LH-Byte
// SCTSTRLL: Symbol Counter Transmit Frame Timestamp Register LL-Byte
SCTSTRLL_SCTSTRLL = 0xff // Symbol Counter Transmit Frame Timestamp Register LL-Byte
// SCOCR1HH: Symbol Counter Output Compare Register 1 HH-Byte
SCOCR1HH_SCOCR1HH = 0xff // Symbol Counter Output Compare Register 1 HH-Byte
// SCOCR1HL: Symbol Counter Output Compare Register 1 HL-Byte
SCOCR1HL_SCOCR1HL = 0xff // Symbol Counter Output Compare Register 1 HL-Byte
// SCOCR1LH: Symbol Counter Output Compare Register 1 LH-Byte
SCOCR1LH_SCOCR1LH = 0xff // Symbol Counter Output Compare Register 1 LH-Byte
// SCOCR1LL: Symbol Counter Output Compare Register 1 LL-Byte
SCOCR1LL_SCOCR1LL = 0xff // Symbol Counter Output Compare Register 1 LL-Byte
// SCOCR2HH: Symbol Counter Output Compare Register 2 HH-Byte
SCOCR2HH_SCOCR2HH = 0xff // Symbol Counter Output Compare Register 2 HH-Byte
// SCOCR2HL: Symbol Counter Output Compare Register 2 HL-Byte
SCOCR2HL_SCOCR2HL = 0xff // Symbol Counter Output Compare Register 2 HL-Byte
// SCOCR2LH: Symbol Counter Output Compare Register 2 LH-Byte
SCOCR2LH_SCOCR2LH = 0xff // Symbol Counter Output Compare Register 2 LH-Byte
// SCOCR2LL: Symbol Counter Output Compare Register 2 LL-Byte
SCOCR2LL_SCOCR2LL = 0xff // Symbol Counter Output Compare Register 2 LL-Byte
// SCOCR3HH: Symbol Counter Output Compare Register 3 HH-Byte
SCOCR3HH_SCOCR3HH = 0xff // Symbol Counter Output Compare Register 3 HH-Byte
// SCOCR3HL: Symbol Counter Output Compare Register 3 HL-Byte
SCOCR3HL_SCOCR3HL = 0xff // Symbol Counter Output Compare Register 3 HL-Byte
// SCOCR3LH: Symbol Counter Output Compare Register 3 LH-Byte
SCOCR3LH_SCOCR3LH = 0xff // Symbol Counter Output Compare Register 3 LH-Byte
// SCOCR3LL: Symbol Counter Output Compare Register 3 LL-Byte
SCOCR3LL_SCOCR3LL = 0xff // Symbol Counter Output Compare Register 3 LL-Byte
// SCTSRHH: Symbol Counter Frame Timestamp Register HH-Byte
SCTSRHH_SCTSRHH = 0xff // Symbol Counter Frame Timestamp Register HH-Byte
// SCTSRHL: Symbol Counter Frame Timestamp Register HL-Byte
SCTSRHL_SCTSRHL = 0xff // Symbol Counter Frame Timestamp Register HL-Byte
// SCTSRLH: Symbol Counter Frame Timestamp Register LH-Byte
SCTSRLH_SCTSRLH = 0xff // Symbol Counter Frame Timestamp Register LH-Byte
// SCTSRLL: Symbol Counter Frame Timestamp Register LL-Byte
SCTSRLL_SCTSRLL = 0xff // Symbol Counter Frame Timestamp Register LL-Byte
// SCBTSRHH: Symbol Counter Beacon Timestamp Register HH-Byte
SCBTSRHH_SCBTSRHH = 0xff // Symbol Counter Beacon Timestamp Register HH-Byte
// SCBTSRHL: Symbol Counter Beacon Timestamp Register HL-Byte
SCBTSRHL_SCBTSRHL = 0xff // Symbol Counter Beacon Timestamp Register HL-Byte
// SCBTSRLH: Symbol Counter Beacon Timestamp Register LH-Byte
SCBTSRLH_SCBTSRLH = 0xff // Symbol Counter Beacon Timestamp Register LH-Byte
// SCBTSRLL: Symbol Counter Beacon Timestamp Register LL-Byte
SCBTSRLL_SCBTSRLL = 0xff // Symbol Counter Beacon Timestamp Register LL-Byte
// SCCNTHH: Symbol Counter Register HH-Byte
SCCNTHH_SCCNTHH = 0xff // Symbol Counter Register HH-Byte
// SCCNTHL: Symbol Counter Register HL-Byte
SCCNTHL_SCCNTHL = 0xff // Symbol Counter Register HL-Byte
// SCCNTLH: Symbol Counter Register LH-Byte
SCCNTLH_SCCNTLH = 0xff // Symbol Counter Register LH-Byte
// SCCNTLL: Symbol Counter Register LL-Byte
SCCNTLL_SCCNTLL = 0xff // Symbol Counter Register LL-Byte
// SCIRQS: Symbol Counter Interrupt Status Register
SCIRQS_IRQSBO = 0x10 // Backoff Slot Counter IRQ
SCIRQS_IRQSOF = 0x8 // Symbol Counter Overflow IRQ
SCIRQS_IRQSCP = 0x7 // Compare Unit 3 Compare Match IRQ
// SCIRQM: Symbol Counter Interrupt Mask Register
SCIRQM_Res = 0xe0 // Reserved Bit
SCIRQM_IRQMBO = 0x10 // Backoff Slot Counter IRQ enable
SCIRQM_IRQMOF = 0x8 // Symbol Counter Overflow IRQ enable
SCIRQM_IRQMCP = 0x7 // Symbol Counter Compare Match 3 IRQ enable
// SCSR: Symbol Counter Status Register
SCSR_Res = 0xfe // Reserved Bit
SCSR_SCBSY = 0x1 // Symbol Counter busy
// SCCR1: Symbol Counter Control Register 1
SCCR1_Res = 0xc0 // Reserved Bit
SCCR1_SCBTSM = 0x20 // Symbol Counter Beacon Timestamp Mask Register
SCCR1_SCCKDIV = 0x1c // Clock divider for synchronous clock source (16MHz Transceiver Clock)
SCCR1_SCEECLK = 0x2 // Enable External Clock Source on PG2
SCCR1_SCENBO = 0x1 // Backoff Slot Counter enable
// SCCR0: Symbol Counter Control Register 0
SCCR0_SCRES = 0x80 // Symbol Counter Synchronization
SCCR0_SCMBTS = 0x40 // Manual Beacon Timestamp
SCCR0_SCEN = 0x20 // Symbol Counter enable
SCCR0_SCCKSEL = 0x10 // Symbol Counter Clock Source select
SCCR0_SCTSE = 0x8 // Symbol Counter Automatic Timestamping enable
SCCR0_SCCMP = 0x7 // Symbol Counter Compare Unit 3 Mode select
// SCCSR: Symbol Counter Compare Source Register
SCCSR_Res = 0xc0 // Reserved Bit
SCCSR_SCCS3 = 0x30 // Symbol Counter Compare Source select register for Compare Unit 3
SCCSR_SCCS2 = 0xc // Symbol Counter Compare Source select register for Compare Unit 2
SCCSR_SCCS1 = 0x3 // Symbol Counter Compare Source select register for Compare Units
// SCRSTRHH: Symbol Counter Received Frame Timestamp Register HH-Byte
SCRSTRHH_SCRSTRHH = 0xff // Symbol Counter Received Frame Timestamp Register HH-Byte
// SCRSTRHL: Symbol Counter Received Frame Timestamp Register HL-Byte
SCRSTRHL_SCRSTRHL = 0xff // Symbol Counter Received Frame Timestamp Register HL-Byte
// SCRSTRLH: Symbol Counter Received Frame Timestamp Register LH-Byte
SCRSTRLH_SCRSTRLH = 0xff // Symbol Counter Received Frame Timestamp Register LH-Byte
// SCRSTRLL: Symbol Counter Received Frame Timestamp Register LL-Byte
SCRSTRLL_SCRSTRLL = 0xff // Symbol Counter Received Frame Timestamp Register LL-Byte
)
// Bitfields for EEPROM: EEPROM
const (
// EECR: EEPROM Control Register
EECR_EEPM = 0x30 // EEPROM Programming Mode
EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable
EECR_EEMPE = 0x4 // EEPROM Master Write Enable
EECR_EEPE = 0x2 // EEPROM Programming Enable
EECR_EERE = 0x1 // EEPROM Read Enable
)
// Bitfields for JTAG: JTAG Interface
const (
// OCDR: On-Chip Debug Register
OCDR_OCDR = 0xff // On-Chip Debug Register Data
)
// Bitfields for EXINT: External Interrupts
const (
// EICRA: External Interrupt Control Register A
EICRA_ISC3 = 0xc0 // External Interrupt 3 Sense Control Bit
EICRA_ISC2 = 0x30 // External Interrupt 2 Sense Control Bit
EICRA_ISC1 = 0xc // External Interrupt 1 Sense Control Bit
EICRA_ISC0 = 0x3 // External Interrupt 0 Sense Control Bit
// EICRB: External Interrupt Control Register B
EICRB_ISC7 = 0xc0 // External Interrupt 7 Sense Control Bit
EICRB_ISC6 = 0x30 // External Interrupt 6 Sense Control Bit
EICRB_ISC5 = 0xc // External Interrupt 5 Sense Control Bit
EICRB_ISC4 = 0x3 // External Interrupt 4 Sense Control Bit
// EIMSK: External Interrupt Mask Register
EIMSK_INT = 0xff // External Interrupt Request Enable
// EIFR: External Interrupt Flag Register
EIFR_INTF = 0xff // External Interrupt Flag
// PCMSK2: Pin Change Mask Register 2
PCMSK2_PCINT = 0xff // Pin Change Enable Mask
// PCMSK1: Pin Change Mask Register 1
PCMSK1_PCINT = 0xff // Pin Change Enable Mask
// PCMSK0: Pin Change Mask Register 0
PCMSK0_PCINT = 0xff // Pin Change Enable Mask
// PCIFR: Pin Change Interrupt Flag Register
PCIFR_Res = 0xf8 // Reserved Bit
PCIFR_PCIF = 0x7 // Pin Change Interrupt Flags
// PCICR: Pin Change Interrupt Control Register
PCICR_Res = 0xf8 // Reserved Bit
PCICR_PCIE = 0x7 // Pin Change Interrupt Enables
)
// Bitfields for ADC: Analog-to-Digital Converter
const (
// ADMUX: The ADC Multiplexer Selection Register
ADMUX_REFS = 0xc0 // Reference Selection Bits
ADMUX_ADLAR = 0x20 // ADC Left Adjust Result
ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits
// ADCSRA: The ADC Control and Status Register A
ADCSRA_ADEN = 0x80 // ADC Enable
ADCSRA_ADSC = 0x40 // ADC Start Conversion
ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable
ADCSRA_ADIF = 0x10 // ADC Interrupt Flag
ADCSRA_ADIE = 0x8 // ADC Interrupt Enable
ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits
// ADCSRC: The ADC Control and Status Register C
ADCSRC_ADTHT = 0xc0 // ADC Track-and-Hold Time
ADCSRC_Res0 = 0x20 // Reserved
ADCSRC_ADSUT = 0x1f // ADC Start-up Time
// DIDR2: Digital Input Disable Register 2
DIDR2_ADC15D = 0x80 // Reserved Bits
DIDR2_ADC14D = 0x40 // Reserved Bits
DIDR2_ADC13D = 0x20 // Reserved Bits
DIDR2_ADC12D = 0x10 // Reserved Bits
DIDR2_ADC11D = 0x8 // Reserved Bits
DIDR2_ADC10D = 0x4 // Reserved Bits
DIDR2_ADC9D = 0x2 // Reserved Bits
DIDR2_ADC8D = 0x1 // Reserved Bits
// DIDR0: Digital Input Disable Register 0
DIDR0_ADC7D = 0x80 // Disable ADC7:0 Digital Input
DIDR0_ADC6D = 0x40 // Disable ADC7:0 Digital Input
DIDR0_ADC5D = 0x20 // Disable ADC7:0 Digital Input
DIDR0_ADC4D = 0x10 // Disable ADC7:0 Digital Input
DIDR0_ADC3D = 0x8 // Disable ADC7:0 Digital Input
DIDR0_ADC2D = 0x4 // Disable ADC7:0 Digital Input
DIDR0_ADC1D = 0x2 // Disable ADC7:0 Digital Input
DIDR0_ADC0D = 0x1 // Disable ADC7:0 Digital Input
)
// Bitfields for BOOT_LOAD: Bootloader
const (
// SPMCSR: Store Program Memory Control Register
SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable
SPMCSR_RWWSB = 0x40 // Read While Write Section Busy
SPMCSR_SIGRD = 0x20 // Signature Row Read
SPMCSR_RWWSRE = 0x10 // Read While Write Section Read Enable
SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set
SPMCSR_PGWRT = 0x4 // Page Write
SPMCSR_PGERS = 0x2 // Page Erase
SPMCSR_SPMEN = 0x1 // Store Program Memory Enable
)
// Bitfields for CPU: CPU Registers
const (
// SREG: Status Register
SREG_I = 0x80 // Global Interrupt Enable
SREG_T = 0x40 // Bit Copy Storage
SREG_H = 0x20 // Half Carry Flag
SREG_S = 0x10 // Sign Bit
SREG_V = 0x8 // Two's Complement Overflow Flag
SREG_N = 0x4 // Negative Flag
SREG_Z = 0x2 // Zero Flag
SREG_C = 0x1 // Carry Flag
// OSCCAL: Oscillator Calibration Value
OSCCAL_CAL = 0xff // Oscillator Calibration Tuning Value
// CLKPR: Clock Prescale Register
CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable
CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits
// SMCR: Sleep Mode Control Register
SMCR_SM = 0xe // Sleep Mode Select bits
SMCR_SE = 0x1 // Sleep Enable
// GPIOR2: General Purpose I/O Register 2
GPIOR2_GPIOR = 0xff // General Purpose I/O Register 2 Value
// GPIOR1: General Purpose IO Register 1
GPIOR1_GPIOR = 0xff // General Purpose I/O Register 1 Value
// GPIOR0: General Purpose IO Register 0
GPIOR0_GPIOR07 = 0x80 // General Purpose I/O Register 0 Value
GPIOR0_GPIOR06 = 0x40 // General Purpose I/O Register 0 Value
GPIOR0_GPIOR05 = 0x20 // General Purpose I/O Register 0 Value
GPIOR0_GPIOR04 = 0x10 // General Purpose I/O Register 0 Value
GPIOR0_GPIOR03 = 0x8 // General Purpose I/O Register 0 Value
GPIOR0_GPIOR02 = 0x4 // General Purpose I/O Register 0 Value
GPIOR0_GPIOR01 = 0x2 // General Purpose I/O Register 0 Value
GPIOR0_GPIOR00 = 0x1 // General Purpose I/O Register 0 Value
// PRR2: Power Reduction Register 2
PRR2_PRRAM3 = 0x8 // Power Reduction SRAM3
PRR2_PRRAM2 = 0x4 // Power Reduction SRAM2
PRR2_PRRAM1 = 0x2 // Power Reduction SRAM1
PRR2_PRRAM0 = 0x1 // Power Reduction SRAM0
// PRR1: Power Reduction Register 1
PRR1_Res = 0x80 // Reserved Bit
PRR1_PRTRX24 = 0x40 // Power Reduction Transceiver
PRR1_PRTIM5 = 0x20 // Power Reduction Timer/Counter5
PRR1_PRTIM4 = 0x10 // Power Reduction Timer/Counter4
PRR1_PRTIM3 = 0x8 // Power Reduction Timer/Counter3
PRR1_PRUSART1 = 0x1 // Power Reduction USART1
// PRR0: Power Reduction Register0
PRR0_PRTWI = 0x80 // Power Reduction TWI
PRR0_PRTIM2 = 0x40 // Power Reduction Timer/Counter2
PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0
PRR0_PRPGA = 0x10 // Power Reduction PGA
PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1
PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface
PRR0_PRUSART0 = 0x2 // Power Reduction USART
PRR0_PRADC = 0x1 // Power Reduction ADC
)
// Bitfields for FLASH: FLASH Controller
const (
// NEMCR: Flash Extended-Mode Control-Register
NEMCR_ENEAM = 0x40 // Enable Extended Address Mode for Extra Rows
NEMCR_AEAM = 0x30 // Address for Extended Address Mode of Extra Rows
// BGCR: Reference Voltage Calibration Register
BGCR_Res = 0x80 // Reserved Bit
BGCR_BGCAL_FINE = 0x78 // Fine Calibration Bits
BGCR_BGCAL = 0x7 // Coarse Calibration Bits
)
// Bitfields for PWRCTRL: Power Controller
const (
// TRXPR: Transceiver Pin Register
TRXPR_SLPTR = 0x2 // Multi-purpose Transceiver Control Bit
TRXPR_TRXRST = 0x1 // Force Transceiver Reset
// DRTRAM0: Data Retention Configuration Register #0
DRTRAM0_DRTSWOK = 0x20 // DRT Switch OK
DRTRAM0_ENDRT = 0x10 // Enable SRAM Data Retention
// DRTRAM1: Data Retention Configuration Register #1
DRTRAM1_DRTSWOK = 0x20 // DRT Switch OK
DRTRAM1_ENDRT = 0x10 // Enable SRAM Data Retention
// DRTRAM2: Data Retention Configuration Register #2
DRTRAM2_Res = 0x40 // Reserved Bit
DRTRAM2_DRTSWOK = 0x20 // DRT Switch OK
DRTRAM2_ENDRT = 0x10 // Enable SRAM Data Retention
// DRTRAM3: Data Retention Configuration Register #3
DRTRAM3_DRTSWOK = 0x20 // DRT Switch OK
DRTRAM3_ENDRT = 0x10 // Enable SRAM Data Retention
// LLDRL: Low Leakage Voltage Regulator Data Register (Low-Byte)
LLDRL_LLDRL = 0xf // Low-Byte Data Register Bits
// LLDRH: Low Leakage Voltage Regulator Data Register (High-Byte)
LLDRH_LLDRH = 0x1f // High-Byte Data Register Bits
// LLCR: Low Leakage Voltage Regulator Control Register
LLCR_Res = 0xc0 // Reserved Bit
LLCR_LLDONE = 0x20 // Calibration Done
LLCR_LLCOMP = 0x10 // Comparator Output
LLCR_LLCAL = 0x8 // Calibration Active
LLCR_LLTCO = 0x4 // Temperature Coefficient of Current Source
LLCR_LLSHORT = 0x2 // Short Lower Calibration Circuit
LLCR_LLENCAL = 0x1 // Enable Automatic Calibration
// DPDS0: Port Driver Strength Register 0
DPDS0_PFDRV = 0xc0 // Driver Strength Port F
DPDS0_PEDRV = 0x30 // Driver Strength Port E
DPDS0_PDDRV = 0xc // Driver Strength Port D
DPDS0_PBDRV = 0x3 // Driver Strength Port B
// DPDS1: Port Driver Strength Register 1
DPDS1_PGDRV = 0x3 // Driver Strength Port G
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