260 строки
9,1 КиБ
Go
260 строки
9,1 КиБ
Go
//go:build stm32l0x2
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// +build stm32l0x2
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package machine
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// Peripheral abstraction layer for the stm32l0
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import (
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"device/stm32"
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"runtime/interrupt"
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"runtime/volatile"
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"unsafe"
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)
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const (
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AF0_SYSTEM_SPI1_2_I2S2_USART1_2_LPUART1_USB_LPTIM1_TSC_TIM2_21_22 = 0
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AF1_SPI1_2_I2S2_I2C1_TIM2_21 = 1
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AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3 = 2
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AF3_I2C1_TSC = 3
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AF4_I2C1_USART1_2_LPUART1_TIM3_22 = 4
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AF5_SPI2_I2S2_I2C2_USART1_TIM2_21_22 = 5
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AF6_I2C1_2_LPUART1_USART4_5_TIM21 = 6
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AF7_I2C3_LPUART1_COMP1_2_TIM3 = 7
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)
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// Enable peripheral clock
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func enableAltFuncClock(bus unsafe.Pointer) {
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switch bus {
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case unsafe.Pointer(stm32.DAC): // DAC interface clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_DACEN)
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case unsafe.Pointer(stm32.PWR): // Power interface clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_PWREN)
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case unsafe.Pointer(stm32.I2C3): // I2C3 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_I2C3EN)
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case unsafe.Pointer(stm32.I2C2): // I2C2 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_I2C2EN)
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case unsafe.Pointer(stm32.I2C1): // I2C1 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_I2C1EN)
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case unsafe.Pointer(stm32.USART5): // UART5 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_USART5EN)
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case unsafe.Pointer(stm32.USART4): // UART4 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_USART4EN)
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case unsafe.Pointer(stm32.USART2): // USART2 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_USART2EN)
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case unsafe.Pointer(stm32.SPI2): // SPI2 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_SPI2EN)
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case unsafe.Pointer(stm32.LPUART1): // LPUART1 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_LPUART1EN)
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case unsafe.Pointer(stm32.WWDG): // Window watchdog clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_WWDGEN)
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case unsafe.Pointer(stm32.TIM7): // TIM7 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM7EN)
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case unsafe.Pointer(stm32.TIM6): // TIM6 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM6EN)
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case unsafe.Pointer(stm32.TIM3): // TIM3 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM3EN)
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case unsafe.Pointer(stm32.TIM2): // TIM2 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM2EN)
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case unsafe.Pointer(stm32.SYSCFG): // System configuration controller clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SYSCFGEN)
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case unsafe.Pointer(stm32.SPI1): // SPI1 clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SPI1EN)
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case unsafe.Pointer(stm32.ADC): // ADC clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_ADCEN)
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case unsafe.Pointer(stm32.USART1): // USART1 clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_USART1EN)
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}
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}
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//---------- Timer related code
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var (
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TIM2 = TIM{
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EnableRegister: &stm32.RCC.APB1ENR,
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EnableFlag: stm32.RCC_APB1ENR_TIM2EN,
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Device: stm32.TIM2,
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Channels: [4]TimerChannel{
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TimerChannel{Pins: []PinFunction{
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{PA0, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3},
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{PA5, AF5_SPI2_I2S2_I2C2_USART1_TIM2_21_22},
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{PA15, AF5_SPI2_I2S2_I2C2_USART1_TIM2_21_22},
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{PE9, AF0_SYSTEM_SPI1_2_I2S2_USART1_2_LPUART1_USB_LPTIM1_TSC_TIM2_21_22},
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}},
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TimerChannel{Pins: []PinFunction{
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{PA1, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3},
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{PB3, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3},
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{PE10, AF0_SYSTEM_SPI1_2_I2S2_USART1_2_LPUART1_USB_LPTIM1_TSC_TIM2_21_22},
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}},
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TimerChannel{Pins: []PinFunction{
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{PA2, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3},
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{PB10, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3},
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{PE11, AF0_SYSTEM_SPI1_2_I2S2_USART1_2_LPUART1_USB_LPTIM1_TSC_TIM2_21_22},
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}},
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TimerChannel{Pins: []PinFunction{
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{PA3, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3},
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{PB11, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3},
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{PE12, AF0_SYSTEM_SPI1_2_I2S2_USART1_2_LPUART1_USB_LPTIM1_TSC_TIM2_21_22},
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}},
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},
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busFreq: APB1_TIM_FREQ,
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}
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TIM3 = TIM{
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EnableRegister: &stm32.RCC.APB1ENR,
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EnableFlag: stm32.RCC_APB1ENR_TIM3EN,
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Device: stm32.TIM3,
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Channels: [4]TimerChannel{
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TimerChannel{Pins: []PinFunction{
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{PA6, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3},
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{PB4, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3},
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{PC6, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3},
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{PE3, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3},
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}},
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TimerChannel{Pins: []PinFunction{
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{PA7, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3},
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{PB5, AF4_I2C1_USART1_2_LPUART1_TIM3_22},
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{PC7, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3},
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{PE4, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3},
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}},
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TimerChannel{Pins: []PinFunction{
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{PB0, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3},
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{PC8, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3},
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{PE5, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3},
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}},
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TimerChannel{Pins: []PinFunction{
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{PB1, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3},
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{PC9, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3},
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{PE6, AF2_SPI1_2_I2S2_LPUART1_USART5_USB_LPTIM1_TIM2_3},
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}},
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},
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busFreq: APB1_TIM_FREQ,
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}
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TIM6 = TIM{
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EnableRegister: &stm32.RCC.APB1ENR,
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EnableFlag: stm32.RCC_APB1ENR_TIM6EN,
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Device: stm32.TIM6,
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Channels: [4]TimerChannel{
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TimerChannel{Pins: []PinFunction{}},
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TimerChannel{Pins: []PinFunction{}},
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TimerChannel{Pins: []PinFunction{}},
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TimerChannel{Pins: []PinFunction{}},
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},
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busFreq: APB1_TIM_FREQ,
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}
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TIM7 = TIM{
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EnableRegister: &stm32.RCC.APB1ENR,
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EnableFlag: stm32.RCC_APB1ENR_TIM7EN,
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Device: stm32.TIM7,
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Channels: [4]TimerChannel{
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TimerChannel{Pins: []PinFunction{}},
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TimerChannel{Pins: []PinFunction{}},
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TimerChannel{Pins: []PinFunction{}},
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TimerChannel{Pins: []PinFunction{}},
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},
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busFreq: APB1_TIM_FREQ,
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}
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TIM21 = TIM{
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EnableRegister: &stm32.RCC.APB2ENR,
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EnableFlag: stm32.RCC_APB2ENR_TIM21EN,
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Device: stm32.TIM21,
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Channels: [4]TimerChannel{
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TimerChannel{Pins: []PinFunction{
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{PA2, AF0_SYSTEM_SPI1_2_I2S2_USART1_2_LPUART1_USB_LPTIM1_TSC_TIM2_21_22},
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{PB13, AF6_I2C1_2_LPUART1_USART4_5_TIM21},
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{PD0, AF0_SYSTEM_SPI1_2_I2S2_USART1_2_LPUART1_USB_LPTIM1_TSC_TIM2_21_22},
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{PE5, AF0_SYSTEM_SPI1_2_I2S2_USART1_2_LPUART1_USB_LPTIM1_TSC_TIM2_21_22},
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}},
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TimerChannel{Pins: []PinFunction{
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{PA3, AF0_SYSTEM_SPI1_2_I2S2_USART1_2_LPUART1_USB_LPTIM1_TSC_TIM2_21_22},
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{PB14, AF6_I2C1_2_LPUART1_USART4_5_TIM21},
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{PD7, AF1_SPI1_2_I2S2_I2C1_TIM2_21},
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{PE6, AF0_SYSTEM_SPI1_2_I2S2_USART1_2_LPUART1_USB_LPTIM1_TSC_TIM2_21_22},
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}},
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TimerChannel{Pins: []PinFunction{}},
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TimerChannel{Pins: []PinFunction{}},
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},
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busFreq: APB2_TIM_FREQ,
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}
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TIM22 = TIM{
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EnableRegister: &stm32.RCC.APB2ENR,
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EnableFlag: stm32.RCC_APB2ENR_TIM22EN,
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Device: stm32.TIM2,
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Channels: [4]TimerChannel{
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TimerChannel{Pins: []PinFunction{
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{PA6, AF5_SPI2_I2S2_I2C2_USART1_TIM2_21_22},
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{PB4, AF4_I2C1_USART1_2_LPUART1_TIM3_22},
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{PC6, AF0_SYSTEM_SPI1_2_I2S2_USART1_2_LPUART1_USB_LPTIM1_TSC_TIM2_21_22},
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{PE3, AF0_SYSTEM_SPI1_2_I2S2_USART1_2_LPUART1_USB_LPTIM1_TSC_TIM2_21_22},
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}},
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TimerChannel{Pins: []PinFunction{
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{PA7, AF5_SPI2_I2S2_I2C2_USART1_TIM2_21_22},
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{PB5, AF4_I2C1_USART1_2_LPUART1_TIM3_22},
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{PC7, AF0_SYSTEM_SPI1_2_I2S2_USART1_2_LPUART1_USB_LPTIM1_TSC_TIM2_21_22},
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{PE4, AF0_SYSTEM_SPI1_2_I2S2_USART1_2_LPUART1_USB_LPTIM1_TSC_TIM2_21_22},
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}},
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TimerChannel{Pins: []PinFunction{}},
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TimerChannel{Pins: []PinFunction{}},
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},
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busFreq: APB2_TIM_FREQ,
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}
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)
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func (t *TIM) registerUPInterrupt() interrupt.Interrupt {
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switch t {
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case &TIM2:
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return interrupt.New(stm32.IRQ_TIM2, TIM2.handleUPInterrupt)
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case &TIM3:
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return interrupt.New(stm32.IRQ_TIM3, TIM3.handleUPInterrupt)
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case &TIM6:
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return interrupt.New(stm32.IRQ_TIM6_DAC, TIM6.handleUPInterrupt)
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case &TIM7:
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return interrupt.New(stm32.IRQ_TIM7, TIM7.handleUPInterrupt)
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case &TIM21:
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return interrupt.New(stm32.IRQ_TIM21, TIM21.handleUPInterrupt)
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case &TIM22:
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return interrupt.New(stm32.IRQ_TIM22, TIM22.handleUPInterrupt)
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}
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return interrupt.Interrupt{}
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}
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func (t *TIM) registerOCInterrupt() interrupt.Interrupt {
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switch t {
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case &TIM2:
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return interrupt.New(stm32.IRQ_TIM2, TIM2.handleOCInterrupt)
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case &TIM3:
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return interrupt.New(stm32.IRQ_TIM3, TIM3.handleOCInterrupt)
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case &TIM6:
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return interrupt.New(stm32.IRQ_TIM6_DAC, TIM6.handleOCInterrupt)
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case &TIM7:
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return interrupt.New(stm32.IRQ_TIM7, TIM7.handleOCInterrupt)
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case &TIM21:
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return interrupt.New(stm32.IRQ_TIM21, TIM21.handleOCInterrupt)
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case &TIM22:
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return interrupt.New(stm32.IRQ_TIM22, TIM22.handleOCInterrupt)
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}
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return interrupt.Interrupt{}
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}
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func (t *TIM) enableMainOutput() {
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// nothing to do - no BDTR register
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}
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type arrtype = uint16
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type arrRegType = volatile.Register16
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const (
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ARR_MAX = 0x10000
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PSC_MAX = 0x10000
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)
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func initRNG() {
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stm32.RCC.AHBENR.SetBits(stm32.RCC_AHBENR_RNGEN)
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stm32.RNG.CR.SetBits(stm32.RNG_CR_RNGEN)
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}
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