avr: remove device files, use them from a subrepository
These files don't really belong in this repository. It's better to generate them automatically from a source, like the one provided by the avr-rust project. So a new command `make gen-device-avr` has been provided for this purpose.
Этот коммит содержится в:
Ayke van Laethem
родитель
7258553528
коммит
93248c93ed
260 изменённых файлов: 10 добавлений и 105301 удалений
2
.gitignore
предоставленный
2
.gitignore
предоставленный
|
|
@ -1,2 +1,4 @@
|
|||
build
|
||||
src/device/avr/*.go
|
||||
src/device/avr/*.ld
|
||||
src/device/nrf/*.go
|
||||
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|
|
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3
.gitmodules
предоставленный
3
.gitmodules
предоставленный
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@ -4,3 +4,6 @@
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[submodule "lib/CMSIS"]
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||||
path = lib/CMSIS
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||||
url = https://github.com/ARM-software/CMSIS.git
|
||||
[submodule "lib/avr"]
|
||||
path = lib/avr
|
||||
url = https://github.com/avr-rust/avr-mcu.git
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|
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4
Makefile
4
Makefile
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@ -83,6 +83,10 @@ gen-device-nrf:
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|||
./gen-device.py lib/nrfx/mdk/ src/device/nrf/
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||||
go fmt ./src/device/nrf
|
||||
|
||||
gen-device-avr:
|
||||
./gen-device.py lib/avr/packs/atmega src/device/avr/
|
||||
go fmt ./src/device/avr
|
||||
|
||||
|
||||
# Build the Go compiler.
|
||||
build/tgo: *.go
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1
lib/avr
Подмодуль
1
lib/avr
Подмодуль
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@ -0,0 +1 @@
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Subproject commit 6624554c02b237b23dc17d53e992bf54033fc228
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||||
Различия файлов не показаны, т.к. их слишком много
Показать различия
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@ -1,6 +0,0 @@
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/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from AT90CAN128.atdf, see http://packs.download.atmel.com/ */
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||||
|
||||
__flash_size = 0x20000;
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__ram_size = 0x1000;
|
||||
__num_isrs = 37;
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||||
Различия файлов не показаны, т.к. их слишком много
Показать различия
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@ -1,6 +0,0 @@
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/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from AT90CAN32.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x8000;
|
||||
__ram_size = 0x800;
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__num_isrs = 37;
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||||
Различия файлов не показаны, т.к. их слишком много
Показать различия
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@ -1,6 +0,0 @@
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/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from AT90CAN64.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x10000;
|
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__ram_size = 0x1000;
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__num_isrs = 37;
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|
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@ -1,841 +0,0 @@
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// Automatically generated file. DO NOT EDIT.
|
||||
// Generated by gen-device.py from AT90PWM1.atdf, see http://packs.download.atmel.com/
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|
||||
// +build avr,at90pwm1
|
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|
||||
// Device information for the AT90PWM1.
|
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//
|
||||
package avr
|
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|
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// Magic type name for the compiler.
|
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type __reg uint8
|
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|
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// Export this magic type name.
|
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type RegValue = __reg
|
||||
|
||||
// Some information about this device.
|
||||
const (
|
||||
DEVICE = "AT90PWM1"
|
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ARCH = "AVR8"
|
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FAMILY = "megaAVR"
|
||||
)
|
||||
|
||||
// Interrupts
|
||||
const (
|
||||
IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset
|
||||
IRQ_PSC2_CAPT = 1 // PSC2 Capture Event
|
||||
IRQ_PSC2_EC = 2 // PSC2 End Cycle
|
||||
IRQ_PSC1_CAPT = 3 // PSC1 Capture Event
|
||||
IRQ_PSC1_EC = 4 // PSC1 End Cycle
|
||||
IRQ_PSC0_CAPT = 5 // PSC0 Capture Event
|
||||
IRQ_PSC0_EC = 6 // PSC0 End Cycle
|
||||
IRQ_ANALOG_COMP_0 = 7 // Analog Comparator 0
|
||||
IRQ_ANALOG_COMP_1 = 8 // Analog Comparator 1
|
||||
IRQ_ANALOG_COMP_2 = 9 // Analog Comparator 2
|
||||
IRQ_INT0 = 10 // External Interrupt Request 0
|
||||
IRQ_TIMER1_CAPT = 11 // Timer/Counter1 Capture Event
|
||||
IRQ_TIMER1_COMPA = 12 // Timer/Counter1 Compare Match A
|
||||
IRQ_TIMER1_COMPB = 13 // Timer/Counter Compare Match B
|
||||
IRQ_RESERVED15 = 14 //
|
||||
IRQ_TIMER1_OVF = 15 // Timer/Counter1 Overflow
|
||||
IRQ_TIMER0_COMP_A = 16 // Timer/Counter0 Compare Match A
|
||||
IRQ_TIMER0_OVF = 17 // Timer/Counter0 Overflow
|
||||
IRQ_ADC = 18 // ADC Conversion Complete
|
||||
IRQ_INT1 = 19 // External Interrupt Request 1
|
||||
IRQ_SPI_STC = 20 // SPI Serial Transfer Complete
|
||||
IRQ_USART_RX = 21 // USART, Rx Complete
|
||||
IRQ_USART_UDRE = 22 // USART Data Register Empty
|
||||
IRQ_USART_TX = 23 // USART, Tx Complete
|
||||
IRQ_INT2 = 24 // External Interrupt Request 2
|
||||
IRQ_WDT = 25 // Watchdog Timeout Interrupt
|
||||
IRQ_EE_READY = 26 // EEPROM Ready
|
||||
IRQ_TIMER0_COMPB = 27 // Timer Counter 0 Compare Match B
|
||||
IRQ_INT3 = 28 // External Interrupt Request 3
|
||||
IRQ_RESERVED30 = 29 //
|
||||
IRQ_RESERVED31 = 30 //
|
||||
IRQ_SPM_READY = 31 // Store Program Memory Read
|
||||
IRQ_max = 31 // Highest interrupt number on this device.
|
||||
)
|
||||
|
||||
// Peripherals
|
||||
var (
|
||||
// Fuses
|
||||
FUSE = struct {
|
||||
EXTENDED __reg
|
||||
HIGH __reg
|
||||
LOW __reg
|
||||
}{
|
||||
EXTENDED: 0x2,
|
||||
HIGH: 0x1,
|
||||
LOW: 0x0,
|
||||
}
|
||||
|
||||
// Lockbits
|
||||
LOCKBIT = struct {
|
||||
LOCKBIT __reg
|
||||
}{
|
||||
LOCKBIT: 0x0,
|
||||
}
|
||||
|
||||
// I/O Port
|
||||
PORT = struct {
|
||||
PORTB __reg
|
||||
DDRB __reg
|
||||
PINB __reg
|
||||
PORTD __reg
|
||||
DDRD __reg
|
||||
PIND __reg
|
||||
PORTE __reg
|
||||
DDRE __reg
|
||||
PINE __reg
|
||||
}{
|
||||
PORTB: 0x25, // Port B Data Register
|
||||
DDRB: 0x24, // Port B Data Direction Register
|
||||
PINB: 0x23, // Port B Input Pins
|
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PORTD: 0x2b, // Port D Data Register
|
||||
DDRD: 0x2a, // Port D Data Direction Register
|
||||
PIND: 0x29, // Port D Input Pins
|
||||
PORTE: 0x2e, // Port E Data Register
|
||||
DDRE: 0x2d, // Port E Data Direction Register
|
||||
PINE: 0x2c, // Port E Input Pins
|
||||
}
|
||||
|
||||
// Bootloader
|
||||
BOOT_LOAD = struct {
|
||||
SPMCSR __reg
|
||||
}{
|
||||
SPMCSR: 0x57, // Store Program Memory Control Register
|
||||
}
|
||||
|
||||
// Power Stage Controller
|
||||
PSC = struct {
|
||||
PICR0L __reg
|
||||
PICR0H __reg
|
||||
PFRC0B __reg
|
||||
PFRC0A __reg
|
||||
PCTL0 __reg
|
||||
PCNF0 __reg
|
||||
OCR0RBL __reg
|
||||
OCR0RBH __reg
|
||||
OCR0SBL __reg
|
||||
OCR0SBH __reg
|
||||
OCR0RAL __reg
|
||||
OCR0RAH __reg
|
||||
OCR0SAL __reg
|
||||
OCR0SAH __reg
|
||||
PSOC0 __reg
|
||||
PIM0 __reg
|
||||
PIFR0 __reg
|
||||
PICR2L __reg
|
||||
PICR2H __reg
|
||||
PFRC2B __reg
|
||||
PFRC2A __reg
|
||||
PCTL2 __reg
|
||||
PCNF2 __reg
|
||||
OCR2RBL __reg
|
||||
OCR2RBH __reg
|
||||
OCR2SBL __reg
|
||||
OCR2SBH __reg
|
||||
OCR2RAL __reg
|
||||
OCR2RAH __reg
|
||||
OCR2SAL __reg
|
||||
OCR2SAH __reg
|
||||
POM2 __reg
|
||||
PSOC2 __reg
|
||||
PIM2 __reg
|
||||
PIFR2 __reg
|
||||
PICR1L __reg
|
||||
PICR1H __reg
|
||||
PFRC1B __reg
|
||||
PFRC1A __reg
|
||||
PCTL1 __reg
|
||||
PSOC1 __reg
|
||||
}{
|
||||
PICR0L: 0xde, // PSC 0 Input Capture Register
|
||||
PICR0H: 0xde, // PSC 0 Input Capture Register
|
||||
PFRC0B: 0xdd, // PSC 0 Input B Control
|
||||
PFRC0A: 0xdc, // PSC 0 Input A Control
|
||||
PCTL0: 0xdb, // PSC 0 Control Register
|
||||
PCNF0: 0xda, // PSC 0 Configuration Register
|
||||
OCR0RBL: 0xd8, // Output Compare RB Register
|
||||
OCR0RBH: 0xd8, // Output Compare RB Register
|
||||
OCR0SBL: 0xd6, // Output Compare SB Register
|
||||
OCR0SBH: 0xd6, // Output Compare SB Register
|
||||
OCR0RAL: 0xd4, // Output Compare RA Register
|
||||
OCR0RAH: 0xd4, // Output Compare RA Register
|
||||
OCR0SAL: 0xd2, // Output Compare SA Register
|
||||
OCR0SAH: 0xd2, // Output Compare SA Register
|
||||
PSOC0: 0xd0, // PSC0 Synchro and Output Configuration
|
||||
PIM0: 0xa1, // PSC0 Interrupt Mask Register
|
||||
PIFR0: 0xa0, // PSC0 Interrupt Flag Register
|
||||
PICR2L: 0xfe, // PSC 2 Input Capture Register
|
||||
PICR2H: 0xfe, // PSC 2 Input Capture Register
|
||||
PFRC2B: 0xfd, // PSC 2 Input B Control
|
||||
PFRC2A: 0xfc, // PSC 2 Input B Control
|
||||
PCTL2: 0xfb, // PSC 2 Control Register
|
||||
PCNF2: 0xfa, // PSC 2 Configuration Register
|
||||
OCR2RBL: 0xf8, // Output Compare RB Register
|
||||
OCR2RBH: 0xf8, // Output Compare RB Register
|
||||
OCR2SBL: 0xf6, // Output Compare SB Register
|
||||
OCR2SBH: 0xf6, // Output Compare SB Register
|
||||
OCR2RAL: 0xf4, // Output Compare RA Register
|
||||
OCR2RAH: 0xf4, // Output Compare RA Register
|
||||
OCR2SAL: 0xf2, // Output Compare SA Register
|
||||
OCR2SAH: 0xf2, // Output Compare SA Register
|
||||
POM2: 0xf1, // PSC 2 Output Matrix
|
||||
PSOC2: 0xf0, // PSC2 Synchro and Output Configuration
|
||||
PIM2: 0xa5, // PSC2 Interrupt Mask Register
|
||||
PIFR2: 0xa4, // PSC2 Interrupt Flag Register
|
||||
PICR1L: 0xee, // PSC 1 Input Capture Register
|
||||
PICR1H: 0xee, // PSC 1 Input Capture Register
|
||||
PFRC1B: 0xed, // PSC 1 Input B Control
|
||||
PFRC1A: 0xec, // PSC 1 Input B Control
|
||||
PCTL1: 0xeb, // PSC 1 Control Register
|
||||
PSOC1: 0xe0, // PSC1 Synchro and Output Configuration
|
||||
}
|
||||
|
||||
// CPU Registers
|
||||
CPU = struct {
|
||||
SREG __reg
|
||||
SPL __reg
|
||||
SPH __reg
|
||||
MCUCR __reg
|
||||
MCUSR __reg
|
||||
OSCCAL __reg
|
||||
CLKPR __reg
|
||||
SMCR __reg
|
||||
GPIOR3 __reg
|
||||
GPIOR2 __reg
|
||||
GPIOR1 __reg
|
||||
GPIOR0 __reg
|
||||
PLLCSR __reg
|
||||
PRR __reg
|
||||
}{
|
||||
SREG: 0x5f, // Status Register
|
||||
SPL: 0x5d, // Stack Pointer
|
||||
SPH: 0x5d, // Stack Pointer
|
||||
MCUCR: 0x55, // MCU Control Register
|
||||
MCUSR: 0x54, // MCU Status Register
|
||||
OSCCAL: 0x66, // Oscillator Calibration Value
|
||||
CLKPR: 0x61,
|
||||
SMCR: 0x53, // Sleep Mode Control Register
|
||||
GPIOR3: 0x3b, // General Purpose IO Register 3
|
||||
GPIOR2: 0x3a, // General Purpose IO Register 2
|
||||
GPIOR1: 0x39, // General Purpose IO Register 1
|
||||
GPIOR0: 0x3e, // General Purpose IO Register 0
|
||||
PLLCSR: 0x49, // PLL Control And Status Register
|
||||
PRR: 0x64, // Power Reduction Register
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit
|
||||
TC8 = struct {
|
||||
TIMSK0 __reg
|
||||
TIFR0 __reg
|
||||
TCCR0A __reg
|
||||
TCCR0B __reg
|
||||
TCNT0 __reg
|
||||
OCR0A __reg
|
||||
OCR0B __reg
|
||||
}{
|
||||
TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register
|
||||
TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register
|
||||
TCCR0A: 0x44, // Timer/Counter Control Register A
|
||||
TCCR0B: 0x45, // Timer/Counter Control Register B
|
||||
TCNT0: 0x46, // Timer/Counter0
|
||||
OCR0A: 0x47, // Timer/Counter0 Output Compare Register
|
||||
OCR0B: 0x48, // Timer/Counter0 Output Compare Register
|
||||
}
|
||||
|
||||
// Timer/Counter, 16-bit
|
||||
TC16 = struct {
|
||||
TIMSK1 __reg
|
||||
TIFR1 __reg
|
||||
TCCR1A __reg
|
||||
TCCR1B __reg
|
||||
TCCR1C __reg
|
||||
TCNT1L __reg
|
||||
TCNT1H __reg
|
||||
OCR1AL __reg
|
||||
OCR1AH __reg
|
||||
OCR1BL __reg
|
||||
OCR1BH __reg
|
||||
ICR1L __reg
|
||||
ICR1H __reg
|
||||
}{
|
||||
TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register
|
||||
TIFR1: 0x36, // Timer/Counter Interrupt Flag register
|
||||
TCCR1A: 0x80, // Timer/Counter1 Control Register A
|
||||
TCCR1B: 0x81, // Timer/Counter1 Control Register B
|
||||
TCCR1C: 0x82, // Timer/Counter1 Control Register C
|
||||
TCNT1L: 0x84, // Timer/Counter1 Bytes
|
||||
TCNT1H: 0x84, // Timer/Counter1 Bytes
|
||||
OCR1AL: 0x88, // Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1AH: 0x88, // Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register Bytes
|
||||
ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
}
|
||||
|
||||
// Analog-to-Digital Converter
|
||||
ADC = struct {
|
||||
ADMUX __reg
|
||||
ADCSRA __reg
|
||||
ADCL __reg
|
||||
ADCH __reg
|
||||
ADCSRB __reg
|
||||
DIDR0 __reg
|
||||
DIDR1 __reg
|
||||
AMP0CSR __reg
|
||||
AMP1CSR __reg
|
||||
}{
|
||||
ADMUX: 0x7c, // The ADC multiplexer Selection Register
|
||||
ADCSRA: 0x7a, // The ADC Control and Status register
|
||||
ADCL: 0x78, // ADC Data Register Bytes
|
||||
ADCH: 0x78, // ADC Data Register Bytes
|
||||
ADCSRB: 0x7b, // ADC Control and Status Register B
|
||||
DIDR0: 0x7e, // Digital Input Disable Register 0
|
||||
DIDR1: 0x7f, // Digital Input Disable Register 1
|
||||
AMP0CSR: 0x76,
|
||||
AMP1CSR: 0x77,
|
||||
}
|
||||
|
||||
// Serial Peripheral Interface
|
||||
SPI = struct {
|
||||
SPCR __reg
|
||||
SPSR __reg
|
||||
SPDR __reg
|
||||
}{
|
||||
SPCR: 0x4c, // SPI Control Register
|
||||
SPSR: 0x4d, // SPI Status Register
|
||||
SPDR: 0x4e, // SPI Data Register
|
||||
}
|
||||
|
||||
// Watchdog Timer
|
||||
WDT = struct {
|
||||
WDTCSR __reg
|
||||
}{
|
||||
WDTCSR: 0x60, // Watchdog Timer Control Register
|
||||
}
|
||||
|
||||
// External Interrupts
|
||||
EXINT = struct {
|
||||
EICRA __reg
|
||||
EIMSK __reg
|
||||
EIFR __reg
|
||||
}{
|
||||
EICRA: 0x69, // External Interrupt Control Register A
|
||||
EIMSK: 0x3d, // External Interrupt Mask Register
|
||||
EIFR: 0x3c, // External Interrupt Flag Register
|
||||
}
|
||||
|
||||
// EEPROM
|
||||
EEPROM = struct {
|
||||
EEARL __reg
|
||||
EEARH __reg
|
||||
EEDR __reg
|
||||
EECR __reg
|
||||
}{
|
||||
EEARL: 0x41, // EEPROM Read/Write Access Bytes
|
||||
EEARH: 0x41, // EEPROM Read/Write Access Bytes
|
||||
EEDR: 0x40, // EEPROM Data Register
|
||||
EECR: 0x3f, // EEPROM Control Register
|
||||
}
|
||||
|
||||
// Analog Comparator
|
||||
AC = struct {
|
||||
AC0CON __reg
|
||||
AC2CON __reg
|
||||
ACSR __reg
|
||||
}{
|
||||
AC0CON: 0xad, // Analog Comparator 0 Control Register
|
||||
AC2CON: 0xaf, // Analog Comparator 2 Control Register
|
||||
ACSR: 0x50, // Analog Comparator Status Register
|
||||
}
|
||||
)
|
||||
|
||||
// Bitfields for FUSE: Fuses
|
||||
const (
|
||||
// EXTENDED
|
||||
EXTENDED_PSC2RB = 0x80 // PSC2 Reset Behavior
|
||||
EXTENDED_PSC0RB = 0x20 // PSC0 Reset Behavior
|
||||
EXTENDED_PSCRV = 0x10 // PSCOUT Reset Value
|
||||
EXTENDED_BOOTSZ = 0x6 // Select Boot Size
|
||||
EXTENDED_BOOTRST = 0x1 // Select Reset Vector
|
||||
|
||||
// HIGH
|
||||
HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PC6 as i/o pin)
|
||||
HIGH_DWEN = 0x40 // Debug Wire enable
|
||||
HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled
|
||||
HIGH_WDTON = 0x10 // Watch-dog Timer always on
|
||||
HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle
|
||||
HIGH_BODLEVEL = 0x7 // Brown-out Detector Trigger Level
|
||||
|
||||
// LOW
|
||||
LOW_CKDIV8 = 0x80 // Divide clock by 8 internally
|
||||
LOW_CKOUT = 0x40 // Clock output on PORTB0
|
||||
LOW_SUT_CKSEL = 0x3f // Select Clock Source
|
||||
)
|
||||
|
||||
// Bitfields for LOCKBIT: Lockbits
|
||||
const (
|
||||
// LOCKBIT
|
||||
LOCKBIT_LB = 0x3 // Memory Lock
|
||||
LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode
|
||||
LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode
|
||||
)
|
||||
|
||||
// Bitfields for BOOT_LOAD: Bootloader
|
||||
const (
|
||||
// SPMCSR: Store Program Memory Control Register
|
||||
SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable
|
||||
SPMCSR_RWWSB = 0x40 // Read While Write Section Busy
|
||||
SPMCSR_RWWSRE = 0x10 // Read While Write section read enable
|
||||
SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set
|
||||
SPMCSR_PGWRT = 0x4 // Page Write
|
||||
SPMCSR_PGERS = 0x2 // Page Erase
|
||||
SPMCSR_SPMEN = 0x1 // Store Program Memory Enable
|
||||
)
|
||||
|
||||
// Bitfields for PSC: Power Stage Controller
|
||||
const (
|
||||
// PICR0L: PSC 0 Input Capture Register
|
||||
|
||||
// PICR0H: PSC 0 Input Capture Register
|
||||
PICR0_PCST0 = 0x8000 // PSC 0 Capture Software Trig bit
|
||||
PICR0_PICR0 = 0xfff // PSC 0 Capture Register
|
||||
|
||||
// PFRC0B: PSC 0 Input B Control
|
||||
PFRC0B_PCAE0B = 0x80 // PSC 0 Capture Enable Input Part B
|
||||
PFRC0B_PISEL0B = 0x40 // PSC 0 Input Select for Part B
|
||||
PFRC0B_PELEV0B = 0x20 // PSC 0 Edge Level Selector on Input Part B
|
||||
PFRC0B_PFLTE0B = 0x10 // PSC 0 Filter Enable on Input Part B
|
||||
PFRC0B_PRFM0B = 0xf // PSC 0 Retrigger and Fault Mode for Part B
|
||||
|
||||
// PFRC0A: PSC 0 Input A Control
|
||||
PFRC0A_PCAE0A = 0x80 // PSC 0 Capture Enable Input Part A
|
||||
PFRC0A_PISEL0A = 0x40 // PSC 0 Input Select for Part A
|
||||
PFRC0A_PELEV0A = 0x20 // PSC 0 Edge Level Selector on Input Part A
|
||||
PFRC0A_PFLTE0A = 0x10 // PSC 0 Filter Enable on Input Part A
|
||||
PFRC0A_PRFM0A = 0xf // PSC 0 Retrigger and Fault Mode for Part A
|
||||
|
||||
// PCTL0: PSC 0 Control Register
|
||||
PCTL0_PPRE0 = 0xc0 // PSC 0 Prescaler Selects
|
||||
PCTL0_PBFM0 = 0x20 // PSC 0 Balance Flank Width Modulation
|
||||
PCTL0_PAOC0B = 0x10 // PSC 0 Asynchronous Output Control B
|
||||
PCTL0_PAOC0A = 0x8 // PSC 0 Asynchronous Output Control A
|
||||
PCTL0_PARUN0 = 0x4 // PSC0 Auto Run
|
||||
PCTL0_PCCYC0 = 0x2 // PSC0 Complete Cycle
|
||||
PCTL0_PRUN0 = 0x1 // PSC 0 Run
|
||||
|
||||
// PCNF0: PSC 0 Configuration Register
|
||||
PCNF0_PFIFTY0 = 0x80 // PSC 0 Fifty
|
||||
PCNF0_PALOCK0 = 0x40 // PSC 0 Autolock
|
||||
PCNF0_PLOCK0 = 0x20 // PSC 0 Lock
|
||||
PCNF0_PMODE0 = 0x18 // PSC 0 Mode
|
||||
PCNF0_POP0 = 0x4 // PSC 0 Output Polarity
|
||||
PCNF0_PCLKSEL0 = 0x2 // PSC 0 Input Clock Select
|
||||
|
||||
// PSOC0: PSC0 Synchro and Output Configuration
|
||||
PSOC0_PSYNC0 = 0x30 // Synchronization Out for ADC Selection
|
||||
PSOC0_POEN0B = 0x4 // PSCOUT01 Output Enable
|
||||
PSOC0_POEN0A = 0x1 // PSCOUT00 Output Enable
|
||||
|
||||
// PIM0: PSC0 Interrupt Mask Register
|
||||
PIM0_PSEIE0 = 0x20 // PSC 0 Synchro Error Interrupt Enable
|
||||
PIM0_PEVE0B = 0x10 // External Event B Interrupt Enable
|
||||
PIM0_PEVE0A = 0x8 // External Event A Interrupt Enable
|
||||
PIM0_PEOPE0 = 0x1 // End of Cycle Interrupt Enable
|
||||
|
||||
// PIFR0: PSC0 Interrupt Flag Register
|
||||
PIFR0_PSEI0 = 0x20 // PSC 0 Synchro Error Interrupt
|
||||
PIFR0_PEV0B = 0x10 // External Event B Interrupt
|
||||
PIFR0_PEV0A = 0x8 // External Event A Interrupt
|
||||
PIFR0_PRN0 = 0x6 // Ramp Number
|
||||
PIFR0_PEOP0 = 0x1 // End of PSC0 Interrupt
|
||||
|
||||
// PICR2L: PSC 2 Input Capture Register
|
||||
|
||||
// PICR2H: PSC 2 Input Capture Register
|
||||
PICR2_PCST2 = 0x8000 // PSC 2 Capture Software Trig bit
|
||||
PICR2_PICR2 = 0xfff // PSC 2 Input Capture Register
|
||||
|
||||
// PFRC2B: PSC 2 Input B Control
|
||||
PFRC2B_PCAE2B = 0x80 // PSC 2 Capture Enable Input Part B
|
||||
PFRC2B_PISEL2B = 0x40 // PSC 2 Input Select for Part B
|
||||
PFRC2B_PELEV2B = 0x20 // PSC 2 Edge Level Selector on Input Part B
|
||||
PFRC2B_PFLTE2B = 0x10 // PSC 2 Filter Enable on Input Part B
|
||||
PFRC2B_PRFM2B = 0xf // PSC 2 Retrigger and Fault Mode for Part B
|
||||
|
||||
// PFRC2A: PSC 2 Input B Control
|
||||
PFRC2A_PCAE2A = 0x80 // PSC 2 Capture Enable Input Part A
|
||||
PFRC2A_PISEL2A = 0x40 // PSC 2 Input Select for Part A
|
||||
PFRC2A_PELEV2A = 0x20 // PSC 2 Edge Level Selector on Input Part A
|
||||
PFRC2A_PFLTE2A = 0x10 // PSC 2 Filter Enable on Input Part A
|
||||
PFRC2A_PRFM2A = 0xf // PSC 2 Retrigger and Fault Mode for Part A
|
||||
|
||||
// PCTL2: PSC 2 Control Register
|
||||
PCTL2_PPRE2 = 0xc0 // PSC 2 Prescaler Selects
|
||||
PCTL2_PBFM2 = 0x20 // Balance Flank Width Modulation
|
||||
PCTL2_PAOC2B = 0x10 // PSC 2 Asynchronous Output Control B
|
||||
PCTL2_PAOC2A = 0x8 // PSC 2 Asynchronous Output Control A
|
||||
PCTL2_PARUN2 = 0x4 // PSC2 Auto Run
|
||||
PCTL2_PCCYC2 = 0x2 // PSC2 Complete Cycle
|
||||
PCTL2_PRUN2 = 0x1 // PSC 2 Run
|
||||
|
||||
// PCNF2: PSC 2 Configuration Register
|
||||
PCNF2_PFIFTY2 = 0x80 // PSC 2 Fifty
|
||||
PCNF2_PALOCK2 = 0x40 // PSC 2 Autolock
|
||||
PCNF2_PLOCK2 = 0x20 // PSC 2 Lock
|
||||
PCNF2_PMODE2 = 0x18 // PSC 2 Mode
|
||||
PCNF2_POP2 = 0x4 // PSC 2 Output Polarity
|
||||
PCNF2_PCLKSEL2 = 0x2 // PSC 2 Input Clock Select
|
||||
PCNF2_POME2 = 0x1 // PSC 2 Output Matrix Enable
|
||||
|
||||
// POM2: PSC 2 Output Matrix
|
||||
POM2_POMV2B = 0xf0 // Output Matrix Output B Ramps
|
||||
POM2_POMV2A = 0xf // Output Matrix Output A Ramps
|
||||
|
||||
// PSOC2: PSC2 Synchro and Output Configuration
|
||||
PSOC2_POS2 = 0xc0 // PSC 2 Output 23 Select
|
||||
PSOC2_PSYNC2 = 0x30 // Synchronization Out for ADC Selection
|
||||
PSOC2_POEN2D = 0x8 // PSCOUT23 Output Enable
|
||||
PSOC2_POEN2B = 0x4 // PSCOUT21 Output Enable
|
||||
PSOC2_POEN2C = 0x2 // PSCOUT22 Output Enable
|
||||
PSOC2_POEN2A = 0x1 // PSCOUT20 Output Enable
|
||||
|
||||
// PIM2: PSC2 Interrupt Mask Register
|
||||
PIM2_PSEIE2 = 0x20 // PSC 2 Synchro Error Interrupt Enable
|
||||
PIM2_PEVE2B = 0x10 // External Event B Interrupt Enable
|
||||
PIM2_PEVE2A = 0x8 // External Event A Interrupt Enable
|
||||
PIM2_PEOPE2 = 0x1 // End of Cycle Interrupt Enable
|
||||
|
||||
// PIFR2: PSC2 Interrupt Flag Register
|
||||
PIFR2_PSEI2 = 0x20 // PSC 2 Synchro Error Interrupt
|
||||
PIFR2_PEV2B = 0x10 // External Event B Interrupt
|
||||
PIFR2_PEV2A = 0x8 // External Event A Interrupt
|
||||
PIFR2_PRN2 = 0x6 // Ramp Number
|
||||
PIFR2_PEOP2 = 0x1 // End of PSC2 Interrupt
|
||||
|
||||
// PFRC1B: PSC 1 Input B Control
|
||||
PFRC1B_PCAE1B = 0x80 // PSC 1 Capture Enable Input Part B
|
||||
PFRC1B_PISEL1B = 0x40 // PSC 1 Input Select for Part B
|
||||
PFRC1B_PELEV1B = 0x20 // PSC 1 Edge Level Selector on Input Part B
|
||||
PFRC1B_PFLTE1B = 0x10 // PSC 1 Filter Enable on Input Part B
|
||||
PFRC1B_PRFM1B = 0xf // PSC 1 Retrigger and Fault Mode for Part B
|
||||
|
||||
// PFRC1A: PSC 1 Input B Control
|
||||
PFRC1A_PCAE1A = 0x80 // PSC 1 Capture Enable Input Part A
|
||||
PFRC1A_PISEL1A = 0x40 // PSC 1 Input Select for Part A
|
||||
PFRC1A_PELEV1A = 0x20 // PSC 1 Edge Level Selector on Input Part A
|
||||
PFRC1A_PFLTE1A = 0x10 // PSC 1 Filter Enable on Input Part A
|
||||
PFRC1A_PRFM1A = 0xf // PSC 1 Retrigger and Fault Mode for Part A
|
||||
|
||||
// PCTL1: PSC 1 Control Register
|
||||
PCTL1_PPRE1 = 0xc0 // PSC 1 Prescaler Selects
|
||||
PCTL1_PBFM1 = 0x20 // Balance Flank Width Modulation
|
||||
PCTL1_PAOC1B = 0x10 // PSC 1 Asynchronous Output Control B
|
||||
PCTL1_PAOC1A = 0x8 // PSC 1 Asynchronous Output Control A
|
||||
PCTL1_PARUN1 = 0x4 // PSC1 Auto Run
|
||||
PCTL1_PCCYC1 = 0x2 // PSC1 Complete Cycle
|
||||
PCTL1_PRUN1 = 0x1 // PSC 1 Run
|
||||
|
||||
// PSOC1: PSC1 Synchro and Output Configuration
|
||||
PSOC1_PSYNC1 = 0x30 // Synchronization Out for ADC Selection
|
||||
PSOC1_POEN1B = 0x4 // PSCOUT11 Output Enable
|
||||
PSOC1_POEN1A = 0x1 // PSCOUT10 Output Enable
|
||||
)
|
||||
|
||||
// Bitfields for CPU: CPU Registers
|
||||
const (
|
||||
// SREG: Status Register
|
||||
SREG_I = 0x80 // Global Interrupt Enable
|
||||
SREG_T = 0x40 // Bit Copy Storage
|
||||
SREG_H = 0x20 // Half Carry Flag
|
||||
SREG_S = 0x10 // Sign Bit
|
||||
SREG_V = 0x8 // Two's Complement Overflow Flag
|
||||
SREG_N = 0x4 // Negative Flag
|
||||
SREG_Z = 0x2 // Zero Flag
|
||||
SREG_C = 0x1 // Carry Flag
|
||||
|
||||
// MCUCR: MCU Control Register
|
||||
MCUCR_SPIPS = 0x80 // SPI Pin Select
|
||||
MCUCR_PUD = 0x10 // Pull-up disable
|
||||
MCUCR_IVSEL = 0x2 // Interrupt Vector Select
|
||||
MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable
|
||||
|
||||
// MCUSR: MCU Status Register
|
||||
MCUSR_WDRF = 0x8 // Watchdog Reset Flag
|
||||
MCUSR_BORF = 0x4 // Brown-out Reset Flag
|
||||
MCUSR_EXTRF = 0x2 // External Reset Flag
|
||||
MCUSR_PORF = 0x1 // Power-on reset flag
|
||||
|
||||
// OSCCAL: Oscillator Calibration Value
|
||||
OSCCAL_OSCCAL = 0xff // Oscillator Calibration
|
||||
|
||||
// CLKPR
|
||||
CLKPR_CLKPCE = 0x80
|
||||
CLKPR_CLKPS = 0xf
|
||||
|
||||
// SMCR: Sleep Mode Control Register
|
||||
SMCR_SM = 0xe // Sleep Mode Select bits
|
||||
SMCR_SE = 0x1 // Sleep Enable
|
||||
|
||||
// GPIOR3: General Purpose IO Register 3
|
||||
GPIOR3_GPIOR = 0xff // General Purpose IO Register 3 bis
|
||||
|
||||
// GPIOR2: General Purpose IO Register 2
|
||||
GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis
|
||||
|
||||
// GPIOR1: General Purpose IO Register 1
|
||||
GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis
|
||||
|
||||
// GPIOR0: General Purpose IO Register 0
|
||||
GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7
|
||||
GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6
|
||||
GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5
|
||||
GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4
|
||||
GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3
|
||||
GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2
|
||||
GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1
|
||||
GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0
|
||||
|
||||
// PLLCSR: PLL Control And Status Register
|
||||
PLLCSR_PLLF = 0x4 // PLL Factor
|
||||
PLLCSR_PLLE = 0x2 // PLL Enable
|
||||
PLLCSR_PLOCK = 0x1 // PLL Lock Detector
|
||||
|
||||
// PRR: Power Reduction Register
|
||||
PRR_PRPSC2 = 0x80 // Power Reduction PSC2
|
||||
PRR_PRPSC1 = 0x40 // Power Reduction PSC1
|
||||
PRR_PRPSC0 = 0x20 // Power Reduction PSC0
|
||||
PRR_PRTIM1 = 0x10 // Power Reduction Timer/Counter1
|
||||
PRR_PRTIM0 = 0x8 // Power Reduction Timer/Counter0
|
||||
PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface
|
||||
PRR_PRUSART0 = 0x2 // Power Reduction USART
|
||||
PRR_PRADC = 0x1 // Power Reduction ADC
|
||||
)
|
||||
|
||||
// Bitfields for TC8: Timer/Counter, 8-bit
|
||||
const (
|
||||
// TIMSK0: Timer/Counter0 Interrupt Mask Register
|
||||
TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable
|
||||
TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable
|
||||
TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable
|
||||
|
||||
// TIFR0: Timer/Counter0 Interrupt Flag register
|
||||
TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B
|
||||
TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A
|
||||
TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag
|
||||
|
||||
// TCCR0A: Timer/Counter Control Register A
|
||||
TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode
|
||||
TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm
|
||||
TCCR0A_WGM0 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TCCR0B: Timer/Counter Control Register B
|
||||
TCCR0B_FOC0A = 0x80 // Force Output Compare A
|
||||
TCCR0B_FOC0B = 0x40 // Force Output Compare B
|
||||
TCCR0B_WGM02 = 0x8
|
||||
TCCR0B_CS0 = 0x7 // Clock Select
|
||||
|
||||
// TCNT0: Timer/Counter0
|
||||
TCNT0_TCNT0 = 0xff // Timer Counter 0 value
|
||||
|
||||
// OCR0A: Timer/Counter0 Output Compare Register
|
||||
OCR0A_OCR0A = 0xff // Output Compare A value
|
||||
|
||||
// OCR0B: Timer/Counter0 Output Compare Register
|
||||
OCR0B_OCR0B = 0xff // Output Compare B value
|
||||
)
|
||||
|
||||
// Bitfields for TC16: Timer/Counter, 16-bit
|
||||
const (
|
||||
// TIMSK1: Timer/Counter Interrupt Mask Register
|
||||
TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable
|
||||
TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output CompareB Match Interrupt Enable
|
||||
TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output CompareA Match Interrupt Enable
|
||||
TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable
|
||||
|
||||
// TIFR1: Timer/Counter Interrupt Flag register
|
||||
TIFR1_ICF1 = 0x20 // Input Capture Flag 1
|
||||
TIFR1_OCF1B = 0x4 // Output Compare Flag 1B
|
||||
TIFR1_OCF1A = 0x2 // Output Compare Flag 1A
|
||||
TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag
|
||||
|
||||
// TCCR1A: Timer/Counter1 Control Register A
|
||||
TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits
|
||||
TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits
|
||||
TCCR1A_WGM1 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TCCR1B: Timer/Counter1 Control Register B
|
||||
TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler
|
||||
TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select
|
||||
TCCR1B_WGM1 = 0x18 // Waveform Generation Mode
|
||||
TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1
|
||||
|
||||
// TCCR1C: Timer/Counter1 Control Register C
|
||||
TCCR1C_FOC1A = 0x80
|
||||
TCCR1C_FOC1B = 0x40
|
||||
|
||||
// TCNT1L: Timer/Counter1 Bytes
|
||||
|
||||
// TCNT1H: Timer/Counter1 Bytes
|
||||
TCNT1_TCNT1 = 0xffff // Timer/Counter1
|
||||
|
||||
// OCR1AL: Timer/Counter1 Output Compare Register Bytes
|
||||
|
||||
// OCR1AH: Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1A_OCR1A = 0xffff // Timer/Counter1 Output Compare A Register
|
||||
|
||||
// OCR1BL: Timer/Counter1 Output Compare Register Bytes
|
||||
|
||||
// OCR1BH: Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1B_OCR1B = 0xffff // Timer/Counter1 Output Compare B Register
|
||||
|
||||
// ICR1L: Timer/Counter1 Input Capture Register Bytes
|
||||
|
||||
// ICR1H: Timer/Counter1 Input Capture Register Bytes
|
||||
ICR1_ICR1 = 0xffff // Timer/Counter Input Capture
|
||||
)
|
||||
|
||||
// Bitfields for ADC: Analog-to-Digital Converter
|
||||
const (
|
||||
// ADMUX: The ADC multiplexer Selection Register
|
||||
ADMUX_REFS = 0xc0 // Reference Selection Bits
|
||||
ADMUX_ADLAR = 0x20 // Left Adjust Result
|
||||
ADMUX_MUX = 0xf // Analog Channel and Gain Selection Bits
|
||||
|
||||
// ADCSRA: The ADC Control and Status register
|
||||
ADCSRA_ADEN = 0x80 // ADC Enable
|
||||
ADCSRA_ADSC = 0x40 // ADC Start Conversion
|
||||
ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable
|
||||
ADCSRA_ADIF = 0x10 // ADC Interrupt Flag
|
||||
ADCSRA_ADIE = 0x8 // ADC Interrupt Enable
|
||||
ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits
|
||||
|
||||
// ADCSRB: ADC Control and Status Register B
|
||||
ADCSRB_ADHSM = 0x80 // ADC High Speed Mode
|
||||
ADCSRB_ADASCR = 0x10 // ADC Start Conversion
|
||||
ADCSRB_ADTS3 = 0x8 // ADC Auto Trigger Source Selection 3
|
||||
ADCSRB_ADTS2 = 0x4 // ADC Auto Trigger Source Selection 2
|
||||
ADCSRB_ADTS1 = 0x2 // ADC Auto Trigger Source Selection 1
|
||||
ADCSRB_ADTS0 = 0x1 // ADC Auto Trigger Source Selection 0
|
||||
|
||||
// DIDR0: Digital Input Disable Register 0
|
||||
DIDR0_ADC7D = 0x80
|
||||
DIDR0_ADC6D = 0x40
|
||||
DIDR0_ADC5D = 0x20
|
||||
DIDR0_ADC4D = 0x10
|
||||
DIDR0_ADC3D = 0x8
|
||||
DIDR0_ADC2D = 0x4
|
||||
DIDR0_ADC1D = 0x2
|
||||
DIDR0_ADC0D = 0x1
|
||||
|
||||
// DIDR1: Digital Input Disable Register 1
|
||||
DIDR1_ACMP0D = 0x20
|
||||
DIDR1_AMP0PD = 0x10
|
||||
DIDR1_AMP0ND = 0x8
|
||||
DIDR1_ADC10D = 0x4
|
||||
DIDR1_ADC9D = 0x2
|
||||
DIDR1_ADC8D = 0x1
|
||||
|
||||
// AMP0CSR
|
||||
AMP0CSR_AMP0EN = 0x80
|
||||
AMP0CSR_AMP0IS = 0x40
|
||||
AMP0CSR_AMP0G = 0x30
|
||||
AMP0CSR_AMP0TS = 0x3
|
||||
|
||||
// AMP1CSR
|
||||
AMP1CSR_AMP1EN = 0x80
|
||||
AMP1CSR_AMP1IS = 0x40
|
||||
AMP1CSR_AMP1G = 0x30
|
||||
AMP1CSR_AMP1TS = 0x3
|
||||
)
|
||||
|
||||
// Bitfields for SPI: Serial Peripheral Interface
|
||||
const (
|
||||
// SPCR: SPI Control Register
|
||||
SPCR_SPIE = 0x80 // SPI Interrupt Enable
|
||||
SPCR_SPE = 0x40 // SPI Enable
|
||||
SPCR_DORD = 0x20 // Data Order
|
||||
SPCR_MSTR = 0x10 // Master/Slave Select
|
||||
SPCR_CPOL = 0x8 // Clock polarity
|
||||
SPCR_CPHA = 0x4 // Clock Phase
|
||||
SPCR_SPR = 0x3 // SPI Clock Rate Selects
|
||||
|
||||
// SPSR: SPI Status Register
|
||||
SPSR_SPIF = 0x80 // SPI Interrupt Flag
|
||||
SPSR_WCOL = 0x40 // Write Collision Flag
|
||||
SPSR_SPI2X = 0x1 // Double SPI Speed Bit
|
||||
|
||||
// SPDR: SPI Data Register
|
||||
SPDR_SPD = 0xff // SPI Data
|
||||
)
|
||||
|
||||
// Bitfields for WDT: Watchdog Timer
|
||||
const (
|
||||
// WDTCSR: Watchdog Timer Control Register
|
||||
WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag
|
||||
WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable
|
||||
WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits
|
||||
WDTCSR_WDCE = 0x10 // Watchdog Change Enable
|
||||
WDTCSR_WDE = 0x8 // Watch Dog Enable
|
||||
)
|
||||
|
||||
// Bitfields for EXINT: External Interrupts
|
||||
const (
|
||||
// EICRA: External Interrupt Control Register A
|
||||
EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit
|
||||
EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit
|
||||
EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit
|
||||
EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit
|
||||
|
||||
// EIMSK: External Interrupt Mask Register
|
||||
EIMSK_INT = 0xf // External Interrupt Mask
|
||||
|
||||
// EIFR: External Interrupt Flag Register
|
||||
EIFR_INTF = 0xf // External Interrupt Flags
|
||||
)
|
||||
|
||||
// Bitfields for EEPROM: EEPROM
|
||||
const (
|
||||
// EEARL: EEPROM Read/Write Access Bytes
|
||||
|
||||
// EEARH: EEPROM Read/Write Access Bytes
|
||||
EEAR_EEAR = 0xfff // EEPROM Address bytes
|
||||
|
||||
// EEDR: EEPROM Data Register
|
||||
EEDR_EEDR = 0xff // EEPROM Data Bits
|
||||
|
||||
// EECR: EEPROM Control Register
|
||||
EECR_EEPM = 0x30 // EEPROM Programming Mode
|
||||
EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable
|
||||
EECR_EEMWE = 0x4 // EEPROM Master Write Enable
|
||||
EECR_EEWE = 0x2 // EEPROM Write Enable
|
||||
EECR_EERE = 0x1 // EEPROM Read Enable
|
||||
)
|
||||
|
||||
// Bitfields for AC: Analog Comparator
|
||||
const (
|
||||
// AC0CON: Analog Comparator 0 Control Register
|
||||
AC0CON_AC0EN = 0x80 // Analog Comparator 0 Enable Bit
|
||||
AC0CON_AC0IE = 0x40 // Analog Comparator 0 Interrupt Enable Bit
|
||||
AC0CON_AC0IS = 0x30 // Analog Comparator 0 Interrupt Select Bit
|
||||
AC0CON_AC0M = 0x7 // Analog Comparator 0 Multiplexer Register
|
||||
|
||||
// AC2CON: Analog Comparator 2 Control Register
|
||||
AC2CON_AC2EN = 0x80 // Analog Comparator 2 Enable Bit
|
||||
AC2CON_AC2IE = 0x40 // Analog Comparator 2 Interrupt Enable Bit
|
||||
AC2CON_AC2IS = 0x30 // Analog Comparator 2 Interrupt Select Bit
|
||||
AC2CON_AC2M = 0x7 // Analog Comparator 2 Multiplexer Register
|
||||
|
||||
// ACSR: Analog Comparator Status Register
|
||||
ACSR_ACCKDIV = 0x80 // Analog Comparator Clock Divider
|
||||
ACSR_AC2IF = 0x40 // Analog Comparator 2 Interrupt Flag Bit
|
||||
ACSR_AC1IF = 0x20 // Analog Comparator 1 Interrupt Flag Bit
|
||||
ACSR_AC0IF = 0x10 // Analog Comparator 0 Interrupt Flag Bit
|
||||
ACSR_AC2O = 0x4 // Analog Comparator 2 Output Bit
|
||||
ACSR_AC1O = 0x2 // Analog Comparator 1 Output Bit
|
||||
ACSR_AC0O = 0x1 // Analog Comparator 0 Output Bit
|
||||
)
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from AT90PWM1.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x2000;
|
||||
__ram_size = 0x200;
|
||||
__num_isrs = 32;
|
||||
|
|
@ -1,757 +0,0 @@
|
|||
// Automatically generated file. DO NOT EDIT.
|
||||
// Generated by gen-device.py from AT90PWM161.atdf, see http://packs.download.atmel.com/
|
||||
|
||||
// +build avr,at90pwm161
|
||||
|
||||
// Device information for the AT90PWM161.
|
||||
//
|
||||
package avr
|
||||
|
||||
// Magic type name for the compiler.
|
||||
type __reg uint8
|
||||
|
||||
// Export this magic type name.
|
||||
type RegValue = __reg
|
||||
|
||||
// Some information about this device.
|
||||
const (
|
||||
DEVICE = "AT90PWM161"
|
||||
ARCH = "AVR8"
|
||||
FAMILY = "megaAVR"
|
||||
)
|
||||
|
||||
// Interrupts
|
||||
const (
|
||||
IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset
|
||||
IRQ_PSC2_CAPT = 1 // PSC2 Capture Event
|
||||
IRQ_PSC2_EC = 2 // PSC2 End Cycle
|
||||
IRQ_PSC2_EEC = 3 // PSC2 End Of Enhanced Cycle
|
||||
IRQ_PSC0_CAPT = 4 // PSC0 Capture Event
|
||||
IRQ_PSC0_EC = 5 // PSC0 End Cycle
|
||||
IRQ_PSC0_EEC = 6 // PSC0 End Of Enhanced Cycle
|
||||
IRQ_ANALOG_COMP_1 = 7 // Analog Comparator 1
|
||||
IRQ_ANALOG_COMP_2 = 8 // Analog Comparator 2
|
||||
IRQ_ANALOG_COMP_3 = 9 // Analog Comparator 3
|
||||
IRQ_INT0 = 10 // External Interrupt Request 0
|
||||
IRQ_TIMER1_CAPT = 11 // Timer/Counter1 Capture Event
|
||||
IRQ_TIMER1_OVF = 12 // Timer/Counter1 Overflow
|
||||
IRQ_ADC = 13 // ADC Conversion Complete
|
||||
IRQ_INT1 = 14 // External Interrupt Request 1
|
||||
IRQ_SPI_STC = 15 // SPI Serial Transfer Complet
|
||||
IRQ_INT2 = 16 // External Interrupt Request 2
|
||||
IRQ_WDT = 17 // Watchdog Timeout Interrupt
|
||||
IRQ_EE_READY = 18 // EEPROM Ready
|
||||
IRQ_SPM_READY = 19 // Store Program Memory Read
|
||||
IRQ_max = 19 // Highest interrupt number on this device.
|
||||
)
|
||||
|
||||
// Peripherals
|
||||
var (
|
||||
// Fuses
|
||||
FUSE = struct {
|
||||
EXTENDED __reg
|
||||
HIGH __reg
|
||||
LOW __reg
|
||||
}{
|
||||
EXTENDED: 0x2,
|
||||
HIGH: 0x1,
|
||||
LOW: 0x0,
|
||||
}
|
||||
|
||||
// Lockbits
|
||||
LOCKBIT = struct {
|
||||
LOCKBIT __reg
|
||||
}{
|
||||
LOCKBIT: 0x0,
|
||||
}
|
||||
|
||||
// I/O Port
|
||||
PORT = struct {
|
||||
PORTB __reg
|
||||
DDRB __reg
|
||||
PINB __reg
|
||||
PORTD __reg
|
||||
DDRD __reg
|
||||
PIND __reg
|
||||
PORTE __reg
|
||||
DDRE __reg
|
||||
PINE __reg
|
||||
}{
|
||||
PORTB: 0x25, // Port B Data Register
|
||||
DDRB: 0x24, // Port B Data Direction Register
|
||||
PINB: 0x23, // Port B Input Pins
|
||||
PORTD: 0x2b, // Port D Data Register
|
||||
DDRD: 0x2a, // Port D Data Direction Register
|
||||
PIND: 0x29, // Port D Input Pins
|
||||
PORTE: 0x2e, // Port E Data Register
|
||||
DDRE: 0x2d, // Port E Data Direction Register
|
||||
PINE: 0x2c, // Port E Input Pins
|
||||
}
|
||||
|
||||
// Digital-to-Analog Converter
|
||||
DAC = struct {
|
||||
DACH __reg
|
||||
DACL __reg
|
||||
DACON __reg
|
||||
}{
|
||||
DACH: 0x59, // DAC Data Register High Byte
|
||||
DACL: 0x58, // DAC Data Register Low Byte
|
||||
DACON: 0x76, // DAC Control Register
|
||||
}
|
||||
|
||||
// Serial Peripheral Interface
|
||||
SPI = struct {
|
||||
SPCR __reg
|
||||
SPSR __reg
|
||||
SPDR __reg
|
||||
}{
|
||||
SPCR: 0x37, // SPI Control Register
|
||||
SPSR: 0x38, // SPI Status Register
|
||||
SPDR: 0x56, // SPI Data Register
|
||||
}
|
||||
|
||||
// Watchdog Timer
|
||||
WDT = struct {
|
||||
WDTCSR __reg
|
||||
}{
|
||||
WDTCSR: 0x82, // Watchdog Timer Control Register
|
||||
}
|
||||
|
||||
// External Interrupts
|
||||
EXINT = struct {
|
||||
EICRA __reg
|
||||
EIMSK __reg
|
||||
EIFR __reg
|
||||
}{
|
||||
EICRA: 0x89, // External Interrupt Control Register A
|
||||
EIMSK: 0x41, // External Interrupt Mask Register
|
||||
EIFR: 0x40, // External Interrupt Flag Register
|
||||
}
|
||||
|
||||
// Analog-to-Digital Converter
|
||||
ADC = struct {
|
||||
ADMUX __reg
|
||||
ADCSRA __reg
|
||||
ADCL __reg
|
||||
ADCH __reg
|
||||
ADCSRB __reg
|
||||
DIDR0 __reg
|
||||
DIDR1 __reg
|
||||
AMP0CSR __reg
|
||||
}{
|
||||
ADMUX: 0x28, // The ADC multiplexer Selection Register
|
||||
ADCSRA: 0x26, // The ADC Control and Status register
|
||||
ADCL: 0x4c, // ADC Data Register Bytes
|
||||
ADCH: 0x4c, // ADC Data Register Bytes
|
||||
ADCSRB: 0x27, // ADC Control and Status Register B
|
||||
DIDR0: 0x77, // Digital Input Disable Register 0
|
||||
DIDR1: 0x78, // Digital Input Disable Register 0
|
||||
AMP0CSR: 0x79,
|
||||
}
|
||||
|
||||
// Analog Comparator
|
||||
AC = struct {
|
||||
AC3CON __reg
|
||||
AC1CON __reg
|
||||
AC2CON __reg
|
||||
ACSR __reg
|
||||
AC3ECON __reg
|
||||
AC2ECON __reg
|
||||
AC1ECON __reg
|
||||
}{
|
||||
AC3CON: 0x7f, // Analog Comparator3 Control Register
|
||||
AC1CON: 0x7d, // Analog Comparator 1 Control Register
|
||||
AC2CON: 0x7e, // Analog Comparator 2 Control Register
|
||||
ACSR: 0x20, // Analog Comparator Status Register
|
||||
AC3ECON: 0x7c,
|
||||
AC2ECON: 0x7b,
|
||||
AC1ECON: 0x7a,
|
||||
}
|
||||
|
||||
// CPU Registers
|
||||
CPU = struct {
|
||||
SREG __reg
|
||||
SPL __reg
|
||||
SPH __reg
|
||||
MCUCR __reg
|
||||
MCUSR __reg
|
||||
OSCCAL __reg
|
||||
CLKPR __reg
|
||||
SMCR __reg
|
||||
GPIOR2 __reg
|
||||
GPIOR1 __reg
|
||||
GPIOR0 __reg
|
||||
PLLCSR __reg
|
||||
PRR __reg
|
||||
CLKCSR __reg
|
||||
CLKSELR __reg
|
||||
BGCCR __reg
|
||||
BGCRR __reg
|
||||
}{
|
||||
SREG: 0x5f, // Status Register
|
||||
SPL: 0x5d, // Stack Pointer
|
||||
SPH: 0x5d, // Stack Pointer
|
||||
MCUCR: 0x55, // MCU Control Register
|
||||
MCUSR: 0x54, // MCU Status Register
|
||||
OSCCAL: 0x88, // Oscillator Calibration Value
|
||||
CLKPR: 0x83,
|
||||
SMCR: 0x53, // Sleep Mode Control Register
|
||||
GPIOR2: 0x3b, // General Purpose IO Register 2
|
||||
GPIOR1: 0x3a, // General Purpose IO Register 1
|
||||
GPIOR0: 0x39, // General Purpose IO Register 0
|
||||
PLLCSR: 0x87, // PLL Control And Status Register
|
||||
PRR: 0x86, // Power Reduction Register
|
||||
CLKCSR: 0x84,
|
||||
CLKSELR: 0x85,
|
||||
BGCCR: 0x81, // BandGap Current Calibration Register
|
||||
BGCRR: 0x80, // BandGap Resistor Calibration Register
|
||||
}
|
||||
|
||||
// EEPROM
|
||||
EEPROM = struct {
|
||||
EEARL __reg
|
||||
EEARH __reg
|
||||
EEDR __reg
|
||||
EECR __reg
|
||||
}{
|
||||
EEARL: 0x3e, // EEPROM Read/Write Access Bytes
|
||||
EEARH: 0x3e, // EEPROM Read/Write Access Bytes
|
||||
EEDR: 0x3d, // EEPROM Data Register
|
||||
EECR: 0x3c, // EEPROM Control Register
|
||||
}
|
||||
|
||||
// Power Stage Controller
|
||||
PSC = struct {
|
||||
PICR0L __reg
|
||||
PICR0H __reg
|
||||
PFRC0B __reg
|
||||
PFRC0A __reg
|
||||
PCTL0 __reg
|
||||
PCNF0 __reg
|
||||
OCR0RBL __reg
|
||||
OCR0RBH __reg
|
||||
OCR0SBL __reg
|
||||
OCR0SBH __reg
|
||||
OCR0RAL __reg
|
||||
OCR0RAH __reg
|
||||
OCR0SAL __reg
|
||||
OCR0SAH __reg
|
||||
PSOC0 __reg
|
||||
PIM0 __reg
|
||||
PIFR0 __reg
|
||||
PICR2H __reg
|
||||
PICR2L __reg
|
||||
PFRC2B __reg
|
||||
PFRC2A __reg
|
||||
PCTL2 __reg
|
||||
PCNF2 __reg
|
||||
PCNFE2 __reg
|
||||
OCR2RBL __reg
|
||||
OCR2RBH __reg
|
||||
OCR2SBL __reg
|
||||
OCR2SBH __reg
|
||||
OCR2RAL __reg
|
||||
OCR2RAH __reg
|
||||
OCR2SAL __reg
|
||||
OCR2SAH __reg
|
||||
POM2 __reg
|
||||
PSOC2 __reg
|
||||
PIM2 __reg
|
||||
PIFR2 __reg
|
||||
PASDLY2 __reg
|
||||
}{
|
||||
PICR0L: 0x68, // PSC 0 Input Capture Register
|
||||
PICR0H: 0x68, // PSC 0 Input Capture Register
|
||||
PFRC0B: 0x63, // PSC 0 Input B Control
|
||||
PFRC0A: 0x62, // PSC 0 Input A Control
|
||||
PCTL0: 0x32, // PSC 0 Control Register
|
||||
PCNF0: 0x31, // PSC 0 Configuration Register
|
||||
OCR0RBL: 0x44, // Output Compare RB Register
|
||||
OCR0RBH: 0x44, // Output Compare RB Register
|
||||
OCR0SBL: 0x42, // Output Compare SB Register
|
||||
OCR0SBH: 0x42, // Output Compare SB Register
|
||||
OCR0RAL: 0x4a, // Output Compare RA Register
|
||||
OCR0RAH: 0x4a, // Output Compare RA Register
|
||||
OCR0SAL: 0x60, // Output Compare SA Register
|
||||
OCR0SAH: 0x60, // Output Compare SA Register
|
||||
PSOC0: 0x6a, // PSC0 Synchro and Output Configuration
|
||||
PIM0: 0x2f, // PSC0 Interrupt Mask Register
|
||||
PIFR0: 0x30, // PSC0 Interrupt Flag Register
|
||||
PICR2H: 0x6d, // PSC 2 Input Capture Register High
|
||||
PICR2L: 0x6c, // PSC 2 Input Capture Register Low
|
||||
PFRC2B: 0x67, // PSC 2 Input B Control
|
||||
PFRC2A: 0x66, // PSC 2 Input B Control
|
||||
PCTL2: 0x36, // PSC 2 Control Register
|
||||
PCNF2: 0x35, // PSC 2 Configuration Register
|
||||
PCNFE2: 0x70, // PSC 2 Enhanced Configuration Register
|
||||
OCR2RBL: 0x48, // Output Compare RB Register
|
||||
OCR2RBH: 0x48, // Output Compare RB Register
|
||||
OCR2SBL: 0x46, // Output Compare SB Register
|
||||
OCR2SBH: 0x46, // Output Compare SB Register
|
||||
OCR2RAL: 0x4e, // Output Compare RA Register
|
||||
OCR2RAH: 0x4e, // Output Compare RA Register
|
||||
OCR2SAL: 0x64, // Output Compare SA Register
|
||||
OCR2SAH: 0x64, // Output Compare SA Register
|
||||
POM2: 0x6f, // PSC 2 Output Matrix
|
||||
PSOC2: 0x6e, // PSC2 Synchro and Output Configuration
|
||||
PIM2: 0x33, // PSC2 Interrupt Mask Register
|
||||
PIFR2: 0x34, // PSC2 Interrupt Flag Register
|
||||
PASDLY2: 0x71, // Analog Synchronization Delay Register
|
||||
}
|
||||
|
||||
// Timer/Counter, 16-bit
|
||||
TC16 = struct {
|
||||
TIMSK1 __reg
|
||||
TIFR1 __reg
|
||||
TCCR1B __reg
|
||||
TCNT1L __reg
|
||||
TCNT1H __reg
|
||||
ICR1L __reg
|
||||
ICR1H __reg
|
||||
}{
|
||||
TIMSK1: 0x21, // Timer/Counter Interrupt Mask Register
|
||||
TIFR1: 0x22, // Timer/Counter Interrupt Flag register
|
||||
TCCR1B: 0x8a, // Timer/Counter1 Control Register B
|
||||
TCNT1L: 0x5a, // Timer/Counter1 Bytes
|
||||
TCNT1H: 0x5a, // Timer/Counter1 Bytes
|
||||
ICR1L: 0x8c, // Timer/Counter1 Input Capture Register Bytes
|
||||
ICR1H: 0x8c, // Timer/Counter1 Input Capture Register Bytes
|
||||
}
|
||||
|
||||
// Bootloader
|
||||
BOOT_LOAD = struct {
|
||||
SPMCSR __reg
|
||||
}{
|
||||
SPMCSR: 0x57, // Store Program Memory Control Register
|
||||
}
|
||||
)
|
||||
|
||||
// Bitfields for FUSE: Fuses
|
||||
const (
|
||||
// EXTENDED
|
||||
EXTENDED_PSC2RB = 0x80 // PSC2 Reset Behavior
|
||||
EXTENDED_PSC2RBA = 0x40 // PSC2 Reset Behavior for 22 and 23
|
||||
EXTENDED_PSC0RB = 0x20 // PSC0 Reset Behavior
|
||||
EXTENDED_PSCRV = 0x10 // PSC Reset Value
|
||||
EXTENDED_PSCINRB = 0x8 // PSC2 and PSC0 input Reset Behavior
|
||||
EXTENDED_BODLEVEL = 0x7 // Brown-out Detector Trigger Level
|
||||
|
||||
// HIGH
|
||||
HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PE0 as I/O pin)
|
||||
HIGH_DWEN = 0x40 // Debug Wire enable
|
||||
HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled
|
||||
HIGH_WDTON = 0x10 // Watch-dog Timer always on
|
||||
HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle
|
||||
HIGH_BOOTSZ = 0x6 // Select Boot Size
|
||||
HIGH_BOOTRST = 0x1 // Select Reset Vector
|
||||
|
||||
// LOW
|
||||
LOW_CKDIV8 = 0x80 // Divide clock by 8 internally
|
||||
LOW_CKOUT = 0x40 // Clock output on PORTD1
|
||||
LOW_SUT_CKSEL = 0x3f // Select Clock Source
|
||||
)
|
||||
|
||||
// Bitfields for LOCKBIT: Lockbits
|
||||
const (
|
||||
// LOCKBIT
|
||||
LOCKBIT_LB = 0x3 // Memory Lock
|
||||
LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode
|
||||
LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode
|
||||
)
|
||||
|
||||
// Bitfields for DAC: Digital-to-Analog Converter
|
||||
const (
|
||||
// DACH: DAC Data Register High Byte
|
||||
DACH_DACH = 0xff // DAC Data Register High Byte Bits
|
||||
|
||||
// DACL: DAC Data Register Low Byte
|
||||
DACL_DACL = 0xff // DAC Data Register Low Byte Bits
|
||||
|
||||
// DACON: DAC Control Register
|
||||
DACON_DAATE = 0x80 // DAC Auto Trigger Enable Bit
|
||||
DACON_DATS = 0x70 // DAC Trigger Selection Bits
|
||||
DACON_DALA = 0x4 // DAC Left Adjust
|
||||
DACON_DAEN = 0x1 // DAC Enable Bit
|
||||
)
|
||||
|
||||
// Bitfields for SPI: Serial Peripheral Interface
|
||||
const (
|
||||
// SPCR: SPI Control Register
|
||||
SPCR_SPIE = 0x80 // SPI Interrupt Enable
|
||||
SPCR_SPE = 0x40 // SPI Enable
|
||||
SPCR_DORD = 0x20 // Data Order
|
||||
SPCR_MSTR = 0x10 // Master/Slave Select
|
||||
SPCR_CPOL = 0x8 // Clock polarity
|
||||
SPCR_CPHA = 0x4 // Clock Phase
|
||||
SPCR_SPR = 0x3 // SPI Clock Rate Selects
|
||||
|
||||
// SPSR: SPI Status Register
|
||||
SPSR_SPIF = 0x80 // SPI Interrupt Flag
|
||||
SPSR_WCOL = 0x40 // Write Collision Flag
|
||||
SPSR_SPI2X = 0x1 // Double SPI Speed Bit
|
||||
)
|
||||
|
||||
// Bitfields for WDT: Watchdog Timer
|
||||
const (
|
||||
// WDTCSR: Watchdog Timer Control Register
|
||||
WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag
|
||||
WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable
|
||||
WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits
|
||||
WDTCSR_WDCE = 0x10 // Watchdog Change Enable
|
||||
WDTCSR_WDE = 0x8 // Watch Dog Enable
|
||||
)
|
||||
|
||||
// Bitfields for EXINT: External Interrupts
|
||||
const (
|
||||
// EICRA: External Interrupt Control Register A
|
||||
EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit
|
||||
EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit
|
||||
EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit
|
||||
|
||||
// EIMSK: External Interrupt Mask Register
|
||||
EIMSK_INT = 0x7 // External Interrupt Request 2 Enable
|
||||
|
||||
// EIFR: External Interrupt Flag Register
|
||||
EIFR_INTF = 0x7 // External Interrupt Flags
|
||||
)
|
||||
|
||||
// Bitfields for ADC: Analog-to-Digital Converter
|
||||
const (
|
||||
// ADMUX: The ADC multiplexer Selection Register
|
||||
ADMUX_REFS = 0xc0 // Reference Selection Bits
|
||||
ADMUX_ADLAR = 0x20 // Left Adjust Result
|
||||
ADMUX_MUX = 0xf // Analog Channel and Gain Selection Bits
|
||||
|
||||
// ADCSRA: The ADC Control and Status register
|
||||
ADCSRA_ADEN = 0x80 // ADC Enable
|
||||
ADCSRA_ADSC = 0x40 // ADC Start Conversion
|
||||
ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable
|
||||
ADCSRA_ADIF = 0x10 // ADC Interrupt Flag
|
||||
ADCSRA_ADIE = 0x8 // ADC Interrupt Enable
|
||||
ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits
|
||||
|
||||
// ADCSRB: ADC Control and Status Register B
|
||||
ADCSRB_ADHSM = 0x80 // ADC High Speed Mode
|
||||
ADCSRB_ADNCDIS = 0x40 // ADC Noise Canceller Disable
|
||||
ADCSRB_ADSSEN = 0x10 // ADC Single Shot Enable on PSC's Synchronisation Signals
|
||||
ADCSRB_ADTS = 0xf // ADC Auto Trigger Sources
|
||||
|
||||
// DIDR0: Digital Input Disable Register 0
|
||||
DIDR0_ADC7D = 0x80
|
||||
DIDR0_ADC6D = 0x40 // ADC7 Digital input Disable
|
||||
DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable
|
||||
DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable
|
||||
DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable
|
||||
DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable
|
||||
DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable
|
||||
DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable
|
||||
|
||||
// DIDR1: Digital Input Disable Register 0
|
||||
DIDR1_ACMP1MD = 0x8
|
||||
DIDR1_AMP0POSD = 0x4
|
||||
DIDR1_ADC10D = 0x2
|
||||
DIDR1_ADC9D = 0x1
|
||||
|
||||
// AMP0CSR
|
||||
AMP0CSR_AMP0EN = 0x80
|
||||
AMP0CSR_AMP0IS = 0x40
|
||||
AMP0CSR_AMP0G = 0x30
|
||||
AMP0CSR_AMP0GS = 0x8
|
||||
AMP0CSR_AMP0TS = 0x3
|
||||
)
|
||||
|
||||
// Bitfields for AC: Analog Comparator
|
||||
const (
|
||||
// AC3CON: Analog Comparator3 Control Register
|
||||
AC3CON_AC3EN = 0x80 // Analog Comparator3 Enable Bit
|
||||
AC3CON_AC3IE = 0x40 // Analog Comparator 3 Interrupt Enable Bit
|
||||
AC3CON_AC3IS = 0x30 // Analog Comparator 3 Interrupt Select Bit
|
||||
AC3CON_AC3OEA = 0x8 // Analog Comparator 3 Alternate Output Enable
|
||||
AC3CON_AC3M = 0x7 // Analog Comparator 3 Multiplexer Register
|
||||
|
||||
// AC1CON: Analog Comparator 1 Control Register
|
||||
AC1CON_AC1EN = 0x80 // Analog Comparator 1 Enable Bit
|
||||
AC1CON_AC1IE = 0x40 // Analog Comparator 1 Interrupt Enable Bit
|
||||
AC1CON_AC1IS = 0x30 // Analog Comparator 1 Interrupt Select Bit
|
||||
AC1CON_AC1M = 0x7 // Analog Comparator 1 Multiplexer Register
|
||||
|
||||
// AC2CON: Analog Comparator 2 Control Register
|
||||
AC2CON_AC2EN = 0x80 // Analog Comparator 2 Enable Bit
|
||||
AC2CON_AC2IE = 0x40 // Analog Comparator 2 Interrupt Enable Bit
|
||||
AC2CON_AC2IS = 0x30 // Analog Comparator 2 Interrupt Select Bit
|
||||
AC2CON_AC2M = 0x7 // Analog Comparator 2 Multiplexer Register
|
||||
|
||||
// ACSR: Analog Comparator Status Register
|
||||
ACSR_AC3IF = 0x80 // Analog Comparator 3 Interrupt Flag Bit
|
||||
ACSR_AC2IF = 0x40 // Analog Comparator 2 Interrupt Flag Bit
|
||||
ACSR_AC1IF = 0x20 // Analog Comparator 1 Interrupt Flag Bit
|
||||
ACSR_AC3O = 0x8 // Analog Comparator 3 Output Bit
|
||||
ACSR_AC2O = 0x4 // Analog Comparator 2 Output Bit
|
||||
ACSR_AC1O = 0x2 // Analog Comparator 1 Output Bit
|
||||
|
||||
// AC3ECON
|
||||
AC3ECON_AC3OI = 0x20 // Analog Comparator Ouput Invert
|
||||
AC3ECON_AC3OE = 0x10 // Analog Comparator Ouput Enable
|
||||
AC3ECON_AC3H = 0x7 // Analog Comparator Hysteresis Select
|
||||
|
||||
// AC2ECON
|
||||
AC2ECON_AC2OI = 0x20 // Analog Comparator Ouput Invert
|
||||
AC2ECON_AC2OE = 0x10 // Analog Comparator Ouput Enable
|
||||
AC2ECON_AC2H = 0x7 // Analog Comparator Hysteresis Select
|
||||
|
||||
// AC1ECON
|
||||
AC1ECON_AC1OI = 0x20 // Analog Comparator Ouput Invert
|
||||
AC1ECON_AC1OE = 0x10 // Analog Comparator Ouput Enable
|
||||
AC1ECON_AC1ICE = 0x8 // Analog Comparator Interrupt Capture Enable
|
||||
AC1ECON_AC1H = 0x7 // Analog Comparator Hysteresis Select
|
||||
)
|
||||
|
||||
// Bitfields for CPU: CPU Registers
|
||||
const (
|
||||
// SREG: Status Register
|
||||
SREG_I = 0x80 // Global Interrupt Enable
|
||||
SREG_T = 0x40 // Bit Copy Storage
|
||||
SREG_H = 0x20 // Half Carry Flag
|
||||
SREG_S = 0x10 // Sign Bit
|
||||
SREG_V = 0x8 // Two's Complement Overflow Flag
|
||||
SREG_N = 0x4 // Negative Flag
|
||||
SREG_Z = 0x2 // Zero Flag
|
||||
SREG_C = 0x1 // Carry Flag
|
||||
|
||||
// MCUCR: MCU Control Register
|
||||
MCUCR_PUD = 0x10 // Pull-up disable
|
||||
MCUCR_RSTDIS = 0x8 // Reset Pin Disable
|
||||
MCUCR_CKRC81 = 0x4 // Frequency Selection of the Calibrated RC Oscillator
|
||||
MCUCR_IVSEL = 0x2 // Interrupt Vector Select
|
||||
MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable
|
||||
|
||||
// MCUSR: MCU Status Register
|
||||
MCUSR_WDRF = 0x8 // Watchdog Reset Flag
|
||||
MCUSR_BORF = 0x4 // Brown-out Reset Flag
|
||||
MCUSR_EXTRF = 0x2 // External Reset Flag
|
||||
MCUSR_PORF = 0x1 // Power-on reset flag
|
||||
|
||||
// OSCCAL: Oscillator Calibration Value
|
||||
OSCCAL_OSCCAL = 0xff // Oscillator Calibration
|
||||
|
||||
// CLKPR
|
||||
CLKPR_CLKPCE = 0x80
|
||||
CLKPR_CLKPS = 0xf
|
||||
|
||||
// SMCR: Sleep Mode Control Register
|
||||
SMCR_SM = 0xe // Sleep Mode Select bits
|
||||
SMCR_SE = 0x1 // Sleep Enable
|
||||
|
||||
// GPIOR2: General Purpose IO Register 2
|
||||
GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis
|
||||
|
||||
// GPIOR1: General Purpose IO Register 1
|
||||
GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis
|
||||
|
||||
// GPIOR0: General Purpose IO Register 0
|
||||
GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7
|
||||
GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6
|
||||
GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5
|
||||
GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4
|
||||
GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3
|
||||
GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2
|
||||
GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1
|
||||
GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0
|
||||
|
||||
// PLLCSR: PLL Control And Status Register
|
||||
PLLCSR_PLLF = 0x3c
|
||||
PLLCSR_PLLE = 0x2 // PLL Enable
|
||||
PLLCSR_PLOCK = 0x1 // PLL Lock Detector
|
||||
|
||||
// PRR: Power Reduction Register
|
||||
PRR_PRPSC2 = 0x80 // Power Reduction PSC2
|
||||
PRR_PRPSCR = 0x20 // Power Reduction PSC0
|
||||
PRR_PRTIM1 = 0x10 // Power Reduction Timer/Counter1
|
||||
PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface
|
||||
PRR_PRADC = 0x1 // Power Reduction ADC
|
||||
|
||||
// CLKCSR
|
||||
CLKCSR_CLKCCE = 0x80 // Clock Control Change Enable
|
||||
CLKCSR_CLKRDY = 0x10 // Clock Ready Flag
|
||||
CLKCSR_CLKC = 0xf // Clock Control
|
||||
|
||||
// CLKSELR
|
||||
CLKSELR_COUT = 0x40 // Clock OUT
|
||||
CLKSELR_CSUT = 0x30 // Clock Start up Time
|
||||
CLKSELR_CKSEL = 0xf // Clock Source Select
|
||||
|
||||
// BGCCR: BandGap Current Calibration Register
|
||||
BGCCR_BGCC = 0xf
|
||||
|
||||
// BGCRR: BandGap Resistor Calibration Register
|
||||
BGCRR_BGCR = 0xf
|
||||
)
|
||||
|
||||
// Bitfields for EEPROM: EEPROM
|
||||
const (
|
||||
// EECR: EEPROM Control Register
|
||||
EECR_NVMBSY = 0x80 // None Volatile Busy Memory Busy
|
||||
EECR_EEPAGE = 0x40 // EEPROM Page Access
|
||||
EECR_EEPM = 0x30 // EEPROM Programming Mode
|
||||
EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable
|
||||
EECR_EEMWE = 0x4 // EEPROM Master Write Enable
|
||||
EECR_EEWE = 0x2 // EEPROM Write Enable
|
||||
EECR_EERE = 0x1 // EEPROM Read Enable
|
||||
)
|
||||
|
||||
// Bitfields for PSC: Power Stage Controller
|
||||
const (
|
||||
// PFRC0B: PSC 0 Input B Control
|
||||
PFRC0B_PCAE0B = 0x80 // PSC 0 Capture Enable Input Part B
|
||||
PFRC0B_PISEL0B = 0x40 // PSC 0 Input Select for Part B
|
||||
PFRC0B_PELEV0B = 0x20 // PSC 0 Edge Level Selector on Input Part B
|
||||
PFRC0B_PFLTE0B = 0x10 // PSC 0 Filter Enable on Input Part B
|
||||
PFRC0B_PRFM0B = 0xf // PSC 0 Retrigger and Fault Mode for Part B
|
||||
|
||||
// PFRC0A: PSC 0 Input A Control
|
||||
PFRC0A_PCAE0A = 0x80 // PSC 0 Capture Enable Input Part A
|
||||
PFRC0A_PISEL0A = 0x40 // PSC 0 Input Select for Part A
|
||||
PFRC0A_PELEV0A = 0x20 // PSC 0 Edge Level Selector on Input Part A
|
||||
PFRC0A_PFLTE0A = 0x10 // PSC 0 Filter Enable on Input Part A
|
||||
PFRC0A_PRFM0A = 0xf // PSC 0 Retrigger and Fault Mode for Part A
|
||||
|
||||
// PCTL0: PSC 0 Control Register
|
||||
PCTL0_PPRE0 = 0xc0 // PSC 0 Prescaler Selects
|
||||
PCTL0_PBFM0 = 0x24 // PSC 0 Balance Flank Width Modulation
|
||||
PCTL0_PAOC0B = 0x10 // PSC 0 Asynchronous Output Control B
|
||||
PCTL0_PAOC0A = 0x8 // PSC 0 Asynchronous Output Control A
|
||||
PCTL0_PCCYC0 = 0x2 // PSC0 Complete Cycle
|
||||
PCTL0_PRUN0 = 0x1 // PSC 0 Run
|
||||
|
||||
// PCNF0: PSC 0 Configuration Register
|
||||
PCNF0_PFIFTY0 = 0x80 // PSC 0 Fifty
|
||||
PCNF0_PALOCK0 = 0x40 // PSC 0 Autolock
|
||||
PCNF0_PLOCK0 = 0x20 // PSC 0 Lock
|
||||
PCNF0_PMODE0 = 0x18 // PSC 0 Mode
|
||||
PCNF0_POP0 = 0x4 // PSC 0 Output Polarity
|
||||
PCNF0_PCLKSEL0 = 0x2 // PSC 0 Input Clock Select
|
||||
|
||||
// PSOC0: PSC0 Synchro and Output Configuration
|
||||
PSOC0_PISEL0A1 = 0x80 // PSC Input Select
|
||||
PSOC0_PISEL0B1 = 0x40 // PSC Input Select
|
||||
PSOC0_PSYNC0 = 0x30 // Synchronisation out for ADC selection
|
||||
PSOC0_POEN0B = 0x4 // PSCOUT01 Output Enable
|
||||
PSOC0_POEN0A = 0x1 // PSCOUT00 Output Enable
|
||||
|
||||
// PIM0: PSC0 Interrupt Mask Register
|
||||
PIM0_PEVE0B = 0x10 // External Event B Interrupt Enable
|
||||
PIM0_PEVE0A = 0x8 // External Event A Interrupt Enable
|
||||
PIM0_PEOEPE0 = 0x2 // End of Enhanced Cycle Enable
|
||||
PIM0_PEOPE0 = 0x1 // End of Cycle Interrupt Enable
|
||||
|
||||
// PIFR0: PSC0 Interrupt Flag Register
|
||||
PIFR0_POAC0B = 0x80 // PSC 0 Output A Activity
|
||||
PIFR0_POAC0A = 0x40 // PSC 0 Output A Activity
|
||||
PIFR0_PEV0B = 0x10 // External Event B Interrupt
|
||||
PIFR0_PEV0A = 0x8 // External Event A Interrupt
|
||||
PIFR0_PRN0 = 0x6 // Ramp Number
|
||||
PIFR0_PEOP0 = 0x1 // End of PSC0 Interrupt
|
||||
|
||||
// PICR2H: PSC 2 Input Capture Register High
|
||||
PICR2H_PCST2 = 0x80 // PSC 2 Capture Software Trigger Bit
|
||||
PICR2H_PICR21 = 0xc
|
||||
PICR2H_PICR2 = 0x3
|
||||
|
||||
// PFRC2B: PSC 2 Input B Control
|
||||
PFRC2B_PCAE2B = 0x80 // PSC 2 Capture Enable Input Part B
|
||||
PFRC2B_PISEL2B = 0x40 // PSC 2 Input Select for Part B
|
||||
PFRC2B_PELEV2B = 0x20 // PSC 2 Edge Level Selector on Input Part B
|
||||
PFRC2B_PFLTE2B = 0x10 // PSC 2 Filter Enable on Input Part B
|
||||
PFRC2B_PRFM2B = 0xf // PSC 2 Retrigger and Fault Mode for Part B
|
||||
|
||||
// PFRC2A: PSC 2 Input B Control
|
||||
PFRC2A_PCAE2A = 0x80 // PSC 2 Capture Enable Input Part A
|
||||
PFRC2A_PISEL2A = 0x40 // PSC 2 Input Select for Part A
|
||||
PFRC2A_PELEV2A = 0x20 // PSC 2 Edge Level Selector on Input Part A
|
||||
PFRC2A_PFLTE2A = 0x10 // PSC 2 Filter Enable on Input Part A
|
||||
PFRC2A_PRFM2A = 0xf // PSC 2 Retrigger and Fault Mode for Part A
|
||||
|
||||
// PCTL2: PSC 2 Control Register
|
||||
PCTL2_PPRE2 = 0xc0 // PSC 2 Prescaler Selects
|
||||
PCTL2_PBFM2 = 0x20 // Balance Flank Width Modulation
|
||||
PCTL2_PAOC2B = 0x10 // PSC 2 Asynchronous Output Control B
|
||||
PCTL2_PAOC2A = 0x8 // PSC 2 Asynchronous Output Control A
|
||||
PCTL2_PARUN2 = 0x4 // PSC2 Auto Run
|
||||
PCTL2_PCCYC2 = 0x2 // PSC2 Complete Cycle
|
||||
PCTL2_PRUN2 = 0x1 // PSC 2 Run
|
||||
|
||||
// PCNF2: PSC 2 Configuration Register
|
||||
PCNF2_PFIFTY2 = 0x80 // PSC 2 Fifty
|
||||
PCNF2_PALOCK2 = 0x40 // PSC 2 Autolock
|
||||
PCNF2_PLOCK2 = 0x20 // PSC 2 Lock
|
||||
PCNF2_PMODE2 = 0x18 // PSC 2 Mode
|
||||
PCNF2_POP2 = 0x4 // PSC 2 Output Polarity
|
||||
PCNF2_PCLKSEL2 = 0x2 // PSC 2 Input Clock Select
|
||||
PCNF2_POME2 = 0x1 // PSC 2 Output Matrix Enable
|
||||
|
||||
// PCNFE2: PSC 2 Enhanced Configuration Register
|
||||
PCNFE2_PASDLK2 = 0xe0
|
||||
PCNFE2_PBFM21 = 0x10
|
||||
PCNFE2_PELEV2A1 = 0x8
|
||||
PCNFE2_PELEV2B1 = 0x4
|
||||
PCNFE2_PISEL2A1 = 0x2
|
||||
PCNFE2_PISEL2B1 = 0x1
|
||||
|
||||
// POM2: PSC 2 Output Matrix
|
||||
POM2_POMV2B = 0xf0 // Output Matrix Output B Ramps
|
||||
POM2_POMV2A = 0xf // Output Matrix Output A Ramps
|
||||
|
||||
// PSOC2: PSC2 Synchro and Output Configuration
|
||||
PSOC2_POS2 = 0xc0 // PSC 2 Output 23 Select
|
||||
PSOC2_PSYNC2 = 0x30 // Synchronization Out for ADC Selection
|
||||
PSOC2_POEN2D = 0x8 // PSCOUT23 Output Enable
|
||||
PSOC2_POEN2B = 0x4 // PSCOUT21 Output Enable
|
||||
PSOC2_POEN2C = 0x2 // PSCOUT22 Output Enable
|
||||
PSOC2_POEN2A = 0x1 // PSCOUT20 Output Enable
|
||||
|
||||
// PIM2: PSC2 Interrupt Mask Register
|
||||
PIM2_PSEIE2 = 0x20 // PSC 2 Synchro Error Interrupt Enable
|
||||
PIM2_PEVE2B = 0x10 // External Event B Interrupt Enable
|
||||
PIM2_PEVE2A = 0x8 // External Event A Interrupt Enable
|
||||
PIM2_PEOEPE2 = 0x2 // End of Enhanced Cycle Interrupt Enable
|
||||
PIM2_PEOPE2 = 0x1 // End of Cycle Interrupt Enable
|
||||
|
||||
// PIFR2: PSC2 Interrupt Flag Register
|
||||
PIFR2_POAC2B = 0x80 // PSC 2 Output A Activity
|
||||
PIFR2_POAC2A = 0x40 // PSC 2 Output A Activity
|
||||
PIFR2_PSEI2 = 0x20 // PSC 2 Synchro Error Interrupt
|
||||
PIFR2_PEV2B = 0x10 // External Event B Interrupt
|
||||
PIFR2_PEV2A = 0x8 // External Event A Interrupt
|
||||
PIFR2_PRN2 = 0x6 // Ramp Number
|
||||
PIFR2_PEOP2 = 0x1 // End of PSC2 Interrupt
|
||||
)
|
||||
|
||||
// Bitfields for TC16: Timer/Counter, 16-bit
|
||||
const (
|
||||
// TIMSK1: Timer/Counter Interrupt Mask Register
|
||||
TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable
|
||||
TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable
|
||||
|
||||
// TIFR1: Timer/Counter Interrupt Flag register
|
||||
TIFR1_ICF1 = 0x20 // Input Capture Flag 1
|
||||
TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag
|
||||
|
||||
// TCCR1B: Timer/Counter1 Control Register B
|
||||
TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler
|
||||
TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select
|
||||
TCCR1B_WGM13 = 0x10 // Waveform Generation Mode
|
||||
TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1
|
||||
)
|
||||
|
||||
// Bitfields for BOOT_LOAD: Bootloader
|
||||
const (
|
||||
// SPMCSR: Store Program Memory Control Register
|
||||
SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable
|
||||
SPMCSR_RWWSB = 0x40 // Read While Write Section Busy
|
||||
SPMCSR_SIGRD = 0x20 // Signature Row Read
|
||||
SPMCSR_RWWSRE = 0x10 // Read While Write section read enable
|
||||
SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set
|
||||
SPMCSR_PGWRT = 0x4 // Page Write
|
||||
SPMCSR_PGERS = 0x2 // Page Erase
|
||||
SPMCSR_SPMEN = 0x1 // Store Program Memory Enable
|
||||
)
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from AT90PWM161.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x4000;
|
||||
__ram_size = 0x400;
|
||||
__num_isrs = 20;
|
||||
|
|
@ -1,934 +0,0 @@
|
|||
// Automatically generated file. DO NOT EDIT.
|
||||
// Generated by gen-device.py from AT90PWM216.atdf, see http://packs.download.atmel.com/
|
||||
|
||||
// +build avr,at90pwm216
|
||||
|
||||
// Device information for the AT90PWM216.
|
||||
//
|
||||
package avr
|
||||
|
||||
// Magic type name for the compiler.
|
||||
type __reg uint8
|
||||
|
||||
// Export this magic type name.
|
||||
type RegValue = __reg
|
||||
|
||||
// Some information about this device.
|
||||
const (
|
||||
DEVICE = "AT90PWM216"
|
||||
ARCH = "AVR8"
|
||||
FAMILY = "megaAVR"
|
||||
)
|
||||
|
||||
// Interrupts
|
||||
const (
|
||||
IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset
|
||||
IRQ_PSC2_CAPT = 1 // PSC2 Capture Event
|
||||
IRQ_PSC2_EC = 2 // PSC2 End Cycle
|
||||
IRQ_PSC1_CAPT = 3 // PSC1 Capture Event
|
||||
IRQ_PSC1_EC = 4 // PSC1 End Cycle
|
||||
IRQ_PSC0_CAPT = 5 // PSC0 Capture Event
|
||||
IRQ_PSC0_EC = 6 // PSC0 End Cycle
|
||||
IRQ_ANALOG_COMP_0 = 7 // Analog Comparator 0
|
||||
IRQ_ANALOG_COMP_1 = 8 // Analog Comparator 1
|
||||
IRQ_ANALOG_COMP_2 = 9 // Analog Comparator 2
|
||||
IRQ_INT0 = 10 // External Interrupt Request 0
|
||||
IRQ_TIMER1_CAPT = 11 // Timer/Counter1 Capture Event
|
||||
IRQ_TIMER1_COMPA = 12 // Timer/Counter1 Compare Match A
|
||||
IRQ_TIMER1_COMPB = 13 // Timer/Counter Compare Match B
|
||||
IRQ_RESERVED15 = 14 //
|
||||
IRQ_TIMER1_OVF = 15 // Timer/Counter1 Overflow
|
||||
IRQ_TIMER0_COMP_A = 16 // Timer/Counter0 Compare Match A
|
||||
IRQ_TIMER0_OVF = 17 // Timer/Counter0 Overflow
|
||||
IRQ_ADC = 18 // ADC Conversion Complete
|
||||
IRQ_INT1 = 19 // External Interrupt Request 1
|
||||
IRQ_SPI_STC = 20 // SPI Serial Transfer Complete
|
||||
IRQ_USART_RX = 21 // USART, Rx Complete
|
||||
IRQ_USART_UDRE = 22 // USART Data Register Empty
|
||||
IRQ_USART_TX = 23 // USART, Tx Complete
|
||||
IRQ_INT2 = 24 // External Interrupt Request 2
|
||||
IRQ_WDT = 25 // Watchdog Timeout Interrupt
|
||||
IRQ_EE_READY = 26 // EEPROM Ready
|
||||
IRQ_TIMER0_COMPB = 27 // Timer Counter 0 Compare Match B
|
||||
IRQ_INT3 = 28 // External Interrupt Request 3
|
||||
IRQ_RESERVED30 = 29 //
|
||||
IRQ_RESERVED31 = 30 //
|
||||
IRQ_SPM_READY = 31 // Store Program Memory Read
|
||||
IRQ_max = 31 // Highest interrupt number on this device.
|
||||
)
|
||||
|
||||
// Peripherals
|
||||
var (
|
||||
// Fuses
|
||||
FUSE = struct {
|
||||
EXTENDED __reg
|
||||
HIGH __reg
|
||||
LOW __reg
|
||||
}{
|
||||
EXTENDED: 0x2,
|
||||
HIGH: 0x1,
|
||||
LOW: 0x0,
|
||||
}
|
||||
|
||||
// Lockbits
|
||||
LOCKBIT = struct {
|
||||
LOCKBIT __reg
|
||||
}{
|
||||
LOCKBIT: 0x0,
|
||||
}
|
||||
|
||||
// I/O Port
|
||||
PORT = struct {
|
||||
PORTB __reg
|
||||
DDRB __reg
|
||||
PINB __reg
|
||||
PORTD __reg
|
||||
DDRD __reg
|
||||
PIND __reg
|
||||
PORTE __reg
|
||||
DDRE __reg
|
||||
PINE __reg
|
||||
}{
|
||||
PORTB: 0x25, // Port B Data Register
|
||||
DDRB: 0x24, // Port B Data Direction Register
|
||||
PINB: 0x23, // Port B Input Pins
|
||||
PORTD: 0x2b, // Port D Data Register
|
||||
DDRD: 0x2a, // Port D Data Direction Register
|
||||
PIND: 0x29, // Port D Input Pins
|
||||
PORTE: 0x2e, // Port E Data Register
|
||||
DDRE: 0x2d, // Port E Data Direction Register
|
||||
PINE: 0x2c, // Port E Input Pins
|
||||
}
|
||||
|
||||
// Bootloader
|
||||
BOOT_LOAD = struct {
|
||||
SPMCSR __reg
|
||||
}{
|
||||
SPMCSR: 0x57, // Store Program Memory Control Register
|
||||
}
|
||||
|
||||
// Extended USART
|
||||
EUSART = struct {
|
||||
EUDR __reg
|
||||
EUCSRA __reg
|
||||
EUCSRB __reg
|
||||
EUCSRC __reg
|
||||
MUBRRH __reg
|
||||
MUBRRL __reg
|
||||
}{
|
||||
EUDR: 0xce, // EUSART I/O Data Register
|
||||
EUCSRA: 0xc8, // EUSART Control and Status Register A
|
||||
EUCSRB: 0xc9, // EUSART Control Register B
|
||||
EUCSRC: 0xca, // EUSART Status Register C
|
||||
MUBRRH: 0xcd, // Manchester Receiver Baud Rate Register High Byte
|
||||
MUBRRL: 0xcc, // Manchester Receiver Baud Rate Register Low Byte
|
||||
}
|
||||
|
||||
// Analog Comparator
|
||||
AC = struct {
|
||||
AC0CON __reg
|
||||
AC1CON __reg
|
||||
AC2CON __reg
|
||||
ACSR __reg
|
||||
}{
|
||||
AC0CON: 0xad, // Analog Comparator 0 Control Register
|
||||
AC1CON: 0xae, // Analog Comparator 1 Control Register
|
||||
AC2CON: 0xaf, // Analog Comparator 2 Control Register
|
||||
ACSR: 0x50, // Analog Comparator Status Register
|
||||
}
|
||||
|
||||
// Digital-to-Analog Converter
|
||||
DAC = struct {
|
||||
DACL __reg
|
||||
DACH __reg
|
||||
DACON __reg
|
||||
}{
|
||||
DACL: 0xab, // DAC Data Register Bytes
|
||||
DACH: 0xab, // DAC Data Register Bytes
|
||||
DACON: 0xaa, // DAC Control Register
|
||||
}
|
||||
|
||||
// CPU Registers
|
||||
CPU = struct {
|
||||
SREG __reg
|
||||
SPL __reg
|
||||
SPH __reg
|
||||
MCUCR __reg
|
||||
MCUSR __reg
|
||||
OSCCAL __reg
|
||||
CLKPR __reg
|
||||
SMCR __reg
|
||||
GPIOR3 __reg
|
||||
GPIOR2 __reg
|
||||
GPIOR1 __reg
|
||||
GPIOR0 __reg
|
||||
PLLCSR __reg
|
||||
PRR __reg
|
||||
}{
|
||||
SREG: 0x5f, // Status Register
|
||||
SPL: 0x5d, // Stack Pointer
|
||||
SPH: 0x5d, // Stack Pointer
|
||||
MCUCR: 0x55, // MCU Control Register
|
||||
MCUSR: 0x54, // MCU Status Register
|
||||
OSCCAL: 0x66, // Oscillator Calibration Value
|
||||
CLKPR: 0x61,
|
||||
SMCR: 0x53, // Sleep Mode Control Register
|
||||
GPIOR3: 0x3b, // General Purpose IO Register 3
|
||||
GPIOR2: 0x3a, // General Purpose IO Register 2
|
||||
GPIOR1: 0x39, // General Purpose IO Register 1
|
||||
GPIOR0: 0x3e, // General Purpose IO Register 0
|
||||
PLLCSR: 0x49, // PLL Control And Status Register
|
||||
PRR: 0x64, // Power Reduction Register
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit
|
||||
TC8 = struct {
|
||||
TIMSK0 __reg
|
||||
TIFR0 __reg
|
||||
TCCR0A __reg
|
||||
TCCR0B __reg
|
||||
TCNT0 __reg
|
||||
OCR0A __reg
|
||||
OCR0B __reg
|
||||
}{
|
||||
TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register
|
||||
TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register
|
||||
TCCR0A: 0x44, // Timer/Counter Control Register A
|
||||
TCCR0B: 0x45, // Timer/Counter Control Register B
|
||||
TCNT0: 0x46, // Timer/Counter0
|
||||
OCR0A: 0x47, // Timer/Counter0 Output Compare Register
|
||||
OCR0B: 0x48, // Timer/Counter0 Output Compare Register
|
||||
}
|
||||
|
||||
// Timer/Counter, 16-bit
|
||||
TC16 = struct {
|
||||
TIMSK1 __reg
|
||||
TIFR1 __reg
|
||||
TCCR1A __reg
|
||||
TCCR1B __reg
|
||||
TCCR1C __reg
|
||||
TCNT1L __reg
|
||||
TCNT1H __reg
|
||||
OCR1AL __reg
|
||||
OCR1AH __reg
|
||||
OCR1BL __reg
|
||||
OCR1BH __reg
|
||||
ICR1L __reg
|
||||
ICR1H __reg
|
||||
}{
|
||||
TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register
|
||||
TIFR1: 0x36, // Timer/Counter Interrupt Flag register
|
||||
TCCR1A: 0x80, // Timer/Counter1 Control Register A
|
||||
TCCR1B: 0x81, // Timer/Counter1 Control Register B
|
||||
TCCR1C: 0x82, // Timer/Counter1 Control Register C
|
||||
TCNT1L: 0x84, // Timer/Counter1 Bytes
|
||||
TCNT1H: 0x84, // Timer/Counter1 Bytes
|
||||
OCR1AL: 0x88, // Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1AH: 0x88, // Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register Bytes
|
||||
ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
}
|
||||
|
||||
// Analog-to-Digital Converter
|
||||
ADC = struct {
|
||||
ADMUX __reg
|
||||
ADCSRA __reg
|
||||
ADCL __reg
|
||||
ADCH __reg
|
||||
ADCSRB __reg
|
||||
DIDR0 __reg
|
||||
DIDR1 __reg
|
||||
AMP0CSR __reg
|
||||
AMP1CSR __reg
|
||||
}{
|
||||
ADMUX: 0x7c, // The ADC multiplexer Selection Register
|
||||
ADCSRA: 0x7a, // The ADC Control and Status register
|
||||
ADCL: 0x78, // ADC Data Register Bytes
|
||||
ADCH: 0x78, // ADC Data Register Bytes
|
||||
ADCSRB: 0x7b, // ADC Control and Status Register B
|
||||
DIDR0: 0x7e, // Digital Input Disable Register 0
|
||||
DIDR1: 0x7f, // Digital Input Disable Register 1
|
||||
AMP0CSR: 0x76,
|
||||
AMP1CSR: 0x77,
|
||||
}
|
||||
|
||||
// USART
|
||||
USART = struct {
|
||||
UDR __reg
|
||||
UCSRA __reg
|
||||
UCSRB __reg
|
||||
UCSRC __reg
|
||||
UBRRH __reg
|
||||
UBRRL __reg
|
||||
}{
|
||||
UDR: 0xc6, // USART I/O Data Register
|
||||
UCSRA: 0xc0, // USART Control and Status register A
|
||||
UCSRB: 0xc1, // USART Control an Status register B
|
||||
UCSRC: 0xc2, // USART Control an Status register C
|
||||
UBRRH: 0xc5, // USART Baud Rate Register High Byte
|
||||
UBRRL: 0xc4, // USART Baud Rate Register Low Byte
|
||||
}
|
||||
|
||||
// Serial Peripheral Interface
|
||||
SPI = struct {
|
||||
SPCR __reg
|
||||
SPSR __reg
|
||||
SPDR __reg
|
||||
}{
|
||||
SPCR: 0x4c, // SPI Control Register
|
||||
SPSR: 0x4d, // SPI Status Register
|
||||
SPDR: 0x4e, // SPI Data Register
|
||||
}
|
||||
|
||||
// Watchdog Timer
|
||||
WDT = struct {
|
||||
WDTCSR __reg
|
||||
}{
|
||||
WDTCSR: 0x60, // Watchdog Timer Control Register
|
||||
}
|
||||
|
||||
// External Interrupts
|
||||
EXINT = struct {
|
||||
EICRA __reg
|
||||
EIMSK __reg
|
||||
EIFR __reg
|
||||
}{
|
||||
EICRA: 0x69, // External Interrupt Control Register A
|
||||
EIMSK: 0x3d, // External Interrupt Mask Register
|
||||
EIFR: 0x3c, // External Interrupt Flag Register
|
||||
}
|
||||
|
||||
// EEPROM
|
||||
EEPROM = struct {
|
||||
EEARL __reg
|
||||
EEARH __reg
|
||||
EEDR __reg
|
||||
EECR __reg
|
||||
}{
|
||||
EEARL: 0x41, // EEPROM Read/Write Access Bytes
|
||||
EEARH: 0x41, // EEPROM Read/Write Access Bytes
|
||||
EEDR: 0x40, // EEPROM Data Register
|
||||
EECR: 0x3f, // EEPROM Control Register
|
||||
}
|
||||
|
||||
// Power Stage Controller
|
||||
PSC = struct {
|
||||
PICR0L __reg
|
||||
PICR0H __reg
|
||||
PFRC0B __reg
|
||||
PFRC0A __reg
|
||||
PCTL0 __reg
|
||||
PCNF0 __reg
|
||||
OCR0RBL __reg
|
||||
OCR0RBH __reg
|
||||
OCR0SBL __reg
|
||||
OCR0SBH __reg
|
||||
OCR0RAL __reg
|
||||
OCR0RAH __reg
|
||||
OCR0SAL __reg
|
||||
OCR0SAH __reg
|
||||
PSOC0 __reg
|
||||
PIM0 __reg
|
||||
PIFR0 __reg
|
||||
PICR2L __reg
|
||||
PICR2H __reg
|
||||
PFRC2B __reg
|
||||
PFRC2A __reg
|
||||
PCTL2 __reg
|
||||
PCNF2 __reg
|
||||
OCR2RBL __reg
|
||||
OCR2RBH __reg
|
||||
OCR2SBL __reg
|
||||
OCR2SBH __reg
|
||||
OCR2RAL __reg
|
||||
OCR2RAH __reg
|
||||
OCR2SAL __reg
|
||||
OCR2SAH __reg
|
||||
POM2 __reg
|
||||
PSOC2 __reg
|
||||
PIM2 __reg
|
||||
PIFR2 __reg
|
||||
}{
|
||||
PICR0L: 0xde, // PSC 0 Input Capture Register
|
||||
PICR0H: 0xde, // PSC 0 Input Capture Register
|
||||
PFRC0B: 0xdd, // PSC 0 Input B Control
|
||||
PFRC0A: 0xdc, // PSC 0 Input A Control
|
||||
PCTL0: 0xdb, // PSC 0 Control Register
|
||||
PCNF0: 0xda, // PSC 0 Configuration Register
|
||||
OCR0RBL: 0xd8, // Output Compare RB Register
|
||||
OCR0RBH: 0xd8, // Output Compare RB Register
|
||||
OCR0SBL: 0xd6, // Output Compare SB Register
|
||||
OCR0SBH: 0xd6, // Output Compare SB Register
|
||||
OCR0RAL: 0xd4, // Output Compare RA Register
|
||||
OCR0RAH: 0xd4, // Output Compare RA Register
|
||||
OCR0SAL: 0xd2, // Output Compare SA Register
|
||||
OCR0SAH: 0xd2, // Output Compare SA Register
|
||||
PSOC0: 0xd0, // PSC0 Synchro and Output Configuration
|
||||
PIM0: 0xa1, // PSC0 Interrupt Mask Register
|
||||
PIFR0: 0xa0, // PSC0 Interrupt Flag Register
|
||||
PICR2L: 0xfe, // PSC 2 Input Capture Register
|
||||
PICR2H: 0xfe, // PSC 2 Input Capture Register
|
||||
PFRC2B: 0xfd, // PSC 2 Input B Control
|
||||
PFRC2A: 0xfc, // PSC 2 Input B Control
|
||||
PCTL2: 0xfb, // PSC 2 Control Register
|
||||
PCNF2: 0xfa, // PSC 2 Configuration Register
|
||||
OCR2RBL: 0xf8, // Output Compare RB Register
|
||||
OCR2RBH: 0xf8, // Output Compare RB Register
|
||||
OCR2SBL: 0xf6, // Output Compare SB Register
|
||||
OCR2SBH: 0xf6, // Output Compare SB Register
|
||||
OCR2RAL: 0xf4, // Output Compare RA Register
|
||||
OCR2RAH: 0xf4, // Output Compare RA Register
|
||||
OCR2SAL: 0xf2, // Output Compare SA Register
|
||||
OCR2SAH: 0xf2, // Output Compare SA Register
|
||||
POM2: 0xf1, // PSC 2 Output Matrix
|
||||
PSOC2: 0xf0, // PSC2 Synchro and Output Configuration
|
||||
PIM2: 0xa5, // PSC2 Interrupt Mask Register
|
||||
PIFR2: 0xa4, // PSC2 Interrupt Flag Register
|
||||
}
|
||||
)
|
||||
|
||||
// Bitfields for FUSE: Fuses
|
||||
const (
|
||||
// EXTENDED
|
||||
EXTENDED_PSC2RB = 0x80 // PSC2 Reset Behavior
|
||||
EXTENDED_PSC1RB = 0x40 // PSC1 Reset Behavior
|
||||
EXTENDED_PSC0RB = 0x20 // PSC0 Reset Behavior
|
||||
EXTENDED_PSCRV = 0x10 // PSCOUT Reset Value
|
||||
EXTENDED_BOOTSZ = 0x6 // Select Boot Size
|
||||
EXTENDED_BOOTRST = 0x1 // Select Reset Vector
|
||||
|
||||
// HIGH
|
||||
HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PC6 as i/o pin)
|
||||
HIGH_DWEN = 0x40 // Debug Wire enable
|
||||
HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled
|
||||
HIGH_WDTON = 0x10 // Watch-dog Timer always on
|
||||
HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle
|
||||
HIGH_BODLEVEL = 0x7 // Brown-out Detector Trigger Level
|
||||
|
||||
// LOW
|
||||
LOW_CKDIV8 = 0x80 // Divide clock by 8 internally
|
||||
LOW_CKOUT = 0x40 // Clock output on PORTB0
|
||||
LOW_SUT_CKSEL = 0x3f // Select Clock Source
|
||||
)
|
||||
|
||||
// Bitfields for LOCKBIT: Lockbits
|
||||
const (
|
||||
// LOCKBIT
|
||||
LOCKBIT_LB = 0x3 // Memory Lock
|
||||
LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode
|
||||
LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode
|
||||
)
|
||||
|
||||
// Bitfields for BOOT_LOAD: Bootloader
|
||||
const (
|
||||
// SPMCSR: Store Program Memory Control Register
|
||||
SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable
|
||||
SPMCSR_RWWSB = 0x40 // Read While Write Section Busy
|
||||
SPMCSR_RWWSRE = 0x10 // Read While Write section read enable
|
||||
SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set
|
||||
SPMCSR_PGWRT = 0x4 // Page Write
|
||||
SPMCSR_PGERS = 0x2 // Page Erase
|
||||
SPMCSR_SPMEN = 0x1 // Store Program Memory Enable
|
||||
)
|
||||
|
||||
// Bitfields for EUSART: Extended USART
|
||||
const (
|
||||
// EUCSRA: EUSART Control and Status Register A
|
||||
EUCSRA_UTxS = 0xf0 // EUSART Control and Status Register A Bits
|
||||
EUCSRA_URxS = 0xf // EUSART Control and Status Register A Bits
|
||||
|
||||
// EUCSRB: EUSART Control Register B
|
||||
EUCSRB_EUSART = 0x10 // EUSART Enable Bit
|
||||
EUCSRB_EUSBS = 0x8 // EUSBS Enable Bit
|
||||
EUCSRB_EMCH = 0x2 // Manchester Mode Bit
|
||||
EUCSRB_BODR = 0x1 // Order Bit
|
||||
|
||||
// EUCSRC: EUSART Status Register C
|
||||
EUCSRC_FEM = 0x8 // Frame Error Manchester Bit
|
||||
EUCSRC_F1617 = 0x4 // F1617 Bit
|
||||
EUCSRC_STP = 0x3 // Stop Bits
|
||||
|
||||
// MUBRRH: Manchester Receiver Baud Rate Register High Byte
|
||||
MUBRRH_MUBRR = 0xff // Manchester Receiver Baud Rate Register Bits
|
||||
|
||||
// MUBRRL: Manchester Receiver Baud Rate Register Low Byte
|
||||
MUBRRL_MUBRR = 0xff // Manchester Receiver Baud Rate Register Bits
|
||||
)
|
||||
|
||||
// Bitfields for AC: Analog Comparator
|
||||
const (
|
||||
// AC0CON: Analog Comparator 0 Control Register
|
||||
AC0CON_AC0EN = 0x80 // Analog Comparator 0 Enable Bit
|
||||
AC0CON_AC0IE = 0x40 // Analog Comparator 0 Interrupt Enable Bit
|
||||
AC0CON_AC0IS = 0x30 // Analog Comparator 0 Interrupt Select Bit
|
||||
AC0CON_AC0M = 0x7 // Analog Comparator 0 Multiplexer Register
|
||||
|
||||
// AC1CON: Analog Comparator 1 Control Register
|
||||
AC1CON_AC1EN = 0x80 // Analog Comparator 1 Enable Bit
|
||||
AC1CON_AC1IE = 0x40 // Analog Comparator 1 Interrupt Enable Bit
|
||||
AC1CON_AC1IS = 0x30 // Analog Comparator 1 Interrupt Select Bit
|
||||
AC1CON_AC1ICE = 0x8 // Analog Comparator 1 Interrupt Capture Enable Bit
|
||||
AC1CON_AC1M = 0x7 // Analog Comparator 1 Multiplexer Register
|
||||
|
||||
// AC2CON: Analog Comparator 2 Control Register
|
||||
AC2CON_AC2EN = 0x80 // Analog Comparator 2 Enable Bit
|
||||
AC2CON_AC2IE = 0x40 // Analog Comparator 2 Interrupt Enable Bit
|
||||
AC2CON_AC2IS = 0x30 // Analog Comparator 2 Interrupt Select Bit
|
||||
AC2CON_AC2M = 0x7 // Analog Comparator 2 Multiplexer Register
|
||||
|
||||
// ACSR: Analog Comparator Status Register
|
||||
ACSR_ACCKDIV = 0x80 // Analog Comparator Clock Divider
|
||||
ACSR_AC2IF = 0x40 // Analog Comparator 2 Interrupt Flag Bit
|
||||
ACSR_AC1IF = 0x20 // Analog Comparator 1 Interrupt Flag Bit
|
||||
ACSR_AC0IF = 0x10 // Analog Comparator 0 Interrupt Flag Bit
|
||||
ACSR_AC2O = 0x4 // Analog Comparator 2 Output Bit
|
||||
ACSR_AC1O = 0x2 // Analog Comparator 1 Output Bit
|
||||
ACSR_AC0O = 0x1 // Analog Comparator 0 Output Bit
|
||||
)
|
||||
|
||||
// Bitfields for DAC: Digital-to-Analog Converter
|
||||
const (
|
||||
// DACL: DAC Data Register Bytes
|
||||
|
||||
// DACH: DAC Data Register Bytes
|
||||
DAC_DAC = 0xffff // DAC Data Register Bits
|
||||
|
||||
// DACON: DAC Control Register
|
||||
DACON_DAATE = 0x80 // DAC Auto Trigger Enable Bit
|
||||
DACON_DATS = 0x70 // DAC Trigger Selection Bits
|
||||
DACON_DALA = 0x4 // DAC Left Adjust
|
||||
DACON_DAOE = 0x2 // DAC Output Enable
|
||||
DACON_DAEN = 0x1 // DAC Enable Bit
|
||||
)
|
||||
|
||||
// Bitfields for CPU: CPU Registers
|
||||
const (
|
||||
// SREG: Status Register
|
||||
SREG_I = 0x80 // Global Interrupt Enable
|
||||
SREG_T = 0x40 // Bit Copy Storage
|
||||
SREG_H = 0x20 // Half Carry Flag
|
||||
SREG_S = 0x10 // Sign Bit
|
||||
SREG_V = 0x8 // Two's Complement Overflow Flag
|
||||
SREG_N = 0x4 // Negative Flag
|
||||
SREG_Z = 0x2 // Zero Flag
|
||||
SREG_C = 0x1 // Carry Flag
|
||||
|
||||
// MCUCR: MCU Control Register
|
||||
MCUCR_SPIPS = 0x80 // SPI Pin Select
|
||||
MCUCR_PUD = 0x10 // Pull-up disable
|
||||
MCUCR_IVSEL = 0x2 // Interrupt Vector Select
|
||||
MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable
|
||||
|
||||
// MCUSR: MCU Status Register
|
||||
MCUSR_WDRF = 0x8 // Watchdog Reset Flag
|
||||
MCUSR_BORF = 0x4 // Brown-out Reset Flag
|
||||
MCUSR_EXTRF = 0x2 // External Reset Flag
|
||||
MCUSR_PORF = 0x1 // Power-on reset flag
|
||||
|
||||
// OSCCAL: Oscillator Calibration Value
|
||||
OSCCAL_OSCCAL = 0xff // Oscillator Calibration
|
||||
|
||||
// CLKPR
|
||||
CLKPR_CLKPCE = 0x80
|
||||
CLKPR_CLKPS = 0xf
|
||||
|
||||
// SMCR: Sleep Mode Control Register
|
||||
SMCR_SM = 0xe // Sleep Mode Select bits
|
||||
SMCR_SE = 0x1 // Sleep Enable
|
||||
|
||||
// GPIOR3: General Purpose IO Register 3
|
||||
GPIOR3_GPIOR = 0xff // General Purpose IO Register 3 bis
|
||||
|
||||
// GPIOR2: General Purpose IO Register 2
|
||||
GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis
|
||||
|
||||
// GPIOR1: General Purpose IO Register 1
|
||||
GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis
|
||||
|
||||
// GPIOR0: General Purpose IO Register 0
|
||||
GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7
|
||||
GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6
|
||||
GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5
|
||||
GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4
|
||||
GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3
|
||||
GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2
|
||||
GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1
|
||||
GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0
|
||||
|
||||
// PLLCSR: PLL Control And Status Register
|
||||
PLLCSR_PLLF = 0x4 // PLL Factor
|
||||
PLLCSR_PLLE = 0x2 // PLL Enable
|
||||
PLLCSR_PLOCK = 0x1 // PLL Lock Detector
|
||||
|
||||
// PRR: Power Reduction Register
|
||||
PRR_PRPSC2 = 0x80 // Power Reduction PSC2
|
||||
PRR_PRPSC1 = 0x40 // Power Reduction PSC1
|
||||
PRR_PRPSC0 = 0x20 // Power Reduction PSC0
|
||||
PRR_PRTIM1 = 0x10 // Power Reduction Timer/Counter1
|
||||
PRR_PRTIM0 = 0x8 // Power Reduction Timer/Counter0
|
||||
PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface
|
||||
PRR_PRUSART0 = 0x2 // Power Reduction USART
|
||||
PRR_PRADC = 0x1 // Power Reduction ADC
|
||||
)
|
||||
|
||||
// Bitfields for TC8: Timer/Counter, 8-bit
|
||||
const (
|
||||
// TIMSK0: Timer/Counter0 Interrupt Mask Register
|
||||
TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable
|
||||
TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable
|
||||
TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable
|
||||
|
||||
// TIFR0: Timer/Counter0 Interrupt Flag register
|
||||
TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B
|
||||
TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A
|
||||
TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag
|
||||
|
||||
// TCCR0A: Timer/Counter Control Register A
|
||||
TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode
|
||||
TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm
|
||||
TCCR0A_WGM0 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TCCR0B: Timer/Counter Control Register B
|
||||
TCCR0B_FOC0A = 0x80 // Force Output Compare A
|
||||
TCCR0B_FOC0B = 0x40 // Force Output Compare B
|
||||
TCCR0B_WGM02 = 0x8
|
||||
TCCR0B_CS0 = 0x7 // Clock Select
|
||||
|
||||
// TCNT0: Timer/Counter0
|
||||
TCNT0_TCNT0 = 0xff // Timer Counter 0 value
|
||||
|
||||
// OCR0A: Timer/Counter0 Output Compare Register
|
||||
OCR0A_OCR0A = 0xff // Output Compare A value
|
||||
|
||||
// OCR0B: Timer/Counter0 Output Compare Register
|
||||
OCR0B_OCR0B = 0xff // Output Compare B value
|
||||
)
|
||||
|
||||
// Bitfields for TC16: Timer/Counter, 16-bit
|
||||
const (
|
||||
// TIMSK1: Timer/Counter Interrupt Mask Register
|
||||
TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable
|
||||
TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output CompareB Match Interrupt Enable
|
||||
TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output CompareA Match Interrupt Enable
|
||||
TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable
|
||||
|
||||
// TIFR1: Timer/Counter Interrupt Flag register
|
||||
TIFR1_ICF1 = 0x20 // Input Capture Flag 1
|
||||
TIFR1_OCF1B = 0x4 // Output Compare Flag 1B
|
||||
TIFR1_OCF1A = 0x2 // Output Compare Flag 1A
|
||||
TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag
|
||||
|
||||
// TCCR1A: Timer/Counter1 Control Register A
|
||||
TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits
|
||||
TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits
|
||||
TCCR1A_WGM1 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TCCR1B: Timer/Counter1 Control Register B
|
||||
TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler
|
||||
TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select
|
||||
TCCR1B_WGM1 = 0x18 // Waveform Generation Mode
|
||||
TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1
|
||||
|
||||
// TCCR1C: Timer/Counter1 Control Register C
|
||||
TCCR1C_FOC1A = 0x80
|
||||
TCCR1C_FOC1B = 0x40
|
||||
|
||||
// TCNT1L: Timer/Counter1 Bytes
|
||||
|
||||
// TCNT1H: Timer/Counter1 Bytes
|
||||
TCNT1_TCNT1 = 0xffff // Timer/Counter1
|
||||
|
||||
// OCR1AL: Timer/Counter1 Output Compare Register Bytes
|
||||
|
||||
// OCR1AH: Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1A_OCR1A = 0xffff // Timer/Counter1 Output Compare A Register
|
||||
|
||||
// OCR1BL: Timer/Counter1 Output Compare Register Bytes
|
||||
|
||||
// OCR1BH: Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1B_OCR1B = 0xffff // Timer/Counter1 Output Compare B Register
|
||||
|
||||
// ICR1L: Timer/Counter1 Input Capture Register Bytes
|
||||
|
||||
// ICR1H: Timer/Counter1 Input Capture Register Bytes
|
||||
ICR1_ICR1 = 0xffff // Timer/Counter Input Capture
|
||||
)
|
||||
|
||||
// Bitfields for ADC: Analog-to-Digital Converter
|
||||
const (
|
||||
// ADMUX: The ADC multiplexer Selection Register
|
||||
ADMUX_REFS = 0xc0 // Reference Selection Bits
|
||||
ADMUX_ADLAR = 0x20 // Left Adjust Result
|
||||
ADMUX_MUX = 0xf // Analog Channel and Gain Selection Bits
|
||||
|
||||
// ADCSRA: The ADC Control and Status register
|
||||
ADCSRA_ADEN = 0x80 // ADC Enable
|
||||
ADCSRA_ADSC = 0x40 // ADC Start Conversion
|
||||
ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable
|
||||
ADCSRA_ADIF = 0x10 // ADC Interrupt Flag
|
||||
ADCSRA_ADIE = 0x8 // ADC Interrupt Enable
|
||||
ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits
|
||||
|
||||
// ADCSRB: ADC Control and Status Register B
|
||||
ADCSRB_ADHSM = 0x80 // ADC High Speed Mode
|
||||
ADCSRB_ADTS3 = 0x8 // ADC Auto Trigger Source Selection 3
|
||||
ADCSRB_ADTS2 = 0x4 // ADC Auto Trigger Source Selection 2
|
||||
ADCSRB_ADTS1 = 0x2 // ADC Auto Trigger Source Selection 1
|
||||
ADCSRB_ADTS0 = 0x1 // ADC Auto Trigger Source Selection 0
|
||||
|
||||
// DIDR0: Digital Input Disable Register 0
|
||||
DIDR0_ADC7D = 0x80
|
||||
DIDR0_ADC6D = 0x40
|
||||
DIDR0_ADC5D = 0x20
|
||||
DIDR0_ADC4D = 0x10
|
||||
DIDR0_ADC3D = 0x8
|
||||
DIDR0_ADC2D = 0x4
|
||||
DIDR0_ADC1D = 0x2
|
||||
DIDR0_ADC0D = 0x1
|
||||
|
||||
// DIDR1: Digital Input Disable Register 1
|
||||
DIDR1_ACMP0D = 0x20
|
||||
DIDR1_AMP0PD = 0x10
|
||||
DIDR1_AMP0ND = 0x8
|
||||
DIDR1_ADC10D = 0x4
|
||||
DIDR1_ADC9D = 0x2
|
||||
DIDR1_ADC8D = 0x1
|
||||
|
||||
// AMP0CSR
|
||||
AMP0CSR_AMP0EN = 0x80
|
||||
AMP0CSR_AMP0IS = 0x40
|
||||
AMP0CSR_AMP0G = 0x30
|
||||
AMP0CSR_AMP0TS = 0x3
|
||||
|
||||
// AMP1CSR
|
||||
AMP1CSR_AMP1EN = 0x80
|
||||
AMP1CSR_AMP1IS = 0x40
|
||||
AMP1CSR_AMP1G = 0x30
|
||||
AMP1CSR_AMP1TS = 0x3
|
||||
)
|
||||
|
||||
// Bitfields for USART: USART
|
||||
const (
|
||||
// UCSRA: USART Control and Status register A
|
||||
UCSRA_RXC = 0x80 // USART Receive Complete
|
||||
UCSRA_TXC = 0x40 // USART Transmitt Complete
|
||||
UCSRA_UDRE = 0x20 // USART Data Register Empty
|
||||
UCSRA_FE = 0x10 // Framing Error
|
||||
UCSRA_DOR = 0x8 // Data Overrun
|
||||
UCSRA_UPE = 0x4 // USART Parity Error
|
||||
UCSRA_U2X = 0x2 // Double USART Transmission Bit
|
||||
UCSRA_MPCM = 0x1 // Multi-processor Communication Mode
|
||||
|
||||
// UCSRB: USART Control an Status register B
|
||||
UCSRB_RXCIE = 0x80 // RX Complete Interrupt Enable
|
||||
UCSRB_TXCIE = 0x40 // TX Complete Interrupt Enable
|
||||
UCSRB_UDRIE = 0x20 // USART Data Register Empty Interrupt Enable
|
||||
UCSRB_RXEN = 0x10 // Receiver Enable
|
||||
UCSRB_TXEN = 0x8 // Transmitter Enable
|
||||
UCSRB_UCSZ2 = 0x4 // Character Size
|
||||
UCSRB_RXB8 = 0x2 // Receive Data Bit 8
|
||||
UCSRB_TXB8 = 0x1 // Transmit Data Bit 8
|
||||
|
||||
// UCSRC: USART Control an Status register C
|
||||
UCSRC_UMSEL0 = 0x40 // USART Mode Select
|
||||
UCSRC_UPM = 0x30 // Parity Mode Bits
|
||||
UCSRC_USBS = 0x8 // Stop Bit Select
|
||||
UCSRC_UCSZ = 0x6 // Character Size Bits
|
||||
UCSRC_UCPOL = 0x1 // Clock Polarity
|
||||
|
||||
// UBRRH: USART Baud Rate Register High Byte
|
||||
UBRRH_UBRR = 0xf // USART Baud Rate Register Bits
|
||||
|
||||
// UBRRL: USART Baud Rate Register Low Byte
|
||||
UBRRL_UBRR = 0xff // USART Baud Rate Register bits
|
||||
)
|
||||
|
||||
// Bitfields for SPI: Serial Peripheral Interface
|
||||
const (
|
||||
// SPCR: SPI Control Register
|
||||
SPCR_SPIE = 0x80 // SPI Interrupt Enable
|
||||
SPCR_SPE = 0x40 // SPI Enable
|
||||
SPCR_DORD = 0x20 // Data Order
|
||||
SPCR_MSTR = 0x10 // Master/Slave Select
|
||||
SPCR_CPOL = 0x8 // Clock polarity
|
||||
SPCR_CPHA = 0x4 // Clock Phase
|
||||
SPCR_SPR = 0x3 // SPI Clock Rate Selects
|
||||
|
||||
// SPSR: SPI Status Register
|
||||
SPSR_SPIF = 0x80 // SPI Interrupt Flag
|
||||
SPSR_WCOL = 0x40 // Write Collision Flag
|
||||
SPSR_SPI2X = 0x1 // Double SPI Speed Bit
|
||||
|
||||
// SPDR: SPI Data Register
|
||||
SPDR_SPD = 0xff // SPI Data
|
||||
)
|
||||
|
||||
// Bitfields for WDT: Watchdog Timer
|
||||
const (
|
||||
// WDTCSR: Watchdog Timer Control Register
|
||||
WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag
|
||||
WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable
|
||||
WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits
|
||||
WDTCSR_WDCE = 0x10 // Watchdog Change Enable
|
||||
WDTCSR_WDE = 0x8 // Watch Dog Enable
|
||||
)
|
||||
|
||||
// Bitfields for EXINT: External Interrupts
|
||||
const (
|
||||
// EICRA: External Interrupt Control Register A
|
||||
EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit
|
||||
EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit
|
||||
EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit
|
||||
EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit
|
||||
|
||||
// EIMSK: External Interrupt Mask Register
|
||||
EIMSK_INT = 0xf // External Interrupt Mask
|
||||
|
||||
// EIFR: External Interrupt Flag Register
|
||||
EIFR_INTF = 0xf // External Interrupt Flags
|
||||
)
|
||||
|
||||
// Bitfields for EEPROM: EEPROM
|
||||
const (
|
||||
// EEARL: EEPROM Read/Write Access Bytes
|
||||
|
||||
// EEARH: EEPROM Read/Write Access Bytes
|
||||
EEAR_EEAR = 0xfff // EEPROM Address bytes
|
||||
|
||||
// EEDR: EEPROM Data Register
|
||||
EEDR_EEDR = 0xff // EEPROM Data Bits
|
||||
|
||||
// EECR: EEPROM Control Register
|
||||
EECR_EEPM = 0x30 // EEPROM Programming Mode
|
||||
EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable
|
||||
EECR_EEMWE = 0x4 // EEPROM Master Write Enable
|
||||
EECR_EEWE = 0x2 // EEPROM Write Enable
|
||||
EECR_EERE = 0x1 // EEPROM Read Enable
|
||||
)
|
||||
|
||||
// Bitfields for PSC: Power Stage Controller
|
||||
const (
|
||||
// PICR0L: PSC 0 Input Capture Register
|
||||
|
||||
// PICR0H: PSC 0 Input Capture Register
|
||||
PICR0_PCST0 = 0x8000 // PSC 0 Input Capture Software Trig
|
||||
PICR0_PICR0 = 0xfff // PSC 0 Input Capture Bytes
|
||||
|
||||
// PFRC0B: PSC 0 Input B Control
|
||||
PFRC0B_PCAE0B = 0x80 // PSC 0 Capture Enable Input Part B
|
||||
PFRC0B_PISEL0B = 0x40 // PSC 0 Input Select for Part B
|
||||
PFRC0B_PELEV0B = 0x20 // PSC 0 Edge Level Selector on Input Part B
|
||||
PFRC0B_PFLTE0B = 0x10 // PSC 0 Filter Enable on Input Part B
|
||||
PFRC0B_PRFM0B = 0xf // PSC 0 Retrigger and Fault Mode for Part B
|
||||
|
||||
// PFRC0A: PSC 0 Input A Control
|
||||
PFRC0A_PCAE0A = 0x80 // PSC 0 Capture Enable Input Part A
|
||||
PFRC0A_PISEL0A = 0x40 // PSC 0 Input Select for Part A
|
||||
PFRC0A_PELEV0A = 0x20 // PSC 0 Edge Level Selector on Input Part A
|
||||
PFRC0A_PFLTE0A = 0x10 // PSC 0 Filter Enable on Input Part A
|
||||
PFRC0A_PRFM0A = 0xf // PSC 0 Retrigger and Fault Mode for Part A
|
||||
|
||||
// PCTL0: PSC 0 Control Register
|
||||
PCTL0_PPRE0 = 0xc0 // PSC 0 Prescaler Selects
|
||||
PCTL0_PBFM0 = 0x20 // PSC 0 Balance Flank Width Modulation
|
||||
PCTL0_PAOC0B = 0x10 // PSC 0 Asynchronous Output Control B
|
||||
PCTL0_PAOC0A = 0x8 // PSC 0 Asynchronous Output Control A
|
||||
PCTL0_PARUN0 = 0x4 // PSC0 Auto Run
|
||||
PCTL0_PCCYC0 = 0x2 // PSC0 Complete Cycle
|
||||
PCTL0_PRUN0 = 0x1 // PSC 0 Run
|
||||
|
||||
// PCNF0: PSC 0 Configuration Register
|
||||
PCNF0_PFIFTY0 = 0x80 // PSC 0 Fifty
|
||||
PCNF0_PALOCK0 = 0x40 // PSC 0 Autolock
|
||||
PCNF0_PLOCK0 = 0x20 // PSC 0 Lock
|
||||
PCNF0_PMODE0 = 0x18 // PSC 0 Mode
|
||||
PCNF0_POP0 = 0x4 // PSC 0 Output Polarity
|
||||
PCNF0_PCLKSEL0 = 0x2 // PSC 0 Input Clock Select
|
||||
|
||||
// PSOC0: PSC0 Synchro and Output Configuration
|
||||
PSOC0_PSYNC0 = 0x30 // Synchronization Out for ADC Selection
|
||||
PSOC0_POEN0B = 0x4 // PSCOUT01 Output Enable
|
||||
PSOC0_POEN0A = 0x1 // PSCOUT00 Output Enable
|
||||
|
||||
// PIM0: PSC0 Interrupt Mask Register
|
||||
PIM0_PSEIE0 = 0x20 // PSC 0 Synchro Error Interrupt Enable
|
||||
PIM0_PEVE0B = 0x10 // External Event B Interrupt Enable
|
||||
PIM0_PEVE0A = 0x8 // External Event A Interrupt Enable
|
||||
PIM0_PEOPE0 = 0x1 // End of Cycle Interrupt Enable
|
||||
|
||||
// PIFR0: PSC0 Interrupt Flag Register
|
||||
PIFR0_POAC0B = 0x80 // PSC 0 Output A Activity
|
||||
PIFR0_POAC0A = 0x40 // PSC 0 Output A Activity
|
||||
PIFR0_PSEI0 = 0x20 // PSC 0 Synchro Error Interrupt
|
||||
PIFR0_PEV0B = 0x10 // External Event B Interrupt
|
||||
PIFR0_PEV0A = 0x8 // External Event A Interrupt
|
||||
PIFR0_PRN0 = 0x6 // Ramp Number
|
||||
PIFR0_PEOP0 = 0x1 // End of PSC0 Interrupt
|
||||
|
||||
// PICR2L: PSC 2 Input Capture Register
|
||||
|
||||
// PICR2H: PSC 2 Input Capture Register
|
||||
PICR2_PCST2 = 0x8000 // PSC 2 Input Capture Software Trig
|
||||
PICR2_PICR2 = 0xfff // PSC 2 Input Capture Bytes
|
||||
|
||||
// PFRC2B: PSC 2 Input B Control
|
||||
PFRC2B_PCAE2B = 0x80 // PSC 2 Capture Enable Input Part B
|
||||
PFRC2B_PISEL2B = 0x40 // PSC 2 Input Select for Part B
|
||||
PFRC2B_PELEV2B = 0x20 // PSC 2 Edge Level Selector on Input Part B
|
||||
PFRC2B_PFLTE2B = 0x10 // PSC 2 Filter Enable on Input Part B
|
||||
PFRC2B_PRFM2B = 0xf // PSC 2 Retrigger and Fault Mode for Part B
|
||||
|
||||
// PFRC2A: PSC 2 Input B Control
|
||||
PFRC2A_PCAE2A = 0x80 // PSC 2 Capture Enable Input Part A
|
||||
PFRC2A_PISEL2A = 0x40 // PSC 2 Input Select for Part A
|
||||
PFRC2A_PELEV2A = 0x20 // PSC 2 Edge Level Selector on Input Part A
|
||||
PFRC2A_PFLTE2A = 0x10 // PSC 2 Filter Enable on Input Part A
|
||||
PFRC2A_PRFM2A = 0xf // PSC 2 Retrigger and Fault Mode for Part A
|
||||
|
||||
// PCTL2: PSC 2 Control Register
|
||||
PCTL2_PPRE2 = 0xc0 // PSC 2 Prescaler Selects
|
||||
PCTL2_PBFM2 = 0x20 // Balance Flank Width Modulation
|
||||
PCTL2_PAOC2B = 0x10 // PSC 2 Asynchronous Output Control B
|
||||
PCTL2_PAOC2A = 0x8 // PSC 2 Asynchronous Output Control A
|
||||
PCTL2_PARUN2 = 0x4 // PSC2 Auto Run
|
||||
PCTL2_PCCYC2 = 0x2 // PSC2 Complete Cycle
|
||||
PCTL2_PRUN2 = 0x1 // PSC 2 Run
|
||||
|
||||
// PCNF2: PSC 2 Configuration Register
|
||||
PCNF2_PFIFTY2 = 0x80 // PSC 2 Fifty
|
||||
PCNF2_PALOCK2 = 0x40 // PSC 2 Autolock
|
||||
PCNF2_PLOCK2 = 0x20 // PSC 2 Lock
|
||||
PCNF2_PMODE2 = 0x18 // PSC 2 Mode
|
||||
PCNF2_POP2 = 0x4 // PSC 2 Output Polarity
|
||||
PCNF2_PCLKSEL2 = 0x2 // PSC 2 Input Clock Select
|
||||
PCNF2_POME2 = 0x1 // PSC 2 Output Matrix Enable
|
||||
|
||||
// POM2: PSC 2 Output Matrix
|
||||
POM2_POMV2B = 0xf0 // Output Matrix Output B Ramps
|
||||
POM2_POMV2A = 0xf // Output Matrix Output A Ramps
|
||||
|
||||
// PSOC2: PSC2 Synchro and Output Configuration
|
||||
PSOC2_POS2 = 0xc0 // PSC 2 Output 23 Select
|
||||
PSOC2_PSYNC2 = 0x30 // Synchronization Out for ADC Selection
|
||||
PSOC2_POEN2D = 0x8 // PSCOUT23 Output Enable
|
||||
PSOC2_POEN2B = 0x4 // PSCOUT21 Output Enable
|
||||
PSOC2_POEN2C = 0x2 // PSCOUT22 Output Enable
|
||||
PSOC2_POEN2A = 0x1 // PSCOUT20 Output Enable
|
||||
|
||||
// PIM2: PSC2 Interrupt Mask Register
|
||||
PIM2_PSEIE2 = 0x20 // PSC 2 Synchro Error Interrupt Enable
|
||||
PIM2_PEVE2B = 0x10 // External Event B Interrupt Enable
|
||||
PIM2_PEVE2A = 0x8 // External Event A Interrupt Enable
|
||||
PIM2_PEOPE2 = 0x1 // End of Cycle Interrupt Enable
|
||||
|
||||
// PIFR2: PSC2 Interrupt Flag Register
|
||||
PIFR2_POAC2B = 0x80 // PSC 2 Output A Activity
|
||||
PIFR2_POAC2A = 0x40 // PSC 2 Output A Activity
|
||||
PIFR2_PSEI2 = 0x20 // PSC 2 Synchro Error Interrupt
|
||||
PIFR2_PEV2B = 0x10 // External Event B Interrupt
|
||||
PIFR2_PEV2A = 0x8 // External Event A Interrupt
|
||||
PIFR2_PRN2 = 0x6 // Ramp Number
|
||||
PIFR2_PEOP2 = 0x1 // End of PSC2 Interrupt
|
||||
)
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from AT90PWM216.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x4000;
|
||||
__ram_size = 0x400;
|
||||
__num_isrs = 32;
|
||||
|
|
@ -1,970 +0,0 @@
|
|||
// Automatically generated file. DO NOT EDIT.
|
||||
// Generated by gen-device.py from AT90PWM2B.atdf, see http://packs.download.atmel.com/
|
||||
|
||||
// +build avr,at90pwm2b
|
||||
|
||||
// Device information for the AT90PWM2B.
|
||||
//
|
||||
package avr
|
||||
|
||||
// Magic type name for the compiler.
|
||||
type __reg uint8
|
||||
|
||||
// Export this magic type name.
|
||||
type RegValue = __reg
|
||||
|
||||
// Some information about this device.
|
||||
const (
|
||||
DEVICE = "AT90PWM2B"
|
||||
ARCH = "AVR8"
|
||||
FAMILY = "megaAVR"
|
||||
)
|
||||
|
||||
// Interrupts
|
||||
const (
|
||||
IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset
|
||||
IRQ_PSC2_CAPT = 1 // PSC2 Capture Event
|
||||
IRQ_PSC2_EC = 2 // PSC2 End Cycle
|
||||
IRQ_PSC1_CAPT = 3 // PSC1 Capture Event
|
||||
IRQ_PSC1_EC = 4 // PSC1 End Cycle
|
||||
IRQ_PSC0_CAPT = 5 // PSC0 Capture Event
|
||||
IRQ_PSC0_EC = 6 // PSC0 End Cycle
|
||||
IRQ_ANALOG_COMP_0 = 7 // Analog Comparator 0
|
||||
IRQ_ANALOG_COMP_1 = 8 // Analog Comparator 1
|
||||
IRQ_ANALOG_COMP_2 = 9 // Analog Comparator 2
|
||||
IRQ_INT0 = 10 // External Interrupt Request 0
|
||||
IRQ_TIMER1_CAPT = 11 // Timer/Counter1 Capture Event
|
||||
IRQ_TIMER1_COMPA = 12 // Timer/Counter1 Compare Match A
|
||||
IRQ_TIMER1_COMPB = 13 // Timer/Counter Compare Match B
|
||||
IRQ_RESERVED15 = 14 //
|
||||
IRQ_TIMER1_OVF = 15 // Timer/Counter1 Overflow
|
||||
IRQ_TIMER0_COMPA = 16 // Timer/Counter0 Compare Match A
|
||||
IRQ_TIMER0_OVF = 17 // Timer/Counter0 Overflow
|
||||
IRQ_ADC = 18 // ADC Conversion Complete
|
||||
IRQ_INT1 = 19 // External Interrupt Request 1
|
||||
IRQ_SPI_STC = 20 // SPI Serial Transfer Complete
|
||||
IRQ_USART_RX = 21 // USART, Rx Complete
|
||||
IRQ_USART_UDRE = 22 // USART Data Register Empty
|
||||
IRQ_USART_TX = 23 // USART, Tx Complete
|
||||
IRQ_INT2 = 24 // External Interrupt Request 2
|
||||
IRQ_WDT = 25 // Watchdog Timeout Interrupt
|
||||
IRQ_EE_READY = 26 // EEPROM Ready
|
||||
IRQ_TIMER0_COMPB = 27 // Timer Counter 0 Compare Match B
|
||||
IRQ_INT3 = 28 // External Interrupt Request 3
|
||||
IRQ_RESERVED30 = 29 //
|
||||
IRQ_RESERVED31 = 30 //
|
||||
IRQ_SPM_READY = 31 // Store Program Memory Read
|
||||
IRQ_max = 31 // Highest interrupt number on this device.
|
||||
)
|
||||
|
||||
// Peripherals
|
||||
var (
|
||||
// Fuses
|
||||
FUSE = struct {
|
||||
EXTENDED __reg
|
||||
HIGH __reg
|
||||
LOW __reg
|
||||
}{
|
||||
EXTENDED: 0x2,
|
||||
HIGH: 0x1,
|
||||
LOW: 0x0,
|
||||
}
|
||||
|
||||
// Lockbits
|
||||
LOCKBIT = struct {
|
||||
LOCKBIT __reg
|
||||
}{
|
||||
LOCKBIT: 0x0,
|
||||
}
|
||||
|
||||
// I/O Port
|
||||
PORT = struct {
|
||||
PORTB __reg
|
||||
DDRB __reg
|
||||
PINB __reg
|
||||
PORTD __reg
|
||||
DDRD __reg
|
||||
PIND __reg
|
||||
PORTE __reg
|
||||
DDRE __reg
|
||||
PINE __reg
|
||||
}{
|
||||
PORTB: 0x25, // Port B Data Register
|
||||
DDRB: 0x24, // Port B Data Direction Register
|
||||
PINB: 0x23, // Port B Input Pins
|
||||
PORTD: 0x2b, // Port D Data Register
|
||||
DDRD: 0x2a, // Port D Data Direction Register
|
||||
PIND: 0x29, // Port D Input Pins
|
||||
PORTE: 0x2e, // Port E Data Register
|
||||
DDRE: 0x2d, // Port E Data Direction Register
|
||||
PINE: 0x2c, // Port E Input Pins
|
||||
}
|
||||
|
||||
// Bootloader
|
||||
BOOT_LOAD = struct {
|
||||
SPMCSR __reg
|
||||
}{
|
||||
SPMCSR: 0x57, // Store Program Memory Control Register
|
||||
}
|
||||
|
||||
// Extended USART
|
||||
EUSART = struct {
|
||||
EUDR __reg
|
||||
EUCSRA __reg
|
||||
EUCSRB __reg
|
||||
EUCSRC __reg
|
||||
MUBRRL __reg
|
||||
MUBRRH __reg
|
||||
}{
|
||||
EUDR: 0xce, // EUSART I/O Data Register
|
||||
EUCSRA: 0xc8, // EUSART Control and Status Register A
|
||||
EUCSRB: 0xc9, // EUSART Control Register B
|
||||
EUCSRC: 0xca, // EUSART Status Register C
|
||||
MUBRRL: 0xcc, // Manchester Receiver Baud Rate Register
|
||||
MUBRRH: 0xcc, // Manchester Receiver Baud Rate Register
|
||||
}
|
||||
|
||||
// Analog Comparator
|
||||
AC = struct {
|
||||
AC0CON __reg
|
||||
AC1CON __reg
|
||||
AC2CON __reg
|
||||
ACSR __reg
|
||||
}{
|
||||
AC0CON: 0xad, // Analog Comparator 0 Control Register
|
||||
AC1CON: 0xae, // Analog Comparator 1 Control Register
|
||||
AC2CON: 0xaf, // Analog Comparator 2 Control Register
|
||||
ACSR: 0x50, // Analog Comparator Status Register
|
||||
}
|
||||
|
||||
// Digital-to-Analog Converter
|
||||
DAC = struct {
|
||||
DACL __reg
|
||||
DACH __reg
|
||||
DACON __reg
|
||||
}{
|
||||
DACL: 0xab, // DAC Data Register
|
||||
DACH: 0xab, // DAC Data Register
|
||||
DACON: 0xaa, // DAC Control Register
|
||||
}
|
||||
|
||||
// CPU Registers
|
||||
CPU = struct {
|
||||
SREG __reg
|
||||
SPL __reg
|
||||
SPH __reg
|
||||
MCUCR __reg
|
||||
MCUSR __reg
|
||||
OSCCAL __reg
|
||||
CLKPR __reg
|
||||
SMCR __reg
|
||||
GPIOR3 __reg
|
||||
GPIOR2 __reg
|
||||
GPIOR1 __reg
|
||||
GPIOR0 __reg
|
||||
PLLCSR __reg
|
||||
PRR __reg
|
||||
}{
|
||||
SREG: 0x5f, // Status Register
|
||||
SPL: 0x5d, // Stack Pointer
|
||||
SPH: 0x5d, // Stack Pointer
|
||||
MCUCR: 0x55, // MCU Control Register
|
||||
MCUSR: 0x54, // MCU Status Register
|
||||
OSCCAL: 0x66, // Oscillator Calibration Value
|
||||
CLKPR: 0x61,
|
||||
SMCR: 0x53, // Sleep Mode Control Register
|
||||
GPIOR3: 0x3b, // General Purpose IO Register 3
|
||||
GPIOR2: 0x3a, // General Purpose IO Register 2
|
||||
GPIOR1: 0x39, // General Purpose IO Register 1
|
||||
GPIOR0: 0x3e, // General Purpose IO Register 0
|
||||
PLLCSR: 0x49, // PLL Control And Status Register
|
||||
PRR: 0x64, // Power Reduction Register
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit
|
||||
TC8 = struct {
|
||||
TIMSK0 __reg
|
||||
TIFR0 __reg
|
||||
TCCR0A __reg
|
||||
TCCR0B __reg
|
||||
TCNT0 __reg
|
||||
OCR0A __reg
|
||||
OCR0B __reg
|
||||
}{
|
||||
TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register
|
||||
TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register
|
||||
TCCR0A: 0x44, // Timer/Counter Control Register A
|
||||
TCCR0B: 0x45, // Timer/Counter Control Register B
|
||||
TCNT0: 0x46, // Timer/Counter0
|
||||
OCR0A: 0x47, // Timer/Counter0 Output Compare Register
|
||||
OCR0B: 0x48, // Timer/Counter0 Output Compare Register
|
||||
}
|
||||
|
||||
// Timer/Counter, 16-bit
|
||||
TC16 = struct {
|
||||
TIMSK1 __reg
|
||||
TIFR1 __reg
|
||||
TCCR1A __reg
|
||||
TCCR1B __reg
|
||||
TCCR1C __reg
|
||||
TCNT1L __reg
|
||||
TCNT1H __reg
|
||||
OCR1AL __reg
|
||||
OCR1AH __reg
|
||||
OCR1BL __reg
|
||||
OCR1BH __reg
|
||||
ICR1L __reg
|
||||
ICR1H __reg
|
||||
}{
|
||||
TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register
|
||||
TIFR1: 0x36, // Timer/Counter Interrupt Flag register
|
||||
TCCR1A: 0x80, // Timer/Counter1 Control Register A
|
||||
TCCR1B: 0x81, // Timer/Counter1 Control Register B
|
||||
TCCR1C: 0x82, // Timer/Counter1 Control Register C
|
||||
TCNT1L: 0x84, // Timer/Counter1 Bytes
|
||||
TCNT1H: 0x84, // Timer/Counter1 Bytes
|
||||
OCR1AL: 0x88, // Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1AH: 0x88, // Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register Bytes
|
||||
ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
}
|
||||
|
||||
// Analog-to-Digital Converter
|
||||
ADC = struct {
|
||||
ADMUX __reg
|
||||
ADCSRA __reg
|
||||
ADCL __reg
|
||||
ADCH __reg
|
||||
ADCSRB __reg
|
||||
DIDR0 __reg
|
||||
DIDR1 __reg
|
||||
AMP0CSR __reg
|
||||
AMP1CSR __reg
|
||||
}{
|
||||
ADMUX: 0x7c, // The ADC multiplexer Selection Register
|
||||
ADCSRA: 0x7a, // The ADC Control and Status register
|
||||
ADCL: 0x78, // ADC Data Register Bytes
|
||||
ADCH: 0x78, // ADC Data Register Bytes
|
||||
ADCSRB: 0x7b, // ADC Control and Status Register B
|
||||
DIDR0: 0x7e, // Digital Input Disable Register 0
|
||||
DIDR1: 0x7f, // Digital Input Disable Register 1
|
||||
AMP0CSR: 0x76,
|
||||
AMP1CSR: 0x77,
|
||||
}
|
||||
|
||||
// USART
|
||||
USART = struct {
|
||||
UDR __reg
|
||||
UCSRA __reg
|
||||
UCSRB __reg
|
||||
UCSRC __reg
|
||||
UBRRL __reg
|
||||
UBRRH __reg
|
||||
}{
|
||||
UDR: 0xc6, // USART I/O Data Register
|
||||
UCSRA: 0xc0, // USART Control and Status register A
|
||||
UCSRB: 0xc1, // USART Control an Status register B
|
||||
UCSRC: 0xc2, // USART Control an Status register C
|
||||
UBRRL: 0xc4, // USART Baud Rate Register
|
||||
UBRRH: 0xc4, // USART Baud Rate Register
|
||||
}
|
||||
|
||||
// Serial Peripheral Interface
|
||||
SPI = struct {
|
||||
SPCR __reg
|
||||
SPSR __reg
|
||||
SPDR __reg
|
||||
}{
|
||||
SPCR: 0x4c, // SPI Control Register
|
||||
SPSR: 0x4d, // SPI Status Register
|
||||
SPDR: 0x4e, // SPI Data Register
|
||||
}
|
||||
|
||||
// Watchdog Timer
|
||||
WDT = struct {
|
||||
WDTCSR __reg
|
||||
}{
|
||||
WDTCSR: 0x60, // Watchdog Timer Control Register
|
||||
}
|
||||
|
||||
// External Interrupts
|
||||
EXINT = struct {
|
||||
EICRA __reg
|
||||
EIMSK __reg
|
||||
EIFR __reg
|
||||
}{
|
||||
EICRA: 0x69, // External Interrupt Control Register A
|
||||
EIMSK: 0x3d, // External Interrupt Mask Register
|
||||
EIFR: 0x3c, // External Interrupt Flag Register
|
||||
}
|
||||
|
||||
// EEPROM
|
||||
EEPROM = struct {
|
||||
EEARL __reg
|
||||
EEARH __reg
|
||||
EEDR __reg
|
||||
EECR __reg
|
||||
}{
|
||||
EEARL: 0x41, // EEPROM Read/Write Access Bytes
|
||||
EEARH: 0x41, // EEPROM Read/Write Access Bytes
|
||||
EEDR: 0x40, // EEPROM Data Register
|
||||
EECR: 0x3f, // EEPROM Control Register
|
||||
}
|
||||
|
||||
// Power Stage Controller
|
||||
PSC = struct {
|
||||
PICR0L __reg
|
||||
PICR0H __reg
|
||||
PFRC0B __reg
|
||||
PFRC0A __reg
|
||||
PCTL0 __reg
|
||||
PCNF0 __reg
|
||||
OCR0RBL __reg
|
||||
OCR0RBH __reg
|
||||
OCR0SBL __reg
|
||||
OCR0SBH __reg
|
||||
OCR0RAL __reg
|
||||
OCR0RAH __reg
|
||||
OCR0SAL __reg
|
||||
OCR0SAH __reg
|
||||
PSOC0 __reg
|
||||
PIM0 __reg
|
||||
PIFR0 __reg
|
||||
PICR2L __reg
|
||||
PICR2H __reg
|
||||
PFRC2B __reg
|
||||
PFRC2A __reg
|
||||
PCTL2 __reg
|
||||
PCNF2 __reg
|
||||
OCR2RBL __reg
|
||||
OCR2RBH __reg
|
||||
OCR2SBL __reg
|
||||
OCR2SBH __reg
|
||||
OCR2RAL __reg
|
||||
OCR2RAH __reg
|
||||
OCR2SAL __reg
|
||||
OCR2SAH __reg
|
||||
POM2 __reg
|
||||
PSOC2 __reg
|
||||
PIM2 __reg
|
||||
PIFR2 __reg
|
||||
}{
|
||||
PICR0L: 0xde, // PSC 0 Input Capture Register
|
||||
PICR0H: 0xde, // PSC 0 Input Capture Register
|
||||
PFRC0B: 0xdd, // PSC 0 Input B Control
|
||||
PFRC0A: 0xdc, // PSC 0 Input A Control
|
||||
PCTL0: 0xdb, // PSC 0 Control Register
|
||||
PCNF0: 0xda, // PSC 0 Configuration Register
|
||||
OCR0RBL: 0xd8, // Output Compare 0 RB Register
|
||||
OCR0RBH: 0xd8, // Output Compare 0 RB Register
|
||||
OCR0SBL: 0xd6, // Output Compare 0 SB Register
|
||||
OCR0SBH: 0xd6, // Output Compare 0 SB Register
|
||||
OCR0RAL: 0xd4, // Output Compare 0 RA Register
|
||||
OCR0RAH: 0xd4, // Output Compare 0 RA Register
|
||||
OCR0SAL: 0xd2, // Output Compare 0 SA Register
|
||||
OCR0SAH: 0xd2, // Output Compare 0 SA Register
|
||||
PSOC0: 0xd0, // PSC0 Synchro and Output Configuration
|
||||
PIM0: 0xa1, // PSC0 Interrupt Mask Register
|
||||
PIFR0: 0xa0, // PSC0 Interrupt Flag Register
|
||||
PICR2L: 0xfe, // PSC 2 Input Capture Register
|
||||
PICR2H: 0xfe, // PSC 2 Input Capture Register
|
||||
PFRC2B: 0xfd, // PSC 2 Input B Control
|
||||
PFRC2A: 0xfc, // PSC 2 Input B Control
|
||||
PCTL2: 0xfb, // PSC 2 Control Register
|
||||
PCNF2: 0xfa, // PSC 2 Configuration Register
|
||||
OCR2RBL: 0xf8, // Output Compare 2 RB Register
|
||||
OCR2RBH: 0xf8, // Output Compare 2 RB Register
|
||||
OCR2SBL: 0xf6, // Output Compare 2 SB Register
|
||||
OCR2SBH: 0xf6, // Output Compare 2 SB Register
|
||||
OCR2RAL: 0xf4, // Output Compare 2 RA Register
|
||||
OCR2RAH: 0xf4, // Output Compare 2 RA Register
|
||||
OCR2SAL: 0xf2, // Output Compare 2 SA Register
|
||||
OCR2SAH: 0xf2, // Output Compare 2 SA Register
|
||||
POM2: 0xf1, // PSC 2 Output Matrix
|
||||
PSOC2: 0xf0, // PSC2 Synchro and Output Configuration
|
||||
PIM2: 0xa5, // PSC2 Interrupt Mask Register
|
||||
PIFR2: 0xa4, // PSC2 Interrupt Flag Register
|
||||
}
|
||||
)
|
||||
|
||||
// Bitfields for FUSE: Fuses
|
||||
const (
|
||||
// EXTENDED
|
||||
EXTENDED_PSC2RB = 0x80 // PSC2 Reset Behavior
|
||||
EXTENDED_PSC1RB = 0x40 // PSC1 Reset Behavior
|
||||
EXTENDED_PSC0RB = 0x20 // PSC0 Reset Behavior
|
||||
EXTENDED_PSCRV = 0x10 // PSCOUT Reset Value
|
||||
EXTENDED_BOOTSZ = 0x6 // Select Boot Size
|
||||
EXTENDED_BOOTRST = 0x1 // Select Reset Vector
|
||||
|
||||
// HIGH
|
||||
HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PC6 as i/o pin)
|
||||
HIGH_DWEN = 0x40 // Debug Wire enable
|
||||
HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled
|
||||
HIGH_WDTON = 0x10 // Watch-dog Timer always on
|
||||
HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle
|
||||
HIGH_BODLEVEL = 0x7 // Brown-out Detector Trigger Level
|
||||
|
||||
// LOW
|
||||
LOW_CKDIV8 = 0x80 // Divide clock by 8 internally
|
||||
LOW_CKOUT = 0x40 // Clock output on PORTB0
|
||||
LOW_SUT_CKSEL = 0x3f // Select Clock Source
|
||||
)
|
||||
|
||||
// Bitfields for LOCKBIT: Lockbits
|
||||
const (
|
||||
// LOCKBIT
|
||||
LOCKBIT_LB = 0x3 // Memory Lock
|
||||
LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode
|
||||
LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode
|
||||
)
|
||||
|
||||
// Bitfields for BOOT_LOAD: Bootloader
|
||||
const (
|
||||
// SPMCSR: Store Program Memory Control Register
|
||||
SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable
|
||||
SPMCSR_RWWSB = 0x40 // Read While Write Section Busy
|
||||
SPMCSR_RWWSRE = 0x10 // Read While Write section read enable
|
||||
SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set
|
||||
SPMCSR_PGWRT = 0x4 // Page Write
|
||||
SPMCSR_PGERS = 0x2 // Page Erase
|
||||
SPMCSR_SPMEN = 0x1 // Store Program Memory Enable
|
||||
)
|
||||
|
||||
// Bitfields for EUSART: Extended USART
|
||||
const (
|
||||
// EUDR: EUSART I/O Data Register
|
||||
EUDR_EUDR = 0xff // EUSART Extended data bits
|
||||
|
||||
// EUCSRA: EUSART Control and Status Register A
|
||||
EUCSRA_UTxS = 0xf0 // EUSART Control and Status Register A Bits
|
||||
EUCSRA_URxS = 0xf // EUSART Control and Status Register A Bits
|
||||
|
||||
// EUCSRB: EUSART Control Register B
|
||||
EUCSRB_EUSART = 0x10 // EUSART Enable Bit
|
||||
EUCSRB_EUSBS = 0x8 // EUSBS Enable Bit
|
||||
EUCSRB_EMCH = 0x2 // Manchester Mode Bit
|
||||
EUCSRB_BODR = 0x1 // Order Bit
|
||||
|
||||
// EUCSRC: EUSART Status Register C
|
||||
EUCSRC_FEM = 0x8 // Frame Error Manchester Bit
|
||||
EUCSRC_F1617 = 0x4 // F1617 Bit
|
||||
EUCSRC_STP = 0x3 // Stop Bits
|
||||
|
||||
// MUBRRL: Manchester Receiver Baud Rate Register
|
||||
|
||||
// MUBRRH: Manchester Receiver Baud Rate Register
|
||||
MUBRR_MUBRR = 0xffff // Manchester Receiver Baud Rate Register Bits
|
||||
)
|
||||
|
||||
// Bitfields for AC: Analog Comparator
|
||||
const (
|
||||
// AC0CON: Analog Comparator 0 Control Register
|
||||
AC0CON_AC0EN = 0x80 // Analog Comparator 0 Enable Bit
|
||||
AC0CON_AC0IE = 0x40 // Analog Comparator 0 Interrupt Enable Bit
|
||||
AC0CON_AC0IS = 0x30 // Analog Comparator 0 Interrupt Select Bit
|
||||
AC0CON_AC0M = 0x7 // Analog Comparator 0 Multiplexer Register
|
||||
|
||||
// AC1CON: Analog Comparator 1 Control Register
|
||||
AC1CON_AC1EN = 0x80 // Analog Comparator 1 Enable Bit
|
||||
AC1CON_AC1IE = 0x40 // Analog Comparator 1 Interrupt Enable Bit
|
||||
AC1CON_AC1IS = 0x30 // Analog Comparator 1 Interrupt Select Bit
|
||||
AC1CON_AC1ICE = 0x8 // Analog Comparator 1 Interrupt Capture Enable Bit
|
||||
AC1CON_AC1M = 0x7 // Analog Comparator 1 Multiplexer Register
|
||||
|
||||
// AC2CON: Analog Comparator 2 Control Register
|
||||
AC2CON_AC2EN = 0x80 // Analog Comparator 2 Enable Bit
|
||||
AC2CON_AC2IE = 0x40 // Analog Comparator 2 Interrupt Enable Bit
|
||||
AC2CON_AC2IS = 0x30 // Analog Comparator 2 Interrupt Select Bit
|
||||
AC2CON_AC2M = 0x7 // Analog Comparator 2 Multiplexer Register
|
||||
|
||||
// ACSR: Analog Comparator Status Register
|
||||
ACSR_ACCKDIV = 0x80 // Analog Comparator Clock Divider
|
||||
ACSR_AC2IF = 0x40 // Analog Comparator 2 Interrupt Flag Bit
|
||||
ACSR_AC1IF = 0x20 // Analog Comparator 1 Interrupt Flag Bit
|
||||
ACSR_AC0IF = 0x10 // Analog Comparator 0 Interrupt Flag Bit
|
||||
ACSR_AC2O = 0x4 // Analog Comparator 2 Output Bit
|
||||
ACSR_AC1O = 0x2 // Analog Comparator 1 Output Bit
|
||||
ACSR_AC0O = 0x1 // Analog Comparator 0 Output Bit
|
||||
)
|
||||
|
||||
// Bitfields for DAC: Digital-to-Analog Converter
|
||||
const (
|
||||
// DACL: DAC Data Register
|
||||
|
||||
// DACH: DAC Data Register
|
||||
DAC_DAC = 0xffff // DAC Data Register Bits
|
||||
|
||||
// DACON: DAC Control Register
|
||||
DACON_DAATE = 0x80 // DAC Auto Trigger Enable Bit
|
||||
DACON_DATS = 0x70 // DAC Trigger Selection Bits
|
||||
DACON_DALA = 0x4 // DAC Left Adjust
|
||||
DACON_DAOE = 0x2 // DAC Output Enable
|
||||
DACON_DAEN = 0x1 // DAC Enable Bit
|
||||
)
|
||||
|
||||
// Bitfields for CPU: CPU Registers
|
||||
const (
|
||||
// SREG: Status Register
|
||||
SREG_I = 0x80 // Global Interrupt Enable
|
||||
SREG_T = 0x40 // Bit Copy Storage
|
||||
SREG_H = 0x20 // Half Carry Flag
|
||||
SREG_S = 0x10 // Sign Bit
|
||||
SREG_V = 0x8 // Two's Complement Overflow Flag
|
||||
SREG_N = 0x4 // Negative Flag
|
||||
SREG_Z = 0x2 // Zero Flag
|
||||
SREG_C = 0x1 // Carry Flag
|
||||
|
||||
// MCUCR: MCU Control Register
|
||||
MCUCR_SPIPS = 0x80 // SPI Pin Select
|
||||
MCUCR_PUD = 0x10 // Pull-up disable
|
||||
MCUCR_IVSEL = 0x2 // Interrupt Vector Select
|
||||
MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable
|
||||
|
||||
// MCUSR: MCU Status Register
|
||||
MCUSR_WDRF = 0x8 // Watchdog Reset Flag
|
||||
MCUSR_BORF = 0x4 // Brown-out Reset Flag
|
||||
MCUSR_EXTRF = 0x2 // External Reset Flag
|
||||
MCUSR_PORF = 0x1 // Power-on reset flag
|
||||
|
||||
// OSCCAL: Oscillator Calibration Value
|
||||
OSCCAL_OSCCAL = 0xff // Oscillator Calibration
|
||||
|
||||
// CLKPR
|
||||
CLKPR_CLKPCE = 0x80
|
||||
CLKPR_CLKPS = 0xf
|
||||
|
||||
// SMCR: Sleep Mode Control Register
|
||||
SMCR_SM = 0xe // Sleep Mode Select bits
|
||||
SMCR_SE = 0x1 // Sleep Enable
|
||||
|
||||
// GPIOR3: General Purpose IO Register 3
|
||||
GPIOR3_GPIOR = 0xff // General Purpose IO Register 3 bis
|
||||
|
||||
// GPIOR2: General Purpose IO Register 2
|
||||
GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis
|
||||
|
||||
// GPIOR1: General Purpose IO Register 1
|
||||
GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis
|
||||
|
||||
// GPIOR0: General Purpose IO Register 0
|
||||
GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7
|
||||
GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6
|
||||
GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5
|
||||
GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4
|
||||
GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3
|
||||
GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2
|
||||
GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1
|
||||
GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0
|
||||
|
||||
// PLLCSR: PLL Control And Status Register
|
||||
PLLCSR_PLLF = 0x4 // PLL Factor
|
||||
PLLCSR_PLLE = 0x2 // PLL Enable
|
||||
PLLCSR_PLOCK = 0x1 // PLL Lock Detector
|
||||
|
||||
// PRR: Power Reduction Register
|
||||
PRR_PRPSC2 = 0x80 // Power Reduction PSC2
|
||||
PRR_PRPSC1 = 0x40 // Power Reduction PSC1
|
||||
PRR_PRPSC0 = 0x20 // Power Reduction PSC0
|
||||
PRR_PRTIM1 = 0x10 // Power Reduction Timer/Counter1
|
||||
PRR_PRTIM0 = 0x8 // Power Reduction Timer/Counter0
|
||||
PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface
|
||||
PRR_PRUSART0 = 0x2 // Power Reduction USART
|
||||
PRR_PRADC = 0x1 // Power Reduction ADC
|
||||
)
|
||||
|
||||
// Bitfields for TC8: Timer/Counter, 8-bit
|
||||
const (
|
||||
// TIMSK0: Timer/Counter0 Interrupt Mask Register
|
||||
TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable
|
||||
TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable
|
||||
TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable
|
||||
|
||||
// TIFR0: Timer/Counter0 Interrupt Flag register
|
||||
TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B
|
||||
TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A
|
||||
TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag
|
||||
|
||||
// TCCR0A: Timer/Counter Control Register A
|
||||
TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode
|
||||
TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm
|
||||
TCCR0A_WGM0 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TCCR0B: Timer/Counter Control Register B
|
||||
TCCR0B_FOC0A = 0x80 // Force Output Compare A
|
||||
TCCR0B_FOC0B = 0x40 // Force Output Compare B
|
||||
TCCR0B_WGM02 = 0x8
|
||||
TCCR0B_CS0 = 0x7 // Clock Select
|
||||
|
||||
// TCNT0: Timer/Counter0
|
||||
TCNT0_TCNT0 = 0xff // Timer Counter 0 value
|
||||
|
||||
// OCR0A: Timer/Counter0 Output Compare Register
|
||||
OCR0A_OCR0A = 0xff // Timer/Counter0 Output Compare A
|
||||
|
||||
// OCR0B: Timer/Counter0 Output Compare Register
|
||||
OCR0B_OCR0B = 0xff // Timer/Counter0 Output Compare B
|
||||
)
|
||||
|
||||
// Bitfields for TC16: Timer/Counter, 16-bit
|
||||
const (
|
||||
// TIMSK1: Timer/Counter Interrupt Mask Register
|
||||
TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable
|
||||
TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output CompareB Match Interrupt Enable
|
||||
TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output CompareA Match Interrupt Enable
|
||||
TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable
|
||||
|
||||
// TIFR1: Timer/Counter Interrupt Flag register
|
||||
TIFR1_ICF1 = 0x20 // Input Capture Flag 1
|
||||
TIFR1_OCF1B = 0x4 // Output Compare Flag 1B
|
||||
TIFR1_OCF1A = 0x2 // Output Compare Flag 1A
|
||||
TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag
|
||||
|
||||
// TCCR1A: Timer/Counter1 Control Register A
|
||||
TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits
|
||||
TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits
|
||||
TCCR1A_WGM1 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TCCR1B: Timer/Counter1 Control Register B
|
||||
TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler
|
||||
TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select
|
||||
TCCR1B_WGM1 = 0x18 // Waveform Generation Mode
|
||||
TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1
|
||||
|
||||
// TCCR1C: Timer/Counter1 Control Register C
|
||||
TCCR1C_FOC1A = 0x80
|
||||
TCCR1C_FOC1B = 0x40
|
||||
|
||||
// TCNT1L: Timer/Counter1 Bytes
|
||||
|
||||
// TCNT1H: Timer/Counter1 Bytes
|
||||
TCNT1_TCNT1 = 0xffff // Timer/Counter1
|
||||
|
||||
// ICR1L: Timer/Counter1 Input Capture Register Bytes
|
||||
|
||||
// ICR1H: Timer/Counter1 Input Capture Register Bytes
|
||||
ICR1_ICR1 = 0xffff // Timer/Counter1 Input Capture
|
||||
)
|
||||
|
||||
// Bitfields for ADC: Analog-to-Digital Converter
|
||||
const (
|
||||
// ADMUX: The ADC multiplexer Selection Register
|
||||
ADMUX_REFS = 0xc0 // Reference Selection Bits
|
||||
ADMUX_ADLAR = 0x20 // Left Adjust Result
|
||||
ADMUX_MUX = 0xf // Analog Channel and Gain Selection Bits
|
||||
|
||||
// ADCSRA: The ADC Control and Status register
|
||||
ADCSRA_ADEN = 0x80 // ADC Enable
|
||||
ADCSRA_ADSC = 0x40 // ADC Start Conversion
|
||||
ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable
|
||||
ADCSRA_ADIF = 0x10 // ADC Interrupt Flag
|
||||
ADCSRA_ADIE = 0x8 // ADC Interrupt Enable
|
||||
ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits
|
||||
|
||||
// ADCL: ADC Data Register Bytes
|
||||
|
||||
// ADCH: ADC Data Register Bytes
|
||||
ADC_ADC = 0xffff // ADC Data Register
|
||||
|
||||
// ADCSRB: ADC Control and Status Register B
|
||||
ADCSRB_ADHSM = 0x80 // ADC High Speed Mode
|
||||
ADCSRB_ADTS = 0xf // ADC Auto Trigger Source
|
||||
|
||||
// DIDR0: Digital Input Disable Register 0
|
||||
DIDR0_ADC7D = 0x80
|
||||
DIDR0_ADC6D = 0x40
|
||||
DIDR0_ADC5D = 0x20
|
||||
DIDR0_ADC4D = 0x10
|
||||
DIDR0_ADC3D = 0x8
|
||||
DIDR0_ADC2D = 0x4
|
||||
DIDR0_ADC1D = 0x2
|
||||
DIDR0_ADC0D = 0x1
|
||||
|
||||
// DIDR1: Digital Input Disable Register 1
|
||||
DIDR1_ACMP0D = 0x20
|
||||
DIDR1_AMP0PD = 0x10
|
||||
DIDR1_AMP0ND = 0x8
|
||||
DIDR1_ADC10D = 0x4
|
||||
DIDR1_ADC9D = 0x2
|
||||
DIDR1_ADC8D = 0x1
|
||||
|
||||
// AMP0CSR
|
||||
AMP0CSR_AMP0EN = 0x80
|
||||
AMP0CSR_AMP0IS = 0x40
|
||||
AMP0CSR_AMP0G = 0x30
|
||||
AMP0CSR_AMP0TS = 0x3
|
||||
|
||||
// AMP1CSR
|
||||
AMP1CSR_AMP1EN = 0x80
|
||||
AMP1CSR_AMP1IS = 0x40
|
||||
AMP1CSR_AMP1G = 0x30
|
||||
AMP1CSR_AMP1TS = 0x3
|
||||
)
|
||||
|
||||
// Bitfields for USART: USART
|
||||
const (
|
||||
// UDR: USART I/O Data Register
|
||||
UDR_UDR = 0xff // USART I/O Data
|
||||
|
||||
// UCSRA: USART Control and Status register A
|
||||
UCSRA_RXC = 0x80 // USART Receive Complete
|
||||
UCSRA_TXC = 0x40 // USART Transmitt Complete
|
||||
UCSRA_UDRE = 0x20 // USART Data Register Empty
|
||||
UCSRA_FE = 0x10 // Framing Error
|
||||
UCSRA_DOR = 0x8 // Data Overrun
|
||||
UCSRA_UPE = 0x4 // USART Parity Error
|
||||
UCSRA_U2X = 0x2 // Double USART Transmission Bit
|
||||
UCSRA_MPCM = 0x1 // Multi-processor Communication Mode
|
||||
|
||||
// UCSRB: USART Control an Status register B
|
||||
UCSRB_RXCIE = 0x80 // RX Complete Interrupt Enable
|
||||
UCSRB_TXCIE = 0x40 // TX Complete Interrupt Enable
|
||||
UCSRB_UDRIE = 0x20 // USART Data Register Empty Interrupt Enable
|
||||
UCSRB_RXEN = 0x10 // Receiver Enable
|
||||
UCSRB_TXEN = 0x8 // Transmitter Enable
|
||||
UCSRB_UCSZ2 = 0x4 // Character Size
|
||||
UCSRB_RXB8 = 0x2 // Receive Data Bit 8
|
||||
UCSRB_TXB8 = 0x1 // Transmit Data Bit 8
|
||||
|
||||
// UCSRC: USART Control an Status register C
|
||||
UCSRC_UMSEL0 = 0x40 // USART Mode Select
|
||||
UCSRC_UPM = 0x30 // Parity Mode Bits
|
||||
UCSRC_USBS = 0x8 // Stop Bit Select
|
||||
UCSRC_UCSZ = 0x6 // Character Size Bits
|
||||
UCSRC_UCPOL = 0x1 // Clock Polarity
|
||||
|
||||
// UBRRL: USART Baud Rate Register
|
||||
|
||||
// UBRRH: USART Baud Rate Register
|
||||
UBRR_UBRR = 0xfff // USART Baud Rate Register Bits
|
||||
)
|
||||
|
||||
// Bitfields for SPI: Serial Peripheral Interface
|
||||
const (
|
||||
// SPCR: SPI Control Register
|
||||
SPCR_SPIE = 0x80 // SPI Interrupt Enable
|
||||
SPCR_SPE = 0x40 // SPI Enable
|
||||
SPCR_DORD = 0x20 // Data Order
|
||||
SPCR_MSTR = 0x10 // Master/Slave Select
|
||||
SPCR_CPOL = 0x8 // Clock polarity
|
||||
SPCR_CPHA = 0x4 // Clock Phase
|
||||
SPCR_SPR = 0x3 // SPI Clock Rate Selects
|
||||
|
||||
// SPSR: SPI Status Register
|
||||
SPSR_SPIF = 0x80 // SPI Interrupt Flag
|
||||
SPSR_WCOL = 0x40 // Write Collision Flag
|
||||
SPSR_SPI2X = 0x1 // Double SPI Speed Bit
|
||||
|
||||
// SPDR: SPI Data Register
|
||||
SPDR_SPD = 0xff // SPI Data bits
|
||||
)
|
||||
|
||||
// Bitfields for WDT: Watchdog Timer
|
||||
const (
|
||||
// WDTCSR: Watchdog Timer Control Register
|
||||
WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag
|
||||
WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable
|
||||
WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits
|
||||
WDTCSR_WDCE = 0x10 // Watchdog Change Enable
|
||||
WDTCSR_WDE = 0x8 // Watch Dog Enable
|
||||
)
|
||||
|
||||
// Bitfields for EXINT: External Interrupts
|
||||
const (
|
||||
// EICRA: External Interrupt Control Register A
|
||||
EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit
|
||||
EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit
|
||||
EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit
|
||||
EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit
|
||||
|
||||
// EIMSK: External Interrupt Mask Register
|
||||
EIMSK_INT = 0x7 // External Interrupt Request Enable
|
||||
|
||||
// EIFR: External Interrupt Flag Register
|
||||
EIFR_INTF = 0x7 // External Interrupt Flags
|
||||
)
|
||||
|
||||
// Bitfields for EEPROM: EEPROM
|
||||
const (
|
||||
// EEARL: EEPROM Read/Write Access Bytes
|
||||
|
||||
// EEARH: EEPROM Read/Write Access Bytes
|
||||
EEAR_EEAR = 0xfff // EEPROM Address bytes
|
||||
|
||||
// EEDR: EEPROM Data Register
|
||||
EEDR_EEDR = 0xff // EEPROM Data Bits
|
||||
|
||||
// EECR: EEPROM Control Register
|
||||
EECR_EEPM = 0x30 // EEPROM Programming Mode
|
||||
EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable
|
||||
EECR_EEMWE = 0x4 // EEPROM Master Write Enable
|
||||
EECR_EEWE = 0x2 // EEPROM Write Enable
|
||||
EECR_EERE = 0x1 // EEPROM Read Enable
|
||||
)
|
||||
|
||||
// Bitfields for PSC: Power Stage Controller
|
||||
const (
|
||||
// PICR0L: PSC 0 Input Capture Register
|
||||
|
||||
// PICR0H: PSC 0 Input Capture Register
|
||||
PICR0_PCST0 = 0x8000 // PSC 0 Input Capture Software Trig
|
||||
PICR0_PICR0 = 0xfff // PSC 0 Input Capture Bytes
|
||||
|
||||
// PFRC0B: PSC 0 Input B Control
|
||||
PFRC0B_PCAE0B = 0x80 // PSC 0 Capture Enable Input Part B
|
||||
PFRC0B_PISEL0B = 0x40 // PSC 0 Input Select for Part B
|
||||
PFRC0B_PELEV0B = 0x20 // PSC 0 Edge Level Selector on Input Part B
|
||||
PFRC0B_PFLTE0B = 0x10 // PSC 0 Filter Enable on Input Part B
|
||||
PFRC0B_PRFM0B = 0xf // PSC 0 Retrigger and Fault Mode for Part B
|
||||
|
||||
// PFRC0A: PSC 0 Input A Control
|
||||
PFRC0A_PCAE0A = 0x80 // PSC 0 Capture Enable Input Part A
|
||||
PFRC0A_PISEL0A = 0x40 // PSC 0 Input Select for Part A
|
||||
PFRC0A_PELEV0A = 0x20 // PSC 0 Edge Level Selector on Input Part A
|
||||
PFRC0A_PFLTE0A = 0x10 // PSC 0 Filter Enable on Input Part A
|
||||
PFRC0A_PRFM0A = 0xf // PSC 0 Retrigger and Fault Mode for Part A
|
||||
|
||||
// PCTL0: PSC 0 Control Register
|
||||
PCTL0_PPRE0 = 0xc0 // PSC 0 Prescaler Selects
|
||||
PCTL0_PBFM0 = 0x20 // PSC 0 Balance Flank Width Modulation
|
||||
PCTL0_PAOC0B = 0x10 // PSC 0 Asynchronous Output Control B
|
||||
PCTL0_PAOC0A = 0x8 // PSC 0 Asynchronous Output Control A
|
||||
PCTL0_PARUN0 = 0x4 // PSC0 Auto Run
|
||||
PCTL0_PCCYC0 = 0x2 // PSC0 Complete Cycle
|
||||
PCTL0_PRUN0 = 0x1 // PSC 0 Run
|
||||
|
||||
// PCNF0: PSC 0 Configuration Register
|
||||
PCNF0_PFIFTY0 = 0x80 // PSC 0 Fifty
|
||||
PCNF0_PALOCK0 = 0x40 // PSC 0 Autolock
|
||||
PCNF0_PLOCK0 = 0x20 // PSC 0 Lock
|
||||
PCNF0_PMODE0 = 0x18 // PSC 0 Mode
|
||||
PCNF0_POP0 = 0x4 // PSC 0 Output Polarity
|
||||
PCNF0_PCLKSEL0 = 0x2 // PSC 0 Input Clock Select
|
||||
|
||||
// OCR0RBL: Output Compare 0 RB Register
|
||||
|
||||
// OCR0RBH: Output Compare 0 RB Register
|
||||
OCR0RB_OCR0RB = 0xffff // Output Compare RB
|
||||
|
||||
// OCR0SBL: Output Compare 0 SB Register
|
||||
|
||||
// OCR0SBH: Output Compare 0 SB Register
|
||||
OCR0SB_OCR0SB = 0xfff // Output Compare SB
|
||||
|
||||
// OCR0RAL: Output Compare 0 RA Register
|
||||
|
||||
// OCR0RAH: Output Compare 0 RA Register
|
||||
OCR0RA_OCR0RA = 0xfff // Output Compare RA
|
||||
|
||||
// OCR0SAL: Output Compare 0 SA Register
|
||||
|
||||
// OCR0SAH: Output Compare 0 SA Register
|
||||
OCR0SA_OCR0SA = 0xfff // Output Compare SA
|
||||
|
||||
// PSOC0: PSC0 Synchro and Output Configuration
|
||||
PSOC0_PSYNC0 = 0x30 // Synchronization Out for ADC Selection
|
||||
PSOC0_POEN0B = 0x4 // PSCOUT01 Output Enable
|
||||
PSOC0_POEN0A = 0x1 // PSCOUT00 Output Enable
|
||||
|
||||
// PIM0: PSC0 Interrupt Mask Register
|
||||
PIM0_PSEIE0 = 0x20 // PSC 0 Synchro Error Interrupt Enable
|
||||
PIM0_PEVE0B = 0x10 // External Event B Interrupt Enable
|
||||
PIM0_PEVE0A = 0x8 // External Event A Interrupt Enable
|
||||
PIM0_PEOPE0 = 0x1 // End of Cycle Interrupt Enable
|
||||
|
||||
// PIFR0: PSC0 Interrupt Flag Register
|
||||
PIFR0_POAC0B = 0x80 // PSC 0 Output A Activity
|
||||
PIFR0_POAC0A = 0x40 // PSC 0 Output A Activity
|
||||
PIFR0_PSEI0 = 0x20 // PSC 0 Synchro Error Interrupt
|
||||
PIFR0_PEV0B = 0x10 // External Event B Interrupt
|
||||
PIFR0_PEV0A = 0x8 // External Event A Interrupt
|
||||
PIFR0_PRN0 = 0x6 // Ramp Number
|
||||
PIFR0_PEOP0 = 0x1 // End of PSC0 Interrupt
|
||||
|
||||
// PICR2L: PSC 2 Input Capture Register
|
||||
|
||||
// PICR2H: PSC 2 Input Capture Register
|
||||
PICR2_PCST2 = 0x8000 // PSC 2 Input Capture Software Trig
|
||||
PICR2_PICR2 = 0xfff // PSC 2 Input Capture Bytes
|
||||
|
||||
// PFRC2B: PSC 2 Input B Control
|
||||
PFRC2B_PCAE2B = 0x80 // PSC 2 Capture Enable Input Part B
|
||||
PFRC2B_PISEL2B = 0x40 // PSC 2 Input Select for Part B
|
||||
PFRC2B_PELEV2B = 0x20 // PSC 2 Edge Level Selector on Input Part B
|
||||
PFRC2B_PFLTE2B = 0x10 // PSC 2 Filter Enable on Input Part B
|
||||
PFRC2B_PRFM2B = 0xf // PSC 2 Retrigger and Fault Mode for Part B
|
||||
|
||||
// PFRC2A: PSC 2 Input B Control
|
||||
PFRC2A_PCAE2A = 0x80 // PSC 2 Capture Enable Input Part A
|
||||
PFRC2A_PISEL2A = 0x40 // PSC 2 Input Select for Part A
|
||||
PFRC2A_PELEV2A = 0x20 // PSC 2 Edge Level Selector on Input Part A
|
||||
PFRC2A_PFLTE2A = 0x10 // PSC 2 Filter Enable on Input Part A
|
||||
PFRC2A_PRFM2A = 0xf // PSC 2 Retrigger and Fault Mode for Part A
|
||||
|
||||
// PCTL2: PSC 2 Control Register
|
||||
PCTL2_PPRE2 = 0xc0 // PSC 2 Prescaler Selects
|
||||
PCTL2_PBFM2 = 0x20 // Balance Flank Width Modulation
|
||||
PCTL2_PAOC2B = 0x10 // PSC 2 Asynchronous Output Control B
|
||||
PCTL2_PAOC2A = 0x8 // PSC 2 Asynchronous Output Control A
|
||||
PCTL2_PARUN2 = 0x4 // PSC2 Auto Run
|
||||
PCTL2_PCCYC2 = 0x2 // PSC2 Complete Cycle
|
||||
PCTL2_PRUN2 = 0x1 // PSC 2 Run
|
||||
|
||||
// PCNF2: PSC 2 Configuration Register
|
||||
PCNF2_PFIFTY2 = 0x80 // PSC 2 Fifty
|
||||
PCNF2_PALOCK2 = 0x40 // PSC 2 Autolock
|
||||
PCNF2_PLOCK2 = 0x20 // PSC 2 Lock
|
||||
PCNF2_PMODE2 = 0x18 // PSC 2 Mode
|
||||
PCNF2_POP2 = 0x4 // PSC 2 Output Polarity
|
||||
PCNF2_PCLKSEL2 = 0x2 // PSC 2 Input Clock Select
|
||||
PCNF2_POME2 = 0x1 // PSC 2 Output Matrix Enable
|
||||
|
||||
// OCR2RBL: Output Compare 2 RB Register
|
||||
|
||||
// OCR2RBH: Output Compare 2 RB Register
|
||||
OCR2RB_OCR2RB = 0xffff // Output Compare RB
|
||||
|
||||
// OCR2SBL: Output Compare 2 SB Register
|
||||
|
||||
// OCR2SBH: Output Compare 2 SB Register
|
||||
OCR2SB_OCR2SB = 0xfff // Output Compare SB
|
||||
|
||||
// OCR2RAL: Output Compare 2 RA Register
|
||||
|
||||
// OCR2RAH: Output Compare 2 RA Register
|
||||
OCR2RA_OCR2RA = 0xfff // Output Compare RA
|
||||
|
||||
// OCR2SAL: Output Compare 2 SA Register
|
||||
|
||||
// OCR2SAH: Output Compare 2 SA Register
|
||||
OCR2SA_OCR2SA = 0xfff // Output Compare SA
|
||||
|
||||
// POM2: PSC 2 Output Matrix
|
||||
POM2_POMV2B = 0xf0 // Output Matrix Output B Ramps
|
||||
POM2_POMV2A = 0xf // Output Matrix Output A Ramps
|
||||
|
||||
// PSOC2: PSC2 Synchro and Output Configuration
|
||||
PSOC2_POS2 = 0xc0 // PSC 2 Output 23 Select
|
||||
PSOC2_PSYNC2_ = 0x30 // Synchronization Out for ADC Selection
|
||||
PSOC2_POEN2D = 0x8 // PSCOUT23 Output Enable
|
||||
PSOC2_POEN2B = 0x4 // PSCOUT21 Output Enable
|
||||
PSOC2_POEN2C = 0x2 // PSCOUT22 Output Enable
|
||||
PSOC2_POEN2A = 0x1 // PSCOUT20 Output Enable
|
||||
|
||||
// PIM2: PSC2 Interrupt Mask Register
|
||||
PIM2_PSEIE2 = 0x20 // PSC 2 Synchro Error Interrupt Enable
|
||||
PIM2_PEVE2B = 0x10 // External Event B Interrupt Enable
|
||||
PIM2_PEVE2A = 0x8 // External Event A Interrupt Enable
|
||||
PIM2_PEOPE2 = 0x1 // End of Cycle Interrupt Enable
|
||||
|
||||
// PIFR2: PSC2 Interrupt Flag Register
|
||||
PIFR2_POAC2B = 0x80 // PSC 2 Output A Activity
|
||||
PIFR2_POAC2A = 0x40 // PSC 2 Output A Activity
|
||||
PIFR2_PSEI2 = 0x20 // PSC 2 Synchro Error Interrupt
|
||||
PIFR2_PEV2B = 0x10 // External Event B Interrupt
|
||||
PIFR2_PEV2A = 0x8 // External Event A Interrupt
|
||||
PIFR2_PRN2 = 0x6 // Ramp Number
|
||||
PIFR2_PEOP2 = 0x1 // End of PSC2 Interrupt
|
||||
)
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from AT90PWM2B.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x2000;
|
||||
__ram_size = 0x200;
|
||||
__num_isrs = 32;
|
||||
Различия файлов не показаны, т.к. их слишком много
Показать различия
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from AT90PWM316.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x4000;
|
||||
__ram_size = 0x400;
|
||||
__num_isrs = 32;
|
||||
Различия файлов не показаны, т.к. их слишком много
Показать различия
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from AT90PWM3B.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x2000;
|
||||
__ram_size = 0x200;
|
||||
__num_isrs = 32;
|
||||
|
|
@ -1,832 +0,0 @@
|
|||
// Automatically generated file. DO NOT EDIT.
|
||||
// Generated by gen-device.py from AT90PWM81.atdf, see http://packs.download.atmel.com/
|
||||
|
||||
// +build avr,at90pwm81
|
||||
|
||||
// Device information for the AT90PWM81.
|
||||
//
|
||||
package avr
|
||||
|
||||
// Magic type name for the compiler.
|
||||
type __reg uint8
|
||||
|
||||
// Export this magic type name.
|
||||
type RegValue = __reg
|
||||
|
||||
// Some information about this device.
|
||||
const (
|
||||
DEVICE = "AT90PWM81"
|
||||
ARCH = "AVR8"
|
||||
FAMILY = "megaAVR"
|
||||
)
|
||||
|
||||
// Interrupts
|
||||
const (
|
||||
IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset
|
||||
IRQ_PSC2_CAPT = 1 // PSC2 Capture Event
|
||||
IRQ_PSC2_EC = 2 // PSC2 End Cycle
|
||||
IRQ_PSC2_EEC = 3 // PSC2 End Of Enhanced Cycle
|
||||
IRQ_PSC0_CAPT = 4 // PSC0 Capture Event
|
||||
IRQ_PSC0_EC = 5 // PSC0 End Cycle
|
||||
IRQ_PSC0_EEC = 6 // PSC0 End Of Enhanced Cycle
|
||||
IRQ_ANALOG_COMP_1 = 7 // Analog Comparator 1
|
||||
IRQ_ANALOG_COMP_2 = 8 // Analog Comparator 2
|
||||
IRQ_ANALOG_COMP_3 = 9 // Analog Comparator 3
|
||||
IRQ_INT0 = 10 // External Interrupt Request 0
|
||||
IRQ_TIMER1_CAPT = 11 // Timer/Counter1 Capture Event
|
||||
IRQ_TIMER1_OVF = 12 // Timer/Counter1 Overflow
|
||||
IRQ_ADC = 13 // ADC Conversion Complete
|
||||
IRQ_INT1 = 14 // External Interrupt Request 1
|
||||
IRQ_SPI_STC = 15 // SPI Serial Transfer Complet
|
||||
IRQ_INT2 = 16 // External Interrupt Request 2
|
||||
IRQ_WDT = 17 // Watchdog Timeout Interrupt
|
||||
IRQ_EE_READY = 18 // EEPROM Ready
|
||||
IRQ_SPM_READY = 19 // Store Program Memory Read
|
||||
IRQ_max = 19 // Highest interrupt number on this device.
|
||||
)
|
||||
|
||||
// Peripherals
|
||||
var (
|
||||
// Fuses
|
||||
FUSE = struct {
|
||||
EXTENDED __reg
|
||||
HIGH __reg
|
||||
LOW __reg
|
||||
}{
|
||||
EXTENDED: 0x2,
|
||||
HIGH: 0x1,
|
||||
LOW: 0x0,
|
||||
}
|
||||
|
||||
// Lockbits
|
||||
LOCKBIT = struct {
|
||||
LOCKBIT __reg
|
||||
}{
|
||||
LOCKBIT: 0x0,
|
||||
}
|
||||
|
||||
// I/O Port
|
||||
PORT = struct {
|
||||
PORTB __reg
|
||||
DDRB __reg
|
||||
PINB __reg
|
||||
PORTD __reg
|
||||
DDRD __reg
|
||||
PIND __reg
|
||||
PORTE __reg
|
||||
DDRE __reg
|
||||
PINE __reg
|
||||
}{
|
||||
PORTB: 0x25, // Port B Data Register
|
||||
DDRB: 0x24, // Port B Data Direction Register
|
||||
PINB: 0x23, // Port B Input Pins
|
||||
PORTD: 0x2b, // Port D Data Register
|
||||
DDRD: 0x2a, // Port D Data Direction Register
|
||||
PIND: 0x29, // Port D Input Pins
|
||||
PORTE: 0x2e, // Port E Data Register
|
||||
DDRE: 0x2d, // Port E Data Direction Register
|
||||
PINE: 0x2c, // Port E Input Pins
|
||||
}
|
||||
|
||||
// Digital-to-Analog Converter
|
||||
DAC = struct {
|
||||
DACL __reg
|
||||
DACH __reg
|
||||
DACON __reg
|
||||
}{
|
||||
DACL: 0x58, // DAC Data Register
|
||||
DACH: 0x58, // DAC Data Register
|
||||
DACON: 0x76, // DAC Control Register
|
||||
}
|
||||
|
||||
// Serial Peripheral Interface
|
||||
SPI = struct {
|
||||
SPCR __reg
|
||||
SPSR __reg
|
||||
SPDR __reg
|
||||
}{
|
||||
SPCR: 0x37, // SPI Control Register
|
||||
SPSR: 0x38, // SPI Status Register
|
||||
SPDR: 0x56, // SPI Data Register
|
||||
}
|
||||
|
||||
// Watchdog Timer
|
||||
WDT = struct {
|
||||
WDTCSR __reg
|
||||
}{
|
||||
WDTCSR: 0x82, // Watchdog Timer Control Register
|
||||
}
|
||||
|
||||
// External Interrupts
|
||||
EXINT = struct {
|
||||
EICRA __reg
|
||||
EIMSK __reg
|
||||
EIFR __reg
|
||||
}{
|
||||
EICRA: 0x89, // External Interrupt Control Register A
|
||||
EIMSK: 0x41, // External Interrupt Mask Register
|
||||
EIFR: 0x40, // External Interrupt Flag Register
|
||||
}
|
||||
|
||||
// Analog-to-Digital Converter
|
||||
ADC = struct {
|
||||
ADMUX __reg
|
||||
ADCSRA __reg
|
||||
ADCL __reg
|
||||
ADCH __reg
|
||||
ADCSRB __reg
|
||||
DIDR0 __reg
|
||||
DIDR1 __reg
|
||||
AMP0CSR __reg
|
||||
}{
|
||||
ADMUX: 0x28, // The ADC multiplexer Selection Register
|
||||
ADCSRA: 0x26, // The ADC Control and Status register
|
||||
ADCL: 0x4c, // ADC Data Register Bytes
|
||||
ADCH: 0x4c, // ADC Data Register Bytes
|
||||
ADCSRB: 0x27, // ADC Control and Status Register B
|
||||
DIDR0: 0x77, // Digital Input Disable Register 0
|
||||
DIDR1: 0x78, // Digital Input Disable Register 1
|
||||
AMP0CSR: 0x79,
|
||||
}
|
||||
|
||||
// Analog Comparator
|
||||
AC = struct {
|
||||
AC3CON __reg
|
||||
AC1CON __reg
|
||||
AC2CON __reg
|
||||
ACSR __reg
|
||||
AC3ECON __reg
|
||||
AC2ECON __reg
|
||||
AC1ECON __reg
|
||||
}{
|
||||
AC3CON: 0x7f, // Analog Comparator3 Control Register
|
||||
AC1CON: 0x7d, // Analog Comparator 1 Control Register
|
||||
AC2CON: 0x7e, // Analog Comparator 2 Control Register
|
||||
ACSR: 0x20, // Analog Comparator Status Register
|
||||
AC3ECON: 0x7c,
|
||||
AC2ECON: 0x7b,
|
||||
AC1ECON: 0x7a,
|
||||
}
|
||||
|
||||
// CPU Registers
|
||||
CPU = struct {
|
||||
SREG __reg
|
||||
SPL __reg
|
||||
SPH __reg
|
||||
MCUCR __reg
|
||||
MCUSR __reg
|
||||
OSCCAL __reg
|
||||
CLKPR __reg
|
||||
SMCR __reg
|
||||
GPIOR2 __reg
|
||||
GPIOR1 __reg
|
||||
GPIOR0 __reg
|
||||
PLLCSR __reg
|
||||
PRR __reg
|
||||
CLKCSR __reg
|
||||
CLKSELR __reg
|
||||
BGCCR __reg
|
||||
BGCRR __reg
|
||||
}{
|
||||
SREG: 0x5f, // Status Register
|
||||
SPL: 0x5d, // Stack Pointer
|
||||
SPH: 0x5d, // Stack Pointer
|
||||
MCUCR: 0x55, // MCU Control Register
|
||||
MCUSR: 0x54, // MCU Status Register
|
||||
OSCCAL: 0x88, // Oscillator Calibration Value
|
||||
CLKPR: 0x83,
|
||||
SMCR: 0x53, // Sleep Mode Control Register
|
||||
GPIOR2: 0x3b, // General Purpose IO Register 2
|
||||
GPIOR1: 0x3a, // General Purpose IO Register 1
|
||||
GPIOR0: 0x39, // General Purpose IO Register 0
|
||||
PLLCSR: 0x87, // PLL Control And Status Register
|
||||
PRR: 0x86, // Power Reduction Register
|
||||
CLKCSR: 0x84,
|
||||
CLKSELR: 0x85,
|
||||
BGCCR: 0x81, // BandGap Current Calibration Register
|
||||
BGCRR: 0x80, // BandGap Resistor Calibration Register
|
||||
}
|
||||
|
||||
// EEPROM
|
||||
EEPROM = struct {
|
||||
EEARL __reg
|
||||
EEARH __reg
|
||||
EEDR __reg
|
||||
EECR __reg
|
||||
}{
|
||||
EEARL: 0x3e, // EEPROM Read/Write Access Bytes
|
||||
EEARH: 0x3e, // EEPROM Read/Write Access Bytes
|
||||
EEDR: 0x3d, // EEPROM Data Register
|
||||
EECR: 0x3c, // EEPROM Control Register
|
||||
}
|
||||
|
||||
// Power Stage Controller
|
||||
PSC = struct {
|
||||
PICR0L __reg
|
||||
PICR0H __reg
|
||||
PFRC0B __reg
|
||||
PFRC0A __reg
|
||||
PCTL0 __reg
|
||||
PCNF0 __reg
|
||||
OCR0RBL __reg
|
||||
OCR0RBH __reg
|
||||
OCR0SBL __reg
|
||||
OCR0SBH __reg
|
||||
OCR0RAL __reg
|
||||
OCR0RAH __reg
|
||||
OCR0SAL __reg
|
||||
OCR0SAH __reg
|
||||
PSOC0 __reg
|
||||
PIM0 __reg
|
||||
PIFR0 __reg
|
||||
PICR2L __reg
|
||||
PICR2H __reg
|
||||
PFRC2B __reg
|
||||
PFRC2A __reg
|
||||
PCTL2 __reg
|
||||
PCNF2 __reg
|
||||
PCNFE2 __reg
|
||||
OCR2RBL __reg
|
||||
OCR2RBH __reg
|
||||
OCR2SBL __reg
|
||||
OCR2SBH __reg
|
||||
OCR2RAL __reg
|
||||
OCR2RAH __reg
|
||||
OCR2SAL __reg
|
||||
OCR2SAH __reg
|
||||
POM2 __reg
|
||||
PSOC2 __reg
|
||||
PIM2 __reg
|
||||
PIFR2 __reg
|
||||
PASDLY2 __reg
|
||||
}{
|
||||
PICR0L: 0x68, // PSC 0 Input Capture Register
|
||||
PICR0H: 0x68, // PSC 0 Input Capture Register
|
||||
PFRC0B: 0x63, // PSC 0 Input B Control
|
||||
PFRC0A: 0x62, // PSC 0 Input A Control
|
||||
PCTL0: 0x32, // PSC 0 Control Register
|
||||
PCNF0: 0x31, // PSC 0 Configuration Register
|
||||
OCR0RBL: 0x44, // Output Compare RB Register
|
||||
OCR0RBH: 0x44, // Output Compare RB Register
|
||||
OCR0SBL: 0x42, // Output Compare SB Register
|
||||
OCR0SBH: 0x42, // Output Compare SB Register
|
||||
OCR0RAL: 0x4a, // Output Compare RA Register
|
||||
OCR0RAH: 0x4a, // Output Compare RA Register
|
||||
OCR0SAL: 0x60, // Output Compare SA Register
|
||||
OCR0SAH: 0x60, // Output Compare SA Register
|
||||
PSOC0: 0x6a, // PSC0 Synchro and Output Configuration
|
||||
PIM0: 0x2f, // PSC0 Interrupt Mask Register
|
||||
PIFR0: 0x30, // PSC0 Interrupt Flag Register
|
||||
PICR2L: 0x6c, // PSC 2 Input Capture Register
|
||||
PICR2H: 0x6c, // PSC 2 Input Capture Register
|
||||
PFRC2B: 0x67, // PSC 2 Input B Control
|
||||
PFRC2A: 0x66, // PSC 2 Input B Control
|
||||
PCTL2: 0x36, // PSC 2 Control Register
|
||||
PCNF2: 0x35, // PSC 2 Configuration Register
|
||||
PCNFE2: 0x70, // PSC 2 Enhanced Configuration Register
|
||||
OCR2RBL: 0x48, // Output Compare RB Register
|
||||
OCR2RBH: 0x48, // Output Compare RB Register
|
||||
OCR2SBL: 0x46, // Output Compare SB Register
|
||||
OCR2SBH: 0x46, // Output Compare SB Register
|
||||
OCR2RAL: 0x4e, // Output Compare RA Register
|
||||
OCR2RAH: 0x4e, // Output Compare RA Register
|
||||
OCR2SAL: 0x64, // Output Compare SA Register
|
||||
OCR2SAH: 0x64, // Output Compare SA Register
|
||||
POM2: 0x6f, // PSC 2 Output Matrix
|
||||
PSOC2: 0x6e, // PSC2 Synchro and Output Configuration
|
||||
PIM2: 0x33, // PSC2 Interrupt Mask Register
|
||||
PIFR2: 0x34, // PSC2 Interrupt Flag Register
|
||||
PASDLY2: 0x71, // Analog Synchronization Delay Register
|
||||
}
|
||||
|
||||
// Timer/Counter, 16-bit
|
||||
TC16 = struct {
|
||||
TIMSK1 __reg
|
||||
TIFR1 __reg
|
||||
TCCR1B __reg
|
||||
TCNT1L __reg
|
||||
TCNT1H __reg
|
||||
ICR1L __reg
|
||||
ICR1H __reg
|
||||
}{
|
||||
TIMSK1: 0x21, // Timer/Counter Interrupt Mask Register
|
||||
TIFR1: 0x22, // Timer/Counter Interrupt Flag register
|
||||
TCCR1B: 0x8a, // Timer/Counter1 Control Register B
|
||||
TCNT1L: 0x5a, // Timer/Counter1 Bytes
|
||||
TCNT1H: 0x5a, // Timer/Counter1 Bytes
|
||||
ICR1L: 0x8c, // Timer/Counter1 Input Capture Register Bytes
|
||||
ICR1H: 0x8c, // Timer/Counter1 Input Capture Register Bytes
|
||||
}
|
||||
|
||||
// Bootloader
|
||||
BOOT_LOAD = struct {
|
||||
SPMCSR __reg
|
||||
}{
|
||||
SPMCSR: 0x57, // Store Program Memory Control Register
|
||||
}
|
||||
)
|
||||
|
||||
// Bitfields for FUSE: Fuses
|
||||
const (
|
||||
// EXTENDED
|
||||
EXTENDED_PSC2RB = 0x80 // PSC2 Reset Behavior
|
||||
EXTENDED_PSC2RBA = 0x40 // PSC2 Reset Behavior for 22 and 23
|
||||
EXTENDED_PSC0RB = 0x20 // PSC0 Reset Behavior
|
||||
EXTENDED_PSCRV = 0x10 // PSC Reset Value
|
||||
EXTENDED_PSCINRB = 0x8 // PSC2 and PSC0 input Reset Behavior
|
||||
EXTENDED_BODLEVEL = 0x7 // Brown-out Detector Trigger Level
|
||||
|
||||
// HIGH
|
||||
HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PE0 as I/O pin)
|
||||
HIGH_DWEN = 0x40 // Debug Wire enable
|
||||
HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled
|
||||
HIGH_WDTON = 0x10 // Watch-dog Timer always on
|
||||
HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle
|
||||
HIGH_BOOTSZ = 0x6 // Select Boot Size
|
||||
HIGH_BOOTRST = 0x1 // Select Reset Vector
|
||||
|
||||
// LOW
|
||||
LOW_CKDIV8 = 0x80 // Divide clock by 8 internally
|
||||
LOW_CKOUT = 0x40 // Clock output on PORTD1
|
||||
LOW_SUT_CKSEL = 0x3f // Select Clock Source
|
||||
)
|
||||
|
||||
// Bitfields for LOCKBIT: Lockbits
|
||||
const (
|
||||
// LOCKBIT
|
||||
LOCKBIT_LB = 0x3 // Memory Lock
|
||||
LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode
|
||||
LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode
|
||||
)
|
||||
|
||||
// Bitfields for DAC: Digital-to-Analog Converter
|
||||
const (
|
||||
// DACL: DAC Data Register
|
||||
|
||||
// DACH: DAC Data Register
|
||||
DAC_DACH = 0x3ff // DAC Data Register Bits
|
||||
|
||||
// DACON: DAC Control Register
|
||||
DACON_DAATE = 0x80 // DAC Auto Trigger Enable Bit
|
||||
DACON_DATS = 0x70 // DAC Trigger Selection Bits
|
||||
DACON_DALA = 0x4 // DAC Left Adjust
|
||||
DACON_DAEN = 0x1 // DAC Enable Bit
|
||||
)
|
||||
|
||||
// Bitfields for SPI: Serial Peripheral Interface
|
||||
const (
|
||||
// SPCR: SPI Control Register
|
||||
SPCR_SPIE = 0x80 // SPI Interrupt Enable
|
||||
SPCR_SPE = 0x40 // SPI Enable
|
||||
SPCR_DORD = 0x20 // Data Order
|
||||
SPCR_MSTR = 0x10 // Master/Slave Select
|
||||
SPCR_CPOL = 0x8 // Clock polarity
|
||||
SPCR_CPHA = 0x4 // Clock Phase
|
||||
SPCR_SPR = 0x3 // SPI Clock Rate Selects
|
||||
|
||||
// SPSR: SPI Status Register
|
||||
SPSR_SPIF = 0x80 // SPI Interrupt Flag
|
||||
SPSR_WCOL = 0x40 // Write Collision Flag
|
||||
SPSR_SPI2X = 0x1 // Double SPI Speed Bit
|
||||
|
||||
// SPDR: SPI Data Register
|
||||
SPDR_SPD = 0xff // SPI Data bits
|
||||
)
|
||||
|
||||
// Bitfields for WDT: Watchdog Timer
|
||||
const (
|
||||
// WDTCSR: Watchdog Timer Control Register
|
||||
WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag
|
||||
WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable
|
||||
WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits
|
||||
WDTCSR_WDCE = 0x10 // Watchdog Change Enable
|
||||
WDTCSR_WDE = 0x8 // Watch Dog Enable
|
||||
)
|
||||
|
||||
// Bitfields for EXINT: External Interrupts
|
||||
const (
|
||||
// EICRA: External Interrupt Control Register A
|
||||
EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit
|
||||
EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit
|
||||
EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit
|
||||
|
||||
// EIMSK: External Interrupt Mask Register
|
||||
EIMSK_INT = 0x7 // External Interrupt Request 2 Enable
|
||||
|
||||
// EIFR: External Interrupt Flag Register
|
||||
EIFR_INTF = 0x7 // External Interrupt Flags
|
||||
)
|
||||
|
||||
// Bitfields for ADC: Analog-to-Digital Converter
|
||||
const (
|
||||
// ADMUX: The ADC multiplexer Selection Register
|
||||
ADMUX_REFS = 0xc0 // Reference Selection Bits
|
||||
ADMUX_ADLAR = 0x20 // Left Adjust Result
|
||||
ADMUX_MUX = 0xf // Analog Channel and Gain Selection Bits
|
||||
|
||||
// ADCSRA: The ADC Control and Status register
|
||||
ADCSRA_ADEN = 0x80 // ADC Enable
|
||||
ADCSRA_ADSC = 0x40 // ADC Start Conversion
|
||||
ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable
|
||||
ADCSRA_ADIF = 0x10 // ADC Interrupt Flag
|
||||
ADCSRA_ADIE = 0x8 // ADC Interrupt Enable
|
||||
ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits
|
||||
|
||||
// ADCL: ADC Data Register Bytes
|
||||
|
||||
// ADCH: ADC Data Register Bytes
|
||||
ADC_ADC = 0xffff // ADC Data Register
|
||||
|
||||
// ADCSRB: ADC Control and Status Register B
|
||||
ADCSRB_ADHSM = 0x80 // ADC High Speed Mode
|
||||
ADCSRB_ADNCDIS = 0x40 // ADC Noise Canceller Disable
|
||||
ADCSRB_ADSSEN = 0x10 // ADC Single Shot Enable on PSC's Synchronisation Signals
|
||||
ADCSRB_ADTS = 0xf // ADC Auto Trigger Sources
|
||||
|
||||
// DIDR0: Digital Input Disable Register 0
|
||||
DIDR0_ADC8D = 0x80 // ADC8 Digital input Disable
|
||||
DIDR0_ADC7D = 0x40 // ADC7 Digital input Disable
|
||||
DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable
|
||||
DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable
|
||||
DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable
|
||||
DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable
|
||||
DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable
|
||||
DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable
|
||||
|
||||
// DIDR1: Digital Input Disable Register 1
|
||||
DIDR1_ACMP1MD = 0x8
|
||||
DIDR1_AMP0PD = 0x4
|
||||
DIDR1_ADC10D = 0x2 // ADC10 Digital input Disable
|
||||
DIDR1_ADC9D = 0x1 // ADC9 Digital input Disable
|
||||
|
||||
// AMP0CSR
|
||||
AMP0CSR_AMP0EN = 0x80
|
||||
AMP0CSR_AMP0IS = 0x40
|
||||
AMP0CSR_AMP0G = 0x30
|
||||
AMP0CSR_AMP0GS = 0x8
|
||||
AMP0CSR_AMP0TS = 0x3
|
||||
)
|
||||
|
||||
// Bitfields for AC: Analog Comparator
|
||||
const (
|
||||
// AC3CON: Analog Comparator3 Control Register
|
||||
AC3CON_AC3EN = 0x80 // Analog Comparator3 Enable Bit
|
||||
AC3CON_AC3IE = 0x40 // Analog Comparator 3 Interrupt Enable Bit
|
||||
AC3CON_AC3IS = 0x30 // Analog Comparator 3 Interrupt Select Bit
|
||||
AC3CON_AC3OEA = 0x8 // Analog Comparator 3 Alternate Output Enable
|
||||
AC3CON_AC3M = 0x7 // Analog Comparator 3 Multiplexer Register
|
||||
|
||||
// AC1CON: Analog Comparator 1 Control Register
|
||||
AC1CON_AC1EN = 0x80 // Analog Comparator 1 Enable Bit
|
||||
AC1CON_AC1IE = 0x40 // Analog Comparator 1 Interrupt Enable Bit
|
||||
AC1CON_AC1IS = 0x30 // Analog Comparator 1 Interrupt Select Bit
|
||||
AC1CON_AC1M = 0x7 // Analog Comparator 1 Multiplexer Register
|
||||
|
||||
// AC2CON: Analog Comparator 2 Control Register
|
||||
AC2CON_AC2EN = 0x80 // Analog Comparator 2 Enable Bit
|
||||
AC2CON_AC2IE = 0x40 // Analog Comparator 2 Interrupt Enable Bit
|
||||
AC2CON_AC2IS = 0x30 // Analog Comparator 2 Interrupt Select Bit
|
||||
AC2CON_AC2M = 0x7 // Analog Comparator 2 Multiplexer Register
|
||||
|
||||
// ACSR: Analog Comparator Status Register
|
||||
ACSR_AC3IF = 0x80 // Analog Comparator 3 Interrupt Flag Bit
|
||||
ACSR_AC2IF = 0x40 // Analog Comparator 2 Interrupt Flag Bit
|
||||
ACSR_AC1IF = 0x20 // Analog Comparator 1 Interrupt Flag Bit
|
||||
ACSR_AC3O = 0x8 // Analog Comparator 3 Output Bit
|
||||
ACSR_AC2O = 0x4 // Analog Comparator 2 Output Bit
|
||||
ACSR_AC1O = 0x2 // Analog Comparator 1 Output Bit
|
||||
|
||||
// AC3ECON
|
||||
AC3ECON_AC3OI = 0x20 // Analog Comparator Ouput Invert
|
||||
AC3ECON_AC3OE = 0x10 // Analog Comparator Ouput Enable
|
||||
AC3ECON_AC3H = 0x7 // Analog Comparator Hysteresis Select
|
||||
|
||||
// AC2ECON
|
||||
AC2ECON_AC2OI = 0x20 // Analog Comparator Ouput Invert
|
||||
AC2ECON_AC2OE = 0x10 // Analog Comparator Ouput Enable
|
||||
AC2ECON_AC2H = 0x7 // Analog Comparator Hysteresis Select
|
||||
|
||||
// AC1ECON
|
||||
AC1ECON_AC1OI = 0x20 // Analog Comparator Ouput Invert
|
||||
AC1ECON_AC1OE = 0x10 // Analog Comparator Ouput Enable
|
||||
AC1ECON_AC1ICE = 0x8 // Analog Comparator Interrupt Capture Enable
|
||||
AC1ECON_AC1H = 0x7 // Analog Comparator Hysteresis Select
|
||||
)
|
||||
|
||||
// Bitfields for CPU: CPU Registers
|
||||
const (
|
||||
// SREG: Status Register
|
||||
SREG_I = 0x80 // Global Interrupt Enable
|
||||
SREG_T = 0x40 // Bit Copy Storage
|
||||
SREG_H = 0x20 // Half Carry Flag
|
||||
SREG_S = 0x10 // Sign Bit
|
||||
SREG_V = 0x8 // Two's Complement Overflow Flag
|
||||
SREG_N = 0x4 // Negative Flag
|
||||
SREG_Z = 0x2 // Zero Flag
|
||||
SREG_C = 0x1 // Carry Flag
|
||||
|
||||
// MCUCR: MCU Control Register
|
||||
MCUCR_PUD = 0x10 // Pull-up disable
|
||||
MCUCR_RSTDIS = 0x8 // Reset Pin Disable
|
||||
MCUCR_CKRC81 = 0x4 // Frequency Selection of the Calibrated RC Oscillator
|
||||
MCUCR_IVSEL = 0x2 // Interrupt Vector Select
|
||||
MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable
|
||||
|
||||
// MCUSR: MCU Status Register
|
||||
MCUSR_WDRF = 0x8 // Watchdog Reset Flag
|
||||
MCUSR_BORF = 0x4 // Brown-out Reset Flag
|
||||
MCUSR_EXTRF = 0x2 // External Reset Flag
|
||||
MCUSR_PORF = 0x1 // Power-on reset flag
|
||||
|
||||
// OSCCAL: Oscillator Calibration Value
|
||||
OSCCAL_OSCCAL = 0xff // Oscillator Calibration
|
||||
|
||||
// CLKPR
|
||||
CLKPR_CLKPCE = 0x80
|
||||
CLKPR_CLKPS = 0xf
|
||||
|
||||
// SMCR: Sleep Mode Control Register
|
||||
SMCR_SM = 0xe // Sleep Mode Select bits
|
||||
SMCR_SE = 0x1 // Sleep Enable
|
||||
|
||||
// GPIOR2: General Purpose IO Register 2
|
||||
GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis
|
||||
|
||||
// GPIOR1: General Purpose IO Register 1
|
||||
GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis
|
||||
|
||||
// GPIOR0: General Purpose IO Register 0
|
||||
GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7
|
||||
GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6
|
||||
GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5
|
||||
GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4
|
||||
GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3
|
||||
GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2
|
||||
GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1
|
||||
GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0
|
||||
|
||||
// PLLCSR: PLL Control And Status Register
|
||||
PLLCSR_PLLF = 0x3c
|
||||
PLLCSR_PLLE = 0x2 // PLL Enable
|
||||
PLLCSR_PLOCK = 0x1 // PLL Lock Detector
|
||||
|
||||
// PRR: Power Reduction Register
|
||||
PRR_PRPSC2 = 0x80 // Power Reduction PSC2
|
||||
PRR_PRPSCR = 0x20 // Power Reduction PSC0
|
||||
PRR_PRTIM1 = 0x10 // Power Reduction Timer/Counter1
|
||||
PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface
|
||||
PRR_PRADC = 0x1 // Power Reduction ADC
|
||||
|
||||
// CLKCSR
|
||||
CLKCSR_CLKCCE = 0x80 // Clock Control Change Enable
|
||||
CLKCSR_CLKRDY = 0x10 // Clock Ready Flag
|
||||
CLKCSR_CLKC = 0xf // Clock Control
|
||||
|
||||
// CLKSELR
|
||||
CLKSELR_COUT = 0x40 // Clock OUT
|
||||
CLKSELR_CSUT = 0x30 // Clock Start up Time
|
||||
CLKSELR_CKSEL = 0xf // Clock Source Select
|
||||
|
||||
// BGCCR: BandGap Current Calibration Register
|
||||
BGCCR_BGCC = 0xf
|
||||
|
||||
// BGCRR: BandGap Resistor Calibration Register
|
||||
BGCRR_BGCR = 0xf
|
||||
)
|
||||
|
||||
// Bitfields for EEPROM: EEPROM
|
||||
const (
|
||||
// EEARL: EEPROM Read/Write Access Bytes
|
||||
|
||||
// EEARH: EEPROM Read/Write Access Bytes
|
||||
EEAR_EEAR = 0x1ff // EEPROM Address bytes
|
||||
|
||||
// EEDR: EEPROM Data Register
|
||||
EEDR_EEDR = 0xff // EEPROM Data bits
|
||||
|
||||
// EECR: EEPROM Control Register
|
||||
EECR_NVMBSY = 0x80 // None Volatile Busy Memory Busy
|
||||
EECR_EEPAGE = 0x40 // EEPROM Page Access
|
||||
EECR_EEPM = 0x30 // EEPROM Programming Mode
|
||||
EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable
|
||||
EECR_EEMWE = 0x4 // EEPROM Master Write Enable
|
||||
EECR_EEWE = 0x2 // EEPROM Write Enable
|
||||
EECR_EERE = 0x1 // EEPROM Read Enable
|
||||
)
|
||||
|
||||
// Bitfields for PSC: Power Stage Controller
|
||||
const (
|
||||
// PICR0L: PSC 0 Input Capture Register
|
||||
|
||||
// PICR0H: PSC 0 Input Capture Register
|
||||
PICR0_PCST0 = 0x8000 // PSC 0 Capture Software Trigger Bit
|
||||
PICR0_PICR0 = 0xfff // PSC 0 Input Capture Bytes
|
||||
|
||||
// PFRC0B: PSC 0 Input B Control
|
||||
PFRC0B_PCAE0B = 0x80 // PSC 0 Capture Enable Input Part B
|
||||
PFRC0B_PISEL0B = 0x40 // PSC 0 Input Select for Part B
|
||||
PFRC0B_PELEV0B = 0x20 // PSC 0 Edge Level Selector on Input Part B
|
||||
PFRC0B_PFLTE0B = 0x10 // PSC 0 Filter Enable on Input Part B
|
||||
PFRC0B_PRFM0B = 0xf // PSC 0 Retrigger and Fault Mode for Part B
|
||||
|
||||
// PFRC0A: PSC 0 Input A Control
|
||||
PFRC0A_PCAE0A = 0x80 // PSC 0 Capture Enable Input Part A
|
||||
PFRC0A_PISEL0A = 0x40 // PSC 0 Input Select for Part A
|
||||
PFRC0A_PELEV0A = 0x20 // PSC 0 Edge Level Selector on Input Part A
|
||||
PFRC0A_PFLTE0A = 0x10 // PSC 0 Filter Enable on Input Part A
|
||||
PFRC0A_PRFM0A = 0xf // PSC 0 Retrigger and Fault Mode for Part A
|
||||
|
||||
// PCTL0: PSC 0 Control Register
|
||||
PCTL0_PPRE0 = 0xc0 // PSC 0 Prescaler Selects
|
||||
PCTL0_PBFM0 = 0x24 // PSC 0 Balance Flank Width Modulation
|
||||
PCTL0_PAOC0B = 0x10 // PSC 0 Asynchronous Output Control B
|
||||
PCTL0_PAOC0A = 0x8 // PSC 0 Asynchronous Output Control A
|
||||
PCTL0_PCCYC0 = 0x2 // PSC0 Complete Cycle
|
||||
PCTL0_PRUN0 = 0x1 // PSC 0 Run
|
||||
|
||||
// PCNF0: PSC 0 Configuration Register
|
||||
PCNF0_PFIFTY0 = 0x80 // PSC 0 Fifty
|
||||
PCNF0_PALOCK0 = 0x40 // PSC 0 Autolock
|
||||
PCNF0_PLOCK0 = 0x20 // PSC 0 Lock
|
||||
PCNF0_PMODE0 = 0x18 // PSC 0 Mode
|
||||
PCNF0_POP0 = 0x4 // PSC 0 Output Polarity
|
||||
PCNF0_PCLKSEL0 = 0x2 // PSC 0 Input Clock Select
|
||||
|
||||
// OCR0RBL: Output Compare RB Register
|
||||
|
||||
// OCR0RBH: Output Compare RB Register
|
||||
OCR0RB_OCR0RB = 0xffff // Output Compare 0 RB
|
||||
|
||||
// OCR0SBL: Output Compare SB Register
|
||||
|
||||
// OCR0SBH: Output Compare SB Register
|
||||
OCR0SB_OCR0SB = 0xfff // Output Compare 0 SB
|
||||
|
||||
// OCR0RAL: Output Compare RA Register
|
||||
|
||||
// OCR0RAH: Output Compare RA Register
|
||||
OCR0RA_OCR0RA = 0xfff // Output Compare 0 RA
|
||||
|
||||
// OCR0SAL: Output Compare SA Register
|
||||
|
||||
// OCR0SAH: Output Compare SA Register
|
||||
OCR0SA_OCR0SA = 0xfff // Output Compare 0 SA
|
||||
|
||||
// PSOC0: PSC0 Synchro and Output Configuration
|
||||
PSOC0_PISEL0A1 = 0x80 // PSC Input Select
|
||||
PSOC0_PISEL0B1 = 0x40 // PSC Input Select
|
||||
PSOC0_PSYNC0 = 0x30 // Synchronisation out for ADC selection
|
||||
PSOC0_POEN0B = 0x4 // PSCOUT01 Output Enable
|
||||
PSOC0_POEN0A = 0x1 // PSCOUT00 Output Enable
|
||||
|
||||
// PIM0: PSC0 Interrupt Mask Register
|
||||
PIM0_PEVE0B = 0x10 // External Event B Interrupt Enable
|
||||
PIM0_PEVE0A = 0x8 // External Event A Interrupt Enable
|
||||
PIM0_PEOEPE0 = 0x2 // End of Enhanced Cycle Enable
|
||||
PIM0_PEOPE0 = 0x1 // End of Cycle Interrupt Enable
|
||||
|
||||
// PIFR0: PSC0 Interrupt Flag Register
|
||||
PIFR0_POAC0B = 0x80 // PSC 0 Output A Activity
|
||||
PIFR0_POAC0A = 0x40 // PSC 0 Output A Activity
|
||||
PIFR0_PEV0B = 0x10 // External Event B Interrupt
|
||||
PIFR0_PEV0A = 0x8 // External Event A Interrupt
|
||||
PIFR0_PRN0 = 0x6 // Ramp Number
|
||||
PIFR0_PEOP0 = 0x1 // End of PSC0 Interrupt
|
||||
|
||||
// PICR2L: PSC 2 Input Capture Register
|
||||
|
||||
// PICR2H: PSC 2 Input Capture Register
|
||||
PICR2_PCST2 = 0x8000 // PSC 2 Capture Software Trigger Bit
|
||||
PICR2_PICR2 = 0xfff // PSC 2 Input Capture Bytes
|
||||
|
||||
// PFRC2B: PSC 2 Input B Control
|
||||
PFRC2B_PCAE2B = 0x80 // PSC 2 Capture Enable Input Part B
|
||||
PFRC2B_PISEL2B = 0x40 // PSC 2 Input Select for Part B
|
||||
PFRC2B_PELEV2B = 0x20 // PSC 2 Edge Level Selector on Input Part B
|
||||
PFRC2B_PFLTE2B = 0x10 // PSC 2 Filter Enable on Input Part B
|
||||
PFRC2B_PRFM2B = 0xf // PSC 2 Retrigger and Fault Mode for Part B
|
||||
|
||||
// PFRC2A: PSC 2 Input B Control
|
||||
PFRC2A_PCAE2A = 0x80 // PSC 2 Capture Enable Input Part A
|
||||
PFRC2A_PISEL2A = 0x40 // PSC 2 Input Select for Part A
|
||||
PFRC2A_PELEV2A = 0x20 // PSC 2 Edge Level Selector on Input Part A
|
||||
PFRC2A_PFLTE2A = 0x10 // PSC 2 Filter Enable on Input Part A
|
||||
PFRC2A_PRFM2A = 0xf // PSC 2 Retrigger and Fault Mode for Part A
|
||||
|
||||
// PCTL2: PSC 2 Control Register
|
||||
PCTL2_PPRE2 = 0xc0 // PSC 2 Prescaler Selects
|
||||
PCTL2_PBFM2 = 0x20 // Balance Flank Width Modulation
|
||||
PCTL2_PAOC2B = 0x10 // PSC 2 Asynchronous Output Control B
|
||||
PCTL2_PAOC2A = 0x8 // PSC 2 Asynchronous Output Control A
|
||||
PCTL2_PARUN2 = 0x4 // PSC2 Auto Run
|
||||
PCTL2_PCCYC2 = 0x2 // PSC2 Complete Cycle
|
||||
PCTL2_PRUN2 = 0x1 // PSC 2 Run
|
||||
|
||||
// PCNF2: PSC 2 Configuration Register
|
||||
PCNF2_PFIFTY2 = 0x80 // PSC 2 Fifty
|
||||
PCNF2_PALOCK2 = 0x40 // PSC 2 Autolock
|
||||
PCNF2_PLOCK2 = 0x20 // PSC 2 Lock
|
||||
PCNF2_PMODE2 = 0x18 // PSC 2 Mode
|
||||
PCNF2_POP2 = 0x4 // PSC 2 Output Polarity
|
||||
PCNF2_PCLKSEL2 = 0x2 // PSC 2 Input Clock Select
|
||||
PCNF2_POME2 = 0x1 // PSC 2 Output Matrix Enable
|
||||
|
||||
// PCNFE2: PSC 2 Enhanced Configuration Register
|
||||
PCNFE2_PASDLK2 = 0xe0
|
||||
PCNFE2_PBFM21 = 0x10
|
||||
PCNFE2_PELEV2A1 = 0x8
|
||||
PCNFE2_PELEV2B1 = 0x4
|
||||
PCNFE2_PISEL2A1 = 0x2
|
||||
PCNFE2_PISEL2B1 = 0x1
|
||||
|
||||
// OCR2RBL: Output Compare RB Register
|
||||
|
||||
// OCR2RBH: Output Compare RB Register
|
||||
OCR2RB_OCR2RB = 0xffff // Output Compare 2 RB
|
||||
|
||||
// OCR2SBL: Output Compare SB Register
|
||||
|
||||
// OCR2SBH: Output Compare SB Register
|
||||
OCR2SB_OCR2SB = 0xfff // Output Compare 2 SB
|
||||
|
||||
// OCR2RAL: Output Compare RA Register
|
||||
|
||||
// OCR2RAH: Output Compare RA Register
|
||||
OCR2RA_OCR2RA = 0xfff // Output Compare 2 RA
|
||||
|
||||
// OCR2SAL: Output Compare SA Register
|
||||
|
||||
// OCR2SAH: Output Compare SA Register
|
||||
OCR2SA_OCR2SA = 0xfff // Output Compare 2 SA
|
||||
|
||||
// POM2: PSC 2 Output Matrix
|
||||
POM2_POMV2B = 0xf0 // Output Matrix Output B Ramps
|
||||
POM2_POMV2A = 0xf // Output Matrix Output A Ramps
|
||||
|
||||
// PSOC2: PSC2 Synchro and Output Configuration
|
||||
PSOC2_POS2 = 0xc0 // PSC 2 Output 23 Select
|
||||
PSOC2_PSYNC2 = 0x30 // Synchronization Out for ADC Selection
|
||||
PSOC2_POEN2D = 0x8 // PSCOUT23 Output Enable
|
||||
PSOC2_POEN2B = 0x4 // PSCOUT21 Output Enable
|
||||
PSOC2_POEN2C = 0x2 // PSCOUT22 Output Enable
|
||||
PSOC2_POEN2A = 0x1 // PSCOUT20 Output Enable
|
||||
|
||||
// PIM2: PSC2 Interrupt Mask Register
|
||||
PIM2_PSEIE2 = 0x20 // PSC 2 Synchro Error Interrupt Enable
|
||||
PIM2_PEVE2B = 0x10 // External Event B Interrupt Enable
|
||||
PIM2_PEVE2A = 0x8 // External Event A Interrupt Enable
|
||||
PIM2_PEOEPE2 = 0x2 // End of Enhanced Cycle Interrupt Enable
|
||||
PIM2_PEOPE2 = 0x1 // End of Cycle Interrupt Enable
|
||||
|
||||
// PIFR2: PSC2 Interrupt Flag Register
|
||||
PIFR2_POAC2B = 0x80 // PSC 2 Output A Activity
|
||||
PIFR2_POAC2A = 0x40 // PSC 2 Output A Activity
|
||||
PIFR2_PSEI2 = 0x20 // PSC 2 Synchro Error Interrupt
|
||||
PIFR2_PEV2B = 0x10 // External Event B Interrupt
|
||||
PIFR2_PEV2A = 0x8 // External Event A Interrupt
|
||||
PIFR2_PRN2 = 0x6 // Ramp Number
|
||||
PIFR2_PEOP2 = 0x1 // End of PSC2 Interrupt
|
||||
|
||||
// PASDLY2: Analog Synchronization Delay Register
|
||||
PASDLY2_PASDLY2 = 0xff // Analog Synchronization Delay bits
|
||||
)
|
||||
|
||||
// Bitfields for TC16: Timer/Counter, 16-bit
|
||||
const (
|
||||
// TIMSK1: Timer/Counter Interrupt Mask Register
|
||||
TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable
|
||||
TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable
|
||||
|
||||
// TIFR1: Timer/Counter Interrupt Flag register
|
||||
TIFR1_ICF1 = 0x20 // Input Capture Flag 1
|
||||
TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag
|
||||
|
||||
// TCCR1B: Timer/Counter1 Control Register B
|
||||
TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler
|
||||
TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select
|
||||
TCCR1B_WGM13 = 0x10 // Waveform Generation Mode
|
||||
TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1
|
||||
|
||||
// TCNT1L: Timer/Counter1 Bytes
|
||||
|
||||
// TCNT1H: Timer/Counter1 Bytes
|
||||
TCNT1_TCNT1 = 0xffff // Timer/Counter 1 bits
|
||||
|
||||
// ICR1L: Timer/Counter1 Input Capture Register Bytes
|
||||
|
||||
// ICR1H: Timer/Counter1 Input Capture Register Bytes
|
||||
ICR1_ICR1 = 0xffff // Timer/Counter1 Input Capture bits
|
||||
)
|
||||
|
||||
// Bitfields for BOOT_LOAD: Bootloader
|
||||
const (
|
||||
// SPMCSR: Store Program Memory Control Register
|
||||
SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable
|
||||
SPMCSR_RWWSB = 0x40 // Read While Write Section Busy
|
||||
SPMCSR_SIGRD = 0x20 // Signature Row Read
|
||||
SPMCSR_RWWSRE = 0x10 // Read While Write section read enable
|
||||
SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set
|
||||
SPMCSR_PGWRT = 0x4 // Page Write
|
||||
SPMCSR_PGERS = 0x2 // Page Erase
|
||||
SPMCSR_SPMEN = 0x1 // Store Program Memory Enable
|
||||
)
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from AT90PWM81.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x2000;
|
||||
__ram_size = 0x100;
|
||||
__num_isrs = 20;
|
||||
|
|
@ -1,952 +0,0 @@
|
|||
// Automatically generated file. DO NOT EDIT.
|
||||
// Generated by gen-device.py from AT90USB1286.atdf, see http://packs.download.atmel.com/
|
||||
|
||||
// +build avr,at90usb1286
|
||||
|
||||
// Device information for the AT90USB1286.
|
||||
//
|
||||
package avr
|
||||
|
||||
// Magic type name for the compiler.
|
||||
type __reg uint8
|
||||
|
||||
// Export this magic type name.
|
||||
type RegValue = __reg
|
||||
|
||||
// Some information about this device.
|
||||
const (
|
||||
DEVICE = "AT90USB1286"
|
||||
ARCH = "AVR8"
|
||||
FAMILY = "megaAVR"
|
||||
)
|
||||
|
||||
// Interrupts
|
||||
const (
|
||||
IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet.
|
||||
IRQ_INT0 = 1 // External Interrupt Request 0
|
||||
IRQ_INT1 = 2 // External Interrupt Request 1
|
||||
IRQ_INT2 = 3 // External Interrupt Request 2
|
||||
IRQ_INT3 = 4 // External Interrupt Request 3
|
||||
IRQ_INT4 = 5 // External Interrupt Request 4
|
||||
IRQ_INT5 = 6 // External Interrupt Request 5
|
||||
IRQ_INT6 = 7 // External Interrupt Request 6
|
||||
IRQ_INT7 = 8 // External Interrupt Request 7
|
||||
IRQ_PCINT0 = 9 // Pin Change Interrupt Request 0
|
||||
IRQ_USB_GEN = 10 // USB General Interrupt Request
|
||||
IRQ_USB_COM = 11 // USB Endpoint/Pipe Interrupt Communication Request
|
||||
IRQ_WDT = 12 // Watchdog Time-out Interrupt
|
||||
IRQ_TIMER2_COMPA = 13 // Timer/Counter2 Compare Match A
|
||||
IRQ_TIMER2_COMPB = 14 // Timer/Counter2 Compare Match B
|
||||
IRQ_TIMER2_OVF = 15 // Timer/Counter2 Overflow
|
||||
IRQ_TIMER1_CAPT = 16 // Timer/Counter1 Capture Event
|
||||
IRQ_TIMER1_COMPA = 17 // Timer/Counter1 Compare Match A
|
||||
IRQ_TIMER1_COMPB = 18 // Timer/Counter1 Compare Match B
|
||||
IRQ_TIMER1_COMPC = 19 // Timer/Counter1 Compare Match C
|
||||
IRQ_TIMER1_OVF = 20 // Timer/Counter1 Overflow
|
||||
IRQ_TIMER0_COMPA = 21 // Timer/Counter0 Compare Match A
|
||||
IRQ_TIMER0_COMPB = 22 // Timer/Counter0 Compare Match B
|
||||
IRQ_TIMER0_OVF = 23 // Timer/Counter0 Overflow
|
||||
IRQ_SPI_STC = 24 // SPI Serial Transfer Complete
|
||||
IRQ_USART1_RX = 25 // USART1, Rx Complete
|
||||
IRQ_USART1_UDRE = 26 // USART1 Data register Empty
|
||||
IRQ_USART1_TX = 27 // USART1, Tx Complete
|
||||
IRQ_ANALOG_COMP = 28 // Analog Comparator
|
||||
IRQ_ADC = 29 // ADC Conversion Complete
|
||||
IRQ_EE_READY = 30 // EEPROM Ready
|
||||
IRQ_TIMER3_CAPT = 31 // Timer/Counter3 Capture Event
|
||||
IRQ_TIMER3_COMPA = 32 // Timer/Counter3 Compare Match A
|
||||
IRQ_TIMER3_COMPB = 33 // Timer/Counter3 Compare Match B
|
||||
IRQ_TIMER3_COMPC = 34 // Timer/Counter3 Compare Match C
|
||||
IRQ_TIMER3_OVF = 35 // Timer/Counter3 Overflow
|
||||
IRQ_TWI = 36 // 2-wire Serial Interface
|
||||
IRQ_SPM_READY = 37 // Store Program Memory Read
|
||||
IRQ_max = 37 // Highest interrupt number on this device.
|
||||
)
|
||||
|
||||
// Peripherals
|
||||
var (
|
||||
// Fuses
|
||||
FUSE = struct {
|
||||
EXTENDED __reg
|
||||
HIGH __reg
|
||||
LOW __reg
|
||||
}{
|
||||
EXTENDED: 0x2,
|
||||
HIGH: 0x1,
|
||||
LOW: 0x0,
|
||||
}
|
||||
|
||||
// Lockbits
|
||||
LOCKBIT = struct {
|
||||
LOCKBIT __reg
|
||||
}{
|
||||
LOCKBIT: 0x0,
|
||||
}
|
||||
|
||||
// Watchdog Timer
|
||||
WDT = struct {
|
||||
WDTCSR __reg
|
||||
}{
|
||||
WDTCSR: 0x60, // Watchdog Timer Control Register
|
||||
}
|
||||
|
||||
// I/O Port
|
||||
PORT = struct {
|
||||
PORTA __reg
|
||||
DDRA __reg
|
||||
PINA __reg
|
||||
PORTB __reg
|
||||
DDRB __reg
|
||||
PINB __reg
|
||||
PORTC __reg
|
||||
DDRC __reg
|
||||
PINC __reg
|
||||
PORTD __reg
|
||||
DDRD __reg
|
||||
PIND __reg
|
||||
PORTE __reg
|
||||
DDRE __reg
|
||||
PINE __reg
|
||||
PORTF __reg
|
||||
DDRF __reg
|
||||
PINF __reg
|
||||
}{
|
||||
PORTA: 0x22, // Port A Data Register
|
||||
DDRA: 0x21, // Port A Data Direction Register
|
||||
PINA: 0x20, // Port A Input Pins
|
||||
PORTB: 0x25, // Port B Data Register
|
||||
DDRB: 0x24, // Port B Data Direction Register
|
||||
PINB: 0x23, // Port B Input Pins
|
||||
PORTC: 0x28, // Port C Data Register
|
||||
DDRC: 0x27, // Port C Data Direction Register
|
||||
PINC: 0x26, // Port C Input Pins
|
||||
PORTD: 0x2b, // Port D Data Register
|
||||
DDRD: 0x2a, // Port D Data Direction Register
|
||||
PIND: 0x29, // Port D Input Pins
|
||||
PORTE: 0x2e, // Data Register, Port E
|
||||
DDRE: 0x2d, // Data Direction Register, Port E
|
||||
PINE: 0x2c, // Input Pins, Port E
|
||||
PORTF: 0x31, // Data Register, Port F
|
||||
DDRF: 0x30, // Data Direction Register, Port F
|
||||
PINF: 0x2f, // Input Pins, Port F
|
||||
}
|
||||
|
||||
// CPU Registers
|
||||
CPU = struct {
|
||||
SREG __reg
|
||||
SPL __reg
|
||||
SPH __reg
|
||||
XMCRA __reg
|
||||
XMCRB __reg
|
||||
OSCCAL __reg
|
||||
CLKPR __reg
|
||||
SMCR __reg
|
||||
EIND __reg
|
||||
RAMPZ __reg
|
||||
GPIOR2 __reg
|
||||
GPIOR1 __reg
|
||||
GPIOR0 __reg
|
||||
PRR1 __reg
|
||||
PRR0 __reg
|
||||
}{
|
||||
SREG: 0x5f, // Status Register
|
||||
SPL: 0x5d, // Stack Pointer
|
||||
SPH: 0x5d, // Stack Pointer
|
||||
XMCRA: 0x74, // External Memory Control Register A
|
||||
XMCRB: 0x75, // External Memory Control Register B
|
||||
OSCCAL: 0x66, // Oscillator Calibration Value
|
||||
CLKPR: 0x61,
|
||||
SMCR: 0x53, // Sleep Mode Control Register
|
||||
EIND: 0x5c, // Extended Indirect Register
|
||||
RAMPZ: 0x5b, // RAM Page Z Select Register
|
||||
GPIOR2: 0x4b, // General Purpose IO Register 2
|
||||
GPIOR1: 0x4a, // General Purpose IO Register 1
|
||||
GPIOR0: 0x3e, // General Purpose IO Register 0
|
||||
PRR1: 0x65, // Power Reduction Register1
|
||||
PRR0: 0x64, // Power Reduction Register0
|
||||
}
|
||||
|
||||
// Two Wire Serial Interface
|
||||
TWI = struct {
|
||||
TWAMR __reg
|
||||
TWBR __reg
|
||||
TWCR __reg
|
||||
TWSR __reg
|
||||
TWDR __reg
|
||||
TWAR __reg
|
||||
}{
|
||||
TWAMR: 0xbd, // TWI (Slave) Address Mask Register
|
||||
TWBR: 0xb8, // TWI Bit Rate register
|
||||
TWCR: 0xbc, // TWI Control Register
|
||||
TWSR: 0xb9, // TWI Status Register
|
||||
TWDR: 0xbb, // TWI Data register
|
||||
TWAR: 0xba, // TWI (Slave) Address register
|
||||
}
|
||||
|
||||
// Serial Peripheral Interface
|
||||
SPI = struct {
|
||||
SPCR __reg
|
||||
SPSR __reg
|
||||
SPDR __reg
|
||||
}{
|
||||
SPCR: 0x4c, // SPI Control Register
|
||||
SPSR: 0x4d, // SPI Status Register
|
||||
SPDR: 0x4e, // SPI Data Register
|
||||
}
|
||||
|
||||
// USART
|
||||
USART = struct {
|
||||
UDR1 __reg
|
||||
UCSR1A __reg
|
||||
UCSR1B __reg
|
||||
UCSR1C __reg
|
||||
UBRR1L __reg
|
||||
UBRR1H __reg
|
||||
}{
|
||||
UDR1: 0xce, // USART I/O Data Register
|
||||
UCSR1A: 0xc8, // USART Control and Status Register A
|
||||
UCSR1B: 0xc9, // USART Control and Status Register B
|
||||
UCSR1C: 0xca, // USART Control and Status Register C
|
||||
UBRR1L: 0xcc, // USART Baud Rate Register Bytes
|
||||
UBRR1H: 0xcc, // USART Baud Rate Register Bytes
|
||||
}
|
||||
|
||||
// USB Device Registers
|
||||
USB_DEVICE = struct {
|
||||
UEINT __reg
|
||||
UEBCHX __reg
|
||||
UEBCLX __reg
|
||||
UEDATX __reg
|
||||
UEIENX __reg
|
||||
UESTA1X __reg
|
||||
UESTA0X __reg
|
||||
UECFG1X __reg
|
||||
UECFG0X __reg
|
||||
UECONX __reg
|
||||
UERST __reg
|
||||
UENUM __reg
|
||||
UEINTX __reg
|
||||
UDMFN __reg
|
||||
UDFNUML __reg
|
||||
UDFNUMH __reg
|
||||
UDADDR __reg
|
||||
UDIEN __reg
|
||||
UDINT __reg
|
||||
UDCON __reg
|
||||
}{
|
||||
UEINT: 0xf4,
|
||||
UEBCHX: 0xf3,
|
||||
UEBCLX: 0xf2,
|
||||
UEDATX: 0xf1,
|
||||
UEIENX: 0xf0,
|
||||
UESTA1X: 0xef,
|
||||
UESTA0X: 0xee,
|
||||
UECFG1X: 0xed,
|
||||
UECFG0X: 0xec,
|
||||
UECONX: 0xeb,
|
||||
UERST: 0xea,
|
||||
UENUM: 0xe9,
|
||||
UEINTX: 0xe8,
|
||||
UDMFN: 0xe6,
|
||||
UDFNUML: 0xe4,
|
||||
UDFNUMH: 0xe4,
|
||||
UDADDR: 0xe3,
|
||||
UDIEN: 0xe2,
|
||||
UDINT: 0xe1,
|
||||
UDCON: 0xe0,
|
||||
}
|
||||
|
||||
// Bootloader
|
||||
BOOT_LOAD = struct {
|
||||
SPMCSR __reg
|
||||
}{
|
||||
SPMCSR: 0x57, // Store Program Memory Control Register
|
||||
}
|
||||
|
||||
// EEPROM
|
||||
EEPROM = struct {
|
||||
EEARL __reg
|
||||
EEARH __reg
|
||||
EEDR __reg
|
||||
EECR __reg
|
||||
}{
|
||||
EEARL: 0x41, // EEPROM Address Register Low Bytes
|
||||
EEARH: 0x41, // EEPROM Address Register Low Bytes
|
||||
EEDR: 0x40, // EEPROM Data Register
|
||||
EECR: 0x3f, // EEPROM Control Register
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit
|
||||
TC8 = struct {
|
||||
OCR0B __reg
|
||||
OCR0A __reg
|
||||
TCNT0 __reg
|
||||
TCCR0B __reg
|
||||
TCCR0A __reg
|
||||
TIMSK0 __reg
|
||||
TIFR0 __reg
|
||||
}{
|
||||
OCR0B: 0x48, // Timer/Counter0 Output Compare Register
|
||||
OCR0A: 0x47, // Timer/Counter0 Output Compare Register
|
||||
TCNT0: 0x46, // Timer/Counter0
|
||||
TCCR0B: 0x45, // Timer/Counter Control Register B
|
||||
TCCR0A: 0x44, // Timer/Counter Control Register A
|
||||
TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register
|
||||
TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit Async
|
||||
TC8_ASYNC = struct {
|
||||
TIMSK2 __reg
|
||||
TIFR2 __reg
|
||||
TCCR2A __reg
|
||||
TCCR2B __reg
|
||||
TCNT2 __reg
|
||||
OCR2B __reg
|
||||
OCR2A __reg
|
||||
ASSR __reg
|
||||
}{
|
||||
TIMSK2: 0x70, // Timer/Counter Interrupt Mask register
|
||||
TIFR2: 0x37, // Timer/Counter Interrupt Flag Register
|
||||
TCCR2A: 0xb0, // Timer/Counter2 Control Register A
|
||||
TCCR2B: 0xb1, // Timer/Counter2 Control Register B
|
||||
TCNT2: 0xb2, // Timer/Counter2
|
||||
OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B
|
||||
OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A
|
||||
ASSR: 0xb6, // Asynchronous Status Register
|
||||
}
|
||||
|
||||
// Timer/Counter, 16-bit
|
||||
TC16 = struct {
|
||||
TCCR3A __reg
|
||||
TCCR3B __reg
|
||||
TCCR3C __reg
|
||||
TCNT3L __reg
|
||||
TCNT3H __reg
|
||||
OCR3AL __reg
|
||||
OCR3AH __reg
|
||||
OCR3BL __reg
|
||||
OCR3BH __reg
|
||||
OCR3CL __reg
|
||||
OCR3CH __reg
|
||||
ICR3L __reg
|
||||
ICR3H __reg
|
||||
TIMSK3 __reg
|
||||
TIFR3 __reg
|
||||
TCCR1A __reg
|
||||
TCCR1B __reg
|
||||
TCCR1C __reg
|
||||
TCNT1L __reg
|
||||
TCNT1H __reg
|
||||
OCR1AL __reg
|
||||
OCR1AH __reg
|
||||
OCR1BL __reg
|
||||
OCR1BH __reg
|
||||
OCR1CL __reg
|
||||
OCR1CH __reg
|
||||
ICR1L __reg
|
||||
ICR1H __reg
|
||||
TIMSK1 __reg
|
||||
TIFR1 __reg
|
||||
}{
|
||||
TCCR3A: 0x90, // Timer/Counter3 Control Register A
|
||||
TCCR3B: 0x91, // Timer/Counter3 Control Register B
|
||||
TCCR3C: 0x92, // Timer/Counter 3 Control Register C
|
||||
TCNT3L: 0x94, // Timer/Counter3 Bytes
|
||||
TCNT3H: 0x94, // Timer/Counter3 Bytes
|
||||
OCR3AL: 0x98, // Timer/Counter3 Output Compare Register A Bytes
|
||||
OCR3AH: 0x98, // Timer/Counter3 Output Compare Register A Bytes
|
||||
OCR3BL: 0x9a, // Timer/Counter3 Output Compare Register B Bytes
|
||||
OCR3BH: 0x9a, // Timer/Counter3 Output Compare Register B Bytes
|
||||
OCR3CL: 0x9c, // Timer/Counter3 Output Compare Register B Bytes
|
||||
OCR3CH: 0x9c, // Timer/Counter3 Output Compare Register B Bytes
|
||||
ICR3L: 0x96, // Timer/Counter3 Input Capture Register Bytes
|
||||
ICR3H: 0x96, // Timer/Counter3 Input Capture Register Bytes
|
||||
TIMSK3: 0x71, // Timer/Counter3 Interrupt Mask Register
|
||||
TIFR3: 0x38, // Timer/Counter3 Interrupt Flag register
|
||||
TCCR1A: 0x80, // Timer/Counter1 Control Register A
|
||||
TCCR1B: 0x81, // Timer/Counter1 Control Register B
|
||||
TCCR1C: 0x82, // Timer/Counter 1 Control Register C
|
||||
TCNT1L: 0x84, // Timer/Counter1 Bytes
|
||||
TCNT1H: 0x84, // Timer/Counter1 Bytes
|
||||
OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes
|
||||
OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes
|
||||
OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes
|
||||
OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes
|
||||
OCR1CL: 0x8c, // Timer/Counter1 Output Compare Register C Bytes
|
||||
OCR1CH: 0x8c, // Timer/Counter1 Output Compare Register C Bytes
|
||||
ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register
|
||||
TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register
|
||||
}
|
||||
|
||||
// JTAG Interface
|
||||
JTAG = struct {
|
||||
OCDR __reg
|
||||
}{
|
||||
OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory
|
||||
}
|
||||
|
||||
// External Interrupts
|
||||
EXINT = struct {
|
||||
EICRA __reg
|
||||
EICRB __reg
|
||||
EIMSK __reg
|
||||
EIFR __reg
|
||||
PCMSK0 __reg
|
||||
PCIFR __reg
|
||||
PCICR __reg
|
||||
}{
|
||||
EICRA: 0x69, // External Interrupt Control Register A
|
||||
EICRB: 0x6a, // External Interrupt Control Register B
|
||||
EIMSK: 0x3d, // External Interrupt Mask Register
|
||||
EIFR: 0x3c, // External Interrupt Flag Register
|
||||
PCMSK0: 0x6b, // Pin Change Mask Register 0
|
||||
PCIFR: 0x3b, // Pin Change Interrupt Flag Register
|
||||
PCICR: 0x68, // Pin Change Interrupt Control Register
|
||||
}
|
||||
|
||||
// Analog-to-Digital Converter
|
||||
ADC = struct {
|
||||
ADMUX __reg
|
||||
ADCSRA __reg
|
||||
ADCL __reg
|
||||
ADCH __reg
|
||||
DIDR0 __reg
|
||||
}{
|
||||
ADMUX: 0x7c, // The ADC multiplexer Selection Register
|
||||
ADCSRA: 0x7a, // The ADC Control and Status register
|
||||
ADCL: 0x78, // ADC Data Register Bytes
|
||||
ADCH: 0x78, // ADC Data Register Bytes
|
||||
DIDR0: 0x7e, // Digital Input Disable Register 1
|
||||
}
|
||||
|
||||
// Analog Comparator
|
||||
AC = struct {
|
||||
ACSR __reg
|
||||
DIDR1 __reg
|
||||
}{
|
||||
ACSR: 0x50, // Analog Comparator Control And Status Register
|
||||
DIDR1: 0x7f,
|
||||
}
|
||||
|
||||
// Phase Locked Loop
|
||||
PLL = struct {
|
||||
PLLCSR __reg
|
||||
}{
|
||||
PLLCSR: 0x49, // PLL Status and Control register
|
||||
}
|
||||
|
||||
// USB Controller
|
||||
USB_GLOBAL = struct {
|
||||
USBINT __reg
|
||||
USBSTA __reg
|
||||
USBCON __reg
|
||||
UHWCON __reg
|
||||
}{
|
||||
USBINT: 0xda,
|
||||
USBSTA: 0xd9,
|
||||
USBCON: 0xd8, // USB General Control Register
|
||||
UHWCON: 0xd7, // USB Hardware Configuration Register
|
||||
}
|
||||
)
|
||||
|
||||
// Bitfields for FUSE: Fuses
|
||||
const (
|
||||
// EXTENDED
|
||||
EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level
|
||||
EXTENDED_HWBE = 0x8 // Hardware Boot Enable
|
||||
|
||||
// HIGH
|
||||
HIGH_OCDEN = 0x80 // On-Chip Debug Enabled
|
||||
HIGH_JTAGEN = 0x40 // JTAG Interface Enabled
|
||||
HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled
|
||||
HIGH_WDTON = 0x10 // Watchdog timer always on
|
||||
HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle
|
||||
HIGH_BOOTSZ = 0x6 // Select Boot Size
|
||||
HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled
|
||||
|
||||
// LOW
|
||||
LOW_CKDIV8 = 0x80 // Divide clock by 8 internally
|
||||
LOW_CKOUT = 0x40 // Clock output on PORTC7
|
||||
LOW_SUT_CKSEL = 0x3f // Select Clock Source
|
||||
)
|
||||
|
||||
// Bitfields for LOCKBIT: Lockbits
|
||||
const (
|
||||
// LOCKBIT
|
||||
LOCKBIT_LB = 0x3 // Memory Lock
|
||||
LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode
|
||||
LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode
|
||||
)
|
||||
|
||||
// Bitfields for WDT: Watchdog Timer
|
||||
const (
|
||||
// WDTCSR: Watchdog Timer Control Register
|
||||
WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag
|
||||
WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable
|
||||
WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits
|
||||
WDTCSR_WDCE = 0x10 // Watchdog Change Enable
|
||||
WDTCSR_WDE = 0x8 // Watch Dog Enable
|
||||
)
|
||||
|
||||
// Bitfields for CPU: CPU Registers
|
||||
const (
|
||||
// SREG: Status Register
|
||||
SREG_I = 0x80 // Global Interrupt Enable
|
||||
SREG_T = 0x40 // Bit Copy Storage
|
||||
SREG_H = 0x20 // Half Carry Flag
|
||||
SREG_S = 0x10 // Sign Bit
|
||||
SREG_V = 0x8 // Two's Complement Overflow Flag
|
||||
SREG_N = 0x4 // Negative Flag
|
||||
SREG_Z = 0x2 // Zero Flag
|
||||
SREG_C = 0x1 // Carry Flag
|
||||
|
||||
// XMCRA: External Memory Control Register A
|
||||
XMCRA_SRE = 0x80 // External SRAM Enable
|
||||
XMCRA_SRL = 0x70 // Wait state page limit
|
||||
XMCRA_SRW1 = 0xc // Wait state select bit upper page
|
||||
XMCRA_SRW0 = 0x3 // Wait state select bit lower page
|
||||
|
||||
// XMCRB: External Memory Control Register B
|
||||
XMCRB_XMBK = 0x80 // External Memory Bus Keeper Enable
|
||||
XMCRB_XMM = 0x7 // External Memory High Mask
|
||||
|
||||
// OSCCAL: Oscillator Calibration Value
|
||||
OSCCAL_OSCCAL = 0xff // Oscillator Calibration
|
||||
|
||||
// CLKPR
|
||||
CLKPR_CLKPCE = 0x80
|
||||
CLKPR_CLKPS = 0xf
|
||||
|
||||
// SMCR: Sleep Mode Control Register
|
||||
SMCR_SM = 0xe // Sleep Mode Select bits
|
||||
SMCR_SE = 0x1 // Sleep Enable
|
||||
|
||||
// GPIOR2: General Purpose IO Register 2
|
||||
GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis
|
||||
|
||||
// GPIOR1: General Purpose IO Register 1
|
||||
GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis
|
||||
|
||||
// GPIOR0: General Purpose IO Register 0
|
||||
GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7
|
||||
GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6
|
||||
GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5
|
||||
GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4
|
||||
GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3
|
||||
GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2
|
||||
GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1
|
||||
GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0
|
||||
|
||||
// PRR1: Power Reduction Register1
|
||||
PRR1_PRUSB = 0x80 // Power Reduction USB
|
||||
PRR1_PRTIM3 = 0x8 // Power Reduction Timer/Counter3
|
||||
PRR1_PRUSART1 = 0x1 // Power Reduction USART1
|
||||
|
||||
// PRR0: Power Reduction Register0
|
||||
PRR0_PRTWI = 0x80 // Power Reduction TWI
|
||||
PRR0_PRTIM2 = 0x40 // Power Reduction Timer/Counter2
|
||||
PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0
|
||||
PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1
|
||||
PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface
|
||||
PRR0_PRADC = 0x1 // Power Reduction ADC
|
||||
)
|
||||
|
||||
// Bitfields for TWI: Two Wire Serial Interface
|
||||
const (
|
||||
// TWAMR: TWI (Slave) Address Mask Register
|
||||
TWAMR_TWAM = 0xfe
|
||||
|
||||
// TWCR: TWI Control Register
|
||||
TWCR_TWINT = 0x80 // TWI Interrupt Flag
|
||||
TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit
|
||||
TWCR_TWSTA = 0x20 // TWI Start Condition Bit
|
||||
TWCR_TWSTO = 0x10 // TWI Stop Condition Bit
|
||||
TWCR_TWWC = 0x8 // TWI Write Collition Flag
|
||||
TWCR_TWEN = 0x4 // TWI Enable Bit
|
||||
TWCR_TWIE = 0x1 // TWI Interrupt Enable
|
||||
|
||||
// TWSR: TWI Status Register
|
||||
TWSR_TWS = 0xf8 // TWI Status
|
||||
TWSR_TWPS = 0x3 // TWI Prescaler
|
||||
|
||||
// TWAR: TWI (Slave) Address register
|
||||
TWAR_TWA = 0xfe // TWI (Slave) Address register Bits
|
||||
TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit
|
||||
)
|
||||
|
||||
// Bitfields for SPI: Serial Peripheral Interface
|
||||
const (
|
||||
// SPCR: SPI Control Register
|
||||
SPCR_SPIE = 0x80 // SPI Interrupt Enable
|
||||
SPCR_SPE = 0x40 // SPI Enable
|
||||
SPCR_DORD = 0x20 // Data Order
|
||||
SPCR_MSTR = 0x10 // Master/Slave Select
|
||||
SPCR_CPOL = 0x8 // Clock polarity
|
||||
SPCR_CPHA = 0x4 // Clock Phase
|
||||
SPCR_SPR = 0x3 // SPI Clock Rate Selects
|
||||
|
||||
// SPSR: SPI Status Register
|
||||
SPSR_SPIF = 0x80 // SPI Interrupt Flag
|
||||
SPSR_WCOL = 0x40 // Write Collision Flag
|
||||
SPSR_SPI2X = 0x1 // Double SPI Speed Bit
|
||||
)
|
||||
|
||||
// Bitfields for USART: USART
|
||||
const (
|
||||
// UCSR1A: USART Control and Status Register A
|
||||
UCSR1A_RXC1 = 0x80 // USART Receive Complete
|
||||
UCSR1A_TXC1 = 0x40 // USART Transmitt Complete
|
||||
UCSR1A_UDRE1 = 0x20 // USART Data Register Empty
|
||||
UCSR1A_FE1 = 0x10 // Framing Error
|
||||
UCSR1A_DOR1 = 0x8 // Data overRun
|
||||
UCSR1A_UPE1 = 0x4 // Parity Error
|
||||
UCSR1A_U2X1 = 0x2 // Double the USART transmission speed
|
||||
UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode
|
||||
|
||||
// UCSR1B: USART Control and Status Register B
|
||||
UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable
|
||||
UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable
|
||||
UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable
|
||||
UCSR1B_RXEN1 = 0x10 // Receiver Enable
|
||||
UCSR1B_TXEN1 = 0x8 // Transmitter Enable
|
||||
UCSR1B_UCSZ12 = 0x4 // Character Size
|
||||
UCSR1B_RXB81 = 0x2 // Receive Data Bit 8
|
||||
UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8
|
||||
|
||||
// UCSR1C: USART Control and Status Register C
|
||||
UCSR1C_UMSEL1 = 0xc0 // USART Mode Select
|
||||
UCSR1C_UPM1 = 0x30 // Parity Mode Bits
|
||||
UCSR1C_USBS1 = 0x8 // Stop Bit Select
|
||||
UCSR1C_UCSZ1 = 0x6 // Character Size
|
||||
UCSR1C_UCPOL1 = 0x1 // Clock Polarity
|
||||
)
|
||||
|
||||
// Bitfields for USB_DEVICE: USB Device Registers
|
||||
const (
|
||||
// UEIENX
|
||||
UEIENX_FLERRE = 0x80
|
||||
UEIENX_NAKINE = 0x40
|
||||
UEIENX_NAKOUTE = 0x10
|
||||
UEIENX_RXSTPE = 0x8
|
||||
UEIENX_RXOUTE = 0x4
|
||||
UEIENX_STALLEDE = 0x2
|
||||
UEIENX_TXINE = 0x1
|
||||
|
||||
// UESTA1X
|
||||
UESTA1X_CTRLDIR = 0x4
|
||||
UESTA1X_CURRBK = 0x3
|
||||
|
||||
// UESTA0X
|
||||
UESTA0X_CFGOK = 0x80
|
||||
UESTA0X_OVERFI = 0x40
|
||||
UESTA0X_UNDERFI = 0x20
|
||||
UESTA0X_DTSEQ = 0xc
|
||||
UESTA0X_NBUSYBK = 0x3
|
||||
|
||||
// UECFG1X
|
||||
UECFG1X_EPSIZE = 0x70
|
||||
UECFG1X_EPBK = 0xc
|
||||
UECFG1X_ALLOC = 0x2
|
||||
|
||||
// UECFG0X
|
||||
UECFG0X_EPTYPE = 0xc0
|
||||
UECFG0X_EPDIR = 0x1
|
||||
|
||||
// UECONX
|
||||
UECONX_STALLRQ = 0x20
|
||||
UECONX_STALLRQC = 0x10
|
||||
UECONX_RSTDT = 0x8
|
||||
UECONX_EPEN = 0x1
|
||||
|
||||
// UERST
|
||||
UERST_EPRST = 0x7f
|
||||
|
||||
// UEINTX
|
||||
UEINTX_FIFOCON = 0x80
|
||||
UEINTX_NAKINI = 0x40
|
||||
UEINTX_RWAL = 0x20
|
||||
UEINTX_NAKOUTI = 0x10
|
||||
UEINTX_RXSTPI = 0x8
|
||||
UEINTX_RXOUTI = 0x4
|
||||
UEINTX_STALLEDI = 0x2
|
||||
UEINTX_TXINI = 0x1
|
||||
|
||||
// UDMFN
|
||||
UDMFN_FNCERR = 0x10
|
||||
|
||||
// UDADDR
|
||||
UDADDR_ADDEN = 0x80
|
||||
UDADDR_UADD = 0x7f
|
||||
|
||||
// UDIEN
|
||||
UDIEN_UPRSME = 0x40
|
||||
UDIEN_EORSME = 0x20
|
||||
UDIEN_WAKEUPE = 0x10
|
||||
UDIEN_EORSTE = 0x8
|
||||
UDIEN_SOFE = 0x4
|
||||
UDIEN_SUSPE = 0x1
|
||||
|
||||
// UDINT
|
||||
UDINT_UPRSMI = 0x40
|
||||
UDINT_EORSMI = 0x20
|
||||
UDINT_WAKEUPI = 0x10
|
||||
UDINT_EORSTI = 0x8
|
||||
UDINT_SOFI = 0x4
|
||||
UDINT_SUSPI = 0x1
|
||||
|
||||
// UDCON
|
||||
UDCON_LSM = 0x4
|
||||
UDCON_RMWKUP = 0x2
|
||||
UDCON_DETACH = 0x1
|
||||
)
|
||||
|
||||
// Bitfields for BOOT_LOAD: Bootloader
|
||||
const (
|
||||
// SPMCSR: Store Program Memory Control Register
|
||||
SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable
|
||||
SPMCSR_RWWSB = 0x40 // Read While Write Section Busy
|
||||
SPMCSR_SIGRD = 0x20 // Signature Row Read
|
||||
SPMCSR_RWWSRE = 0x10 // Read While Write section read enable
|
||||
SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set
|
||||
SPMCSR_PGWRT = 0x4 // Page Write
|
||||
SPMCSR_PGERS = 0x2 // Page Erase
|
||||
SPMCSR_SPMEN = 0x1 // Store Program Memory Enable
|
||||
)
|
||||
|
||||
// Bitfields for EEPROM: EEPROM
|
||||
const (
|
||||
// EECR: EEPROM Control Register
|
||||
EECR_EEPM = 0x30 // EEPROM Programming Mode Bits
|
||||
EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable
|
||||
EECR_EEMPE = 0x4 // EEPROM Master Write Enable
|
||||
EECR_EEPE = 0x2 // EEPROM Write Enable
|
||||
EECR_EERE = 0x1 // EEPROM Read Enable
|
||||
)
|
||||
|
||||
// Bitfields for TC8: Timer/Counter, 8-bit
|
||||
const (
|
||||
// TCCR0B: Timer/Counter Control Register B
|
||||
TCCR0B_FOC0A = 0x80 // Force Output Compare A
|
||||
TCCR0B_FOC0B = 0x40 // Force Output Compare B
|
||||
TCCR0B_WGM02 = 0x8
|
||||
TCCR0B_CS0 = 0x7 // Clock Select
|
||||
|
||||
// TCCR0A: Timer/Counter Control Register A
|
||||
TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode
|
||||
TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm
|
||||
TCCR0A_WGM0 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TIMSK0: Timer/Counter0 Interrupt Mask Register
|
||||
TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable
|
||||
TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable
|
||||
TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable
|
||||
|
||||
// TIFR0: Timer/Counter0 Interrupt Flag register
|
||||
TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B
|
||||
TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A
|
||||
TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag
|
||||
)
|
||||
|
||||
// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async
|
||||
const (
|
||||
// TIMSK2: Timer/Counter Interrupt Mask register
|
||||
TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable
|
||||
TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable
|
||||
TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable
|
||||
|
||||
// TIFR2: Timer/Counter Interrupt Flag Register
|
||||
TIFR2_OCF2B = 0x4 // Output Compare Flag 2B
|
||||
TIFR2_OCF2A = 0x2 // Output Compare Flag 2A
|
||||
TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag
|
||||
|
||||
// TCCR2A: Timer/Counter2 Control Register A
|
||||
TCCR2A_COM2A = 0xc0 // Compare Output Mode bits
|
||||
TCCR2A_COM2B = 0x30 // Compare Output Mode bits
|
||||
TCCR2A_WGM2 = 0x3 // Waveform Genration Mode
|
||||
|
||||
// TCCR2B: Timer/Counter2 Control Register B
|
||||
TCCR2B_FOC2A = 0x80 // Force Output Compare A
|
||||
TCCR2B_FOC2B = 0x40 // Force Output Compare B
|
||||
TCCR2B_WGM22 = 0x8 // Waveform Generation Mode
|
||||
TCCR2B_CS2 = 0x7 // Clock Select bits
|
||||
|
||||
// ASSR: Asynchronous Status Register
|
||||
ASSR_EXCLK = 0x40 // Enable External Clock Input
|
||||
ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2
|
||||
ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy
|
||||
ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy
|
||||
ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy
|
||||
ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy
|
||||
ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy
|
||||
)
|
||||
|
||||
// Bitfields for TC16: Timer/Counter, 16-bit
|
||||
const (
|
||||
// TCCR3A: Timer/Counter3 Control Register A
|
||||
TCCR3A_COM3A = 0xc0 // Compare Output Mode 1A, bits
|
||||
TCCR3A_COM3B = 0x30 // Compare Output Mode 3B, bits
|
||||
TCCR3A_COM3C = 0xc // Compare Output Mode 3C, bits
|
||||
TCCR3A_WGM3 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TCCR3B: Timer/Counter3 Control Register B
|
||||
TCCR3B_ICNC3 = 0x80 // Input Capture 3 Noise Canceler
|
||||
TCCR3B_ICES3 = 0x40 // Input Capture 3 Edge Select
|
||||
TCCR3B_WGM3 = 0x18 // Waveform Generation Mode
|
||||
TCCR3B_CS3 = 0x7 // Prescaler source of Timer/Counter 3
|
||||
|
||||
// TCCR3C: Timer/Counter 3 Control Register C
|
||||
TCCR3C_FOC3A = 0x80 // Force Output Compare 3A
|
||||
TCCR3C_FOC3B = 0x40 // Force Output Compare 3B
|
||||
TCCR3C_FOC3C = 0x20 // Force Output Compare 3C
|
||||
|
||||
// TIMSK3: Timer/Counter3 Interrupt Mask Register
|
||||
TIMSK3_ICIE3 = 0x20 // Timer/Counter3 Input Capture Interrupt Enable
|
||||
TIMSK3_OCIE3C = 0x8 // Timer/Counter3 Output Compare C Match Interrupt Enable
|
||||
TIMSK3_OCIE3B = 0x4 // Timer/Counter3 Output Compare B Match Interrupt Enable
|
||||
TIMSK3_OCIE3A = 0x2 // Timer/Counter3 Output Compare A Match Interrupt Enable
|
||||
TIMSK3_TOIE3 = 0x1 // Timer/Counter3 Overflow Interrupt Enable
|
||||
|
||||
// TIFR3: Timer/Counter3 Interrupt Flag register
|
||||
TIFR3_ICF3 = 0x20 // Input Capture Flag 3
|
||||
TIFR3_OCF3C = 0x8 // Output Compare Flag 3C
|
||||
TIFR3_OCF3B = 0x4 // Output Compare Flag 3B
|
||||
TIFR3_OCF3A = 0x2 // Output Compare Flag 3A
|
||||
TIFR3_TOV3 = 0x1 // Timer/Counter3 Overflow Flag
|
||||
|
||||
// TCCR1A: Timer/Counter1 Control Register A
|
||||
TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits
|
||||
TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits
|
||||
TCCR1A_COM1C = 0xc // Compare Output Mode 1C, bits
|
||||
TCCR1A_WGM1 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TCCR1B: Timer/Counter1 Control Register B
|
||||
TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler
|
||||
TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select
|
||||
TCCR1B_WGM1 = 0x18 // Waveform Generation Mode
|
||||
TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1
|
||||
|
||||
// TCCR1C: Timer/Counter 1 Control Register C
|
||||
TCCR1C_FOC1A = 0x80 // Force Output Compare 1A
|
||||
TCCR1C_FOC1B = 0x40 // Force Output Compare 1B
|
||||
TCCR1C_FOC1C = 0x20 // Force Output Compare 1C
|
||||
|
||||
// TIMSK1: Timer/Counter1 Interrupt Mask Register
|
||||
TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable
|
||||
TIMSK1_OCIE1C = 0x8 // Timer/Counter1 Output Compare C Match Interrupt Enable
|
||||
TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable
|
||||
TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable
|
||||
TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable
|
||||
|
||||
// TIFR1: Timer/Counter1 Interrupt Flag register
|
||||
TIFR1_ICF1 = 0x20 // Input Capture Flag 1
|
||||
TIFR1_OCF1C = 0x8 // Output Compare Flag 1C
|
||||
TIFR1_OCF1B = 0x4 // Output Compare Flag 1B
|
||||
TIFR1_OCF1A = 0x2 // Output Compare Flag 1A
|
||||
TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag
|
||||
)
|
||||
|
||||
// Bitfields for EXINT: External Interrupts
|
||||
const (
|
||||
// EICRA: External Interrupt Control Register A
|
||||
EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit
|
||||
EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit
|
||||
EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit
|
||||
EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit
|
||||
|
||||
// EICRB: External Interrupt Control Register B
|
||||
EICRB_ISC7 = 0xc0 // External Interrupt 7-4 Sense Control Bit
|
||||
EICRB_ISC6 = 0x30 // External Interrupt 7-4 Sense Control Bit
|
||||
EICRB_ISC5 = 0xc // External Interrupt 7-4 Sense Control Bit
|
||||
EICRB_ISC4 = 0x3 // External Interrupt 7-4 Sense Control Bit
|
||||
|
||||
// EIMSK: External Interrupt Mask Register
|
||||
EIMSK_INT = 0xff // External Interrupt Request 7 Enable
|
||||
|
||||
// EIFR: External Interrupt Flag Register
|
||||
EIFR_INTF = 0xff // External Interrupt Flags
|
||||
|
||||
// PCIFR: Pin Change Interrupt Flag Register
|
||||
PCIFR_PCIF0 = 0x1 // Pin Change Interrupt Flag 0
|
||||
|
||||
// PCICR: Pin Change Interrupt Control Register
|
||||
PCICR_PCIE0 = 0x1 // Pin Change Interrupt Enable 0
|
||||
)
|
||||
|
||||
// Bitfields for ADC: Analog-to-Digital Converter
|
||||
const (
|
||||
// ADMUX: The ADC multiplexer Selection Register
|
||||
ADMUX_REFS = 0xc0 // Reference Selection Bits
|
||||
ADMUX_ADLAR = 0x20 // Left Adjust Result
|
||||
ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits
|
||||
|
||||
// ADCSRA: The ADC Control and Status register
|
||||
ADCSRA_ADEN = 0x80 // ADC Enable
|
||||
ADCSRA_ADSC = 0x40 // ADC Start Conversion
|
||||
ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable
|
||||
ADCSRA_ADIF = 0x10 // ADC Interrupt Flag
|
||||
ADCSRA_ADIE = 0x8 // ADC Interrupt Enable
|
||||
ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits
|
||||
|
||||
// DIDR0: Digital Input Disable Register 1
|
||||
DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable
|
||||
DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable
|
||||
DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable
|
||||
DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable
|
||||
DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable
|
||||
DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable
|
||||
DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable
|
||||
DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable
|
||||
)
|
||||
|
||||
// Bitfields for AC: Analog Comparator
|
||||
const (
|
||||
// ACSR: Analog Comparator Control And Status Register
|
||||
ACSR_ACD = 0x80 // Analog Comparator Disable
|
||||
ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select
|
||||
ACSR_ACO = 0x20 // Analog Compare Output
|
||||
ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag
|
||||
ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable
|
||||
ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable
|
||||
ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits
|
||||
|
||||
// DIDR1
|
||||
DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable
|
||||
DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable
|
||||
)
|
||||
|
||||
// Bitfields for PLL: Phase Locked Loop
|
||||
const (
|
||||
// PLLCSR: PLL Status and Control register
|
||||
PLLCSR_PLLP = 0x1c // PLL prescaler Bits
|
||||
PLLCSR_PLLE = 0x2 // PLL Enable Bit
|
||||
PLLCSR_PLOCK = 0x1 // PLL Lock Status Bit
|
||||
)
|
||||
|
||||
// Bitfields for USB_GLOBAL: USB Controller
|
||||
const (
|
||||
// USBINT
|
||||
USBINT_IDTI = 0x2
|
||||
USBINT_VBUSTI = 0x1
|
||||
|
||||
// USBSTA
|
||||
USBSTA_SPEED = 0x8
|
||||
USBSTA_ID = 0x2
|
||||
USBSTA_VBUS = 0x1
|
||||
|
||||
// USBCON: USB General Control Register
|
||||
USBCON_USBE = 0x80
|
||||
USBCON_HOST = 0x40
|
||||
USBCON_FRZCLK = 0x20
|
||||
USBCON_OTGPADE = 0x10
|
||||
USBCON_IDTE = 0x2
|
||||
USBCON_VBUSTE = 0x1
|
||||
|
||||
// UHWCON: USB Hardware Configuration Register
|
||||
UHWCON_UIMOD = 0x80
|
||||
UHWCON_UIDE = 0x40
|
||||
UHWCON_UVCONE = 0x10
|
||||
UHWCON_UVREGE = 0x1
|
||||
)
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from AT90USB1286.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x20000;
|
||||
__ram_size = 0x2000;
|
||||
__num_isrs = 38;
|
||||
Различия файлов не показаны, т.к. их слишком много
Показать различия
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from AT90USB1287.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x20000;
|
||||
__ram_size = 0x2000;
|
||||
__num_isrs = 38;
|
||||
|
|
@ -1,776 +0,0 @@
|
|||
// Automatically generated file. DO NOT EDIT.
|
||||
// Generated by gen-device.py from AT90USB162.atdf, see http://packs.download.atmel.com/
|
||||
|
||||
// +build avr,at90usb162
|
||||
|
||||
// Device information for the AT90USB162.
|
||||
//
|
||||
package avr
|
||||
|
||||
// Magic type name for the compiler.
|
||||
type __reg uint8
|
||||
|
||||
// Export this magic type name.
|
||||
type RegValue = __reg
|
||||
|
||||
// Some information about this device.
|
||||
const (
|
||||
DEVICE = "AT90USB162"
|
||||
ARCH = "AVR8"
|
||||
FAMILY = "megaAVR"
|
||||
)
|
||||
|
||||
// Interrupts
|
||||
const (
|
||||
IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet.
|
||||
IRQ_INT0 = 1 // External Interrupt Request 0
|
||||
IRQ_INT1 = 2 // External Interrupt Request 1
|
||||
IRQ_INT2 = 3 // External Interrupt Request 2
|
||||
IRQ_INT3 = 4 // External Interrupt Request 3
|
||||
IRQ_INT4 = 5 // External Interrupt Request 4
|
||||
IRQ_INT5 = 6 // External Interrupt Request 5
|
||||
IRQ_INT6 = 7 // External Interrupt Request 6
|
||||
IRQ_INT7 = 8 // External Interrupt Request 7
|
||||
IRQ_PCINT0 = 9 // Pin Change Interrupt Request 0
|
||||
IRQ_PCINT1 = 10 // Pin Change Interrupt Request 1
|
||||
IRQ_USB_GEN = 11 // USB General Interrupt Request
|
||||
IRQ_USB_COM = 12 // USB Endpoint/Pipe Interrupt Communication Request
|
||||
IRQ_WDT = 13 // Watchdog Time-out Interrupt
|
||||
IRQ_TIMER1_CAPT = 14 // Timer/Counter2 Capture Event
|
||||
IRQ_TIMER1_COMPA = 15 // Timer/Counter2 Compare Match B
|
||||
IRQ_TIMER1_COMPB = 16 // Timer/Counter2 Compare Match B
|
||||
IRQ_TIMER1_COMPC = 17 // Timer/Counter2 Compare Match C
|
||||
IRQ_TIMER1_OVF = 18 // Timer/Counter1 Overflow
|
||||
IRQ_TIMER0_COMPA = 19 // Timer/Counter0 Compare Match A
|
||||
IRQ_TIMER0_COMPB = 20 // Timer/Counter0 Compare Match B
|
||||
IRQ_TIMER0_OVF = 21 // Timer/Counter0 Overflow
|
||||
IRQ_SPI_STC = 22 // SPI Serial Transfer Complete
|
||||
IRQ_USART1_RX = 23 // USART1, Rx Complete
|
||||
IRQ_USART1_UDRE = 24 // USART1 Data register Empty
|
||||
IRQ_USART1_TX = 25 // USART1, Tx Complete
|
||||
IRQ_ANALOG_COMP = 26 // Analog Comparator
|
||||
IRQ_EE_READY = 27 // EEPROM Ready
|
||||
IRQ_SPM_READY = 28 // Store Program Memory Read
|
||||
IRQ_max = 28 // Highest interrupt number on this device.
|
||||
)
|
||||
|
||||
// Peripherals
|
||||
var (
|
||||
// Fuses
|
||||
FUSE = struct {
|
||||
EXTENDED __reg
|
||||
HIGH __reg
|
||||
LOW __reg
|
||||
}{
|
||||
EXTENDED: 0x2,
|
||||
HIGH: 0x1,
|
||||
LOW: 0x0,
|
||||
}
|
||||
|
||||
// Lockbits
|
||||
LOCKBIT = struct {
|
||||
LOCKBIT __reg
|
||||
}{
|
||||
LOCKBIT: 0x0,
|
||||
}
|
||||
|
||||
// I/O Port
|
||||
PORT = struct {
|
||||
PORTB __reg
|
||||
DDRB __reg
|
||||
PINB __reg
|
||||
PORTD __reg
|
||||
DDRD __reg
|
||||
PIND __reg
|
||||
PORTC __reg
|
||||
DDRC __reg
|
||||
PINC __reg
|
||||
}{
|
||||
PORTB: 0x25, // Port B Data Register
|
||||
DDRB: 0x24, // Port B Data Direction Register
|
||||
PINB: 0x23, // Port B Input Pins
|
||||
PORTD: 0x2b, // Port D Data Register
|
||||
DDRD: 0x2a, // Port D Data Direction Register
|
||||
PIND: 0x29, // Port D Input Pins
|
||||
PORTC: 0x28, // Port C Data Register
|
||||
DDRC: 0x27, // Port C Data Direction Register
|
||||
PINC: 0x26, // Port C Input Pins
|
||||
}
|
||||
|
||||
// Serial Peripheral Interface
|
||||
SPI = struct {
|
||||
SPCR __reg
|
||||
SPSR __reg
|
||||
SPDR __reg
|
||||
}{
|
||||
SPCR: 0x4c, // SPI Control Register
|
||||
SPSR: 0x4d, // SPI Status Register
|
||||
SPDR: 0x4e, // SPI Data Register
|
||||
}
|
||||
|
||||
// Bootloader
|
||||
BOOT_LOAD = struct {
|
||||
SPMCSR __reg
|
||||
}{
|
||||
SPMCSR: 0x57, // Store Program Memory Control Register
|
||||
}
|
||||
|
||||
// EEPROM
|
||||
EEPROM = struct {
|
||||
EEARL __reg
|
||||
EEARH __reg
|
||||
EEDR __reg
|
||||
EECR __reg
|
||||
}{
|
||||
EEARL: 0x41, // EEPROM Address Register Low Bytes
|
||||
EEARH: 0x41, // EEPROM Address Register Low Bytes
|
||||
EEDR: 0x40, // EEPROM Data Register
|
||||
EECR: 0x3f, // EEPROM Control Register
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit
|
||||
TC8 = struct {
|
||||
OCR0B __reg
|
||||
OCR0A __reg
|
||||
TCNT0 __reg
|
||||
TCCR0B __reg
|
||||
TCCR0A __reg
|
||||
TIMSK0 __reg
|
||||
TIFR0 __reg
|
||||
GTCCR __reg
|
||||
}{
|
||||
OCR0B: 0x48, // Timer/Counter0 Output Compare Register
|
||||
OCR0A: 0x47, // Timer/Counter0 Output Compare Register
|
||||
TCNT0: 0x46, // Timer/Counter0
|
||||
TCCR0B: 0x45, // Timer/Counter Control Register B
|
||||
TCCR0A: 0x44, // Timer/Counter Control Register A
|
||||
TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register
|
||||
TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register
|
||||
GTCCR: 0x43, // General Timer/Counter Control Register
|
||||
}
|
||||
|
||||
// Timer/Counter, 16-bit
|
||||
TC16 = struct {
|
||||
TCCR1A __reg
|
||||
TCCR1B __reg
|
||||
TCCR1C __reg
|
||||
TCNT1L __reg
|
||||
TCNT1H __reg
|
||||
OCR1AL __reg
|
||||
OCR1AH __reg
|
||||
OCR1BL __reg
|
||||
OCR1BH __reg
|
||||
OCR1CL __reg
|
||||
OCR1CH __reg
|
||||
ICR1L __reg
|
||||
ICR1H __reg
|
||||
TIMSK1 __reg
|
||||
TIFR1 __reg
|
||||
}{
|
||||
TCCR1A: 0x80, // Timer/Counter1 Control Register A
|
||||
TCCR1B: 0x81, // Timer/Counter1 Control Register B
|
||||
TCCR1C: 0x82, // Timer/Counter 1 Control Register C
|
||||
TCNT1L: 0x84, // Timer/Counter1 Bytes
|
||||
TCNT1H: 0x84, // Timer/Counter1 Bytes
|
||||
OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes
|
||||
OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes
|
||||
OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes
|
||||
OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes
|
||||
OCR1CL: 0x8c, // Timer/Counter1 Output Compare Register C Bytes
|
||||
OCR1CH: 0x8c, // Timer/Counter1 Output Compare Register C Bytes
|
||||
ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register
|
||||
TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register
|
||||
}
|
||||
|
||||
// Phase Locked Loop
|
||||
PLL = struct {
|
||||
PLLCSR __reg
|
||||
}{
|
||||
PLLCSR: 0x49, // PLL Status and Control register
|
||||
}
|
||||
|
||||
// USB Device Registers
|
||||
USB_DEVICE = struct {
|
||||
UEINT __reg
|
||||
UEBCLX __reg
|
||||
UEDATX __reg
|
||||
UEIENX __reg
|
||||
UESTA1X __reg
|
||||
UESTA0X __reg
|
||||
UECFG1X __reg
|
||||
UECFG0X __reg
|
||||
UECONX __reg
|
||||
UERST __reg
|
||||
UENUM __reg
|
||||
UEINTX __reg
|
||||
UDMFN __reg
|
||||
UDFNUML __reg
|
||||
UDFNUMH __reg
|
||||
UDADDR __reg
|
||||
UDIEN __reg
|
||||
UDINT __reg
|
||||
UDCON __reg
|
||||
USBCON __reg
|
||||
REGCR __reg
|
||||
}{
|
||||
UEINT: 0xf4,
|
||||
UEBCLX: 0xf2,
|
||||
UEDATX: 0xf1,
|
||||
UEIENX: 0xf0,
|
||||
UESTA1X: 0xef,
|
||||
UESTA0X: 0xee,
|
||||
UECFG1X: 0xed,
|
||||
UECFG0X: 0xec,
|
||||
UECONX: 0xeb,
|
||||
UERST: 0xea,
|
||||
UENUM: 0xe9,
|
||||
UEINTX: 0xe8,
|
||||
UDMFN: 0xe6,
|
||||
UDFNUML: 0xe4,
|
||||
UDFNUMH: 0xe4,
|
||||
UDADDR: 0xe3,
|
||||
UDIEN: 0xe2,
|
||||
UDINT: 0xe1,
|
||||
UDCON: 0xe0,
|
||||
USBCON: 0xd8, // USB General Control Register
|
||||
REGCR: 0x63, // Regulator Control Register
|
||||
}
|
||||
|
||||
// PS/2 Controller
|
||||
PS2 = struct {
|
||||
UPOE __reg
|
||||
PS2CON __reg
|
||||
}{
|
||||
UPOE: 0xfb,
|
||||
PS2CON: 0xfa, // PS2 Pad Enable register
|
||||
}
|
||||
|
||||
// CPU Registers
|
||||
CPU = struct {
|
||||
SREG __reg
|
||||
SPL __reg
|
||||
SPH __reg
|
||||
MCUCR __reg
|
||||
MCUSR __reg
|
||||
OSCCAL __reg
|
||||
CLKPR __reg
|
||||
SMCR __reg
|
||||
EIND __reg
|
||||
GPIOR2 __reg
|
||||
GPIOR1 __reg
|
||||
GPIOR0 __reg
|
||||
PRR1 __reg
|
||||
PRR0 __reg
|
||||
CLKSTA __reg
|
||||
CLKSEL1 __reg
|
||||
CLKSEL0 __reg
|
||||
DWDR __reg
|
||||
}{
|
||||
SREG: 0x5f, // Status Register
|
||||
SPL: 0x5d, // Stack Pointer
|
||||
SPH: 0x5d, // Stack Pointer
|
||||
MCUCR: 0x55, // MCU Control Register
|
||||
MCUSR: 0x54, // MCU Status Register
|
||||
OSCCAL: 0x66, // Oscillator Calibration Value
|
||||
CLKPR: 0x61,
|
||||
SMCR: 0x53, // Sleep Mode Control Register
|
||||
EIND: 0x5c, // Extended Indirect Register
|
||||
GPIOR2: 0x4b, // General Purpose IO Register 2
|
||||
GPIOR1: 0x4a, // General Purpose IO Register 1
|
||||
GPIOR0: 0x3e, // General Purpose IO Register 0
|
||||
PRR1: 0x65, // Power Reduction Register1
|
||||
PRR0: 0x64, // Power Reduction Register0
|
||||
CLKSTA: 0xd2,
|
||||
CLKSEL1: 0xd1,
|
||||
CLKSEL0: 0xd0,
|
||||
DWDR: 0x51, // debugWire communication register
|
||||
}
|
||||
|
||||
// External Interrupts
|
||||
EXINT = struct {
|
||||
EICRA __reg
|
||||
EICRB __reg
|
||||
EIMSK __reg
|
||||
EIFR __reg
|
||||
PCMSK0 __reg
|
||||
PCMSK1 __reg
|
||||
PCIFR __reg
|
||||
PCICR __reg
|
||||
}{
|
||||
EICRA: 0x69, // External Interrupt Control Register A
|
||||
EICRB: 0x6a, // External Interrupt Control Register B
|
||||
EIMSK: 0x3d, // External Interrupt Mask Register
|
||||
EIFR: 0x3c, // External Interrupt Flag Register
|
||||
PCMSK0: 0x6b, // Pin Change Mask Register 0
|
||||
PCMSK1: 0x6c, // Pin Change Mask Register 1
|
||||
PCIFR: 0x3b, // Pin Change Interrupt Flag Register
|
||||
PCICR: 0x68, // Pin Change Interrupt Control Register
|
||||
}
|
||||
|
||||
// USART
|
||||
USART = struct {
|
||||
UDR1 __reg
|
||||
UCSR1A __reg
|
||||
UCSR1B __reg
|
||||
UCSR1C __reg
|
||||
UCSR1D __reg
|
||||
UBRR1L __reg
|
||||
UBRR1H __reg
|
||||
}{
|
||||
UDR1: 0xce, // USART I/O Data Register
|
||||
UCSR1A: 0xc8, // USART Control and Status Register A
|
||||
UCSR1B: 0xc9, // USART Control and Status Register B
|
||||
UCSR1C: 0xca, // USART Control and Status Register C
|
||||
UCSR1D: 0xcb, // USART Control and Status Register D
|
||||
UBRR1L: 0xcc, // USART Baud Rate Register Bytes
|
||||
UBRR1H: 0xcc, // USART Baud Rate Register Bytes
|
||||
}
|
||||
|
||||
// Watchdog Timer
|
||||
WDT = struct {
|
||||
WDTCSR __reg
|
||||
WDTCKD __reg
|
||||
}{
|
||||
WDTCSR: 0x60, // Watchdog Timer Control Register
|
||||
WDTCKD: 0x62, // Watchdog Timer Clock Divider
|
||||
}
|
||||
|
||||
// Analog Comparator
|
||||
AC = struct {
|
||||
ACSR __reg
|
||||
DIDR1 __reg
|
||||
}{
|
||||
ACSR: 0x50, // Analog Comparator Control And Status Register
|
||||
DIDR1: 0x7f,
|
||||
}
|
||||
)
|
||||
|
||||
// Bitfields for FUSE: Fuses
|
||||
const (
|
||||
// EXTENDED
|
||||
EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level
|
||||
EXTENDED_HWBE = 0x8 // Hardware Boot Enable
|
||||
|
||||
// HIGH
|
||||
HIGH_DWEN = 0x80 // Debug Wire enable
|
||||
HIGH_RSTDISBL = 0x40 // Reset Disabled (Enable PC6 as i/o pin)
|
||||
HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled
|
||||
HIGH_WDTON = 0x10 // Watchdog timer always on
|
||||
HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle
|
||||
HIGH_BOOTSZ = 0x6 // Select Boot Size
|
||||
HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled
|
||||
|
||||
// LOW
|
||||
LOW_CKDIV8 = 0x80 // Divide clock by 8 internally
|
||||
LOW_CKOUT = 0x40 // Clock output on PORTC7
|
||||
LOW_SUT_CKSEL = 0x3f // Select Clock Source
|
||||
)
|
||||
|
||||
// Bitfields for LOCKBIT: Lockbits
|
||||
const (
|
||||
// LOCKBIT
|
||||
LOCKBIT_LB = 0x3 // Memory Lock
|
||||
LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode
|
||||
LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode
|
||||
)
|
||||
|
||||
// Bitfields for PORT: I/O Port
|
||||
const (
|
||||
// PORTC: Port C Data Register
|
||||
PORTC_PORTC = 0xf0 // Port C Data Register bits
|
||||
PORTC_PORTC = 0x7 // Port C Data Register bits
|
||||
|
||||
// DDRC: Port C Data Direction Register
|
||||
DDRC_DDC = 0xf0 // Port C Data Direction Register bits
|
||||
DDRC_DDC = 0x7 // Port C Data Direction Register bits
|
||||
|
||||
// PINC: Port C Input Pins
|
||||
PINC_PINC = 0xf0 // Port C Input Pins bits
|
||||
PINC_PINC = 0x7 // Port C Input Pins bits
|
||||
)
|
||||
|
||||
// Bitfields for SPI: Serial Peripheral Interface
|
||||
const (
|
||||
// SPCR: SPI Control Register
|
||||
SPCR_SPIE = 0x80 // SPI Interrupt Enable
|
||||
SPCR_SPE = 0x40 // SPI Enable
|
||||
SPCR_DORD = 0x20 // Data Order
|
||||
SPCR_MSTR = 0x10 // Master/Slave Select
|
||||
SPCR_CPOL = 0x8 // Clock polarity
|
||||
SPCR_CPHA = 0x4 // Clock Phase
|
||||
SPCR_SPR = 0x3 // SPI Clock Rate Selects
|
||||
|
||||
// SPSR: SPI Status Register
|
||||
SPSR_SPIF = 0x80 // SPI Interrupt Flag
|
||||
SPSR_WCOL = 0x40 // Write Collision Flag
|
||||
SPSR_SPI2X = 0x1 // Double SPI Speed Bit
|
||||
)
|
||||
|
||||
// Bitfields for BOOT_LOAD: Bootloader
|
||||
const (
|
||||
// SPMCSR: Store Program Memory Control Register
|
||||
SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable
|
||||
SPMCSR_RWWSB = 0x40 // Read While Write Section Busy
|
||||
SPMCSR_SIGRD = 0x20 // Signature Row Read
|
||||
SPMCSR_RWWSRE = 0x10 // Read While Write section read enable
|
||||
SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set
|
||||
SPMCSR_PGWRT = 0x4 // Page Write
|
||||
SPMCSR_PGERS = 0x2 // Page Erase
|
||||
SPMCSR_SPMEN = 0x1 // Store Program Memory Enable
|
||||
)
|
||||
|
||||
// Bitfields for EEPROM: EEPROM
|
||||
const (
|
||||
// EECR: EEPROM Control Register
|
||||
EECR_EEPM = 0x30 // EEPROM Programming Mode Bits
|
||||
EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable
|
||||
EECR_EEMPE = 0x4 // EEPROM Master Write Enable
|
||||
EECR_EEPE = 0x2 // EEPROM Write Enable
|
||||
EECR_EERE = 0x1 // EEPROM Read Enable
|
||||
)
|
||||
|
||||
// Bitfields for TC8: Timer/Counter, 8-bit
|
||||
const (
|
||||
// TCCR0B: Timer/Counter Control Register B
|
||||
TCCR0B_FOC0A = 0x80 // Force Output Compare A
|
||||
TCCR0B_FOC0B = 0x40 // Force Output Compare B
|
||||
TCCR0B_WGM02 = 0x8
|
||||
TCCR0B_CS0 = 0x7 // Clock Select
|
||||
|
||||
// TCCR0A: Timer/Counter Control Register A
|
||||
TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode
|
||||
TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm
|
||||
TCCR0A_WGM0 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TIMSK0: Timer/Counter0 Interrupt Mask Register
|
||||
TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable
|
||||
TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable
|
||||
TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable
|
||||
|
||||
// TIFR0: Timer/Counter0 Interrupt Flag register
|
||||
TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B
|
||||
TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A
|
||||
TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag
|
||||
|
||||
// GTCCR: General Timer/Counter Control Register
|
||||
GTCCR_TSM = 0x80 // Timer/Counter Synchronization Mode
|
||||
GTCCR_PSRSYNC = 0x1 // Prescaler Reset Timer/Counter1 and Timer/Counter0
|
||||
)
|
||||
|
||||
// Bitfields for TC16: Timer/Counter, 16-bit
|
||||
const (
|
||||
// TCCR1A: Timer/Counter1 Control Register A
|
||||
TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits
|
||||
TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits
|
||||
TCCR1A_COM1C = 0xc // Compare Output Mode 1C, bits
|
||||
TCCR1A_WGM1 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TCCR1B: Timer/Counter1 Control Register B
|
||||
TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler
|
||||
TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select
|
||||
TCCR1B_WGM1 = 0x18 // Waveform Generation Mode
|
||||
TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1
|
||||
|
||||
// TCCR1C: Timer/Counter 1 Control Register C
|
||||
TCCR1C_FOC1A = 0x80 // Force Output Compare 1A
|
||||
TCCR1C_FOC1B = 0x40 // Force Output Compare 1B
|
||||
TCCR1C_FOC1C = 0x20 // Force Output Compare 1C
|
||||
|
||||
// TIMSK1: Timer/Counter1 Interrupt Mask Register
|
||||
TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable
|
||||
TIMSK1_OCIE1C = 0x8 // Timer/Counter1 Output Compare C Match Interrupt Enable
|
||||
TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable
|
||||
TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable
|
||||
TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable
|
||||
|
||||
// TIFR1: Timer/Counter1 Interrupt Flag register
|
||||
TIFR1_ICF1 = 0x20 // Input Capture Flag 1
|
||||
TIFR1_OCF1C = 0x8 // Output Compare Flag 1C
|
||||
TIFR1_OCF1B = 0x4 // Output Compare Flag 1B
|
||||
TIFR1_OCF1A = 0x2 // Output Compare Flag 1A
|
||||
TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag
|
||||
)
|
||||
|
||||
// Bitfields for PLL: Phase Locked Loop
|
||||
const (
|
||||
// PLLCSR: PLL Status and Control register
|
||||
PLLCSR_PLLP = 0x1c // PLL prescaler Bits
|
||||
PLLCSR_PLLE = 0x2 // PLL Enable Bit
|
||||
PLLCSR_PLOCK = 0x1 // PLL Lock Status Bit
|
||||
)
|
||||
|
||||
// Bitfields for USB_DEVICE: USB Device Registers
|
||||
const (
|
||||
// UEIENX
|
||||
UEIENX_FLERRE = 0x80
|
||||
UEIENX_NAKINE = 0x40
|
||||
UEIENX_NAKOUTE = 0x10
|
||||
UEIENX_RXSTPE = 0x8
|
||||
UEIENX_RXOUTE = 0x4
|
||||
UEIENX_STALLEDE = 0x2
|
||||
UEIENX_TXINE = 0x1
|
||||
|
||||
// UESTA1X
|
||||
UESTA1X_CTRLDIR = 0x4
|
||||
UESTA1X_CURRBK = 0x3
|
||||
|
||||
// UESTA0X
|
||||
UESTA0X_CFGOK = 0x80
|
||||
UESTA0X_OVERFI = 0x40
|
||||
UESTA0X_UNDERFI = 0x20
|
||||
UESTA0X_DTSEQ = 0xc
|
||||
UESTA0X_NBUSYBK = 0x3
|
||||
|
||||
// UECFG1X
|
||||
UECFG1X_EPSIZE = 0x70
|
||||
UECFG1X_EPBK = 0xc
|
||||
UECFG1X_ALLOC = 0x2
|
||||
|
||||
// UECFG0X
|
||||
UECFG0X_EPTYPE = 0xc0
|
||||
UECFG0X_EPDIR = 0x1
|
||||
|
||||
// UECONX
|
||||
UECONX_STALLRQ = 0x20
|
||||
UECONX_STALLRQC = 0x10
|
||||
UECONX_RSTDT = 0x8
|
||||
UECONX_EPEN = 0x1
|
||||
|
||||
// UERST
|
||||
UERST_EPRST = 0x1f
|
||||
|
||||
// UEINTX
|
||||
UEINTX_FIFOCON = 0x80
|
||||
UEINTX_NAKINI = 0x40
|
||||
UEINTX_RWAL = 0x20
|
||||
UEINTX_NAKOUTI = 0x10
|
||||
UEINTX_RXSTPI = 0x8
|
||||
UEINTX_RXOUTI = 0x4
|
||||
UEINTX_STALLEDI = 0x2
|
||||
UEINTX_TXINI = 0x1
|
||||
|
||||
// UDMFN
|
||||
UDMFN_FNCERR = 0x10
|
||||
|
||||
// UDADDR
|
||||
UDADDR_ADDEN = 0x80
|
||||
UDADDR_UADD = 0x7f
|
||||
|
||||
// UDIEN
|
||||
UDIEN_UPRSME = 0x40
|
||||
UDIEN_EORSME = 0x20
|
||||
UDIEN_WAKEUPE = 0x10
|
||||
UDIEN_EORSTE = 0x8
|
||||
UDIEN_SOFE = 0x4
|
||||
UDIEN_SUSPE = 0x1
|
||||
|
||||
// UDINT
|
||||
UDINT_UPRSMI = 0x40
|
||||
UDINT_EORSMI = 0x20
|
||||
UDINT_WAKEUPI = 0x10
|
||||
UDINT_EORSTI = 0x8
|
||||
UDINT_SOFI = 0x4
|
||||
UDINT_SUSPI = 0x1
|
||||
|
||||
// UDCON
|
||||
UDCON_RSTCPU = 0x4
|
||||
UDCON_RMWKUP = 0x2
|
||||
UDCON_DETACH = 0x1
|
||||
|
||||
// USBCON: USB General Control Register
|
||||
USBCON_USBE = 0x80
|
||||
USBCON_FRZCLK = 0x20
|
||||
|
||||
// REGCR: Regulator Control Register
|
||||
REGCR_REGDIS = 0x1
|
||||
)
|
||||
|
||||
// Bitfields for PS2: PS/2 Controller
|
||||
const (
|
||||
// UPOE
|
||||
UPOE_UPWE = 0xc0
|
||||
UPOE_UPDRV = 0x30
|
||||
UPOE_SCKI = 0x8
|
||||
UPOE_DATAI = 0x4
|
||||
UPOE_DPI = 0x2
|
||||
UPOE_DMI = 0x1
|
||||
|
||||
// PS2CON: PS2 Pad Enable register
|
||||
PS2CON_PS2EN = 0x1 // Enable
|
||||
)
|
||||
|
||||
// Bitfields for CPU: CPU Registers
|
||||
const (
|
||||
// SREG: Status Register
|
||||
SREG_I = 0x80 // Global Interrupt Enable
|
||||
SREG_T = 0x40 // Bit Copy Storage
|
||||
SREG_H = 0x20 // Half Carry Flag
|
||||
SREG_S = 0x10 // Sign Bit
|
||||
SREG_V = 0x8 // Two's Complement Overflow Flag
|
||||
SREG_N = 0x4 // Negative Flag
|
||||
SREG_Z = 0x2 // Zero Flag
|
||||
SREG_C = 0x1 // Carry Flag
|
||||
|
||||
// MCUCR: MCU Control Register
|
||||
MCUCR_PUD = 0x10 // Pull-up disable
|
||||
MCUCR_IVSEL = 0x2 // Interrupt Vector Select
|
||||
MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable
|
||||
|
||||
// MCUSR: MCU Status Register
|
||||
MCUSR_USBRF = 0x20 // USB reset flag
|
||||
MCUSR_WDRF = 0x8 // Watchdog Reset Flag
|
||||
MCUSR_BORF = 0x4 // Brown-out Reset Flag
|
||||
MCUSR_EXTRF = 0x2 // External Reset Flag
|
||||
MCUSR_PORF = 0x1 // Power-on reset flag
|
||||
|
||||
// OSCCAL: Oscillator Calibration Value
|
||||
OSCCAL_OSCCAL = 0xff // Oscillator Calibration
|
||||
|
||||
// CLKPR
|
||||
CLKPR_CLKPCE = 0x80
|
||||
CLKPR_CLKPS = 0xf
|
||||
|
||||
// SMCR: Sleep Mode Control Register
|
||||
SMCR_SM = 0xe // Sleep Mode Select bits
|
||||
SMCR_SE = 0x1 // Sleep Enable
|
||||
|
||||
// GPIOR2: General Purpose IO Register 2
|
||||
GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis
|
||||
|
||||
// GPIOR1: General Purpose IO Register 1
|
||||
GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis
|
||||
|
||||
// GPIOR0: General Purpose IO Register 0
|
||||
GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7
|
||||
GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6
|
||||
GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5
|
||||
GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4
|
||||
GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3
|
||||
GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2
|
||||
GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1
|
||||
GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0
|
||||
|
||||
// PRR1: Power Reduction Register1
|
||||
PRR1_PRUSB = 0x80 // Power Reduction USB
|
||||
PRR1_PRUSART1 = 0x1 // Power Reduction USART1
|
||||
|
||||
// PRR0: Power Reduction Register0
|
||||
PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0
|
||||
PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1
|
||||
PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface
|
||||
|
||||
// CLKSTA
|
||||
CLKSTA_RCON = 0x2
|
||||
CLKSTA_EXTON = 0x1
|
||||
|
||||
// CLKSEL1
|
||||
CLKSEL1_RCCKSEL = 0xf0
|
||||
CLKSEL1_EXCKSEL = 0xf
|
||||
|
||||
// CLKSEL0
|
||||
CLKSEL0_RCSUT = 0xc0
|
||||
CLKSEL0_EXSUT = 0x30
|
||||
CLKSEL0_RCE = 0x8
|
||||
CLKSEL0_EXTE = 0x4
|
||||
CLKSEL0_CLKS = 0x1
|
||||
)
|
||||
|
||||
// Bitfields for EXINT: External Interrupts
|
||||
const (
|
||||
// EICRA: External Interrupt Control Register A
|
||||
EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit
|
||||
EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit
|
||||
EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit
|
||||
EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit
|
||||
|
||||
// EICRB: External Interrupt Control Register B
|
||||
EICRB_ISC7 = 0xc0 // External Interrupt 7-4 Sense Control Bit
|
||||
EICRB_ISC6 = 0x30 // External Interrupt 7-4 Sense Control Bit
|
||||
EICRB_ISC5 = 0xc // External Interrupt 7-4 Sense Control Bit
|
||||
EICRB_ISC4 = 0x3 // External Interrupt 7-4 Sense Control Bit
|
||||
|
||||
// EIMSK: External Interrupt Mask Register
|
||||
EIMSK_INT = 0xff // External Interrupt Request 7 Enable
|
||||
|
||||
// EIFR: External Interrupt Flag Register
|
||||
EIFR_INTF = 0xff // External Interrupt Flags
|
||||
|
||||
// PCMSK0: Pin Change Mask Register 0
|
||||
PCMSK0_PCINT = 0xff // Pin Change Enable Masks
|
||||
|
||||
// PCMSK1: Pin Change Mask Register 1
|
||||
PCMSK1_PCINT = 0x1f
|
||||
|
||||
// PCIFR: Pin Change Interrupt Flag Register
|
||||
PCIFR_PCIF = 0x3 // Pin Change Interrupt Flags
|
||||
|
||||
// PCICR: Pin Change Interrupt Control Register
|
||||
PCICR_PCIE = 0x3 // Pin Change Interrupt Enables
|
||||
)
|
||||
|
||||
// Bitfields for USART: USART
|
||||
const (
|
||||
// UCSR1A: USART Control and Status Register A
|
||||
UCSR1A_RXC1 = 0x80 // USART Receive Complete
|
||||
UCSR1A_TXC1 = 0x40 // USART Transmitt Complete
|
||||
UCSR1A_UDRE1 = 0x20 // USART Data Register Empty
|
||||
UCSR1A_FE1 = 0x10 // Framing Error
|
||||
UCSR1A_DOR1 = 0x8 // Data overRun
|
||||
UCSR1A_UPE1 = 0x4 // Parity Error
|
||||
UCSR1A_U2X1 = 0x2 // Double the USART transmission speed
|
||||
UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode
|
||||
|
||||
// UCSR1B: USART Control and Status Register B
|
||||
UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable
|
||||
UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable
|
||||
UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable
|
||||
UCSR1B_RXEN1 = 0x10 // Receiver Enable
|
||||
UCSR1B_TXEN1 = 0x8 // Transmitter Enable
|
||||
UCSR1B_UCSZ12 = 0x4 // Character Size
|
||||
UCSR1B_RXB81 = 0x2 // Receive Data Bit 8
|
||||
UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8
|
||||
|
||||
// UCSR1C: USART Control and Status Register C
|
||||
UCSR1C_UMSEL1 = 0xc0 // USART Mode Select
|
||||
UCSR1C_UPM1 = 0x30 // Parity Mode Bits
|
||||
UCSR1C_USBS1 = 0x8 // Stop Bit Select
|
||||
UCSR1C_UCSZ1 = 0x6 // Character Size
|
||||
UCSR1C_UCPOL1 = 0x1 // Clock Polarity
|
||||
|
||||
// UCSR1D: USART Control and Status Register D
|
||||
UCSR1D_CTSEN = 0x2 // CTS Enable
|
||||
UCSR1D_RTSEN = 0x1 // RTS Enable
|
||||
)
|
||||
|
||||
// Bitfields for WDT: Watchdog Timer
|
||||
const (
|
||||
// WDTCSR: Watchdog Timer Control Register
|
||||
WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag
|
||||
WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable
|
||||
WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits
|
||||
WDTCSR_WDCE = 0x10 // Watchdog Change Enable
|
||||
WDTCSR_WDE = 0x8 // Watch Dog Enable
|
||||
|
||||
// WDTCKD: Watchdog Timer Clock Divider
|
||||
WDTCKD_WDEWIF = 0x8 // Watchdog Early Warning Interrupt Flag
|
||||
WDTCKD_WDEWIE = 0x4 // Watchdog Early Warning Interrupt Enable
|
||||
WDTCKD_WCLKD = 0x3 // Watchdog Timer Clock Dividers
|
||||
)
|
||||
|
||||
// Bitfields for AC: Analog Comparator
|
||||
const (
|
||||
// ACSR: Analog Comparator Control And Status Register
|
||||
ACSR_ACD = 0x80 // Analog Comparator Disable
|
||||
ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select
|
||||
ACSR_ACO = 0x20 // Analog Compare Output
|
||||
ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag
|
||||
ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable
|
||||
ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable
|
||||
ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits
|
||||
|
||||
// DIDR1
|
||||
DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable
|
||||
DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable
|
||||
)
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from AT90USB162.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x4000;
|
||||
__ram_size = 0x200;
|
||||
__num_isrs = 29;
|
||||
Различия файлов не показаны, т.к. их слишком много
Показать различия
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from AT90USB646.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x10000;
|
||||
__ram_size = 0x1000;
|
||||
__num_isrs = 38;
|
||||
Различия файлов не показаны, т.к. их слишком много
Показать различия
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from AT90USB647.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x10000;
|
||||
__ram_size = 0x1000;
|
||||
__num_isrs = 38;
|
||||
|
|
@ -1,776 +0,0 @@
|
|||
// Automatically generated file. DO NOT EDIT.
|
||||
// Generated by gen-device.py from AT90USB82.atdf, see http://packs.download.atmel.com/
|
||||
|
||||
// +build avr,at90usb82
|
||||
|
||||
// Device information for the AT90USB82.
|
||||
//
|
||||
package avr
|
||||
|
||||
// Magic type name for the compiler.
|
||||
type __reg uint8
|
||||
|
||||
// Export this magic type name.
|
||||
type RegValue = __reg
|
||||
|
||||
// Some information about this device.
|
||||
const (
|
||||
DEVICE = "AT90USB82"
|
||||
ARCH = "AVR8"
|
||||
FAMILY = "megaAVR"
|
||||
)
|
||||
|
||||
// Interrupts
|
||||
const (
|
||||
IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet.
|
||||
IRQ_INT0 = 1 // External Interrupt Request 0
|
||||
IRQ_INT1 = 2 // External Interrupt Request 1
|
||||
IRQ_INT2 = 3 // External Interrupt Request 2
|
||||
IRQ_INT3 = 4 // External Interrupt Request 3
|
||||
IRQ_INT4 = 5 // External Interrupt Request 4
|
||||
IRQ_INT5 = 6 // External Interrupt Request 5
|
||||
IRQ_INT6 = 7 // External Interrupt Request 6
|
||||
IRQ_INT7 = 8 // External Interrupt Request 7
|
||||
IRQ_PCINT0 = 9 // Pin Change Interrupt Request 0
|
||||
IRQ_PCINT1 = 10 // Pin Change Interrupt Request 1
|
||||
IRQ_USB_GEN = 11 // USB General Interrupt Request
|
||||
IRQ_USB_COM = 12 // USB Endpoint/Pipe Interrupt Communication Request
|
||||
IRQ_WDT = 13 // Watchdog Time-out Interrupt
|
||||
IRQ_TIMER1_CAPT = 14 // Timer/Counter2 Capture Event
|
||||
IRQ_TIMER1_COMPA = 15 // Timer/Counter2 Compare Match B
|
||||
IRQ_TIMER1_COMPB = 16 // Timer/Counter2 Compare Match B
|
||||
IRQ_TIMER1_COMPC = 17 // Timer/Counter2 Compare Match C
|
||||
IRQ_TIMER1_OVF = 18 // Timer/Counter1 Overflow
|
||||
IRQ_TIMER0_COMPA = 19 // Timer/Counter0 Compare Match A
|
||||
IRQ_TIMER0_COMPB = 20 // Timer/Counter0 Compare Match B
|
||||
IRQ_TIMER0_OVF = 21 // Timer/Counter0 Overflow
|
||||
IRQ_SPI_STC = 22 // SPI Serial Transfer Complete
|
||||
IRQ_USART1_RX = 23 // USART1, Rx Complete
|
||||
IRQ_USART1_UDRE = 24 // USART1 Data register Empty
|
||||
IRQ_USART1_TX = 25 // USART1, Tx Complete
|
||||
IRQ_ANALOG_COMP = 26 // Analog Comparator
|
||||
IRQ_EE_READY = 27 // EEPROM Ready
|
||||
IRQ_SPM_READY = 28 // Store Program Memory Read
|
||||
IRQ_max = 28 // Highest interrupt number on this device.
|
||||
)
|
||||
|
||||
// Peripherals
|
||||
var (
|
||||
// Fuses
|
||||
FUSE = struct {
|
||||
EXTENDED __reg
|
||||
HIGH __reg
|
||||
LOW __reg
|
||||
}{
|
||||
EXTENDED: 0x2,
|
||||
HIGH: 0x1,
|
||||
LOW: 0x0,
|
||||
}
|
||||
|
||||
// Lockbits
|
||||
LOCKBIT = struct {
|
||||
LOCKBIT __reg
|
||||
}{
|
||||
LOCKBIT: 0x0,
|
||||
}
|
||||
|
||||
// I/O Port
|
||||
PORT = struct {
|
||||
PORTB __reg
|
||||
DDRB __reg
|
||||
PINB __reg
|
||||
PORTD __reg
|
||||
DDRD __reg
|
||||
PIND __reg
|
||||
PORTC __reg
|
||||
DDRC __reg
|
||||
PINC __reg
|
||||
}{
|
||||
PORTB: 0x25, // Port B Data Register
|
||||
DDRB: 0x24, // Port B Data Direction Register
|
||||
PINB: 0x23, // Port B Input Pins
|
||||
PORTD: 0x2b, // Port D Data Register
|
||||
DDRD: 0x2a, // Port D Data Direction Register
|
||||
PIND: 0x29, // Port D Input Pins
|
||||
PORTC: 0x28, // Port C Data Register
|
||||
DDRC: 0x27, // Port C Data Direction Register
|
||||
PINC: 0x26, // Port C Input Pins
|
||||
}
|
||||
|
||||
// Serial Peripheral Interface
|
||||
SPI = struct {
|
||||
SPCR __reg
|
||||
SPSR __reg
|
||||
SPDR __reg
|
||||
}{
|
||||
SPCR: 0x4c, // SPI Control Register
|
||||
SPSR: 0x4d, // SPI Status Register
|
||||
SPDR: 0x4e, // SPI Data Register
|
||||
}
|
||||
|
||||
// Bootloader
|
||||
BOOT_LOAD = struct {
|
||||
SPMCSR __reg
|
||||
}{
|
||||
SPMCSR: 0x57, // Store Program Memory Control Register
|
||||
}
|
||||
|
||||
// EEPROM
|
||||
EEPROM = struct {
|
||||
EEARL __reg
|
||||
EEARH __reg
|
||||
EEDR __reg
|
||||
EECR __reg
|
||||
}{
|
||||
EEARL: 0x41, // EEPROM Address Register Low Bytes
|
||||
EEARH: 0x41, // EEPROM Address Register Low Bytes
|
||||
EEDR: 0x40, // EEPROM Data Register
|
||||
EECR: 0x3f, // EEPROM Control Register
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit
|
||||
TC8 = struct {
|
||||
OCR0B __reg
|
||||
OCR0A __reg
|
||||
TCNT0 __reg
|
||||
TCCR0B __reg
|
||||
TCCR0A __reg
|
||||
TIMSK0 __reg
|
||||
TIFR0 __reg
|
||||
GTCCR __reg
|
||||
}{
|
||||
OCR0B: 0x48, // Timer/Counter0 Output Compare Register
|
||||
OCR0A: 0x47, // Timer/Counter0 Output Compare Register
|
||||
TCNT0: 0x46, // Timer/Counter0
|
||||
TCCR0B: 0x45, // Timer/Counter Control Register B
|
||||
TCCR0A: 0x44, // Timer/Counter Control Register A
|
||||
TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register
|
||||
TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register
|
||||
GTCCR: 0x43, // General Timer/Counter Control Register
|
||||
}
|
||||
|
||||
// Timer/Counter, 16-bit
|
||||
TC16 = struct {
|
||||
TCCR1A __reg
|
||||
TCCR1B __reg
|
||||
TCCR1C __reg
|
||||
TCNT1L __reg
|
||||
TCNT1H __reg
|
||||
OCR1AL __reg
|
||||
OCR1AH __reg
|
||||
OCR1BL __reg
|
||||
OCR1BH __reg
|
||||
OCR1CL __reg
|
||||
OCR1CH __reg
|
||||
ICR1L __reg
|
||||
ICR1H __reg
|
||||
TIMSK1 __reg
|
||||
TIFR1 __reg
|
||||
}{
|
||||
TCCR1A: 0x80, // Timer/Counter1 Control Register A
|
||||
TCCR1B: 0x81, // Timer/Counter1 Control Register B
|
||||
TCCR1C: 0x82, // Timer/Counter 1 Control Register C
|
||||
TCNT1L: 0x84, // Timer/Counter1 Bytes
|
||||
TCNT1H: 0x84, // Timer/Counter1 Bytes
|
||||
OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes
|
||||
OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes
|
||||
OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes
|
||||
OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes
|
||||
OCR1CL: 0x8c, // Timer/Counter1 Output Compare Register C Bytes
|
||||
OCR1CH: 0x8c, // Timer/Counter1 Output Compare Register C Bytes
|
||||
ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register
|
||||
TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register
|
||||
}
|
||||
|
||||
// Phase Locked Loop
|
||||
PLL = struct {
|
||||
PLLCSR __reg
|
||||
}{
|
||||
PLLCSR: 0x49, // PLL Status and Control register
|
||||
}
|
||||
|
||||
// USB Device Registers
|
||||
USB_DEVICE = struct {
|
||||
UEINT __reg
|
||||
UEBCLX __reg
|
||||
UEDATX __reg
|
||||
UEIENX __reg
|
||||
UESTA1X __reg
|
||||
UESTA0X __reg
|
||||
UECFG1X __reg
|
||||
UECFG0X __reg
|
||||
UECONX __reg
|
||||
UERST __reg
|
||||
UENUM __reg
|
||||
UEINTX __reg
|
||||
UDMFN __reg
|
||||
UDFNUML __reg
|
||||
UDFNUMH __reg
|
||||
UDADDR __reg
|
||||
UDIEN __reg
|
||||
UDINT __reg
|
||||
UDCON __reg
|
||||
USBCON __reg
|
||||
REGCR __reg
|
||||
}{
|
||||
UEINT: 0xf4,
|
||||
UEBCLX: 0xf2,
|
||||
UEDATX: 0xf1,
|
||||
UEIENX: 0xf0,
|
||||
UESTA1X: 0xef,
|
||||
UESTA0X: 0xee,
|
||||
UECFG1X: 0xed,
|
||||
UECFG0X: 0xec,
|
||||
UECONX: 0xeb,
|
||||
UERST: 0xea,
|
||||
UENUM: 0xe9,
|
||||
UEINTX: 0xe8,
|
||||
UDMFN: 0xe6,
|
||||
UDFNUML: 0xe4,
|
||||
UDFNUMH: 0xe4,
|
||||
UDADDR: 0xe3,
|
||||
UDIEN: 0xe2,
|
||||
UDINT: 0xe1,
|
||||
UDCON: 0xe0,
|
||||
USBCON: 0xd8, // USB General Control Register
|
||||
REGCR: 0x63, // Regulator Control Register
|
||||
}
|
||||
|
||||
// PS/2 Controller
|
||||
PS2 = struct {
|
||||
UPOE __reg
|
||||
PS2CON __reg
|
||||
}{
|
||||
UPOE: 0xfb,
|
||||
PS2CON: 0xfa, // PS2 Pad Enable register
|
||||
}
|
||||
|
||||
// CPU Registers
|
||||
CPU = struct {
|
||||
SREG __reg
|
||||
SPL __reg
|
||||
SPH __reg
|
||||
MCUCR __reg
|
||||
MCUSR __reg
|
||||
OSCCAL __reg
|
||||
CLKPR __reg
|
||||
SMCR __reg
|
||||
EIND __reg
|
||||
GPIOR2 __reg
|
||||
GPIOR1 __reg
|
||||
GPIOR0 __reg
|
||||
PRR1 __reg
|
||||
PRR0 __reg
|
||||
CLKSTA __reg
|
||||
CLKSEL1 __reg
|
||||
CLKSEL0 __reg
|
||||
DWDR __reg
|
||||
}{
|
||||
SREG: 0x5f, // Status Register
|
||||
SPL: 0x5d, // Stack Pointer
|
||||
SPH: 0x5d, // Stack Pointer
|
||||
MCUCR: 0x55, // MCU Control Register
|
||||
MCUSR: 0x54, // MCU Status Register
|
||||
OSCCAL: 0x66, // Oscillator Calibration Value
|
||||
CLKPR: 0x61,
|
||||
SMCR: 0x53, // Sleep Mode Control Register
|
||||
EIND: 0x5c, // Extended Indirect Register
|
||||
GPIOR2: 0x4b, // General Purpose IO Register 2
|
||||
GPIOR1: 0x4a, // General Purpose IO Register 1
|
||||
GPIOR0: 0x3e, // General Purpose IO Register 0
|
||||
PRR1: 0x65, // Power Reduction Register1
|
||||
PRR0: 0x64, // Power Reduction Register0
|
||||
CLKSTA: 0xd2,
|
||||
CLKSEL1: 0xd1,
|
||||
CLKSEL0: 0xd0,
|
||||
DWDR: 0x51, // debugWire communication register
|
||||
}
|
||||
|
||||
// External Interrupts
|
||||
EXINT = struct {
|
||||
EICRA __reg
|
||||
EICRB __reg
|
||||
EIMSK __reg
|
||||
EIFR __reg
|
||||
PCMSK0 __reg
|
||||
PCMSK1 __reg
|
||||
PCIFR __reg
|
||||
PCICR __reg
|
||||
}{
|
||||
EICRA: 0x69, // External Interrupt Control Register A
|
||||
EICRB: 0x6a, // External Interrupt Control Register B
|
||||
EIMSK: 0x3d, // External Interrupt Mask Register
|
||||
EIFR: 0x3c, // External Interrupt Flag Register
|
||||
PCMSK0: 0x6b, // Pin Change Mask Register 0
|
||||
PCMSK1: 0x6c, // Pin Change Mask Register 1
|
||||
PCIFR: 0x3b, // Pin Change Interrupt Flag Register
|
||||
PCICR: 0x68, // Pin Change Interrupt Control Register
|
||||
}
|
||||
|
||||
// USART
|
||||
USART = struct {
|
||||
UDR1 __reg
|
||||
UCSR1A __reg
|
||||
UCSR1B __reg
|
||||
UCSR1C __reg
|
||||
UCSR1D __reg
|
||||
UBRR1L __reg
|
||||
UBRR1H __reg
|
||||
}{
|
||||
UDR1: 0xce, // USART I/O Data Register
|
||||
UCSR1A: 0xc8, // USART Control and Status Register A
|
||||
UCSR1B: 0xc9, // USART Control and Status Register B
|
||||
UCSR1C: 0xca, // USART Control and Status Register C
|
||||
UCSR1D: 0xcb, // USART Control and Status Register D
|
||||
UBRR1L: 0xcc, // USART Baud Rate Register Bytes
|
||||
UBRR1H: 0xcc, // USART Baud Rate Register Bytes
|
||||
}
|
||||
|
||||
// Watchdog Timer
|
||||
WDT = struct {
|
||||
WDTCSR __reg
|
||||
WDTCKD __reg
|
||||
}{
|
||||
WDTCSR: 0x60, // Watchdog Timer Control Register
|
||||
WDTCKD: 0x62, // Watchdog Timer Clock Divider
|
||||
}
|
||||
|
||||
// Analog Comparator
|
||||
AC = struct {
|
||||
ACSR __reg
|
||||
DIDR1 __reg
|
||||
}{
|
||||
ACSR: 0x50, // Analog Comparator Control And Status Register
|
||||
DIDR1: 0x7f,
|
||||
}
|
||||
)
|
||||
|
||||
// Bitfields for FUSE: Fuses
|
||||
const (
|
||||
// EXTENDED
|
||||
EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level
|
||||
EXTENDED_HWBE = 0x8 // Hardware Boot Enable
|
||||
|
||||
// HIGH
|
||||
HIGH_DWEN = 0x80 // Debug Wire enable
|
||||
HIGH_RSTDISBL = 0x40 // Reset Disabled (Enable PC6 as i/o pin)
|
||||
HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled
|
||||
HIGH_WDTON = 0x10 // Watchdog timer always on
|
||||
HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle
|
||||
HIGH_BOOTSZ = 0x6 // Select Boot Size
|
||||
HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled
|
||||
|
||||
// LOW
|
||||
LOW_CKDIV8 = 0x80 // Divide clock by 8 internally
|
||||
LOW_CKOUT = 0x40 // Clock output on PORTC7
|
||||
LOW_SUT_CKSEL = 0x3f // Select Clock Source
|
||||
)
|
||||
|
||||
// Bitfields for LOCKBIT: Lockbits
|
||||
const (
|
||||
// LOCKBIT
|
||||
LOCKBIT_LB = 0x3 // Memory Lock
|
||||
LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode
|
||||
LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode
|
||||
)
|
||||
|
||||
// Bitfields for PORT: I/O Port
|
||||
const (
|
||||
// PORTC: Port C Data Register
|
||||
PORTC_PORTC = 0xf0 // Port C Data Register bits
|
||||
PORTC_PORTC = 0x7 // Port C Data Register bits
|
||||
|
||||
// DDRC: Port C Data Direction Register
|
||||
DDRC_DDC = 0xf0 // Port C Data Direction Register bits
|
||||
DDRC_DDC = 0x7 // Port C Data Direction Register bits
|
||||
|
||||
// PINC: Port C Input Pins
|
||||
PINC_PINC = 0xf0 // Port C Input Pins bits
|
||||
PINC_PINC = 0x7 // Port C Input Pins bits
|
||||
)
|
||||
|
||||
// Bitfields for SPI: Serial Peripheral Interface
|
||||
const (
|
||||
// SPCR: SPI Control Register
|
||||
SPCR_SPIE = 0x80 // SPI Interrupt Enable
|
||||
SPCR_SPE = 0x40 // SPI Enable
|
||||
SPCR_DORD = 0x20 // Data Order
|
||||
SPCR_MSTR = 0x10 // Master/Slave Select
|
||||
SPCR_CPOL = 0x8 // Clock polarity
|
||||
SPCR_CPHA = 0x4 // Clock Phase
|
||||
SPCR_SPR = 0x3 // SPI Clock Rate Selects
|
||||
|
||||
// SPSR: SPI Status Register
|
||||
SPSR_SPIF = 0x80 // SPI Interrupt Flag
|
||||
SPSR_WCOL = 0x40 // Write Collision Flag
|
||||
SPSR_SPI2X = 0x1 // Double SPI Speed Bit
|
||||
)
|
||||
|
||||
// Bitfields for BOOT_LOAD: Bootloader
|
||||
const (
|
||||
// SPMCSR: Store Program Memory Control Register
|
||||
SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable
|
||||
SPMCSR_RWWSB = 0x40 // Read While Write Section Busy
|
||||
SPMCSR_SIGRD = 0x20 // Signature Row Read
|
||||
SPMCSR_RWWSRE = 0x10 // Read While Write section read enable
|
||||
SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set
|
||||
SPMCSR_PGWRT = 0x4 // Page Write
|
||||
SPMCSR_PGERS = 0x2 // Page Erase
|
||||
SPMCSR_SPMEN = 0x1 // Store Program Memory Enable
|
||||
)
|
||||
|
||||
// Bitfields for EEPROM: EEPROM
|
||||
const (
|
||||
// EECR: EEPROM Control Register
|
||||
EECR_EEPM = 0x30 // EEPROM Programming Mode Bits
|
||||
EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable
|
||||
EECR_EEMPE = 0x4 // EEPROM Master Write Enable
|
||||
EECR_EEPE = 0x2 // EEPROM Write Enable
|
||||
EECR_EERE = 0x1 // EEPROM Read Enable
|
||||
)
|
||||
|
||||
// Bitfields for TC8: Timer/Counter, 8-bit
|
||||
const (
|
||||
// TCCR0B: Timer/Counter Control Register B
|
||||
TCCR0B_FOC0A = 0x80 // Force Output Compare A
|
||||
TCCR0B_FOC0B = 0x40 // Force Output Compare B
|
||||
TCCR0B_WGM02 = 0x8
|
||||
TCCR0B_CS0 = 0x7 // Clock Select
|
||||
|
||||
// TCCR0A: Timer/Counter Control Register A
|
||||
TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode
|
||||
TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm
|
||||
TCCR0A_WGM0 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TIMSK0: Timer/Counter0 Interrupt Mask Register
|
||||
TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable
|
||||
TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable
|
||||
TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable
|
||||
|
||||
// TIFR0: Timer/Counter0 Interrupt Flag register
|
||||
TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B
|
||||
TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A
|
||||
TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag
|
||||
|
||||
// GTCCR: General Timer/Counter Control Register
|
||||
GTCCR_TSM = 0x80 // Timer/Counter Synchronization Mode
|
||||
GTCCR_PSRSYNC = 0x1 // Prescaler Reset Timer/Counter1 and Timer/Counter0
|
||||
)
|
||||
|
||||
// Bitfields for TC16: Timer/Counter, 16-bit
|
||||
const (
|
||||
// TCCR1A: Timer/Counter1 Control Register A
|
||||
TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits
|
||||
TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits
|
||||
TCCR1A_COM1C = 0xc // Compare Output Mode 1C, bits
|
||||
TCCR1A_WGM1 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TCCR1B: Timer/Counter1 Control Register B
|
||||
TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler
|
||||
TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select
|
||||
TCCR1B_WGM1 = 0x18 // Waveform Generation Mode
|
||||
TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1
|
||||
|
||||
// TCCR1C: Timer/Counter 1 Control Register C
|
||||
TCCR1C_FOC1A = 0x80 // Force Output Compare 1A
|
||||
TCCR1C_FOC1B = 0x40 // Force Output Compare 1B
|
||||
TCCR1C_FOC1C = 0x20 // Force Output Compare 1C
|
||||
|
||||
// TIMSK1: Timer/Counter1 Interrupt Mask Register
|
||||
TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable
|
||||
TIMSK1_OCIE1C = 0x8 // Timer/Counter1 Output Compare C Match Interrupt Enable
|
||||
TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable
|
||||
TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable
|
||||
TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable
|
||||
|
||||
// TIFR1: Timer/Counter1 Interrupt Flag register
|
||||
TIFR1_ICF1 = 0x20 // Input Capture Flag 1
|
||||
TIFR1_OCF1C = 0x8 // Output Compare Flag 1C
|
||||
TIFR1_OCF1B = 0x4 // Output Compare Flag 1B
|
||||
TIFR1_OCF1A = 0x2 // Output Compare Flag 1A
|
||||
TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag
|
||||
)
|
||||
|
||||
// Bitfields for PLL: Phase Locked Loop
|
||||
const (
|
||||
// PLLCSR: PLL Status and Control register
|
||||
PLLCSR_PLLP = 0x1c // PLL prescaler Bits
|
||||
PLLCSR_PLLE = 0x2 // PLL Enable Bit
|
||||
PLLCSR_PLOCK = 0x1 // PLL Lock Status Bit
|
||||
)
|
||||
|
||||
// Bitfields for USB_DEVICE: USB Device Registers
|
||||
const (
|
||||
// UEIENX
|
||||
UEIENX_FLERRE = 0x80
|
||||
UEIENX_NAKINE = 0x40
|
||||
UEIENX_NAKOUTE = 0x10
|
||||
UEIENX_RXSTPE = 0x8
|
||||
UEIENX_RXOUTE = 0x4
|
||||
UEIENX_STALLEDE = 0x2
|
||||
UEIENX_TXINE = 0x1
|
||||
|
||||
// UESTA1X
|
||||
UESTA1X_CTRLDIR = 0x4
|
||||
UESTA1X_CURRBK = 0x3
|
||||
|
||||
// UESTA0X
|
||||
UESTA0X_CFGOK = 0x80
|
||||
UESTA0X_OVERFI = 0x40
|
||||
UESTA0X_UNDERFI = 0x20
|
||||
UESTA0X_DTSEQ = 0xc
|
||||
UESTA0X_NBUSYBK = 0x3
|
||||
|
||||
// UECFG1X
|
||||
UECFG1X_EPSIZE = 0x70
|
||||
UECFG1X_EPBK = 0xc
|
||||
UECFG1X_ALLOC = 0x2
|
||||
|
||||
// UECFG0X
|
||||
UECFG0X_EPTYPE = 0xc0
|
||||
UECFG0X_EPDIR = 0x1
|
||||
|
||||
// UECONX
|
||||
UECONX_STALLRQ = 0x20
|
||||
UECONX_STALLRQC = 0x10
|
||||
UECONX_RSTDT = 0x8
|
||||
UECONX_EPEN = 0x1
|
||||
|
||||
// UERST
|
||||
UERST_EPRST = 0x1f
|
||||
|
||||
// UEINTX
|
||||
UEINTX_FIFOCON = 0x80
|
||||
UEINTX_NAKINI = 0x40
|
||||
UEINTX_RWAL = 0x20
|
||||
UEINTX_NAKOUTI = 0x10
|
||||
UEINTX_RXSTPI = 0x8
|
||||
UEINTX_RXOUTI = 0x4
|
||||
UEINTX_STALLEDI = 0x2
|
||||
UEINTX_TXINI = 0x1
|
||||
|
||||
// UDMFN
|
||||
UDMFN_FNCERR = 0x10
|
||||
|
||||
// UDADDR
|
||||
UDADDR_ADDEN = 0x80
|
||||
UDADDR_UADD = 0x7f
|
||||
|
||||
// UDIEN
|
||||
UDIEN_UPRSME = 0x40
|
||||
UDIEN_EORSME = 0x20
|
||||
UDIEN_WAKEUPE = 0x10
|
||||
UDIEN_EORSTE = 0x8
|
||||
UDIEN_SOFE = 0x4
|
||||
UDIEN_SUSPE = 0x1
|
||||
|
||||
// UDINT
|
||||
UDINT_UPRSMI = 0x40
|
||||
UDINT_EORSMI = 0x20
|
||||
UDINT_WAKEUPI = 0x10
|
||||
UDINT_EORSTI = 0x8
|
||||
UDINT_SOFI = 0x4
|
||||
UDINT_SUSPI = 0x1
|
||||
|
||||
// UDCON
|
||||
UDCON_RSTCPU = 0x4
|
||||
UDCON_RMWKUP = 0x2
|
||||
UDCON_DETACH = 0x1
|
||||
|
||||
// USBCON: USB General Control Register
|
||||
USBCON_USBE = 0x80
|
||||
USBCON_FRZCLK = 0x20
|
||||
|
||||
// REGCR: Regulator Control Register
|
||||
REGCR_REGDIS = 0x1
|
||||
)
|
||||
|
||||
// Bitfields for PS2: PS/2 Controller
|
||||
const (
|
||||
// UPOE
|
||||
UPOE_UPWE = 0xc0
|
||||
UPOE_UPDRV = 0x30
|
||||
UPOE_SCKI = 0x8
|
||||
UPOE_DATAI = 0x4
|
||||
UPOE_DPI = 0x2
|
||||
UPOE_DMI = 0x1
|
||||
|
||||
// PS2CON: PS2 Pad Enable register
|
||||
PS2CON_PS2EN = 0x1 // Enable
|
||||
)
|
||||
|
||||
// Bitfields for CPU: CPU Registers
|
||||
const (
|
||||
// SREG: Status Register
|
||||
SREG_I = 0x80 // Global Interrupt Enable
|
||||
SREG_T = 0x40 // Bit Copy Storage
|
||||
SREG_H = 0x20 // Half Carry Flag
|
||||
SREG_S = 0x10 // Sign Bit
|
||||
SREG_V = 0x8 // Two's Complement Overflow Flag
|
||||
SREG_N = 0x4 // Negative Flag
|
||||
SREG_Z = 0x2 // Zero Flag
|
||||
SREG_C = 0x1 // Carry Flag
|
||||
|
||||
// MCUCR: MCU Control Register
|
||||
MCUCR_PUD = 0x10 // Pull-up disable
|
||||
MCUCR_IVSEL = 0x2 // Interrupt Vector Select
|
||||
MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable
|
||||
|
||||
// MCUSR: MCU Status Register
|
||||
MCUSR_USBRF = 0x20 // USB reset flag
|
||||
MCUSR_WDRF = 0x8 // Watchdog Reset Flag
|
||||
MCUSR_BORF = 0x4 // Brown-out Reset Flag
|
||||
MCUSR_EXTRF = 0x2 // External Reset Flag
|
||||
MCUSR_PORF = 0x1 // Power-on reset flag
|
||||
|
||||
// OSCCAL: Oscillator Calibration Value
|
||||
OSCCAL_OSCCAL = 0xff // Oscillator Calibration
|
||||
|
||||
// CLKPR
|
||||
CLKPR_CLKPCE = 0x80
|
||||
CLKPR_CLKPS = 0xf
|
||||
|
||||
// SMCR: Sleep Mode Control Register
|
||||
SMCR_SM = 0xe // Sleep Mode Select bits
|
||||
SMCR_SE = 0x1 // Sleep Enable
|
||||
|
||||
// GPIOR2: General Purpose IO Register 2
|
||||
GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis
|
||||
|
||||
// GPIOR1: General Purpose IO Register 1
|
||||
GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis
|
||||
|
||||
// GPIOR0: General Purpose IO Register 0
|
||||
GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7
|
||||
GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6
|
||||
GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5
|
||||
GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4
|
||||
GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3
|
||||
GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2
|
||||
GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1
|
||||
GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0
|
||||
|
||||
// PRR1: Power Reduction Register1
|
||||
PRR1_PRUSB = 0x80 // Power Reduction USB
|
||||
PRR1_PRUSART1 = 0x1 // Power Reduction USART1
|
||||
|
||||
// PRR0: Power Reduction Register0
|
||||
PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0
|
||||
PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1
|
||||
PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface
|
||||
|
||||
// CLKSTA
|
||||
CLKSTA_RCON = 0x2
|
||||
CLKSTA_EXTON = 0x1
|
||||
|
||||
// CLKSEL1
|
||||
CLKSEL1_RCCKSEL = 0xf0
|
||||
CLKSEL1_EXCKSEL = 0xf
|
||||
|
||||
// CLKSEL0
|
||||
CLKSEL0_RCSUT = 0xc0
|
||||
CLKSEL0_EXSUT = 0x30
|
||||
CLKSEL0_RCE = 0x8
|
||||
CLKSEL0_EXTE = 0x4
|
||||
CLKSEL0_CLKS = 0x1
|
||||
)
|
||||
|
||||
// Bitfields for EXINT: External Interrupts
|
||||
const (
|
||||
// EICRA: External Interrupt Control Register A
|
||||
EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit
|
||||
EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit
|
||||
EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit
|
||||
EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit
|
||||
|
||||
// EICRB: External Interrupt Control Register B
|
||||
EICRB_ISC7 = 0xc0 // External Interrupt 7-4 Sense Control Bit
|
||||
EICRB_ISC6 = 0x30 // External Interrupt 7-4 Sense Control Bit
|
||||
EICRB_ISC5 = 0xc // External Interrupt 7-4 Sense Control Bit
|
||||
EICRB_ISC4 = 0x3 // External Interrupt 7-4 Sense Control Bit
|
||||
|
||||
// EIMSK: External Interrupt Mask Register
|
||||
EIMSK_INT = 0xff // External Interrupt Request 7 Enable
|
||||
|
||||
// EIFR: External Interrupt Flag Register
|
||||
EIFR_INTF = 0xff // External Interrupt Flags
|
||||
|
||||
// PCMSK0: Pin Change Mask Register 0
|
||||
PCMSK0_PCINT = 0xff // Pin Change Enable Masks
|
||||
|
||||
// PCMSK1: Pin Change Mask Register 1
|
||||
PCMSK1_PCINT = 0x1f
|
||||
|
||||
// PCIFR: Pin Change Interrupt Flag Register
|
||||
PCIFR_PCIF = 0x3 // Pin Change Interrupt Flags
|
||||
|
||||
// PCICR: Pin Change Interrupt Control Register
|
||||
PCICR_PCIE = 0x3 // Pin Change Interrupt Enables
|
||||
)
|
||||
|
||||
// Bitfields for USART: USART
|
||||
const (
|
||||
// UCSR1A: USART Control and Status Register A
|
||||
UCSR1A_RXC1 = 0x80 // USART Receive Complete
|
||||
UCSR1A_TXC1 = 0x40 // USART Transmitt Complete
|
||||
UCSR1A_UDRE1 = 0x20 // USART Data Register Empty
|
||||
UCSR1A_FE1 = 0x10 // Framing Error
|
||||
UCSR1A_DOR1 = 0x8 // Data overRun
|
||||
UCSR1A_UPE1 = 0x4 // Parity Error
|
||||
UCSR1A_U2X1 = 0x2 // Double the USART transmission speed
|
||||
UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode
|
||||
|
||||
// UCSR1B: USART Control and Status Register B
|
||||
UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable
|
||||
UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable
|
||||
UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable
|
||||
UCSR1B_RXEN1 = 0x10 // Receiver Enable
|
||||
UCSR1B_TXEN1 = 0x8 // Transmitter Enable
|
||||
UCSR1B_UCSZ12 = 0x4 // Character Size
|
||||
UCSR1B_RXB81 = 0x2 // Receive Data Bit 8
|
||||
UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8
|
||||
|
||||
// UCSR1C: USART Control and Status Register C
|
||||
UCSR1C_UMSEL1 = 0xc0 // USART Mode Select
|
||||
UCSR1C_UPM1 = 0x30 // Parity Mode Bits
|
||||
UCSR1C_USBS1 = 0x8 // Stop Bit Select
|
||||
UCSR1C_UCSZ1 = 0x6 // Character Size
|
||||
UCSR1C_UCPOL1 = 0x1 // Clock Polarity
|
||||
|
||||
// UCSR1D: USART Control and Status Register D
|
||||
UCSR1D_CTSEN = 0x2 // CTS Enable
|
||||
UCSR1D_RTSEN = 0x1 // RTS Enable
|
||||
)
|
||||
|
||||
// Bitfields for WDT: Watchdog Timer
|
||||
const (
|
||||
// WDTCSR: Watchdog Timer Control Register
|
||||
WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag
|
||||
WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable
|
||||
WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits
|
||||
WDTCSR_WDCE = 0x10 // Watchdog Change Enable
|
||||
WDTCSR_WDE = 0x8 // Watch Dog Enable
|
||||
|
||||
// WDTCKD: Watchdog Timer Clock Divider
|
||||
WDTCKD_WDEWIF = 0x8 // Watchdog Early Warning Interrupt Flag
|
||||
WDTCKD_WDEWIE = 0x4 // Watchdog Early Warning Interrupt Enable
|
||||
WDTCKD_WCLKD = 0x3 // Watchdog Timer Clock Dividers
|
||||
)
|
||||
|
||||
// Bitfields for AC: Analog Comparator
|
||||
const (
|
||||
// ACSR: Analog Comparator Control And Status Register
|
||||
ACSR_ACD = 0x80 // Analog Comparator Disable
|
||||
ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select
|
||||
ACSR_ACO = 0x20 // Analog Compare Output
|
||||
ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag
|
||||
ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable
|
||||
ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable
|
||||
ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits
|
||||
|
||||
// DIDR1
|
||||
DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable
|
||||
DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable
|
||||
)
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from AT90USB82.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x2000;
|
||||
__ram_size = 0x200;
|
||||
__num_isrs = 29;
|
||||
|
|
@ -1,676 +0,0 @@
|
|||
// Automatically generated file. DO NOT EDIT.
|
||||
// Generated by gen-device.py from ATmega128.atdf, see http://packs.download.atmel.com/
|
||||
|
||||
// +build avr,atmega128
|
||||
|
||||
// Device information for the ATmega128.
|
||||
//
|
||||
package avr
|
||||
|
||||
// Magic type name for the compiler.
|
||||
type __reg uint8
|
||||
|
||||
// Export this magic type name.
|
||||
type RegValue = __reg
|
||||
|
||||
// Some information about this device.
|
||||
const (
|
||||
DEVICE = "ATmega128"
|
||||
ARCH = "AVR8"
|
||||
FAMILY = "megaAVR"
|
||||
)
|
||||
|
||||
// Interrupts
|
||||
const (
|
||||
IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset
|
||||
IRQ_INT0 = 1 // External Interrupt Request 0
|
||||
IRQ_INT1 = 2 // External Interrupt Request 1
|
||||
IRQ_INT2 = 3 // External Interrupt Request 2
|
||||
IRQ_INT3 = 4 // External Interrupt Request 3
|
||||
IRQ_INT4 = 5 // External Interrupt Request 4
|
||||
IRQ_INT5 = 6 // External Interrupt Request 5
|
||||
IRQ_INT6 = 7 // External Interrupt Request 6
|
||||
IRQ_INT7 = 8 // External Interrupt Request 7
|
||||
IRQ_TIMER2_COMP = 9 // Timer/Counter2 Compare Match
|
||||
IRQ_TIMER2_OVF = 10 // Timer/Counter2 Overflow
|
||||
IRQ_TIMER1_CAPT = 11 // Timer/Counter1 Capture Event
|
||||
IRQ_TIMER1_COMPA = 12 // Timer/Counter1 Compare Match A
|
||||
IRQ_TIMER1_COMPB = 13 // Timer/Counter Compare Match B
|
||||
IRQ_TIMER1_OVF = 14 // Timer/Counter1 Overflow
|
||||
IRQ_TIMER0_COMP = 15 // Timer/Counter0 Compare Match
|
||||
IRQ_TIMER0_OVF = 16 // Timer/Counter0 Overflow
|
||||
IRQ_SPI_STC = 17 // SPI Serial Transfer Complete
|
||||
IRQ_USART0_RX = 18 // USART0, Rx Complete
|
||||
IRQ_USART0_UDRE = 19 // USART0 Data Register Empty
|
||||
IRQ_USART0_TX = 20 // USART0, Tx Complete
|
||||
IRQ_ADC = 21 // ADC Conversion Complete
|
||||
IRQ_EE_READY = 22 // EEPROM Ready
|
||||
IRQ_ANALOG_COMP = 23 // Analog Comparator
|
||||
IRQ_TIMER1_COMPC = 24 // Timer/Counter1 Compare Match C
|
||||
IRQ_TIMER3_CAPT = 25 // Timer/Counter3 Capture Event
|
||||
IRQ_TIMER3_COMPA = 26 // Timer/Counter3 Compare Match A
|
||||
IRQ_TIMER3_COMPB = 27 // Timer/Counter3 Compare Match B
|
||||
IRQ_TIMER3_COMPC = 28 // Timer/Counter3 Compare Match C
|
||||
IRQ_TIMER3_OVF = 29 // Timer/Counter3 Overflow
|
||||
IRQ_USART1_RX = 30 // USART1, Rx Complete
|
||||
IRQ_USART1_UDRE = 31 // USART1, Data Register Empty
|
||||
IRQ_USART1_TX = 32 // USART1, Tx Complete
|
||||
IRQ_TWI = 33 // 2-wire Serial Interface
|
||||
IRQ_SPM_READY = 34 // Store Program Memory Read
|
||||
IRQ_max = 34 // Highest interrupt number on this device.
|
||||
)
|
||||
|
||||
// Peripherals
|
||||
var (
|
||||
// Fuses
|
||||
FUSE = struct {
|
||||
EXTENDED __reg
|
||||
HIGH __reg
|
||||
LOW __reg
|
||||
}{
|
||||
EXTENDED: 0x2,
|
||||
HIGH: 0x1,
|
||||
LOW: 0x0,
|
||||
}
|
||||
|
||||
// Lockbits
|
||||
LOCKBIT = struct {
|
||||
LOCKBIT __reg
|
||||
}{
|
||||
LOCKBIT: 0x0,
|
||||
}
|
||||
|
||||
// Analog Comparator
|
||||
AC = struct {
|
||||
ACSR __reg
|
||||
}{
|
||||
ACSR: 0x28, // Analog Comparator Control And Status Register
|
||||
}
|
||||
|
||||
// Serial Peripheral Interface
|
||||
SPI = struct {
|
||||
SPDR __reg
|
||||
SPSR __reg
|
||||
SPCR __reg
|
||||
}{
|
||||
SPDR: 0x2f, // SPI Data Register
|
||||
SPSR: 0x2e, // SPI Status Register
|
||||
SPCR: 0x2d, // SPI Control Register
|
||||
}
|
||||
|
||||
// Two Wire Serial Interface
|
||||
TWI = struct {
|
||||
TWBR __reg
|
||||
TWCR __reg
|
||||
TWSR __reg
|
||||
TWDR __reg
|
||||
TWAR __reg
|
||||
}{
|
||||
TWBR: 0x70, // TWI Bit Rate register
|
||||
TWCR: 0x74, // TWI Control Register
|
||||
TWSR: 0x71, // TWI Status Register
|
||||
TWDR: 0x73, // TWI Data register
|
||||
TWAR: 0x72, // TWI (Slave) Address register
|
||||
}
|
||||
|
||||
// USART
|
||||
USART = struct {
|
||||
UDR0 __reg
|
||||
UCSR0A __reg
|
||||
UCSR0B __reg
|
||||
UCSR0C __reg
|
||||
UBRR0H __reg
|
||||
UBRR0L __reg
|
||||
UDR1 __reg
|
||||
UCSR1A __reg
|
||||
UCSR1B __reg
|
||||
UCSR1C __reg
|
||||
UBRR1H __reg
|
||||
UBRR1L __reg
|
||||
}{
|
||||
UDR0: 0x2c, // USART I/O Data Register
|
||||
UCSR0A: 0x2b, // USART Control and Status Register A
|
||||
UCSR0B: 0x2a, // USART Control and Status Register B
|
||||
UCSR0C: 0x95, // USART Control and Status Register C
|
||||
UBRR0H: 0x90, // USART Baud Rate Register Hight Byte
|
||||
UBRR0L: 0x29, // USART Baud Rate Register Low Byte
|
||||
UDR1: 0x9c, // USART I/O Data Register
|
||||
UCSR1A: 0x9b, // USART Control and Status Register A
|
||||
UCSR1B: 0x9a, // USART Control and Status Register B
|
||||
UCSR1C: 0x9d, // USART Control and Status Register C
|
||||
UBRR1H: 0x98, // USART Baud Rate Register Hight Byte
|
||||
UBRR1L: 0x99, // USART Baud Rate Register Low Byte
|
||||
}
|
||||
|
||||
// CPU Registers
|
||||
CPU = struct {
|
||||
SREG __reg
|
||||
SPL __reg
|
||||
SPH __reg
|
||||
MCUCR __reg
|
||||
XDIV __reg
|
||||
XMCRA __reg
|
||||
XMCRB __reg
|
||||
OSCCAL __reg
|
||||
RAMPZ __reg
|
||||
}{
|
||||
SREG: 0x5f, // Status Register
|
||||
SPL: 0x5d, // Stack Pointer
|
||||
SPH: 0x5d, // Stack Pointer
|
||||
MCUCR: 0x55, // MCU Control Register
|
||||
XDIV: 0x5c, // XTAL Divide Control Register
|
||||
XMCRA: 0x6d, // External Memory Control Register A
|
||||
XMCRB: 0x6c, // External Memory Control Register B
|
||||
OSCCAL: 0x6f, // Oscillator Calibration Value
|
||||
RAMPZ: 0x5b, // RAM Page Z Select Register
|
||||
}
|
||||
|
||||
// Bootloader
|
||||
BOOT_LOAD = struct {
|
||||
SPMCSR __reg
|
||||
}{
|
||||
SPMCSR: 0x68, // Store Program Memory Control Register
|
||||
}
|
||||
|
||||
// JTAG Interface
|
||||
JTAG = struct {
|
||||
OCDR __reg
|
||||
}{
|
||||
OCDR: 0x42, // On-Chip Debug Related Register in I/O Memory
|
||||
}
|
||||
|
||||
// Other Registers
|
||||
MISC = struct {
|
||||
}{}
|
||||
|
||||
// External Interrupts
|
||||
EXINT = struct {
|
||||
EICRA __reg
|
||||
EICRB __reg
|
||||
EIMSK __reg
|
||||
EIFR __reg
|
||||
}{
|
||||
EICRA: 0x6a, // External Interrupt Control Register A
|
||||
EICRB: 0x5a, // External Interrupt Control Register B
|
||||
EIMSK: 0x59, // External Interrupt Mask Register
|
||||
EIFR: 0x58, // External Interrupt Flag Register
|
||||
}
|
||||
|
||||
// EEPROM
|
||||
EEPROM = struct {
|
||||
EEARL __reg
|
||||
EEARH __reg
|
||||
EEDR __reg
|
||||
EECR __reg
|
||||
}{
|
||||
EEARL: 0x3e, // EEPROM Read/Write Access Bytes
|
||||
EEARH: 0x3e, // EEPROM Read/Write Access Bytes
|
||||
EEDR: 0x3d, // EEPROM Data Register
|
||||
EECR: 0x3c, // EEPROM Control Register
|
||||
}
|
||||
|
||||
// I/O Port
|
||||
PORT = struct {
|
||||
PORTA __reg
|
||||
DDRA __reg
|
||||
PINA __reg
|
||||
PORTB __reg
|
||||
DDRB __reg
|
||||
PINB __reg
|
||||
PORTC __reg
|
||||
DDRC __reg
|
||||
PINC __reg
|
||||
PORTD __reg
|
||||
DDRD __reg
|
||||
PIND __reg
|
||||
PORTE __reg
|
||||
DDRE __reg
|
||||
PINE __reg
|
||||
PORTF __reg
|
||||
DDRF __reg
|
||||
PINF __reg
|
||||
PORTG __reg
|
||||
DDRG __reg
|
||||
PING __reg
|
||||
}{
|
||||
PORTA: 0x3b, // Port A Data Register
|
||||
DDRA: 0x3a, // Port A Data Direction Register
|
||||
PINA: 0x39, // Port A Input Pins
|
||||
PORTB: 0x38, // Port B Data Register
|
||||
DDRB: 0x37, // Port B Data Direction Register
|
||||
PINB: 0x36, // Port B Input Pins
|
||||
PORTC: 0x35, // Port C Data Register
|
||||
DDRC: 0x34, // Port C Data Direction Register
|
||||
PINC: 0x33, // Port C Input Pins
|
||||
PORTD: 0x32, // Port D Data Register
|
||||
DDRD: 0x31, // Port D Data Direction Register
|
||||
PIND: 0x30, // Port D Input Pins
|
||||
PORTE: 0x23, // Data Register, Port E
|
||||
DDRE: 0x22, // Data Direction Register, Port E
|
||||
PINE: 0x21, // Input Pins, Port E
|
||||
PORTF: 0x62, // Data Register, Port F
|
||||
DDRF: 0x61, // Data Direction Register, Port F
|
||||
PINF: 0x20, // Input Pins, Port F
|
||||
PORTG: 0x65, // Data Register, Port G
|
||||
DDRG: 0x64, // Data Direction Register, Port G
|
||||
PING: 0x63, // Input Pins, Port G
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit Async
|
||||
TC8_ASYNC = struct {
|
||||
TCCR0 __reg
|
||||
TCNT0 __reg
|
||||
OCR0 __reg
|
||||
ASSR __reg
|
||||
}{
|
||||
TCCR0: 0x53, // Timer/Counter Control Register
|
||||
TCNT0: 0x52, // Timer/Counter Register
|
||||
OCR0: 0x51, // Output Compare Register
|
||||
ASSR: 0x50, // Asynchronus Status Register
|
||||
}
|
||||
|
||||
// Timer/Counter, 16-bit
|
||||
TC16 = struct {
|
||||
TCCR1A __reg
|
||||
TCCR1B __reg
|
||||
TCCR1C __reg
|
||||
TCNT1L __reg
|
||||
TCNT1H __reg
|
||||
OCR1AL __reg
|
||||
OCR1AH __reg
|
||||
OCR1BL __reg
|
||||
OCR1BH __reg
|
||||
OCR1CL __reg
|
||||
OCR1CH __reg
|
||||
ICR1L __reg
|
||||
ICR1H __reg
|
||||
TCCR3A __reg
|
||||
TCCR3B __reg
|
||||
TCCR3C __reg
|
||||
TCNT3L __reg
|
||||
TCNT3H __reg
|
||||
OCR3AL __reg
|
||||
OCR3AH __reg
|
||||
OCR3BL __reg
|
||||
OCR3BH __reg
|
||||
OCR3CL __reg
|
||||
OCR3CH __reg
|
||||
ICR3L __reg
|
||||
ICR3H __reg
|
||||
}{
|
||||
TCCR1A: 0x4f, // Timer/Counter1 Control Register A
|
||||
TCCR1B: 0x4e, // Timer/Counter1 Control Register B
|
||||
TCCR1C: 0x7a, // Timer/Counter1 Control Register C
|
||||
TCNT1L: 0x4c, // Timer/Counter1 Bytes
|
||||
TCNT1H: 0x4c, // Timer/Counter1 Bytes
|
||||
OCR1AL: 0x4a, // Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1AH: 0x4a, // Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1BL: 0x48, // Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1BH: 0x48, // Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1CL: 0x78, // Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1CH: 0x78, // Timer/Counter1 Output Compare Register Bytes
|
||||
ICR1L: 0x46, // Timer/Counter1 Input Capture Register Bytes
|
||||
ICR1H: 0x46, // Timer/Counter1 Input Capture Register Bytes
|
||||
TCCR3A: 0x8b, // Timer/Counter3 Control Register A
|
||||
TCCR3B: 0x8a, // Timer/Counter3 Control Register B
|
||||
TCCR3C: 0x8c, // Timer/Counter3 Control Register C
|
||||
TCNT3L: 0x88, // Timer/Counter3 Bytes
|
||||
TCNT3H: 0x88, // Timer/Counter3 Bytes
|
||||
OCR3AL: 0x86, // Timer/Counter3 Output Compare Register A Bytes
|
||||
OCR3AH: 0x86, // Timer/Counter3 Output Compare Register A Bytes
|
||||
OCR3BL: 0x84, // Timer/Counter3 Output Compare Register B Bytes
|
||||
OCR3BH: 0x84, // Timer/Counter3 Output Compare Register B Bytes
|
||||
OCR3CL: 0x82, // Timer/Counter3 Output compare Register C Bytes
|
||||
OCR3CH: 0x82, // Timer/Counter3 Output compare Register C Bytes
|
||||
ICR3L: 0x80, // Timer/Counter3 Input Capture Register Bytes
|
||||
ICR3H: 0x80, // Timer/Counter3 Input Capture Register Bytes
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit
|
||||
TC8 = struct {
|
||||
TCCR2 __reg
|
||||
TCNT2 __reg
|
||||
OCR2 __reg
|
||||
}{
|
||||
TCCR2: 0x45, // Timer/Counter Control Register
|
||||
TCNT2: 0x44, // Timer/Counter Register
|
||||
OCR2: 0x43, // Output Compare Register
|
||||
}
|
||||
|
||||
// Watchdog Timer
|
||||
WDT = struct {
|
||||
WDTCR __reg
|
||||
}{
|
||||
WDTCR: 0x41, // Watchdog Timer Control Register
|
||||
}
|
||||
|
||||
// Analog-to-Digital Converter
|
||||
ADC = struct {
|
||||
ADMUX __reg
|
||||
ADCSRA __reg
|
||||
ADCL __reg
|
||||
ADCH __reg
|
||||
}{
|
||||
ADMUX: 0x27, // The ADC multiplexer Selection Register
|
||||
ADCSRA: 0x26, // The ADC Control and Status register
|
||||
ADCL: 0x24, // ADC Data Register Bytes
|
||||
ADCH: 0x24, // ADC Data Register Bytes
|
||||
}
|
||||
)
|
||||
|
||||
// Bitfields for FUSE: Fuses
|
||||
const (
|
||||
// EXTENDED
|
||||
EXTENDED_M103C = 0x2 // ATmega103 Compatibility Mode
|
||||
EXTENDED_WDTON = 0x1 // Watchdog Timer always on
|
||||
|
||||
// HIGH
|
||||
HIGH_OCDEN = 0x80 // On-Chip Debug Enabled
|
||||
HIGH_JTAGEN = 0x40 // JTAG Interface Enabled
|
||||
HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled
|
||||
HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle
|
||||
HIGH_BOOTSZ = 0x6 // Select Boot Size
|
||||
HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled
|
||||
HIGH_CKOPT = 0x10 // CKOPT fuse (operation dependent of CKSEL fuses)
|
||||
|
||||
// LOW
|
||||
LOW_BODLEVEL = 0x80 // Brownout detector trigger level
|
||||
LOW_BODEN = 0x40 // Brown-out detection enabled
|
||||
LOW_SUT_CKSEL = 0x3f // Select Clock Source
|
||||
)
|
||||
|
||||
// Bitfields for LOCKBIT: Lockbits
|
||||
const (
|
||||
// LOCKBIT
|
||||
LOCKBIT_LB = 0x3 // Memory Lock
|
||||
LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode
|
||||
LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode
|
||||
)
|
||||
|
||||
// Bitfields for AC: Analog Comparator
|
||||
const (
|
||||
// ACSR: Analog Comparator Control And Status Register
|
||||
ACSR_ACD = 0x80 // Analog Comparator Disable
|
||||
ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select
|
||||
ACSR_ACO = 0x20 // Analog Compare Output
|
||||
ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag
|
||||
ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable
|
||||
ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable
|
||||
ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits
|
||||
)
|
||||
|
||||
// Bitfields for SPI: Serial Peripheral Interface
|
||||
const (
|
||||
// SPSR: SPI Status Register
|
||||
SPSR_SPIF = 0x80 // SPI Interrupt Flag
|
||||
SPSR_WCOL = 0x40 // Write Collision Flag
|
||||
SPSR_SPI2X = 0x1 // Double SPI Speed Bit
|
||||
|
||||
// SPCR: SPI Control Register
|
||||
SPCR_SPIE = 0x80 // SPI Interrupt Enable
|
||||
SPCR_SPE = 0x40 // SPI Enable
|
||||
SPCR_DORD = 0x20 // Data Order
|
||||
SPCR_MSTR = 0x10 // Master/Slave Select
|
||||
SPCR_CPOL = 0x8 // Clock polarity
|
||||
SPCR_CPHA = 0x4 // Clock Phase
|
||||
SPCR_SPR = 0x3 // SPI Clock Rate Selects
|
||||
)
|
||||
|
||||
// Bitfields for TWI: Two Wire Serial Interface
|
||||
const (
|
||||
// TWCR: TWI Control Register
|
||||
TWCR_TWINT = 0x80 // TWI Interrupt Flag
|
||||
TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit
|
||||
TWCR_TWSTA = 0x20 // TWI Start Condition Bit
|
||||
TWCR_TWSTO = 0x10 // TWI Stop Condition Bit
|
||||
TWCR_TWWC = 0x8 // TWI Write Collition Flag
|
||||
TWCR_TWEN = 0x4 // TWI Enable Bit
|
||||
TWCR_TWIE = 0x1 // TWI Interrupt Enable
|
||||
|
||||
// TWSR: TWI Status Register
|
||||
TWSR_TWS = 0xf8 // TWI Status
|
||||
TWSR_TWPS = 0x3 // TWI Prescaler
|
||||
|
||||
// TWAR: TWI (Slave) Address register
|
||||
TWAR_TWA = 0xfe // TWI (Slave) Address register Bits
|
||||
TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit
|
||||
)
|
||||
|
||||
// Bitfields for USART: USART
|
||||
const (
|
||||
// UCSR0A: USART Control and Status Register A
|
||||
UCSR0A_RXC0 = 0x80 // USART Receive Complete
|
||||
UCSR0A_TXC0 = 0x40 // USART Transmitt Complete
|
||||
UCSR0A_UDRE0 = 0x20 // USART Data Register Empty
|
||||
UCSR0A_FE0 = 0x10 // Framing Error
|
||||
UCSR0A_DOR0 = 0x8 // Data overRun
|
||||
UCSR0A_UPE0 = 0x4 // Parity Error
|
||||
UCSR0A_U2X0 = 0x2 // Double the USART transmission speed
|
||||
UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode
|
||||
|
||||
// UCSR0B: USART Control and Status Register B
|
||||
UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable
|
||||
UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable
|
||||
UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable
|
||||
UCSR0B_RXEN0 = 0x10 // Receiver Enable
|
||||
UCSR0B_TXEN0 = 0x8 // Transmitter Enable
|
||||
UCSR0B_UCSZ02 = 0x4 // Character Size
|
||||
UCSR0B_RXB80 = 0x2 // Receive Data Bit 8
|
||||
UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8
|
||||
|
||||
// UCSR0C: USART Control and Status Register C
|
||||
UCSR0C_UMSEL0 = 0x40 // USART Mode Select
|
||||
UCSR0C_UPM0 = 0x30 // Parity Mode Bits
|
||||
UCSR0C_USBS0 = 0x8 // Stop Bit Select
|
||||
UCSR0C_UCSZ0 = 0x6 // Character Size
|
||||
UCSR0C_UCPOL0 = 0x1 // Clock Polarity
|
||||
|
||||
// UCSR1A: USART Control and Status Register A
|
||||
UCSR1A_RXC1 = 0x80 // USART Receive Complete
|
||||
UCSR1A_TXC1 = 0x40 // USART Transmitt Complete
|
||||
UCSR1A_UDRE1 = 0x20 // USART Data Register Empty
|
||||
UCSR1A_FE1 = 0x10 // Framing Error
|
||||
UCSR1A_DOR1 = 0x8 // Data overRun
|
||||
UCSR1A_UPE1 = 0x4 // Parity Error
|
||||
UCSR1A_U2X1 = 0x2 // Double the USART transmission speed
|
||||
UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode
|
||||
|
||||
// UCSR1B: USART Control and Status Register B
|
||||
UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable
|
||||
UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable
|
||||
UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable
|
||||
UCSR1B_RXEN1 = 0x10 // Receiver Enable
|
||||
UCSR1B_TXEN1 = 0x8 // Transmitter Enable
|
||||
UCSR1B_UCSZ12 = 0x4 // Character Size
|
||||
UCSR1B_RXB81 = 0x2 // Receive Data Bit 8
|
||||
UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8
|
||||
|
||||
// UCSR1C: USART Control and Status Register C
|
||||
UCSR1C_UMSEL1 = 0x40 // USART Mode Select
|
||||
UCSR1C_UPM1 = 0x30 // Parity Mode Bits
|
||||
UCSR1C_USBS1 = 0x8 // Stop Bit Select
|
||||
UCSR1C_UCSZ1 = 0x6 // Character Size
|
||||
UCSR1C_UCPOL1 = 0x1 // Clock Polarity
|
||||
)
|
||||
|
||||
// Bitfields for CPU: CPU Registers
|
||||
const (
|
||||
// SREG: Status Register
|
||||
SREG_I = 0x80 // Global Interrupt Enable
|
||||
SREG_T = 0x40 // Bit Copy Storage
|
||||
SREG_H = 0x20 // Half Carry Flag
|
||||
SREG_S = 0x10 // Sign Bit
|
||||
SREG_V = 0x8 // Two's Complement Overflow Flag
|
||||
SREG_N = 0x4 // Negative Flag
|
||||
SREG_Z = 0x2 // Zero Flag
|
||||
SREG_C = 0x1 // Carry Flag
|
||||
|
||||
// MCUCR: MCU Control Register
|
||||
MCUCR_SRE = 0x80 // External SRAM Enable
|
||||
MCUCR_SRW10 = 0x40 // External SRAM Wait State Select
|
||||
MCUCR_SE = 0x20 // Sleep Enable
|
||||
MCUCR_SM = 0x18 // Sleep Mode Select
|
||||
MCUCR_SM2 = 0x4 // Sleep Mode Select
|
||||
MCUCR_IVSEL = 0x2 // Interrupt Vector Select
|
||||
MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable
|
||||
|
||||
// XDIV: XTAL Divide Control Register
|
||||
XDIV_XDIVEN = 0x80 // XTAL Divide Enable
|
||||
XDIV_XDIV6 = 0x40 // XTAL Divide Select Bit 6
|
||||
XDIV_XDIV5 = 0x20 // XTAL Divide Select Bit 5
|
||||
XDIV_XDIV4 = 0x10 // XTAL Divide Select Bit 4
|
||||
XDIV_XDIV3 = 0x8 // XTAL Divide Select Bit 3
|
||||
XDIV_XDIV2 = 0x4 // XTAL Divide Select Bit 2
|
||||
XDIV_XDIV1 = 0x2 // XTAL Divide Select Bit 1
|
||||
XDIV_XDIV0 = 0x1 // XTAL Divide Select Bit 0
|
||||
|
||||
// XMCRA: External Memory Control Register A
|
||||
XMCRA_SRL = 0x70 // Wait state page limit
|
||||
XMCRA_SRW0 = 0xc // Wait state select bit lower page
|
||||
XMCRA_SRW11 = 0x2 // Wait state select bit upper page
|
||||
|
||||
// XMCRB: External Memory Control Register B
|
||||
XMCRB_XMBK = 0x80 // External Memory Bus Keeper Enable
|
||||
XMCRB_XMM = 0x7 // External Memory High Mask
|
||||
|
||||
// OSCCAL: Oscillator Calibration Value
|
||||
OSCCAL_OSCCAL = 0xff // Oscillator Calibration
|
||||
|
||||
// RAMPZ: RAM Page Z Select Register
|
||||
RAMPZ_RAMPZ0 = 0x1 // RAM Page Z Select Register Bit 0
|
||||
)
|
||||
|
||||
// Bitfields for BOOT_LOAD: Bootloader
|
||||
const (
|
||||
// SPMCSR: Store Program Memory Control Register
|
||||
SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable
|
||||
SPMCSR_RWWSB = 0x40 // Read While Write Section Busy
|
||||
SPMCSR_RWWSRE = 0x10 // Read While Write section read enable
|
||||
SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set
|
||||
SPMCSR_PGWRT = 0x4 // Page Write
|
||||
SPMCSR_PGERS = 0x2 // Page Erase
|
||||
SPMCSR_SPMEN = 0x1 // Store Program Memory Enable
|
||||
)
|
||||
|
||||
// Bitfields for JTAG: JTAG Interface
|
||||
const (
|
||||
// OCDR: On-Chip Debug Related Register in I/O Memory
|
||||
OCDR_OCDR = 0xff // On-Chip Debug Register Bits
|
||||
)
|
||||
|
||||
// Bitfields for EXINT: External Interrupts
|
||||
const (
|
||||
// EICRA: External Interrupt Control Register A
|
||||
EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit
|
||||
EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit
|
||||
EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit
|
||||
EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit
|
||||
|
||||
// EICRB: External Interrupt Control Register B
|
||||
EICRB_ISC7 = 0xc0 // External Interrupt 7-4 Sense Control Bit
|
||||
EICRB_ISC6 = 0x30 // External Interrupt 7-4 Sense Control Bit
|
||||
EICRB_ISC5 = 0xc // External Interrupt 7-4 Sense Control Bit
|
||||
EICRB_ISC4 = 0x3 // External Interrupt 7-4 Sense Control Bit
|
||||
|
||||
// EIMSK: External Interrupt Mask Register
|
||||
EIMSK_INT = 0xff // External Interrupt Request 7 Enable
|
||||
|
||||
// EIFR: External Interrupt Flag Register
|
||||
EIFR_INTF = 0xff // External Interrupt Flags
|
||||
)
|
||||
|
||||
// Bitfields for EEPROM: EEPROM
|
||||
const (
|
||||
// EECR: EEPROM Control Register
|
||||
EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable
|
||||
EECR_EEMWE = 0x4 // EEPROM Master Write Enable
|
||||
EECR_EEWE = 0x2 // EEPROM Write Enable
|
||||
EECR_EERE = 0x1 // EEPROM Read Enable
|
||||
)
|
||||
|
||||
// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async
|
||||
const (
|
||||
// TCCR0: Timer/Counter Control Register
|
||||
TCCR0_FOC0 = 0x80 // Force Output Compare
|
||||
TCCR0_WGM00 = 0x40 // Waveform Generation Mode 0
|
||||
TCCR0_COM0 = 0x30 // Compare Match Output Modes
|
||||
TCCR0_WGM01 = 0x8 // Waveform Generation Mode 1
|
||||
TCCR0_CS0 = 0x7 // Clock Selects
|
||||
|
||||
// ASSR: Asynchronus Status Register
|
||||
ASSR_AS0 = 0x8 // Asynchronus Timer/Counter 0
|
||||
ASSR_TCN0UB = 0x4 // Timer/Counter0 Update Busy
|
||||
ASSR_OCR0UB = 0x2 // Output Compare register 0 Busy
|
||||
ASSR_TCR0UB = 0x1 // Timer/Counter Control Register 0 Update Busy
|
||||
)
|
||||
|
||||
// Bitfields for TC16: Timer/Counter, 16-bit
|
||||
const (
|
||||
// TCCR1A: Timer/Counter1 Control Register A
|
||||
TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits
|
||||
TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits
|
||||
TCCR1A_COM1C = 0xc // Compare Output Mode 1C, bits
|
||||
TCCR1A_WGM1 = 0x3 // Waveform Generation Mode Bits
|
||||
|
||||
// TCCR1B: Timer/Counter1 Control Register B
|
||||
TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler
|
||||
TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select
|
||||
TCCR1B_WGM1 = 0x18 // Waveform Generation Mode
|
||||
TCCR1B_CS1 = 0x7 // Clock Select1 bits
|
||||
|
||||
// TCCR1C: Timer/Counter1 Control Register C
|
||||
TCCR1C_FOC1A = 0x80 // Force Output Compare for channel A
|
||||
TCCR1C_FOC1B = 0x40 // Force Output Compare for channel B
|
||||
TCCR1C_FOC1C = 0x20 // Force Output Compare for channel C
|
||||
|
||||
// TCCR3A: Timer/Counter3 Control Register A
|
||||
TCCR3A_COM3A = 0xc0 // Compare Output Mode 3A, bits
|
||||
TCCR3A_COM3B = 0x30 // Compare Output Mode 3B, bits
|
||||
TCCR3A_COM3C = 0xc // Compare Output Mode 3C, bits
|
||||
TCCR3A_WGM3 = 0x3 // Waveform Generation Mode Bits
|
||||
|
||||
// TCCR3B: Timer/Counter3 Control Register B
|
||||
TCCR3B_ICNC3 = 0x80 // Input Capture 3 Noise Canceler
|
||||
TCCR3B_ICES3 = 0x40 // Input Capture 3 Edge Select
|
||||
TCCR3B_WGM3 = 0x18 // Waveform Generation Mode
|
||||
TCCR3B_CS3 = 0x7 // Clock Select3 bits
|
||||
|
||||
// TCCR3C: Timer/Counter3 Control Register C
|
||||
TCCR3C_FOC3A = 0x80 // Force Output Compare for channel A
|
||||
TCCR3C_FOC3B = 0x40 // Force Output Compare for channel B
|
||||
TCCR3C_FOC3C = 0x20 // Force Output Compare for channel C
|
||||
)
|
||||
|
||||
// Bitfields for TC8: Timer/Counter, 8-bit
|
||||
const (
|
||||
// TCCR2: Timer/Counter Control Register
|
||||
TCCR2_FOC2 = 0x80 // Force Output Compare
|
||||
TCCR2_WGM20 = 0x40 // Wafeform Generation Mode
|
||||
TCCR2_COM2 = 0x30 // Compare Match Output Mode
|
||||
TCCR2_WGM21 = 0x8 // Waveform Generation Mode
|
||||
TCCR2_CS2 = 0x7 // Clock Select
|
||||
)
|
||||
|
||||
// Bitfields for WDT: Watchdog Timer
|
||||
const (
|
||||
// WDTCR: Watchdog Timer Control Register
|
||||
WDTCR_WDCE = 0x10 // Watchdog Change Enable
|
||||
WDTCR_WDE = 0x8 // Watch Dog Enable
|
||||
WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits
|
||||
)
|
||||
|
||||
// Bitfields for ADC: Analog-to-Digital Converter
|
||||
const (
|
||||
// ADMUX: The ADC multiplexer Selection Register
|
||||
ADMUX_REFS = 0xc0 // Reference Selection Bits
|
||||
ADMUX_ADLAR = 0x20 // Left Adjust Result
|
||||
ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits
|
||||
|
||||
// ADCSRA: The ADC Control and Status register
|
||||
ADCSRA_ADEN = 0x80 // ADC Enable
|
||||
ADCSRA_ADSC = 0x40 // ADC Start Conversion
|
||||
ADCSRA_ADFR = 0x20 // ADC Free Running Select
|
||||
ADCSRA_ADIF = 0x10 // ADC Interrupt Flag
|
||||
ADCSRA_ADIE = 0x8 // ADC Interrupt Enable
|
||||
ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits
|
||||
)
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from ATmega128.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x20000;
|
||||
__ram_size = 0x1000;
|
||||
__num_isrs = 35;
|
||||
Различия файлов не показаны, т.к. их слишком много
Показать различия
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from ATmega1280.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x20000;
|
||||
__ram_size = 0x2000;
|
||||
__num_isrs = 57;
|
||||
|
|
@ -1,986 +0,0 @@
|
|||
// Automatically generated file. DO NOT EDIT.
|
||||
// Generated by gen-device.py from ATmega1281.atdf, see http://packs.download.atmel.com/
|
||||
|
||||
// +build avr,atmega1281
|
||||
|
||||
// Device information for the ATmega1281.
|
||||
//
|
||||
package avr
|
||||
|
||||
// Magic type name for the compiler.
|
||||
type __reg uint8
|
||||
|
||||
// Export this magic type name.
|
||||
type RegValue = __reg
|
||||
|
||||
// Some information about this device.
|
||||
const (
|
||||
DEVICE = "ATmega1281"
|
||||
ARCH = "AVR8"
|
||||
FAMILY = "megaAVR"
|
||||
)
|
||||
|
||||
// Interrupts
|
||||
const (
|
||||
IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet.
|
||||
IRQ_INT0 = 1 // External Interrupt Request 0
|
||||
IRQ_INT1 = 2 // External Interrupt Request 1
|
||||
IRQ_INT2 = 3 // External Interrupt Request 2
|
||||
IRQ_INT3 = 4 // External Interrupt Request 3
|
||||
IRQ_INT4 = 5 // External Interrupt Request 4
|
||||
IRQ_INT5 = 6 // External Interrupt Request 5
|
||||
IRQ_INT6 = 7 // External Interrupt Request 6
|
||||
IRQ_INT7 = 8 // External Interrupt Request 7
|
||||
IRQ_PCINT0 = 9 // Pin Change Interrupt Request 0
|
||||
IRQ_PCINT1 = 10 // Pin Change Interrupt Request 1
|
||||
IRQ_PCINT2 = 11 // Pin Change Interrupt Request 2
|
||||
IRQ_WDT = 12 // Watchdog Time-out Interrupt
|
||||
IRQ_TIMER2_COMPA = 13 // Timer/Counter2 Compare Match A
|
||||
IRQ_TIMER2_COMPB = 14 // Timer/Counter2 Compare Match B
|
||||
IRQ_TIMER2_OVF = 15 // Timer/Counter2 Overflow
|
||||
IRQ_TIMER1_CAPT = 16 // Timer/Counter1 Capture Event
|
||||
IRQ_TIMER1_COMPA = 17 // Timer/Counter1 Compare Match A
|
||||
IRQ_TIMER1_COMPB = 18 // Timer/Counter1 Compare Match B
|
||||
IRQ_TIMER1_COMPC = 19 // Timer/Counter1 Compare Match C
|
||||
IRQ_TIMER1_OVF = 20 // Timer/Counter1 Overflow
|
||||
IRQ_TIMER0_COMPA = 21 // Timer/Counter0 Compare Match A
|
||||
IRQ_TIMER0_COMPB = 22 // Timer/Counter0 Compare Match B
|
||||
IRQ_TIMER0_OVF = 23 // Timer/Counter0 Overflow
|
||||
IRQ_SPI_STC = 24 // SPI Serial Transfer Complete
|
||||
IRQ_USART0_RX = 25 // USART0, Rx Complete
|
||||
IRQ_USART0_UDRE = 26 // USART0 Data register Empty
|
||||
IRQ_USART0_TX = 27 // USART0, Tx Complete
|
||||
IRQ_ANALOG_COMP = 28 // Analog Comparator
|
||||
IRQ_ADC = 29 // ADC Conversion Complete
|
||||
IRQ_EE_READY = 30 // EEPROM Ready
|
||||
IRQ_TIMER3_CAPT = 31 // Timer/Counter3 Capture Event
|
||||
IRQ_TIMER3_COMPA = 32 // Timer/Counter3 Compare Match A
|
||||
IRQ_TIMER3_COMPB = 33 // Timer/Counter3 Compare Match B
|
||||
IRQ_TIMER3_COMPC = 34 // Timer/Counter3 Compare Match C
|
||||
IRQ_TIMER3_OVF = 35 // Timer/Counter3 Overflow
|
||||
IRQ_USART1_RX = 36 // USART1, Rx Complete
|
||||
IRQ_USART1_UDRE = 37 // USART1 Data register Empty
|
||||
IRQ_USART1_TX = 38 // USART1, Tx Complete
|
||||
IRQ_TWI = 39 // 2-wire Serial Interface
|
||||
IRQ_SPM_READY = 40 // Store Program Memory Read
|
||||
IRQ_TIMER4_CAPT = 41 // Timer/Counter4 Capture Event
|
||||
IRQ_TIMER4_COMPA = 42 // Timer/Counter4 Compare Match A
|
||||
IRQ_TIMER4_COMPB = 43 // Timer/Counter4 Compare Match B
|
||||
IRQ_TIMER4_COMPC = 44 // Timer/Counter4 Compare Match C
|
||||
IRQ_TIMER4_OVF = 45 // Timer/Counter4 Overflow
|
||||
IRQ_TIMER5_CAPT = 46 // Timer/Counter5 Capture Event
|
||||
IRQ_TIMER5_COMPA = 47 // Timer/Counter5 Compare Match A
|
||||
IRQ_TIMER5_COMPB = 48 // Timer/Counter5 Compare Match B
|
||||
IRQ_TIMER5_COMPC = 49 // Timer/Counter5 Compare Match C
|
||||
IRQ_TIMER5_OVF = 50 // Timer/Counter5 Overflow
|
||||
IRQ_USART2_RX = 51 // USART2, Rx Complete
|
||||
IRQ_USART2_UDRE = 52 // USART2 Data register Empty
|
||||
IRQ_USART2_TX = 53 // USART2, Tx Complete
|
||||
IRQ_USART3_RX = 54 // USART3, Rx Complete
|
||||
IRQ_USART3_UDRE = 55 // USART3 Data register Empty
|
||||
IRQ_USART3_TX = 56 // USART3, Tx Complete
|
||||
IRQ_max = 56 // Highest interrupt number on this device.
|
||||
)
|
||||
|
||||
// Peripherals
|
||||
var (
|
||||
// Fuses
|
||||
FUSE = struct {
|
||||
EXTENDED __reg
|
||||
HIGH __reg
|
||||
LOW __reg
|
||||
}{
|
||||
EXTENDED: 0x2,
|
||||
HIGH: 0x1,
|
||||
LOW: 0x0,
|
||||
}
|
||||
|
||||
// Lockbits
|
||||
LOCKBIT = struct {
|
||||
LOCKBIT __reg
|
||||
}{
|
||||
LOCKBIT: 0x0,
|
||||
}
|
||||
|
||||
// Analog Comparator
|
||||
AC = struct {
|
||||
ACSR __reg
|
||||
DIDR1 __reg
|
||||
}{
|
||||
ACSR: 0x50, // Analog Comparator Control And Status Register
|
||||
DIDR1: 0x7f, // Digital Input Disable Register 1
|
||||
}
|
||||
|
||||
// USART
|
||||
USART = struct {
|
||||
UDR0 __reg
|
||||
UCSR0A __reg
|
||||
UCSR0B __reg
|
||||
UCSR0C __reg
|
||||
UBRR0L __reg
|
||||
UBRR0H __reg
|
||||
UDR1 __reg
|
||||
UCSR1A __reg
|
||||
UCSR1B __reg
|
||||
UCSR1C __reg
|
||||
UBRR1L __reg
|
||||
UBRR1H __reg
|
||||
}{
|
||||
UDR0: 0xc6, // USART I/O Data Register
|
||||
UCSR0A: 0xc0, // USART Control and Status Register A
|
||||
UCSR0B: 0xc1, // USART Control and Status Register B
|
||||
UCSR0C: 0xc2, // USART Control and Status Register C
|
||||
UBRR0L: 0xc4, // USART Baud Rate Register Bytes
|
||||
UBRR0H: 0xc4, // USART Baud Rate Register Bytes
|
||||
UDR1: 0xce, // USART I/O Data Register
|
||||
UCSR1A: 0xc8, // USART Control and Status Register A
|
||||
UCSR1B: 0xc9, // USART Control and Status Register B
|
||||
UCSR1C: 0xca, // USART Control and Status Register C
|
||||
UBRR1L: 0xcc, // USART Baud Rate Register Bytes
|
||||
UBRR1H: 0xcc, // USART Baud Rate Register Bytes
|
||||
}
|
||||
|
||||
// Two Wire Serial Interface
|
||||
TWI = struct {
|
||||
TWAMR __reg
|
||||
TWBR __reg
|
||||
TWCR __reg
|
||||
TWSR __reg
|
||||
TWDR __reg
|
||||
TWAR __reg
|
||||
}{
|
||||
TWAMR: 0xbd, // TWI (Slave) Address Mask Register
|
||||
TWBR: 0xb8, // TWI Bit Rate register
|
||||
TWCR: 0xbc, // TWI Control Register
|
||||
TWSR: 0xb9, // TWI Status Register
|
||||
TWDR: 0xbb, // TWI Data register
|
||||
TWAR: 0xba, // TWI (Slave) Address register
|
||||
}
|
||||
|
||||
// Serial Peripheral Interface
|
||||
SPI = struct {
|
||||
SPCR __reg
|
||||
SPSR __reg
|
||||
SPDR __reg
|
||||
}{
|
||||
SPCR: 0x4c, // SPI Control Register
|
||||
SPSR: 0x4d, // SPI Status Register
|
||||
SPDR: 0x4e, // SPI Data Register
|
||||
}
|
||||
|
||||
// I/O Port
|
||||
PORT = struct {
|
||||
PORTA __reg
|
||||
DDRA __reg
|
||||
PINA __reg
|
||||
PORTB __reg
|
||||
DDRB __reg
|
||||
PINB __reg
|
||||
PORTC __reg
|
||||
DDRC __reg
|
||||
PINC __reg
|
||||
PORTD __reg
|
||||
DDRD __reg
|
||||
PIND __reg
|
||||
PORTE __reg
|
||||
DDRE __reg
|
||||
PINE __reg
|
||||
PORTF __reg
|
||||
DDRF __reg
|
||||
PINF __reg
|
||||
PORTG __reg
|
||||
DDRG __reg
|
||||
PING __reg
|
||||
}{
|
||||
PORTA: 0x22, // Port A Data Register
|
||||
DDRA: 0x21, // Port A Data Direction Register
|
||||
PINA: 0x20, // Port A Input Pins
|
||||
PORTB: 0x25, // Port B Data Register
|
||||
DDRB: 0x24, // Port B Data Direction Register
|
||||
PINB: 0x23, // Port B Input Pins
|
||||
PORTC: 0x28, // Port C Data Register
|
||||
DDRC: 0x27, // Port C Data Direction Register
|
||||
PINC: 0x26, // Port C Input Pins
|
||||
PORTD: 0x2b, // Port D Data Register
|
||||
DDRD: 0x2a, // Port D Data Direction Register
|
||||
PIND: 0x29, // Port D Input Pins
|
||||
PORTE: 0x2e, // Data Register, Port E
|
||||
DDRE: 0x2d, // Data Direction Register, Port E
|
||||
PINE: 0x2c, // Input Pins, Port E
|
||||
PORTF: 0x31, // Data Register, Port F
|
||||
DDRF: 0x30, // Data Direction Register, Port F
|
||||
PINF: 0x2f, // Input Pins, Port F
|
||||
PORTG: 0x34, // Data Register, Port G
|
||||
DDRG: 0x33, // Data Direction Register, Port G
|
||||
PING: 0x32, // Input Pins, Port G
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit
|
||||
TC8 = struct {
|
||||
OCR0B __reg
|
||||
OCR0A __reg
|
||||
TCNT0 __reg
|
||||
TCCR0B __reg
|
||||
TCCR0A __reg
|
||||
TIMSK0 __reg
|
||||
TIFR0 __reg
|
||||
}{
|
||||
OCR0B: 0x48, // Timer/Counter0 Output Compare Register
|
||||
OCR0A: 0x47, // Timer/Counter0 Output Compare Register
|
||||
TCNT0: 0x46, // Timer/Counter0
|
||||
TCCR0B: 0x45, // Timer/Counter Control Register B
|
||||
TCCR0A: 0x44, // Timer/Counter Control Register A
|
||||
TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register
|
||||
TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit Async
|
||||
TC8_ASYNC = struct {
|
||||
TIMSK2 __reg
|
||||
TIFR2 __reg
|
||||
TCCR2A __reg
|
||||
TCCR2B __reg
|
||||
TCNT2 __reg
|
||||
OCR2B __reg
|
||||
OCR2A __reg
|
||||
ASSR __reg
|
||||
}{
|
||||
TIMSK2: 0x70, // Timer/Counter Interrupt Mask register
|
||||
TIFR2: 0x37, // Timer/Counter Interrupt Flag Register
|
||||
TCCR2A: 0xb0, // Timer/Counter2 Control Register A
|
||||
TCCR2B: 0xb1, // Timer/Counter2 Control Register B
|
||||
TCNT2: 0xb2, // Timer/Counter2
|
||||
OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B
|
||||
OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A
|
||||
ASSR: 0xb6, // Asynchronous Status Register
|
||||
}
|
||||
|
||||
// Watchdog Timer
|
||||
WDT = struct {
|
||||
WDTCSR __reg
|
||||
}{
|
||||
WDTCSR: 0x60, // Watchdog Timer Control Register
|
||||
}
|
||||
|
||||
// Timer/Counter, 16-bit
|
||||
TC16 = struct {
|
||||
TCCR5A __reg
|
||||
TCCR5B __reg
|
||||
TCCR5C __reg
|
||||
TCNT5L __reg
|
||||
TCNT5H __reg
|
||||
OCR5AL __reg
|
||||
OCR5AH __reg
|
||||
OCR5BL __reg
|
||||
OCR5BH __reg
|
||||
OCR5CL __reg
|
||||
OCR5CH __reg
|
||||
ICR5L __reg
|
||||
ICR5H __reg
|
||||
TIMSK5 __reg
|
||||
TIFR5 __reg
|
||||
TCCR4A __reg
|
||||
TCCR4B __reg
|
||||
TCCR4C __reg
|
||||
TCNT4L __reg
|
||||
TCNT4H __reg
|
||||
OCR4AL __reg
|
||||
OCR4AH __reg
|
||||
OCR4BL __reg
|
||||
OCR4BH __reg
|
||||
OCR4CL __reg
|
||||
OCR4CH __reg
|
||||
ICR4L __reg
|
||||
ICR4H __reg
|
||||
TIMSK4 __reg
|
||||
TIFR4 __reg
|
||||
TCCR3A __reg
|
||||
TCCR3B __reg
|
||||
TCCR3C __reg
|
||||
TCNT3L __reg
|
||||
TCNT3H __reg
|
||||
OCR3AL __reg
|
||||
OCR3AH __reg
|
||||
OCR3BL __reg
|
||||
OCR3BH __reg
|
||||
OCR3CL __reg
|
||||
OCR3CH __reg
|
||||
ICR3L __reg
|
||||
ICR3H __reg
|
||||
TIMSK3 __reg
|
||||
TIFR3 __reg
|
||||
TCCR1A __reg
|
||||
TCCR1B __reg
|
||||
TCCR1C __reg
|
||||
TCNT1L __reg
|
||||
TCNT1H __reg
|
||||
OCR1AL __reg
|
||||
OCR1AH __reg
|
||||
OCR1BL __reg
|
||||
OCR1BH __reg
|
||||
OCR1CL __reg
|
||||
OCR1CH __reg
|
||||
ICR1L __reg
|
||||
ICR1H __reg
|
||||
TIMSK1 __reg
|
||||
TIFR1 __reg
|
||||
}{
|
||||
TCCR5A: 0x120, // Timer/Counter5 Control Register A
|
||||
TCCR5B: 0x121, // Timer/Counter5 Control Register B
|
||||
TCCR5C: 0x122, // Timer/Counter 5 Control Register C
|
||||
TCNT5L: 0x124, // Timer/Counter5 Bytes
|
||||
TCNT5H: 0x124, // Timer/Counter5 Bytes
|
||||
OCR5AL: 0x128, // Timer/Counter5 Output Compare Register A Bytes
|
||||
OCR5AH: 0x128, // Timer/Counter5 Output Compare Register A Bytes
|
||||
OCR5BL: 0x12a, // Timer/Counter5 Output Compare Register B Bytes
|
||||
OCR5BH: 0x12a, // Timer/Counter5 Output Compare Register B Bytes
|
||||
OCR5CL: 0x12c, // Timer/Counter5 Output Compare Register B Bytes
|
||||
OCR5CH: 0x12c, // Timer/Counter5 Output Compare Register B Bytes
|
||||
ICR5L: 0x126, // Timer/Counter5 Input Capture Register Bytes
|
||||
ICR5H: 0x126, // Timer/Counter5 Input Capture Register Bytes
|
||||
TIMSK5: 0x73, // Timer/Counter5 Interrupt Mask Register
|
||||
TIFR5: 0x3a, // Timer/Counter5 Interrupt Flag register
|
||||
TCCR4A: 0xa0, // Timer/Counter4 Control Register A
|
||||
TCCR4B: 0xa1, // Timer/Counter4 Control Register B
|
||||
TCCR4C: 0xa2, // Timer/Counter 4 Control Register C
|
||||
TCNT4L: 0xa4, // Timer/Counter4 Bytes
|
||||
TCNT4H: 0xa4, // Timer/Counter4 Bytes
|
||||
OCR4AL: 0xa8, // Timer/Counter4 Output Compare Register A Bytes
|
||||
OCR4AH: 0xa8, // Timer/Counter4 Output Compare Register A Bytes
|
||||
OCR4BL: 0xaa, // Timer/Counter4 Output Compare Register B Bytes
|
||||
OCR4BH: 0xaa, // Timer/Counter4 Output Compare Register B Bytes
|
||||
OCR4CL: 0xac, // Timer/Counter4 Output Compare Register B Bytes
|
||||
OCR4CH: 0xac, // Timer/Counter4 Output Compare Register B Bytes
|
||||
ICR4L: 0xa6, // Timer/Counter4 Input Capture Register Bytes
|
||||
ICR4H: 0xa6, // Timer/Counter4 Input Capture Register Bytes
|
||||
TIMSK4: 0x72, // Timer/Counter4 Interrupt Mask Register
|
||||
TIFR4: 0x39, // Timer/Counter4 Interrupt Flag register
|
||||
TCCR3A: 0x90, // Timer/Counter3 Control Register A
|
||||
TCCR3B: 0x91, // Timer/Counter3 Control Register B
|
||||
TCCR3C: 0x92, // Timer/Counter 3 Control Register C
|
||||
TCNT3L: 0x94, // Timer/Counter3 Bytes
|
||||
TCNT3H: 0x94, // Timer/Counter3 Bytes
|
||||
OCR3AL: 0x98, // Timer/Counter3 Output Compare Register A Bytes
|
||||
OCR3AH: 0x98, // Timer/Counter3 Output Compare Register A Bytes
|
||||
OCR3BL: 0x9a, // Timer/Counter3 Output Compare Register B Bytes
|
||||
OCR3BH: 0x9a, // Timer/Counter3 Output Compare Register B Bytes
|
||||
OCR3CL: 0x9c, // Timer/Counter3 Output Compare Register B Bytes
|
||||
OCR3CH: 0x9c, // Timer/Counter3 Output Compare Register B Bytes
|
||||
ICR3L: 0x96, // Timer/Counter3 Input Capture Register Bytes
|
||||
ICR3H: 0x96, // Timer/Counter3 Input Capture Register Bytes
|
||||
TIMSK3: 0x71, // Timer/Counter3 Interrupt Mask Register
|
||||
TIFR3: 0x38, // Timer/Counter3 Interrupt Flag register
|
||||
TCCR1A: 0x80, // Timer/Counter1 Control Register A
|
||||
TCCR1B: 0x81, // Timer/Counter1 Control Register B
|
||||
TCCR1C: 0x82, // Timer/Counter 1 Control Register C
|
||||
TCNT1L: 0x84, // Timer/Counter1 Bytes
|
||||
TCNT1H: 0x84, // Timer/Counter1 Bytes
|
||||
OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes
|
||||
OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes
|
||||
OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes
|
||||
OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes
|
||||
OCR1CL: 0x8c, // Timer/Counter1 Output Compare Register C Bytes
|
||||
OCR1CH: 0x8c, // Timer/Counter1 Output Compare Register C Bytes
|
||||
ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register
|
||||
TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register
|
||||
}
|
||||
|
||||
// EEPROM
|
||||
EEPROM = struct {
|
||||
EEARL __reg
|
||||
EEARH __reg
|
||||
EEDR __reg
|
||||
EECR __reg
|
||||
}{
|
||||
EEARL: 0x41, // EEPROM Address Register Low Bytes
|
||||
EEARH: 0x41, // EEPROM Address Register Low Bytes
|
||||
EEDR: 0x40, // EEPROM Data Register
|
||||
EECR: 0x3f, // EEPROM Control Register
|
||||
}
|
||||
|
||||
// JTAG Interface
|
||||
JTAG = struct {
|
||||
OCDR __reg
|
||||
}{
|
||||
OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory
|
||||
}
|
||||
|
||||
// External Interrupts
|
||||
EXINT = struct {
|
||||
EICRA __reg
|
||||
EICRB __reg
|
||||
EIMSK __reg
|
||||
EIFR __reg
|
||||
PCMSK2 __reg
|
||||
PCMSK1 __reg
|
||||
PCMSK0 __reg
|
||||
PCIFR __reg
|
||||
PCICR __reg
|
||||
}{
|
||||
EICRA: 0x69, // External Interrupt Control Register A
|
||||
EICRB: 0x6a, // External Interrupt Control Register B
|
||||
EIMSK: 0x3d, // External Interrupt Mask Register
|
||||
EIFR: 0x3c, // External Interrupt Flag Register
|
||||
PCMSK2: 0x6d, // Pin Change Mask Register 2
|
||||
PCMSK1: 0x6c, // Pin Change Mask Register 1
|
||||
PCMSK0: 0x6b, // Pin Change Mask Register 0
|
||||
PCIFR: 0x3b, // Pin Change Interrupt Flag Register
|
||||
PCICR: 0x68, // Pin Change Interrupt Control Register
|
||||
}
|
||||
|
||||
// Analog-to-Digital Converter
|
||||
ADC = struct {
|
||||
ADMUX __reg
|
||||
ADCL __reg
|
||||
ADCH __reg
|
||||
ADCSRA __reg
|
||||
DIDR2 __reg
|
||||
DIDR0 __reg
|
||||
}{
|
||||
ADMUX: 0x7c, // The ADC multiplexer Selection Register
|
||||
ADCL: 0x78, // ADC Data Register Bytes
|
||||
ADCH: 0x78, // ADC Data Register Bytes
|
||||
ADCSRA: 0x7a, // The ADC Control and Status register A
|
||||
DIDR2: 0x7d, // Digital Input Disable Register
|
||||
DIDR0: 0x7e, // Digital Input Disable Register
|
||||
}
|
||||
|
||||
// Bootloader
|
||||
BOOT_LOAD = struct {
|
||||
SPMCSR __reg
|
||||
}{
|
||||
SPMCSR: 0x57, // Store Program Memory Control Register
|
||||
}
|
||||
|
||||
// CPU Registers
|
||||
CPU = struct {
|
||||
SREG __reg
|
||||
SPL __reg
|
||||
SPH __reg
|
||||
XMCRA __reg
|
||||
XMCRB __reg
|
||||
OSCCAL __reg
|
||||
CLKPR __reg
|
||||
SMCR __reg
|
||||
RAMPZ __reg
|
||||
GPIOR2 __reg
|
||||
GPIOR1 __reg
|
||||
GPIOR0 __reg
|
||||
PRR1 __reg
|
||||
PRR0 __reg
|
||||
}{
|
||||
SREG: 0x5f, // Status Register
|
||||
SPL: 0x5d, // Stack Pointer
|
||||
SPH: 0x5d, // Stack Pointer
|
||||
XMCRA: 0x74, // External Memory Control Register A
|
||||
XMCRB: 0x75, // External Memory Control Register B
|
||||
OSCCAL: 0x66, // Oscillator Calibration Value
|
||||
CLKPR: 0x61,
|
||||
SMCR: 0x53, // Sleep Mode Control Register
|
||||
RAMPZ: 0x5b, // RAM Page Z Select Register
|
||||
GPIOR2: 0x4b, // General Purpose IO Register 2
|
||||
GPIOR1: 0x4a, // General Purpose IO Register 1
|
||||
GPIOR0: 0x3e, // General Purpose IO Register 0
|
||||
PRR1: 0x65, // Power Reduction Register1
|
||||
PRR0: 0x64, // Power Reduction Register0
|
||||
}
|
||||
)
|
||||
|
||||
// Bitfields for FUSE: Fuses
|
||||
const (
|
||||
// EXTENDED
|
||||
EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level
|
||||
|
||||
// HIGH
|
||||
HIGH_OCDEN = 0x80 // On-Chip Debug Enabled
|
||||
HIGH_JTAGEN = 0x40 // JTAG Interface Enabled
|
||||
HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled
|
||||
HIGH_WDTON = 0x10 // Watchdog timer always on
|
||||
HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle
|
||||
HIGH_BOOTSZ = 0x6 // Select Boot Size
|
||||
HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled
|
||||
|
||||
// LOW
|
||||
LOW_CKDIV8 = 0x80 // Divide clock by 8 internally
|
||||
LOW_CKOUT = 0x40 // Clock output on PORTE7
|
||||
LOW_SUT_CKSEL = 0x3f // Select Clock Source
|
||||
)
|
||||
|
||||
// Bitfields for LOCKBIT: Lockbits
|
||||
const (
|
||||
// LOCKBIT
|
||||
LOCKBIT_LB = 0x3 // Memory Lock
|
||||
LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode
|
||||
LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode
|
||||
)
|
||||
|
||||
// Bitfields for AC: Analog Comparator
|
||||
const (
|
||||
// ACSR: Analog Comparator Control And Status Register
|
||||
ACSR_ACD = 0x80 // Analog Comparator Disable
|
||||
ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select
|
||||
ACSR_ACO = 0x20 // Analog Compare Output
|
||||
ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag
|
||||
ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable
|
||||
ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable
|
||||
ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits
|
||||
|
||||
// DIDR1: Digital Input Disable Register 1
|
||||
DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable
|
||||
DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable
|
||||
)
|
||||
|
||||
// Bitfields for USART: USART
|
||||
const (
|
||||
// UCSR0A: USART Control and Status Register A
|
||||
UCSR0A_RXC0 = 0x80 // USART Receive Complete
|
||||
UCSR0A_TXC0 = 0x40 // USART Transmitt Complete
|
||||
UCSR0A_UDRE0 = 0x20 // USART Data Register Empty
|
||||
UCSR0A_FE0 = 0x10 // Framing Error
|
||||
UCSR0A_DOR0 = 0x8 // Data overRun
|
||||
UCSR0A_UPE0 = 0x4 // Parity Error
|
||||
UCSR0A_U2X0 = 0x2 // Double the USART transmission speed
|
||||
UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode
|
||||
|
||||
// UCSR0B: USART Control and Status Register B
|
||||
UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable
|
||||
UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable
|
||||
UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable
|
||||
UCSR0B_RXEN0 = 0x10 // Receiver Enable
|
||||
UCSR0B_TXEN0 = 0x8 // Transmitter Enable
|
||||
UCSR0B_UCSZ02 = 0x4 // Character Size
|
||||
UCSR0B_RXB80 = 0x2 // Receive Data Bit 8
|
||||
UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8
|
||||
|
||||
// UCSR0C: USART Control and Status Register C
|
||||
UCSR0C_UMSEL0 = 0xc0 // USART Mode Select
|
||||
UCSR0C_UPM0 = 0x30 // Parity Mode Bits
|
||||
UCSR0C_USBS0 = 0x8 // Stop Bit Select
|
||||
UCSR0C_UCSZ0 = 0x6 // Character Size
|
||||
UCSR0C_UCPOL0 = 0x1 // Clock Polarity
|
||||
|
||||
// UCSR1A: USART Control and Status Register A
|
||||
UCSR1A_RXC1 = 0x80 // USART Receive Complete
|
||||
UCSR1A_TXC1 = 0x40 // USART Transmitt Complete
|
||||
UCSR1A_UDRE1 = 0x20 // USART Data Register Empty
|
||||
UCSR1A_FE1 = 0x10 // Framing Error
|
||||
UCSR1A_DOR1 = 0x8 // Data overRun
|
||||
UCSR1A_UPE1 = 0x4 // Parity Error
|
||||
UCSR1A_U2X1 = 0x2 // Double the USART transmission speed
|
||||
UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode
|
||||
|
||||
// UCSR1B: USART Control and Status Register B
|
||||
UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable
|
||||
UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable
|
||||
UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable
|
||||
UCSR1B_RXEN1 = 0x10 // Receiver Enable
|
||||
UCSR1B_TXEN1 = 0x8 // Transmitter Enable
|
||||
UCSR1B_UCSZ12 = 0x4 // Character Size
|
||||
UCSR1B_RXB81 = 0x2 // Receive Data Bit 8
|
||||
UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8
|
||||
|
||||
// UCSR1C: USART Control and Status Register C
|
||||
UCSR1C_UMSEL1 = 0xc0 // USART Mode Select
|
||||
UCSR1C_UPM1 = 0x30 // Parity Mode Bits
|
||||
UCSR1C_USBS1 = 0x8 // Stop Bit Select
|
||||
UCSR1C_UCSZ1 = 0x6 // Character Size
|
||||
UCSR1C_UCPOL1 = 0x1 // Clock Polarity
|
||||
)
|
||||
|
||||
// Bitfields for TWI: Two Wire Serial Interface
|
||||
const (
|
||||
// TWAMR: TWI (Slave) Address Mask Register
|
||||
TWAMR_TWAM = 0xfe
|
||||
|
||||
// TWCR: TWI Control Register
|
||||
TWCR_TWINT = 0x80 // TWI Interrupt Flag
|
||||
TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit
|
||||
TWCR_TWSTA = 0x20 // TWI Start Condition Bit
|
||||
TWCR_TWSTO = 0x10 // TWI Stop Condition Bit
|
||||
TWCR_TWWC = 0x8 // TWI Write Collition Flag
|
||||
TWCR_TWEN = 0x4 // TWI Enable Bit
|
||||
TWCR_TWIE = 0x1 // TWI Interrupt Enable
|
||||
|
||||
// TWSR: TWI Status Register
|
||||
TWSR_TWS = 0xf8 // TWI Status
|
||||
TWSR_TWPS = 0x3 // TWI Prescaler
|
||||
|
||||
// TWAR: TWI (Slave) Address register
|
||||
TWAR_TWA = 0xfe // TWI (Slave) Address register Bits
|
||||
TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit
|
||||
)
|
||||
|
||||
// Bitfields for SPI: Serial Peripheral Interface
|
||||
const (
|
||||
// SPCR: SPI Control Register
|
||||
SPCR_SPIE = 0x80 // SPI Interrupt Enable
|
||||
SPCR_SPE = 0x40 // SPI Enable
|
||||
SPCR_DORD = 0x20 // Data Order
|
||||
SPCR_MSTR = 0x10 // Master/Slave Select
|
||||
SPCR_CPOL = 0x8 // Clock polarity
|
||||
SPCR_CPHA = 0x4 // Clock Phase
|
||||
SPCR_SPR = 0x3 // SPI Clock Rate Selects
|
||||
|
||||
// SPSR: SPI Status Register
|
||||
SPSR_SPIF = 0x80 // SPI Interrupt Flag
|
||||
SPSR_WCOL = 0x40 // Write Collision Flag
|
||||
SPSR_SPI2X = 0x1 // Double SPI Speed Bit
|
||||
)
|
||||
|
||||
// Bitfields for TC8: Timer/Counter, 8-bit
|
||||
const (
|
||||
// TCCR0B: Timer/Counter Control Register B
|
||||
TCCR0B_FOC0A = 0x80 // Force Output Compare A
|
||||
TCCR0B_FOC0B = 0x40 // Force Output Compare B
|
||||
TCCR0B_WGM02 = 0x8
|
||||
TCCR0B_CS0 = 0x7 // Clock Select
|
||||
|
||||
// TCCR0A: Timer/Counter Control Register A
|
||||
TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode
|
||||
TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm
|
||||
TCCR0A_WGM0 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TIMSK0: Timer/Counter0 Interrupt Mask Register
|
||||
TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable
|
||||
TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable
|
||||
TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable
|
||||
|
||||
// TIFR0: Timer/Counter0 Interrupt Flag register
|
||||
TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B
|
||||
TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A
|
||||
TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag
|
||||
)
|
||||
|
||||
// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async
|
||||
const (
|
||||
// TIMSK2: Timer/Counter Interrupt Mask register
|
||||
TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable
|
||||
TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable
|
||||
TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable
|
||||
|
||||
// TIFR2: Timer/Counter Interrupt Flag Register
|
||||
TIFR2_OCF2B = 0x4 // Output Compare Flag 2B
|
||||
TIFR2_OCF2A = 0x2 // Output Compare Flag 2A
|
||||
TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag
|
||||
|
||||
// TCCR2A: Timer/Counter2 Control Register A
|
||||
TCCR2A_COM2A = 0xc0 // Compare Output Mode bits
|
||||
TCCR2A_COM2B = 0x30 // Compare Output Mode bits
|
||||
TCCR2A_WGM2 = 0x3 // Waveform Genration Mode
|
||||
|
||||
// TCCR2B: Timer/Counter2 Control Register B
|
||||
TCCR2B_FOC2A = 0x80 // Force Output Compare A
|
||||
TCCR2B_FOC2B = 0x40 // Force Output Compare B
|
||||
TCCR2B_WGM22 = 0x8 // Waveform Generation Mode
|
||||
TCCR2B_CS2 = 0x7 // Clock Select bits
|
||||
|
||||
// ASSR: Asynchronous Status Register
|
||||
ASSR_EXCLK = 0x40 // Enable External Clock Input
|
||||
ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2
|
||||
ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy
|
||||
ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy
|
||||
ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy
|
||||
ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy
|
||||
ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy
|
||||
)
|
||||
|
||||
// Bitfields for WDT: Watchdog Timer
|
||||
const (
|
||||
// WDTCSR: Watchdog Timer Control Register
|
||||
WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag
|
||||
WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable
|
||||
WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits
|
||||
WDTCSR_WDCE = 0x10 // Watchdog Change Enable
|
||||
WDTCSR_WDE = 0x8 // Watch Dog Enable
|
||||
)
|
||||
|
||||
// Bitfields for TC16: Timer/Counter, 16-bit
|
||||
const (
|
||||
// TCCR5A: Timer/Counter5 Control Register A
|
||||
TCCR5A_COM5A = 0xc0 // Compare Output Mode 1A, bits
|
||||
TCCR5A_COM5B = 0x30 // Compare Output Mode 5B, bits
|
||||
TCCR5A_COM5C = 0xc // Compare Output Mode 5C, bits
|
||||
TCCR5A_WGM5 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TCCR5B: Timer/Counter5 Control Register B
|
||||
TCCR5B_ICNC5 = 0x80 // Input Capture 5 Noise Canceler
|
||||
TCCR5B_ICES5 = 0x40 // Input Capture 5 Edge Select
|
||||
TCCR5B_WGM5 = 0x18 // Waveform Generation Mode
|
||||
TCCR5B_CS5 = 0x7 // Prescaler source of Timer/Counter 5
|
||||
|
||||
// TCCR5C: Timer/Counter 5 Control Register C
|
||||
TCCR5C_FOC5A = 0x80 // Force Output Compare 5A
|
||||
TCCR5C_FOC5B = 0x40 // Force Output Compare 5B
|
||||
TCCR5C_FOC5C = 0x20 // Force Output Compare 5C
|
||||
|
||||
// TIMSK5: Timer/Counter5 Interrupt Mask Register
|
||||
TIMSK5_ICIE5 = 0x20 // Timer/Counter5 Input Capture Interrupt Enable
|
||||
TIMSK5_OCIE5C = 0x8 // Timer/Counter5 Output Compare C Match Interrupt Enable
|
||||
TIMSK5_OCIE5B = 0x4 // Timer/Counter5 Output Compare B Match Interrupt Enable
|
||||
TIMSK5_OCIE5A = 0x2 // Timer/Counter5 Output Compare A Match Interrupt Enable
|
||||
TIMSK5_TOIE5 = 0x1 // Timer/Counter5 Overflow Interrupt Enable
|
||||
|
||||
// TIFR5: Timer/Counter5 Interrupt Flag register
|
||||
TIFR5_ICF5 = 0x20 // Input Capture Flag 5
|
||||
TIFR5_OCF5C = 0x8 // Output Compare Flag 5C
|
||||
TIFR5_OCF5B = 0x4 // Output Compare Flag 5B
|
||||
TIFR5_OCF5A = 0x2 // Output Compare Flag 5A
|
||||
TIFR5_TOV5 = 0x1 // Timer/Counter5 Overflow Flag
|
||||
|
||||
// TCCR4A: Timer/Counter4 Control Register A
|
||||
TCCR4A_COM4A = 0xc0 // Compare Output Mode 1A, bits
|
||||
TCCR4A_COM4B = 0x30 // Compare Output Mode 4B, bits
|
||||
TCCR4A_COM4C = 0xc // Compare Output Mode 4C, bits
|
||||
TCCR4A_WGM4 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TCCR4B: Timer/Counter4 Control Register B
|
||||
TCCR4B_ICNC4 = 0x80 // Input Capture 4 Noise Canceler
|
||||
TCCR4B_ICES4 = 0x40 // Input Capture 4 Edge Select
|
||||
TCCR4B_WGM4 = 0x18 // Waveform Generation Mode
|
||||
TCCR4B_CS4 = 0x7 // Prescaler source of Timer/Counter 4
|
||||
|
||||
// TCCR4C: Timer/Counter 4 Control Register C
|
||||
TCCR4C_FOC4A = 0x80 // Force Output Compare 4A
|
||||
TCCR4C_FOC4B = 0x40 // Force Output Compare 4B
|
||||
TCCR4C_FOC4C = 0x20 // Force Output Compare 4C
|
||||
|
||||
// TIMSK4: Timer/Counter4 Interrupt Mask Register
|
||||
TIMSK4_ICIE4 = 0x20 // Timer/Counter4 Input Capture Interrupt Enable
|
||||
TIMSK4_OCIE4C = 0x8 // Timer/Counter4 Output Compare C Match Interrupt Enable
|
||||
TIMSK4_OCIE4B = 0x4 // Timer/Counter4 Output Compare B Match Interrupt Enable
|
||||
TIMSK4_OCIE4A = 0x2 // Timer/Counter4 Output Compare A Match Interrupt Enable
|
||||
TIMSK4_TOIE4 = 0x1 // Timer/Counter4 Overflow Interrupt Enable
|
||||
|
||||
// TIFR4: Timer/Counter4 Interrupt Flag register
|
||||
TIFR4_ICF4 = 0x20 // Input Capture Flag 4
|
||||
TIFR4_OCF4C = 0x8 // Output Compare Flag 4C
|
||||
TIFR4_OCF4B = 0x4 // Output Compare Flag 4B
|
||||
TIFR4_OCF4A = 0x2 // Output Compare Flag 4A
|
||||
TIFR4_TOV4 = 0x1 // Timer/Counter4 Overflow Flag
|
||||
|
||||
// TCCR3A: Timer/Counter3 Control Register A
|
||||
TCCR3A_COM3A = 0xc0 // Compare Output Mode 1A, bits
|
||||
TCCR3A_COM3B = 0x30 // Compare Output Mode 3B, bits
|
||||
TCCR3A_COM3C = 0xc // Compare Output Mode 3C, bits
|
||||
TCCR3A_WGM3 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TCCR3B: Timer/Counter3 Control Register B
|
||||
TCCR3B_ICNC3 = 0x80 // Input Capture 3 Noise Canceler
|
||||
TCCR3B_ICES3 = 0x40 // Input Capture 3 Edge Select
|
||||
TCCR3B_WGM3 = 0x18 // Waveform Generation Mode
|
||||
TCCR3B_CS3 = 0x7 // Prescaler source of Timer/Counter 3
|
||||
|
||||
// TCCR3C: Timer/Counter 3 Control Register C
|
||||
TCCR3C_FOC3A = 0x80 // Force Output Compare 3A
|
||||
TCCR3C_FOC3B = 0x40 // Force Output Compare 3B
|
||||
TCCR3C_FOC3C = 0x20 // Force Output Compare 3C
|
||||
|
||||
// TIMSK3: Timer/Counter3 Interrupt Mask Register
|
||||
TIMSK3_ICIE3 = 0x20 // Timer/Counter3 Input Capture Interrupt Enable
|
||||
TIMSK3_OCIE3C = 0x8 // Timer/Counter3 Output Compare C Match Interrupt Enable
|
||||
TIMSK3_OCIE3B = 0x4 // Timer/Counter3 Output Compare B Match Interrupt Enable
|
||||
TIMSK3_OCIE3A = 0x2 // Timer/Counter3 Output Compare A Match Interrupt Enable
|
||||
TIMSK3_TOIE3 = 0x1 // Timer/Counter3 Overflow Interrupt Enable
|
||||
|
||||
// TIFR3: Timer/Counter3 Interrupt Flag register
|
||||
TIFR3_ICF3 = 0x20 // Input Capture Flag 3
|
||||
TIFR3_OCF3C = 0x8 // Output Compare Flag 3C
|
||||
TIFR3_OCF3B = 0x4 // Output Compare Flag 3B
|
||||
TIFR3_OCF3A = 0x2 // Output Compare Flag 3A
|
||||
TIFR3_TOV3 = 0x1 // Timer/Counter3 Overflow Flag
|
||||
|
||||
// TCCR1A: Timer/Counter1 Control Register A
|
||||
TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits
|
||||
TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits
|
||||
TCCR1A_COM1C = 0xc // Compare Output Mode 1C, bits
|
||||
TCCR1A_WGM1 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TCCR1B: Timer/Counter1 Control Register B
|
||||
TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler
|
||||
TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select
|
||||
TCCR1B_WGM1 = 0x18 // Waveform Generation Mode
|
||||
TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1
|
||||
|
||||
// TCCR1C: Timer/Counter 1 Control Register C
|
||||
TCCR1C_FOC1A = 0x80 // Force Output Compare 1A
|
||||
TCCR1C_FOC1B = 0x40 // Force Output Compare 1B
|
||||
TCCR1C_FOC1C = 0x20 // Force Output Compare 1C
|
||||
|
||||
// TIMSK1: Timer/Counter1 Interrupt Mask Register
|
||||
TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable
|
||||
TIMSK1_OCIE1C = 0x8 // Timer/Counter1 Output Compare C Match Interrupt Enable
|
||||
TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable
|
||||
TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable
|
||||
TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable
|
||||
|
||||
// TIFR1: Timer/Counter1 Interrupt Flag register
|
||||
TIFR1_ICF1 = 0x20 // Input Capture Flag 1
|
||||
TIFR1_OCF1C = 0x8 // Output Compare Flag 1C
|
||||
TIFR1_OCF1B = 0x4 // Output Compare Flag 1B
|
||||
TIFR1_OCF1A = 0x2 // Output Compare Flag 1A
|
||||
TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag
|
||||
)
|
||||
|
||||
// Bitfields for EEPROM: EEPROM
|
||||
const (
|
||||
// EECR: EEPROM Control Register
|
||||
EECR_EEPM = 0x30 // EEPROM Programming Mode Bits
|
||||
EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable
|
||||
EECR_EEMPE = 0x4 // EEPROM Master Write Enable
|
||||
EECR_EEPE = 0x2 // EEPROM Write Enable
|
||||
EECR_EERE = 0x1 // EEPROM Read Enable
|
||||
)
|
||||
|
||||
// Bitfields for EXINT: External Interrupts
|
||||
const (
|
||||
// EICRA: External Interrupt Control Register A
|
||||
EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit
|
||||
EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit
|
||||
EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit
|
||||
EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit
|
||||
|
||||
// EICRB: External Interrupt Control Register B
|
||||
EICRB_ISC7 = 0xc0 // External Interrupt 7-4 Sense Control Bit
|
||||
EICRB_ISC6 = 0x30 // External Interrupt 7-4 Sense Control Bit
|
||||
EICRB_ISC5 = 0xc // External Interrupt 7-4 Sense Control Bit
|
||||
EICRB_ISC4 = 0x3 // External Interrupt 7-4 Sense Control Bit
|
||||
|
||||
// EIMSK: External Interrupt Mask Register
|
||||
EIMSK_INT = 0xff // External Interrupt Request 7 Enable
|
||||
|
||||
// EIFR: External Interrupt Flag Register
|
||||
EIFR_INTF = 0xff // External Interrupt Flags
|
||||
|
||||
// PCMSK2: Pin Change Mask Register 2
|
||||
PCMSK2_PCINT = 0xff // Pin Change Enable mask
|
||||
|
||||
// PCMSK1: Pin Change Mask Register 1
|
||||
PCMSK1_PCINT = 0xff // Pin Change Enable mask
|
||||
|
||||
// PCMSK0: Pin Change Mask Register 0
|
||||
PCMSK0_PCINT = 0xff // Pin Change Enable mask
|
||||
|
||||
// PCIFR: Pin Change Interrupt Flag Register
|
||||
PCIFR_PCIF = 0x7 // Pin Change Interrupt Flags
|
||||
|
||||
// PCICR: Pin Change Interrupt Control Register
|
||||
PCICR_PCIE = 0x7 // Pin Change Interrupt Enables
|
||||
)
|
||||
|
||||
// Bitfields for ADC: Analog-to-Digital Converter
|
||||
const (
|
||||
// ADMUX: The ADC multiplexer Selection Register
|
||||
ADMUX_REFS = 0xc0 // Reference Selection Bits
|
||||
ADMUX_ADLAR = 0x20 // Left Adjust Result
|
||||
ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits
|
||||
|
||||
// ADCSRA: The ADC Control and Status register A
|
||||
ADCSRA_ADEN = 0x80 // ADC Enable
|
||||
ADCSRA_ADSC = 0x40 // ADC Start Conversion
|
||||
ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable
|
||||
ADCSRA_ADIF = 0x10 // ADC Interrupt Flag
|
||||
ADCSRA_ADIE = 0x8 // ADC Interrupt Enable
|
||||
ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits
|
||||
|
||||
// DIDR2: Digital Input Disable Register
|
||||
DIDR2_ADC15D = 0x80
|
||||
DIDR2_ADC14D = 0x40
|
||||
DIDR2_ADC13D = 0x20
|
||||
DIDR2_ADC12D = 0x10
|
||||
DIDR2_ADC11D = 0x8
|
||||
DIDR2_ADC10D = 0x4
|
||||
DIDR2_ADC9D = 0x2
|
||||
DIDR2_ADC8D = 0x1
|
||||
|
||||
// DIDR0: Digital Input Disable Register
|
||||
DIDR0_ADC7D = 0x80
|
||||
DIDR0_ADC6D = 0x40
|
||||
DIDR0_ADC5D = 0x20
|
||||
DIDR0_ADC4D = 0x10
|
||||
DIDR0_ADC3D = 0x8
|
||||
DIDR0_ADC2D = 0x4
|
||||
DIDR0_ADC1D = 0x2
|
||||
DIDR0_ADC0D = 0x1
|
||||
)
|
||||
|
||||
// Bitfields for BOOT_LOAD: Bootloader
|
||||
const (
|
||||
// SPMCSR: Store Program Memory Control Register
|
||||
SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable
|
||||
SPMCSR_RWWSB = 0x40 // Read While Write Section Busy
|
||||
SPMCSR_SIGRD = 0x20 // Signature Row Read
|
||||
SPMCSR_RWWSRE = 0x10 // Read While Write section read enable
|
||||
SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set
|
||||
SPMCSR_PGWRT = 0x4 // Page Write
|
||||
SPMCSR_PGERS = 0x2 // Page Erase
|
||||
SPMCSR_SPMEN = 0x1 // Store Program Memory Enable
|
||||
)
|
||||
|
||||
// Bitfields for CPU: CPU Registers
|
||||
const (
|
||||
// SREG: Status Register
|
||||
SREG_I = 0x80 // Global Interrupt Enable
|
||||
SREG_T = 0x40 // Bit Copy Storage
|
||||
SREG_H = 0x20 // Half Carry Flag
|
||||
SREG_S = 0x10 // Sign Bit
|
||||
SREG_V = 0x8 // Two's Complement Overflow Flag
|
||||
SREG_N = 0x4 // Negative Flag
|
||||
SREG_Z = 0x2 // Zero Flag
|
||||
SREG_C = 0x1 // Carry Flag
|
||||
|
||||
// XMCRA: External Memory Control Register A
|
||||
XMCRA_SRE = 0x80 // External SRAM Enable
|
||||
XMCRA_SRL = 0x70 // Wait state page limit
|
||||
XMCRA_SRW1 = 0xc // Wait state select bit upper page
|
||||
XMCRA_SRW0 = 0x3 // Wait state select bit lower page
|
||||
|
||||
// XMCRB: External Memory Control Register B
|
||||
XMCRB_XMBK = 0x80 // External Memory Bus Keeper Enable
|
||||
XMCRB_XMM = 0x7 // External Memory High Mask
|
||||
|
||||
// OSCCAL: Oscillator Calibration Value
|
||||
OSCCAL_OSCCAL = 0xff // Oscillator Calibration
|
||||
|
||||
// CLKPR
|
||||
CLKPR_CLKPCE = 0x80
|
||||
CLKPR_CLKPS = 0xf
|
||||
|
||||
// SMCR: Sleep Mode Control Register
|
||||
SMCR_SM = 0xe // Sleep Mode Select bits
|
||||
SMCR_SE = 0x1 // Sleep Enable
|
||||
|
||||
// GPIOR2: General Purpose IO Register 2
|
||||
GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis
|
||||
|
||||
// GPIOR1: General Purpose IO Register 1
|
||||
GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis
|
||||
|
||||
// GPIOR0: General Purpose IO Register 0
|
||||
GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7
|
||||
GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6
|
||||
GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5
|
||||
GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4
|
||||
GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3
|
||||
GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2
|
||||
GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1
|
||||
GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0
|
||||
|
||||
// PRR1: Power Reduction Register1
|
||||
PRR1_PRTIM5 = 0x20 // Power Reduction Timer/Counter5
|
||||
PRR1_PRTIM4 = 0x10 // Power Reduction Timer/Counter4
|
||||
PRR1_PRTIM3 = 0x8 // Power Reduction Timer/Counter3
|
||||
PRR1_PRUSART3 = 0x4 // Power Reduction USART3
|
||||
PRR1_PRUSART2 = 0x2 // Power Reduction USART2
|
||||
PRR1_PRUSART1 = 0x1 // Power Reduction USART1
|
||||
|
||||
// PRR0: Power Reduction Register0
|
||||
PRR0_PRTWI = 0x80 // Power Reduction TWI
|
||||
PRR0_PRTIM2 = 0x40 // Power Reduction Timer/Counter2
|
||||
PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0
|
||||
PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1
|
||||
PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface
|
||||
PRR0_PRUSART0 = 0x2 // Power Reduction USART0
|
||||
PRR0_PRADC = 0x1 // Power Reduction ADC
|
||||
)
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from ATmega1281.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x20000;
|
||||
__ram_size = 0x2000;
|
||||
__num_isrs = 57;
|
||||
|
|
@ -1,774 +0,0 @@
|
|||
// Automatically generated file. DO NOT EDIT.
|
||||
// Generated by gen-device.py from ATmega1284.atdf, see http://packs.download.atmel.com/
|
||||
|
||||
// +build avr,atmega1284
|
||||
|
||||
// Device information for the ATmega1284.
|
||||
//
|
||||
package avr
|
||||
|
||||
// Magic type name for the compiler.
|
||||
type __reg uint8
|
||||
|
||||
// Export this magic type name.
|
||||
type RegValue = __reg
|
||||
|
||||
// Some information about this device.
|
||||
const (
|
||||
DEVICE = "ATmega1284"
|
||||
ARCH = "AVR8"
|
||||
FAMILY = "megaAVR"
|
||||
)
|
||||
|
||||
// Interrupts
|
||||
const (
|
||||
IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet.
|
||||
IRQ_INT0 = 1 // External Interrupt Request 0
|
||||
IRQ_INT1 = 2 // External Interrupt Request 1
|
||||
IRQ_INT2 = 3 // External Interrupt Request 2
|
||||
IRQ_PCINT0 = 4 // Pin Change Interrupt Request 0
|
||||
IRQ_PCINT1 = 5 // Pin Change Interrupt Request 1
|
||||
IRQ_PCINT2 = 6 // Pin Change Interrupt Request 2
|
||||
IRQ_PCINT3 = 7 // Pin Change Interrupt Request 3
|
||||
IRQ_WDT = 8 // Watchdog Time-out Interrupt
|
||||
IRQ_TIMER2_COMPA = 9 // Timer/Counter2 Compare Match A
|
||||
IRQ_TIMER2_COMPB = 10 // Timer/Counter2 Compare Match B
|
||||
IRQ_TIMER2_OVF = 11 // Timer/Counter2 Overflow
|
||||
IRQ_TIMER1_CAPT = 12 // Timer/Counter1 Capture Event
|
||||
IRQ_TIMER1_COMPA = 13 // Timer/Counter1 Compare Match A
|
||||
IRQ_TIMER1_COMPB = 14 // Timer/Counter1 Compare Match B
|
||||
IRQ_TIMER1_OVF = 15 // Timer/Counter1 Overflow
|
||||
IRQ_TIMER0_COMPA = 16 // Timer/Counter0 Compare Match A
|
||||
IRQ_TIMER0_COMPB = 17 // Timer/Counter0 Compare Match B
|
||||
IRQ_TIMER0_OVF = 18 // Timer/Counter0 Overflow
|
||||
IRQ_SPI_STC = 19 // SPI Serial Transfer Complete
|
||||
IRQ_USART0_RX = 20 // USART0, Rx Complete
|
||||
IRQ_USART0_UDRE = 21 // USART0 Data register Empty
|
||||
IRQ_USART0_TX = 22 // USART0, Tx Complete
|
||||
IRQ_ANALOG_COMP = 23 // Analog Comparator
|
||||
IRQ_ADC = 24 // ADC Conversion Complete
|
||||
IRQ_EE_READY = 25 // EEPROM Ready
|
||||
IRQ_TWI = 26 // 2-wire Serial Interface
|
||||
IRQ_SPM_READY = 27 // Store Program Memory Read
|
||||
IRQ_USART1_RX = 28 // USART1 RX complete
|
||||
IRQ_USART1_UDRE = 29 // USART1 Data Register Empty
|
||||
IRQ_USART1_TX = 30 // USART1 TX complete
|
||||
IRQ_TIMER3_CAPT = 31 // Timer/Counter3 Capture Event
|
||||
IRQ_TIMER3_COMPA = 32 // Timer/Counter3 Compare Match A
|
||||
IRQ_TIMER3_COMPB = 33 // Timer/Counter3 Compare Match B
|
||||
IRQ_TIMER3_OVF = 34 // Timer/Counter3 Overflow
|
||||
IRQ_max = 34 // Highest interrupt number on this device.
|
||||
)
|
||||
|
||||
// Peripherals
|
||||
var (
|
||||
// Fuses
|
||||
FUSE = struct {
|
||||
EXTENDED __reg
|
||||
HIGH __reg
|
||||
LOW __reg
|
||||
}{
|
||||
EXTENDED: 0x2,
|
||||
HIGH: 0x1,
|
||||
LOW: 0x0,
|
||||
}
|
||||
|
||||
// Lockbits
|
||||
LOCKBIT = struct {
|
||||
LOCKBIT __reg
|
||||
}{
|
||||
LOCKBIT: 0x0,
|
||||
}
|
||||
|
||||
// Analog Comparator
|
||||
AC = struct {
|
||||
ACSR __reg
|
||||
DIDR1 __reg
|
||||
}{
|
||||
ACSR: 0x50, // Analog Comparator Control And Status Register
|
||||
DIDR1: 0x7f, // Digital Input Disable Register 1
|
||||
}
|
||||
|
||||
// USART
|
||||
USART = struct {
|
||||
UDR0 __reg
|
||||
UCSR0A __reg
|
||||
UCSR0B __reg
|
||||
UCSR0C __reg
|
||||
UBRR0L __reg
|
||||
UBRR0H __reg
|
||||
UDR1 __reg
|
||||
UCSR1A __reg
|
||||
UCSR1B __reg
|
||||
UCSR1C __reg
|
||||
UBRR1L __reg
|
||||
UBRR1H __reg
|
||||
}{
|
||||
UDR0: 0xc6, // USART I/O Data Register
|
||||
UCSR0A: 0xc0, // USART Control and Status Register A
|
||||
UCSR0B: 0xc1, // USART Control and Status Register B
|
||||
UCSR0C: 0xc2, // USART Control and Status Register C
|
||||
UBRR0L: 0xc4, // USART Baud Rate Register Bytes
|
||||
UBRR0H: 0xc4, // USART Baud Rate Register Bytes
|
||||
UDR1: 0xce, // USART I/O Data Register
|
||||
UCSR1A: 0xc8, // USART Control and Status Register A
|
||||
UCSR1B: 0xc9, // USART Control and Status Register B
|
||||
UCSR1C: 0xca, // USART Control and Status Register C
|
||||
UBRR1L: 0xcc, // USART Baud Rate Register Bytes
|
||||
UBRR1H: 0xcc, // USART Baud Rate Register Bytes
|
||||
}
|
||||
|
||||
// I/O Port
|
||||
PORT = struct {
|
||||
PORTA __reg
|
||||
DDRA __reg
|
||||
PINA __reg
|
||||
PORTB __reg
|
||||
DDRB __reg
|
||||
PINB __reg
|
||||
PORTC __reg
|
||||
DDRC __reg
|
||||
PINC __reg
|
||||
PORTD __reg
|
||||
DDRD __reg
|
||||
PIND __reg
|
||||
}{
|
||||
PORTA: 0x22, // Port A Data Register
|
||||
DDRA: 0x21, // Port A Data Direction Register
|
||||
PINA: 0x20, // Port A Input Pins
|
||||
PORTB: 0x25, // Port B Data Register
|
||||
DDRB: 0x24, // Port B Data Direction Register
|
||||
PINB: 0x23, // Port B Input Pins
|
||||
PORTC: 0x28, // Port C Data Register
|
||||
DDRC: 0x27, // Port C Data Direction Register
|
||||
PINC: 0x26, // Port C Input Pins
|
||||
PORTD: 0x2b, // Port D Data Register
|
||||
DDRD: 0x2a, // Port D Data Direction Register
|
||||
PIND: 0x29, // Port D Input Pins
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit
|
||||
TC8 = struct {
|
||||
OCR0B __reg
|
||||
OCR0A __reg
|
||||
TCNT0 __reg
|
||||
TCCR0B __reg
|
||||
TCCR0A __reg
|
||||
TIMSK0 __reg
|
||||
TIFR0 __reg
|
||||
}{
|
||||
OCR0B: 0x48, // Timer/Counter0 Output Compare Register
|
||||
OCR0A: 0x47, // Timer/Counter0 Output Compare Register
|
||||
TCNT0: 0x46, // Timer/Counter0
|
||||
TCCR0B: 0x45, // Timer/Counter Control Register B
|
||||
TCCR0A: 0x44, // Timer/Counter Control Register A
|
||||
TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register
|
||||
TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register
|
||||
}
|
||||
|
||||
// Timer/Counter, 16-bit
|
||||
TC16 = struct {
|
||||
TIMSK1 __reg
|
||||
TIFR1 __reg
|
||||
TCCR1A __reg
|
||||
TCCR1B __reg
|
||||
TCCR1C __reg
|
||||
TCNT1L __reg
|
||||
TCNT1H __reg
|
||||
OCR1AL __reg
|
||||
OCR1AH __reg
|
||||
OCR1BL __reg
|
||||
OCR1BH __reg
|
||||
ICR1L __reg
|
||||
ICR1H __reg
|
||||
TIMSK3 __reg
|
||||
TIFR3 __reg
|
||||
TCCR3A __reg
|
||||
TCCR3B __reg
|
||||
TCCR3C __reg
|
||||
TCNT3L __reg
|
||||
TCNT3H __reg
|
||||
OCR3AL __reg
|
||||
OCR3AH __reg
|
||||
OCR3BL __reg
|
||||
OCR3BH __reg
|
||||
ICR3L __reg
|
||||
ICR3H __reg
|
||||
}{
|
||||
TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register
|
||||
TIFR1: 0x36, // Timer/Counter Interrupt Flag register
|
||||
TCCR1A: 0x80, // Timer/Counter1 Control Register A
|
||||
TCCR1B: 0x81, // Timer/Counter1 Control Register B
|
||||
TCCR1C: 0x82, // Timer/Counter1 Control Register C
|
||||
TCNT1L: 0x84, // Timer/Counter1 Bytes
|
||||
TCNT1H: 0x84, // Timer/Counter1 Bytes
|
||||
OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes
|
||||
OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes
|
||||
OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes
|
||||
OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes
|
||||
ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
TIMSK3: 0x71, // Timer/Counter3 Interrupt Mask Register
|
||||
TIFR3: 0x38, // Timer/Counter Interrupt Flag register
|
||||
TCCR3A: 0x90, // Timer/Counter3 Control Register A
|
||||
TCCR3B: 0x91, // Timer/Counter3 Control Register B
|
||||
TCCR3C: 0x92, // Timer/Counter3 Control Register C
|
||||
TCNT3L: 0x94, // Timer/Counter3 Bytes
|
||||
TCNT3H: 0x94, // Timer/Counter3 Bytes
|
||||
OCR3AL: 0x98, // Timer/Counter3 Output Compare Register A Bytes
|
||||
OCR3AH: 0x98, // Timer/Counter3 Output Compare Register A Bytes
|
||||
OCR3BL: 0x9a, // Timer/Counter3 Output Compare Register B Bytes
|
||||
OCR3BH: 0x9a, // Timer/Counter3 Output Compare Register B Bytes
|
||||
ICR3L: 0x96, // Timer/Counter3 Input Capture Register Bytes
|
||||
ICR3H: 0x96, // Timer/Counter3 Input Capture Register Bytes
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit Async
|
||||
TC8_ASYNC = struct {
|
||||
TIMSK2 __reg
|
||||
TIFR2 __reg
|
||||
TCCR2A __reg
|
||||
TCCR2B __reg
|
||||
TCNT2 __reg
|
||||
OCR2B __reg
|
||||
OCR2A __reg
|
||||
ASSR __reg
|
||||
}{
|
||||
TIMSK2: 0x70, // Timer/Counter Interrupt Mask register
|
||||
TIFR2: 0x37, // Timer/Counter Interrupt Flag Register
|
||||
TCCR2A: 0xb0, // Timer/Counter2 Control Register A
|
||||
TCCR2B: 0xb1, // Timer/Counter2 Control Register B
|
||||
TCNT2: 0xb2, // Timer/Counter2
|
||||
OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B
|
||||
OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A
|
||||
ASSR: 0xb6, // Asynchronous Status Register
|
||||
}
|
||||
|
||||
// Bootloader
|
||||
BOOT_LOAD = struct {
|
||||
SPMCSR __reg
|
||||
}{
|
||||
SPMCSR: 0x57, // Store Program Memory Control Register
|
||||
}
|
||||
|
||||
// External Interrupts
|
||||
EXINT = struct {
|
||||
EICRA __reg
|
||||
EIMSK __reg
|
||||
EIFR __reg
|
||||
PCMSK3 __reg
|
||||
PCMSK2 __reg
|
||||
PCMSK1 __reg
|
||||
PCMSK0 __reg
|
||||
PCIFR __reg
|
||||
PCICR __reg
|
||||
}{
|
||||
EICRA: 0x69, // External Interrupt Control Register A
|
||||
EIMSK: 0x3d, // External Interrupt Mask Register
|
||||
EIFR: 0x3c, // External Interrupt Flag Register
|
||||
PCMSK3: 0x73, // Pin Change Mask Register 3
|
||||
PCMSK2: 0x6d, // Pin Change Mask Register 2
|
||||
PCMSK1: 0x6c, // Pin Change Mask Register 1
|
||||
PCMSK0: 0x6b, // Pin Change Mask Register 0
|
||||
PCIFR: 0x3b, // Pin Change Interrupt Flag Register
|
||||
PCICR: 0x68, // Pin Change Interrupt Control Register
|
||||
}
|
||||
|
||||
// Analog-to-Digital Converter
|
||||
ADC = struct {
|
||||
ADMUX __reg
|
||||
ADCL __reg
|
||||
ADCH __reg
|
||||
ADCSRA __reg
|
||||
DIDR0 __reg
|
||||
}{
|
||||
ADMUX: 0x7c, // The ADC multiplexer Selection Register
|
||||
ADCL: 0x78, // ADC Data Register Bytes
|
||||
ADCH: 0x78, // ADC Data Register Bytes
|
||||
ADCSRA: 0x7a, // The ADC Control and Status register A
|
||||
DIDR0: 0x7e, // Digital Input Disable Register
|
||||
}
|
||||
|
||||
// JTAG Interface
|
||||
JTAG = struct {
|
||||
OCDR __reg
|
||||
}{
|
||||
OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory
|
||||
}
|
||||
|
||||
// EEPROM
|
||||
EEPROM = struct {
|
||||
EEARL __reg
|
||||
EEARH __reg
|
||||
EEDR __reg
|
||||
EECR __reg
|
||||
}{
|
||||
EEARL: 0x41, // EEPROM Address Register Low Bytes
|
||||
EEARH: 0x41, // EEPROM Address Register Low Bytes
|
||||
EEDR: 0x40, // EEPROM Data Register
|
||||
EECR: 0x3f, // EEPROM Control Register
|
||||
}
|
||||
|
||||
// Two Wire Serial Interface
|
||||
TWI = struct {
|
||||
TWAMR __reg
|
||||
TWBR __reg
|
||||
TWCR __reg
|
||||
TWSR __reg
|
||||
TWDR __reg
|
||||
TWAR __reg
|
||||
}{
|
||||
TWAMR: 0xbd, // TWI (Slave) Address Mask Register
|
||||
TWBR: 0xb8, // TWI Bit Rate register
|
||||
TWCR: 0xbc, // TWI Control Register
|
||||
TWSR: 0xb9, // TWI Status Register
|
||||
TWDR: 0xbb, // TWI Data register
|
||||
TWAR: 0xba, // TWI (Slave) Address register
|
||||
}
|
||||
|
||||
// Serial Peripheral Interface
|
||||
SPI = struct {
|
||||
SPDR __reg
|
||||
SPSR __reg
|
||||
SPCR __reg
|
||||
}{
|
||||
SPDR: 0x4e, // SPI Data Register
|
||||
SPSR: 0x4d, // SPI Status Register
|
||||
SPCR: 0x4c, // SPI Control Register
|
||||
}
|
||||
|
||||
// Watchdog Timer
|
||||
WDT = struct {
|
||||
WDTCSR __reg
|
||||
}{
|
||||
WDTCSR: 0x60, // Watchdog Timer Control Register
|
||||
}
|
||||
|
||||
// CPU Registers
|
||||
CPU = struct {
|
||||
SREG __reg
|
||||
SPL __reg
|
||||
SPH __reg
|
||||
OSCCAL __reg
|
||||
CLKPR __reg
|
||||
SMCR __reg
|
||||
RAMPZ __reg
|
||||
GPIOR2 __reg
|
||||
GPIOR1 __reg
|
||||
GPIOR0 __reg
|
||||
PRR0 __reg
|
||||
PRR1 __reg
|
||||
}{
|
||||
SREG: 0x5f, // Status Register
|
||||
SPL: 0x5d, // Stack Pointer
|
||||
SPH: 0x5d, // Stack Pointer
|
||||
OSCCAL: 0x66, // Oscillator Calibration Value
|
||||
CLKPR: 0x61,
|
||||
SMCR: 0x53, // Sleep Mode Control Register
|
||||
RAMPZ: 0x5b, // RAM Page Z Select Register
|
||||
GPIOR2: 0x4b, // General Purpose IO Register 2
|
||||
GPIOR1: 0x4a, // General Purpose IO Register 1
|
||||
GPIOR0: 0x3e, // General Purpose IO Register 0
|
||||
PRR0: 0x64, // Power Reduction Register0
|
||||
PRR1: 0x65, // Power Reduction Register1
|
||||
}
|
||||
)
|
||||
|
||||
// Bitfields for FUSE: Fuses
|
||||
const (
|
||||
// EXTENDED
|
||||
EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level
|
||||
|
||||
// HIGH
|
||||
HIGH_OCDEN = 0x80 // On-Chip Debug Enabled
|
||||
HIGH_JTAGEN = 0x40 // JTAG Interface Enabled
|
||||
HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled
|
||||
HIGH_WDTON = 0x10 // Watchdog timer always on
|
||||
HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle
|
||||
HIGH_BOOTSZ = 0x6 // Select Boot Size
|
||||
HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled
|
||||
|
||||
// LOW
|
||||
LOW_CKDIV8 = 0x80 // Divide clock by 8 internally
|
||||
LOW_CKOUT = 0x40 // Clock output on PORTB1
|
||||
LOW_SUT_CKSEL = 0x3f // Select Clock Source
|
||||
)
|
||||
|
||||
// Bitfields for LOCKBIT: Lockbits
|
||||
const (
|
||||
// LOCKBIT
|
||||
LOCKBIT_LB = 0x3 // Memory Lock
|
||||
LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode
|
||||
LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode
|
||||
)
|
||||
|
||||
// Bitfields for AC: Analog Comparator
|
||||
const (
|
||||
// ACSR: Analog Comparator Control And Status Register
|
||||
ACSR_ACD = 0x80 // Analog Comparator Disable
|
||||
ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select
|
||||
ACSR_ACO = 0x20 // Analog Compare Output
|
||||
ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag
|
||||
ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable
|
||||
ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable
|
||||
ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits
|
||||
|
||||
// DIDR1: Digital Input Disable Register 1
|
||||
DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable
|
||||
DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable
|
||||
)
|
||||
|
||||
// Bitfields for USART: USART
|
||||
const (
|
||||
// UCSR0A: USART Control and Status Register A
|
||||
UCSR0A_RXC0 = 0x80 // USART Receive Complete
|
||||
UCSR0A_TXC0 = 0x40 // USART Transmitt Complete
|
||||
UCSR0A_UDRE0 = 0x20 // USART Data Register Empty
|
||||
UCSR0A_FE0 = 0x10 // Framing Error
|
||||
UCSR0A_DOR0 = 0x8 // Data overRun
|
||||
UCSR0A_UPE0 = 0x4 // Parity Error
|
||||
UCSR0A_U2X0 = 0x2 // Double the USART transmission speed
|
||||
UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode
|
||||
|
||||
// UCSR0B: USART Control and Status Register B
|
||||
UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable
|
||||
UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable
|
||||
UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable
|
||||
UCSR0B_RXEN0 = 0x10 // Receiver Enable
|
||||
UCSR0B_TXEN0 = 0x8 // Transmitter Enable
|
||||
UCSR0B_UCSZ02 = 0x4 // Character Size
|
||||
UCSR0B_RXB80 = 0x2 // Receive Data Bit 8
|
||||
UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8
|
||||
|
||||
// UCSR0C: USART Control and Status Register C
|
||||
UCSR0C_UMSEL0 = 0xc0 // USART Mode Select
|
||||
UCSR0C_UPM0 = 0x30 // Parity Mode Bits
|
||||
UCSR0C_USBS0 = 0x8 // Stop Bit Select
|
||||
UCSR0C_UCSZ0 = 0x6 // Character Size
|
||||
UCSR0C_UCPOL0 = 0x1 // Clock Polarity
|
||||
|
||||
// UCSR1A: USART Control and Status Register A
|
||||
UCSR1A_RXC1 = 0x80 // USART Receive Complete
|
||||
UCSR1A_TXC1 = 0x40 // USART Transmitt Complete
|
||||
UCSR1A_UDRE1 = 0x20 // USART Data Register Empty
|
||||
UCSR1A_FE1 = 0x10 // Framing Error
|
||||
UCSR1A_DOR1 = 0x8 // Data overRun
|
||||
UCSR1A_UPE1 = 0x4 // Parity Error
|
||||
UCSR1A_U2X1 = 0x2 // Double the USART transmission speed
|
||||
UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode
|
||||
|
||||
// UCSR1B: USART Control and Status Register B
|
||||
UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable
|
||||
UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable
|
||||
UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable
|
||||
UCSR1B_RXEN1 = 0x10 // Receiver Enable
|
||||
UCSR1B_TXEN1 = 0x8 // Transmitter Enable
|
||||
UCSR1B_UCSZ12 = 0x4 // Character Size
|
||||
UCSR1B_RXB81 = 0x2 // Receive Data Bit 8
|
||||
UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8
|
||||
|
||||
// UCSR1C: USART Control and Status Register C
|
||||
UCSR1C_UMSEL1 = 0xc0 // USART Mode Select
|
||||
UCSR1C_UPM1 = 0x30 // Parity Mode Bits
|
||||
UCSR1C_USBS1 = 0x8 // Stop Bit Select
|
||||
UCSR1C_UCSZ1 = 0x6 // Character Size
|
||||
UCSR1C_UCPOL1 = 0x1 // Clock Polarity
|
||||
)
|
||||
|
||||
// Bitfields for TC8: Timer/Counter, 8-bit
|
||||
const (
|
||||
// TCCR0B: Timer/Counter Control Register B
|
||||
TCCR0B_FOC0A = 0x80 // Force Output Compare A
|
||||
TCCR0B_FOC0B = 0x40 // Force Output Compare B
|
||||
TCCR0B_WGM02 = 0x8
|
||||
TCCR0B_CS0 = 0x7 // Clock Select
|
||||
|
||||
// TCCR0A: Timer/Counter Control Register A
|
||||
TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode
|
||||
TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm
|
||||
TCCR0A_WGM0 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TIMSK0: Timer/Counter0 Interrupt Mask Register
|
||||
TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable
|
||||
TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable
|
||||
TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable
|
||||
|
||||
// TIFR0: Timer/Counter0 Interrupt Flag register
|
||||
TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B
|
||||
TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A
|
||||
TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag
|
||||
)
|
||||
|
||||
// Bitfields for TC16: Timer/Counter, 16-bit
|
||||
const (
|
||||
// TIMSK1: Timer/Counter1 Interrupt Mask Register
|
||||
TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable
|
||||
TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable
|
||||
TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable
|
||||
TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable
|
||||
|
||||
// TIFR1: Timer/Counter Interrupt Flag register
|
||||
TIFR1_ICF1 = 0x20 // Timer/Counter1 Input Capture Flag
|
||||
TIFR1_OCF1B = 0x4 // Timer/Counter1 Output Compare B Match Flag
|
||||
TIFR1_OCF1A = 0x2 // Timer/Counter1 Output Compare A Match Flag
|
||||
TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag
|
||||
|
||||
// TCCR1A: Timer/Counter1 Control Register A
|
||||
TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits
|
||||
TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits
|
||||
TCCR1A_WGM1 = 0x3 // Pulse Width Modulator Select Bits
|
||||
|
||||
// TCCR1B: Timer/Counter1 Control Register B
|
||||
TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler
|
||||
TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select
|
||||
TCCR1B_WGM1 = 0x18 // Waveform Generation Mode Bits
|
||||
TCCR1B_CS1 = 0x7 // Clock Select1 bits
|
||||
|
||||
// TCCR1C: Timer/Counter1 Control Register C
|
||||
TCCR1C_FOC1A = 0x80 // Force Output Compare for Channel A
|
||||
TCCR1C_FOC1B = 0x40 // Force Output Compare for Channel B
|
||||
|
||||
// TIMSK3: Timer/Counter3 Interrupt Mask Register
|
||||
TIMSK3_ICIE3 = 0x20 // Timer/Counter3 Input Capture Interrupt Enable
|
||||
TIMSK3_OCIE3B = 0x4 // Timer/Counter3 Output Compare B Match Interrupt Enable
|
||||
TIMSK3_OCIE3A = 0x2 // Timer/Counter3 Output Compare A Match Interrupt Enable
|
||||
TIMSK3_TOIE3 = 0x1 // Timer/Counter3 Overflow Interrupt Enable
|
||||
|
||||
// TIFR3: Timer/Counter Interrupt Flag register
|
||||
TIFR3_ICF3 = 0x20 // Timer/Counter3 Input Capture Flag
|
||||
TIFR3_OCF3B = 0x4 // Timer/Counter3 Output Compare B Match Flag
|
||||
TIFR3_OCF3A = 0x2 // Timer/Counter3 Output Compare A Match Flag
|
||||
TIFR3_TOV3 = 0x1 // Timer/Counter3 Overflow Flag
|
||||
|
||||
// TCCR3A: Timer/Counter3 Control Register A
|
||||
TCCR3A_COM3A = 0xc0 // Compare Output Mode 3A, bits
|
||||
TCCR3A_COM3B = 0x30 // Compare Output Mode 3B, bits
|
||||
TCCR3A_WGM3 = 0x3 // Pulse Width Modulator Select Bits
|
||||
|
||||
// TCCR3B: Timer/Counter3 Control Register B
|
||||
TCCR3B_ICNC3 = 0x80 // Input Capture 3 Noise Canceler
|
||||
TCCR3B_ICES3 = 0x40 // Input Capture 3 Edge Select
|
||||
TCCR3B_WGM3 = 0x18 // Waveform Generation Mode Bits
|
||||
TCCR3B_CS3 = 0x7 // Clock Select3 bits
|
||||
|
||||
// TCCR3C: Timer/Counter3 Control Register C
|
||||
TCCR3C_FOC3A = 0x80 // Force Output Compare for Channel A
|
||||
TCCR3C_FOC3B = 0x40 // Force Output Compare for Channel B
|
||||
)
|
||||
|
||||
// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async
|
||||
const (
|
||||
// TIMSK2: Timer/Counter Interrupt Mask register
|
||||
TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable
|
||||
TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable
|
||||
TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable
|
||||
|
||||
// TIFR2: Timer/Counter Interrupt Flag Register
|
||||
TIFR2_OCF2B = 0x4 // Output Compare Flag 2B
|
||||
TIFR2_OCF2A = 0x2 // Output Compare Flag 2A
|
||||
TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag
|
||||
|
||||
// TCCR2A: Timer/Counter2 Control Register A
|
||||
TCCR2A_COM2A = 0xc0 // Compare Output Mode bits
|
||||
TCCR2A_COM2B = 0x30 // Compare Output Mode bits
|
||||
TCCR2A_WGM2 = 0x3 // Waveform Genration Mode
|
||||
|
||||
// TCCR2B: Timer/Counter2 Control Register B
|
||||
TCCR2B_FOC2A = 0x80 // Force Output Compare A
|
||||
TCCR2B_FOC2B = 0x40 // Force Output Compare B
|
||||
TCCR2B_WGM22 = 0x8 // Waveform Generation Mode
|
||||
TCCR2B_CS2 = 0x7 // Clock Select bits
|
||||
|
||||
// ASSR: Asynchronous Status Register
|
||||
ASSR_EXCLK = 0x40 // Enable External Clock Input
|
||||
ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2
|
||||
ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy
|
||||
ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy
|
||||
ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy
|
||||
ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy
|
||||
ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy
|
||||
)
|
||||
|
||||
// Bitfields for BOOT_LOAD: Bootloader
|
||||
const (
|
||||
// SPMCSR: Store Program Memory Control Register
|
||||
SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable
|
||||
SPMCSR_RWWSB = 0x40 // Read While Write Section Busy
|
||||
SPMCSR_SIGRD = 0x20 // Signature Row Read
|
||||
SPMCSR_RWWSRE = 0x10 // Read While Write section read enable
|
||||
SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set
|
||||
SPMCSR_PGWRT = 0x4 // Page Write
|
||||
SPMCSR_PGERS = 0x2 // Page Erase
|
||||
SPMCSR_SPMEN = 0x1 // Store Program Memory Enable
|
||||
)
|
||||
|
||||
// Bitfields for EXINT: External Interrupts
|
||||
const (
|
||||
// EICRA: External Interrupt Control Register A
|
||||
EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit
|
||||
EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit
|
||||
EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit
|
||||
|
||||
// EIMSK: External Interrupt Mask Register
|
||||
EIMSK_INT = 0x7 // External Interrupt Request 2 Enable
|
||||
|
||||
// EIFR: External Interrupt Flag Register
|
||||
EIFR_INTF = 0x7 // External Interrupt Flags
|
||||
|
||||
// PCMSK3: Pin Change Mask Register 3
|
||||
PCMSK3_PCINT = 0xff // Pin Change Enable Masks
|
||||
|
||||
// PCMSK2: Pin Change Mask Register 2
|
||||
PCMSK2_PCINT = 0xff // Pin Change Enable Masks
|
||||
|
||||
// PCMSK1: Pin Change Mask Register 1
|
||||
PCMSK1_PCINT = 0xff // Pin Change Enable Masks
|
||||
|
||||
// PCMSK0: Pin Change Mask Register 0
|
||||
PCMSK0_PCINT = 0xff // Pin Change Enable Masks
|
||||
|
||||
// PCIFR: Pin Change Interrupt Flag Register
|
||||
PCIFR_PCIF = 0xf // Pin Change Interrupt Flags
|
||||
|
||||
// PCICR: Pin Change Interrupt Control Register
|
||||
PCICR_PCIE = 0xf // Pin Change Interrupt Enables
|
||||
)
|
||||
|
||||
// Bitfields for ADC: Analog-to-Digital Converter
|
||||
const (
|
||||
// ADMUX: The ADC multiplexer Selection Register
|
||||
ADMUX_REFS = 0xc0 // Reference Selection Bits
|
||||
ADMUX_ADLAR = 0x20 // Left Adjust Result
|
||||
ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits
|
||||
|
||||
// ADCSRA: The ADC Control and Status register A
|
||||
ADCSRA_ADEN = 0x80 // ADC Enable
|
||||
ADCSRA_ADSC = 0x40 // ADC Start Conversion
|
||||
ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable
|
||||
ADCSRA_ADIF = 0x10 // ADC Interrupt Flag
|
||||
ADCSRA_ADIE = 0x8 // ADC Interrupt Enable
|
||||
ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits
|
||||
|
||||
// DIDR0: Digital Input Disable Register
|
||||
DIDR0_ADC7D = 0x80
|
||||
DIDR0_ADC6D = 0x40
|
||||
DIDR0_ADC5D = 0x20
|
||||
DIDR0_ADC4D = 0x10
|
||||
DIDR0_ADC3D = 0x8
|
||||
DIDR0_ADC2D = 0x4
|
||||
DIDR0_ADC1D = 0x2
|
||||
DIDR0_ADC0D = 0x1
|
||||
)
|
||||
|
||||
// Bitfields for EEPROM: EEPROM
|
||||
const (
|
||||
// EECR: EEPROM Control Register
|
||||
EECR_EEPM = 0x30 // EEPROM Programming Mode Bits
|
||||
EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable
|
||||
EECR_EEMPE = 0x4 // EEPROM Master Write Enable
|
||||
EECR_EEPE = 0x2 // EEPROM Write Enable
|
||||
EECR_EERE = 0x1 // EEPROM Read Enable
|
||||
)
|
||||
|
||||
// Bitfields for TWI: Two Wire Serial Interface
|
||||
const (
|
||||
// TWAMR: TWI (Slave) Address Mask Register
|
||||
TWAMR_TWAM = 0xfe
|
||||
|
||||
// TWCR: TWI Control Register
|
||||
TWCR_TWINT = 0x80 // TWI Interrupt Flag
|
||||
TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit
|
||||
TWCR_TWSTA = 0x20 // TWI Start Condition Bit
|
||||
TWCR_TWSTO = 0x10 // TWI Stop Condition Bit
|
||||
TWCR_TWWC = 0x8 // TWI Write Collition Flag
|
||||
TWCR_TWEN = 0x4 // TWI Enable Bit
|
||||
TWCR_TWIE = 0x1 // TWI Interrupt Enable
|
||||
|
||||
// TWSR: TWI Status Register
|
||||
TWSR_TWS = 0xf8 // TWI Status
|
||||
TWSR_TWPS = 0x3 // TWI Prescaler
|
||||
|
||||
// TWAR: TWI (Slave) Address register
|
||||
TWAR_TWA = 0xfe // TWI (Slave) Address register Bits
|
||||
TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit
|
||||
)
|
||||
|
||||
// Bitfields for SPI: Serial Peripheral Interface
|
||||
const (
|
||||
// SPSR: SPI Status Register
|
||||
SPSR_SPIF = 0x80 // SPI Interrupt Flag
|
||||
SPSR_WCOL = 0x40 // Write Collision Flag
|
||||
SPSR_SPI2X = 0x1 // Double SPI Speed Bit
|
||||
|
||||
// SPCR: SPI Control Register
|
||||
SPCR_SPIE = 0x80 // SPI Interrupt Enable
|
||||
SPCR_SPE = 0x40 // SPI Enable
|
||||
SPCR_DORD = 0x20 // Data Order
|
||||
SPCR_MSTR = 0x10 // Master/Slave Select
|
||||
SPCR_CPOL = 0x8 // Clock polarity
|
||||
SPCR_CPHA = 0x4 // Clock Phase
|
||||
SPCR_SPR = 0x3 // SPI Clock Rate Selects
|
||||
)
|
||||
|
||||
// Bitfields for WDT: Watchdog Timer
|
||||
const (
|
||||
// WDTCSR: Watchdog Timer Control Register
|
||||
WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag
|
||||
WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable
|
||||
WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits
|
||||
WDTCSR_WDCE = 0x10 // Watchdog Change Enable
|
||||
WDTCSR_WDE = 0x8 // Watch Dog Enable
|
||||
)
|
||||
|
||||
// Bitfields for CPU: CPU Registers
|
||||
const (
|
||||
// SREG: Status Register
|
||||
SREG_I = 0x80 // Global Interrupt Enable
|
||||
SREG_T = 0x40 // Bit Copy Storage
|
||||
SREG_H = 0x20 // Half Carry Flag
|
||||
SREG_S = 0x10 // Sign Bit
|
||||
SREG_V = 0x8 // Two's Complement Overflow Flag
|
||||
SREG_N = 0x4 // Negative Flag
|
||||
SREG_Z = 0x2 // Zero Flag
|
||||
SREG_C = 0x1 // Carry Flag
|
||||
|
||||
// OSCCAL: Oscillator Calibration Value
|
||||
OSCCAL_OSCCAL = 0xff // Oscillator Calibration
|
||||
|
||||
// CLKPR
|
||||
CLKPR_CLKPCE = 0x80
|
||||
CLKPR_CLKPS = 0xf
|
||||
|
||||
// SMCR: Sleep Mode Control Register
|
||||
SMCR_SM = 0xe // Sleep Mode Select bits
|
||||
SMCR_SE = 0x1 // Sleep Enable
|
||||
|
||||
// GPIOR2: General Purpose IO Register 2
|
||||
GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis
|
||||
|
||||
// GPIOR1: General Purpose IO Register 1
|
||||
GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis
|
||||
|
||||
// GPIOR0: General Purpose IO Register 0
|
||||
GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7
|
||||
GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6
|
||||
GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5
|
||||
GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4
|
||||
GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3
|
||||
GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2
|
||||
GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1
|
||||
GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0
|
||||
|
||||
// PRR0: Power Reduction Register0
|
||||
PRR0_PRTWI = 0x80 // Power Reduction TWI
|
||||
PRR0_PRTIM2 = 0x40 // Power Reduction Timer/Counter2
|
||||
PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0
|
||||
PRR0_PRUSART1 = 0x10 // Power Reduction USART1
|
||||
PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1
|
||||
PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface
|
||||
PRR0_PRUSART0 = 0x2 // Power Reduction USART0
|
||||
PRR0_PRADC = 0x1 // Power Reduction ADC
|
||||
|
||||
// PRR1: Power Reduction Register1
|
||||
PRR1_PRTIM3 = 0x1 // Power Reduction Timer/Counter3
|
||||
)
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from ATmega1284.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x20000;
|
||||
__ram_size = 0x4000;
|
||||
__num_isrs = 35;
|
||||
|
|
@ -1,870 +0,0 @@
|
|||
// Automatically generated file. DO NOT EDIT.
|
||||
// Generated by gen-device.py from ATmega1284P.atdf, see http://packs.download.atmel.com/
|
||||
|
||||
// +build avr,atmega1284p
|
||||
|
||||
// Device information for the ATmega1284P.
|
||||
//
|
||||
package avr
|
||||
|
||||
// Magic type name for the compiler.
|
||||
type __reg uint8
|
||||
|
||||
// Export this magic type name.
|
||||
type RegValue = __reg
|
||||
|
||||
// Some information about this device.
|
||||
const (
|
||||
DEVICE = "ATmega1284P"
|
||||
ARCH = "AVR8"
|
||||
FAMILY = "megaAVR"
|
||||
)
|
||||
|
||||
// Interrupts
|
||||
const (
|
||||
IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet.
|
||||
IRQ_INT0 = 1 // External Interrupt Request 0
|
||||
IRQ_INT1 = 2 // External Interrupt Request 1
|
||||
IRQ_INT2 = 3 // External Interrupt Request 2
|
||||
IRQ_PCINT0 = 4 // Pin Change Interrupt Request 0
|
||||
IRQ_PCINT1 = 5 // Pin Change Interrupt Request 1
|
||||
IRQ_PCINT2 = 6 // Pin Change Interrupt Request 2
|
||||
IRQ_PCINT3 = 7 // Pin Change Interrupt Request 3
|
||||
IRQ_WDT = 8 // Watchdog Time-out Interrupt
|
||||
IRQ_TIMER2_COMPA = 9 // Timer/Counter2 Compare Match A
|
||||
IRQ_TIMER2_COMPB = 10 // Timer/Counter2 Compare Match B
|
||||
IRQ_TIMER2_OVF = 11 // Timer/Counter2 Overflow
|
||||
IRQ_TIMER1_CAPT = 12 // Timer/Counter1 Capture Event
|
||||
IRQ_TIMER1_COMPA = 13 // Timer/Counter1 Compare Match A
|
||||
IRQ_TIMER1_COMPB = 14 // Timer/Counter1 Compare Match B
|
||||
IRQ_TIMER1_OVF = 15 // Timer/Counter1 Overflow
|
||||
IRQ_TIMER0_COMPA = 16 // Timer/Counter0 Compare Match A
|
||||
IRQ_TIMER0_COMPB = 17 // Timer/Counter0 Compare Match B
|
||||
IRQ_TIMER0_OVF = 18 // Timer/Counter0 Overflow
|
||||
IRQ_SPI_STC = 19 // SPI Serial Transfer Complete
|
||||
IRQ_USART0_RX = 20 // USART0, Rx Complete
|
||||
IRQ_USART0_UDRE = 21 // USART0 Data register Empty
|
||||
IRQ_USART0_TX = 22 // USART0, Tx Complete
|
||||
IRQ_ANALOG_COMP = 23 // Analog Comparator
|
||||
IRQ_ADC = 24 // ADC Conversion Complete
|
||||
IRQ_EE_READY = 25 // EEPROM Ready
|
||||
IRQ_TWI = 26 // 2-wire Serial Interface
|
||||
IRQ_SPM_READY = 27 // Store Program Memory Read
|
||||
IRQ_USART1_RX = 28 // USART1 RX complete
|
||||
IRQ_USART1_UDRE = 29 // USART1 Data Register Empty
|
||||
IRQ_USART1_TX = 30 // USART1 TX complete
|
||||
IRQ_TIMER3_CAPT = 31 // Timer/Counter3 Capture Event
|
||||
IRQ_TIMER3_COMPA = 32 // Timer/Counter3 Compare Match A
|
||||
IRQ_TIMER3_COMPB = 33 // Timer/Counter3 Compare Match B
|
||||
IRQ_TIMER3_OVF = 34 // Timer/Counter3 Overflow
|
||||
IRQ_max = 34 // Highest interrupt number on this device.
|
||||
)
|
||||
|
||||
// Peripherals
|
||||
var (
|
||||
// Fuses
|
||||
FUSE = struct {
|
||||
EXTENDED __reg
|
||||
HIGH __reg
|
||||
LOW __reg
|
||||
}{
|
||||
EXTENDED: 0x2,
|
||||
HIGH: 0x1,
|
||||
LOW: 0x0,
|
||||
}
|
||||
|
||||
// Lockbits
|
||||
LOCKBIT = struct {
|
||||
LOCKBIT __reg
|
||||
}{
|
||||
LOCKBIT: 0x0,
|
||||
}
|
||||
|
||||
// Analog Comparator
|
||||
AC = struct {
|
||||
ACSR __reg
|
||||
DIDR1 __reg
|
||||
}{
|
||||
ACSR: 0x50, // Analog Comparator Control And Status Register
|
||||
DIDR1: 0x7f, // Digital Input Disable Register 1
|
||||
}
|
||||
|
||||
// USART
|
||||
USART = struct {
|
||||
UDR0 __reg
|
||||
UCSR0A __reg
|
||||
UCSR0B __reg
|
||||
UCSR0C __reg
|
||||
UBRR0L __reg
|
||||
UBRR0H __reg
|
||||
UDR1 __reg
|
||||
UCSR1A __reg
|
||||
UCSR1B __reg
|
||||
UCSR1C __reg
|
||||
UBRR1L __reg
|
||||
UBRR1H __reg
|
||||
}{
|
||||
UDR0: 0xc6, // USART I/O Data Register
|
||||
UCSR0A: 0xc0, // USART Control and Status Register A
|
||||
UCSR0B: 0xc1, // USART Control and Status Register B
|
||||
UCSR0C: 0xc2, // USART Control and Status Register C
|
||||
UBRR0L: 0xc4, // USART Baud Rate Register Bytes
|
||||
UBRR0H: 0xc4, // USART Baud Rate Register Bytes
|
||||
UDR1: 0xce, // USART I/O Data Register
|
||||
UCSR1A: 0xc8, // USART Control and Status Register A
|
||||
UCSR1B: 0xc9, // USART Control and Status Register B
|
||||
UCSR1C: 0xca, // USART Control and Status Register C
|
||||
UBRR1L: 0xcc, // USART Baud Rate Register Bytes
|
||||
UBRR1H: 0xcc, // USART Baud Rate Register Bytes
|
||||
}
|
||||
|
||||
// I/O Port
|
||||
PORT = struct {
|
||||
PORTA __reg
|
||||
DDRA __reg
|
||||
PINA __reg
|
||||
PORTB __reg
|
||||
DDRB __reg
|
||||
PINB __reg
|
||||
PORTC __reg
|
||||
DDRC __reg
|
||||
PINC __reg
|
||||
PORTD __reg
|
||||
DDRD __reg
|
||||
PIND __reg
|
||||
}{
|
||||
PORTA: 0x22, // Port A Data Register
|
||||
DDRA: 0x21, // Port A Data Direction Register
|
||||
PINA: 0x20, // Port A Input Pins
|
||||
PORTB: 0x25, // Port B Data Register
|
||||
DDRB: 0x24, // Port B Data Direction Register
|
||||
PINB: 0x23, // Port B Input Pins
|
||||
PORTC: 0x28, // Port C Data Register
|
||||
DDRC: 0x27, // Port C Data Direction Register
|
||||
PINC: 0x26, // Port C Input Pins
|
||||
PORTD: 0x2b, // Port D Data Register
|
||||
DDRD: 0x2a, // Port D Data Direction Register
|
||||
PIND: 0x29, // Port D Input Pins
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit
|
||||
TC8 = struct {
|
||||
OCR0B __reg
|
||||
OCR0A __reg
|
||||
TCNT0 __reg
|
||||
TCCR0B __reg
|
||||
TCCR0A __reg
|
||||
TIMSK0 __reg
|
||||
TIFR0 __reg
|
||||
}{
|
||||
OCR0B: 0x48, // Timer/Counter0 Output Compare Register B
|
||||
OCR0A: 0x47, // Timer/Counter0 Output Compare Register A
|
||||
TCNT0: 0x46, // Timer/Counter0
|
||||
TCCR0B: 0x45, // Timer/Counter Control Register B
|
||||
TCCR0A: 0x44, // Timer/Counter Control Register A
|
||||
TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register
|
||||
TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register
|
||||
}
|
||||
|
||||
// Timer/Counter, 16-bit
|
||||
TC16 = struct {
|
||||
TIMSK1 __reg
|
||||
TIFR1 __reg
|
||||
TCCR1A __reg
|
||||
TCCR1B __reg
|
||||
TCCR1C __reg
|
||||
TCNT1L __reg
|
||||
TCNT1H __reg
|
||||
OCR1AL __reg
|
||||
OCR1AH __reg
|
||||
OCR1BL __reg
|
||||
OCR1BH __reg
|
||||
ICR1L __reg
|
||||
ICR1H __reg
|
||||
TIMSK3 __reg
|
||||
TIFR3 __reg
|
||||
TCCR3A __reg
|
||||
TCCR3B __reg
|
||||
TCCR3C __reg
|
||||
TCNT3L __reg
|
||||
TCNT3H __reg
|
||||
OCR3AL __reg
|
||||
OCR3AH __reg
|
||||
OCR3BL __reg
|
||||
OCR3BH __reg
|
||||
ICR3L __reg
|
||||
ICR3H __reg
|
||||
}{
|
||||
TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register
|
||||
TIFR1: 0x36, // Timer/Counter Interrupt Flag register
|
||||
TCCR1A: 0x80, // Timer/Counter1 Control Register A
|
||||
TCCR1B: 0x81, // Timer/Counter1 Control Register B
|
||||
TCCR1C: 0x82, // Timer/Counter1 Control Register C
|
||||
TCNT1L: 0x84, // Timer/Counter1 Bytes
|
||||
TCNT1H: 0x84, // Timer/Counter1 Bytes
|
||||
OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes
|
||||
OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes
|
||||
OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes
|
||||
OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes
|
||||
ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
TIMSK3: 0x71, // Timer/Counter3 Interrupt Mask Register
|
||||
TIFR3: 0x38, // Timer/Counter Interrupt Flag register
|
||||
TCCR3A: 0x90, // Timer/Counter3 Control Register A
|
||||
TCCR3B: 0x91, // Timer/Counter3 Control Register B
|
||||
TCCR3C: 0x92, // Timer/Counter3 Control Register C
|
||||
TCNT3L: 0x94, // Timer/Counter3 Bytes
|
||||
TCNT3H: 0x94, // Timer/Counter3 Bytes
|
||||
OCR3AL: 0x98, // Timer/Counter3 Output Compare Register A Bytes
|
||||
OCR3AH: 0x98, // Timer/Counter3 Output Compare Register A Bytes
|
||||
OCR3BL: 0x9a, // Timer/Counter3 Output Compare Register B Bytes
|
||||
OCR3BH: 0x9a, // Timer/Counter3 Output Compare Register B Bytes
|
||||
ICR3L: 0x96, // Timer/Counter3 Input Capture Register Bytes
|
||||
ICR3H: 0x96, // Timer/Counter3 Input Capture Register Bytes
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit Async
|
||||
TC8_ASYNC = struct {
|
||||
TIMSK2 __reg
|
||||
TIFR2 __reg
|
||||
TCCR2A __reg
|
||||
TCCR2B __reg
|
||||
TCNT2 __reg
|
||||
OCR2B __reg
|
||||
OCR2A __reg
|
||||
ASSR __reg
|
||||
}{
|
||||
TIMSK2: 0x70, // Timer/Counter Interrupt Mask register
|
||||
TIFR2: 0x37, // Timer/Counter Interrupt Flag Register
|
||||
TCCR2A: 0xb0, // Timer/Counter2 Control Register A
|
||||
TCCR2B: 0xb1, // Timer/Counter2 Control Register B
|
||||
TCNT2: 0xb2, // Timer/Counter2
|
||||
OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B
|
||||
OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A
|
||||
ASSR: 0xb6, // Asynchronous Status Register
|
||||
}
|
||||
|
||||
// Bootloader
|
||||
BOOT_LOAD = struct {
|
||||
SPMCSR __reg
|
||||
}{
|
||||
SPMCSR: 0x57, // Store Program Memory Control Register
|
||||
}
|
||||
|
||||
// External Interrupts
|
||||
EXINT = struct {
|
||||
EICRA __reg
|
||||
EIMSK __reg
|
||||
EIFR __reg
|
||||
PCMSK3 __reg
|
||||
PCMSK2 __reg
|
||||
PCMSK1 __reg
|
||||
PCMSK0 __reg
|
||||
PCIFR __reg
|
||||
PCICR __reg
|
||||
}{
|
||||
EICRA: 0x69, // External Interrupt Control Register A
|
||||
EIMSK: 0x3d, // External Interrupt Mask Register
|
||||
EIFR: 0x3c, // External Interrupt Flag Register
|
||||
PCMSK3: 0x73, // Pin Change Mask Register 3
|
||||
PCMSK2: 0x6d, // Pin Change Mask Register 2
|
||||
PCMSK1: 0x6c, // Pin Change Mask Register 1
|
||||
PCMSK0: 0x6b, // Pin Change Mask Register 0
|
||||
PCIFR: 0x3b, // Pin Change Interrupt Flag Register
|
||||
PCICR: 0x68, // Pin Change Interrupt Control Register
|
||||
}
|
||||
|
||||
// Analog-to-Digital Converter
|
||||
ADC = struct {
|
||||
ADMUX __reg
|
||||
ADCL __reg
|
||||
ADCH __reg
|
||||
ADCSRA __reg
|
||||
DIDR0 __reg
|
||||
}{
|
||||
ADMUX: 0x7c, // The ADC multiplexer Selection Register
|
||||
ADCL: 0x78, // ADC Data Register Bytes
|
||||
ADCH: 0x78, // ADC Data Register Bytes
|
||||
ADCSRA: 0x7a, // The ADC Control and Status register A
|
||||
DIDR0: 0x7e, // Digital Input Disable Register
|
||||
}
|
||||
|
||||
// JTAG Interface
|
||||
JTAG = struct {
|
||||
OCDR __reg
|
||||
}{
|
||||
OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory
|
||||
}
|
||||
|
||||
// EEPROM
|
||||
EEPROM = struct {
|
||||
EEARL __reg
|
||||
EEARH __reg
|
||||
EEDR __reg
|
||||
EECR __reg
|
||||
}{
|
||||
EEARL: 0x41, // EEPROM Address Register Low Bytes
|
||||
EEARH: 0x41, // EEPROM Address Register Low Bytes
|
||||
EEDR: 0x40, // EEPROM Data Register
|
||||
EECR: 0x3f, // EEPROM Control Register
|
||||
}
|
||||
|
||||
// Two Wire Serial Interface
|
||||
TWI = struct {
|
||||
TWAMR __reg
|
||||
TWBR __reg
|
||||
TWCR __reg
|
||||
TWSR __reg
|
||||
TWDR __reg
|
||||
TWAR __reg
|
||||
}{
|
||||
TWAMR: 0xbd, // TWI (Slave) Address Mask Register
|
||||
TWBR: 0xb8, // TWI Bit Rate register
|
||||
TWCR: 0xbc, // TWI Control Register
|
||||
TWSR: 0xb9, // TWI Status Register
|
||||
TWDR: 0xbb, // TWI Data register
|
||||
TWAR: 0xba, // TWI (Slave) Address register
|
||||
}
|
||||
|
||||
// Serial Peripheral Interface
|
||||
SPI = struct {
|
||||
SPDR __reg
|
||||
SPSR __reg
|
||||
SPCR __reg
|
||||
}{
|
||||
SPDR: 0x4e, // SPI Data Register
|
||||
SPSR: 0x4d, // SPI Status Register
|
||||
SPCR: 0x4c, // SPI Control Register
|
||||
}
|
||||
|
||||
// Watchdog Timer
|
||||
WDT = struct {
|
||||
WDTCSR __reg
|
||||
}{
|
||||
WDTCSR: 0x60, // Watchdog Timer Control Register
|
||||
}
|
||||
|
||||
// CPU Registers
|
||||
CPU = struct {
|
||||
SREG __reg
|
||||
SPL __reg
|
||||
SPH __reg
|
||||
OSCCAL __reg
|
||||
CLKPR __reg
|
||||
SMCR __reg
|
||||
RAMPZ __reg
|
||||
GPIOR2 __reg
|
||||
GPIOR1 __reg
|
||||
GPIOR0 __reg
|
||||
PRR0 __reg
|
||||
PRR1 __reg
|
||||
}{
|
||||
SREG: 0x5f, // Status Register
|
||||
SPL: 0x5d, // Stack Pointer
|
||||
SPH: 0x5d, // Stack Pointer
|
||||
OSCCAL: 0x66, // Oscillator Calibration Value
|
||||
CLKPR: 0x61,
|
||||
SMCR: 0x53, // Sleep Mode Control Register
|
||||
RAMPZ: 0x5b, // RAM Page Z Select Register
|
||||
GPIOR2: 0x4b, // General Purpose IO Register 2
|
||||
GPIOR1: 0x4a, // General Purpose IO Register 1
|
||||
GPIOR0: 0x3e, // General Purpose IO Register 0
|
||||
PRR0: 0x64, // Power Reduction Register0
|
||||
PRR1: 0x65, // Power Reduction Register1
|
||||
}
|
||||
)
|
||||
|
||||
// Bitfields for FUSE: Fuses
|
||||
const (
|
||||
// EXTENDED
|
||||
EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level
|
||||
|
||||
// HIGH
|
||||
HIGH_OCDEN = 0x80 // On-Chip Debug Enabled
|
||||
HIGH_JTAGEN = 0x40 // JTAG Interface Enabled
|
||||
HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled
|
||||
HIGH_WDTON = 0x10 // Watchdog timer always on
|
||||
HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle
|
||||
HIGH_BOOTSZ = 0x6 // Select Boot Size
|
||||
HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled
|
||||
|
||||
// LOW
|
||||
LOW_CKDIV8 = 0x80 // Divide clock by 8 internally
|
||||
LOW_CKOUT = 0x40 // Clock output on PORTB1
|
||||
LOW_SUT_CKSEL = 0x3f // Select Clock Source
|
||||
)
|
||||
|
||||
// Bitfields for LOCKBIT: Lockbits
|
||||
const (
|
||||
// LOCKBIT
|
||||
LOCKBIT_LB = 0x3 // Memory Lock
|
||||
LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode
|
||||
LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode
|
||||
)
|
||||
|
||||
// Bitfields for AC: Analog Comparator
|
||||
const (
|
||||
// ACSR: Analog Comparator Control And Status Register
|
||||
ACSR_ACD = 0x80 // Analog Comparator Disable
|
||||
ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select
|
||||
ACSR_ACO = 0x20 // Analog Compare Output
|
||||
ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag
|
||||
ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable
|
||||
ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable
|
||||
ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits
|
||||
|
||||
// DIDR1: Digital Input Disable Register 1
|
||||
DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable
|
||||
DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable
|
||||
)
|
||||
|
||||
// Bitfields for USART: USART
|
||||
const (
|
||||
// UDR0: USART I/O Data Register
|
||||
UDR0_UDR0 = 0xff // USART I/O Data bits
|
||||
|
||||
// UCSR0A: USART Control and Status Register A
|
||||
UCSR0A_RXC0 = 0x80 // USART Receive Complete
|
||||
UCSR0A_TXC0 = 0x40 // USART Transmitt Complete
|
||||
UCSR0A_UDRE0 = 0x20 // USART Data Register Empty
|
||||
UCSR0A_FE0 = 0x10 // Framing Error
|
||||
UCSR0A_DOR0 = 0x8 // Data overRun
|
||||
UCSR0A_UPE0 = 0x4 // Parity Error
|
||||
UCSR0A_U2X0 = 0x2 // Double the USART transmission speed
|
||||
UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode
|
||||
|
||||
// UCSR0B: USART Control and Status Register B
|
||||
UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable
|
||||
UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable
|
||||
UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable
|
||||
UCSR0B_RXEN0 = 0x10 // Receiver Enable
|
||||
UCSR0B_TXEN0 = 0x8 // Transmitter Enable
|
||||
UCSR0B_UCSZ02 = 0x4 // Character Size
|
||||
UCSR0B_RXB80 = 0x2 // Receive Data Bit 8
|
||||
UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8
|
||||
|
||||
// UCSR0C: USART Control and Status Register C
|
||||
UCSR0C_UMSEL0 = 0xc0 // USART Mode Select
|
||||
UCSR0C_UPM0 = 0x30 // Parity Mode Bits
|
||||
UCSR0C_USBS0 = 0x8 // Stop Bit Select
|
||||
UCSR0C_UCSZ0 = 0x6 // Character Size
|
||||
UCSR0C_UCPOL0 = 0x1 // Clock Polarity
|
||||
|
||||
// UBRR0L: USART Baud Rate Register Bytes
|
||||
|
||||
// UBRR0H: USART Baud Rate Register Bytes
|
||||
UBRR0_UBRR0 = 0xfff // USART Baud Rate Register
|
||||
|
||||
// UDR1: USART I/O Data Register
|
||||
UDR1_UDR1 = 0xff // USART I/O Data bits
|
||||
|
||||
// UCSR1A: USART Control and Status Register A
|
||||
UCSR1A_RXC1 = 0x80 // USART Receive Complete
|
||||
UCSR1A_TXC1 = 0x40 // USART Transmitt Complete
|
||||
UCSR1A_UDRE1 = 0x20 // USART Data Register Empty
|
||||
UCSR1A_FE1 = 0x10 // Framing Error
|
||||
UCSR1A_DOR1 = 0x8 // Data overRun
|
||||
UCSR1A_UPE1 = 0x4 // Parity Error
|
||||
UCSR1A_U2X1 = 0x2 // Double the USART transmission speed
|
||||
UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode
|
||||
|
||||
// UCSR1B: USART Control and Status Register B
|
||||
UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable
|
||||
UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable
|
||||
UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable
|
||||
UCSR1B_RXEN1 = 0x10 // Receiver Enable
|
||||
UCSR1B_TXEN1 = 0x8 // Transmitter Enable
|
||||
UCSR1B_UCSZ12 = 0x4 // Character Size
|
||||
UCSR1B_RXB81 = 0x2 // Receive Data Bit 8
|
||||
UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8
|
||||
|
||||
// UCSR1C: USART Control and Status Register C
|
||||
UCSR1C_UMSEL1 = 0xc0 // USART Mode Select
|
||||
UCSR1C_UPM1 = 0x30 // Parity Mode Bits
|
||||
UCSR1C_USBS1 = 0x8 // Stop Bit Select
|
||||
UCSR1C_UCSZ1 = 0x6 // Character Size
|
||||
UCSR1C_UCPOL1 = 0x1 // Clock Polarity
|
||||
|
||||
// UBRR1L: USART Baud Rate Register Bytes
|
||||
|
||||
// UBRR1H: USART Baud Rate Register Bytes
|
||||
UBRR1_UBRR1 = 0xfff // USART Baud Rate Register
|
||||
)
|
||||
|
||||
// Bitfields for TC8: Timer/Counter, 8-bit
|
||||
const (
|
||||
// OCR0B: Timer/Counter0 Output Compare Register B
|
||||
OCR0B_OCR0B = 0xff // Timer/Counter0 Output Compare B bits
|
||||
|
||||
// OCR0A: Timer/Counter0 Output Compare Register A
|
||||
OCR0A_OCR0A = 0xff // Timer/Counter0 Output Compare A bits
|
||||
|
||||
// TCNT0: Timer/Counter0
|
||||
TCNT0_TCNT0 = 0xff // Timer/Counter0 bits
|
||||
|
||||
// TCCR0B: Timer/Counter Control Register B
|
||||
TCCR0B_FOC0A = 0x80 // Force Output Compare A
|
||||
TCCR0B_FOC0B = 0x40 // Force Output Compare B
|
||||
TCCR0B_WGM02 = 0x8
|
||||
TCCR0B_CS0 = 0x7 // Clock Select
|
||||
|
||||
// TCCR0A: Timer/Counter Control Register A
|
||||
TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode
|
||||
TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm
|
||||
TCCR0A_WGM0 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TIMSK0: Timer/Counter0 Interrupt Mask Register
|
||||
TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable
|
||||
TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable
|
||||
TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable
|
||||
|
||||
// TIFR0: Timer/Counter0 Interrupt Flag register
|
||||
TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B
|
||||
TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A
|
||||
TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag
|
||||
)
|
||||
|
||||
// Bitfields for TC16: Timer/Counter, 16-bit
|
||||
const (
|
||||
// TIMSK1: Timer/Counter1 Interrupt Mask Register
|
||||
TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable
|
||||
TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable
|
||||
TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable
|
||||
TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable
|
||||
|
||||
// TIFR1: Timer/Counter Interrupt Flag register
|
||||
TIFR1_ICF1 = 0x20 // Timer/Counter1 Input Capture Flag
|
||||
TIFR1_OCF1B = 0x4 // Timer/Counter1 Output Compare B Match Flag
|
||||
TIFR1_OCF1A = 0x2 // Timer/Counter1 Output Compare A Match Flag
|
||||
TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag
|
||||
|
||||
// TCCR1A: Timer/Counter1 Control Register A
|
||||
TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits
|
||||
TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits
|
||||
TCCR1A_WGM1 = 0x3 // Pulse Width Modulator Select Bits
|
||||
|
||||
// TCCR1B: Timer/Counter1 Control Register B
|
||||
TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler
|
||||
TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select
|
||||
TCCR1B_WGM1 = 0x18 // Waveform Generation Mode Bits
|
||||
TCCR1B_CS1 = 0x7 // Clock Select1 bits
|
||||
|
||||
// TCCR1C: Timer/Counter1 Control Register C
|
||||
TCCR1C_FOC1A = 0x80 // Force Output Compare for Channel A
|
||||
TCCR1C_FOC1B = 0x40 // Force Output Compare for Channel B
|
||||
|
||||
// TCNT1L: Timer/Counter1 Bytes
|
||||
|
||||
// TCNT1H: Timer/Counter1 Bytes
|
||||
TCNT1_TCNT1 = 0xffff // Timer/Counter1 bits
|
||||
|
||||
// OCR1AL: Timer/Counter1 Output Compare Register A Bytes
|
||||
|
||||
// OCR1AH: Timer/Counter1 Output Compare Register A Bytes
|
||||
OCR1A_OCR1A = 0xffff // Timer/Counter1 Output Compare A bits
|
||||
|
||||
// OCR1BL: Timer/Counter1 Output Compare Register B Bytes
|
||||
|
||||
// OCR1BH: Timer/Counter1 Output Compare Register B Bytes
|
||||
OCR1B_OCR1B = 0xffff // Timer/Counter1 Output Compare B bits
|
||||
|
||||
// ICR1L: Timer/Counter1 Input Capture Register Bytes
|
||||
|
||||
// ICR1H: Timer/Counter1 Input Capture Register Bytes
|
||||
ICR1_ICR1 = 0xffff // Timer/Counter1 Input Capture bits
|
||||
|
||||
// TIMSK3: Timer/Counter3 Interrupt Mask Register
|
||||
TIMSK3_ICIE3 = 0x20 // Timer/Counter3 Input Capture Interrupt Enable
|
||||
TIMSK3_OCIE3B = 0x4 // Timer/Counter3 Output Compare B Match Interrupt Enable
|
||||
TIMSK3_OCIE3A = 0x2 // Timer/Counter3 Output Compare A Match Interrupt Enable
|
||||
TIMSK3_TOIE3 = 0x1 // Timer/Counter3 Overflow Interrupt Enable
|
||||
|
||||
// TIFR3: Timer/Counter Interrupt Flag register
|
||||
TIFR3_ICF3 = 0x20 // Timer/Counter3 Input Capture Flag
|
||||
TIFR3_OCF3B = 0x4 // Timer/Counter3 Output Compare B Match Flag
|
||||
TIFR3_OCF3A = 0x2 // Timer/Counter3 Output Compare A Match Flag
|
||||
TIFR3_TOV3 = 0x1 // Timer/Counter3 Overflow Flag
|
||||
|
||||
// TCCR3A: Timer/Counter3 Control Register A
|
||||
TCCR3A_COM3A = 0xc0 // Compare Output Mode 3A, bits
|
||||
TCCR3A_COM3B = 0x30 // Compare Output Mode 3B, bits
|
||||
TCCR3A_WGM3 = 0x3 // Pulse Width Modulator Select Bits
|
||||
|
||||
// TCCR3B: Timer/Counter3 Control Register B
|
||||
TCCR3B_ICNC3 = 0x80 // Input Capture 3 Noise Canceler
|
||||
TCCR3B_ICES3 = 0x40 // Input Capture 3 Edge Select
|
||||
TCCR3B_WGM3 = 0x18 // Waveform Generation Mode Bits
|
||||
TCCR3B_CS3 = 0x7 // Clock Select3 bits
|
||||
|
||||
// TCCR3C: Timer/Counter3 Control Register C
|
||||
TCCR3C_FOC3A = 0x80 // Force Output Compare for Channel A
|
||||
TCCR3C_FOC3B = 0x40 // Force Output Compare for Channel B
|
||||
|
||||
// TCNT3L: Timer/Counter3 Bytes
|
||||
|
||||
// TCNT3H: Timer/Counter3 Bytes
|
||||
TCNT3_TCNT3 = 0xffff // Timer/Counter3 bits
|
||||
|
||||
// OCR3AL: Timer/Counter3 Output Compare Register A Bytes
|
||||
|
||||
// OCR3AH: Timer/Counter3 Output Compare Register A Bytes
|
||||
OCR3A_OCR3A = 0xffff // Timer/Counter3 Output Compare A bits
|
||||
|
||||
// OCR3BL: Timer/Counter3 Output Compare Register B Bytes
|
||||
|
||||
// OCR3BH: Timer/Counter3 Output Compare Register B Bytes
|
||||
OCR3B_OCR3B = 0xffff // Timer/Counter3 Output Compare B bits
|
||||
|
||||
// ICR3L: Timer/Counter3 Input Capture Register Bytes
|
||||
|
||||
// ICR3H: Timer/Counter3 Input Capture Register Bytes
|
||||
ICR3_ICR3 = 0xffff // Timer/Counter3 Input Capture bits
|
||||
)
|
||||
|
||||
// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async
|
||||
const (
|
||||
// TIMSK2: Timer/Counter Interrupt Mask register
|
||||
TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable
|
||||
TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable
|
||||
TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable
|
||||
|
||||
// TIFR2: Timer/Counter Interrupt Flag Register
|
||||
TIFR2_OCF2B = 0x4 // Output Compare Flag 2B
|
||||
TIFR2_OCF2A = 0x2 // Output Compare Flag 2A
|
||||
TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag
|
||||
|
||||
// TCCR2A: Timer/Counter2 Control Register A
|
||||
TCCR2A_COM2A = 0xc0 // Compare Output Mode bits
|
||||
TCCR2A_COM2B = 0x30 // Compare Output Mode bits
|
||||
TCCR2A_WGM2 = 0x3 // Waveform Genration Mode
|
||||
|
||||
// TCCR2B: Timer/Counter2 Control Register B
|
||||
TCCR2B_FOC2A = 0x80 // Force Output Compare A
|
||||
TCCR2B_FOC2B = 0x40 // Force Output Compare B
|
||||
TCCR2B_WGM22 = 0x8 // Waveform Generation Mode
|
||||
TCCR2B_CS2 = 0x7 // Clock Select bits
|
||||
|
||||
// TCNT2: Timer/Counter2
|
||||
TCNT2_TCNT2 = 0xff // Timer/Counter2 bits
|
||||
|
||||
// OCR2B: Timer/Counter2 Output Compare Register B
|
||||
OCR2B_OCR2B = 0xff // Timer/Counter2 Output Compare B bits
|
||||
|
||||
// OCR2A: Timer/Counter2 Output Compare Register A
|
||||
OCR2A_OCR2A = 0xff // Timer/Counter2 Output Compare A bits
|
||||
|
||||
// ASSR: Asynchronous Status Register
|
||||
ASSR_EXCLK = 0x40 // Enable External Clock Input
|
||||
ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2
|
||||
ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy
|
||||
ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy
|
||||
ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy
|
||||
ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy
|
||||
ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy
|
||||
)
|
||||
|
||||
// Bitfields for BOOT_LOAD: Bootloader
|
||||
const (
|
||||
// SPMCSR: Store Program Memory Control Register
|
||||
SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable
|
||||
SPMCSR_RWWSB = 0x40 // Read While Write Section Busy
|
||||
SPMCSR_SIGRD = 0x20 // Signature Row Read
|
||||
SPMCSR_RWWSRE = 0x10 // Read While Write section read enable
|
||||
SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set
|
||||
SPMCSR_PGWRT = 0x4 // Page Write
|
||||
SPMCSR_PGERS = 0x2 // Page Erase
|
||||
SPMCSR_SPMEN = 0x1 // Store Program Memory Enable
|
||||
)
|
||||
|
||||
// Bitfields for EXINT: External Interrupts
|
||||
const (
|
||||
// EICRA: External Interrupt Control Register A
|
||||
EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit
|
||||
EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit
|
||||
EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit
|
||||
|
||||
// EIMSK: External Interrupt Mask Register
|
||||
EIMSK_INT = 0x7 // External Interrupt Request 2 Enable
|
||||
|
||||
// EIFR: External Interrupt Flag Register
|
||||
EIFR_INTF = 0x7 // External Interrupt Flags
|
||||
|
||||
// PCMSK3: Pin Change Mask Register 3
|
||||
PCMSK3_PCINT = 0xff // Pin Change Enable Masks
|
||||
|
||||
// PCMSK2: Pin Change Mask Register 2
|
||||
PCMSK2_PCINT = 0xff // Pin Change Enable Masks
|
||||
|
||||
// PCMSK1: Pin Change Mask Register 1
|
||||
PCMSK1_PCINT = 0xff // Pin Change Enable Masks
|
||||
|
||||
// PCMSK0: Pin Change Mask Register 0
|
||||
PCMSK0_PCINT = 0xff // Pin Change Enable Masks
|
||||
|
||||
// PCIFR: Pin Change Interrupt Flag Register
|
||||
PCIFR_PCIF = 0xf // Pin Change Interrupt Flags
|
||||
|
||||
// PCICR: Pin Change Interrupt Control Register
|
||||
PCICR_PCIE = 0xf // Pin Change Interrupt Enables
|
||||
)
|
||||
|
||||
// Bitfields for ADC: Analog-to-Digital Converter
|
||||
const (
|
||||
// ADMUX: The ADC multiplexer Selection Register
|
||||
ADMUX_REFS = 0xc0 // Reference Selection Bits
|
||||
ADMUX_ADLAR = 0x20 // Left Adjust Result
|
||||
ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits
|
||||
|
||||
// ADCL: ADC Data Register Bytes
|
||||
|
||||
// ADCH: ADC Data Register Bytes
|
||||
ADC_ADC = 0xffff // ADC Data bits
|
||||
|
||||
// ADCSRA: The ADC Control and Status register A
|
||||
ADCSRA_ADEN = 0x80 // ADC Enable
|
||||
ADCSRA_ADSC = 0x40 // ADC Start Conversion
|
||||
ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable
|
||||
ADCSRA_ADIF = 0x10 // ADC Interrupt Flag
|
||||
ADCSRA_ADIE = 0x8 // ADC Interrupt Enable
|
||||
ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits
|
||||
|
||||
// DIDR0: Digital Input Disable Register
|
||||
DIDR0_ADC7D = 0x80
|
||||
DIDR0_ADC6D = 0x40
|
||||
DIDR0_ADC5D = 0x20
|
||||
DIDR0_ADC4D = 0x10
|
||||
DIDR0_ADC3D = 0x8
|
||||
DIDR0_ADC2D = 0x4
|
||||
DIDR0_ADC1D = 0x2
|
||||
DIDR0_ADC0D = 0x1
|
||||
)
|
||||
|
||||
// Bitfields for EEPROM: EEPROM
|
||||
const (
|
||||
// EEARL: EEPROM Address Register Low Bytes
|
||||
|
||||
// EEARH: EEPROM Address Register Low Bytes
|
||||
EEAR_EEAR = 0xfff // EEPROM Address bits
|
||||
|
||||
// EEDR: EEPROM Data Register
|
||||
EEDR_EEDR = 0xff // EEPROM Data bits
|
||||
|
||||
// EECR: EEPROM Control Register
|
||||
EECR_EEPM = 0x30 // EEPROM Programming Mode Bits
|
||||
EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable
|
||||
EECR_EEMPE = 0x4 // EEPROM Master Write Enable
|
||||
EECR_EEPE = 0x2 // EEPROM Write Enable
|
||||
EECR_EERE = 0x1 // EEPROM Read Enable
|
||||
)
|
||||
|
||||
// Bitfields for TWI: Two Wire Serial Interface
|
||||
const (
|
||||
// TWAMR: TWI (Slave) Address Mask Register
|
||||
TWAMR_TWAM = 0xfe
|
||||
|
||||
// TWBR: TWI Bit Rate register
|
||||
TWBR_TWBR = 0xff // TWI Bit Rate bits
|
||||
|
||||
// TWCR: TWI Control Register
|
||||
TWCR_TWINT = 0x80 // TWI Interrupt Flag
|
||||
TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit
|
||||
TWCR_TWSTA = 0x20 // TWI Start Condition Bit
|
||||
TWCR_TWSTO = 0x10 // TWI Stop Condition Bit
|
||||
TWCR_TWWC = 0x8 // TWI Write Collition Flag
|
||||
TWCR_TWEN = 0x4 // TWI Enable Bit
|
||||
TWCR_TWIE = 0x1 // TWI Interrupt Enable
|
||||
|
||||
// TWSR: TWI Status Register
|
||||
TWSR_TWS = 0xf8 // TWI Status
|
||||
TWSR_TWPS = 0x3 // TWI Prescaler
|
||||
|
||||
// TWDR: TWI Data register
|
||||
TWDR_TWD = 0xff // TWI Data bits
|
||||
|
||||
// TWAR: TWI (Slave) Address register
|
||||
TWAR_TWA = 0xfe // TWI (Slave) Address register Bits
|
||||
TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit
|
||||
)
|
||||
|
||||
// Bitfields for SPI: Serial Peripheral Interface
|
||||
const (
|
||||
// SPDR: SPI Data Register
|
||||
SPDR_SPD = 0xff // SPI Data bits
|
||||
|
||||
// SPSR: SPI Status Register
|
||||
SPSR_SPIF = 0x80 // SPI Interrupt Flag
|
||||
SPSR_WCOL = 0x40 // Write Collision Flag
|
||||
SPSR_SPI2X = 0x1 // Double SPI Speed Bit
|
||||
|
||||
// SPCR: SPI Control Register
|
||||
SPCR_SPIE = 0x80 // SPI Interrupt Enable
|
||||
SPCR_SPE = 0x40 // SPI Enable
|
||||
SPCR_DORD = 0x20 // Data Order
|
||||
SPCR_MSTR = 0x10 // Master/Slave Select
|
||||
SPCR_CPOL = 0x8 // Clock polarity
|
||||
SPCR_CPHA = 0x4 // Clock Phase
|
||||
SPCR_SPR = 0x3 // SPI Clock Rate Selects
|
||||
)
|
||||
|
||||
// Bitfields for WDT: Watchdog Timer
|
||||
const (
|
||||
// WDTCSR: Watchdog Timer Control Register
|
||||
WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag
|
||||
WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable
|
||||
WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits
|
||||
WDTCSR_WDCE = 0x10 // Watchdog Change Enable
|
||||
WDTCSR_WDE = 0x8 // Watch Dog Enable
|
||||
)
|
||||
|
||||
// Bitfields for CPU: CPU Registers
|
||||
const (
|
||||
// SREG: Status Register
|
||||
SREG_I = 0x80 // Global Interrupt Enable
|
||||
SREG_T = 0x40 // Bit Copy Storage
|
||||
SREG_H = 0x20 // Half Carry Flag
|
||||
SREG_S = 0x10 // Sign Bit
|
||||
SREG_V = 0x8 // Two's Complement Overflow Flag
|
||||
SREG_N = 0x4 // Negative Flag
|
||||
SREG_Z = 0x2 // Zero Flag
|
||||
SREG_C = 0x1 // Carry Flag
|
||||
|
||||
// OSCCAL: Oscillator Calibration Value
|
||||
OSCCAL_OSCCAL = 0xff // Oscillator Calibration
|
||||
|
||||
// CLKPR
|
||||
CLKPR_CLKPCE = 0x80
|
||||
CLKPR_CLKPS = 0xf
|
||||
|
||||
// SMCR: Sleep Mode Control Register
|
||||
SMCR_SM = 0xe // Sleep Mode Select bits
|
||||
SMCR_SE = 0x1 // Sleep Enable
|
||||
|
||||
// GPIOR2: General Purpose IO Register 2
|
||||
GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis
|
||||
|
||||
// GPIOR1: General Purpose IO Register 1
|
||||
GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis
|
||||
|
||||
// GPIOR0: General Purpose IO Register 0
|
||||
GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7
|
||||
GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6
|
||||
GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5
|
||||
GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4
|
||||
GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3
|
||||
GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2
|
||||
GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1
|
||||
GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0
|
||||
|
||||
// PRR0: Power Reduction Register0
|
||||
PRR0_PRTWI = 0x80 // Power Reduction TWI
|
||||
PRR0_PRTIM2 = 0x40 // Power Reduction Timer/Counter2
|
||||
PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0
|
||||
PRR0_PRUSART1 = 0x10 // Power Reduction USART1
|
||||
PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1
|
||||
PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface
|
||||
PRR0_PRUSART0 = 0x2 // Power Reduction USART0
|
||||
PRR0_PRADC = 0x1 // Power Reduction ADC
|
||||
|
||||
// PRR1: Power Reduction Register1
|
||||
PRR1_PRTIM3 = 0x1 // Power Reduction Timer/Counter3
|
||||
)
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from ATmega1284P.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x20000;
|
||||
__ram_size = 0x4000;
|
||||
__num_isrs = 35;
|
||||
Различия файлов не показаны, т.к. их слишком много
Показать различия
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from ATmega1284RFR2.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x20000;
|
||||
__ram_size = 0x4000;
|
||||
__num_isrs = 71;
|
||||
|
|
@ -1,666 +0,0 @@
|
|||
// Automatically generated file. DO NOT EDIT.
|
||||
// Generated by gen-device.py from ATmega128A.atdf, see http://packs.download.atmel.com/
|
||||
|
||||
// +build avr,atmega128a
|
||||
|
||||
// Device information for the ATmega128A.
|
||||
//
|
||||
package avr
|
||||
|
||||
// Magic type name for the compiler.
|
||||
type __reg uint8
|
||||
|
||||
// Export this magic type name.
|
||||
type RegValue = __reg
|
||||
|
||||
// Some information about this device.
|
||||
const (
|
||||
DEVICE = "ATmega128A"
|
||||
ARCH = "AVR8"
|
||||
FAMILY = "megaAVR"
|
||||
)
|
||||
|
||||
// Interrupts
|
||||
const (
|
||||
IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset
|
||||
IRQ_INT0 = 1 // External Interrupt Request 0
|
||||
IRQ_INT1 = 2 // External Interrupt Request 1
|
||||
IRQ_INT2 = 3 // External Interrupt Request 2
|
||||
IRQ_INT3 = 4 // External Interrupt Request 3
|
||||
IRQ_INT4 = 5 // External Interrupt Request 4
|
||||
IRQ_INT5 = 6 // External Interrupt Request 5
|
||||
IRQ_INT6 = 7 // External Interrupt Request 6
|
||||
IRQ_INT7 = 8 // External Interrupt Request 7
|
||||
IRQ_TIMER2_COMP = 9 // Timer/Counter2 Compare Match
|
||||
IRQ_TIMER2_OVF = 10 // Timer/Counter2 Overflow
|
||||
IRQ_TIMER1_CAPT = 11 // Timer/Counter1 Capture Event
|
||||
IRQ_TIMER1_COMPA = 12 // Timer/Counter1 Compare Match A
|
||||
IRQ_TIMER1_COMPB = 13 // Timer/Counter Compare Match B
|
||||
IRQ_TIMER1_OVF = 14 // Timer/Counter1 Overflow
|
||||
IRQ_TIMER0_COMP = 15 // Timer/Counter0 Compare Match
|
||||
IRQ_TIMER0_OVF = 16 // Timer/Counter0 Overflow
|
||||
IRQ_SPI_STC = 17 // SPI Serial Transfer Complete
|
||||
IRQ_USART0_RX = 18 // USART0, Rx Complete
|
||||
IRQ_USART0_UDRE = 19 // USART0 Data Register Empty
|
||||
IRQ_USART0_TX = 20 // USART0, Tx Complete
|
||||
IRQ_ADC = 21 // ADC Conversion Complete
|
||||
IRQ_EE_READY = 22 // EEPROM Ready
|
||||
IRQ_ANALOG_COMP = 23 // Analog Comparator
|
||||
IRQ_TIMER1_COMPC = 24 // Timer/Counter1 Compare Match C
|
||||
IRQ_TIMER3_CAPT = 25 // Timer/Counter3 Capture Event
|
||||
IRQ_TIMER3_COMPA = 26 // Timer/Counter3 Compare Match A
|
||||
IRQ_TIMER3_COMPB = 27 // Timer/Counter3 Compare Match B
|
||||
IRQ_TIMER3_COMPC = 28 // Timer/Counter3 Compare Match C
|
||||
IRQ_TIMER3_OVF = 29 // Timer/Counter3 Overflow
|
||||
IRQ_USART1_RX = 30 // USART1, Rx Complete
|
||||
IRQ_USART1_UDRE = 31 // USART1, Data Register Empty
|
||||
IRQ_USART1_TX = 32 // USART1, Tx Complete
|
||||
IRQ_TWI = 33 // 2-wire Serial Interface
|
||||
IRQ_SPM_READY = 34 // Store Program Memory Read
|
||||
IRQ_max = 34 // Highest interrupt number on this device.
|
||||
)
|
||||
|
||||
// Peripherals
|
||||
var (
|
||||
// Fuses
|
||||
FUSE = struct {
|
||||
EXTENDED __reg
|
||||
HIGH __reg
|
||||
LOW __reg
|
||||
}{
|
||||
EXTENDED: 0x2,
|
||||
HIGH: 0x1,
|
||||
LOW: 0x0,
|
||||
}
|
||||
|
||||
// Lockbits
|
||||
LOCKBIT = struct {
|
||||
LOCKBIT __reg
|
||||
}{
|
||||
LOCKBIT: 0x0,
|
||||
}
|
||||
|
||||
// Analog Comparator
|
||||
AC = struct {
|
||||
ACSR __reg
|
||||
}{
|
||||
ACSR: 0x28, // Analog Comparator Control And Status Register
|
||||
}
|
||||
|
||||
// Serial Peripheral Interface
|
||||
SPI = struct {
|
||||
SPDR __reg
|
||||
SPSR __reg
|
||||
SPCR __reg
|
||||
}{
|
||||
SPDR: 0x2f, // SPI Data Register
|
||||
SPSR: 0x2e, // SPI Status Register
|
||||
SPCR: 0x2d, // SPI Control Register
|
||||
}
|
||||
|
||||
// Two Wire Serial Interface
|
||||
TWI = struct {
|
||||
TWBR __reg
|
||||
TWCR __reg
|
||||
TWSR __reg
|
||||
TWDR __reg
|
||||
TWAR __reg
|
||||
}{
|
||||
TWBR: 0x70, // TWI Bit Rate register
|
||||
TWCR: 0x74, // TWI Control Register
|
||||
TWSR: 0x71, // TWI Status Register
|
||||
TWDR: 0x73, // TWI Data register
|
||||
TWAR: 0x72, // TWI (Slave) Address register
|
||||
}
|
||||
|
||||
// USART
|
||||
USART = struct {
|
||||
UDR0 __reg
|
||||
UCSR0A __reg
|
||||
UCSR0B __reg
|
||||
UCSR0C __reg
|
||||
UBRR0H __reg
|
||||
UBRR0L __reg
|
||||
UDR1 __reg
|
||||
UCSR1A __reg
|
||||
UCSR1B __reg
|
||||
UCSR1C __reg
|
||||
UBRR1H __reg
|
||||
UBRR1L __reg
|
||||
}{
|
||||
UDR0: 0x2c, // USART I/O Data Register
|
||||
UCSR0A: 0x2b, // USART Control and Status Register A
|
||||
UCSR0B: 0x2a, // USART Control and Status Register B
|
||||
UCSR0C: 0x95, // USART Control and Status Register C
|
||||
UBRR0H: 0x90, // USART Baud Rate Register Hight Byte
|
||||
UBRR0L: 0x29, // USART Baud Rate Register Low Byte
|
||||
UDR1: 0x9c, // USART I/O Data Register
|
||||
UCSR1A: 0x9b, // USART Control and Status Register A
|
||||
UCSR1B: 0x9a, // USART Control and Status Register B
|
||||
UCSR1C: 0x9d, // USART Control and Status Register C
|
||||
UBRR1H: 0x98, // USART Baud Rate Register Hight Byte
|
||||
UBRR1L: 0x99, // USART Baud Rate Register Low Byte
|
||||
}
|
||||
|
||||
// CPU Registers
|
||||
CPU = struct {
|
||||
SREG __reg
|
||||
SPL __reg
|
||||
SPH __reg
|
||||
MCUCR __reg
|
||||
XMCRA __reg
|
||||
XMCRB __reg
|
||||
OSCCAL __reg
|
||||
XDIV __reg
|
||||
RAMPZ __reg
|
||||
}{
|
||||
SREG: 0x5f, // Status Register
|
||||
SPL: 0x5d, // Stack Pointer
|
||||
SPH: 0x5d, // Stack Pointer
|
||||
MCUCR: 0x55, // MCU Control Register
|
||||
XMCRA: 0x6d, // External Memory Control Register A
|
||||
XMCRB: 0x6c, // External Memory Control Register B
|
||||
OSCCAL: 0x6f, // Oscillator Calibration Value
|
||||
XDIV: 0x5c, // XTAL Divide Control Register
|
||||
RAMPZ: 0x5b, // RAM Page Z Select Register
|
||||
}
|
||||
|
||||
// Bootloader
|
||||
BOOT_LOAD = struct {
|
||||
SPMCSR __reg
|
||||
}{
|
||||
SPMCSR: 0x68, // Store Program Memory Control Register
|
||||
}
|
||||
|
||||
// JTAG Interface
|
||||
JTAG = struct {
|
||||
OCDR __reg
|
||||
}{
|
||||
OCDR: 0x42, // On-Chip Debug Related Register in I/O Memory
|
||||
}
|
||||
|
||||
// Other Registers
|
||||
MISC = struct {
|
||||
}{}
|
||||
|
||||
// External Interrupts
|
||||
EXINT = struct {
|
||||
EICRA __reg
|
||||
EICRB __reg
|
||||
EIMSK __reg
|
||||
EIFR __reg
|
||||
}{
|
||||
EICRA: 0x6a, // External Interrupt Control Register A
|
||||
EICRB: 0x5a, // External Interrupt Control Register B
|
||||
EIMSK: 0x59, // External Interrupt Mask Register
|
||||
EIFR: 0x58, // External Interrupt Flag Register
|
||||
}
|
||||
|
||||
// EEPROM
|
||||
EEPROM = struct {
|
||||
EEARL __reg
|
||||
EEARH __reg
|
||||
EEDR __reg
|
||||
EECR __reg
|
||||
}{
|
||||
EEARL: 0x3e, // EEPROM Read/Write Access Bytes
|
||||
EEARH: 0x3e, // EEPROM Read/Write Access Bytes
|
||||
EEDR: 0x3d, // EEPROM Data Register
|
||||
EECR: 0x3c, // EEPROM Control Register
|
||||
}
|
||||
|
||||
// I/O Port
|
||||
PORT = struct {
|
||||
PORTA __reg
|
||||
DDRA __reg
|
||||
PINA __reg
|
||||
PORTB __reg
|
||||
DDRB __reg
|
||||
PINB __reg
|
||||
PORTC __reg
|
||||
DDRC __reg
|
||||
PINC __reg
|
||||
PORTD __reg
|
||||
DDRD __reg
|
||||
PIND __reg
|
||||
PORTE __reg
|
||||
DDRE __reg
|
||||
PINE __reg
|
||||
PORTF __reg
|
||||
DDRF __reg
|
||||
PINF __reg
|
||||
PORTG __reg
|
||||
DDRG __reg
|
||||
PING __reg
|
||||
}{
|
||||
PORTA: 0x3b, // Port A Data Register
|
||||
DDRA: 0x3a, // Port A Data Direction Register
|
||||
PINA: 0x39, // Port A Input Pins
|
||||
PORTB: 0x38, // Port B Data Register
|
||||
DDRB: 0x37, // Port B Data Direction Register
|
||||
PINB: 0x36, // Port B Input Pins
|
||||
PORTC: 0x35, // Port C Data Register
|
||||
DDRC: 0x34, // Port C Data Direction Register
|
||||
PINC: 0x33, // Port C Input Pins
|
||||
PORTD: 0x32, // Port D Data Register
|
||||
DDRD: 0x31, // Port D Data Direction Register
|
||||
PIND: 0x30, // Port D Input Pins
|
||||
PORTE: 0x23, // Data Register, Port E
|
||||
DDRE: 0x22, // Data Direction Register, Port E
|
||||
PINE: 0x21, // Input Pins, Port E
|
||||
PORTF: 0x62, // Data Register, Port F
|
||||
DDRF: 0x61, // Data Direction Register, Port F
|
||||
PINF: 0x20, // Input Pins, Port F
|
||||
PORTG: 0x65, // Data Register, Port G
|
||||
DDRG: 0x64, // Data Direction Register, Port G
|
||||
PING: 0x63, // Input Pins, Port G
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit Async
|
||||
TC8_ASYNC = struct {
|
||||
TCCR0 __reg
|
||||
TCNT0 __reg
|
||||
OCR0 __reg
|
||||
ASSR __reg
|
||||
}{
|
||||
TCCR0: 0x53, // Timer/Counter Control Register
|
||||
TCNT0: 0x52, // Timer/Counter Register
|
||||
OCR0: 0x51, // Output Compare Register
|
||||
ASSR: 0x50, // Asynchronus Status Register
|
||||
}
|
||||
|
||||
// Timer/Counter, 16-bit
|
||||
TC16 = struct {
|
||||
TCCR1A __reg
|
||||
TCCR1B __reg
|
||||
TCCR1C __reg
|
||||
TCNT1L __reg
|
||||
TCNT1H __reg
|
||||
OCR1AL __reg
|
||||
OCR1AH __reg
|
||||
OCR1BL __reg
|
||||
OCR1BH __reg
|
||||
OCR1CL __reg
|
||||
OCR1CH __reg
|
||||
ICR1L __reg
|
||||
ICR1H __reg
|
||||
TCCR3A __reg
|
||||
TCCR3B __reg
|
||||
TCCR3C __reg
|
||||
TCNT3L __reg
|
||||
TCNT3H __reg
|
||||
OCR3AL __reg
|
||||
OCR3AH __reg
|
||||
OCR3BL __reg
|
||||
OCR3BH __reg
|
||||
OCR3CL __reg
|
||||
OCR3CH __reg
|
||||
ICR3L __reg
|
||||
ICR3H __reg
|
||||
}{
|
||||
TCCR1A: 0x4f, // Timer/Counter1 Control Register A
|
||||
TCCR1B: 0x4e, // Timer/Counter1 Control Register B
|
||||
TCCR1C: 0x7a, // Timer/Counter1 Control Register C
|
||||
TCNT1L: 0x4c, // Timer/Counter1 Bytes
|
||||
TCNT1H: 0x4c, // Timer/Counter1 Bytes
|
||||
OCR1AL: 0x4a, // Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1AH: 0x4a, // Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1BL: 0x48, // Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1BH: 0x48, // Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1CL: 0x78, // Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1CH: 0x78, // Timer/Counter1 Output Compare Register Bytes
|
||||
ICR1L: 0x46, // Timer/Counter1 Input Capture Register Bytes
|
||||
ICR1H: 0x46, // Timer/Counter1 Input Capture Register Bytes
|
||||
TCCR3A: 0x8b, // Timer/Counter3 Control Register A
|
||||
TCCR3B: 0x8a, // Timer/Counter3 Control Register B
|
||||
TCCR3C: 0x8c, // Timer/Counter3 Control Register C
|
||||
TCNT3L: 0x88, // Timer/Counter3 Bytes
|
||||
TCNT3H: 0x88, // Timer/Counter3 Bytes
|
||||
OCR3AL: 0x86, // Timer/Counter3 Output Compare Register A Bytes
|
||||
OCR3AH: 0x86, // Timer/Counter3 Output Compare Register A Bytes
|
||||
OCR3BL: 0x84, // Timer/Counter3 Output Compare Register B Bytes
|
||||
OCR3BH: 0x84, // Timer/Counter3 Output Compare Register B Bytes
|
||||
OCR3CL: 0x82, // Timer/Counter3 Output compare Register C Bytes
|
||||
OCR3CH: 0x82, // Timer/Counter3 Output compare Register C Bytes
|
||||
ICR3L: 0x80, // Timer/Counter3 Input Capture Register Bytes
|
||||
ICR3H: 0x80, // Timer/Counter3 Input Capture Register Bytes
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit
|
||||
TC8 = struct {
|
||||
TCCR2 __reg
|
||||
TCNT2 __reg
|
||||
OCR2 __reg
|
||||
}{
|
||||
TCCR2: 0x45, // Timer/Counter Control Register
|
||||
TCNT2: 0x44, // Timer/Counter Register
|
||||
OCR2: 0x43, // Output Compare Register
|
||||
}
|
||||
|
||||
// Watchdog Timer
|
||||
WDT = struct {
|
||||
WDTCR __reg
|
||||
}{
|
||||
WDTCR: 0x41, // Watchdog Timer Control Register
|
||||
}
|
||||
|
||||
// Analog-to-Digital Converter
|
||||
ADC = struct {
|
||||
ADMUX __reg
|
||||
ADCSRA __reg
|
||||
ADCL __reg
|
||||
ADCH __reg
|
||||
}{
|
||||
ADMUX: 0x27, // The ADC multiplexer Selection Register
|
||||
ADCSRA: 0x26, // The ADC Control and Status register
|
||||
ADCL: 0x24, // ADC Data Register Bytes
|
||||
ADCH: 0x24, // ADC Data Register Bytes
|
||||
}
|
||||
)
|
||||
|
||||
// Bitfields for FUSE: Fuses
|
||||
const (
|
||||
// EXTENDED
|
||||
EXTENDED_M103C = 0x2 // ATmega103 Compatibility Mode
|
||||
EXTENDED_WDTON = 0x1 // Watchdog Timer always on
|
||||
|
||||
// HIGH
|
||||
HIGH_OCDEN = 0x80 // On-Chip Debug Enabled
|
||||
HIGH_JTAGEN = 0x40 // JTAG Interface Enabled
|
||||
HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled
|
||||
HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle
|
||||
HIGH_BOOTSZ = 0x6 // Select Boot Size
|
||||
HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled
|
||||
HIGH_CKOPT = 0x10 // CKOPT fuse (operation dependent of CKSEL fuses)
|
||||
|
||||
// LOW
|
||||
LOW_BODLEVEL = 0x80 // Brownout detector trigger level
|
||||
LOW_BODEN = 0x40 // Brown-out detection enabled
|
||||
LOW_SUT_CKSEL = 0x3f // Select Clock Source
|
||||
)
|
||||
|
||||
// Bitfields for LOCKBIT: Lockbits
|
||||
const (
|
||||
// LOCKBIT
|
||||
LOCKBIT_LB = 0x3 // Memory Lock
|
||||
LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode
|
||||
LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode
|
||||
)
|
||||
|
||||
// Bitfields for AC: Analog Comparator
|
||||
const (
|
||||
// ACSR: Analog Comparator Control And Status Register
|
||||
ACSR_ACD = 0x80 // Analog Comparator Disable
|
||||
ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select
|
||||
ACSR_ACO = 0x20 // Analog Compare Output
|
||||
ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag
|
||||
ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable
|
||||
ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable
|
||||
ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits
|
||||
)
|
||||
|
||||
// Bitfields for SPI: Serial Peripheral Interface
|
||||
const (
|
||||
// SPSR: SPI Status Register
|
||||
SPSR_SPIF = 0x80 // SPI Interrupt Flag
|
||||
SPSR_WCOL = 0x40 // Write Collision Flag
|
||||
SPSR_SPI2X = 0x1 // Double SPI Speed Bit
|
||||
|
||||
// SPCR: SPI Control Register
|
||||
SPCR_SPIE = 0x80 // SPI Interrupt Enable
|
||||
SPCR_SPE = 0x40 // SPI Enable
|
||||
SPCR_DORD = 0x20 // Data Order
|
||||
SPCR_MSTR = 0x10 // Master/Slave Select
|
||||
SPCR_CPOL = 0x8 // Clock polarity
|
||||
SPCR_CPHA = 0x4 // Clock Phase
|
||||
SPCR_SPR = 0x3 // SPI Clock Rate Selects
|
||||
)
|
||||
|
||||
// Bitfields for TWI: Two Wire Serial Interface
|
||||
const (
|
||||
// TWCR: TWI Control Register
|
||||
TWCR_TWINT = 0x80 // TWI Interrupt Flag
|
||||
TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit
|
||||
TWCR_TWSTA = 0x20 // TWI Start Condition Bit
|
||||
TWCR_TWSTO = 0x10 // TWI Stop Condition Bit
|
||||
TWCR_TWWC = 0x8 // TWI Write Collition Flag
|
||||
TWCR_TWEN = 0x4 // TWI Enable Bit
|
||||
TWCR_TWIE = 0x1 // TWI Interrupt Enable
|
||||
|
||||
// TWSR: TWI Status Register
|
||||
TWSR_TWS = 0xf8 // TWI Status
|
||||
TWSR_TWPS = 0x3 // TWI Prescaler
|
||||
|
||||
// TWAR: TWI (Slave) Address register
|
||||
TWAR_TWA = 0xfe // TWI (Slave) Address register Bits
|
||||
TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit
|
||||
)
|
||||
|
||||
// Bitfields for USART: USART
|
||||
const (
|
||||
// UCSR0A: USART Control and Status Register A
|
||||
UCSR0A_RXC0 = 0x80 // USART Receive Complete
|
||||
UCSR0A_TXC0 = 0x40 // USART Transmitt Complete
|
||||
UCSR0A_UDRE0 = 0x20 // USART Data Register Empty
|
||||
UCSR0A_FE0 = 0x10 // Framing Error
|
||||
UCSR0A_DOR0 = 0x8 // Data overRun
|
||||
UCSR0A_UPE0 = 0x4 // Parity Error
|
||||
UCSR0A_U2X0 = 0x2 // Double the USART transmission speed
|
||||
UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode
|
||||
|
||||
// UCSR0B: USART Control and Status Register B
|
||||
UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable
|
||||
UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable
|
||||
UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable
|
||||
UCSR0B_RXEN0 = 0x10 // Receiver Enable
|
||||
UCSR0B_TXEN0 = 0x8 // Transmitter Enable
|
||||
UCSR0B_UCSZ02 = 0x4 // Character Size
|
||||
UCSR0B_RXB80 = 0x2 // Receive Data Bit 8
|
||||
UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8
|
||||
|
||||
// UCSR0C: USART Control and Status Register C
|
||||
UCSR0C_UMSEL0 = 0x40 // USART Mode Select
|
||||
UCSR0C_UPM0 = 0x30 // Parity Mode Bits
|
||||
UCSR0C_USBS0 = 0x8 // Stop Bit Select
|
||||
UCSR0C_UCSZ0 = 0x6 // Character Size
|
||||
UCSR0C_UCPOL0 = 0x1 // Clock Polarity
|
||||
|
||||
// UCSR1A: USART Control and Status Register A
|
||||
UCSR1A_RXC1 = 0x80 // USART Receive Complete
|
||||
UCSR1A_TXC1 = 0x40 // USART Transmitt Complete
|
||||
UCSR1A_UDRE1 = 0x20 // USART Data Register Empty
|
||||
UCSR1A_FE1 = 0x10 // Framing Error
|
||||
UCSR1A_DOR1 = 0x8 // Data overRun
|
||||
UCSR1A_UPE1 = 0x4 // Parity Error
|
||||
UCSR1A_U2X1 = 0x2 // Double the USART transmission speed
|
||||
UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode
|
||||
|
||||
// UCSR1B: USART Control and Status Register B
|
||||
UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable
|
||||
UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable
|
||||
UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable
|
||||
UCSR1B_RXEN1 = 0x10 // Receiver Enable
|
||||
UCSR1B_TXEN1 = 0x8 // Transmitter Enable
|
||||
UCSR1B_UCSZ12 = 0x4 // Character Size
|
||||
UCSR1B_RXB81 = 0x2 // Receive Data Bit 8
|
||||
UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8
|
||||
|
||||
// UCSR1C: USART Control and Status Register C
|
||||
UCSR1C_UMSEL1 = 0x40 // USART Mode Select
|
||||
UCSR1C_UPM1 = 0x30 // Parity Mode Bits
|
||||
UCSR1C_USBS1 = 0x8 // Stop Bit Select
|
||||
UCSR1C_UCSZ1 = 0x6 // Character Size
|
||||
UCSR1C_UCPOL1 = 0x1 // Clock Polarity
|
||||
)
|
||||
|
||||
// Bitfields for CPU: CPU Registers
|
||||
const (
|
||||
// SREG: Status Register
|
||||
SREG_I = 0x80 // Global Interrupt Enable
|
||||
SREG_T = 0x40 // Bit Copy Storage
|
||||
SREG_H = 0x20 // Half Carry Flag
|
||||
SREG_S = 0x10 // Sign Bit
|
||||
SREG_V = 0x8 // Two's Complement Overflow Flag
|
||||
SREG_N = 0x4 // Negative Flag
|
||||
SREG_Z = 0x2 // Zero Flag
|
||||
SREG_C = 0x1 // Carry Flag
|
||||
|
||||
// MCUCR: MCU Control Register
|
||||
MCUCR_SRE = 0x80 // External SRAM Enable
|
||||
MCUCR_SRW10 = 0x40 // External SRAM Wait State Select
|
||||
MCUCR_SE = 0x20 // Sleep Enable
|
||||
MCUCR_SM = 0x18 // Sleep Mode Select
|
||||
MCUCR_SM2 = 0x4 // Sleep Mode Select
|
||||
MCUCR_IVSEL = 0x2 // Interrupt Vector Select
|
||||
MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable
|
||||
|
||||
// XMCRA: External Memory Control Register A
|
||||
XMCRA_SRL = 0x70 // Wait state page limit
|
||||
XMCRA_SRW0 = 0xc // Wait state select bit lower page
|
||||
XMCRA_SRW11 = 0x2 // Wait state select bit upper page
|
||||
|
||||
// XMCRB: External Memory Control Register B
|
||||
XMCRB_XMBK = 0x80 // External Memory Bus Keeper Enable
|
||||
XMCRB_XMM = 0x7 // External Memory High Mask
|
||||
|
||||
// OSCCAL: Oscillator Calibration Value
|
||||
OSCCAL_OSCCAL = 0xff // Oscillator Calibration
|
||||
|
||||
// RAMPZ: RAM Page Z Select Register
|
||||
RAMPZ_RAMPZ0 = 0x1 // RAM Page Z Select Register Bit 0
|
||||
)
|
||||
|
||||
// Bitfields for BOOT_LOAD: Bootloader
|
||||
const (
|
||||
// SPMCSR: Store Program Memory Control Register
|
||||
SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable
|
||||
SPMCSR_RWWSB = 0x40 // Read While Write Section Busy
|
||||
SPMCSR_RWWSRE = 0x10 // Read While Write section read enable
|
||||
SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set
|
||||
SPMCSR_PGWRT = 0x4 // Page Write
|
||||
SPMCSR_PGERS = 0x2 // Page Erase
|
||||
SPMCSR_SPMEN = 0x1 // Store Program Memory Enable
|
||||
)
|
||||
|
||||
// Bitfields for JTAG: JTAG Interface
|
||||
const (
|
||||
// OCDR: On-Chip Debug Related Register in I/O Memory
|
||||
OCDR_OCDR = 0xff // On-Chip Debug Register Bits
|
||||
)
|
||||
|
||||
// Bitfields for EXINT: External Interrupts
|
||||
const (
|
||||
// EICRA: External Interrupt Control Register A
|
||||
EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit
|
||||
EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit
|
||||
EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit
|
||||
EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit
|
||||
|
||||
// EICRB: External Interrupt Control Register B
|
||||
EICRB_ISC7 = 0xc0 // External Interrupt 7-4 Sense Control Bit
|
||||
EICRB_ISC6 = 0x30 // External Interrupt 7-4 Sense Control Bit
|
||||
EICRB_ISC5 = 0xc // External Interrupt 7-4 Sense Control Bit
|
||||
EICRB_ISC4 = 0x3 // External Interrupt 7-4 Sense Control Bit
|
||||
|
||||
// EIMSK: External Interrupt Mask Register
|
||||
EIMSK_INT = 0xff // External Interrupt Request 7 Enable
|
||||
|
||||
// EIFR: External Interrupt Flag Register
|
||||
EIFR_INTF = 0xff // External Interrupt Flags
|
||||
)
|
||||
|
||||
// Bitfields for EEPROM: EEPROM
|
||||
const (
|
||||
// EECR: EEPROM Control Register
|
||||
EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable
|
||||
EECR_EEMWE = 0x4 // EEPROM Master Write Enable
|
||||
EECR_EEWE = 0x2 // EEPROM Write Enable
|
||||
EECR_EERE = 0x1 // EEPROM Read Enable
|
||||
)
|
||||
|
||||
// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async
|
||||
const (
|
||||
// TCCR0: Timer/Counter Control Register
|
||||
TCCR0_FOC0 = 0x80 // Force Output Compare
|
||||
TCCR0_WGM00 = 0x40 // Waveform Generation Mode 0
|
||||
TCCR0_COM0 = 0x30 // Compare Match Output Modes
|
||||
TCCR0_WGM01 = 0x8 // Waveform Generation Mode 1
|
||||
TCCR0_CS0 = 0x7 // Clock Selects
|
||||
|
||||
// ASSR: Asynchronus Status Register
|
||||
ASSR_AS0 = 0x8 // Asynchronus Timer/Counter 0
|
||||
ASSR_TCN0UB = 0x4 // Timer/Counter0 Update Busy
|
||||
ASSR_OCR0UB = 0x2 // Output Compare register 0 Busy
|
||||
ASSR_TCR0UB = 0x1 // Timer/Counter Control Register 0 Update Busy
|
||||
)
|
||||
|
||||
// Bitfields for TC16: Timer/Counter, 16-bit
|
||||
const (
|
||||
// TCCR1A: Timer/Counter1 Control Register A
|
||||
TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits
|
||||
TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits
|
||||
TCCR1A_COM1C = 0xc // Compare Output Mode 1C, bits
|
||||
TCCR1A_WGM1 = 0x3 // Waveform Generation Mode Bits
|
||||
|
||||
// TCCR1B: Timer/Counter1 Control Register B
|
||||
TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler
|
||||
TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select
|
||||
TCCR1B_WGM1 = 0x18 // Waveform Generation Mode
|
||||
TCCR1B_CS1 = 0x7 // Clock Select1 bits
|
||||
|
||||
// TCCR1C: Timer/Counter1 Control Register C
|
||||
TCCR1C_FOC1A = 0x80 // Force Output Compare for channel A
|
||||
TCCR1C_FOC1B = 0x40 // Force Output Compare for channel B
|
||||
TCCR1C_FOC1C = 0x20 // Force Output Compare for channel C
|
||||
|
||||
// TCCR3A: Timer/Counter3 Control Register A
|
||||
TCCR3A_COM3A = 0xc0 // Compare Output Mode 3A, bits
|
||||
TCCR3A_COM3B = 0x30 // Compare Output Mode 3B, bits
|
||||
TCCR3A_COM3C = 0xc // Compare Output Mode 3C, bits
|
||||
TCCR3A_WGM3 = 0x3 // Waveform Generation Mode Bits
|
||||
|
||||
// TCCR3B: Timer/Counter3 Control Register B
|
||||
TCCR3B_ICNC3 = 0x80 // Input Capture 3 Noise Canceler
|
||||
TCCR3B_ICES3 = 0x40 // Input Capture 3 Edge Select
|
||||
TCCR3B_WGM3 = 0x18 // Waveform Generation Mode
|
||||
TCCR3B_CS3 = 0x7 // Clock Select3 bits
|
||||
|
||||
// TCCR3C: Timer/Counter3 Control Register C
|
||||
TCCR3C_FOC3A = 0x80 // Force Output Compare for channel A
|
||||
TCCR3C_FOC3B = 0x40 // Force Output Compare for channel B
|
||||
TCCR3C_FOC3C = 0x20 // Force Output Compare for channel C
|
||||
)
|
||||
|
||||
// Bitfields for TC8: Timer/Counter, 8-bit
|
||||
const (
|
||||
// TCCR2: Timer/Counter Control Register
|
||||
TCCR2_FOC2 = 0x80 // Force Output Compare
|
||||
TCCR2_WGM20 = 0x40 // Wafeform Generation Mode
|
||||
TCCR2_COM2 = 0x30 // Compare Match Output Mode
|
||||
TCCR2_WGM21 = 0x8 // Waveform Generation Mode
|
||||
TCCR2_CS2 = 0x7 // Clock Select
|
||||
)
|
||||
|
||||
// Bitfields for WDT: Watchdog Timer
|
||||
const (
|
||||
// WDTCR: Watchdog Timer Control Register
|
||||
WDTCR_WDCE = 0x10 // Watchdog Change Enable
|
||||
WDTCR_WDE = 0x8 // Watch Dog Enable
|
||||
WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits
|
||||
)
|
||||
|
||||
// Bitfields for ADC: Analog-to-Digital Converter
|
||||
const (
|
||||
// ADMUX: The ADC multiplexer Selection Register
|
||||
ADMUX_REFS = 0xc0 // Reference Selection Bits
|
||||
ADMUX_ADLAR = 0x20 // Left Adjust Result
|
||||
ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits
|
||||
|
||||
// ADCSRA: The ADC Control and Status register
|
||||
ADCSRA_ADEN = 0x80 // ADC Enable
|
||||
ADCSRA_ADSC = 0x40 // ADC Start Conversion
|
||||
ADCSRA_ADFR = 0x20 // ADC Free Running Select
|
||||
ADCSRA_ADIF = 0x10 // ADC Interrupt Flag
|
||||
ADCSRA_ADIE = 0x8 // ADC Interrupt Enable
|
||||
ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits
|
||||
)
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from ATmega128A.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x20000;
|
||||
__ram_size = 0x1000;
|
||||
__num_isrs = 35;
|
||||
Различия файлов не показаны, т.к. их слишком много
Показать различия
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from ATmega128RFA1.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x20000;
|
||||
__ram_size = 0x4000;
|
||||
__num_isrs = 72;
|
||||
Различия файлов не показаны, т.к. их слишком много
Показать различия
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from ATmega128RFR2.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x20000;
|
||||
__ram_size = 0x4000;
|
||||
__num_isrs = 71;
|
||||
|
|
@ -1,491 +0,0 @@
|
|||
// Automatically generated file. DO NOT EDIT.
|
||||
// Generated by gen-device.py from ATmega16.atdf, see http://packs.download.atmel.com/
|
||||
|
||||
// +build avr,atmega16
|
||||
|
||||
// Device information for the ATmega16.
|
||||
//
|
||||
package avr
|
||||
|
||||
// Magic type name for the compiler.
|
||||
type __reg uint8
|
||||
|
||||
// Export this magic type name.
|
||||
type RegValue = __reg
|
||||
|
||||
// Some information about this device.
|
||||
const (
|
||||
DEVICE = "ATmega16"
|
||||
ARCH = "AVR8"
|
||||
FAMILY = "megaAVR"
|
||||
)
|
||||
|
||||
// Interrupts
|
||||
const (
|
||||
IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset
|
||||
IRQ_INT0 = 1 // External Interrupt Request 0
|
||||
IRQ_INT1 = 2 // External Interrupt Request 1
|
||||
IRQ_TIMER2_COMP = 3 // Timer/Counter2 Compare Match
|
||||
IRQ_TIMER2_OVF = 4 // Timer/Counter2 Overflow
|
||||
IRQ_TIMER1_CAPT = 5 // Timer/Counter1 Capture Event
|
||||
IRQ_TIMER1_COMPA = 6 // Timer/Counter1 Compare Match A
|
||||
IRQ_TIMER1_COMPB = 7 // Timer/Counter1 Compare Match B
|
||||
IRQ_TIMER1_OVF = 8 // Timer/Counter1 Overflow
|
||||
IRQ_TIMER0_OVF = 9 // Timer/Counter0 Overflow
|
||||
IRQ_SPI_STC = 10 // Serial Transfer Complete
|
||||
IRQ_USART_RXC = 11 // USART, Rx Complete
|
||||
IRQ_USART_UDRE = 12 // USART Data Register Empty
|
||||
IRQ_USART_TXC = 13 // USART, Tx Complete
|
||||
IRQ_ADC = 14 // ADC Conversion Complete
|
||||
IRQ_EE_RDY = 15 // EEPROM Ready
|
||||
IRQ_ANA_COMP = 16 // Analog Comparator
|
||||
IRQ_TWI = 17 // 2-wire Serial Interface
|
||||
IRQ_INT2 = 18 // External Interrupt Request 2
|
||||
IRQ_TIMER0_COMP = 19 // Timer/Counter0 Compare Match
|
||||
IRQ_SPM_RDY = 20 // Store Program Memory Ready
|
||||
IRQ_max = 20 // Highest interrupt number on this device.
|
||||
)
|
||||
|
||||
// Peripherals
|
||||
var (
|
||||
// Fuses
|
||||
FUSE = struct {
|
||||
HIGH __reg
|
||||
LOW __reg
|
||||
}{
|
||||
HIGH: 0x1,
|
||||
LOW: 0x0,
|
||||
}
|
||||
|
||||
// Lockbits
|
||||
LOCKBIT = struct {
|
||||
LOCKBIT __reg
|
||||
}{
|
||||
LOCKBIT: 0x0,
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit
|
||||
TC8 = struct {
|
||||
TCCR0 __reg
|
||||
TCNT0 __reg
|
||||
OCR0 __reg
|
||||
}{
|
||||
TCCR0: 0x53, // Timer/Counter Control Register
|
||||
TCNT0: 0x52, // Timer/Counter Register
|
||||
OCR0: 0x5c, // Output Compare Register
|
||||
}
|
||||
|
||||
// Timer/Counter, 16-bit
|
||||
TC16 = struct {
|
||||
TCCR1A __reg
|
||||
TCCR1B __reg
|
||||
TCNT1L __reg
|
||||
TCNT1H __reg
|
||||
OCR1AL __reg
|
||||
OCR1AH __reg
|
||||
OCR1BL __reg
|
||||
OCR1BH __reg
|
||||
ICR1L __reg
|
||||
ICR1H __reg
|
||||
}{
|
||||
TCCR1A: 0x4f, // Timer/Counter1 Control Register A
|
||||
TCCR1B: 0x4e, // Timer/Counter1 Control Register B
|
||||
TCNT1L: 0x4c, // Timer/Counter1 Bytes
|
||||
TCNT1H: 0x4c, // Timer/Counter1 Bytes
|
||||
OCR1AL: 0x4a, // Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1AH: 0x4a, // Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1BL: 0x48, // Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1BH: 0x48, // Timer/Counter1 Output Compare Register Bytes
|
||||
ICR1L: 0x46, // Timer/Counter1 Input Capture Register Bytes
|
||||
ICR1H: 0x46, // Timer/Counter1 Input Capture Register Bytes
|
||||
}
|
||||
|
||||
// External Interrupts
|
||||
EXINT = struct {
|
||||
GICR __reg
|
||||
GIFR __reg
|
||||
}{
|
||||
GICR: 0x5b, // General Interrupt Control Register
|
||||
GIFR: 0x5a, // General Interrupt Flag Register
|
||||
}
|
||||
|
||||
// EEPROM
|
||||
EEPROM = struct {
|
||||
EEARL __reg
|
||||
EEARH __reg
|
||||
EEDR __reg
|
||||
EECR __reg
|
||||
}{
|
||||
EEARL: 0x3e, // EEPROM Address Register Bytes
|
||||
EEARH: 0x3e, // EEPROM Address Register Bytes
|
||||
EEDR: 0x3d, // EEPROM Data Register
|
||||
EECR: 0x3c, // EEPROM Control Register
|
||||
}
|
||||
|
||||
// CPU Registers
|
||||
CPU = struct {
|
||||
SREG __reg
|
||||
SPL __reg
|
||||
SPH __reg
|
||||
OSCCAL __reg
|
||||
}{
|
||||
SREG: 0x5f, // Status Register
|
||||
SPL: 0x5d, // Stack Pointer
|
||||
SPH: 0x5d, // Stack Pointer
|
||||
OSCCAL: 0x51, // Oscillator Calibration Value
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit Async
|
||||
TC8_ASYNC = struct {
|
||||
TCCR2 __reg
|
||||
TCNT2 __reg
|
||||
OCR2 __reg
|
||||
ASSR __reg
|
||||
}{
|
||||
TCCR2: 0x45, // Timer/Counter2 Control Register
|
||||
TCNT2: 0x44, // Timer/Counter2
|
||||
OCR2: 0x43, // Timer/Counter2 Output Compare Register
|
||||
ASSR: 0x42, // Asynchronous Status Register
|
||||
}
|
||||
|
||||
// Serial Peripheral Interface
|
||||
SPI = struct {
|
||||
SPDR __reg
|
||||
SPSR __reg
|
||||
SPCR __reg
|
||||
}{
|
||||
SPDR: 0x2f, // SPI Data Register
|
||||
SPSR: 0x2e, // SPI Status Register
|
||||
SPCR: 0x2d, // SPI Control Register
|
||||
}
|
||||
|
||||
// USART
|
||||
USART = struct {
|
||||
UDR __reg
|
||||
UCSRA __reg
|
||||
UCSRB __reg
|
||||
UCSRC __reg
|
||||
UBRRH __reg
|
||||
UBRRL __reg
|
||||
}{
|
||||
UDR: 0x2c, // USART I/O Data Register
|
||||
UCSRA: 0x2b, // USART Control and Status Register A
|
||||
UCSRB: 0x2a, // USART Control and Status Register B
|
||||
UCSRC: 0x40, // USART Control and Status Register C
|
||||
UBRRH: 0x40, // USART Baud Rate Register Hight Byte
|
||||
UBRRL: 0x29, // USART Baud Rate Register Low Byte
|
||||
}
|
||||
|
||||
// Two Wire Serial Interface
|
||||
TWI = struct {
|
||||
TWBR __reg
|
||||
TWCR __reg
|
||||
TWSR __reg
|
||||
TWDR __reg
|
||||
TWAR __reg
|
||||
}{
|
||||
TWBR: 0x20, // TWI Bit Rate register
|
||||
TWCR: 0x56, // TWI Control Register
|
||||
TWSR: 0x21, // TWI Status Register
|
||||
TWDR: 0x23, // TWI Data register
|
||||
TWAR: 0x22, // TWI (Slave) Address register
|
||||
}
|
||||
|
||||
// Analog Comparator
|
||||
AC = struct {
|
||||
ACSR __reg
|
||||
}{
|
||||
ACSR: 0x28, // Analog Comparator Control And Status Register
|
||||
}
|
||||
|
||||
// Analog-to-Digital Converter
|
||||
ADC = struct {
|
||||
ADMUX __reg
|
||||
ADCSRA __reg
|
||||
ADCL __reg
|
||||
ADCH __reg
|
||||
}{
|
||||
ADMUX: 0x27, // The ADC multiplexer Selection Register
|
||||
ADCSRA: 0x26, // The ADC Control and Status register
|
||||
ADCL: 0x24, // ADC Data Register Bytes
|
||||
ADCH: 0x24, // ADC Data Register Bytes
|
||||
}
|
||||
|
||||
// JTAG Interface
|
||||
JTAG = struct {
|
||||
OCDR __reg
|
||||
}{
|
||||
OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory
|
||||
}
|
||||
|
||||
// Bootloader
|
||||
BOOT_LOAD = struct {
|
||||
SPMCSR __reg
|
||||
}{
|
||||
SPMCSR: 0x57, // Store Program Memory Control Register
|
||||
}
|
||||
|
||||
// I/O Port
|
||||
PORT = struct {
|
||||
PORTA __reg
|
||||
DDRA __reg
|
||||
PINA __reg
|
||||
PORTB __reg
|
||||
DDRB __reg
|
||||
PINB __reg
|
||||
PORTC __reg
|
||||
DDRC __reg
|
||||
PINC __reg
|
||||
PORTD __reg
|
||||
DDRD __reg
|
||||
PIND __reg
|
||||
}{
|
||||
PORTA: 0x3b, // Port A Data Register
|
||||
DDRA: 0x3a, // Port A Data Direction Register
|
||||
PINA: 0x39, // Port A Input Pins
|
||||
PORTB: 0x38, // Port B Data Register
|
||||
DDRB: 0x37, // Port B Data Direction Register
|
||||
PINB: 0x36, // Port B Input Pins
|
||||
PORTC: 0x35, // Port C Data Register
|
||||
DDRC: 0x34, // Port C Data Direction Register
|
||||
PINC: 0x33, // Port C Input Pins
|
||||
PORTD: 0x32, // Port D Data Register
|
||||
DDRD: 0x31, // Port D Data Direction Register
|
||||
PIND: 0x30, // Port D Input Pins
|
||||
}
|
||||
|
||||
// Watchdog Timer
|
||||
WDT = struct {
|
||||
WDTCR __reg
|
||||
}{
|
||||
WDTCR: 0x41, // Watchdog Timer Control Register
|
||||
}
|
||||
)
|
||||
|
||||
// Bitfields for FUSE: Fuses
|
||||
const (
|
||||
// HIGH
|
||||
HIGH_OCDEN = 0x80 // On-Chip Debug Enabled
|
||||
HIGH_JTAGEN = 0x40 // JTAG Interface Enabled
|
||||
HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled
|
||||
HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle
|
||||
HIGH_BOOTSZ = 0x6 // Select Boot Size
|
||||
HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled
|
||||
HIGH_CKOPT = 0x10 // CKOPT fuse (operation dependent of CKSEL fuses)
|
||||
|
||||
// LOW
|
||||
LOW_BODLEVEL = 0x80 // Brownout detector trigger level
|
||||
LOW_BODEN = 0x40 // Brown-out detection enabled
|
||||
LOW_SUT_CKSEL = 0x3f // Select Clock Source
|
||||
)
|
||||
|
||||
// Bitfields for LOCKBIT: Lockbits
|
||||
const (
|
||||
// LOCKBIT
|
||||
LOCKBIT_LB = 0x3 // Memory Lock
|
||||
LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode
|
||||
LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode
|
||||
)
|
||||
|
||||
// Bitfields for TC8: Timer/Counter, 8-bit
|
||||
const (
|
||||
// TCCR0: Timer/Counter Control Register
|
||||
TCCR0_FOC0 = 0x80 // Force Output Compare
|
||||
TCCR0_WGM00 = 0x40 // Waveform Generation Mode 0
|
||||
TCCR0_COM0 = 0x30 // Compare Match Output Modes
|
||||
TCCR0_WGM01 = 0x8 // Waveform Generation Mode 1
|
||||
TCCR0_CS0 = 0x7 // Clock Selects
|
||||
)
|
||||
|
||||
// Bitfields for TC16: Timer/Counter, 16-bit
|
||||
const (
|
||||
// TCCR1A: Timer/Counter1 Control Register A
|
||||
TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits
|
||||
TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits
|
||||
TCCR1A_FOC1A = 0x8 // Force Output Compare 1A
|
||||
TCCR1A_FOC1B = 0x4 // Force Output Compare 1B
|
||||
TCCR1A_WGM1 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TCCR1B: Timer/Counter1 Control Register B
|
||||
TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler
|
||||
TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select
|
||||
TCCR1B_WGM1 = 0x18 // Waveform Generation Mode
|
||||
TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1
|
||||
)
|
||||
|
||||
// Bitfields for EXINT: External Interrupts
|
||||
const (
|
||||
// GICR: General Interrupt Control Register
|
||||
GICR_INT0 = 0x40 // External Interrupt Request 0 Enable
|
||||
GICR_INT1 = 0x80 // External Interrupt Request 1 Enable
|
||||
GICR_INT2 = 0x20 // External Interrupt Request 2 Enable
|
||||
GICR_IVSEL = 0x2 // Interrupt Vector Select
|
||||
GICR_IVCE = 0x1 // Interrupt Vector Change Enable
|
||||
|
||||
// GIFR: General Interrupt Flag Register
|
||||
GIFR_INTF = 0xc0 // External Interrupt Flags
|
||||
GIFR_INTF2 = 0x20 // External Interrupt Flag 2
|
||||
)
|
||||
|
||||
// Bitfields for EEPROM: EEPROM
|
||||
const (
|
||||
// EECR: EEPROM Control Register
|
||||
EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable
|
||||
EECR_EEMWE = 0x4 // EEPROM Master Write Enable
|
||||
EECR_EEWE = 0x2 // EEPROM Write Enable
|
||||
EECR_EERE = 0x1 // EEPROM Read Enable
|
||||
)
|
||||
|
||||
// Bitfields for CPU: CPU Registers
|
||||
const (
|
||||
// SREG: Status Register
|
||||
SREG_I = 0x80 // Global Interrupt Enable
|
||||
SREG_T = 0x40 // Bit Copy Storage
|
||||
SREG_H = 0x20 // Half Carry Flag
|
||||
SREG_S = 0x10 // Sign Bit
|
||||
SREG_V = 0x8 // Two's Complement Overflow Flag
|
||||
SREG_N = 0x4 // Negative Flag
|
||||
SREG_Z = 0x2 // Zero Flag
|
||||
SREG_C = 0x1 // Carry Flag
|
||||
|
||||
// OSCCAL: Oscillator Calibration Value
|
||||
OSCCAL_OSCCAL = 0xff // Oscillator Calibration
|
||||
)
|
||||
|
||||
// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async
|
||||
const (
|
||||
// TCCR2: Timer/Counter2 Control Register
|
||||
TCCR2_FOC2 = 0x80 // Force Output Compare
|
||||
TCCR2_WGM20 = 0x40 // Waveform Genration Mode
|
||||
TCCR2_COM2 = 0x30 // Compare Output Mode bits
|
||||
TCCR2_WGM21 = 0x8 // Waveform Generation Mode
|
||||
TCCR2_CS2 = 0x7 // Clock Select bits
|
||||
|
||||
// ASSR: Asynchronous Status Register
|
||||
ASSR_AS2 = 0x8 // Asynchronous Timer/counter2
|
||||
ASSR_TCN2UB = 0x4 // Timer/Counter2 Update Busy
|
||||
ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy
|
||||
ASSR_TCR2UB = 0x1 // Timer/counter Control Register2 Update Busy
|
||||
)
|
||||
|
||||
// Bitfields for SPI: Serial Peripheral Interface
|
||||
const (
|
||||
// SPSR: SPI Status Register
|
||||
SPSR_SPIF = 0x80 // SPI Interrupt Flag
|
||||
SPSR_WCOL = 0x40 // Write Collision Flag
|
||||
SPSR_SPI2X = 0x1 // Double SPI Speed Bit
|
||||
|
||||
// SPCR: SPI Control Register
|
||||
SPCR_SPIE = 0x80 // SPI Interrupt Enable
|
||||
SPCR_SPE = 0x40 // SPI Enable
|
||||
SPCR_DORD = 0x20 // Data Order
|
||||
SPCR_MSTR = 0x10 // Master/Slave Select
|
||||
SPCR_CPOL = 0x8 // Clock polarity
|
||||
SPCR_CPHA = 0x4 // Clock Phase
|
||||
SPCR_SPR = 0x3 // SPI Clock Rate Selects
|
||||
)
|
||||
|
||||
// Bitfields for USART: USART
|
||||
const (
|
||||
// UCSRA: USART Control and Status Register A
|
||||
UCSRA_RXC = 0x80 // USART Receive Complete
|
||||
UCSRA_TXC = 0x40 // USART Transmitt Complete
|
||||
UCSRA_UDRE = 0x20 // USART Data Register Empty
|
||||
UCSRA_FE = 0x10 // Framing Error
|
||||
UCSRA_DOR = 0x8 // Data overRun
|
||||
UCSRA_UPE = 0x4 // Parity Error
|
||||
UCSRA_U2X = 0x2 // Double the USART transmission speed
|
||||
UCSRA_MPCM = 0x1 // Multi-processor Communication Mode
|
||||
|
||||
// UCSRB: USART Control and Status Register B
|
||||
UCSRB_RXCIE = 0x80 // RX Complete Interrupt Enable
|
||||
UCSRB_TXCIE = 0x40 // TX Complete Interrupt Enable
|
||||
UCSRB_UDRIE = 0x20 // USART Data register Empty Interrupt Enable
|
||||
UCSRB_RXEN = 0x10 // Receiver Enable
|
||||
UCSRB_TXEN = 0x8 // Transmitter Enable
|
||||
UCSRB_UCSZ2 = 0x4 // Character Size
|
||||
UCSRB_RXB8 = 0x2 // Receive Data Bit 8
|
||||
UCSRB_TXB8 = 0x1 // Transmit Data Bit 8
|
||||
|
||||
// UCSRC: USART Control and Status Register C
|
||||
UCSRC_URSEL = 0x80 // Register Select
|
||||
UCSRC_UMSEL = 0x40 // USART Mode Select
|
||||
UCSRC_UPM = 0x30 // Parity Mode Bits
|
||||
UCSRC_USBS = 0x8 // Stop Bit Select
|
||||
UCSRC_UCSZ = 0x6 // Character Size
|
||||
UCSRC_UCPOL = 0x1 // Clock Polarity
|
||||
)
|
||||
|
||||
// Bitfields for TWI: Two Wire Serial Interface
|
||||
const (
|
||||
// TWCR: TWI Control Register
|
||||
TWCR_TWINT = 0x80 // TWI Interrupt Flag
|
||||
TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit
|
||||
TWCR_TWSTA = 0x20 // TWI Start Condition Bit
|
||||
TWCR_TWSTO = 0x10 // TWI Stop Condition Bit
|
||||
TWCR_TWWC = 0x8 // TWI Write Collition Flag
|
||||
TWCR_TWEN = 0x4 // TWI Enable Bit
|
||||
TWCR_TWIE = 0x1 // TWI Interrupt Enable
|
||||
|
||||
// TWSR: TWI Status Register
|
||||
TWSR_TWS = 0xf8 // TWI Status
|
||||
TWSR_TWPS = 0x3 // TWI Prescaler
|
||||
|
||||
// TWAR: TWI (Slave) Address register
|
||||
TWAR_TWA = 0xfe // TWI (Slave) Address register Bits
|
||||
TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit
|
||||
)
|
||||
|
||||
// Bitfields for AC: Analog Comparator
|
||||
const (
|
||||
// ACSR: Analog Comparator Control And Status Register
|
||||
ACSR_ACD = 0x80 // Analog Comparator Disable
|
||||
ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select
|
||||
ACSR_ACO = 0x20 // Analog Compare Output
|
||||
ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag
|
||||
ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable
|
||||
ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable
|
||||
ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits
|
||||
)
|
||||
|
||||
// Bitfields for ADC: Analog-to-Digital Converter
|
||||
const (
|
||||
// ADMUX: The ADC multiplexer Selection Register
|
||||
ADMUX_REFS = 0xc0 // Reference Selection Bits
|
||||
ADMUX_ADLAR = 0x20 // Left Adjust Result
|
||||
ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits
|
||||
|
||||
// ADCSRA: The ADC Control and Status register
|
||||
ADCSRA_ADEN = 0x80 // ADC Enable
|
||||
ADCSRA_ADSC = 0x40 // ADC Start Conversion
|
||||
ADCSRA_ADATE = 0x20 // ADC Auto Trigger
|
||||
ADCSRA_ADIF = 0x10 // ADC Interrupt Flag
|
||||
ADCSRA_ADIE = 0x8 // ADC Interrupt Enable
|
||||
ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits
|
||||
)
|
||||
|
||||
// Bitfields for JTAG: JTAG Interface
|
||||
const (
|
||||
// OCDR: On-Chip Debug Related Register in I/O Memory
|
||||
OCDR_OCDR = 0xff // On-Chip Debug Register Bits
|
||||
)
|
||||
|
||||
// Bitfields for BOOT_LOAD: Bootloader
|
||||
const (
|
||||
// SPMCSR: Store Program Memory Control Register
|
||||
SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable
|
||||
SPMCSR_RWWSB = 0x40 // Read While Write Section Busy
|
||||
SPMCSR_RWWSRE = 0x10 // Read While Write section read enable
|
||||
SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set
|
||||
SPMCSR_PGWRT = 0x4 // Page Write
|
||||
SPMCSR_PGERS = 0x2 // Page Erase
|
||||
SPMCSR_SPMEN = 0x1 // Store Program Memory Enable
|
||||
)
|
||||
|
||||
// Bitfields for WDT: Watchdog Timer
|
||||
const (
|
||||
// WDTCR: Watchdog Timer Control Register
|
||||
WDTCR_WDTOE = 0x10 // RW
|
||||
WDTCR_WDE = 0x8 // Watch Dog Enable
|
||||
WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits
|
||||
)
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from ATmega16.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x4000;
|
||||
__ram_size = 0x400;
|
||||
__num_isrs = 21;
|
||||
|
|
@ -1,585 +0,0 @@
|
|||
// Automatically generated file. DO NOT EDIT.
|
||||
// Generated by gen-device.py from ATmega162.atdf, see http://packs.download.atmel.com/
|
||||
|
||||
// +build avr,atmega162
|
||||
|
||||
// Device information for the ATmega162.
|
||||
//
|
||||
package avr
|
||||
|
||||
// Magic type name for the compiler.
|
||||
type __reg uint8
|
||||
|
||||
// Export this magic type name.
|
||||
type RegValue = __reg
|
||||
|
||||
// Some information about this device.
|
||||
const (
|
||||
DEVICE = "ATmega162"
|
||||
ARCH = "AVR8"
|
||||
FAMILY = "megaAVR"
|
||||
)
|
||||
|
||||
// Interrupts
|
||||
const (
|
||||
IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet.
|
||||
IRQ_INT0 = 1 // External Interrupt Request 0
|
||||
IRQ_INT1 = 2 // External Interrupt Request 1
|
||||
IRQ_INT2 = 3 // External Interrupt Request 2
|
||||
IRQ_PCINT0 = 4 // Pin Change Interrupt Request 0
|
||||
IRQ_PCINT1 = 5 // Pin Change Interrupt Request 1
|
||||
IRQ_TIMER3_CAPT = 6 // Timer/Counter3 Capture Event
|
||||
IRQ_TIMER3_COMPA = 7 // Timer/Counter3 Compare Match A
|
||||
IRQ_TIMER3_COMPB = 8 // Timer/Counter3 Compare Match B
|
||||
IRQ_TIMER3_OVF = 9 // Timer/Counter3 Overflow
|
||||
IRQ_TIMER2_COMP = 10 // Timer/Counter2 Compare Match
|
||||
IRQ_TIMER2_OVF = 11 // Timer/Counter2 Overflow
|
||||
IRQ_TIMER1_CAPT = 12 // Timer/Counter1 Capture Event
|
||||
IRQ_TIMER1_COMPA = 13 // Timer/Counter1 Compare Match A
|
||||
IRQ_TIMER1_COMPB = 14 // Timer/Counter Compare Match B
|
||||
IRQ_TIMER1_OVF = 15 // Timer/Counter1 Overflow
|
||||
IRQ_TIMER0_COMP = 16 // Timer/Counter0 Compare Match
|
||||
IRQ_TIMER0_OVF = 17 // Timer/Counter0 Overflow
|
||||
IRQ_SPI_STC = 18 // SPI Serial Transfer Complete
|
||||
IRQ_USART0_RXC = 19 // USART0, Rx Complete
|
||||
IRQ_USART1_RXC = 20 // USART1, Rx Complete
|
||||
IRQ_USART0_UDRE = 21 // USART0 Data register Empty
|
||||
IRQ_USART1_UDRE = 22 // USART1, Data register Empty
|
||||
IRQ_USART0_TXC = 23 // USART0, Tx Complete
|
||||
IRQ_USART1_TXC = 24 // USART1, Tx Complete
|
||||
IRQ_EE_RDY = 25 // EEPROM Ready
|
||||
IRQ_ANA_COMP = 26 // Analog Comparator
|
||||
IRQ_SPM_RDY = 27 // Store Program Memory Read
|
||||
IRQ_max = 27 // Highest interrupt number on this device.
|
||||
)
|
||||
|
||||
// Peripherals
|
||||
var (
|
||||
// Fuses
|
||||
FUSE = struct {
|
||||
EXTENDED __reg
|
||||
HIGH __reg
|
||||
LOW __reg
|
||||
}{
|
||||
EXTENDED: 0x2,
|
||||
HIGH: 0x1,
|
||||
LOW: 0x0,
|
||||
}
|
||||
|
||||
// Lockbits
|
||||
LOCKBIT = struct {
|
||||
LOCKBIT __reg
|
||||
}{
|
||||
LOCKBIT: 0x0,
|
||||
}
|
||||
|
||||
// Timer/Counter, 16-bit
|
||||
TC16 = struct {
|
||||
TCCR1A __reg
|
||||
TCCR1B __reg
|
||||
TCNT1L __reg
|
||||
TCNT1H __reg
|
||||
OCR1AL __reg
|
||||
OCR1AH __reg
|
||||
OCR1BL __reg
|
||||
OCR1BH __reg
|
||||
ICR1L __reg
|
||||
ICR1H __reg
|
||||
ETIMSK __reg
|
||||
ETIFR __reg
|
||||
TCCR3A __reg
|
||||
TCCR3B __reg
|
||||
TCNT3L __reg
|
||||
TCNT3H __reg
|
||||
OCR3AL __reg
|
||||
OCR3AH __reg
|
||||
OCR3BL __reg
|
||||
OCR3BH __reg
|
||||
ICR3L __reg
|
||||
ICR3H __reg
|
||||
}{
|
||||
TCCR1A: 0x4f, // Timer/Counter1 Control Register A
|
||||
TCCR1B: 0x4e, // Timer/Counter1 Control Register B
|
||||
TCNT1L: 0x4c, // Timer/Counter1 Bytes
|
||||
TCNT1H: 0x4c, // Timer/Counter1 Bytes
|
||||
OCR1AL: 0x4a, // Timer/Counter1 Output Compare Register A Bytes
|
||||
OCR1AH: 0x4a, // Timer/Counter1 Output Compare Register A Bytes
|
||||
OCR1BL: 0x48, // Timer/Counter1 Output Compare Register B Bytes
|
||||
OCR1BH: 0x48, // Timer/Counter1 Output Compare Register B Bytes
|
||||
ICR1L: 0x44, // Timer/Counter1 Input Capture Register Bytes
|
||||
ICR1H: 0x44, // Timer/Counter1 Input Capture Register Bytes
|
||||
ETIMSK: 0x7d, // Extended Timer/Counter Interrupt Mask Register
|
||||
ETIFR: 0x7c, // Extended Timer/Counter Interrupt Flag register
|
||||
TCCR3A: 0x8b, // Timer/Counter3 Control Register A
|
||||
TCCR3B: 0x8a, // Timer/Counter3 Control Register B
|
||||
TCNT3L: 0x88, // Timer/Counter3 Bytes
|
||||
TCNT3H: 0x88, // Timer/Counter3 Bytes
|
||||
OCR3AL: 0x86, // Timer/Counter3 Output Compare Register A Bytes
|
||||
OCR3AH: 0x86, // Timer/Counter3 Output Compare Register A Bytes
|
||||
OCR3BL: 0x84, // Timer/Counte3 Output Compare Register B Bytes
|
||||
OCR3BH: 0x84, // Timer/Counte3 Output Compare Register B Bytes
|
||||
ICR3L: 0x80, // Timer/Counter3 Input Capture Register Bytes
|
||||
ICR3H: 0x80, // Timer/Counter3 Input Capture Register Bytes
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit Async
|
||||
TC8_ASYNC = struct {
|
||||
TCCR2 __reg
|
||||
TCNT2 __reg
|
||||
OCR2 __reg
|
||||
ASSR __reg
|
||||
}{
|
||||
TCCR2: 0x47, // Timer/Counter Control Register
|
||||
TCNT2: 0x43, // Timer/Counter Register
|
||||
OCR2: 0x42, // Output Compare Register
|
||||
ASSR: 0x46, // Asynchronous Status Register
|
||||
}
|
||||
|
||||
// Analog Comparator
|
||||
AC = struct {
|
||||
ACSR __reg
|
||||
}{
|
||||
ACSR: 0x28, // Analog Comparator Control And Status Register
|
||||
}
|
||||
|
||||
// USART
|
||||
USART = struct {
|
||||
UDR0 __reg
|
||||
UCSR0A __reg
|
||||
UCSR0B __reg
|
||||
UCSR0C __reg
|
||||
UBRR0H __reg
|
||||
UBRR0L __reg
|
||||
UDR1 __reg
|
||||
UCSR1A __reg
|
||||
UCSR1B __reg
|
||||
UCSR1C __reg
|
||||
UBRR1H __reg
|
||||
UBRR1L __reg
|
||||
}{
|
||||
UDR0: 0x2c, // USART I/O Data Register
|
||||
UCSR0A: 0x2b, // USART Control and Status Register A
|
||||
UCSR0B: 0x2a, // USART Control and Status Register B
|
||||
UCSR0C: 0x40, // USART Control and Status Register C
|
||||
UBRR0H: 0x40, // USART Baud Rate Register High Byte
|
||||
UBRR0L: 0x29, // USART Baud Rate Register Low Byte
|
||||
UDR1: 0x23, // USART I/O Data Register
|
||||
UCSR1A: 0x22, // USART Control and Status Register A
|
||||
UCSR1B: 0x21, // USART Control and Status Register B
|
||||
UCSR1C: 0x5c, // USART Control and Status Register C
|
||||
UBRR1H: 0x5c, // USART Baud Rate Register Highg Byte
|
||||
UBRR1L: 0x20, // USART Baud Rate Register Low Byte
|
||||
}
|
||||
|
||||
// Serial Peripheral Interface
|
||||
SPI = struct {
|
||||
SPCR __reg
|
||||
SPSR __reg
|
||||
SPDR __reg
|
||||
}{
|
||||
SPCR: 0x2d, // SPI Control Register
|
||||
SPSR: 0x2e, // SPI Status Register
|
||||
SPDR: 0x2f, // SPI Data Register
|
||||
}
|
||||
|
||||
// CPU Registers
|
||||
CPU = struct {
|
||||
SREG __reg
|
||||
SPL __reg
|
||||
SPH __reg
|
||||
OSCCAL __reg
|
||||
CLKPR __reg
|
||||
SFIOR __reg
|
||||
}{
|
||||
SREG: 0x5f, // Status Register
|
||||
SPL: 0x5d, // Stack Pointer
|
||||
SPH: 0x5d, // Stack Pointer
|
||||
OSCCAL: 0x24, // Oscillator Calibration Value
|
||||
CLKPR: 0x61, // Clock prescale register
|
||||
SFIOR: 0x50, // Special Function IO Register
|
||||
}
|
||||
|
||||
// JTAG Interface
|
||||
JTAG = struct {
|
||||
OCDR __reg
|
||||
}{
|
||||
OCDR: 0x24, // On-Chip Debug Related Register in I/O Memory
|
||||
}
|
||||
|
||||
// Bootloader
|
||||
BOOT_LOAD = struct {
|
||||
SPMCR __reg
|
||||
}{
|
||||
SPMCR: 0x57, // Store Program Memory Control Register
|
||||
}
|
||||
|
||||
// EEPROM
|
||||
EEPROM = struct {
|
||||
EEARL __reg
|
||||
EEARH __reg
|
||||
EEDR __reg
|
||||
EECR __reg
|
||||
}{
|
||||
EEARL: 0x3e, // EEPROM Address Register Bytes
|
||||
EEARH: 0x3e, // EEPROM Address Register Bytes
|
||||
EEDR: 0x3d, // EEPROM Data Register
|
||||
EECR: 0x3c, // EEPROM Control Register
|
||||
}
|
||||
|
||||
// I/O Port
|
||||
PORT = struct {
|
||||
PORTA __reg
|
||||
DDRA __reg
|
||||
PINA __reg
|
||||
PORTB __reg
|
||||
DDRB __reg
|
||||
PINB __reg
|
||||
PORTC __reg
|
||||
DDRC __reg
|
||||
PINC __reg
|
||||
PORTD __reg
|
||||
DDRD __reg
|
||||
PIND __reg
|
||||
PORTE __reg
|
||||
DDRE __reg
|
||||
PINE __reg
|
||||
}{
|
||||
PORTA: 0x3b, // Port A Data Register
|
||||
DDRA: 0x3a, // Port A Data Direction Register
|
||||
PINA: 0x39, // Port A Input Pins
|
||||
PORTB: 0x38, // Port B Data Register
|
||||
DDRB: 0x37, // Port B Data Direction Register
|
||||
PINB: 0x36, // Port B Input Pins
|
||||
PORTC: 0x35, // Port C Data Register
|
||||
DDRC: 0x34, // Port C Data Direction Register
|
||||
PINC: 0x33, // Port C Input Pins
|
||||
PORTD: 0x32, // Port D Data Register
|
||||
DDRD: 0x31, // Port D Data Direction Register
|
||||
PIND: 0x30, // Port D Input Pins
|
||||
PORTE: 0x27, // Data Register, Port E
|
||||
DDRE: 0x26, // Data Direction Register, Port E
|
||||
PINE: 0x25, // Input Pins, Port E
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit
|
||||
TC8 = struct {
|
||||
TCCR0 __reg
|
||||
TCNT0 __reg
|
||||
OCR0 __reg
|
||||
}{
|
||||
TCCR0: 0x53, // Timer/Counter 0 Control Register
|
||||
TCNT0: 0x52, // Timer/Counter 0 Register
|
||||
OCR0: 0x51, // Timer/Counter 0 Output Compare Register
|
||||
}
|
||||
|
||||
// Watchdog Timer
|
||||
WDT = struct {
|
||||
WDTCR __reg
|
||||
}{
|
||||
WDTCR: 0x41, // Watchdog Timer Control Register
|
||||
}
|
||||
|
||||
// External Interrupts
|
||||
EXINT = struct {
|
||||
GICR __reg
|
||||
GIFR __reg
|
||||
PCMSK1 __reg
|
||||
PCMSK0 __reg
|
||||
}{
|
||||
GICR: 0x5b, // General Interrupt Control Register
|
||||
GIFR: 0x5a, // General Interrupt Flag Register
|
||||
PCMSK1: 0x6c, // Pin Change Mask Register 1
|
||||
PCMSK0: 0x6b, // Pin Change Enable Mask
|
||||
}
|
||||
)
|
||||
|
||||
// Bitfields for FUSE: Fuses
|
||||
const (
|
||||
// EXTENDED
|
||||
EXTENDED_M161C = 0x10 // ATmega161 compability mode
|
||||
EXTENDED_BODLEVEL = 0xe // Brownout detector trigger level
|
||||
|
||||
// HIGH
|
||||
HIGH_OCDEN = 0x80 // On-Chip Debug Enabled
|
||||
HIGH_JTAGEN = 0x40 // JTAG Interface Enabled
|
||||
HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled
|
||||
HIGH_WDTON = 0x10 // Watchdog timer always on
|
||||
HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle
|
||||
HIGH_BOOTSZ = 0x6 // Select Boot Size
|
||||
HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled
|
||||
|
||||
// LOW
|
||||
LOW_CKDIV8 = 0x80 // Divide clock by 8 internally
|
||||
LOW_CKOUT = 0x40 // Clock output on PORTB0
|
||||
LOW_SUT_CKSEL = 0x3f // Select Clock Source
|
||||
)
|
||||
|
||||
// Bitfields for LOCKBIT: Lockbits
|
||||
const (
|
||||
// LOCKBIT
|
||||
LOCKBIT_LB = 0x3 // Memory Lock
|
||||
LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode
|
||||
LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode
|
||||
)
|
||||
|
||||
// Bitfields for TC16: Timer/Counter, 16-bit
|
||||
const (
|
||||
// TCCR1A: Timer/Counter1 Control Register A
|
||||
TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits
|
||||
TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits
|
||||
TCCR1A_FOC1A = 0x8 // Force Output Compare for Channel A
|
||||
TCCR1A_FOC1B = 0x4 // Force Output Compare for Channel B
|
||||
TCCR1A_WGM1 = 0x3 // Pulse Width Modulator Select Bits
|
||||
|
||||
// TCCR1B: Timer/Counter1 Control Register B
|
||||
TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler
|
||||
TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select
|
||||
TCCR1B_WGM1 = 0x18 // Pulse Width Modulator Select Bits
|
||||
TCCR1B_CS1 = 0x7 // Clock Select1 bits
|
||||
|
||||
// ETIMSK: Extended Timer/Counter Interrupt Mask Register
|
||||
ETIMSK_TICIE3 = 0x20 // Timer/Counter3 Input Capture Interrupt Enable
|
||||
ETIMSK_OCIE3A = 0x10 // Timer/Counter3 Output CompareA Match Interrupt Enable
|
||||
ETIMSK_OCIE3B = 0x8 // Timer/Counter3 Output CompareB Match Interrupt Enable
|
||||
ETIMSK_TOIE3 = 0x4 // Timer/Counter3 Overflow Interrupt Enable
|
||||
|
||||
// ETIFR: Extended Timer/Counter Interrupt Flag register
|
||||
ETIFR_ICF3 = 0x20 // Input Capture Flag 3
|
||||
ETIFR_OCF3A = 0x10 // Output Compare Flag 3A
|
||||
ETIFR_OCF3B = 0x8 // Output Compare Flag 3B
|
||||
ETIFR_TOV3 = 0x4 // Timer/Counter3 Overflow Flag
|
||||
|
||||
// TCCR3A: Timer/Counter3 Control Register A
|
||||
TCCR3A_COM3A = 0xc0 // Compare Output Mode 3A, bits
|
||||
TCCR3A_COM3B = 0x30 // Compare Output Mode 3B, bits
|
||||
TCCR3A_FOC3A = 0x8 // Force Output Compare for Channel A
|
||||
TCCR3A_FOC3B = 0x4 // Force Output Compare for Channel B
|
||||
TCCR3A_WGM3 = 0x3 // Pulse Width Modulator Select Bits
|
||||
|
||||
// TCCR3B: Timer/Counter3 Control Register B
|
||||
TCCR3B_ICNC3 = 0x80 // Input Capture 3 Noise Canceler
|
||||
TCCR3B_ICES3 = 0x40 // Input Capture 3 Edge Select
|
||||
TCCR3B_WGM3 = 0x18 // Pulse Width Modulator Select Bits
|
||||
TCCR3B_CS3 = 0x7 // Clock Select3 bits
|
||||
)
|
||||
|
||||
// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async
|
||||
const (
|
||||
// TCCR2: Timer/Counter Control Register
|
||||
TCCR2_FOC2 = 0x80 // Forde Output Compare
|
||||
TCCR2_WGM20 = 0x40 // Pulse Width Modulator Select Bit 0
|
||||
TCCR2_COM2 = 0x30 // Compare Match Output Mode
|
||||
TCCR2_WGM21 = 0x8 // Pulse Width Modulator Select Bit 1
|
||||
TCCR2_CS2 = 0x7 // Clock Select
|
||||
|
||||
// ASSR: Asynchronous Status Register
|
||||
ASSR_AS2 = 0x8 // Asynchronous Timer 2
|
||||
ASSR_TCN2UB = 0x4 // Timer/Counter2 Update Busy
|
||||
ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy
|
||||
ASSR_TCR2UB = 0x1 // Timer/Counter Control Register2 Update Busy
|
||||
)
|
||||
|
||||
// Bitfields for AC: Analog Comparator
|
||||
const (
|
||||
// ACSR: Analog Comparator Control And Status Register
|
||||
ACSR_ACD = 0x80 // Analog Comparator Disable
|
||||
ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select
|
||||
ACSR_ACO = 0x20 // Analog Compare Output
|
||||
ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag
|
||||
ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable
|
||||
ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable
|
||||
ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits
|
||||
)
|
||||
|
||||
// Bitfields for USART: USART
|
||||
const (
|
||||
// UCSR0A: USART Control and Status Register A
|
||||
UCSR0A_RXC0 = 0x80 // USART Receive Complete
|
||||
UCSR0A_TXC0 = 0x40 // USART Transmitt Complete
|
||||
UCSR0A_UDRE0 = 0x20 // USART Data Register Empty
|
||||
UCSR0A_FE0 = 0x10 // Framing Error
|
||||
UCSR0A_DOR0 = 0x8 // Data overRun
|
||||
UCSR0A_UPE0 = 0x4 // Parity Error
|
||||
UCSR0A_U2X0 = 0x2 // Double the USART transmission speed
|
||||
UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode
|
||||
|
||||
// UCSR0B: USART Control and Status Register B
|
||||
UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable
|
||||
UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable
|
||||
UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable
|
||||
UCSR0B_RXEN0 = 0x10 // Receiver Enable
|
||||
UCSR0B_TXEN0 = 0x8 // Transmitter Enable
|
||||
UCSR0B_UCSZ02 = 0x4 // Character Size
|
||||
UCSR0B_RXB80 = 0x2 // Receive Data Bit 8
|
||||
UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8
|
||||
|
||||
// UCSR0C: USART Control and Status Register C
|
||||
UCSR0C_URSEL0 = 0x80 // Register Select
|
||||
UCSR0C_UMSEL0 = 0x40 // USART Mode Select
|
||||
UCSR0C_UPM0 = 0x30 // Parity Mode Bits
|
||||
UCSR0C_USBS0 = 0x8 // Stop Bit Select
|
||||
UCSR0C_UCSZ0 = 0x6 // Character Size
|
||||
UCSR0C_UCPOL0 = 0x1 // Clock Polarity
|
||||
|
||||
// UBRR0H: USART Baud Rate Register High Byte
|
||||
UBRR0H_URSEL0 = 0x80 // Register Select
|
||||
UBRR0H_UBRR0 = 0xf // USART Baud Rate Register High bits
|
||||
|
||||
// UBRR0L: USART Baud Rate Register Low Byte
|
||||
UBRR0L_UBRR0 = 0xff // USART Baud Rate Register Low bits
|
||||
|
||||
// UCSR1A: USART Control and Status Register A
|
||||
UCSR1A_RXC1 = 0x80 // USART Receive Complete
|
||||
UCSR1A_TXC1 = 0x40 // USART Transmitt Complete
|
||||
UCSR1A_UDRE1 = 0x20 // USART Data Register Empty
|
||||
UCSR1A_FE1 = 0x10 // Framing Error
|
||||
UCSR1A_DOR1 = 0x8 // Data overRun
|
||||
UCSR1A_UPE1 = 0x4 // Parity Error
|
||||
UCSR1A_U2X1 = 0x2 // Double the USART transmission speed
|
||||
UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode
|
||||
|
||||
// UCSR1B: USART Control and Status Register B
|
||||
UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable
|
||||
UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable
|
||||
UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable
|
||||
UCSR1B_RXEN1 = 0x10 // Receiver Enable
|
||||
UCSR1B_TXEN1 = 0x8 // Transmitter Enable
|
||||
UCSR1B_UCSZ12 = 0x4 // Character Size
|
||||
UCSR1B_RXB81 = 0x2 // Receive Data Bit 8
|
||||
UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8
|
||||
|
||||
// UCSR1C: USART Control and Status Register C
|
||||
UCSR1C_URSEL1 = 0x80 // Register Select
|
||||
UCSR1C_UMSEL1 = 0x40 // USART Mode Select
|
||||
UCSR1C_UPM1 = 0x30 // Parity Mode Bits
|
||||
UCSR1C_USBS1 = 0x8 // Stop Bit Select
|
||||
UCSR1C_UCSZ1 = 0x6 // Character Size
|
||||
UCSR1C_UCPOL1 = 0x1 // Clock Polarity
|
||||
|
||||
// UBRR1H: USART Baud Rate Register Highg Byte
|
||||
UBRR1H_URSEL0 = 0x80 // Register Select
|
||||
UBRR1H_UBRR1 = 0xf // USART Baud Rate Register High bits
|
||||
|
||||
// UBRR1L: USART Baud Rate Register Low Byte
|
||||
UBRR1L_UBRR1 = 0xff // USART Baud Rate Register Low bits
|
||||
)
|
||||
|
||||
// Bitfields for SPI: Serial Peripheral Interface
|
||||
const (
|
||||
// SPCR: SPI Control Register
|
||||
SPCR_SPIE = 0x80 // SPI Interrupt Enable
|
||||
SPCR_SPE = 0x40 // SPI Enable
|
||||
SPCR_DORD = 0x20 // Data Order
|
||||
SPCR_MSTR = 0x10 // Master/Slave Select
|
||||
SPCR_CPOL = 0x8 // Clock polarity
|
||||
SPCR_CPHA = 0x4 // Clock Phase
|
||||
SPCR_SPR = 0x3 // SPI Clock Rate Selects
|
||||
|
||||
// SPSR: SPI Status Register
|
||||
SPSR_SPIF = 0x80 // SPI Interrupt Flag
|
||||
SPSR_WCOL = 0x40 // Write Collision Flag
|
||||
SPSR_SPI2X = 0x1 // Double SPI Speed Bit
|
||||
)
|
||||
|
||||
// Bitfields for CPU: CPU Registers
|
||||
const (
|
||||
// SREG: Status Register
|
||||
SREG_I = 0x80 // Global Interrupt Enable
|
||||
SREG_T = 0x40 // Bit Copy Storage
|
||||
SREG_H = 0x20 // Half Carry Flag
|
||||
SREG_S = 0x10 // Sign Bit
|
||||
SREG_V = 0x8 // Two's Complement Overflow Flag
|
||||
SREG_N = 0x4 // Negative Flag
|
||||
SREG_Z = 0x2 // Zero Flag
|
||||
SREG_C = 0x1 // Carry Flag
|
||||
|
||||
// OSCCAL: Oscillator Calibration Value
|
||||
OSCCAL_OSCCAL = 0xff // Oscillator Calibration
|
||||
|
||||
// CLKPR: Clock prescale register
|
||||
CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable
|
||||
CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits
|
||||
|
||||
// SFIOR: Special Function IO Register
|
||||
SFIOR_TSM = 0x80 // Timer/Counter Synchronization Mode
|
||||
SFIOR_XMBK = 0x40 // External Memory Bus Keeper Enable
|
||||
SFIOR_XMM = 0x38 // External Memory High Mask Bits
|
||||
SFIOR_PUD = 0x4 // Pull-up Disable
|
||||
SFIOR_PSR2 = 0x2 // Prescaler Reset Timer/Counter2
|
||||
SFIOR_PSR310 = 0x1 // Prescaler Reset Timer/Counter3, Timer/Counter1 and Timer/Counter0
|
||||
)
|
||||
|
||||
// Bitfields for JTAG: JTAG Interface
|
||||
const (
|
||||
// OCDR: On-Chip Debug Related Register in I/O Memory
|
||||
OCDR_OCDR = 0xff // On-Chip Debug Register Bits
|
||||
)
|
||||
|
||||
// Bitfields for BOOT_LOAD: Bootloader
|
||||
const (
|
||||
// SPMCR: Store Program Memory Control Register
|
||||
SPMCR_SPMIE = 0x80 // SPM Interrupt Enable
|
||||
SPMCR_RWWSB = 0x40 // Read While Write Section Busy
|
||||
SPMCR_RWWSRE = 0x10 // Read While Write secion read enable
|
||||
SPMCR_BLBSET = 0x8 // Boot Lock Bit Set
|
||||
SPMCR_PGWRT = 0x4 // Page Write
|
||||
SPMCR_PGERS = 0x2 // Page Erase
|
||||
SPMCR_SPMEN = 0x1 // Store Program Memory Enable
|
||||
)
|
||||
|
||||
// Bitfields for EEPROM: EEPROM
|
||||
const (
|
||||
// EEARL: EEPROM Address Register Bytes
|
||||
|
||||
// EEARH: EEPROM Address Register Bytes
|
||||
EEAR_EEAR = 0x1ff // EEPROM Address Register bits
|
||||
|
||||
// EEDR: EEPROM Data Register
|
||||
EEDR_EEDR = 0xff // EEPROM Data Register bits
|
||||
|
||||
// EECR: EEPROM Control Register
|
||||
EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable
|
||||
EECR_EEMWE = 0x4 // EEPROM Master Write Enable
|
||||
EECR_EEWE = 0x2 // EEPROM Write Enable
|
||||
EECR_EERE = 0x1 // EEPROM Read Enable
|
||||
)
|
||||
|
||||
// Bitfields for TC8: Timer/Counter, 8-bit
|
||||
const (
|
||||
// TCCR0: Timer/Counter 0 Control Register
|
||||
TCCR0_FOC0 = 0x80 // Force Output Compare
|
||||
TCCR0_WGM00 = 0x40 // Waveform Generation Mode 0
|
||||
TCCR0_COM0 = 0x30 // Compare Match Output Modes
|
||||
TCCR0_WGM01 = 0x8 // Waveform Generation Mode 1
|
||||
TCCR0_CS0 = 0x7 // Clock Selects
|
||||
)
|
||||
|
||||
// Bitfields for WDT: Watchdog Timer
|
||||
const (
|
||||
// WDTCR: Watchdog Timer Control Register
|
||||
WDTCR_WDCE = 0x10 // Watchdog Change Enable
|
||||
WDTCR_WDE = 0x8 // Watch Dog Enable
|
||||
WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits
|
||||
)
|
||||
|
||||
// Bitfields for EXINT: External Interrupts
|
||||
const (
|
||||
// GICR: General Interrupt Control Register
|
||||
GICR_INT0 = 0x40 // External Interrupt Request 0 Enable
|
||||
GICR_INT1 = 0x80 // External Interrupt Request 1 Enable
|
||||
GICR_INT2 = 0x20 // External Interrupt Request 2 Enable
|
||||
GICR_PCIE = 0x18 // Pin Change Interrupt Enables
|
||||
GICR_IVSEL = 0x2 // Interrupt Vector Select
|
||||
GICR_IVCE = 0x1 // Interrupt Vector Change Enable
|
||||
|
||||
// GIFR: General Interrupt Flag Register
|
||||
GIFR_INTF = 0xc0 // External Interrupt Flags
|
||||
GIFR_INTF2 = 0x20 // External Interrupt Flag 2
|
||||
GIFR_PCIF = 0x18 // Pin Change Interrupt Flags
|
||||
|
||||
// PCMSK1: Pin Change Mask Register 1
|
||||
PCMSK1_PCINT = 0xff // Pin Change Interrupt mask bits
|
||||
|
||||
// PCMSK0: Pin Change Enable Mask
|
||||
PCMSK0_PCINT = 0xff // Pin Change Interrupt mask bits
|
||||
)
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from ATmega162.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x4000;
|
||||
__ram_size = 0x400;
|
||||
__num_isrs = 28;
|
||||
|
|
@ -1,711 +0,0 @@
|
|||
// Automatically generated file. DO NOT EDIT.
|
||||
// Generated by gen-device.py from ATmega164A.atdf, see http://packs.download.atmel.com/
|
||||
|
||||
// +build avr,atmega164a
|
||||
|
||||
// Device information for the ATmega164A.
|
||||
//
|
||||
package avr
|
||||
|
||||
// Magic type name for the compiler.
|
||||
type __reg uint8
|
||||
|
||||
// Export this magic type name.
|
||||
type RegValue = __reg
|
||||
|
||||
// Some information about this device.
|
||||
const (
|
||||
DEVICE = "ATmega164A"
|
||||
ARCH = "AVR8"
|
||||
FAMILY = "megaAVR"
|
||||
)
|
||||
|
||||
// Interrupts
|
||||
const (
|
||||
IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet.
|
||||
IRQ_INT0 = 1 // External Interrupt Request 0
|
||||
IRQ_INT1 = 2 // External Interrupt Request 1
|
||||
IRQ_INT2 = 3 // External Interrupt Request 2
|
||||
IRQ_PCINT0 = 4 // Pin Change Interrupt Request 0
|
||||
IRQ_PCINT1 = 5 // Pin Change Interrupt Request 1
|
||||
IRQ_PCINT2 = 6 // Pin Change Interrupt Request 2
|
||||
IRQ_PCINT3 = 7 // Pin Change Interrupt Request 3
|
||||
IRQ_WDT = 8 // Watchdog Time-out Interrupt
|
||||
IRQ_TIMER2_COMPA = 9 // Timer/Counter2 Compare Match A
|
||||
IRQ_TIMER2_COMPB = 10 // Timer/Counter2 Compare Match B
|
||||
IRQ_TIMER2_OVF = 11 // Timer/Counter2 Overflow
|
||||
IRQ_TIMER1_CAPT = 12 // Timer/Counter1 Capture Event
|
||||
IRQ_TIMER1_COMPA = 13 // Timer/Counter1 Compare Match A
|
||||
IRQ_TIMER1_COMPB = 14 // Timer/Counter1 Compare Match B
|
||||
IRQ_TIMER1_OVF = 15 // Timer/Counter1 Overflow
|
||||
IRQ_TIMER0_COMPA = 16 // Timer/Counter0 Compare Match A
|
||||
IRQ_TIMER0_COMPB = 17 // Timer/Counter0 Compare Match B
|
||||
IRQ_TIMER0_OVF = 18 // Timer/Counter0 Overflow
|
||||
IRQ_SPI_STC = 19 // SPI Serial Transfer Complete
|
||||
IRQ_USART0_RX = 20 // USART0, Rx Complete
|
||||
IRQ_USART0_UDRE = 21 // USART0 Data register Empty
|
||||
IRQ_USART0_TX = 22 // USART0, Tx Complete
|
||||
IRQ_ANALOG_COMP = 23 // Analog Comparator
|
||||
IRQ_ADC = 24 // ADC Conversion Complete
|
||||
IRQ_EE_READY = 25 // EEPROM Ready
|
||||
IRQ_TWI = 26 // 2-wire Serial Interface
|
||||
IRQ_SPM_READY = 27 // Store Program Memory Read
|
||||
IRQ_USART1_RX = 28 // USART1 RX complete
|
||||
IRQ_USART1_UDRE = 29 // USART1 Data Register Empty
|
||||
IRQ_USART1_TX = 30 // USART1 TX complete
|
||||
IRQ_max = 30 // Highest interrupt number on this device.
|
||||
)
|
||||
|
||||
// Peripherals
|
||||
var (
|
||||
// Fuses
|
||||
FUSE = struct {
|
||||
EXTENDED __reg
|
||||
HIGH __reg
|
||||
LOW __reg
|
||||
}{
|
||||
EXTENDED: 0x2,
|
||||
HIGH: 0x1,
|
||||
LOW: 0x0,
|
||||
}
|
||||
|
||||
// Lockbits
|
||||
LOCKBIT = struct {
|
||||
LOCKBIT __reg
|
||||
}{
|
||||
LOCKBIT: 0x0,
|
||||
}
|
||||
|
||||
// Analog Comparator
|
||||
AC = struct {
|
||||
ACSR __reg
|
||||
DIDR1 __reg
|
||||
}{
|
||||
ACSR: 0x50, // Analog Comparator Control And Status Register
|
||||
DIDR1: 0x7f, // Digital Input Disable Register 1
|
||||
}
|
||||
|
||||
// USART
|
||||
USART = struct {
|
||||
UDR0 __reg
|
||||
UCSR0A __reg
|
||||
UCSR0B __reg
|
||||
UCSR0C __reg
|
||||
UBRR0L __reg
|
||||
UBRR0H __reg
|
||||
UDR1 __reg
|
||||
UCSR1A __reg
|
||||
UCSR1B __reg
|
||||
UCSR1C __reg
|
||||
UBRR1L __reg
|
||||
UBRR1H __reg
|
||||
}{
|
||||
UDR0: 0xc6, // USART I/O Data Register
|
||||
UCSR0A: 0xc0, // USART Control and Status Register A
|
||||
UCSR0B: 0xc1, // USART Control and Status Register B
|
||||
UCSR0C: 0xc2, // USART Control and Status Register C
|
||||
UBRR0L: 0xc4, // USART Baud Rate Register Bytes
|
||||
UBRR0H: 0xc4, // USART Baud Rate Register Bytes
|
||||
UDR1: 0xce, // USART I/O Data Register
|
||||
UCSR1A: 0xc8, // USART Control and Status Register A
|
||||
UCSR1B: 0xc9, // USART Control and Status Register B
|
||||
UCSR1C: 0xca, // USART Control and Status Register C
|
||||
UBRR1L: 0xcc, // USART Baud Rate Register Bytes
|
||||
UBRR1H: 0xcc, // USART Baud Rate Register Bytes
|
||||
}
|
||||
|
||||
// I/O Port
|
||||
PORT = struct {
|
||||
PORTA __reg
|
||||
DDRA __reg
|
||||
PINA __reg
|
||||
PORTB __reg
|
||||
DDRB __reg
|
||||
PINB __reg
|
||||
PORTC __reg
|
||||
DDRC __reg
|
||||
PINC __reg
|
||||
PORTD __reg
|
||||
DDRD __reg
|
||||
PIND __reg
|
||||
}{
|
||||
PORTA: 0x22, // Port A Data Register
|
||||
DDRA: 0x21, // Port A Data Direction Register
|
||||
PINA: 0x20, // Port A Input Pins
|
||||
PORTB: 0x25, // Port B Data Register
|
||||
DDRB: 0x24, // Port B Data Direction Register
|
||||
PINB: 0x23, // Port B Input Pins
|
||||
PORTC: 0x28, // Port C Data Register
|
||||
DDRC: 0x27, // Port C Data Direction Register
|
||||
PINC: 0x26, // Port C Input Pins
|
||||
PORTD: 0x2b, // Port D Data Register
|
||||
DDRD: 0x2a, // Port D Data Direction Register
|
||||
PIND: 0x29, // Port D Input Pins
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit
|
||||
TC8 = struct {
|
||||
OCR0B __reg
|
||||
OCR0A __reg
|
||||
TCNT0 __reg
|
||||
TCCR0B __reg
|
||||
TCCR0A __reg
|
||||
TIMSK0 __reg
|
||||
TIFR0 __reg
|
||||
}{
|
||||
OCR0B: 0x48, // Timer/Counter0 Output Compare Register
|
||||
OCR0A: 0x47, // Timer/Counter0 Output Compare Register
|
||||
TCNT0: 0x46, // Timer/Counter0
|
||||
TCCR0B: 0x45, // Timer/Counter Control Register B
|
||||
TCCR0A: 0x44, // Timer/Counter Control Register A
|
||||
TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register
|
||||
TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit Async
|
||||
TC8_ASYNC = struct {
|
||||
TIMSK2 __reg
|
||||
TIFR2 __reg
|
||||
TCCR2A __reg
|
||||
TCCR2B __reg
|
||||
TCNT2 __reg
|
||||
OCR2B __reg
|
||||
OCR2A __reg
|
||||
ASSR __reg
|
||||
}{
|
||||
TIMSK2: 0x70, // Timer/Counter Interrupt Mask register
|
||||
TIFR2: 0x37, // Timer/Counter Interrupt Flag Register
|
||||
TCCR2A: 0xb0, // Timer/Counter2 Control Register A
|
||||
TCCR2B: 0xb1, // Timer/Counter2 Control Register B
|
||||
TCNT2: 0xb2, // Timer/Counter2
|
||||
OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B
|
||||
OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A
|
||||
ASSR: 0xb6, // Asynchronous Status Register
|
||||
}
|
||||
|
||||
// Watchdog Timer
|
||||
WDT = struct {
|
||||
WDTCSR __reg
|
||||
}{
|
||||
WDTCSR: 0x60, // Watchdog Timer Control Register
|
||||
}
|
||||
|
||||
// JTAG Interface
|
||||
JTAG = struct {
|
||||
OCDR __reg
|
||||
}{
|
||||
OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory
|
||||
}
|
||||
|
||||
// Bootloader
|
||||
BOOT_LOAD = struct {
|
||||
SPMCSR __reg
|
||||
}{
|
||||
SPMCSR: 0x57, // Store Program Memory Control Register
|
||||
}
|
||||
|
||||
// External Interrupts
|
||||
EXINT = struct {
|
||||
EICRA __reg
|
||||
EIMSK __reg
|
||||
EIFR __reg
|
||||
PCMSK3 __reg
|
||||
PCMSK2 __reg
|
||||
PCMSK1 __reg
|
||||
PCMSK0 __reg
|
||||
PCIFR __reg
|
||||
PCICR __reg
|
||||
}{
|
||||
EICRA: 0x69, // External Interrupt Control Register A
|
||||
EIMSK: 0x3d, // External Interrupt Mask Register
|
||||
EIFR: 0x3c, // External Interrupt Flag Register
|
||||
PCMSK3: 0x73, // Pin Change Mask Register 3
|
||||
PCMSK2: 0x6d, // Pin Change Mask Register 2
|
||||
PCMSK1: 0x6c, // Pin Change Mask Register 1
|
||||
PCMSK0: 0x6b, // Pin Change Mask Register 0
|
||||
PCIFR: 0x3b, // Pin Change Interrupt Flag Register
|
||||
PCICR: 0x68, // Pin Change Interrupt Control Register
|
||||
}
|
||||
|
||||
// Analog-to-Digital Converter
|
||||
ADC = struct {
|
||||
ADMUX __reg
|
||||
ADCL __reg
|
||||
ADCH __reg
|
||||
ADCSRA __reg
|
||||
DIDR0 __reg
|
||||
}{
|
||||
ADMUX: 0x7c, // The ADC multiplexer Selection Register
|
||||
ADCL: 0x78, // ADC Data Register Bytes
|
||||
ADCH: 0x78, // ADC Data Register Bytes
|
||||
ADCSRA: 0x7a, // The ADC Control and Status register A
|
||||
DIDR0: 0x7e, // Digital Input Disable Register
|
||||
}
|
||||
|
||||
// Timer/Counter, 16-bit
|
||||
TC16 = struct {
|
||||
TIMSK1 __reg
|
||||
TIFR1 __reg
|
||||
TCCR1A __reg
|
||||
TCCR1B __reg
|
||||
TCCR1C __reg
|
||||
TCNT1L __reg
|
||||
TCNT1H __reg
|
||||
OCR1AL __reg
|
||||
OCR1AH __reg
|
||||
OCR1BL __reg
|
||||
OCR1BH __reg
|
||||
ICR1L __reg
|
||||
ICR1H __reg
|
||||
}{
|
||||
TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register
|
||||
TIFR1: 0x36, // Timer/Counter Interrupt Flag register
|
||||
TCCR1A: 0x80, // Timer/Counter1 Control Register A
|
||||
TCCR1B: 0x81, // Timer/Counter1 Control Register B
|
||||
TCCR1C: 0x82, // Timer/Counter1 Control Register C
|
||||
TCNT1L: 0x84, // Timer/Counter1 Bytes
|
||||
TCNT1H: 0x84, // Timer/Counter1 Bytes
|
||||
OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes
|
||||
OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes
|
||||
OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes
|
||||
OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes
|
||||
ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
}
|
||||
|
||||
// EEPROM
|
||||
EEPROM = struct {
|
||||
EEARL __reg
|
||||
EEARH __reg
|
||||
EEDR __reg
|
||||
EECR __reg
|
||||
}{
|
||||
EEARL: 0x41, // EEPROM Address Register Low Bytes
|
||||
EEARH: 0x41, // EEPROM Address Register Low Bytes
|
||||
EEDR: 0x40, // EEPROM Data Register
|
||||
EECR: 0x3f, // EEPROM Control Register
|
||||
}
|
||||
|
||||
// Serial Peripheral Interface
|
||||
SPI = struct {
|
||||
SPDR0 __reg
|
||||
SPSR0 __reg
|
||||
SPCR0 __reg
|
||||
}{
|
||||
SPDR0: 0x4e, // SPI Data Register
|
||||
SPSR0: 0x4d, // SPI Status Register
|
||||
SPCR0: 0x4c, // SPI Control Register
|
||||
}
|
||||
|
||||
// Two Wire Serial Interface
|
||||
TWI = struct {
|
||||
TWAMR __reg
|
||||
TWBR __reg
|
||||
TWCR __reg
|
||||
TWSR __reg
|
||||
TWDR __reg
|
||||
TWAR __reg
|
||||
}{
|
||||
TWAMR: 0xbd, // TWI (Slave) Address Mask Register
|
||||
TWBR: 0xb8, // TWI Bit Rate register
|
||||
TWCR: 0xbc, // TWI Control Register
|
||||
TWSR: 0xb9, // TWI Status Register
|
||||
TWDR: 0xbb, // TWI Data register
|
||||
TWAR: 0xba, // TWI (Slave) Address register
|
||||
}
|
||||
|
||||
// CPU Registers
|
||||
CPU = struct {
|
||||
SREG __reg
|
||||
SPL __reg
|
||||
SPH __reg
|
||||
OSCCAL __reg
|
||||
CLKPR __reg
|
||||
SMCR __reg
|
||||
GPIOR2 __reg
|
||||
GPIOR1 __reg
|
||||
GPIOR0 __reg
|
||||
PRR0 __reg
|
||||
}{
|
||||
SREG: 0x5f, // Status Register
|
||||
SPL: 0x5d, // Stack Pointer
|
||||
SPH: 0x5d, // Stack Pointer
|
||||
OSCCAL: 0x66, // Oscillator Calibration Value
|
||||
CLKPR: 0x61,
|
||||
SMCR: 0x53, // Sleep Mode Control Register
|
||||
GPIOR2: 0x4b, // General Purpose IO Register 2
|
||||
GPIOR1: 0x4a, // General Purpose IO Register 1
|
||||
GPIOR0: 0x3e, // General Purpose IO Register 0
|
||||
PRR0: 0x64, // Power Reduction Register0
|
||||
}
|
||||
)
|
||||
|
||||
// Bitfields for FUSE: Fuses
|
||||
const (
|
||||
// EXTENDED
|
||||
EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level
|
||||
|
||||
// HIGH
|
||||
HIGH_OCDEN = 0x80 // On-Chip Debug Enabled
|
||||
HIGH_JTAGEN = 0x40 // JTAG Interface Enabled
|
||||
HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled
|
||||
HIGH_WDTON = 0x10 // Watchdog timer always on
|
||||
HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle
|
||||
HIGH_BOOTSZ = 0x6 // Select Boot Size
|
||||
HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled
|
||||
|
||||
// LOW
|
||||
LOW_CKDIV8 = 0x80 // Divide clock by 8 internally
|
||||
LOW_CKOUT = 0x40 // Clock output on PORTB1
|
||||
LOW_SUT_CKSEL = 0x3f // Select Clock Source
|
||||
)
|
||||
|
||||
// Bitfields for LOCKBIT: Lockbits
|
||||
const (
|
||||
// LOCKBIT
|
||||
LOCKBIT_LB = 0x3 // Memory Lock
|
||||
LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode
|
||||
LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode
|
||||
)
|
||||
|
||||
// Bitfields for AC: Analog Comparator
|
||||
const (
|
||||
// ACSR: Analog Comparator Control And Status Register
|
||||
ACSR_ACD = 0x80 // Analog Comparator Disable
|
||||
ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select
|
||||
ACSR_ACO = 0x20 // Analog Compare Output
|
||||
ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag
|
||||
ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable
|
||||
ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable
|
||||
ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits
|
||||
|
||||
// DIDR1: Digital Input Disable Register 1
|
||||
DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable
|
||||
DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable
|
||||
)
|
||||
|
||||
// Bitfields for USART: USART
|
||||
const (
|
||||
// UCSR0A: USART Control and Status Register A
|
||||
UCSR0A_RXC0 = 0x80 // USART Receive Complete
|
||||
UCSR0A_TXC0 = 0x40 // USART Transmitt Complete
|
||||
UCSR0A_UDRE0 = 0x20 // USART Data Register Empty
|
||||
UCSR0A_FE0 = 0x10 // Framing Error
|
||||
UCSR0A_DOR0 = 0x8 // Data overRun
|
||||
UCSR0A_UPE0 = 0x4 // Parity Error
|
||||
UCSR0A_U2X0 = 0x2 // Double the USART transmission speed
|
||||
UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode
|
||||
|
||||
// UCSR0B: USART Control and Status Register B
|
||||
UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable
|
||||
UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable
|
||||
UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable
|
||||
UCSR0B_RXEN0 = 0x10 // Receiver Enable
|
||||
UCSR0B_TXEN0 = 0x8 // Transmitter Enable
|
||||
UCSR0B_UCSZ02 = 0x4 // Character Size
|
||||
UCSR0B_RXB80 = 0x2 // Receive Data Bit 8
|
||||
UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8
|
||||
|
||||
// UCSR0C: USART Control and Status Register C
|
||||
UCSR0C_UMSEL0 = 0xc0 // USART Mode Select
|
||||
UCSR0C_UPM0 = 0x30 // Parity Mode Bits
|
||||
UCSR0C_USBS0 = 0x8 // Stop Bit Select
|
||||
UCSR0C_UCSZ0 = 0x6 // Character Size
|
||||
UCSR0C_UCPOL0 = 0x1 // Clock Polarity
|
||||
|
||||
// UCSR1A: USART Control and Status Register A
|
||||
UCSR1A_RXC1 = 0x80 // USART Receive Complete
|
||||
UCSR1A_TXC1 = 0x40 // USART Transmitt Complete
|
||||
UCSR1A_UDRE1 = 0x20 // USART Data Register Empty
|
||||
UCSR1A_FE1 = 0x10 // Framing Error
|
||||
UCSR1A_DOR1 = 0x8 // Data overRun
|
||||
UCSR1A_UPE1 = 0x4 // Parity Error
|
||||
UCSR1A_U2X1 = 0x2 // Double the USART transmission speed
|
||||
UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode
|
||||
|
||||
// UCSR1B: USART Control and Status Register B
|
||||
UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable
|
||||
UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable
|
||||
UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable
|
||||
UCSR1B_RXEN1 = 0x10 // Receiver Enable
|
||||
UCSR1B_TXEN1 = 0x8 // Transmitter Enable
|
||||
UCSR1B_UCSZ12 = 0x4 // Character Size
|
||||
UCSR1B_RXB81 = 0x2 // Receive Data Bit 8
|
||||
UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8
|
||||
|
||||
// UCSR1C: USART Control and Status Register C
|
||||
UCSR1C_UMSEL1 = 0xc0 // USART Mode Select
|
||||
UCSR1C_UPM1 = 0x30 // Parity Mode Bits
|
||||
UCSR1C_USBS1 = 0x8 // Stop Bit Select
|
||||
UCSR1C_UCSZ1 = 0x6 // Character Size
|
||||
UCSR1C_UCPOL1 = 0x1 // Clock Polarity
|
||||
)
|
||||
|
||||
// Bitfields for TC8: Timer/Counter, 8-bit
|
||||
const (
|
||||
// TCCR0B: Timer/Counter Control Register B
|
||||
TCCR0B_FOC0A = 0x80 // Force Output Compare A
|
||||
TCCR0B_FOC0B = 0x40 // Force Output Compare B
|
||||
TCCR0B_WGM02 = 0x8
|
||||
TCCR0B_CS0 = 0x7 // Clock Select
|
||||
|
||||
// TCCR0A: Timer/Counter Control Register A
|
||||
TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode
|
||||
TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm
|
||||
TCCR0A_WGM0 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TIMSK0: Timer/Counter0 Interrupt Mask Register
|
||||
TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable
|
||||
TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable
|
||||
TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable
|
||||
|
||||
// TIFR0: Timer/Counter0 Interrupt Flag register
|
||||
TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B
|
||||
TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A
|
||||
TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag
|
||||
)
|
||||
|
||||
// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async
|
||||
const (
|
||||
// TIMSK2: Timer/Counter Interrupt Mask register
|
||||
TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable
|
||||
TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable
|
||||
TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable
|
||||
|
||||
// TIFR2: Timer/Counter Interrupt Flag Register
|
||||
TIFR2_OCF2B = 0x4 // Output Compare Flag 2B
|
||||
TIFR2_OCF2A = 0x2 // Output Compare Flag 2A
|
||||
TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag
|
||||
|
||||
// TCCR2A: Timer/Counter2 Control Register A
|
||||
TCCR2A_COM2A = 0xc0 // Compare Output Mode bits
|
||||
TCCR2A_COM2B = 0x30 // Compare Output Mode bits
|
||||
TCCR2A_WGM2 = 0x3 // Waveform Genration Mode
|
||||
|
||||
// TCCR2B: Timer/Counter2 Control Register B
|
||||
TCCR2B_FOC2A = 0x80 // Force Output Compare A
|
||||
TCCR2B_FOC2B = 0x40 // Force Output Compare B
|
||||
TCCR2B_WGM22 = 0x8 // Waveform Generation Mode
|
||||
TCCR2B_CS2 = 0x7 // Clock Select bits
|
||||
|
||||
// ASSR: Asynchronous Status Register
|
||||
ASSR_EXCLK = 0x40 // Enable External Clock Input
|
||||
ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2
|
||||
ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy
|
||||
ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy
|
||||
ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy
|
||||
ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy
|
||||
ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy
|
||||
)
|
||||
|
||||
// Bitfields for WDT: Watchdog Timer
|
||||
const (
|
||||
// WDTCSR: Watchdog Timer Control Register
|
||||
WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag
|
||||
WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable
|
||||
WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits
|
||||
WDTCSR_WDCE = 0x10 // Watchdog Change Enable
|
||||
WDTCSR_WDE = 0x8 // Watch Dog Enable
|
||||
)
|
||||
|
||||
// Bitfields for BOOT_LOAD: Bootloader
|
||||
const (
|
||||
// SPMCSR: Store Program Memory Control Register
|
||||
SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable
|
||||
SPMCSR_RWWSB = 0x40 // Read While Write Section Busy
|
||||
SPMCSR_SIGRD = 0x20 // Signature Row Read
|
||||
SPMCSR_RWWSRE = 0x10 // Read While Write section read enable
|
||||
SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set
|
||||
SPMCSR_PGWRT = 0x4 // Page Write
|
||||
SPMCSR_PGERS = 0x2 // Page Erase
|
||||
SPMCSR_SPMEN = 0x1 // Store Program Memory Enable
|
||||
)
|
||||
|
||||
// Bitfields for EXINT: External Interrupts
|
||||
const (
|
||||
// EICRA: External Interrupt Control Register A
|
||||
EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit
|
||||
EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit
|
||||
EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit
|
||||
|
||||
// EIMSK: External Interrupt Mask Register
|
||||
EIMSK_INT = 0x7 // External Interrupt Request 2 Enable
|
||||
|
||||
// EIFR: External Interrupt Flag Register
|
||||
EIFR_INTF = 0x7 // External Interrupt Flags
|
||||
|
||||
// PCMSK3: Pin Change Mask Register 3
|
||||
PCMSK3_PCINT = 0xff // Pin Change Enable Masks
|
||||
|
||||
// PCMSK2: Pin Change Mask Register 2
|
||||
PCMSK2_PCINT = 0xff // Pin Change Enable Masks
|
||||
|
||||
// PCMSK1: Pin Change Mask Register 1
|
||||
PCMSK1_PCINT = 0xff // Pin Change Enable Masks
|
||||
|
||||
// PCMSK0: Pin Change Mask Register 0
|
||||
PCMSK0_PCINT = 0xff // Pin Change Enable Masks
|
||||
|
||||
// PCIFR: Pin Change Interrupt Flag Register
|
||||
PCIFR_PCIF = 0xf // Pin Change Interrupt Flags
|
||||
|
||||
// PCICR: Pin Change Interrupt Control Register
|
||||
PCICR_PCIE = 0xf // Pin Change Interrupt Enables
|
||||
)
|
||||
|
||||
// Bitfields for ADC: Analog-to-Digital Converter
|
||||
const (
|
||||
// ADMUX: The ADC multiplexer Selection Register
|
||||
ADMUX_REFS = 0xc0 // Reference Selection Bits
|
||||
ADMUX_ADLAR = 0x20 // Left Adjust Result
|
||||
ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits
|
||||
|
||||
// ADCSRA: The ADC Control and Status register A
|
||||
ADCSRA_ADEN = 0x80 // ADC Enable
|
||||
ADCSRA_ADSC = 0x40 // ADC Start Conversion
|
||||
ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable
|
||||
ADCSRA_ADIF = 0x10 // ADC Interrupt Flag
|
||||
ADCSRA_ADIE = 0x8 // ADC Interrupt Enable
|
||||
ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits
|
||||
|
||||
// DIDR0: Digital Input Disable Register
|
||||
DIDR0_ADC7D = 0x80
|
||||
DIDR0_ADC6D = 0x40
|
||||
DIDR0_ADC5D = 0x20
|
||||
DIDR0_ADC4D = 0x10
|
||||
DIDR0_ADC3D = 0x8
|
||||
DIDR0_ADC2D = 0x4
|
||||
DIDR0_ADC1D = 0x2
|
||||
DIDR0_ADC0D = 0x1
|
||||
)
|
||||
|
||||
// Bitfields for TC16: Timer/Counter, 16-bit
|
||||
const (
|
||||
// TIMSK1: Timer/Counter1 Interrupt Mask Register
|
||||
TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable
|
||||
TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable
|
||||
TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable
|
||||
TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable
|
||||
|
||||
// TIFR1: Timer/Counter Interrupt Flag register
|
||||
TIFR1_ICF1 = 0x20 // Timer/Counter1 Input Capture Flag
|
||||
TIFR1_OCF1B = 0x4 // Timer/Counter1 Output Compare B Match Flag
|
||||
TIFR1_OCF1A = 0x2 // Timer/Counter1 Output Compare A Match Flag
|
||||
TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag
|
||||
|
||||
// TCCR1A: Timer/Counter1 Control Register A
|
||||
TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits
|
||||
TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits
|
||||
TCCR1A_WGM1 = 0x3 // Pulse Width Modulator Select Bits
|
||||
|
||||
// TCCR1B: Timer/Counter1 Control Register B
|
||||
TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler
|
||||
TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select
|
||||
TCCR1B_WGM1 = 0x18 // Waveform Generation Mode Bits
|
||||
TCCR1B_CS1 = 0x7 // Clock Select1 bits
|
||||
|
||||
// TCCR1C: Timer/Counter1 Control Register C
|
||||
TCCR1C_FOC1A = 0x80 // Force Output Compare for Channel A
|
||||
TCCR1C_FOC1B = 0x40 // Force Output Compare for Channel B
|
||||
)
|
||||
|
||||
// Bitfields for EEPROM: EEPROM
|
||||
const (
|
||||
// EECR: EEPROM Control Register
|
||||
EECR_EEPM = 0x30 // EEPROM Programming Mode Bits
|
||||
EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable
|
||||
EECR_EEMPE = 0x4 // EEPROM Master Write Enable
|
||||
EECR_EEPE = 0x2 // EEPROM Write Enable
|
||||
EECR_EERE = 0x1 // EEPROM Read Enable
|
||||
)
|
||||
|
||||
// Bitfields for SPI: Serial Peripheral Interface
|
||||
const (
|
||||
// SPSR0: SPI Status Register
|
||||
SPSR0_SPIF0 = 0x80 // SPI Interrupt Flag
|
||||
SPSR0_WCOL0 = 0x40 // Write Collision Flag
|
||||
SPSR0_SPI2X0 = 0x1 // Double SPI Speed Bit
|
||||
|
||||
// SPCR0: SPI Control Register
|
||||
SPCR0_SPIE0 = 0x80 // SPI Interrupt Enable
|
||||
SPCR0_SPE0 = 0x40 // SPI Enable
|
||||
SPCR0_DORD0 = 0x20 // Data Order
|
||||
SPCR0_MSTR0 = 0x10 // Master/Slave Select
|
||||
SPCR0_CPOL0 = 0x8 // Clock polarity
|
||||
SPCR0_CPHA0 = 0x4 // Clock Phase
|
||||
SPCR0_SPR01 = 0x2 // SPI Clock Rate Select 1
|
||||
SPCR0_SPR00 = 0x1 // SPI Clock Rate Select 0
|
||||
)
|
||||
|
||||
// Bitfields for TWI: Two Wire Serial Interface
|
||||
const (
|
||||
// TWAMR: TWI (Slave) Address Mask Register
|
||||
TWAMR_TWAM = 0xfe
|
||||
|
||||
// TWCR: TWI Control Register
|
||||
TWCR_TWINT = 0x80 // TWI Interrupt Flag
|
||||
TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit
|
||||
TWCR_TWSTA = 0x20 // TWI Start Condition Bit
|
||||
TWCR_TWSTO = 0x10 // TWI Stop Condition Bit
|
||||
TWCR_TWWC = 0x8 // TWI Write Collition Flag
|
||||
TWCR_TWEN = 0x4 // TWI Enable Bit
|
||||
TWCR_TWIE = 0x1 // TWI Interrupt Enable
|
||||
|
||||
// TWSR: TWI Status Register
|
||||
TWSR_TWS = 0xf8 // TWI Status
|
||||
TWSR_TWPS = 0x3 // TWI Prescaler
|
||||
|
||||
// TWAR: TWI (Slave) Address register
|
||||
TWAR_TWA = 0xfe // TWI (Slave) Address register Bits
|
||||
TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit
|
||||
)
|
||||
|
||||
// Bitfields for CPU: CPU Registers
|
||||
const (
|
||||
// SREG: Status Register
|
||||
SREG_I = 0x80 // Global Interrupt Enable
|
||||
SREG_T = 0x40 // Bit Copy Storage
|
||||
SREG_H = 0x20 // Half Carry Flag
|
||||
SREG_S = 0x10 // Sign Bit
|
||||
SREG_V = 0x8 // Two's Complement Overflow Flag
|
||||
SREG_N = 0x4 // Negative Flag
|
||||
SREG_Z = 0x2 // Zero Flag
|
||||
SREG_C = 0x1 // Carry Flag
|
||||
|
||||
// OSCCAL: Oscillator Calibration Value
|
||||
OSCCAL_OSCCAL = 0xff // Oscillator Calibration
|
||||
|
||||
// CLKPR
|
||||
CLKPR_CLKPCE = 0x80
|
||||
CLKPR_CLKPS = 0xf
|
||||
|
||||
// SMCR: Sleep Mode Control Register
|
||||
SMCR_SM = 0xe // Sleep Mode Select bits
|
||||
SMCR_SE = 0x1 // Sleep Enable
|
||||
|
||||
// GPIOR2: General Purpose IO Register 2
|
||||
GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis
|
||||
|
||||
// GPIOR1: General Purpose IO Register 1
|
||||
GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis
|
||||
|
||||
// GPIOR0: General Purpose IO Register 0
|
||||
GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7
|
||||
GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6
|
||||
GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5
|
||||
GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4
|
||||
GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3
|
||||
GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2
|
||||
GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1
|
||||
GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0
|
||||
|
||||
// PRR0: Power Reduction Register0
|
||||
PRR0_PRTWI = 0x80 // Power Reduction TWI
|
||||
PRR0_PRTIM2 = 0x40 // Power Reduction Timer/Counter2
|
||||
PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0
|
||||
PRR0_PRUSART1 = 0x10 // Power Reduction USART1
|
||||
PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1
|
||||
PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface
|
||||
PRR0_PRUSART0 = 0x2 // Power Reduction USART0
|
||||
PRR0_PRADC = 0x1 // Power Reduction ADC
|
||||
)
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from ATmega164A.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x4000;
|
||||
__ram_size = 0x400;
|
||||
__num_isrs = 31;
|
||||
|
|
@ -1,711 +0,0 @@
|
|||
// Automatically generated file. DO NOT EDIT.
|
||||
// Generated by gen-device.py from ATmega164P.atdf, see http://packs.download.atmel.com/
|
||||
|
||||
// +build avr,atmega164p
|
||||
|
||||
// Device information for the ATmega164P.
|
||||
//
|
||||
package avr
|
||||
|
||||
// Magic type name for the compiler.
|
||||
type __reg uint8
|
||||
|
||||
// Export this magic type name.
|
||||
type RegValue = __reg
|
||||
|
||||
// Some information about this device.
|
||||
const (
|
||||
DEVICE = "ATmega164P"
|
||||
ARCH = "AVR8"
|
||||
FAMILY = "megaAVR"
|
||||
)
|
||||
|
||||
// Interrupts
|
||||
const (
|
||||
IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet.
|
||||
IRQ_INT0 = 1 // External Interrupt Request 0
|
||||
IRQ_INT1 = 2 // External Interrupt Request 1
|
||||
IRQ_INT2 = 3 // External Interrupt Request 2
|
||||
IRQ_PCINT0 = 4 // Pin Change Interrupt Request 0
|
||||
IRQ_PCINT1 = 5 // Pin Change Interrupt Request 1
|
||||
IRQ_PCINT2 = 6 // Pin Change Interrupt Request 2
|
||||
IRQ_PCINT3 = 7 // Pin Change Interrupt Request 3
|
||||
IRQ_WDT = 8 // Watchdog Time-out Interrupt
|
||||
IRQ_TIMER2_COMPA = 9 // Timer/Counter2 Compare Match A
|
||||
IRQ_TIMER2_COMPB = 10 // Timer/Counter2 Compare Match B
|
||||
IRQ_TIMER2_OVF = 11 // Timer/Counter2 Overflow
|
||||
IRQ_TIMER1_CAPT = 12 // Timer/Counter1 Capture Event
|
||||
IRQ_TIMER1_COMPA = 13 // Timer/Counter1 Compare Match A
|
||||
IRQ_TIMER1_COMPB = 14 // Timer/Counter1 Compare Match B
|
||||
IRQ_TIMER1_OVF = 15 // Timer/Counter1 Overflow
|
||||
IRQ_TIMER0_COMPA = 16 // Timer/Counter0 Compare Match A
|
||||
IRQ_TIMER0_COMPB = 17 // Timer/Counter0 Compare Match B
|
||||
IRQ_TIMER0_OVF = 18 // Timer/Counter0 Overflow
|
||||
IRQ_SPI_STC = 19 // SPI Serial Transfer Complete
|
||||
IRQ_USART0_RX = 20 // USART0, Rx Complete
|
||||
IRQ_USART0_UDRE = 21 // USART0 Data register Empty
|
||||
IRQ_USART0_TX = 22 // USART0, Tx Complete
|
||||
IRQ_ANALOG_COMP = 23 // Analog Comparator
|
||||
IRQ_ADC = 24 // ADC Conversion Complete
|
||||
IRQ_EE_READY = 25 // EEPROM Ready
|
||||
IRQ_TWI = 26 // 2-wire Serial Interface
|
||||
IRQ_SPM_READY = 27 // Store Program Memory Read
|
||||
IRQ_USART1_RX = 28 // USART1 RX complete
|
||||
IRQ_USART1_UDRE = 29 // USART1 Data Register Empty
|
||||
IRQ_USART1_TX = 30 // USART1 TX complete
|
||||
IRQ_max = 30 // Highest interrupt number on this device.
|
||||
)
|
||||
|
||||
// Peripherals
|
||||
var (
|
||||
// Fuses
|
||||
FUSE = struct {
|
||||
EXTENDED __reg
|
||||
HIGH __reg
|
||||
LOW __reg
|
||||
}{
|
||||
EXTENDED: 0x2,
|
||||
HIGH: 0x1,
|
||||
LOW: 0x0,
|
||||
}
|
||||
|
||||
// Lockbits
|
||||
LOCKBIT = struct {
|
||||
LOCKBIT __reg
|
||||
}{
|
||||
LOCKBIT: 0x0,
|
||||
}
|
||||
|
||||
// Analog Comparator
|
||||
AC = struct {
|
||||
ACSR __reg
|
||||
DIDR1 __reg
|
||||
}{
|
||||
ACSR: 0x50, // Analog Comparator Control And Status Register
|
||||
DIDR1: 0x7f, // Digital Input Disable Register 1
|
||||
}
|
||||
|
||||
// USART
|
||||
USART = struct {
|
||||
UDR0 __reg
|
||||
UCSR0A __reg
|
||||
UCSR0B __reg
|
||||
UCSR0C __reg
|
||||
UBRR0L __reg
|
||||
UBRR0H __reg
|
||||
UDR1 __reg
|
||||
UCSR1A __reg
|
||||
UCSR1B __reg
|
||||
UCSR1C __reg
|
||||
UBRR1L __reg
|
||||
UBRR1H __reg
|
||||
}{
|
||||
UDR0: 0xc6, // USART I/O Data Register
|
||||
UCSR0A: 0xc0, // USART Control and Status Register A
|
||||
UCSR0B: 0xc1, // USART Control and Status Register B
|
||||
UCSR0C: 0xc2, // USART Control and Status Register C
|
||||
UBRR0L: 0xc4, // USART Baud Rate Register Bytes
|
||||
UBRR0H: 0xc4, // USART Baud Rate Register Bytes
|
||||
UDR1: 0xce, // USART I/O Data Register
|
||||
UCSR1A: 0xc8, // USART Control and Status Register A
|
||||
UCSR1B: 0xc9, // USART Control and Status Register B
|
||||
UCSR1C: 0xca, // USART Control and Status Register C
|
||||
UBRR1L: 0xcc, // USART Baud Rate Register Bytes
|
||||
UBRR1H: 0xcc, // USART Baud Rate Register Bytes
|
||||
}
|
||||
|
||||
// I/O Port
|
||||
PORT = struct {
|
||||
PORTA __reg
|
||||
DDRA __reg
|
||||
PINA __reg
|
||||
PORTB __reg
|
||||
DDRB __reg
|
||||
PINB __reg
|
||||
PORTC __reg
|
||||
DDRC __reg
|
||||
PINC __reg
|
||||
PORTD __reg
|
||||
DDRD __reg
|
||||
PIND __reg
|
||||
}{
|
||||
PORTA: 0x22, // Port A Data Register
|
||||
DDRA: 0x21, // Port A Data Direction Register
|
||||
PINA: 0x20, // Port A Input Pins
|
||||
PORTB: 0x25, // Port B Data Register
|
||||
DDRB: 0x24, // Port B Data Direction Register
|
||||
PINB: 0x23, // Port B Input Pins
|
||||
PORTC: 0x28, // Port C Data Register
|
||||
DDRC: 0x27, // Port C Data Direction Register
|
||||
PINC: 0x26, // Port C Input Pins
|
||||
PORTD: 0x2b, // Port D Data Register
|
||||
DDRD: 0x2a, // Port D Data Direction Register
|
||||
PIND: 0x29, // Port D Input Pins
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit
|
||||
TC8 = struct {
|
||||
OCR0B __reg
|
||||
OCR0A __reg
|
||||
TCNT0 __reg
|
||||
TCCR0B __reg
|
||||
TCCR0A __reg
|
||||
TIMSK0 __reg
|
||||
TIFR0 __reg
|
||||
}{
|
||||
OCR0B: 0x48, // Timer/Counter0 Output Compare Register
|
||||
OCR0A: 0x47, // Timer/Counter0 Output Compare Register
|
||||
TCNT0: 0x46, // Timer/Counter0
|
||||
TCCR0B: 0x45, // Timer/Counter Control Register B
|
||||
TCCR0A: 0x44, // Timer/Counter Control Register A
|
||||
TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register
|
||||
TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit Async
|
||||
TC8_ASYNC = struct {
|
||||
TIMSK2 __reg
|
||||
TIFR2 __reg
|
||||
TCCR2A __reg
|
||||
TCCR2B __reg
|
||||
TCNT2 __reg
|
||||
OCR2B __reg
|
||||
OCR2A __reg
|
||||
ASSR __reg
|
||||
}{
|
||||
TIMSK2: 0x70, // Timer/Counter Interrupt Mask register
|
||||
TIFR2: 0x37, // Timer/Counter Interrupt Flag Register
|
||||
TCCR2A: 0xb0, // Timer/Counter2 Control Register A
|
||||
TCCR2B: 0xb1, // Timer/Counter2 Control Register B
|
||||
TCNT2: 0xb2, // Timer/Counter2
|
||||
OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B
|
||||
OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A
|
||||
ASSR: 0xb6, // Asynchronous Status Register
|
||||
}
|
||||
|
||||
// Watchdog Timer
|
||||
WDT = struct {
|
||||
WDTCSR __reg
|
||||
}{
|
||||
WDTCSR: 0x60, // Watchdog Timer Control Register
|
||||
}
|
||||
|
||||
// JTAG Interface
|
||||
JTAG = struct {
|
||||
OCDR __reg
|
||||
}{
|
||||
OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory
|
||||
}
|
||||
|
||||
// Bootloader
|
||||
BOOT_LOAD = struct {
|
||||
SPMCSR __reg
|
||||
}{
|
||||
SPMCSR: 0x57, // Store Program Memory Control Register
|
||||
}
|
||||
|
||||
// External Interrupts
|
||||
EXINT = struct {
|
||||
EICRA __reg
|
||||
EIMSK __reg
|
||||
EIFR __reg
|
||||
PCMSK3 __reg
|
||||
PCMSK2 __reg
|
||||
PCMSK1 __reg
|
||||
PCMSK0 __reg
|
||||
PCIFR __reg
|
||||
PCICR __reg
|
||||
}{
|
||||
EICRA: 0x69, // External Interrupt Control Register A
|
||||
EIMSK: 0x3d, // External Interrupt Mask Register
|
||||
EIFR: 0x3c, // External Interrupt Flag Register
|
||||
PCMSK3: 0x73, // Pin Change Mask Register 3
|
||||
PCMSK2: 0x6d, // Pin Change Mask Register 2
|
||||
PCMSK1: 0x6c, // Pin Change Mask Register 1
|
||||
PCMSK0: 0x6b, // Pin Change Mask Register 0
|
||||
PCIFR: 0x3b, // Pin Change Interrupt Flag Register
|
||||
PCICR: 0x68, // Pin Change Interrupt Control Register
|
||||
}
|
||||
|
||||
// Analog-to-Digital Converter
|
||||
ADC = struct {
|
||||
ADMUX __reg
|
||||
ADCL __reg
|
||||
ADCH __reg
|
||||
ADCSRA __reg
|
||||
DIDR0 __reg
|
||||
}{
|
||||
ADMUX: 0x7c, // The ADC multiplexer Selection Register
|
||||
ADCL: 0x78, // ADC Data Register Bytes
|
||||
ADCH: 0x78, // ADC Data Register Bytes
|
||||
ADCSRA: 0x7a, // The ADC Control and Status register A
|
||||
DIDR0: 0x7e, // Digital Input Disable Register
|
||||
}
|
||||
|
||||
// Timer/Counter, 16-bit
|
||||
TC16 = struct {
|
||||
TIMSK1 __reg
|
||||
TIFR1 __reg
|
||||
TCCR1A __reg
|
||||
TCCR1B __reg
|
||||
TCCR1C __reg
|
||||
TCNT1L __reg
|
||||
TCNT1H __reg
|
||||
OCR1AL __reg
|
||||
OCR1AH __reg
|
||||
OCR1BL __reg
|
||||
OCR1BH __reg
|
||||
ICR1L __reg
|
||||
ICR1H __reg
|
||||
}{
|
||||
TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register
|
||||
TIFR1: 0x36, // Timer/Counter Interrupt Flag register
|
||||
TCCR1A: 0x80, // Timer/Counter1 Control Register A
|
||||
TCCR1B: 0x81, // Timer/Counter1 Control Register B
|
||||
TCCR1C: 0x82, // Timer/Counter1 Control Register C
|
||||
TCNT1L: 0x84, // Timer/Counter1 Bytes
|
||||
TCNT1H: 0x84, // Timer/Counter1 Bytes
|
||||
OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes
|
||||
OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes
|
||||
OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes
|
||||
OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes
|
||||
ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
}
|
||||
|
||||
// EEPROM
|
||||
EEPROM = struct {
|
||||
EEARL __reg
|
||||
EEARH __reg
|
||||
EEDR __reg
|
||||
EECR __reg
|
||||
}{
|
||||
EEARL: 0x41, // EEPROM Address Register Low Bytes
|
||||
EEARH: 0x41, // EEPROM Address Register Low Bytes
|
||||
EEDR: 0x40, // EEPROM Data Register
|
||||
EECR: 0x3f, // EEPROM Control Register
|
||||
}
|
||||
|
||||
// Serial Peripheral Interface
|
||||
SPI = struct {
|
||||
SPDR0 __reg
|
||||
SPSR0 __reg
|
||||
SPCR0 __reg
|
||||
}{
|
||||
SPDR0: 0x4e, // SPI Data Register
|
||||
SPSR0: 0x4d, // SPI Status Register
|
||||
SPCR0: 0x4c, // SPI Control Register
|
||||
}
|
||||
|
||||
// Two Wire Serial Interface
|
||||
TWI = struct {
|
||||
TWAMR __reg
|
||||
TWBR __reg
|
||||
TWCR __reg
|
||||
TWSR __reg
|
||||
TWDR __reg
|
||||
TWAR __reg
|
||||
}{
|
||||
TWAMR: 0xbd, // TWI (Slave) Address Mask Register
|
||||
TWBR: 0xb8, // TWI Bit Rate register
|
||||
TWCR: 0xbc, // TWI Control Register
|
||||
TWSR: 0xb9, // TWI Status Register
|
||||
TWDR: 0xbb, // TWI Data register
|
||||
TWAR: 0xba, // TWI (Slave) Address register
|
||||
}
|
||||
|
||||
// CPU Registers
|
||||
CPU = struct {
|
||||
SREG __reg
|
||||
SPL __reg
|
||||
SPH __reg
|
||||
OSCCAL __reg
|
||||
CLKPR __reg
|
||||
SMCR __reg
|
||||
GPIOR2 __reg
|
||||
GPIOR1 __reg
|
||||
GPIOR0 __reg
|
||||
PRR0 __reg
|
||||
}{
|
||||
SREG: 0x5f, // Status Register
|
||||
SPL: 0x5d, // Stack Pointer
|
||||
SPH: 0x5d, // Stack Pointer
|
||||
OSCCAL: 0x66, // Oscillator Calibration Value
|
||||
CLKPR: 0x61,
|
||||
SMCR: 0x53, // Sleep Mode Control Register
|
||||
GPIOR2: 0x4b, // General Purpose IO Register 2
|
||||
GPIOR1: 0x4a, // General Purpose IO Register 1
|
||||
GPIOR0: 0x3e, // General Purpose IO Register 0
|
||||
PRR0: 0x64, // Power Reduction Register0
|
||||
}
|
||||
)
|
||||
|
||||
// Bitfields for FUSE: Fuses
|
||||
const (
|
||||
// EXTENDED
|
||||
EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level
|
||||
|
||||
// HIGH
|
||||
HIGH_OCDEN = 0x80 // On-Chip Debug Enabled
|
||||
HIGH_JTAGEN = 0x40 // JTAG Interface Enabled
|
||||
HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled
|
||||
HIGH_WDTON = 0x10 // Watchdog timer always on
|
||||
HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle
|
||||
HIGH_BOOTSZ = 0x6 // Select Boot Size
|
||||
HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled
|
||||
|
||||
// LOW
|
||||
LOW_CKDIV8 = 0x80 // Divide clock by 8 internally
|
||||
LOW_CKOUT = 0x40 // Clock output on PORTB1
|
||||
LOW_SUT_CKSEL = 0x3f // Select Clock Source
|
||||
)
|
||||
|
||||
// Bitfields for LOCKBIT: Lockbits
|
||||
const (
|
||||
// LOCKBIT
|
||||
LOCKBIT_LB = 0x3 // Memory Lock
|
||||
LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode
|
||||
LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode
|
||||
)
|
||||
|
||||
// Bitfields for AC: Analog Comparator
|
||||
const (
|
||||
// ACSR: Analog Comparator Control And Status Register
|
||||
ACSR_ACD = 0x80 // Analog Comparator Disable
|
||||
ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select
|
||||
ACSR_ACO = 0x20 // Analog Compare Output
|
||||
ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag
|
||||
ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable
|
||||
ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable
|
||||
ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits
|
||||
|
||||
// DIDR1: Digital Input Disable Register 1
|
||||
DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable
|
||||
DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable
|
||||
)
|
||||
|
||||
// Bitfields for USART: USART
|
||||
const (
|
||||
// UCSR0A: USART Control and Status Register A
|
||||
UCSR0A_RXC0 = 0x80 // USART Receive Complete
|
||||
UCSR0A_TXC0 = 0x40 // USART Transmitt Complete
|
||||
UCSR0A_UDRE0 = 0x20 // USART Data Register Empty
|
||||
UCSR0A_FE0 = 0x10 // Framing Error
|
||||
UCSR0A_DOR0 = 0x8 // Data overRun
|
||||
UCSR0A_UPE0 = 0x4 // Parity Error
|
||||
UCSR0A_U2X0 = 0x2 // Double the USART transmission speed
|
||||
UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode
|
||||
|
||||
// UCSR0B: USART Control and Status Register B
|
||||
UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable
|
||||
UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable
|
||||
UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable
|
||||
UCSR0B_RXEN0 = 0x10 // Receiver Enable
|
||||
UCSR0B_TXEN0 = 0x8 // Transmitter Enable
|
||||
UCSR0B_UCSZ02 = 0x4 // Character Size
|
||||
UCSR0B_RXB80 = 0x2 // Receive Data Bit 8
|
||||
UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8
|
||||
|
||||
// UCSR0C: USART Control and Status Register C
|
||||
UCSR0C_UMSEL0 = 0xc0 // USART Mode Select
|
||||
UCSR0C_UPM0 = 0x30 // Parity Mode Bits
|
||||
UCSR0C_USBS0 = 0x8 // Stop Bit Select
|
||||
UCSR0C_UCSZ0 = 0x6 // Character Size
|
||||
UCSR0C_UCPOL0 = 0x1 // Clock Polarity
|
||||
|
||||
// UCSR1A: USART Control and Status Register A
|
||||
UCSR1A_RXC1 = 0x80 // USART Receive Complete
|
||||
UCSR1A_TXC1 = 0x40 // USART Transmitt Complete
|
||||
UCSR1A_UDRE1 = 0x20 // USART Data Register Empty
|
||||
UCSR1A_FE1 = 0x10 // Framing Error
|
||||
UCSR1A_DOR1 = 0x8 // Data overRun
|
||||
UCSR1A_UPE1 = 0x4 // Parity Error
|
||||
UCSR1A_U2X1 = 0x2 // Double the USART transmission speed
|
||||
UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode
|
||||
|
||||
// UCSR1B: USART Control and Status Register B
|
||||
UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable
|
||||
UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable
|
||||
UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable
|
||||
UCSR1B_RXEN1 = 0x10 // Receiver Enable
|
||||
UCSR1B_TXEN1 = 0x8 // Transmitter Enable
|
||||
UCSR1B_UCSZ12 = 0x4 // Character Size
|
||||
UCSR1B_RXB81 = 0x2 // Receive Data Bit 8
|
||||
UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8
|
||||
|
||||
// UCSR1C: USART Control and Status Register C
|
||||
UCSR1C_UMSEL1 = 0xc0 // USART Mode Select
|
||||
UCSR1C_UPM1 = 0x30 // Parity Mode Bits
|
||||
UCSR1C_USBS1 = 0x8 // Stop Bit Select
|
||||
UCSR1C_UCSZ1 = 0x6 // Character Size
|
||||
UCSR1C_UCPOL1 = 0x1 // Clock Polarity
|
||||
)
|
||||
|
||||
// Bitfields for TC8: Timer/Counter, 8-bit
|
||||
const (
|
||||
// TCCR0B: Timer/Counter Control Register B
|
||||
TCCR0B_FOC0A = 0x80 // Force Output Compare A
|
||||
TCCR0B_FOC0B = 0x40 // Force Output Compare B
|
||||
TCCR0B_WGM02 = 0x8
|
||||
TCCR0B_CS0 = 0x7 // Clock Select
|
||||
|
||||
// TCCR0A: Timer/Counter Control Register A
|
||||
TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode
|
||||
TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm
|
||||
TCCR0A_WGM0 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TIMSK0: Timer/Counter0 Interrupt Mask Register
|
||||
TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable
|
||||
TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable
|
||||
TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable
|
||||
|
||||
// TIFR0: Timer/Counter0 Interrupt Flag register
|
||||
TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B
|
||||
TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A
|
||||
TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag
|
||||
)
|
||||
|
||||
// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async
|
||||
const (
|
||||
// TIMSK2: Timer/Counter Interrupt Mask register
|
||||
TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable
|
||||
TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable
|
||||
TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable
|
||||
|
||||
// TIFR2: Timer/Counter Interrupt Flag Register
|
||||
TIFR2_OCF2B = 0x4 // Output Compare Flag 2B
|
||||
TIFR2_OCF2A = 0x2 // Output Compare Flag 2A
|
||||
TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag
|
||||
|
||||
// TCCR2A: Timer/Counter2 Control Register A
|
||||
TCCR2A_COM2A = 0xc0 // Compare Output Mode bits
|
||||
TCCR2A_COM2B = 0x30 // Compare Output Mode bits
|
||||
TCCR2A_WGM2 = 0x3 // Waveform Genration Mode
|
||||
|
||||
// TCCR2B: Timer/Counter2 Control Register B
|
||||
TCCR2B_FOC2A = 0x80 // Force Output Compare A
|
||||
TCCR2B_FOC2B = 0x40 // Force Output Compare B
|
||||
TCCR2B_WGM22 = 0x8 // Waveform Generation Mode
|
||||
TCCR2B_CS2 = 0x7 // Clock Select bits
|
||||
|
||||
// ASSR: Asynchronous Status Register
|
||||
ASSR_EXCLK = 0x40 // Enable External Clock Input
|
||||
ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2
|
||||
ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy
|
||||
ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy
|
||||
ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy
|
||||
ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy
|
||||
ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy
|
||||
)
|
||||
|
||||
// Bitfields for WDT: Watchdog Timer
|
||||
const (
|
||||
// WDTCSR: Watchdog Timer Control Register
|
||||
WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag
|
||||
WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable
|
||||
WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits
|
||||
WDTCSR_WDCE = 0x10 // Watchdog Change Enable
|
||||
WDTCSR_WDE = 0x8 // Watch Dog Enable
|
||||
)
|
||||
|
||||
// Bitfields for BOOT_LOAD: Bootloader
|
||||
const (
|
||||
// SPMCSR: Store Program Memory Control Register
|
||||
SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable
|
||||
SPMCSR_RWWSB = 0x40 // Read While Write Section Busy
|
||||
SPMCSR_SIGRD = 0x20 // Signature Row Read
|
||||
SPMCSR_RWWSRE = 0x10 // Read While Write section read enable
|
||||
SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set
|
||||
SPMCSR_PGWRT = 0x4 // Page Write
|
||||
SPMCSR_PGERS = 0x2 // Page Erase
|
||||
SPMCSR_SPMEN = 0x1 // Store Program Memory Enable
|
||||
)
|
||||
|
||||
// Bitfields for EXINT: External Interrupts
|
||||
const (
|
||||
// EICRA: External Interrupt Control Register A
|
||||
EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit
|
||||
EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit
|
||||
EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit
|
||||
|
||||
// EIMSK: External Interrupt Mask Register
|
||||
EIMSK_INT = 0x7 // External Interrupt Request 2 Enable
|
||||
|
||||
// EIFR: External Interrupt Flag Register
|
||||
EIFR_INTF = 0x7 // External Interrupt Flags
|
||||
|
||||
// PCMSK3: Pin Change Mask Register 3
|
||||
PCMSK3_PCINT = 0xff // Pin Change Enable Masks
|
||||
|
||||
// PCMSK2: Pin Change Mask Register 2
|
||||
PCMSK2_PCINT = 0xff // Pin Change Enable Masks
|
||||
|
||||
// PCMSK1: Pin Change Mask Register 1
|
||||
PCMSK1_PCINT = 0xff // Pin Change Enable Masks
|
||||
|
||||
// PCMSK0: Pin Change Mask Register 0
|
||||
PCMSK0_PCINT = 0xff // Pin Change Enable Masks
|
||||
|
||||
// PCIFR: Pin Change Interrupt Flag Register
|
||||
PCIFR_PCIF = 0xf // Pin Change Interrupt Flags
|
||||
|
||||
// PCICR: Pin Change Interrupt Control Register
|
||||
PCICR_PCIE = 0xf // Pin Change Interrupt Enables
|
||||
)
|
||||
|
||||
// Bitfields for ADC: Analog-to-Digital Converter
|
||||
const (
|
||||
// ADMUX: The ADC multiplexer Selection Register
|
||||
ADMUX_REFS = 0xc0 // Reference Selection Bits
|
||||
ADMUX_ADLAR = 0x20 // Left Adjust Result
|
||||
ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits
|
||||
|
||||
// ADCSRA: The ADC Control and Status register A
|
||||
ADCSRA_ADEN = 0x80 // ADC Enable
|
||||
ADCSRA_ADSC = 0x40 // ADC Start Conversion
|
||||
ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable
|
||||
ADCSRA_ADIF = 0x10 // ADC Interrupt Flag
|
||||
ADCSRA_ADIE = 0x8 // ADC Interrupt Enable
|
||||
ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits
|
||||
|
||||
// DIDR0: Digital Input Disable Register
|
||||
DIDR0_ADC7D = 0x80
|
||||
DIDR0_ADC6D = 0x40
|
||||
DIDR0_ADC5D = 0x20
|
||||
DIDR0_ADC4D = 0x10
|
||||
DIDR0_ADC3D = 0x8
|
||||
DIDR0_ADC2D = 0x4
|
||||
DIDR0_ADC1D = 0x2
|
||||
DIDR0_ADC0D = 0x1
|
||||
)
|
||||
|
||||
// Bitfields for TC16: Timer/Counter, 16-bit
|
||||
const (
|
||||
// TIMSK1: Timer/Counter1 Interrupt Mask Register
|
||||
TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable
|
||||
TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable
|
||||
TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable
|
||||
TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable
|
||||
|
||||
// TIFR1: Timer/Counter Interrupt Flag register
|
||||
TIFR1_ICF1 = 0x20 // Timer/Counter1 Input Capture Flag
|
||||
TIFR1_OCF1B = 0x4 // Timer/Counter1 Output Compare B Match Flag
|
||||
TIFR1_OCF1A = 0x2 // Timer/Counter1 Output Compare A Match Flag
|
||||
TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag
|
||||
|
||||
// TCCR1A: Timer/Counter1 Control Register A
|
||||
TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits
|
||||
TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits
|
||||
TCCR1A_WGM1 = 0x3 // Pulse Width Modulator Select Bits
|
||||
|
||||
// TCCR1B: Timer/Counter1 Control Register B
|
||||
TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler
|
||||
TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select
|
||||
TCCR1B_WGM1 = 0x18 // Waveform Generation Mode Bits
|
||||
TCCR1B_CS1 = 0x7 // Clock Select1 bits
|
||||
|
||||
// TCCR1C: Timer/Counter1 Control Register C
|
||||
TCCR1C_FOC1A = 0x80 // Force Output Compare for Channel A
|
||||
TCCR1C_FOC1B = 0x40 // Force Output Compare for Channel B
|
||||
)
|
||||
|
||||
// Bitfields for EEPROM: EEPROM
|
||||
const (
|
||||
// EECR: EEPROM Control Register
|
||||
EECR_EEPM = 0x30 // EEPROM Programming Mode Bits
|
||||
EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable
|
||||
EECR_EEMPE = 0x4 // EEPROM Master Write Enable
|
||||
EECR_EEPE = 0x2 // EEPROM Write Enable
|
||||
EECR_EERE = 0x1 // EEPROM Read Enable
|
||||
)
|
||||
|
||||
// Bitfields for SPI: Serial Peripheral Interface
|
||||
const (
|
||||
// SPSR0: SPI Status Register
|
||||
SPSR0_SPIF0 = 0x80 // SPI Interrupt Flag
|
||||
SPSR0_WCOL0 = 0x40 // Write Collision Flag
|
||||
SPSR0_SPI2X0 = 0x1 // Double SPI Speed Bit
|
||||
|
||||
// SPCR0: SPI Control Register
|
||||
SPCR0_SPIE0 = 0x80 // SPI Interrupt Enable
|
||||
SPCR0_SPE0 = 0x40 // SPI Enable
|
||||
SPCR0_DORD0 = 0x20 // Data Order
|
||||
SPCR0_MSTR0 = 0x10 // Master/Slave Select
|
||||
SPCR0_CPOL0 = 0x8 // Clock polarity
|
||||
SPCR0_CPHA0 = 0x4 // Clock Phase
|
||||
SPCR0_SPR10 = 0x2 // SPI Clock Rate Select 1
|
||||
SPCR0_SPR00 = 0x1 // SPI Clock Rate Select 0
|
||||
)
|
||||
|
||||
// Bitfields for TWI: Two Wire Serial Interface
|
||||
const (
|
||||
// TWAMR: TWI (Slave) Address Mask Register
|
||||
TWAMR_TWAM = 0xfe
|
||||
|
||||
// TWCR: TWI Control Register
|
||||
TWCR_TWINT = 0x80 // TWI Interrupt Flag
|
||||
TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit
|
||||
TWCR_TWSTA = 0x20 // TWI Start Condition Bit
|
||||
TWCR_TWSTO = 0x10 // TWI Stop Condition Bit
|
||||
TWCR_TWWC = 0x8 // TWI Write Collition Flag
|
||||
TWCR_TWEN = 0x4 // TWI Enable Bit
|
||||
TWCR_TWIE = 0x1 // TWI Interrupt Enable
|
||||
|
||||
// TWSR: TWI Status Register
|
||||
TWSR_TWS = 0xf8 // TWI Status
|
||||
TWSR_TWPS = 0x3 // TWI Prescaler
|
||||
|
||||
// TWAR: TWI (Slave) Address register
|
||||
TWAR_TWA = 0xfe // TWI (Slave) Address register Bits
|
||||
TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit
|
||||
)
|
||||
|
||||
// Bitfields for CPU: CPU Registers
|
||||
const (
|
||||
// SREG: Status Register
|
||||
SREG_I = 0x80 // Global Interrupt Enable
|
||||
SREG_T = 0x40 // Bit Copy Storage
|
||||
SREG_H = 0x20 // Half Carry Flag
|
||||
SREG_S = 0x10 // Sign Bit
|
||||
SREG_V = 0x8 // Two's Complement Overflow Flag
|
||||
SREG_N = 0x4 // Negative Flag
|
||||
SREG_Z = 0x2 // Zero Flag
|
||||
SREG_C = 0x1 // Carry Flag
|
||||
|
||||
// OSCCAL: Oscillator Calibration Value
|
||||
OSCCAL_OSCCAL = 0xff // Oscillator Calibration
|
||||
|
||||
// CLKPR
|
||||
CLKPR_CLKPCE = 0x80
|
||||
CLKPR_CLKPS = 0xf
|
||||
|
||||
// SMCR: Sleep Mode Control Register
|
||||
SMCR_SM = 0xe // Sleep Mode Select bits
|
||||
SMCR_SE = 0x1 // Sleep Enable
|
||||
|
||||
// GPIOR2: General Purpose IO Register 2
|
||||
GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis
|
||||
|
||||
// GPIOR1: General Purpose IO Register 1
|
||||
GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis
|
||||
|
||||
// GPIOR0: General Purpose IO Register 0
|
||||
GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7
|
||||
GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6
|
||||
GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5
|
||||
GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4
|
||||
GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3
|
||||
GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2
|
||||
GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1
|
||||
GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0
|
||||
|
||||
// PRR0: Power Reduction Register0
|
||||
PRR0_PRTWI = 0x80 // Power Reduction TWI
|
||||
PRR0_PRTIM2 = 0x40 // Power Reduction Timer/Counter2
|
||||
PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0
|
||||
PRR0_PRUSART1 = 0x10 // Power Reduction USART1
|
||||
PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1
|
||||
PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface
|
||||
PRR0_PRUSART0 = 0x2 // Power Reduction USART0
|
||||
PRR0_PRADC = 0x1 // Power Reduction ADC
|
||||
)
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from ATmega164P.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x4000;
|
||||
__ram_size = 0x400;
|
||||
__num_isrs = 31;
|
||||
|
|
@ -1,711 +0,0 @@
|
|||
// Automatically generated file. DO NOT EDIT.
|
||||
// Generated by gen-device.py from ATmega164PA.atdf, see http://packs.download.atmel.com/
|
||||
|
||||
// +build avr,atmega164pa
|
||||
|
||||
// Device information for the ATmega164PA.
|
||||
//
|
||||
package avr
|
||||
|
||||
// Magic type name for the compiler.
|
||||
type __reg uint8
|
||||
|
||||
// Export this magic type name.
|
||||
type RegValue = __reg
|
||||
|
||||
// Some information about this device.
|
||||
const (
|
||||
DEVICE = "ATmega164PA"
|
||||
ARCH = "AVR8"
|
||||
FAMILY = "megaAVR"
|
||||
)
|
||||
|
||||
// Interrupts
|
||||
const (
|
||||
IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet.
|
||||
IRQ_INT0 = 1 // External Interrupt Request 0
|
||||
IRQ_INT1 = 2 // External Interrupt Request 1
|
||||
IRQ_INT2 = 3 // External Interrupt Request 2
|
||||
IRQ_PCINT0 = 4 // Pin Change Interrupt Request 0
|
||||
IRQ_PCINT1 = 5 // Pin Change Interrupt Request 1
|
||||
IRQ_PCINT2 = 6 // Pin Change Interrupt Request 2
|
||||
IRQ_PCINT3 = 7 // Pin Change Interrupt Request 3
|
||||
IRQ_WDT = 8 // Watchdog Time-out Interrupt
|
||||
IRQ_TIMER2_COMPA = 9 // Timer/Counter2 Compare Match A
|
||||
IRQ_TIMER2_COMPB = 10 // Timer/Counter2 Compare Match B
|
||||
IRQ_TIMER2_OVF = 11 // Timer/Counter2 Overflow
|
||||
IRQ_TIMER1_CAPT = 12 // Timer/Counter1 Capture Event
|
||||
IRQ_TIMER1_COMPA = 13 // Timer/Counter1 Compare Match A
|
||||
IRQ_TIMER1_COMPB = 14 // Timer/Counter1 Compare Match B
|
||||
IRQ_TIMER1_OVF = 15 // Timer/Counter1 Overflow
|
||||
IRQ_TIMER0_COMPA = 16 // Timer/Counter0 Compare Match A
|
||||
IRQ_TIMER0_COMPB = 17 // Timer/Counter0 Compare Match B
|
||||
IRQ_TIMER0_OVF = 18 // Timer/Counter0 Overflow
|
||||
IRQ_SPI_STC = 19 // SPI Serial Transfer Complete
|
||||
IRQ_USART0_RX = 20 // USART0, Rx Complete
|
||||
IRQ_USART0_UDRE = 21 // USART0 Data register Empty
|
||||
IRQ_USART0_TX = 22 // USART0, Tx Complete
|
||||
IRQ_ANALOG_COMP = 23 // Analog Comparator
|
||||
IRQ_ADC = 24 // ADC Conversion Complete
|
||||
IRQ_EE_READY = 25 // EEPROM Ready
|
||||
IRQ_TWI = 26 // 2-wire Serial Interface
|
||||
IRQ_SPM_READY = 27 // Store Program Memory Read
|
||||
IRQ_USART1_RX = 28 // USART1 RX complete
|
||||
IRQ_USART1_UDRE = 29 // USART1 Data Register Empty
|
||||
IRQ_USART1_TX = 30 // USART1 TX complete
|
||||
IRQ_max = 30 // Highest interrupt number on this device.
|
||||
)
|
||||
|
||||
// Peripherals
|
||||
var (
|
||||
// Fuses
|
||||
FUSE = struct {
|
||||
EXTENDED __reg
|
||||
HIGH __reg
|
||||
LOW __reg
|
||||
}{
|
||||
EXTENDED: 0x2,
|
||||
HIGH: 0x1,
|
||||
LOW: 0x0,
|
||||
}
|
||||
|
||||
// Lockbits
|
||||
LOCKBIT = struct {
|
||||
LOCKBIT __reg
|
||||
}{
|
||||
LOCKBIT: 0x0,
|
||||
}
|
||||
|
||||
// Analog Comparator
|
||||
AC = struct {
|
||||
ACSR __reg
|
||||
DIDR1 __reg
|
||||
}{
|
||||
ACSR: 0x50, // Analog Comparator Control And Status Register
|
||||
DIDR1: 0x7f, // Digital Input Disable Register 1
|
||||
}
|
||||
|
||||
// USART
|
||||
USART = struct {
|
||||
UDR0 __reg
|
||||
UCSR0A __reg
|
||||
UCSR0B __reg
|
||||
UCSR0C __reg
|
||||
UBRR0L __reg
|
||||
UBRR0H __reg
|
||||
UDR1 __reg
|
||||
UCSR1A __reg
|
||||
UCSR1B __reg
|
||||
UCSR1C __reg
|
||||
UBRR1L __reg
|
||||
UBRR1H __reg
|
||||
}{
|
||||
UDR0: 0xc6, // USART I/O Data Register
|
||||
UCSR0A: 0xc0, // USART Control and Status Register A
|
||||
UCSR0B: 0xc1, // USART Control and Status Register B
|
||||
UCSR0C: 0xc2, // USART Control and Status Register C
|
||||
UBRR0L: 0xc4, // USART Baud Rate Register Bytes
|
||||
UBRR0H: 0xc4, // USART Baud Rate Register Bytes
|
||||
UDR1: 0xce, // USART I/O Data Register
|
||||
UCSR1A: 0xc8, // USART Control and Status Register A
|
||||
UCSR1B: 0xc9, // USART Control and Status Register B
|
||||
UCSR1C: 0xca, // USART Control and Status Register C
|
||||
UBRR1L: 0xcc, // USART Baud Rate Register Bytes
|
||||
UBRR1H: 0xcc, // USART Baud Rate Register Bytes
|
||||
}
|
||||
|
||||
// I/O Port
|
||||
PORT = struct {
|
||||
PORTA __reg
|
||||
DDRA __reg
|
||||
PINA __reg
|
||||
PORTB __reg
|
||||
DDRB __reg
|
||||
PINB __reg
|
||||
PORTC __reg
|
||||
DDRC __reg
|
||||
PINC __reg
|
||||
PORTD __reg
|
||||
DDRD __reg
|
||||
PIND __reg
|
||||
}{
|
||||
PORTA: 0x22, // Port A Data Register
|
||||
DDRA: 0x21, // Port A Data Direction Register
|
||||
PINA: 0x20, // Port A Input Pins
|
||||
PORTB: 0x25, // Port B Data Register
|
||||
DDRB: 0x24, // Port B Data Direction Register
|
||||
PINB: 0x23, // Port B Input Pins
|
||||
PORTC: 0x28, // Port C Data Register
|
||||
DDRC: 0x27, // Port C Data Direction Register
|
||||
PINC: 0x26, // Port C Input Pins
|
||||
PORTD: 0x2b, // Port D Data Register
|
||||
DDRD: 0x2a, // Port D Data Direction Register
|
||||
PIND: 0x29, // Port D Input Pins
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit
|
||||
TC8 = struct {
|
||||
OCR0B __reg
|
||||
OCR0A __reg
|
||||
TCNT0 __reg
|
||||
TCCR0B __reg
|
||||
TCCR0A __reg
|
||||
TIMSK0 __reg
|
||||
TIFR0 __reg
|
||||
}{
|
||||
OCR0B: 0x48, // Timer/Counter0 Output Compare Register
|
||||
OCR0A: 0x47, // Timer/Counter0 Output Compare Register
|
||||
TCNT0: 0x46, // Timer/Counter0
|
||||
TCCR0B: 0x45, // Timer/Counter Control Register B
|
||||
TCCR0A: 0x44, // Timer/Counter Control Register A
|
||||
TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register
|
||||
TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit Async
|
||||
TC8_ASYNC = struct {
|
||||
TIMSK2 __reg
|
||||
TIFR2 __reg
|
||||
TCCR2A __reg
|
||||
TCCR2B __reg
|
||||
TCNT2 __reg
|
||||
OCR2B __reg
|
||||
OCR2A __reg
|
||||
ASSR __reg
|
||||
}{
|
||||
TIMSK2: 0x70, // Timer/Counter Interrupt Mask register
|
||||
TIFR2: 0x37, // Timer/Counter Interrupt Flag Register
|
||||
TCCR2A: 0xb0, // Timer/Counter2 Control Register A
|
||||
TCCR2B: 0xb1, // Timer/Counter2 Control Register B
|
||||
TCNT2: 0xb2, // Timer/Counter2
|
||||
OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B
|
||||
OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A
|
||||
ASSR: 0xb6, // Asynchronous Status Register
|
||||
}
|
||||
|
||||
// Watchdog Timer
|
||||
WDT = struct {
|
||||
WDTCSR __reg
|
||||
}{
|
||||
WDTCSR: 0x60, // Watchdog Timer Control Register
|
||||
}
|
||||
|
||||
// JTAG Interface
|
||||
JTAG = struct {
|
||||
OCDR __reg
|
||||
}{
|
||||
OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory
|
||||
}
|
||||
|
||||
// Bootloader
|
||||
BOOT_LOAD = struct {
|
||||
SPMCSR __reg
|
||||
}{
|
||||
SPMCSR: 0x57, // Store Program Memory Control Register
|
||||
}
|
||||
|
||||
// External Interrupts
|
||||
EXINT = struct {
|
||||
EICRA __reg
|
||||
EIMSK __reg
|
||||
EIFR __reg
|
||||
PCMSK3 __reg
|
||||
PCMSK2 __reg
|
||||
PCMSK1 __reg
|
||||
PCMSK0 __reg
|
||||
PCIFR __reg
|
||||
PCICR __reg
|
||||
}{
|
||||
EICRA: 0x69, // External Interrupt Control Register A
|
||||
EIMSK: 0x3d, // External Interrupt Mask Register
|
||||
EIFR: 0x3c, // External Interrupt Flag Register
|
||||
PCMSK3: 0x73, // Pin Change Mask Register 3
|
||||
PCMSK2: 0x6d, // Pin Change Mask Register 2
|
||||
PCMSK1: 0x6c, // Pin Change Mask Register 1
|
||||
PCMSK0: 0x6b, // Pin Change Mask Register 0
|
||||
PCIFR: 0x3b, // Pin Change Interrupt Flag Register
|
||||
PCICR: 0x68, // Pin Change Interrupt Control Register
|
||||
}
|
||||
|
||||
// Analog-to-Digital Converter
|
||||
ADC = struct {
|
||||
ADMUX __reg
|
||||
ADCL __reg
|
||||
ADCH __reg
|
||||
ADCSRA __reg
|
||||
DIDR0 __reg
|
||||
}{
|
||||
ADMUX: 0x7c, // The ADC multiplexer Selection Register
|
||||
ADCL: 0x78, // ADC Data Register Bytes
|
||||
ADCH: 0x78, // ADC Data Register Bytes
|
||||
ADCSRA: 0x7a, // The ADC Control and Status register A
|
||||
DIDR0: 0x7e, // Digital Input Disable Register
|
||||
}
|
||||
|
||||
// Timer/Counter, 16-bit
|
||||
TC16 = struct {
|
||||
TIMSK1 __reg
|
||||
TIFR1 __reg
|
||||
TCCR1A __reg
|
||||
TCCR1B __reg
|
||||
TCCR1C __reg
|
||||
TCNT1L __reg
|
||||
TCNT1H __reg
|
||||
OCR1AL __reg
|
||||
OCR1AH __reg
|
||||
OCR1BL __reg
|
||||
OCR1BH __reg
|
||||
ICR1L __reg
|
||||
ICR1H __reg
|
||||
}{
|
||||
TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register
|
||||
TIFR1: 0x36, // Timer/Counter Interrupt Flag register
|
||||
TCCR1A: 0x80, // Timer/Counter1 Control Register A
|
||||
TCCR1B: 0x81, // Timer/Counter1 Control Register B
|
||||
TCCR1C: 0x82, // Timer/Counter1 Control Register C
|
||||
TCNT1L: 0x84, // Timer/Counter1 Bytes
|
||||
TCNT1H: 0x84, // Timer/Counter1 Bytes
|
||||
OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes
|
||||
OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes
|
||||
OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes
|
||||
OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes
|
||||
ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
}
|
||||
|
||||
// EEPROM
|
||||
EEPROM = struct {
|
||||
EEARL __reg
|
||||
EEARH __reg
|
||||
EEDR __reg
|
||||
EECR __reg
|
||||
}{
|
||||
EEARL: 0x41, // EEPROM Address Register Low Bytes
|
||||
EEARH: 0x41, // EEPROM Address Register Low Bytes
|
||||
EEDR: 0x40, // EEPROM Data Register
|
||||
EECR: 0x3f, // EEPROM Control Register
|
||||
}
|
||||
|
||||
// Serial Peripheral Interface
|
||||
SPI = struct {
|
||||
SPDR0 __reg
|
||||
SPSR0 __reg
|
||||
SPCR0 __reg
|
||||
}{
|
||||
SPDR0: 0x4e, // SPI Data Register
|
||||
SPSR0: 0x4d, // SPI Status Register
|
||||
SPCR0: 0x4c, // SPI Control Register
|
||||
}
|
||||
|
||||
// Two Wire Serial Interface
|
||||
TWI = struct {
|
||||
TWAMR __reg
|
||||
TWBR __reg
|
||||
TWCR __reg
|
||||
TWSR __reg
|
||||
TWDR __reg
|
||||
TWAR __reg
|
||||
}{
|
||||
TWAMR: 0xbd, // TWI (Slave) Address Mask Register
|
||||
TWBR: 0xb8, // TWI Bit Rate register
|
||||
TWCR: 0xbc, // TWI Control Register
|
||||
TWSR: 0xb9, // TWI Status Register
|
||||
TWDR: 0xbb, // TWI Data register
|
||||
TWAR: 0xba, // TWI (Slave) Address register
|
||||
}
|
||||
|
||||
// CPU Registers
|
||||
CPU = struct {
|
||||
SREG __reg
|
||||
SPL __reg
|
||||
SPH __reg
|
||||
OSCCAL __reg
|
||||
CLKPR __reg
|
||||
SMCR __reg
|
||||
GPIOR2 __reg
|
||||
GPIOR1 __reg
|
||||
GPIOR0 __reg
|
||||
PRR0 __reg
|
||||
}{
|
||||
SREG: 0x5f, // Status Register
|
||||
SPL: 0x5d, // Stack Pointer
|
||||
SPH: 0x5d, // Stack Pointer
|
||||
OSCCAL: 0x66, // Oscillator Calibration Value
|
||||
CLKPR: 0x61,
|
||||
SMCR: 0x53, // Sleep Mode Control Register
|
||||
GPIOR2: 0x4b, // General Purpose IO Register 2
|
||||
GPIOR1: 0x4a, // General Purpose IO Register 1
|
||||
GPIOR0: 0x3e, // General Purpose IO Register 0
|
||||
PRR0: 0x64, // Power Reduction Register0
|
||||
}
|
||||
)
|
||||
|
||||
// Bitfields for FUSE: Fuses
|
||||
const (
|
||||
// EXTENDED
|
||||
EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level
|
||||
|
||||
// HIGH
|
||||
HIGH_OCDEN = 0x80 // On-Chip Debug Enabled
|
||||
HIGH_JTAGEN = 0x40 // JTAG Interface Enabled
|
||||
HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled
|
||||
HIGH_WDTON = 0x10 // Watchdog timer always on
|
||||
HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle
|
||||
HIGH_BOOTSZ = 0x6 // Select Boot Size
|
||||
HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled
|
||||
|
||||
// LOW
|
||||
LOW_CKDIV8 = 0x80 // Divide clock by 8 internally
|
||||
LOW_CKOUT = 0x40 // Clock output on PORTB1
|
||||
LOW_SUT_CKSEL = 0x3f // Select Clock Source
|
||||
)
|
||||
|
||||
// Bitfields for LOCKBIT: Lockbits
|
||||
const (
|
||||
// LOCKBIT
|
||||
LOCKBIT_LB = 0x3 // Memory Lock
|
||||
LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode
|
||||
LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode
|
||||
)
|
||||
|
||||
// Bitfields for AC: Analog Comparator
|
||||
const (
|
||||
// ACSR: Analog Comparator Control And Status Register
|
||||
ACSR_ACD = 0x80 // Analog Comparator Disable
|
||||
ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select
|
||||
ACSR_ACO = 0x20 // Analog Compare Output
|
||||
ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag
|
||||
ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable
|
||||
ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable
|
||||
ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits
|
||||
|
||||
// DIDR1: Digital Input Disable Register 1
|
||||
DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable
|
||||
DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable
|
||||
)
|
||||
|
||||
// Bitfields for USART: USART
|
||||
const (
|
||||
// UCSR0A: USART Control and Status Register A
|
||||
UCSR0A_RXC0 = 0x80 // USART Receive Complete
|
||||
UCSR0A_TXC0 = 0x40 // USART Transmitt Complete
|
||||
UCSR0A_UDRE0 = 0x20 // USART Data Register Empty
|
||||
UCSR0A_FE0 = 0x10 // Framing Error
|
||||
UCSR0A_DOR0 = 0x8 // Data overRun
|
||||
UCSR0A_UPE0 = 0x4 // Parity Error
|
||||
UCSR0A_U2X0 = 0x2 // Double the USART transmission speed
|
||||
UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode
|
||||
|
||||
// UCSR0B: USART Control and Status Register B
|
||||
UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable
|
||||
UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable
|
||||
UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable
|
||||
UCSR0B_RXEN0 = 0x10 // Receiver Enable
|
||||
UCSR0B_TXEN0 = 0x8 // Transmitter Enable
|
||||
UCSR0B_UCSZ02 = 0x4 // Character Size
|
||||
UCSR0B_RXB80 = 0x2 // Receive Data Bit 8
|
||||
UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8
|
||||
|
||||
// UCSR0C: USART Control and Status Register C
|
||||
UCSR0C_UMSEL0 = 0xc0 // USART Mode Select
|
||||
UCSR0C_UPM0 = 0x30 // Parity Mode Bits
|
||||
UCSR0C_USBS0 = 0x8 // Stop Bit Select
|
||||
UCSR0C_UCSZ0 = 0x6 // Character Size
|
||||
UCSR0C_UCPOL0 = 0x1 // Clock Polarity
|
||||
|
||||
// UCSR1A: USART Control and Status Register A
|
||||
UCSR1A_RXC1 = 0x80 // USART Receive Complete
|
||||
UCSR1A_TXC1 = 0x40 // USART Transmitt Complete
|
||||
UCSR1A_UDRE1 = 0x20 // USART Data Register Empty
|
||||
UCSR1A_FE1 = 0x10 // Framing Error
|
||||
UCSR1A_DOR1 = 0x8 // Data overRun
|
||||
UCSR1A_UPE1 = 0x4 // Parity Error
|
||||
UCSR1A_U2X1 = 0x2 // Double the USART transmission speed
|
||||
UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode
|
||||
|
||||
// UCSR1B: USART Control and Status Register B
|
||||
UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable
|
||||
UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable
|
||||
UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable
|
||||
UCSR1B_RXEN1 = 0x10 // Receiver Enable
|
||||
UCSR1B_TXEN1 = 0x8 // Transmitter Enable
|
||||
UCSR1B_UCSZ12 = 0x4 // Character Size
|
||||
UCSR1B_RXB81 = 0x2 // Receive Data Bit 8
|
||||
UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8
|
||||
|
||||
// UCSR1C: USART Control and Status Register C
|
||||
UCSR1C_UMSEL1 = 0xc0 // USART Mode Select
|
||||
UCSR1C_UPM1 = 0x30 // Parity Mode Bits
|
||||
UCSR1C_USBS1 = 0x8 // Stop Bit Select
|
||||
UCSR1C_UCSZ1 = 0x6 // Character Size
|
||||
UCSR1C_UCPOL1 = 0x1 // Clock Polarity
|
||||
)
|
||||
|
||||
// Bitfields for TC8: Timer/Counter, 8-bit
|
||||
const (
|
||||
// TCCR0B: Timer/Counter Control Register B
|
||||
TCCR0B_FOC0A = 0x80 // Force Output Compare A
|
||||
TCCR0B_FOC0B = 0x40 // Force Output Compare B
|
||||
TCCR0B_WGM02 = 0x8
|
||||
TCCR0B_CS0 = 0x7 // Clock Select
|
||||
|
||||
// TCCR0A: Timer/Counter Control Register A
|
||||
TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode
|
||||
TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm
|
||||
TCCR0A_WGM0 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TIMSK0: Timer/Counter0 Interrupt Mask Register
|
||||
TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable
|
||||
TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable
|
||||
TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable
|
||||
|
||||
// TIFR0: Timer/Counter0 Interrupt Flag register
|
||||
TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B
|
||||
TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A
|
||||
TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag
|
||||
)
|
||||
|
||||
// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async
|
||||
const (
|
||||
// TIMSK2: Timer/Counter Interrupt Mask register
|
||||
TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable
|
||||
TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable
|
||||
TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable
|
||||
|
||||
// TIFR2: Timer/Counter Interrupt Flag Register
|
||||
TIFR2_OCF2B = 0x4 // Output Compare Flag 2B
|
||||
TIFR2_OCF2A = 0x2 // Output Compare Flag 2A
|
||||
TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag
|
||||
|
||||
// TCCR2A: Timer/Counter2 Control Register A
|
||||
TCCR2A_COM2A = 0xc0 // Compare Output Mode bits
|
||||
TCCR2A_COM2B = 0x30 // Compare Output Mode bits
|
||||
TCCR2A_WGM2 = 0x3 // Waveform Genration Mode
|
||||
|
||||
// TCCR2B: Timer/Counter2 Control Register B
|
||||
TCCR2B_FOC2A = 0x80 // Force Output Compare A
|
||||
TCCR2B_FOC2B = 0x40 // Force Output Compare B
|
||||
TCCR2B_WGM22 = 0x8 // Waveform Generation Mode
|
||||
TCCR2B_CS2 = 0x7 // Clock Select bits
|
||||
|
||||
// ASSR: Asynchronous Status Register
|
||||
ASSR_EXCLK = 0x40 // Enable External Clock Input
|
||||
ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2
|
||||
ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy
|
||||
ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy
|
||||
ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy
|
||||
ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy
|
||||
ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy
|
||||
)
|
||||
|
||||
// Bitfields for WDT: Watchdog Timer
|
||||
const (
|
||||
// WDTCSR: Watchdog Timer Control Register
|
||||
WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag
|
||||
WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable
|
||||
WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits
|
||||
WDTCSR_WDCE = 0x10 // Watchdog Change Enable
|
||||
WDTCSR_WDE = 0x8 // Watch Dog Enable
|
||||
)
|
||||
|
||||
// Bitfields for BOOT_LOAD: Bootloader
|
||||
const (
|
||||
// SPMCSR: Store Program Memory Control Register
|
||||
SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable
|
||||
SPMCSR_RWWSB = 0x40 // Read While Write Section Busy
|
||||
SPMCSR_SIGRD = 0x20 // Signature Row Read
|
||||
SPMCSR_RWWSRE = 0x10 // Read While Write section read enable
|
||||
SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set
|
||||
SPMCSR_PGWRT = 0x4 // Page Write
|
||||
SPMCSR_PGERS = 0x2 // Page Erase
|
||||
SPMCSR_SPMEN = 0x1 // Store Program Memory Enable
|
||||
)
|
||||
|
||||
// Bitfields for EXINT: External Interrupts
|
||||
const (
|
||||
// EICRA: External Interrupt Control Register A
|
||||
EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit
|
||||
EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit
|
||||
EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit
|
||||
|
||||
// EIMSK: External Interrupt Mask Register
|
||||
EIMSK_INT = 0x7 // External Interrupt Request 2 Enable
|
||||
|
||||
// EIFR: External Interrupt Flag Register
|
||||
EIFR_INTF = 0x7 // External Interrupt Flags
|
||||
|
||||
// PCMSK3: Pin Change Mask Register 3
|
||||
PCMSK3_PCINT = 0xff // Pin Change Enable Masks
|
||||
|
||||
// PCMSK2: Pin Change Mask Register 2
|
||||
PCMSK2_PCINT = 0xff // Pin Change Enable Masks
|
||||
|
||||
// PCMSK1: Pin Change Mask Register 1
|
||||
PCMSK1_PCINT = 0xff // Pin Change Enable Masks
|
||||
|
||||
// PCMSK0: Pin Change Mask Register 0
|
||||
PCMSK0_PCINT = 0xff // Pin Change Enable Masks
|
||||
|
||||
// PCIFR: Pin Change Interrupt Flag Register
|
||||
PCIFR_PCIF = 0xf // Pin Change Interrupt Flags
|
||||
|
||||
// PCICR: Pin Change Interrupt Control Register
|
||||
PCICR_PCIE = 0xf // Pin Change Interrupt Enables
|
||||
)
|
||||
|
||||
// Bitfields for ADC: Analog-to-Digital Converter
|
||||
const (
|
||||
// ADMUX: The ADC multiplexer Selection Register
|
||||
ADMUX_REFS = 0xc0 // Reference Selection Bits
|
||||
ADMUX_ADLAR = 0x20 // Left Adjust Result
|
||||
ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits
|
||||
|
||||
// ADCSRA: The ADC Control and Status register A
|
||||
ADCSRA_ADEN = 0x80 // ADC Enable
|
||||
ADCSRA_ADSC = 0x40 // ADC Start Conversion
|
||||
ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable
|
||||
ADCSRA_ADIF = 0x10 // ADC Interrupt Flag
|
||||
ADCSRA_ADIE = 0x8 // ADC Interrupt Enable
|
||||
ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits
|
||||
|
||||
// DIDR0: Digital Input Disable Register
|
||||
DIDR0_ADC7D = 0x80
|
||||
DIDR0_ADC6D = 0x40
|
||||
DIDR0_ADC5D = 0x20
|
||||
DIDR0_ADC4D = 0x10
|
||||
DIDR0_ADC3D = 0x8
|
||||
DIDR0_ADC2D = 0x4
|
||||
DIDR0_ADC1D = 0x2
|
||||
DIDR0_ADC0D = 0x1
|
||||
)
|
||||
|
||||
// Bitfields for TC16: Timer/Counter, 16-bit
|
||||
const (
|
||||
// TIMSK1: Timer/Counter1 Interrupt Mask Register
|
||||
TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable
|
||||
TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable
|
||||
TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable
|
||||
TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable
|
||||
|
||||
// TIFR1: Timer/Counter Interrupt Flag register
|
||||
TIFR1_ICF1 = 0x20 // Timer/Counter1 Input Capture Flag
|
||||
TIFR1_OCF1B = 0x4 // Timer/Counter1 Output Compare B Match Flag
|
||||
TIFR1_OCF1A = 0x2 // Timer/Counter1 Output Compare A Match Flag
|
||||
TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag
|
||||
|
||||
// TCCR1A: Timer/Counter1 Control Register A
|
||||
TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits
|
||||
TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits
|
||||
TCCR1A_WGM1 = 0x3 // Pulse Width Modulator Select Bits
|
||||
|
||||
// TCCR1B: Timer/Counter1 Control Register B
|
||||
TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler
|
||||
TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select
|
||||
TCCR1B_WGM1 = 0x18 // Waveform Generation Mode Bits
|
||||
TCCR1B_CS1 = 0x7 // Clock Select1 bits
|
||||
|
||||
// TCCR1C: Timer/Counter1 Control Register C
|
||||
TCCR1C_FOC1A = 0x80 // Force Output Compare for Channel A
|
||||
TCCR1C_FOC1B = 0x40 // Force Output Compare for Channel B
|
||||
)
|
||||
|
||||
// Bitfields for EEPROM: EEPROM
|
||||
const (
|
||||
// EECR: EEPROM Control Register
|
||||
EECR_EEPM = 0x30 // EEPROM Programming Mode Bits
|
||||
EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable
|
||||
EECR_EEMPE = 0x4 // EEPROM Master Write Enable
|
||||
EECR_EEPE = 0x2 // EEPROM Write Enable
|
||||
EECR_EERE = 0x1 // EEPROM Read Enable
|
||||
)
|
||||
|
||||
// Bitfields for SPI: Serial Peripheral Interface
|
||||
const (
|
||||
// SPSR0: SPI Status Register
|
||||
SPSR0_SPIF0 = 0x80 // SPI Interrupt Flag
|
||||
SPSR0_WCOL0 = 0x40 // Write Collision Flag
|
||||
SPSR0_SPI2X0 = 0x1 // Double SPI Speed Bit
|
||||
|
||||
// SPCR0: SPI Control Register
|
||||
SPCR0_SPIE0 = 0x80 // SPI Interrupt Enable
|
||||
SPCR0_SPE0 = 0x40 // SPI Enable
|
||||
SPCR0_DORD0 = 0x20 // Data Order
|
||||
SPCR0_MSTR0 = 0x10 // Master/Slave Select
|
||||
SPCR0_CPOL0 = 0x8 // Clock polarity
|
||||
SPCR0_CPHA0 = 0x4 // Clock Phase
|
||||
SPCR0_SPR10 = 0x2 // SPI Clock Rate Select 1
|
||||
SPCR0_SPR00 = 0x1 // SPI Clock Rate Select 0
|
||||
)
|
||||
|
||||
// Bitfields for TWI: Two Wire Serial Interface
|
||||
const (
|
||||
// TWAMR: TWI (Slave) Address Mask Register
|
||||
TWAMR_TWAM = 0xfe
|
||||
|
||||
// TWCR: TWI Control Register
|
||||
TWCR_TWINT = 0x80 // TWI Interrupt Flag
|
||||
TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit
|
||||
TWCR_TWSTA = 0x20 // TWI Start Condition Bit
|
||||
TWCR_TWSTO = 0x10 // TWI Stop Condition Bit
|
||||
TWCR_TWWC = 0x8 // TWI Write Collition Flag
|
||||
TWCR_TWEN = 0x4 // TWI Enable Bit
|
||||
TWCR_TWIE = 0x1 // TWI Interrupt Enable
|
||||
|
||||
// TWSR: TWI Status Register
|
||||
TWSR_TWS = 0xf8 // TWI Status
|
||||
TWSR_TWPS = 0x3 // TWI Prescaler
|
||||
|
||||
// TWAR: TWI (Slave) Address register
|
||||
TWAR_TWA = 0xfe // TWI (Slave) Address register Bits
|
||||
TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit
|
||||
)
|
||||
|
||||
// Bitfields for CPU: CPU Registers
|
||||
const (
|
||||
// SREG: Status Register
|
||||
SREG_I = 0x80 // Global Interrupt Enable
|
||||
SREG_T = 0x40 // Bit Copy Storage
|
||||
SREG_H = 0x20 // Half Carry Flag
|
||||
SREG_S = 0x10 // Sign Bit
|
||||
SREG_V = 0x8 // Two's Complement Overflow Flag
|
||||
SREG_N = 0x4 // Negative Flag
|
||||
SREG_Z = 0x2 // Zero Flag
|
||||
SREG_C = 0x1 // Carry Flag
|
||||
|
||||
// OSCCAL: Oscillator Calibration Value
|
||||
OSCCAL_OSCCAL = 0xff // Oscillator Calibration
|
||||
|
||||
// CLKPR
|
||||
CLKPR_CLKPCE = 0x80
|
||||
CLKPR_CLKPS = 0xf
|
||||
|
||||
// SMCR: Sleep Mode Control Register
|
||||
SMCR_SM = 0xe // Sleep Mode Select bits
|
||||
SMCR_SE = 0x1 // Sleep Enable
|
||||
|
||||
// GPIOR2: General Purpose IO Register 2
|
||||
GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis
|
||||
|
||||
// GPIOR1: General Purpose IO Register 1
|
||||
GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis
|
||||
|
||||
// GPIOR0: General Purpose IO Register 0
|
||||
GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7
|
||||
GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6
|
||||
GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5
|
||||
GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4
|
||||
GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3
|
||||
GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2
|
||||
GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1
|
||||
GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0
|
||||
|
||||
// PRR0: Power Reduction Register0
|
||||
PRR0_PRTWI = 0x80 // Power Reduction TWI
|
||||
PRR0_PRTIM2 = 0x40 // Power Reduction Timer/Counter2
|
||||
PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0
|
||||
PRR0_PRUSART1 = 0x10 // Power Reduction USART1
|
||||
PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1
|
||||
PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface
|
||||
PRR0_PRUSART0 = 0x2 // Power Reduction USART0
|
||||
PRR0_PRADC = 0x1 // Power Reduction ADC
|
||||
)
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from ATmega164PA.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x4000;
|
||||
__ram_size = 0x400;
|
||||
__num_isrs = 31;
|
||||
|
|
@ -1,605 +0,0 @@
|
|||
// Automatically generated file. DO NOT EDIT.
|
||||
// Generated by gen-device.py from ATmega165A.atdf, see http://packs.download.atmel.com/
|
||||
|
||||
// +build avr,atmega165a
|
||||
|
||||
// Device information for the ATmega165A.
|
||||
//
|
||||
package avr
|
||||
|
||||
// Magic type name for the compiler.
|
||||
type __reg uint8
|
||||
|
||||
// Export this magic type name.
|
||||
type RegValue = __reg
|
||||
|
||||
// Some information about this device.
|
||||
const (
|
||||
DEVICE = "ATmega165A"
|
||||
ARCH = "AVR8"
|
||||
FAMILY = "megaAVR"
|
||||
)
|
||||
|
||||
// Interrupts
|
||||
const (
|
||||
IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet.
|
||||
IRQ_INT0 = 1 // External Interrupt Request 0
|
||||
IRQ_PCINT0 = 2 // Pin Change Interrupt Request 0
|
||||
IRQ_PCINT1 = 3 // Pin Change Interrupt Request 1
|
||||
IRQ_TIMER2_COMP = 4 // Timer/Counter2 Compare Match
|
||||
IRQ_TIMER2_OVF = 5 // Timer/Counter2 Overflow
|
||||
IRQ_TIMER1_CAPT = 6 // Timer/Counter1 Capture Event
|
||||
IRQ_TIMER1_COMPA = 7 // Timer/Counter1 Compare Match A
|
||||
IRQ_TIMER1_COMPB = 8 // Timer/Counter Compare Match B
|
||||
IRQ_TIMER1_OVF = 9 // Timer/Counter1 Overflow
|
||||
IRQ_TIMER0_COMP = 10 // Timer/Counter0 Compare Match
|
||||
IRQ_TIMER0_OVF = 11 // Timer/Counter0 Overflow
|
||||
IRQ_SPI_STC = 12 // SPI Serial Transfer Complete
|
||||
IRQ_USART0_RX = 13 // USART0, Rx Complete
|
||||
IRQ_USART0_UDRE = 14 // USART0 Data register Empty
|
||||
IRQ_USART0_TX = 15 // USART0, Tx Complete
|
||||
IRQ_USI_START = 16 // USI Start Condition
|
||||
IRQ_USI_OVERFLOW = 17 // USI Overflow
|
||||
IRQ_ANALOG_COMP = 18 // Analog Comparator
|
||||
IRQ_ADC = 19 // ADC Conversion Complete
|
||||
IRQ_EE_READY = 20 // EEPROM Ready
|
||||
IRQ_SPM_READY = 21 // Store Program Memory Read
|
||||
IRQ_max = 21 // Highest interrupt number on this device.
|
||||
)
|
||||
|
||||
// Peripherals
|
||||
var (
|
||||
// Fuses
|
||||
FUSE = struct {
|
||||
EXTENDED __reg
|
||||
HIGH __reg
|
||||
LOW __reg
|
||||
}{
|
||||
EXTENDED: 0x2,
|
||||
HIGH: 0x1,
|
||||
LOW: 0x0,
|
||||
}
|
||||
|
||||
// Lockbits
|
||||
LOCKBIT = struct {
|
||||
LOCKBIT __reg
|
||||
}{
|
||||
LOCKBIT: 0x0,
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit
|
||||
TC8 = struct {
|
||||
TCCR0A __reg
|
||||
TCNT0 __reg
|
||||
OCR0A __reg
|
||||
TIMSK0 __reg
|
||||
TIFR0 __reg
|
||||
}{
|
||||
TCCR0A: 0x44, // Timer/Counter0 Control Register
|
||||
TCNT0: 0x46, // Timer/Counter0
|
||||
OCR0A: 0x47, // Timer/Counter0 Output Compare Register
|
||||
TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register
|
||||
TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register
|
||||
}
|
||||
|
||||
// Timer/Counter, 16-bit
|
||||
TC16 = struct {
|
||||
TCCR1A __reg
|
||||
TCCR1B __reg
|
||||
TCCR1C __reg
|
||||
TCNT1L __reg
|
||||
TCNT1H __reg
|
||||
OCR1AL __reg
|
||||
OCR1AH __reg
|
||||
OCR1BL __reg
|
||||
OCR1BH __reg
|
||||
ICR1L __reg
|
||||
ICR1H __reg
|
||||
TIMSK1 __reg
|
||||
TIFR1 __reg
|
||||
}{
|
||||
TCCR1A: 0x80, // Timer/Counter1 Control Register A
|
||||
TCCR1B: 0x81, // Timer/Counter1 Control Register B
|
||||
TCCR1C: 0x82, // Timer/Counter 1 Control Register C
|
||||
TCNT1L: 0x84, // Timer/Counter1 Bytes
|
||||
TCNT1H: 0x84, // Timer/Counter1 Bytes
|
||||
OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes
|
||||
OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes
|
||||
OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes
|
||||
OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes
|
||||
ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register
|
||||
TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit Async
|
||||
TC8_ASYNC = struct {
|
||||
TCCR2A __reg
|
||||
TCNT2 __reg
|
||||
OCR2A __reg
|
||||
TIMSK2 __reg
|
||||
TIFR2 __reg
|
||||
ASSR __reg
|
||||
}{
|
||||
TCCR2A: 0xb0, // Timer/Counter2 Control Register
|
||||
TCNT2: 0xb2, // Timer/Counter2
|
||||
OCR2A: 0xb3, // Timer/Counter2 Output Compare Register
|
||||
TIMSK2: 0x70, // Timer/Counter2 Interrupt Mask register
|
||||
TIFR2: 0x37, // Timer/Counter2 Interrupt Flag Register
|
||||
ASSR: 0xb6, // Asynchronous Status Register
|
||||
}
|
||||
|
||||
// Watchdog Timer
|
||||
WDT = struct {
|
||||
WDTCR __reg
|
||||
}{
|
||||
WDTCR: 0x60, // Watchdog Timer Control Register
|
||||
}
|
||||
|
||||
// EEPROM
|
||||
EEPROM = struct {
|
||||
EEARL __reg
|
||||
EEARH __reg
|
||||
EEDR __reg
|
||||
EECR __reg
|
||||
}{
|
||||
EEARL: 0x41, // EEPROM Address Register Bytes
|
||||
EEARH: 0x41, // EEPROM Address Register Bytes
|
||||
EEDR: 0x40, // EEPROM Data Register
|
||||
EECR: 0x3f, // EEPROM Control Register
|
||||
}
|
||||
|
||||
// Serial Peripheral Interface
|
||||
SPI = struct {
|
||||
SPCR __reg
|
||||
SPSR __reg
|
||||
SPDR __reg
|
||||
}{
|
||||
SPCR: 0x4c, // SPI Control Register
|
||||
SPSR: 0x4d, // SPI Status Register
|
||||
SPDR: 0x4e, // SPI Data Register
|
||||
}
|
||||
|
||||
// I/O Port
|
||||
PORT = struct {
|
||||
PORTA __reg
|
||||
DDRA __reg
|
||||
PINA __reg
|
||||
PORTB __reg
|
||||
DDRB __reg
|
||||
PINB __reg
|
||||
PORTC __reg
|
||||
DDRC __reg
|
||||
PINC __reg
|
||||
PORTD __reg
|
||||
DDRD __reg
|
||||
PIND __reg
|
||||
PORTE __reg
|
||||
DDRE __reg
|
||||
PINE __reg
|
||||
PORTF __reg
|
||||
DDRF __reg
|
||||
PINF __reg
|
||||
PORTG __reg
|
||||
DDRG __reg
|
||||
PING __reg
|
||||
}{
|
||||
PORTA: 0x22, // Port A Data Register
|
||||
DDRA: 0x21, // Port A Data Direction Register
|
||||
PINA: 0x20, // Port A Input Pins
|
||||
PORTB: 0x25, // Port B Data Register
|
||||
DDRB: 0x24, // Port B Data Direction Register
|
||||
PINB: 0x23, // Port B Input Pins
|
||||
PORTC: 0x28, // Port C Data Register
|
||||
DDRC: 0x27, // Port C Data Direction Register
|
||||
PINC: 0x26, // Port C Input Pins
|
||||
PORTD: 0x2b, // Port D Data Register
|
||||
DDRD: 0x2a, // Port D Data Direction Register
|
||||
PIND: 0x29, // Port D Input Pins
|
||||
PORTE: 0x2e, // Data Register, Port E
|
||||
DDRE: 0x2d, // Data Direction Register, Port E
|
||||
PINE: 0x2c, // Input Pins, Port E
|
||||
PORTF: 0x31, // Data Register, Port F
|
||||
DDRF: 0x30, // Data Direction Register, Port F
|
||||
PINF: 0x2f, // Input Pins, Port F
|
||||
PORTG: 0x34, // Port G Data Register
|
||||
DDRG: 0x33, // Port G Data Direction Register
|
||||
PING: 0x32, // Port G Input Pins
|
||||
}
|
||||
|
||||
// Analog Comparator
|
||||
AC = struct {
|
||||
ACSR __reg
|
||||
DIDR1 __reg
|
||||
}{
|
||||
ACSR: 0x50, // Analog Comparator Control And Status Register
|
||||
DIDR1: 0x7f, // Digital Input Disable Register 1
|
||||
}
|
||||
|
||||
// JTAG Interface
|
||||
JTAG = struct {
|
||||
OCDR __reg
|
||||
}{
|
||||
OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory
|
||||
}
|
||||
|
||||
// Universal Serial Interface
|
||||
USI = struct {
|
||||
USIDR __reg
|
||||
USISR __reg
|
||||
USICR __reg
|
||||
}{
|
||||
USIDR: 0xba, // USI Data Register
|
||||
USISR: 0xb9, // USI Status Register
|
||||
USICR: 0xb8, // USI Control Register
|
||||
}
|
||||
|
||||
// Analog-to-Digital Converter
|
||||
ADC = struct {
|
||||
ADMUX __reg
|
||||
ADCSRA __reg
|
||||
ADCL __reg
|
||||
ADCH __reg
|
||||
DIDR0 __reg
|
||||
}{
|
||||
ADMUX: 0x7c, // The ADC multiplexer Selection Register
|
||||
ADCSRA: 0x7a, // The ADC Control and Status register
|
||||
ADCL: 0x78, // ADC Data Register Bytes
|
||||
ADCH: 0x78, // ADC Data Register Bytes
|
||||
DIDR0: 0x7e, // Digital Input Disable Register 0
|
||||
}
|
||||
|
||||
// Bootloader
|
||||
BOOT_LOAD = struct {
|
||||
SPMCSR __reg
|
||||
}{
|
||||
SPMCSR: 0x57, // Store Program Memory Control Register
|
||||
}
|
||||
|
||||
// USART
|
||||
USART = struct {
|
||||
UDR0 __reg
|
||||
UCSR0A __reg
|
||||
UCSR0B __reg
|
||||
UCSR0C __reg
|
||||
UBRR0L __reg
|
||||
UBRR0H __reg
|
||||
}{
|
||||
UDR0: 0xc6, // USART I/O Data Register
|
||||
UCSR0A: 0xc0, // USART Control and Status Register A
|
||||
UCSR0B: 0xc1, // USART Control and Status Register B
|
||||
UCSR0C: 0xc2, // USART Control and Status Register C
|
||||
UBRR0L: 0xc4, // USART Baud Rate Register Bytes
|
||||
UBRR0H: 0xc4, // USART Baud Rate Register Bytes
|
||||
}
|
||||
|
||||
// External Interrupts
|
||||
EXINT = struct {
|
||||
EICRA __reg
|
||||
EIMSK __reg
|
||||
EIFR __reg
|
||||
PCMSK1 __reg
|
||||
PCMSK0 __reg
|
||||
}{
|
||||
EICRA: 0x69, // External Interrupt Control Register
|
||||
EIMSK: 0x3d, // External Interrupt Mask Register
|
||||
EIFR: 0x3c, // External Interrupt Flag Register
|
||||
PCMSK1: 0x6c, // Pin Change Mask Register 1
|
||||
PCMSK0: 0x6b, // Pin Change Mask Register 0
|
||||
}
|
||||
|
||||
// CPU Registers
|
||||
CPU = struct {
|
||||
SREG __reg
|
||||
SPL __reg
|
||||
SPH __reg
|
||||
OSCCAL __reg
|
||||
CLKPR __reg
|
||||
PRR __reg
|
||||
SMCR __reg
|
||||
GPIOR2 __reg
|
||||
GPIOR1 __reg
|
||||
GPIOR0 __reg
|
||||
}{
|
||||
SREG: 0x5f, // Status Register
|
||||
SPL: 0x5d, // Stack Pointer
|
||||
SPH: 0x5d, // Stack Pointer
|
||||
OSCCAL: 0x66, // Oscillator Calibration Value
|
||||
CLKPR: 0x61, // Clock Prescale Register
|
||||
PRR: 0x64, // Power Reduction Register
|
||||
SMCR: 0x53, // Sleep Mode Control Register
|
||||
GPIOR2: 0x4b, // General Purpose IO Register 2
|
||||
GPIOR1: 0x4a, // General Purpose IO Register 1
|
||||
GPIOR0: 0x3e, // General Purpose IO Register 0
|
||||
}
|
||||
)
|
||||
|
||||
// Bitfields for FUSE: Fuses
|
||||
const (
|
||||
// EXTENDED
|
||||
EXTENDED_BODLEVEL = 0xe // Brown-out Detector trigger level
|
||||
EXTENDED_RSTDISBL = 0x1 // Disable external reset
|
||||
|
||||
// HIGH
|
||||
HIGH_OCDEN = 0x80 // On-Chip Debug Enabled
|
||||
HIGH_JTAGEN = 0x40 // JTAG Interface Enabled
|
||||
HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled
|
||||
HIGH_WDTON = 0x10 // Watchdog timer always on
|
||||
HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle
|
||||
HIGH_BOOTSZ = 0x6 // Select Boot Size
|
||||
HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled
|
||||
|
||||
// LOW
|
||||
LOW_CKDIV8 = 0x80 // Divide clock by 8 internally
|
||||
LOW_CKOUT = 0x40 // Clock output on PORTE7
|
||||
LOW_SUT_CKSEL = 0x3f // Select Clock Source
|
||||
)
|
||||
|
||||
// Bitfields for LOCKBIT: Lockbits
|
||||
const (
|
||||
// LOCKBIT
|
||||
LOCKBIT_LB = 0x3 // Memory Lock
|
||||
LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode
|
||||
LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode
|
||||
)
|
||||
|
||||
// Bitfields for TC8: Timer/Counter, 8-bit
|
||||
const (
|
||||
// TCCR0A: Timer/Counter0 Control Register
|
||||
TCCR0A_FOC0A = 0x80 // Force Output Compare
|
||||
TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0
|
||||
TCCR0A_COM0A = 0x30 // Compare Match Output Modes
|
||||
TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1
|
||||
TCCR0A_CS0 = 0x7 // Clock Selects
|
||||
|
||||
// TIMSK0: Timer/Counter0 Interrupt Mask Register
|
||||
TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable
|
||||
TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable
|
||||
|
||||
// TIFR0: Timer/Counter0 Interrupt Flag register
|
||||
TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0
|
||||
TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag
|
||||
)
|
||||
|
||||
// Bitfields for TC16: Timer/Counter, 16-bit
|
||||
const (
|
||||
// TCCR1A: Timer/Counter1 Control Register A
|
||||
TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits
|
||||
TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits
|
||||
TCCR1A_WGM1 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TCCR1B: Timer/Counter1 Control Register B
|
||||
TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler
|
||||
TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select
|
||||
TCCR1B_WGM1 = 0x18 // Waveform Generation Mode
|
||||
TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1
|
||||
|
||||
// TCCR1C: Timer/Counter 1 Control Register C
|
||||
TCCR1C_FOC1A = 0x80 // Force Output Compare 1A
|
||||
TCCR1C_FOC1B = 0x40 // Force Output Compare 1B
|
||||
|
||||
// TIMSK1: Timer/Counter1 Interrupt Mask Register
|
||||
TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable
|
||||
TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable
|
||||
TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable
|
||||
TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable
|
||||
|
||||
// TIFR1: Timer/Counter1 Interrupt Flag register
|
||||
TIFR1_ICF1 = 0x20 // Input Capture Flag 1
|
||||
TIFR1_OCF1B = 0x4 // Output Compare Flag 1B
|
||||
TIFR1_OCF1A = 0x2 // Output Compare Flag 1A
|
||||
TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag
|
||||
)
|
||||
|
||||
// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async
|
||||
const (
|
||||
// TCCR2A: Timer/Counter2 Control Register
|
||||
TCCR2A_FOC2A = 0x80 // Force Output Compare A
|
||||
TCCR2A_WGM20 = 0x40 // Waveform Generation Mode
|
||||
TCCR2A_COM2A = 0x30 // Compare Output Mode bits
|
||||
TCCR2A_WGM21 = 0x8 // Waveform Generation Mode
|
||||
TCCR2A_CS2 = 0x7 // Clock Select bits
|
||||
|
||||
// TIMSK2: Timer/Counter2 Interrupt Mask register
|
||||
TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable
|
||||
TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable
|
||||
|
||||
// TIFR2: Timer/Counter2 Interrupt Flag Register
|
||||
TIFR2_OCF2A = 0x2 // Timer/Counter2 Output Compare Flag 2
|
||||
TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag
|
||||
|
||||
// ASSR: Asynchronous Status Register
|
||||
ASSR_EXCLK = 0x10 // Enable External Clock Interrupt
|
||||
ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2
|
||||
ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy
|
||||
ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy
|
||||
ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy
|
||||
)
|
||||
|
||||
// Bitfields for WDT: Watchdog Timer
|
||||
const (
|
||||
// WDTCR: Watchdog Timer Control Register
|
||||
WDTCR_WDCE = 0x10 // Watchdog Change Enable
|
||||
WDTCR_WDE = 0x8 // Watch Dog Enable
|
||||
WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits
|
||||
)
|
||||
|
||||
// Bitfields for EEPROM: EEPROM
|
||||
const (
|
||||
// EECR: EEPROM Control Register
|
||||
EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable
|
||||
EECR_EEMWE = 0x4 // EEPROM Master Write Enable
|
||||
EECR_EEWE = 0x2 // EEPROM Write Enable
|
||||
EECR_EERE = 0x1 // EEPROM Read Enable
|
||||
)
|
||||
|
||||
// Bitfields for SPI: Serial Peripheral Interface
|
||||
const (
|
||||
// SPCR: SPI Control Register
|
||||
SPCR_SPIE = 0x80 // SPI Interrupt Enable
|
||||
SPCR_SPE = 0x40 // SPI Enable
|
||||
SPCR_DORD = 0x20 // Data Order
|
||||
SPCR_MSTR = 0x10 // Master/Slave Select
|
||||
SPCR_CPOL = 0x8 // Clock polarity
|
||||
SPCR_CPHA = 0x4 // Clock Phase
|
||||
SPCR_SPR = 0x3 // SPI Clock Rate Selects
|
||||
|
||||
// SPSR: SPI Status Register
|
||||
SPSR_SPIF = 0x80 // SPI Interrupt Flag
|
||||
SPSR_WCOL = 0x40 // Write Collision Flag
|
||||
SPSR_SPI2X = 0x1 // Double SPI Speed Bit
|
||||
)
|
||||
|
||||
// Bitfields for AC: Analog Comparator
|
||||
const (
|
||||
// ACSR: Analog Comparator Control And Status Register
|
||||
ACSR_ACD = 0x80 // Analog Comparator Disable
|
||||
ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select
|
||||
ACSR_ACO = 0x20 // Analog Compare Output
|
||||
ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag
|
||||
ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable
|
||||
ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable
|
||||
ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits
|
||||
|
||||
// DIDR1: Digital Input Disable Register 1
|
||||
DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable
|
||||
DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable
|
||||
)
|
||||
|
||||
// Bitfields for USI: Universal Serial Interface
|
||||
const (
|
||||
// USISR: USI Status Register
|
||||
USISR_USISIF = 0x80 // Start Condition Interrupt Flag
|
||||
USISR_USIOIF = 0x40 // Counter Overflow Interrupt Flag
|
||||
USISR_USIPF = 0x20 // Stop Condition Flag
|
||||
USISR_USIDC = 0x10 // Data Output Collision
|
||||
USISR_USICNT = 0xf // USI Counter Value Bits
|
||||
|
||||
// USICR: USI Control Register
|
||||
USICR_USISIE = 0x80 // Start Condition Interrupt Enable
|
||||
USICR_USIOIE = 0x40 // Counter Overflow Interrupt Enable
|
||||
USICR_USIWM = 0x30 // USI Wire Mode Bits
|
||||
USICR_USICS = 0xc // USI Clock Source Select Bits
|
||||
USICR_USICLK = 0x2 // Clock Strobe
|
||||
USICR_USITC = 0x1 // Toggle Clock Port Pin
|
||||
)
|
||||
|
||||
// Bitfields for ADC: Analog-to-Digital Converter
|
||||
const (
|
||||
// ADMUX: The ADC multiplexer Selection Register
|
||||
ADMUX_REFS = 0xc0 // Reference Selection Bits
|
||||
ADMUX_ADLAR = 0x20 // Left Adjust Result
|
||||
ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits
|
||||
|
||||
// ADCSRA: The ADC Control and Status register
|
||||
ADCSRA_ADEN = 0x80 // ADC Enable
|
||||
ADCSRA_ADSC = 0x40 // ADC Start Conversion
|
||||
ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable
|
||||
ADCSRA_ADIF = 0x10 // ADC Interrupt Flag
|
||||
ADCSRA_ADIE = 0x8 // ADC Interrupt Enable
|
||||
ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits
|
||||
|
||||
// DIDR0: Digital Input Disable Register 0
|
||||
DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable
|
||||
DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable
|
||||
DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable
|
||||
DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable
|
||||
DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable
|
||||
DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable
|
||||
DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable
|
||||
DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable
|
||||
)
|
||||
|
||||
// Bitfields for BOOT_LOAD: Bootloader
|
||||
const (
|
||||
// SPMCSR: Store Program Memory Control Register
|
||||
SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable
|
||||
SPMCSR_RWWSB = 0x40 // Read While Write Section Busy
|
||||
SPMCSR_RWWSRE = 0x10 // Read While Write section read enable
|
||||
SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set
|
||||
SPMCSR_PGWRT = 0x4 // Page Write
|
||||
SPMCSR_PGERS = 0x2 // Page Erase
|
||||
SPMCSR_SPMEN = 0x1 // Store Program Memory Enable
|
||||
)
|
||||
|
||||
// Bitfields for USART: USART
|
||||
const (
|
||||
// UCSR0A: USART Control and Status Register A
|
||||
UCSR0A_RXC0 = 0x80 // USART Receive Complete
|
||||
UCSR0A_TXC0 = 0x40 // USART Transmit Complete
|
||||
UCSR0A_UDRE0 = 0x20 // USART Data Register Empty
|
||||
UCSR0A_FE0 = 0x10 // Framing Error
|
||||
UCSR0A_DOR0 = 0x8 // Data OverRun
|
||||
UCSR0A_UPE0 = 0x4 // USART Parity Error
|
||||
UCSR0A_U2X0 = 0x2 // Double the USART Transmission Speed
|
||||
UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode
|
||||
|
||||
// UCSR0B: USART Control and Status Register B
|
||||
UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable
|
||||
UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable
|
||||
UCSR0B_UDRIE0 = 0x20 // USART Data Register Empty Interrupt Enable
|
||||
UCSR0B_RXEN0 = 0x10 // Receiver Enable
|
||||
UCSR0B_TXEN0 = 0x8 // Transmitter Enable
|
||||
UCSR0B_UCSZ02 = 0x4 // Character Size
|
||||
UCSR0B_RXB80 = 0x2 // Receive Data Bit 8
|
||||
UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8
|
||||
|
||||
// UCSR0C: USART Control and Status Register C
|
||||
UCSR0C_UMSEL0 = 0x40 // USART Mode Select
|
||||
UCSR0C_UPM0 = 0x30 // Parity Mode Bits
|
||||
UCSR0C_USBS0 = 0x8 // Stop Bit Select
|
||||
UCSR0C_UCSZ0 = 0x6 // Character Size
|
||||
UCSR0C_UCPOL0 = 0x1 // Clock Polarity
|
||||
)
|
||||
|
||||
// Bitfields for EXINT: External Interrupts
|
||||
const (
|
||||
// EICRA: External Interrupt Control Register
|
||||
EICRA_ISC01 = 0x2 // External Interrupt Sense Control 0 Bit 1
|
||||
EICRA_ISC00 = 0x1 // External Interrupt Sense Control 0 Bit 0
|
||||
|
||||
// EIMSK: External Interrupt Mask Register
|
||||
EIMSK_PCIE = 0x30 // Pin Change Interrupt Enables
|
||||
EIMSK_INT0 = 0x1 // External Interrupt Request 0 Enable
|
||||
|
||||
// EIFR: External Interrupt Flag Register
|
||||
EIFR_PCIF = 0x30 // Pin Change Interrupt Flags
|
||||
EIFR_INTF0 = 0x1 // External Interrupt Flag 0
|
||||
|
||||
// PCMSK1: Pin Change Mask Register 1
|
||||
PCMSK1_PCINT = 0xff // Pin Change Enable Masks
|
||||
|
||||
// PCMSK0: Pin Change Mask Register 0
|
||||
PCMSK0_PCINT = 0xff // Pin Change Enable Masks
|
||||
)
|
||||
|
||||
// Bitfields for CPU: CPU Registers
|
||||
const (
|
||||
// SREG: Status Register
|
||||
SREG_I = 0x80 // Global Interrupt Enable
|
||||
SREG_T = 0x40 // Bit Copy Storage
|
||||
SREG_H = 0x20 // Half Carry Flag
|
||||
SREG_S = 0x10 // Sign Bit
|
||||
SREG_V = 0x8 // Two's Complement Overflow Flag
|
||||
SREG_N = 0x4 // Negative Flag
|
||||
SREG_Z = 0x2 // Zero Flag
|
||||
SREG_C = 0x1 // Carry Flag
|
||||
|
||||
// OSCCAL: Oscillator Calibration Value
|
||||
OSCCAL_OSCCAL = 0xff // Oscillator Calibration
|
||||
|
||||
// CLKPR: Clock Prescale Register
|
||||
CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable
|
||||
CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits
|
||||
|
||||
// PRR: Power Reduction Register
|
||||
PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1
|
||||
PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface
|
||||
PRR_PRUSART0 = 0x2 // Power Reduction USART
|
||||
PRR_PRADC = 0x1 // Power Reduction ADC
|
||||
|
||||
// SMCR: Sleep Mode Control Register
|
||||
SMCR_SM = 0xe // Sleep Mode Select bits
|
||||
SMCR_SE = 0x1 // Sleep Enable
|
||||
)
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from ATmega165A.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x4000;
|
||||
__ram_size = 0x400;
|
||||
__num_isrs = 22;
|
||||
|
|
@ -1,605 +0,0 @@
|
|||
// Automatically generated file. DO NOT EDIT.
|
||||
// Generated by gen-device.py from ATmega165P.atdf, see http://packs.download.atmel.com/
|
||||
|
||||
// +build avr,atmega165p
|
||||
|
||||
// Device information for the ATmega165P.
|
||||
//
|
||||
package avr
|
||||
|
||||
// Magic type name for the compiler.
|
||||
type __reg uint8
|
||||
|
||||
// Export this magic type name.
|
||||
type RegValue = __reg
|
||||
|
||||
// Some information about this device.
|
||||
const (
|
||||
DEVICE = "ATmega165P"
|
||||
ARCH = "AVR8"
|
||||
FAMILY = "megaAVR"
|
||||
)
|
||||
|
||||
// Interrupts
|
||||
const (
|
||||
IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet.
|
||||
IRQ_INT0 = 1 // External Interrupt Request 0
|
||||
IRQ_PCINT0 = 2 // Pin Change Interrupt Request 0
|
||||
IRQ_PCINT1 = 3 // Pin Change Interrupt Request 1
|
||||
IRQ_TIMER2_COMP = 4 // Timer/Counter2 Compare Match
|
||||
IRQ_TIMER2_OVF = 5 // Timer/Counter2 Overflow
|
||||
IRQ_TIMER1_CAPT = 6 // Timer/Counter1 Capture Event
|
||||
IRQ_TIMER1_COMPA = 7 // Timer/Counter1 Compare Match A
|
||||
IRQ_TIMER1_COMPB = 8 // Timer/Counter Compare Match B
|
||||
IRQ_TIMER1_OVF = 9 // Timer/Counter1 Overflow
|
||||
IRQ_TIMER0_COMP = 10 // Timer/Counter0 Compare Match
|
||||
IRQ_TIMER0_OVF = 11 // Timer/Counter0 Overflow
|
||||
IRQ_SPI_STC = 12 // SPI Serial Transfer Complete
|
||||
IRQ_USART0_RX = 13 // USART0, Rx Complete
|
||||
IRQ_USART0_UDRE = 14 // USART0 Data register Empty
|
||||
IRQ_USART0_TX = 15 // USART0, Tx Complete
|
||||
IRQ_USI_START = 16 // USI Start Condition
|
||||
IRQ_USI_OVERFLOW = 17 // USI Overflow
|
||||
IRQ_ANALOG_COMP = 18 // Analog Comparator
|
||||
IRQ_ADC = 19 // ADC Conversion Complete
|
||||
IRQ_EE_READY = 20 // EEPROM Ready
|
||||
IRQ_SPM_READY = 21 // Store Program Memory Read
|
||||
IRQ_max = 21 // Highest interrupt number on this device.
|
||||
)
|
||||
|
||||
// Peripherals
|
||||
var (
|
||||
// Fuses
|
||||
FUSE = struct {
|
||||
EXTENDED __reg
|
||||
HIGH __reg
|
||||
LOW __reg
|
||||
}{
|
||||
EXTENDED: 0x2,
|
||||
HIGH: 0x1,
|
||||
LOW: 0x0,
|
||||
}
|
||||
|
||||
// Lockbits
|
||||
LOCKBIT = struct {
|
||||
LOCKBIT __reg
|
||||
}{
|
||||
LOCKBIT: 0x0,
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit
|
||||
TC8 = struct {
|
||||
TCCR0A __reg
|
||||
TCNT0 __reg
|
||||
OCR0A __reg
|
||||
TIMSK0 __reg
|
||||
TIFR0 __reg
|
||||
}{
|
||||
TCCR0A: 0x44, // Timer/Counter0 Control Register
|
||||
TCNT0: 0x46, // Timer/Counter0
|
||||
OCR0A: 0x47, // Timer/Counter0 Output Compare Register
|
||||
TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register
|
||||
TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register
|
||||
}
|
||||
|
||||
// Timer/Counter, 16-bit
|
||||
TC16 = struct {
|
||||
TCCR1A __reg
|
||||
TCCR1B __reg
|
||||
TCCR1C __reg
|
||||
TCNT1L __reg
|
||||
TCNT1H __reg
|
||||
OCR1AL __reg
|
||||
OCR1AH __reg
|
||||
OCR1BL __reg
|
||||
OCR1BH __reg
|
||||
ICR1L __reg
|
||||
ICR1H __reg
|
||||
TIMSK1 __reg
|
||||
TIFR1 __reg
|
||||
}{
|
||||
TCCR1A: 0x80, // Timer/Counter1 Control Register A
|
||||
TCCR1B: 0x81, // Timer/Counter1 Control Register B
|
||||
TCCR1C: 0x82, // Timer/Counter 1 Control Register C
|
||||
TCNT1L: 0x84, // Timer/Counter1 Bytes
|
||||
TCNT1H: 0x84, // Timer/Counter1 Bytes
|
||||
OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes
|
||||
OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes
|
||||
OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes
|
||||
OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes
|
||||
ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register
|
||||
TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit Async
|
||||
TC8_ASYNC = struct {
|
||||
TCCR2A __reg
|
||||
TCNT2 __reg
|
||||
OCR2A __reg
|
||||
TIMSK2 __reg
|
||||
TIFR2 __reg
|
||||
ASSR __reg
|
||||
}{
|
||||
TCCR2A: 0xb0, // Timer/Counter2 Control Register
|
||||
TCNT2: 0xb2, // Timer/Counter2
|
||||
OCR2A: 0xb3, // Timer/Counter2 Output Compare Register
|
||||
TIMSK2: 0x70, // Timer/Counter2 Interrupt Mask register
|
||||
TIFR2: 0x37, // Timer/Counter2 Interrupt Flag Register
|
||||
ASSR: 0xb6, // Asynchronous Status Register
|
||||
}
|
||||
|
||||
// Watchdog Timer
|
||||
WDT = struct {
|
||||
WDTCR __reg
|
||||
}{
|
||||
WDTCR: 0x60, // Watchdog Timer Control Register
|
||||
}
|
||||
|
||||
// EEPROM
|
||||
EEPROM = struct {
|
||||
EEARL __reg
|
||||
EEARH __reg
|
||||
EEDR __reg
|
||||
EECR __reg
|
||||
}{
|
||||
EEARL: 0x41, // EEPROM Address Register Bytes
|
||||
EEARH: 0x41, // EEPROM Address Register Bytes
|
||||
EEDR: 0x40, // EEPROM Data Register
|
||||
EECR: 0x3f, // EEPROM Control Register
|
||||
}
|
||||
|
||||
// Serial Peripheral Interface
|
||||
SPI = struct {
|
||||
SPCR __reg
|
||||
SPSR __reg
|
||||
SPDR __reg
|
||||
}{
|
||||
SPCR: 0x4c, // SPI Control Register
|
||||
SPSR: 0x4d, // SPI Status Register
|
||||
SPDR: 0x4e, // SPI Data Register
|
||||
}
|
||||
|
||||
// I/O Port
|
||||
PORT = struct {
|
||||
PORTA __reg
|
||||
DDRA __reg
|
||||
PINA __reg
|
||||
PORTB __reg
|
||||
DDRB __reg
|
||||
PINB __reg
|
||||
PORTC __reg
|
||||
DDRC __reg
|
||||
PINC __reg
|
||||
PORTD __reg
|
||||
DDRD __reg
|
||||
PIND __reg
|
||||
PORTE __reg
|
||||
DDRE __reg
|
||||
PINE __reg
|
||||
PORTF __reg
|
||||
DDRF __reg
|
||||
PINF __reg
|
||||
PORTG __reg
|
||||
DDRG __reg
|
||||
PING __reg
|
||||
}{
|
||||
PORTA: 0x22, // Port A Data Register
|
||||
DDRA: 0x21, // Port A Data Direction Register
|
||||
PINA: 0x20, // Port A Input Pins
|
||||
PORTB: 0x25, // Port B Data Register
|
||||
DDRB: 0x24, // Port B Data Direction Register
|
||||
PINB: 0x23, // Port B Input Pins
|
||||
PORTC: 0x28, // Port C Data Register
|
||||
DDRC: 0x27, // Port C Data Direction Register
|
||||
PINC: 0x26, // Port C Input Pins
|
||||
PORTD: 0x2b, // Port D Data Register
|
||||
DDRD: 0x2a, // Port D Data Direction Register
|
||||
PIND: 0x29, // Port D Input Pins
|
||||
PORTE: 0x2e, // Data Register, Port E
|
||||
DDRE: 0x2d, // Data Direction Register, Port E
|
||||
PINE: 0x2c, // Input Pins, Port E
|
||||
PORTF: 0x31, // Data Register, Port F
|
||||
DDRF: 0x30, // Data Direction Register, Port F
|
||||
PINF: 0x2f, // Input Pins, Port F
|
||||
PORTG: 0x34, // Port G Data Register
|
||||
DDRG: 0x33, // Port G Data Direction Register
|
||||
PING: 0x32, // Port G Input Pins
|
||||
}
|
||||
|
||||
// Analog Comparator
|
||||
AC = struct {
|
||||
ACSR __reg
|
||||
DIDR1 __reg
|
||||
}{
|
||||
ACSR: 0x50, // Analog Comparator Control And Status Register
|
||||
DIDR1: 0x7f, // Digital Input Disable Register 1
|
||||
}
|
||||
|
||||
// JTAG Interface
|
||||
JTAG = struct {
|
||||
OCDR __reg
|
||||
}{
|
||||
OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory
|
||||
}
|
||||
|
||||
// External Interrupts
|
||||
EXINT = struct {
|
||||
EICRA __reg
|
||||
EIMSK __reg
|
||||
EIFR __reg
|
||||
PCMSK1 __reg
|
||||
PCMSK0 __reg
|
||||
}{
|
||||
EICRA: 0x69, // External Interrupt Control Register
|
||||
EIMSK: 0x3d, // External Interrupt Mask Register
|
||||
EIFR: 0x3c, // External Interrupt Flag Register
|
||||
PCMSK1: 0x6c, // Pin Change Mask Register 1
|
||||
PCMSK0: 0x6b, // Pin Change Mask Register 0
|
||||
}
|
||||
|
||||
// Universal Serial Interface
|
||||
USI = struct {
|
||||
USIDR __reg
|
||||
USISR __reg
|
||||
USICR __reg
|
||||
}{
|
||||
USIDR: 0xba, // USI Data Register
|
||||
USISR: 0xb9, // USI Status Register
|
||||
USICR: 0xb8, // USI Control Register
|
||||
}
|
||||
|
||||
// Analog-to-Digital Converter
|
||||
ADC = struct {
|
||||
ADMUX __reg
|
||||
ADCSRA __reg
|
||||
ADCL __reg
|
||||
ADCH __reg
|
||||
DIDR0 __reg
|
||||
}{
|
||||
ADMUX: 0x7c, // The ADC multiplexer Selection Register
|
||||
ADCSRA: 0x7a, // The ADC Control and Status register
|
||||
ADCL: 0x78, // ADC Data Register Bytes
|
||||
ADCH: 0x78, // ADC Data Register Bytes
|
||||
DIDR0: 0x7e, // Digital Input Disable Register 0
|
||||
}
|
||||
|
||||
// Bootloader
|
||||
BOOT_LOAD = struct {
|
||||
SPMCSR __reg
|
||||
}{
|
||||
SPMCSR: 0x57, // Store Program Memory Control Register
|
||||
}
|
||||
|
||||
// USART
|
||||
USART = struct {
|
||||
UDR0 __reg
|
||||
UCSR0A __reg
|
||||
UCSR0B __reg
|
||||
UCSR0C __reg
|
||||
UBRR0L __reg
|
||||
UBRR0H __reg
|
||||
}{
|
||||
UDR0: 0xc6, // USART I/O Data Register
|
||||
UCSR0A: 0xc0, // USART Control and Status Register A
|
||||
UCSR0B: 0xc1, // USART Control and Status Register B
|
||||
UCSR0C: 0xc2, // USART Control and Status Register C
|
||||
UBRR0L: 0xc4, // USART Baud Rate Register Bytes
|
||||
UBRR0H: 0xc4, // USART Baud Rate Register Bytes
|
||||
}
|
||||
|
||||
// CPU Registers
|
||||
CPU = struct {
|
||||
SREG __reg
|
||||
SPL __reg
|
||||
SPH __reg
|
||||
OSCCAL __reg
|
||||
CLKPR __reg
|
||||
PRR __reg
|
||||
SMCR __reg
|
||||
GPIOR2 __reg
|
||||
GPIOR1 __reg
|
||||
GPIOR0 __reg
|
||||
}{
|
||||
SREG: 0x5f, // Status Register
|
||||
SPL: 0x5d, // Stack Pointer
|
||||
SPH: 0x5d, // Stack Pointer
|
||||
OSCCAL: 0x66, // Oscillator Calibration Value
|
||||
CLKPR: 0x61, // Clock Prescale Register
|
||||
PRR: 0x64, // Power Reduction Register
|
||||
SMCR: 0x53, // Sleep Mode Control Register
|
||||
GPIOR2: 0x4b, // General Purpose IO Register 2
|
||||
GPIOR1: 0x4a, // General Purpose IO Register 1
|
||||
GPIOR0: 0x3e, // General Purpose IO Register 0
|
||||
}
|
||||
)
|
||||
|
||||
// Bitfields for FUSE: Fuses
|
||||
const (
|
||||
// EXTENDED
|
||||
EXTENDED_BODLEVEL = 0xe // Brown-out Detector trigger level
|
||||
EXTENDED_RSTDISBL = 0x1 // Disable external reset
|
||||
|
||||
// HIGH
|
||||
HIGH_OCDEN = 0x80 // On-Chip Debug Enabled
|
||||
HIGH_JTAGEN = 0x40 // JTAG Interface Enabled
|
||||
HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled
|
||||
HIGH_WDTON = 0x10 // Watchdog timer always on
|
||||
HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle
|
||||
HIGH_BOOTSZ = 0x6 // Select Boot Size
|
||||
HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled
|
||||
|
||||
// LOW
|
||||
LOW_CKDIV8 = 0x80 // Divide clock by 8 internally
|
||||
LOW_CKOUT = 0x40 // Clock output on PORTE7
|
||||
LOW_SUT_CKSEL = 0x3f // Select Clock Source
|
||||
)
|
||||
|
||||
// Bitfields for LOCKBIT: Lockbits
|
||||
const (
|
||||
// LOCKBIT
|
||||
LOCKBIT_LB = 0x3 // Memory Lock
|
||||
LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode
|
||||
LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode
|
||||
)
|
||||
|
||||
// Bitfields for TC8: Timer/Counter, 8-bit
|
||||
const (
|
||||
// TCCR0A: Timer/Counter0 Control Register
|
||||
TCCR0A_FOC0A = 0x80 // Force Output Compare
|
||||
TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0
|
||||
TCCR0A_COM0A = 0x30 // Compare Match Output Modes
|
||||
TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1
|
||||
TCCR0A_CS0 = 0x7 // Clock Selects
|
||||
|
||||
// TIMSK0: Timer/Counter0 Interrupt Mask Register
|
||||
TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable
|
||||
TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable
|
||||
|
||||
// TIFR0: Timer/Counter0 Interrupt Flag register
|
||||
TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0
|
||||
TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag
|
||||
)
|
||||
|
||||
// Bitfields for TC16: Timer/Counter, 16-bit
|
||||
const (
|
||||
// TCCR1A: Timer/Counter1 Control Register A
|
||||
TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits
|
||||
TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits
|
||||
TCCR1A_WGM1 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TCCR1B: Timer/Counter1 Control Register B
|
||||
TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler
|
||||
TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select
|
||||
TCCR1B_WGM1 = 0x18 // Waveform Generation Mode
|
||||
TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1
|
||||
|
||||
// TCCR1C: Timer/Counter 1 Control Register C
|
||||
TCCR1C_FOC1A = 0x80 // Force Output Compare 1A
|
||||
TCCR1C_FOC1B = 0x40 // Force Output Compare 1B
|
||||
|
||||
// TIMSK1: Timer/Counter1 Interrupt Mask Register
|
||||
TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable
|
||||
TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable
|
||||
TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable
|
||||
TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable
|
||||
|
||||
// TIFR1: Timer/Counter1 Interrupt Flag register
|
||||
TIFR1_ICF1 = 0x20 // Input Capture Flag 1
|
||||
TIFR1_OCF1B = 0x4 // Output Compare Flag 1B
|
||||
TIFR1_OCF1A = 0x2 // Output Compare Flag 1A
|
||||
TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag
|
||||
)
|
||||
|
||||
// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async
|
||||
const (
|
||||
// TCCR2A: Timer/Counter2 Control Register
|
||||
TCCR2A_FOC2A = 0x80 // Force Output Compare A
|
||||
TCCR2A_WGM20 = 0x40 // Waveform Generation Mode
|
||||
TCCR2A_COM2A = 0x30 // Compare Output Mode bits
|
||||
TCCR2A_WGM21 = 0x8 // Waveform Generation Mode
|
||||
TCCR2A_CS2 = 0x7 // Clock Select bits
|
||||
|
||||
// TIMSK2: Timer/Counter2 Interrupt Mask register
|
||||
TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable
|
||||
TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable
|
||||
|
||||
// TIFR2: Timer/Counter2 Interrupt Flag Register
|
||||
TIFR2_OCF2A = 0x2 // Timer/Counter2 Output Compare Flag 2
|
||||
TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag
|
||||
|
||||
// ASSR: Asynchronous Status Register
|
||||
ASSR_EXCLK = 0x10 // Enable External Clock Interrupt
|
||||
ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2
|
||||
ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy
|
||||
ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy
|
||||
ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy
|
||||
)
|
||||
|
||||
// Bitfields for WDT: Watchdog Timer
|
||||
const (
|
||||
// WDTCR: Watchdog Timer Control Register
|
||||
WDTCR_WDCE = 0x10 // Watchdog Change Enable
|
||||
WDTCR_WDE = 0x8 // Watch Dog Enable
|
||||
WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits
|
||||
)
|
||||
|
||||
// Bitfields for EEPROM: EEPROM
|
||||
const (
|
||||
// EECR: EEPROM Control Register
|
||||
EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable
|
||||
EECR_EEMWE = 0x4 // EEPROM Master Write Enable
|
||||
EECR_EEWE = 0x2 // EEPROM Write Enable
|
||||
EECR_EERE = 0x1 // EEPROM Read Enable
|
||||
)
|
||||
|
||||
// Bitfields for SPI: Serial Peripheral Interface
|
||||
const (
|
||||
// SPCR: SPI Control Register
|
||||
SPCR_SPIE = 0x80 // SPI Interrupt Enable
|
||||
SPCR_SPE = 0x40 // SPI Enable
|
||||
SPCR_DORD = 0x20 // Data Order
|
||||
SPCR_MSTR = 0x10 // Master/Slave Select
|
||||
SPCR_CPOL = 0x8 // Clock polarity
|
||||
SPCR_CPHA = 0x4 // Clock Phase
|
||||
SPCR_SPR = 0x3 // SPI Clock Rate Selects
|
||||
|
||||
// SPSR: SPI Status Register
|
||||
SPSR_SPIF = 0x80 // SPI Interrupt Flag
|
||||
SPSR_WCOL = 0x40 // Write Collision Flag
|
||||
SPSR_SPI2X = 0x1 // Double SPI Speed Bit
|
||||
)
|
||||
|
||||
// Bitfields for AC: Analog Comparator
|
||||
const (
|
||||
// ACSR: Analog Comparator Control And Status Register
|
||||
ACSR_ACD = 0x80 // Analog Comparator Disable
|
||||
ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select
|
||||
ACSR_ACO = 0x20 // Analog Compare Output
|
||||
ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag
|
||||
ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable
|
||||
ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable
|
||||
ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits
|
||||
|
||||
// DIDR1: Digital Input Disable Register 1
|
||||
DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable
|
||||
DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable
|
||||
)
|
||||
|
||||
// Bitfields for EXINT: External Interrupts
|
||||
const (
|
||||
// EICRA: External Interrupt Control Register
|
||||
EICRA_ISC01 = 0x2 // External Interrupt Sense Control 0 Bit 1
|
||||
EICRA_ISC00 = 0x1 // External Interrupt Sense Control 0 Bit 0
|
||||
|
||||
// EIMSK: External Interrupt Mask Register
|
||||
EIMSK_PCIE = 0xc0 // Pin Change Interrupt Enables
|
||||
EIMSK_INT0 = 0x1 // External Interrupt Request 0 Enable
|
||||
|
||||
// EIFR: External Interrupt Flag Register
|
||||
EIFR_PCIF = 0xc0 // Pin Change Interrupt Flags
|
||||
EIFR_INTF0 = 0x1 // External Interrupt Flag 0
|
||||
|
||||
// PCMSK1: Pin Change Mask Register 1
|
||||
PCMSK1_PCINT = 0xff // Pin Change Enable Masks
|
||||
|
||||
// PCMSK0: Pin Change Mask Register 0
|
||||
PCMSK0_PCINT = 0xff // Pin Change Enable Masks
|
||||
)
|
||||
|
||||
// Bitfields for USI: Universal Serial Interface
|
||||
const (
|
||||
// USISR: USI Status Register
|
||||
USISR_USISIF = 0x80 // Start Condition Interrupt Flag
|
||||
USISR_USIOIF = 0x40 // Counter Overflow Interrupt Flag
|
||||
USISR_USIPF = 0x20 // Stop Condition Flag
|
||||
USISR_USIDC = 0x10 // Data Output Collision
|
||||
USISR_USICNT = 0xf // USI Counter Value Bits
|
||||
|
||||
// USICR: USI Control Register
|
||||
USICR_USISIE = 0x80 // Start Condition Interrupt Enable
|
||||
USICR_USIOIE = 0x40 // Counter Overflow Interrupt Enable
|
||||
USICR_USIWM = 0x30 // USI Wire Mode Bits
|
||||
USICR_USICS = 0xc // USI Clock Source Select Bits
|
||||
USICR_USICLK = 0x2 // Clock Strobe
|
||||
USICR_USITC = 0x1 // Toggle Clock Port Pin
|
||||
)
|
||||
|
||||
// Bitfields for ADC: Analog-to-Digital Converter
|
||||
const (
|
||||
// ADMUX: The ADC multiplexer Selection Register
|
||||
ADMUX_REFS = 0xc0 // Reference Selection Bits
|
||||
ADMUX_ADLAR = 0x20 // Left Adjust Result
|
||||
ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits
|
||||
|
||||
// ADCSRA: The ADC Control and Status register
|
||||
ADCSRA_ADEN = 0x80 // ADC Enable
|
||||
ADCSRA_ADSC = 0x40 // ADC Start Conversion
|
||||
ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable
|
||||
ADCSRA_ADIF = 0x10 // ADC Interrupt Flag
|
||||
ADCSRA_ADIE = 0x8 // ADC Interrupt Enable
|
||||
ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits
|
||||
|
||||
// DIDR0: Digital Input Disable Register 0
|
||||
DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable
|
||||
DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable
|
||||
DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable
|
||||
DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable
|
||||
DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable
|
||||
DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable
|
||||
DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable
|
||||
DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable
|
||||
)
|
||||
|
||||
// Bitfields for BOOT_LOAD: Bootloader
|
||||
const (
|
||||
// SPMCSR: Store Program Memory Control Register
|
||||
SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable
|
||||
SPMCSR_RWWSB = 0x40 // Read While Write Section Busy
|
||||
SPMCSR_RWWSRE = 0x10 // Read While Write section read enable
|
||||
SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set
|
||||
SPMCSR_PGWRT = 0x4 // Page Write
|
||||
SPMCSR_PGERS = 0x2 // Page Erase
|
||||
SPMCSR_SPMEN = 0x1 // Store Program Memory Enable
|
||||
)
|
||||
|
||||
// Bitfields for USART: USART
|
||||
const (
|
||||
// UCSR0A: USART Control and Status Register A
|
||||
UCSR0A_RXC0 = 0x80 // USART Receive Complete
|
||||
UCSR0A_TXC0 = 0x40 // USART Transmit Complete
|
||||
UCSR0A_UDRE0 = 0x20 // USART Data Register Empty
|
||||
UCSR0A_FE0 = 0x10 // Framing Error
|
||||
UCSR0A_DOR0 = 0x8 // Data OverRun
|
||||
UCSR0A_UPE0 = 0x4 // USART Parity Error
|
||||
UCSR0A_U2X0 = 0x2 // Double the USART Transmission Speed
|
||||
UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode
|
||||
|
||||
// UCSR0B: USART Control and Status Register B
|
||||
UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable
|
||||
UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable
|
||||
UCSR0B_UDRIE0 = 0x20 // USART Data Register Empty Interrupt Enable
|
||||
UCSR0B_RXEN0 = 0x10 // Receiver Enable
|
||||
UCSR0B_TXEN0 = 0x8 // Transmitter Enable
|
||||
UCSR0B_UCSZ02 = 0x4 // Character Size
|
||||
UCSR0B_RXB80 = 0x2 // Receive Data Bit 8
|
||||
UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8
|
||||
|
||||
// UCSR0C: USART Control and Status Register C
|
||||
UCSR0C_UMSEL0 = 0x40 // USART Mode Select
|
||||
UCSR0C_UPM0 = 0x30 // Parity Mode Bits
|
||||
UCSR0C_USBS0 = 0x8 // Stop Bit Select
|
||||
UCSR0C_UCSZ0 = 0x6 // Character Size
|
||||
UCSR0C_UCPOL0 = 0x1 // Clock Polarity
|
||||
)
|
||||
|
||||
// Bitfields for CPU: CPU Registers
|
||||
const (
|
||||
// SREG: Status Register
|
||||
SREG_I = 0x80 // Global Interrupt Enable
|
||||
SREG_T = 0x40 // Bit Copy Storage
|
||||
SREG_H = 0x20 // Half Carry Flag
|
||||
SREG_S = 0x10 // Sign Bit
|
||||
SREG_V = 0x8 // Two's Complement Overflow Flag
|
||||
SREG_N = 0x4 // Negative Flag
|
||||
SREG_Z = 0x2 // Zero Flag
|
||||
SREG_C = 0x1 // Carry Flag
|
||||
|
||||
// OSCCAL: Oscillator Calibration Value
|
||||
OSCCAL_OSCCAL = 0xff // Oscillator Calibration
|
||||
|
||||
// CLKPR: Clock Prescale Register
|
||||
CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable
|
||||
CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits
|
||||
|
||||
// PRR: Power Reduction Register
|
||||
PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1
|
||||
PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface
|
||||
PRR_PRUSART0 = 0x2 // Power Reduction USART
|
||||
PRR_PRADC = 0x1 // Power Reduction ADC
|
||||
|
||||
// SMCR: Sleep Mode Control Register
|
||||
SMCR_SM = 0xe // Sleep Mode Select bits
|
||||
SMCR_SE = 0x1 // Sleep Enable
|
||||
)
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from ATmega165P.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x4000;
|
||||
__ram_size = 0x400;
|
||||
__num_isrs = 22;
|
||||
|
|
@ -1,605 +0,0 @@
|
|||
// Automatically generated file. DO NOT EDIT.
|
||||
// Generated by gen-device.py from ATmega165PA.atdf, see http://packs.download.atmel.com/
|
||||
|
||||
// +build avr,atmega165pa
|
||||
|
||||
// Device information for the ATmega165PA.
|
||||
//
|
||||
package avr
|
||||
|
||||
// Magic type name for the compiler.
|
||||
type __reg uint8
|
||||
|
||||
// Export this magic type name.
|
||||
type RegValue = __reg
|
||||
|
||||
// Some information about this device.
|
||||
const (
|
||||
DEVICE = "ATmega165PA"
|
||||
ARCH = "AVR8"
|
||||
FAMILY = "megaAVR"
|
||||
)
|
||||
|
||||
// Interrupts
|
||||
const (
|
||||
IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet.
|
||||
IRQ_INT0 = 1 // External Interrupt Request 0
|
||||
IRQ_PCINT0 = 2 // Pin Change Interrupt Request 0
|
||||
IRQ_PCINT1 = 3 // Pin Change Interrupt Request 1
|
||||
IRQ_TIMER2_COMP = 4 // Timer/Counter2 Compare Match
|
||||
IRQ_TIMER2_OVF = 5 // Timer/Counter2 Overflow
|
||||
IRQ_TIMER1_CAPT = 6 // Timer/Counter1 Capture Event
|
||||
IRQ_TIMER1_COMPA = 7 // Timer/Counter1 Compare Match A
|
||||
IRQ_TIMER1_COMPB = 8 // Timer/Counter Compare Match B
|
||||
IRQ_TIMER1_OVF = 9 // Timer/Counter1 Overflow
|
||||
IRQ_TIMER0_COMP = 10 // Timer/Counter0 Compare Match
|
||||
IRQ_TIMER0_OVF = 11 // Timer/Counter0 Overflow
|
||||
IRQ_SPI_STC = 12 // SPI Serial Transfer Complete
|
||||
IRQ_USART0_RX = 13 // USART0, Rx Complete
|
||||
IRQ_USART0_UDRE = 14 // USART0 Data register Empty
|
||||
IRQ_USART0_TX = 15 // USART0, Tx Complete
|
||||
IRQ_USI_START = 16 // USI Start Condition
|
||||
IRQ_USI_OVERFLOW = 17 // USI Overflow
|
||||
IRQ_ANALOG_COMP = 18 // Analog Comparator
|
||||
IRQ_ADC = 19 // ADC Conversion Complete
|
||||
IRQ_EE_READY = 20 // EEPROM Ready
|
||||
IRQ_SPM_READY = 21 // Store Program Memory Read
|
||||
IRQ_max = 21 // Highest interrupt number on this device.
|
||||
)
|
||||
|
||||
// Peripherals
|
||||
var (
|
||||
// Fuses
|
||||
FUSE = struct {
|
||||
EXTENDED __reg
|
||||
HIGH __reg
|
||||
LOW __reg
|
||||
}{
|
||||
EXTENDED: 0x2,
|
||||
HIGH: 0x1,
|
||||
LOW: 0x0,
|
||||
}
|
||||
|
||||
// Lockbits
|
||||
LOCKBIT = struct {
|
||||
LOCKBIT __reg
|
||||
}{
|
||||
LOCKBIT: 0x0,
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit
|
||||
TC8 = struct {
|
||||
TCCR0A __reg
|
||||
TCNT0 __reg
|
||||
OCR0A __reg
|
||||
TIMSK0 __reg
|
||||
TIFR0 __reg
|
||||
}{
|
||||
TCCR0A: 0x44, // Timer/Counter0 Control Register
|
||||
TCNT0: 0x46, // Timer/Counter0
|
||||
OCR0A: 0x47, // Timer/Counter0 Output Compare Register
|
||||
TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register
|
||||
TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register
|
||||
}
|
||||
|
||||
// Timer/Counter, 16-bit
|
||||
TC16 = struct {
|
||||
TCCR1A __reg
|
||||
TCCR1B __reg
|
||||
TCCR1C __reg
|
||||
TCNT1L __reg
|
||||
TCNT1H __reg
|
||||
OCR1AL __reg
|
||||
OCR1AH __reg
|
||||
OCR1BL __reg
|
||||
OCR1BH __reg
|
||||
ICR1L __reg
|
||||
ICR1H __reg
|
||||
TIMSK1 __reg
|
||||
TIFR1 __reg
|
||||
}{
|
||||
TCCR1A: 0x80, // Timer/Counter1 Control Register A
|
||||
TCCR1B: 0x81, // Timer/Counter1 Control Register B
|
||||
TCCR1C: 0x82, // Timer/Counter 1 Control Register C
|
||||
TCNT1L: 0x84, // Timer/Counter1 Bytes
|
||||
TCNT1H: 0x84, // Timer/Counter1 Bytes
|
||||
OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes
|
||||
OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes
|
||||
OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes
|
||||
OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes
|
||||
ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register
|
||||
TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit Async
|
||||
TC8_ASYNC = struct {
|
||||
TCCR2A __reg
|
||||
TCNT2 __reg
|
||||
OCR2A __reg
|
||||
TIMSK2 __reg
|
||||
TIFR2 __reg
|
||||
ASSR __reg
|
||||
}{
|
||||
TCCR2A: 0xb0, // Timer/Counter2 Control Register
|
||||
TCNT2: 0xb2, // Timer/Counter2
|
||||
OCR2A: 0xb3, // Timer/Counter2 Output Compare Register
|
||||
TIMSK2: 0x70, // Timer/Counter2 Interrupt Mask register
|
||||
TIFR2: 0x37, // Timer/Counter2 Interrupt Flag Register
|
||||
ASSR: 0xb6, // Asynchronous Status Register
|
||||
}
|
||||
|
||||
// Watchdog Timer
|
||||
WDT = struct {
|
||||
WDTCR __reg
|
||||
}{
|
||||
WDTCR: 0x60, // Watchdog Timer Control Register
|
||||
}
|
||||
|
||||
// EEPROM
|
||||
EEPROM = struct {
|
||||
EEARL __reg
|
||||
EEARH __reg
|
||||
EEDR __reg
|
||||
EECR __reg
|
||||
}{
|
||||
EEARL: 0x41, // EEPROM Address Register Bytes
|
||||
EEARH: 0x41, // EEPROM Address Register Bytes
|
||||
EEDR: 0x40, // EEPROM Data Register
|
||||
EECR: 0x3f, // EEPROM Control Register
|
||||
}
|
||||
|
||||
// Serial Peripheral Interface
|
||||
SPI = struct {
|
||||
SPCR __reg
|
||||
SPSR __reg
|
||||
SPDR __reg
|
||||
}{
|
||||
SPCR: 0x4c, // SPI Control Register
|
||||
SPSR: 0x4d, // SPI Status Register
|
||||
SPDR: 0x4e, // SPI Data Register
|
||||
}
|
||||
|
||||
// I/O Port
|
||||
PORT = struct {
|
||||
PORTA __reg
|
||||
DDRA __reg
|
||||
PINA __reg
|
||||
PORTB __reg
|
||||
DDRB __reg
|
||||
PINB __reg
|
||||
PORTC __reg
|
||||
DDRC __reg
|
||||
PINC __reg
|
||||
PORTD __reg
|
||||
DDRD __reg
|
||||
PIND __reg
|
||||
PORTE __reg
|
||||
DDRE __reg
|
||||
PINE __reg
|
||||
PORTF __reg
|
||||
DDRF __reg
|
||||
PINF __reg
|
||||
PORTG __reg
|
||||
DDRG __reg
|
||||
PING __reg
|
||||
}{
|
||||
PORTA: 0x22, // Port A Data Register
|
||||
DDRA: 0x21, // Port A Data Direction Register
|
||||
PINA: 0x20, // Port A Input Pins
|
||||
PORTB: 0x25, // Port B Data Register
|
||||
DDRB: 0x24, // Port B Data Direction Register
|
||||
PINB: 0x23, // Port B Input Pins
|
||||
PORTC: 0x28, // Port C Data Register
|
||||
DDRC: 0x27, // Port C Data Direction Register
|
||||
PINC: 0x26, // Port C Input Pins
|
||||
PORTD: 0x2b, // Port D Data Register
|
||||
DDRD: 0x2a, // Port D Data Direction Register
|
||||
PIND: 0x29, // Port D Input Pins
|
||||
PORTE: 0x2e, // Data Register, Port E
|
||||
DDRE: 0x2d, // Data Direction Register, Port E
|
||||
PINE: 0x2c, // Input Pins, Port E
|
||||
PORTF: 0x31, // Data Register, Port F
|
||||
DDRF: 0x30, // Data Direction Register, Port F
|
||||
PINF: 0x2f, // Input Pins, Port F
|
||||
PORTG: 0x34, // Port G Data Register
|
||||
DDRG: 0x33, // Port G Data Direction Register
|
||||
PING: 0x32, // Port G Input Pins
|
||||
}
|
||||
|
||||
// Analog Comparator
|
||||
AC = struct {
|
||||
ACSR __reg
|
||||
DIDR1 __reg
|
||||
}{
|
||||
ACSR: 0x50, // Analog Comparator Control And Status Register
|
||||
DIDR1: 0x7f, // Digital Input Disable Register 1
|
||||
}
|
||||
|
||||
// JTAG Interface
|
||||
JTAG = struct {
|
||||
OCDR __reg
|
||||
}{
|
||||
OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory
|
||||
}
|
||||
|
||||
// Universal Serial Interface
|
||||
USI = struct {
|
||||
USIDR __reg
|
||||
USISR __reg
|
||||
USICR __reg
|
||||
}{
|
||||
USIDR: 0xba, // USI Data Register
|
||||
USISR: 0xb9, // USI Status Register
|
||||
USICR: 0xb8, // USI Control Register
|
||||
}
|
||||
|
||||
// Analog-to-Digital Converter
|
||||
ADC = struct {
|
||||
ADMUX __reg
|
||||
ADCSRA __reg
|
||||
ADCL __reg
|
||||
ADCH __reg
|
||||
DIDR0 __reg
|
||||
}{
|
||||
ADMUX: 0x7c, // The ADC multiplexer Selection Register
|
||||
ADCSRA: 0x7a, // The ADC Control and Status register
|
||||
ADCL: 0x78, // ADC Data Register Bytes
|
||||
ADCH: 0x78, // ADC Data Register Bytes
|
||||
DIDR0: 0x7e, // Digital Input Disable Register 0
|
||||
}
|
||||
|
||||
// Bootloader
|
||||
BOOT_LOAD = struct {
|
||||
SPMCSR __reg
|
||||
}{
|
||||
SPMCSR: 0x57, // Store Program Memory Control Register
|
||||
}
|
||||
|
||||
// USART
|
||||
USART = struct {
|
||||
UDR0 __reg
|
||||
UCSR0A __reg
|
||||
UCSR0B __reg
|
||||
UCSR0C __reg
|
||||
UBRR0L __reg
|
||||
UBRR0H __reg
|
||||
}{
|
||||
UDR0: 0xc6, // USART I/O Data Register
|
||||
UCSR0A: 0xc0, // USART Control and Status Register A
|
||||
UCSR0B: 0xc1, // USART Control and Status Register B
|
||||
UCSR0C: 0xc2, // USART Control and Status Register C
|
||||
UBRR0L: 0xc4, // USART Baud Rate Register Bytes
|
||||
UBRR0H: 0xc4, // USART Baud Rate Register Bytes
|
||||
}
|
||||
|
||||
// External Interrupts
|
||||
EXINT = struct {
|
||||
EICRA __reg
|
||||
EIMSK __reg
|
||||
EIFR __reg
|
||||
PCMSK1 __reg
|
||||
PCMSK0 __reg
|
||||
}{
|
||||
EICRA: 0x69, // External Interrupt Control Register
|
||||
EIMSK: 0x3d, // External Interrupt Mask Register
|
||||
EIFR: 0x3c, // External Interrupt Flag Register
|
||||
PCMSK1: 0x6c, // Pin Change Mask Register 1
|
||||
PCMSK0: 0x6b, // Pin Change Mask Register 0
|
||||
}
|
||||
|
||||
// CPU Registers
|
||||
CPU = struct {
|
||||
SREG __reg
|
||||
SPL __reg
|
||||
SPH __reg
|
||||
OSCCAL __reg
|
||||
CLKPR __reg
|
||||
PRR __reg
|
||||
SMCR __reg
|
||||
GPIOR2 __reg
|
||||
GPIOR1 __reg
|
||||
GPIOR0 __reg
|
||||
}{
|
||||
SREG: 0x5f, // Status Register
|
||||
SPL: 0x5d, // Stack Pointer
|
||||
SPH: 0x5d, // Stack Pointer
|
||||
OSCCAL: 0x66, // Oscillator Calibration Value
|
||||
CLKPR: 0x61, // Clock Prescale Register
|
||||
PRR: 0x64, // Power Reduction Register
|
||||
SMCR: 0x53, // Sleep Mode Control Register
|
||||
GPIOR2: 0x4b, // General Purpose IO Register 2
|
||||
GPIOR1: 0x4a, // General Purpose IO Register 1
|
||||
GPIOR0: 0x3e, // General Purpose IO Register 0
|
||||
}
|
||||
)
|
||||
|
||||
// Bitfields for FUSE: Fuses
|
||||
const (
|
||||
// EXTENDED
|
||||
EXTENDED_BODLEVEL = 0xe // Brown-out Detector trigger level
|
||||
EXTENDED_RSTDISBL = 0x1 // Disable external reset
|
||||
|
||||
// HIGH
|
||||
HIGH_OCDEN = 0x80 // On-Chip Debug Enabled
|
||||
HIGH_JTAGEN = 0x40 // JTAG Interface Enabled
|
||||
HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled
|
||||
HIGH_WDTON = 0x10 // Watchdog timer always on
|
||||
HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle
|
||||
HIGH_BOOTSZ = 0x6 // Select Boot Size
|
||||
HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled
|
||||
|
||||
// LOW
|
||||
LOW_CKDIV8 = 0x80 // Divide clock by 8 internally
|
||||
LOW_CKOUT = 0x40 // Clock output on PORTE7
|
||||
LOW_SUT_CKSEL = 0x3f // Select Clock Source
|
||||
)
|
||||
|
||||
// Bitfields for LOCKBIT: Lockbits
|
||||
const (
|
||||
// LOCKBIT
|
||||
LOCKBIT_LB = 0x3 // Memory Lock
|
||||
LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode
|
||||
LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode
|
||||
)
|
||||
|
||||
// Bitfields for TC8: Timer/Counter, 8-bit
|
||||
const (
|
||||
// TCCR0A: Timer/Counter0 Control Register
|
||||
TCCR0A_FOC0A = 0x80 // Force Output Compare
|
||||
TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0
|
||||
TCCR0A_COM0A = 0x30 // Compare Match Output Modes
|
||||
TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1
|
||||
TCCR0A_CS0 = 0x7 // Clock Selects
|
||||
|
||||
// TIMSK0: Timer/Counter0 Interrupt Mask Register
|
||||
TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable
|
||||
TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable
|
||||
|
||||
// TIFR0: Timer/Counter0 Interrupt Flag register
|
||||
TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0
|
||||
TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag
|
||||
)
|
||||
|
||||
// Bitfields for TC16: Timer/Counter, 16-bit
|
||||
const (
|
||||
// TCCR1A: Timer/Counter1 Control Register A
|
||||
TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits
|
||||
TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits
|
||||
TCCR1A_WGM1 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TCCR1B: Timer/Counter1 Control Register B
|
||||
TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler
|
||||
TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select
|
||||
TCCR1B_WGM1 = 0x18 // Waveform Generation Mode
|
||||
TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1
|
||||
|
||||
// TCCR1C: Timer/Counter 1 Control Register C
|
||||
TCCR1C_FOC1A = 0x80 // Force Output Compare 1A
|
||||
TCCR1C_FOC1B = 0x40 // Force Output Compare 1B
|
||||
|
||||
// TIMSK1: Timer/Counter1 Interrupt Mask Register
|
||||
TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable
|
||||
TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable
|
||||
TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable
|
||||
TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable
|
||||
|
||||
// TIFR1: Timer/Counter1 Interrupt Flag register
|
||||
TIFR1_ICF1 = 0x20 // Input Capture Flag 1
|
||||
TIFR1_OCF1B = 0x4 // Output Compare Flag 1B
|
||||
TIFR1_OCF1A = 0x2 // Output Compare Flag 1A
|
||||
TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag
|
||||
)
|
||||
|
||||
// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async
|
||||
const (
|
||||
// TCCR2A: Timer/Counter2 Control Register
|
||||
TCCR2A_FOC2A = 0x80 // Force Output Compare A
|
||||
TCCR2A_WGM20 = 0x40 // Waveform Generation Mode
|
||||
TCCR2A_COM2A = 0x30 // Compare Output Mode bits
|
||||
TCCR2A_WGM21 = 0x8 // Waveform Generation Mode
|
||||
TCCR2A_CS2 = 0x7 // Clock Select bits
|
||||
|
||||
// TIMSK2: Timer/Counter2 Interrupt Mask register
|
||||
TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable
|
||||
TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable
|
||||
|
||||
// TIFR2: Timer/Counter2 Interrupt Flag Register
|
||||
TIFR2_OCF2A = 0x2 // Timer/Counter2 Output Compare Flag 2
|
||||
TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag
|
||||
|
||||
// ASSR: Asynchronous Status Register
|
||||
ASSR_EXCLK = 0x10 // Enable External Clock Interrupt
|
||||
ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2
|
||||
ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy
|
||||
ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy
|
||||
ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy
|
||||
)
|
||||
|
||||
// Bitfields for WDT: Watchdog Timer
|
||||
const (
|
||||
// WDTCR: Watchdog Timer Control Register
|
||||
WDTCR_WDCE = 0x10 // Watchdog Change Enable
|
||||
WDTCR_WDE = 0x8 // Watch Dog Enable
|
||||
WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits
|
||||
)
|
||||
|
||||
// Bitfields for EEPROM: EEPROM
|
||||
const (
|
||||
// EECR: EEPROM Control Register
|
||||
EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable
|
||||
EECR_EEMWE = 0x4 // EEPROM Master Write Enable
|
||||
EECR_EEWE = 0x2 // EEPROM Write Enable
|
||||
EECR_EERE = 0x1 // EEPROM Read Enable
|
||||
)
|
||||
|
||||
// Bitfields for SPI: Serial Peripheral Interface
|
||||
const (
|
||||
// SPCR: SPI Control Register
|
||||
SPCR_SPIE = 0x80 // SPI Interrupt Enable
|
||||
SPCR_SPE = 0x40 // SPI Enable
|
||||
SPCR_DORD = 0x20 // Data Order
|
||||
SPCR_MSTR = 0x10 // Master/Slave Select
|
||||
SPCR_CPOL = 0x8 // Clock polarity
|
||||
SPCR_CPHA = 0x4 // Clock Phase
|
||||
SPCR_SPR = 0x3 // SPI Clock Rate Selects
|
||||
|
||||
// SPSR: SPI Status Register
|
||||
SPSR_SPIF = 0x80 // SPI Interrupt Flag
|
||||
SPSR_WCOL = 0x40 // Write Collision Flag
|
||||
SPSR_SPI2X = 0x1 // Double SPI Speed Bit
|
||||
)
|
||||
|
||||
// Bitfields for AC: Analog Comparator
|
||||
const (
|
||||
// ACSR: Analog Comparator Control And Status Register
|
||||
ACSR_ACD = 0x80 // Analog Comparator Disable
|
||||
ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select
|
||||
ACSR_ACO = 0x20 // Analog Compare Output
|
||||
ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag
|
||||
ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable
|
||||
ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable
|
||||
ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits
|
||||
|
||||
// DIDR1: Digital Input Disable Register 1
|
||||
DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable
|
||||
DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable
|
||||
)
|
||||
|
||||
// Bitfields for USI: Universal Serial Interface
|
||||
const (
|
||||
// USISR: USI Status Register
|
||||
USISR_USISIF = 0x80 // Start Condition Interrupt Flag
|
||||
USISR_USIOIF = 0x40 // Counter Overflow Interrupt Flag
|
||||
USISR_USIPF = 0x20 // Stop Condition Flag
|
||||
USISR_USIDC = 0x10 // Data Output Collision
|
||||
USISR_USICNT = 0xf // USI Counter Value Bits
|
||||
|
||||
// USICR: USI Control Register
|
||||
USICR_USISIE = 0x80 // Start Condition Interrupt Enable
|
||||
USICR_USIOIE = 0x40 // Counter Overflow Interrupt Enable
|
||||
USICR_USIWM = 0x30 // USI Wire Mode Bits
|
||||
USICR_USICS = 0xc // USI Clock Source Select Bits
|
||||
USICR_USICLK = 0x2 // Clock Strobe
|
||||
USICR_USITC = 0x1 // Toggle Clock Port Pin
|
||||
)
|
||||
|
||||
// Bitfields for ADC: Analog-to-Digital Converter
|
||||
const (
|
||||
// ADMUX: The ADC multiplexer Selection Register
|
||||
ADMUX_REFS = 0xc0 // Reference Selection Bits
|
||||
ADMUX_ADLAR = 0x20 // Left Adjust Result
|
||||
ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits
|
||||
|
||||
// ADCSRA: The ADC Control and Status register
|
||||
ADCSRA_ADEN = 0x80 // ADC Enable
|
||||
ADCSRA_ADSC = 0x40 // ADC Start Conversion
|
||||
ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable
|
||||
ADCSRA_ADIF = 0x10 // ADC Interrupt Flag
|
||||
ADCSRA_ADIE = 0x8 // ADC Interrupt Enable
|
||||
ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits
|
||||
|
||||
// DIDR0: Digital Input Disable Register 0
|
||||
DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable
|
||||
DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable
|
||||
DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable
|
||||
DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable
|
||||
DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable
|
||||
DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable
|
||||
DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable
|
||||
DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable
|
||||
)
|
||||
|
||||
// Bitfields for BOOT_LOAD: Bootloader
|
||||
const (
|
||||
// SPMCSR: Store Program Memory Control Register
|
||||
SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable
|
||||
SPMCSR_RWWSB = 0x40 // Read While Write Section Busy
|
||||
SPMCSR_RWWSRE = 0x10 // Read While Write section read enable
|
||||
SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set
|
||||
SPMCSR_PGWRT = 0x4 // Page Write
|
||||
SPMCSR_PGERS = 0x2 // Page Erase
|
||||
SPMCSR_SPMEN = 0x1 // Store Program Memory Enable
|
||||
)
|
||||
|
||||
// Bitfields for USART: USART
|
||||
const (
|
||||
// UCSR0A: USART Control and Status Register A
|
||||
UCSR0A_RXC0 = 0x80 // USART Receive Complete
|
||||
UCSR0A_TXC0 = 0x40 // USART Transmit Complete
|
||||
UCSR0A_UDRE0 = 0x20 // USART Data Register Empty
|
||||
UCSR0A_FE0 = 0x10 // Framing Error
|
||||
UCSR0A_DOR0 = 0x8 // Data OverRun
|
||||
UCSR0A_UPE0 = 0x4 // USART Parity Error
|
||||
UCSR0A_U2X0 = 0x2 // Double the USART Transmission Speed
|
||||
UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode
|
||||
|
||||
// UCSR0B: USART Control and Status Register B
|
||||
UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable
|
||||
UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable
|
||||
UCSR0B_UDRIE0 = 0x20 // USART Data Register Empty Interrupt Enable
|
||||
UCSR0B_RXEN0 = 0x10 // Receiver Enable
|
||||
UCSR0B_TXEN0 = 0x8 // Transmitter Enable
|
||||
UCSR0B_UCSZ02 = 0x4 // Character Size
|
||||
UCSR0B_RXB80 = 0x2 // Receive Data Bit 8
|
||||
UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8
|
||||
|
||||
// UCSR0C: USART Control and Status Register C
|
||||
UCSR0C_UMSEL0 = 0x40 // USART Mode Select
|
||||
UCSR0C_UPM0 = 0x30 // Parity Mode Bits
|
||||
UCSR0C_USBS0 = 0x8 // Stop Bit Select
|
||||
UCSR0C_UCSZ0 = 0x6 // Character Size
|
||||
UCSR0C_UCPOL0 = 0x1 // Clock Polarity
|
||||
)
|
||||
|
||||
// Bitfields for EXINT: External Interrupts
|
||||
const (
|
||||
// EICRA: External Interrupt Control Register
|
||||
EICRA_ISC01 = 0x2 // External Interrupt Sense Control 0 Bit 1
|
||||
EICRA_ISC00 = 0x1 // External Interrupt Sense Control 0 Bit 0
|
||||
|
||||
// EIMSK: External Interrupt Mask Register
|
||||
EIMSK_PCIE = 0x30 // Pin Change Interrupt Enables
|
||||
EIMSK_INT0 = 0x1 // External Interrupt Request 0 Enable
|
||||
|
||||
// EIFR: External Interrupt Flag Register
|
||||
EIFR_PCIF = 0x30 // Pin Change Interrupt Flags
|
||||
EIFR_INTF0 = 0x1 // External Interrupt Flag 0
|
||||
|
||||
// PCMSK1: Pin Change Mask Register 1
|
||||
PCMSK1_PCINT = 0xff // Pin Change Enable Masks
|
||||
|
||||
// PCMSK0: Pin Change Mask Register 0
|
||||
PCMSK0_PCINT = 0xff // Pin Change Enable Masks
|
||||
)
|
||||
|
||||
// Bitfields for CPU: CPU Registers
|
||||
const (
|
||||
// SREG: Status Register
|
||||
SREG_I = 0x80 // Global Interrupt Enable
|
||||
SREG_T = 0x40 // Bit Copy Storage
|
||||
SREG_H = 0x20 // Half Carry Flag
|
||||
SREG_S = 0x10 // Sign Bit
|
||||
SREG_V = 0x8 // Two's Complement Overflow Flag
|
||||
SREG_N = 0x4 // Negative Flag
|
||||
SREG_Z = 0x2 // Zero Flag
|
||||
SREG_C = 0x1 // Carry Flag
|
||||
|
||||
// OSCCAL: Oscillator Calibration Value
|
||||
OSCCAL_OSCCAL = 0xff // Oscillator Calibration
|
||||
|
||||
// CLKPR: Clock Prescale Register
|
||||
CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable
|
||||
CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits
|
||||
|
||||
// PRR: Power Reduction Register
|
||||
PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1
|
||||
PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface
|
||||
PRR_PRUSART0 = 0x2 // Power Reduction USART
|
||||
PRR_PRADC = 0x1 // Power Reduction ADC
|
||||
|
||||
// SMCR: Sleep Mode Control Register
|
||||
SMCR_SM = 0xe // Sleep Mode Select bits
|
||||
SMCR_SE = 0x1 // Sleep Enable
|
||||
)
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from ATmega165PA.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x4000;
|
||||
__ram_size = 0x400;
|
||||
__num_isrs = 22;
|
||||
|
|
@ -1,640 +0,0 @@
|
|||
// Automatically generated file. DO NOT EDIT.
|
||||
// Generated by gen-device.py from ATmega168.atdf, see http://packs.download.atmel.com/
|
||||
|
||||
// +build avr,atmega168
|
||||
|
||||
// Device information for the ATmega168.
|
||||
//
|
||||
package avr
|
||||
|
||||
// Magic type name for the compiler.
|
||||
type __reg uint8
|
||||
|
||||
// Export this magic type name.
|
||||
type RegValue = __reg
|
||||
|
||||
// Some information about this device.
|
||||
const (
|
||||
DEVICE = "ATmega168"
|
||||
ARCH = "AVR8"
|
||||
FAMILY = "megaAVR"
|
||||
)
|
||||
|
||||
// Interrupts
|
||||
const (
|
||||
IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset
|
||||
IRQ_INT0 = 1 // External Interrupt Request 0
|
||||
IRQ_INT1 = 2 // External Interrupt Request 1
|
||||
IRQ_PCINT0 = 3 // Pin Change Interrupt Request 0
|
||||
IRQ_PCINT1 = 4 // Pin Change Interrupt Request 0
|
||||
IRQ_PCINT2 = 5 // Pin Change Interrupt Request 1
|
||||
IRQ_WDT = 6 // Watchdog Time-out Interrupt
|
||||
IRQ_TIMER2_COMPA = 7 // Timer/Counter2 Compare Match A
|
||||
IRQ_TIMER2_COMPB = 8 // Timer/Counter2 Compare Match A
|
||||
IRQ_TIMER2_OVF = 9 // Timer/Counter2 Overflow
|
||||
IRQ_TIMER1_CAPT = 10 // Timer/Counter1 Capture Event
|
||||
IRQ_TIMER1_COMPA = 11 // Timer/Counter1 Compare Match A
|
||||
IRQ_TIMER1_COMPB = 12 // Timer/Counter1 Compare Match B
|
||||
IRQ_TIMER1_OVF = 13 // Timer/Counter1 Overflow
|
||||
IRQ_TIMER0_COMPA = 14 // TimerCounter0 Compare Match A
|
||||
IRQ_TIMER0_COMPB = 15 // TimerCounter0 Compare Match B
|
||||
IRQ_TIMER0_OVF = 16 // Timer/Couner0 Overflow
|
||||
IRQ_SPI_STC = 17 // SPI Serial Transfer Complete
|
||||
IRQ_USART_RX = 18 // USART Rx Complete
|
||||
IRQ_USART_UDRE = 19 // USART, Data Register Empty
|
||||
IRQ_USART_TX = 20 // USART Tx Complete
|
||||
IRQ_ADC = 21 // ADC Conversion Complete
|
||||
IRQ_EE_READY = 22 // EEPROM Ready
|
||||
IRQ_ANALOG_COMP = 23 // Analog Comparator
|
||||
IRQ_TWI = 24 // Two-wire Serial Interface
|
||||
IRQ_SPM_READY = 25 // Store Program Memory Read
|
||||
IRQ_max = 25 // Highest interrupt number on this device.
|
||||
)
|
||||
|
||||
// Peripherals
|
||||
var (
|
||||
// Fuses
|
||||
FUSE = struct {
|
||||
EXTENDED __reg
|
||||
HIGH __reg
|
||||
LOW __reg
|
||||
}{
|
||||
EXTENDED: 0x2,
|
||||
HIGH: 0x1,
|
||||
LOW: 0x0,
|
||||
}
|
||||
|
||||
// Lockbits
|
||||
LOCKBIT = struct {
|
||||
LOCKBIT __reg
|
||||
}{
|
||||
LOCKBIT: 0x0,
|
||||
}
|
||||
|
||||
// USART
|
||||
USART = struct {
|
||||
UDR0 __reg
|
||||
UCSR0A __reg
|
||||
UCSR0B __reg
|
||||
UCSR0C __reg
|
||||
UBRR0L __reg
|
||||
UBRR0H __reg
|
||||
}{
|
||||
UDR0: 0xc6, // USART I/O Data Register
|
||||
UCSR0A: 0xc0, // USART Control and Status Register A
|
||||
UCSR0B: 0xc1, // USART Control and Status Register B
|
||||
UCSR0C: 0xc2, // USART Control and Status Register C
|
||||
UBRR0L: 0xc4, // USART Baud Rate Register Bytes
|
||||
UBRR0H: 0xc4, // USART Baud Rate Register Bytes
|
||||
}
|
||||
|
||||
// Two Wire Serial Interface
|
||||
TWI = struct {
|
||||
TWAMR __reg
|
||||
TWBR __reg
|
||||
TWCR __reg
|
||||
TWSR __reg
|
||||
TWDR __reg
|
||||
TWAR __reg
|
||||
}{
|
||||
TWAMR: 0xbd, // TWI (Slave) Address Mask Register
|
||||
TWBR: 0xb8, // TWI Bit Rate register
|
||||
TWCR: 0xbc, // TWI Control Register
|
||||
TWSR: 0xb9, // TWI Status Register
|
||||
TWDR: 0xbb, // TWI Data register
|
||||
TWAR: 0xba, // TWI (Slave) Address register
|
||||
}
|
||||
|
||||
// Timer/Counter, 16-bit
|
||||
TC16 = struct {
|
||||
TIMSK1 __reg
|
||||
TIFR1 __reg
|
||||
TCCR1A __reg
|
||||
TCCR1B __reg
|
||||
TCCR1C __reg
|
||||
TCNT1L __reg
|
||||
TCNT1H __reg
|
||||
OCR1AL __reg
|
||||
OCR1AH __reg
|
||||
OCR1BL __reg
|
||||
OCR1BH __reg
|
||||
ICR1L __reg
|
||||
ICR1H __reg
|
||||
}{
|
||||
TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register
|
||||
TIFR1: 0x36, // Timer/Counter Interrupt Flag register
|
||||
TCCR1A: 0x80, // Timer/Counter1 Control Register A
|
||||
TCCR1B: 0x81, // Timer/Counter1 Control Register B
|
||||
TCCR1C: 0x82, // Timer/Counter1 Control Register C
|
||||
TCNT1L: 0x84, // Timer/Counter1 Bytes
|
||||
TCNT1H: 0x84, // Timer/Counter1 Bytes
|
||||
OCR1AL: 0x88, // Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1AH: 0x88, // Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register Bytes
|
||||
ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit Async
|
||||
TC8_ASYNC = struct {
|
||||
TIMSK2 __reg
|
||||
TIFR2 __reg
|
||||
TCCR2A __reg
|
||||
TCCR2B __reg
|
||||
TCNT2 __reg
|
||||
OCR2B __reg
|
||||
OCR2A __reg
|
||||
ASSR __reg
|
||||
}{
|
||||
TIMSK2: 0x70, // Timer/Counter Interrupt Mask register
|
||||
TIFR2: 0x37, // Timer/Counter Interrupt Flag Register
|
||||
TCCR2A: 0xb0, // Timer/Counter2 Control Register A
|
||||
TCCR2B: 0xb1, // Timer/Counter2 Control Register B
|
||||
TCNT2: 0xb2, // Timer/Counter2
|
||||
OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B
|
||||
OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A
|
||||
ASSR: 0xb6, // Asynchronous Status Register
|
||||
}
|
||||
|
||||
// Analog-to-Digital Converter
|
||||
ADC = struct {
|
||||
ADMUX __reg
|
||||
ADCL __reg
|
||||
ADCH __reg
|
||||
ADCSRA __reg
|
||||
ADCSRB __reg
|
||||
DIDR0 __reg
|
||||
}{
|
||||
ADMUX: 0x7c, // The ADC multiplexer Selection Register
|
||||
ADCL: 0x78, // ADC Data Register Bytes
|
||||
ADCH: 0x78, // ADC Data Register Bytes
|
||||
ADCSRA: 0x7a, // The ADC Control and Status register A
|
||||
ADCSRB: 0x7b, // The ADC Control and Status register B
|
||||
DIDR0: 0x7e, // Digital Input Disable Register
|
||||
}
|
||||
|
||||
// Analog Comparator
|
||||
AC = struct {
|
||||
ACSR __reg
|
||||
DIDR1 __reg
|
||||
}{
|
||||
ACSR: 0x50, // Analog Comparator Control And Status Register
|
||||
DIDR1: 0x7f, // Digital Input Disable Register 1
|
||||
}
|
||||
|
||||
// I/O Port
|
||||
PORT = struct {
|
||||
PORTB __reg
|
||||
DDRB __reg
|
||||
PINB __reg
|
||||
PORTC __reg
|
||||
DDRC __reg
|
||||
PINC __reg
|
||||
PORTD __reg
|
||||
DDRD __reg
|
||||
PIND __reg
|
||||
}{
|
||||
PORTB: 0x25, // Port B Data Register
|
||||
DDRB: 0x24, // Port B Data Direction Register
|
||||
PINB: 0x23, // Port B Input Pins
|
||||
PORTC: 0x28, // Port C Data Register
|
||||
DDRC: 0x27, // Port C Data Direction Register
|
||||
PINC: 0x26, // Port C Input Pins
|
||||
PORTD: 0x2b, // Port D Data Register
|
||||
DDRD: 0x2a, // Port D Data Direction Register
|
||||
PIND: 0x29, // Port D Input Pins
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit
|
||||
TC8 = struct {
|
||||
OCR0B __reg
|
||||
OCR0A __reg
|
||||
TCNT0 __reg
|
||||
TCCR0B __reg
|
||||
TCCR0A __reg
|
||||
TIMSK0 __reg
|
||||
TIFR0 __reg
|
||||
}{
|
||||
OCR0B: 0x48, // Timer/Counter0 Output Compare Register
|
||||
OCR0A: 0x47, // Timer/Counter0 Output Compare Register
|
||||
TCNT0: 0x46, // Timer/Counter0
|
||||
TCCR0B: 0x45, // Timer/Counter Control Register B
|
||||
TCCR0A: 0x44, // Timer/Counter Control Register A
|
||||
TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register
|
||||
TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register
|
||||
}
|
||||
|
||||
// External Interrupts
|
||||
EXINT = struct {
|
||||
EICRA __reg
|
||||
EIMSK __reg
|
||||
EIFR __reg
|
||||
PCICR __reg
|
||||
PCMSK2 __reg
|
||||
PCMSK1 __reg
|
||||
PCMSK0 __reg
|
||||
PCIFR __reg
|
||||
}{
|
||||
EICRA: 0x69, // External Interrupt Control Register
|
||||
EIMSK: 0x3d, // External Interrupt Mask Register
|
||||
EIFR: 0x3c, // External Interrupt Flag Register
|
||||
PCICR: 0x68, // Pin Change Interrupt Control Register
|
||||
PCMSK2: 0x6d, // Pin Change Mask Register 2
|
||||
PCMSK1: 0x6c, // Pin Change Mask Register 1
|
||||
PCMSK0: 0x6b, // Pin Change Mask Register 0
|
||||
PCIFR: 0x3b, // Pin Change Interrupt Flag Register
|
||||
}
|
||||
|
||||
// Serial Peripheral Interface
|
||||
SPI = struct {
|
||||
SPDR __reg
|
||||
SPSR __reg
|
||||
SPCR __reg
|
||||
}{
|
||||
SPDR: 0x4e, // SPI Data Register
|
||||
SPSR: 0x4d, // SPI Status Register
|
||||
SPCR: 0x4c, // SPI Control Register
|
||||
}
|
||||
|
||||
// CPU Registers
|
||||
CPU = struct {
|
||||
PRR __reg
|
||||
OSCCAL __reg
|
||||
CLKPR __reg
|
||||
SREG __reg
|
||||
SPL __reg
|
||||
SPH __reg
|
||||
SPMCSR __reg
|
||||
MCUCR __reg
|
||||
MCUSR __reg
|
||||
SMCR __reg
|
||||
GPIOR2 __reg
|
||||
GPIOR1 __reg
|
||||
GPIOR0 __reg
|
||||
}{
|
||||
PRR: 0x64, // Power Reduction Register
|
||||
OSCCAL: 0x66, // Oscillator Calibration Value
|
||||
CLKPR: 0x61, // Clock Prescale Register
|
||||
SREG: 0x5f, // Status Register
|
||||
SPL: 0x5d, // Stack Pointer
|
||||
SPH: 0x5d, // Stack Pointer
|
||||
SPMCSR: 0x57, // Store Program Memory Control and Status Register
|
||||
MCUCR: 0x55, // MCU Control Register
|
||||
MCUSR: 0x54, // MCU Status Register
|
||||
SMCR: 0x53, // Sleep Mode Control Register
|
||||
GPIOR2: 0x4b, // General Purpose I/O Register 2
|
||||
GPIOR1: 0x4a, // General Purpose I/O Register 1
|
||||
GPIOR0: 0x3e, // General Purpose I/O Register 0
|
||||
}
|
||||
|
||||
// Watchdog Timer
|
||||
WDT = struct {
|
||||
WDTCSR __reg
|
||||
}{
|
||||
WDTCSR: 0x60, // Watchdog Timer Control Register
|
||||
}
|
||||
|
||||
// EEPROM
|
||||
EEPROM = struct {
|
||||
EEARL __reg
|
||||
EEARH __reg
|
||||
EEDR __reg
|
||||
EECR __reg
|
||||
}{
|
||||
EEARL: 0x41, // EEPROM Address Register Bytes
|
||||
EEARH: 0x41, // EEPROM Address Register Bytes
|
||||
EEDR: 0x40, // EEPROM Data Register
|
||||
EECR: 0x3f, // EEPROM Control Register
|
||||
}
|
||||
)
|
||||
|
||||
// Bitfields for FUSE: Fuses
|
||||
const (
|
||||
// EXTENDED
|
||||
EXTENDED_BOOTSZ = 0x6 // Select boot size
|
||||
EXTENDED_BOOTRST = 0x1 // Boot Reset vector Enabled
|
||||
|
||||
// HIGH
|
||||
HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PC6 as i/o pin)
|
||||
HIGH_DWEN = 0x40 // Debug Wire enable
|
||||
HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled
|
||||
HIGH_WDTON = 0x10 // Watch-dog Timer always on
|
||||
HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle
|
||||
HIGH_BODLEVEL = 0x7 // Brown-out Detector trigger level
|
||||
|
||||
// LOW
|
||||
LOW_CKDIV8 = 0x80 // Divide clock by 8 internally
|
||||
LOW_CKOUT = 0x40 // Clock output on PORTB0
|
||||
LOW_SUT_CKSEL = 0x3f // Select Clock Source
|
||||
)
|
||||
|
||||
// Bitfields for LOCKBIT: Lockbits
|
||||
const (
|
||||
// LOCKBIT
|
||||
LOCKBIT_LB = 0x3 // Memory Lock
|
||||
LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode
|
||||
LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode
|
||||
)
|
||||
|
||||
// Bitfields for USART: USART
|
||||
const (
|
||||
// UCSR0A: USART Control and Status Register A
|
||||
UCSR0A_RXC0 = 0x80 // USART Receive Complete
|
||||
UCSR0A_TXC0 = 0x40 // USART Transmitt Complete
|
||||
UCSR0A_UDRE0 = 0x20 // USART Data Register Empty
|
||||
UCSR0A_FE0 = 0x10 // Framing Error
|
||||
UCSR0A_DOR0 = 0x8 // Data overRun
|
||||
UCSR0A_UPE0 = 0x4 // Parity Error
|
||||
UCSR0A_U2X0 = 0x2 // Double the USART transmission speed
|
||||
UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode
|
||||
|
||||
// UCSR0B: USART Control and Status Register B
|
||||
UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable
|
||||
UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable
|
||||
UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable
|
||||
UCSR0B_RXEN0 = 0x10 // Receiver Enable
|
||||
UCSR0B_TXEN0 = 0x8 // Transmitter Enable
|
||||
UCSR0B_UCSZ02 = 0x4 // Character Size
|
||||
UCSR0B_RXB80 = 0x2 // Receive Data Bit 8
|
||||
UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8
|
||||
|
||||
// UCSR0C: USART Control and Status Register C
|
||||
UCSR0C_UMSEL0 = 0xc0 // USART Mode Select
|
||||
UCSR0C_UPM0 = 0x30 // Parity Mode Bits
|
||||
UCSR0C_USBS0 = 0x8 // Stop Bit Select
|
||||
UCSR0C_UCSZ0 = 0x6 // Character Size
|
||||
UCSR0C_UCPOL0 = 0x1 // Clock Polarity
|
||||
)
|
||||
|
||||
// Bitfields for TWI: Two Wire Serial Interface
|
||||
const (
|
||||
// TWAMR: TWI (Slave) Address Mask Register
|
||||
TWAMR_TWAM = 0xfe
|
||||
|
||||
// TWCR: TWI Control Register
|
||||
TWCR_TWINT = 0x80 // TWI Interrupt Flag
|
||||
TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit
|
||||
TWCR_TWSTA = 0x20 // TWI Start Condition Bit
|
||||
TWCR_TWSTO = 0x10 // TWI Stop Condition Bit
|
||||
TWCR_TWWC = 0x8 // TWI Write Collition Flag
|
||||
TWCR_TWEN = 0x4 // TWI Enable Bit
|
||||
TWCR_TWIE = 0x1 // TWI Interrupt Enable
|
||||
|
||||
// TWSR: TWI Status Register
|
||||
TWSR_TWS = 0xf8 // TWI Status
|
||||
TWSR_TWPS = 0x3 // TWI Prescaler
|
||||
|
||||
// TWAR: TWI (Slave) Address register
|
||||
TWAR_TWA = 0xfe // TWI (Slave) Address register Bits
|
||||
TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit
|
||||
)
|
||||
|
||||
// Bitfields for TC16: Timer/Counter, 16-bit
|
||||
const (
|
||||
// TIMSK1: Timer/Counter Interrupt Mask Register
|
||||
TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable
|
||||
TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output CompareB Match Interrupt Enable
|
||||
TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output CompareA Match Interrupt Enable
|
||||
TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable
|
||||
|
||||
// TIFR1: Timer/Counter Interrupt Flag register
|
||||
TIFR1_ICF1 = 0x20 // Input Capture Flag 1
|
||||
TIFR1_OCF1B = 0x4 // Output Compare Flag 1B
|
||||
TIFR1_OCF1A = 0x2 // Output Compare Flag 1A
|
||||
TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag
|
||||
|
||||
// TCCR1A: Timer/Counter1 Control Register A
|
||||
TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits
|
||||
TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits
|
||||
TCCR1A_WGM1 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TCCR1B: Timer/Counter1 Control Register B
|
||||
TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler
|
||||
TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select
|
||||
TCCR1B_WGM1 = 0x18 // Waveform Generation Mode
|
||||
TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1
|
||||
|
||||
// TCCR1C: Timer/Counter1 Control Register C
|
||||
TCCR1C_FOC1A = 0x80
|
||||
TCCR1C_FOC1B = 0x40
|
||||
)
|
||||
|
||||
// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async
|
||||
const (
|
||||
// TIMSK2: Timer/Counter Interrupt Mask register
|
||||
TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable
|
||||
TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable
|
||||
TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable
|
||||
|
||||
// TIFR2: Timer/Counter Interrupt Flag Register
|
||||
TIFR2_OCF2B = 0x4 // Output Compare Flag 2B
|
||||
TIFR2_OCF2A = 0x2 // Output Compare Flag 2A
|
||||
TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag
|
||||
|
||||
// TCCR2A: Timer/Counter2 Control Register A
|
||||
TCCR2A_COM2A = 0xc0 // Compare Output Mode bits
|
||||
TCCR2A_COM2B = 0x30 // Compare Output Mode bits
|
||||
TCCR2A_WGM2 = 0x3 // Waveform Genration Mode
|
||||
|
||||
// TCCR2B: Timer/Counter2 Control Register B
|
||||
TCCR2B_FOC2A = 0x80 // Force Output Compare A
|
||||
TCCR2B_FOC2B = 0x40 // Force Output Compare B
|
||||
TCCR2B_WGM22 = 0x8 // Waveform Generation Mode
|
||||
TCCR2B_CS2 = 0x7 // Clock Select bits
|
||||
|
||||
// ASSR: Asynchronous Status Register
|
||||
ASSR_EXCLK = 0x40 // Enable External Clock Input
|
||||
ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2
|
||||
ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy
|
||||
ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy
|
||||
ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy
|
||||
ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy
|
||||
ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy
|
||||
)
|
||||
|
||||
// Bitfields for ADC: Analog-to-Digital Converter
|
||||
const (
|
||||
// ADMUX: The ADC multiplexer Selection Register
|
||||
ADMUX_REFS = 0xc0 // Reference Selection Bits
|
||||
ADMUX_ADLAR = 0x20 // Left Adjust Result
|
||||
ADMUX_MUX = 0xf // Analog Channel Selection Bits
|
||||
|
||||
// ADCSRA: The ADC Control and Status register A
|
||||
ADCSRA_ADEN = 0x80 // ADC Enable
|
||||
ADCSRA_ADSC = 0x40 // ADC Start Conversion
|
||||
ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable
|
||||
ADCSRA_ADIF = 0x10 // ADC Interrupt Flag
|
||||
ADCSRA_ADIE = 0x8 // ADC Interrupt Enable
|
||||
ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits
|
||||
|
||||
// ADCSRB: The ADC Control and Status register B
|
||||
ADCSRB_ACME = 0x40
|
||||
ADCSRB_ADTS = 0x7 // ADC Auto Trigger Source bits
|
||||
|
||||
// DIDR0: Digital Input Disable Register
|
||||
DIDR0_ADC5D = 0x20
|
||||
DIDR0_ADC4D = 0x10
|
||||
DIDR0_ADC3D = 0x8
|
||||
DIDR0_ADC2D = 0x4
|
||||
DIDR0_ADC1D = 0x2
|
||||
DIDR0_ADC0D = 0x1
|
||||
)
|
||||
|
||||
// Bitfields for AC: Analog Comparator
|
||||
const (
|
||||
// ACSR: Analog Comparator Control And Status Register
|
||||
ACSR_ACD = 0x80 // Analog Comparator Disable
|
||||
ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select
|
||||
ACSR_ACO = 0x20 // Analog Compare Output
|
||||
ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag
|
||||
ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable
|
||||
ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable
|
||||
ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits
|
||||
|
||||
// DIDR1: Digital Input Disable Register 1
|
||||
DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable
|
||||
DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable
|
||||
)
|
||||
|
||||
// Bitfields for TC8: Timer/Counter, 8-bit
|
||||
const (
|
||||
// TCCR0B: Timer/Counter Control Register B
|
||||
TCCR0B_FOC0A = 0x80 // Force Output Compare A
|
||||
TCCR0B_FOC0B = 0x40 // Force Output Compare B
|
||||
TCCR0B_WGM02 = 0x8
|
||||
TCCR0B_CS0 = 0x7 // Clock Select
|
||||
|
||||
// TCCR0A: Timer/Counter Control Register A
|
||||
TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode
|
||||
TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm
|
||||
TCCR0A_WGM0 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TIMSK0: Timer/Counter0 Interrupt Mask Register
|
||||
TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable
|
||||
TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable
|
||||
TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable
|
||||
|
||||
// TIFR0: Timer/Counter0 Interrupt Flag register
|
||||
TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B
|
||||
TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A
|
||||
TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag
|
||||
)
|
||||
|
||||
// Bitfields for EXINT: External Interrupts
|
||||
const (
|
||||
// EICRA: External Interrupt Control Register
|
||||
EICRA_ISC1 = 0xc // External Interrupt Sense Control 1 Bits
|
||||
EICRA_ISC0 = 0x3 // External Interrupt Sense Control 0 Bits
|
||||
|
||||
// EIMSK: External Interrupt Mask Register
|
||||
EIMSK_INT = 0x3 // External Interrupt Request 1 Enable
|
||||
|
||||
// EIFR: External Interrupt Flag Register
|
||||
EIFR_INTF = 0x3 // External Interrupt Flags
|
||||
|
||||
// PCICR: Pin Change Interrupt Control Register
|
||||
PCICR_PCIE = 0x7 // Pin Change Interrupt Enables
|
||||
|
||||
// PCMSK2: Pin Change Mask Register 2
|
||||
PCMSK2_PCINT = 0xff // Pin Change Enable Masks
|
||||
|
||||
// PCMSK1: Pin Change Mask Register 1
|
||||
PCMSK1_PCINT = 0x7f // Pin Change Enable Masks
|
||||
|
||||
// PCMSK0: Pin Change Mask Register 0
|
||||
PCMSK0_PCINT = 0xff // Pin Change Enable Masks
|
||||
|
||||
// PCIFR: Pin Change Interrupt Flag Register
|
||||
PCIFR_PCIF = 0x7 // Pin Change Interrupt Flags
|
||||
)
|
||||
|
||||
// Bitfields for SPI: Serial Peripheral Interface
|
||||
const (
|
||||
// SPSR: SPI Status Register
|
||||
SPSR_SPIF = 0x80 // SPI Interrupt Flag
|
||||
SPSR_WCOL = 0x40 // Write Collision Flag
|
||||
SPSR_SPI2X = 0x1 // Double SPI Speed Bit
|
||||
|
||||
// SPCR: SPI Control Register
|
||||
SPCR_SPIE = 0x80 // SPI Interrupt Enable
|
||||
SPCR_SPE = 0x40 // SPI Enable
|
||||
SPCR_DORD = 0x20 // Data Order
|
||||
SPCR_MSTR = 0x10 // Master/Slave Select
|
||||
SPCR_CPOL = 0x8 // Clock polarity
|
||||
SPCR_CPHA = 0x4 // Clock Phase
|
||||
SPCR_SPR = 0x3 // SPI Clock Rate Selects
|
||||
)
|
||||
|
||||
// Bitfields for CPU: CPU Registers
|
||||
const (
|
||||
// PRR: Power Reduction Register
|
||||
PRR_PRTWI = 0x80 // Power Reduction TWI
|
||||
PRR_PRTIM2 = 0x40 // Power Reduction Timer/Counter2
|
||||
PRR_PRTIM0 = 0x20 // Power Reduction Timer/Counter0
|
||||
PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1
|
||||
PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface
|
||||
PRR_PRUSART0 = 0x2 // Power Reduction USART
|
||||
PRR_PRADC = 0x1 // Power Reduction ADC
|
||||
|
||||
// OSCCAL: Oscillator Calibration Value
|
||||
OSCCAL_OSCCAL = 0xff // Oscillator Calibration
|
||||
|
||||
// CLKPR: Clock Prescale Register
|
||||
CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable
|
||||
CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits
|
||||
|
||||
// SREG: Status Register
|
||||
SREG_I = 0x80 // Global Interrupt Enable
|
||||
SREG_T = 0x40 // Bit Copy Storage
|
||||
SREG_H = 0x20 // Half Carry Flag
|
||||
SREG_S = 0x10 // Sign Bit
|
||||
SREG_V = 0x8 // Two's Complement Overflow Flag
|
||||
SREG_N = 0x4 // Negative Flag
|
||||
SREG_Z = 0x2 // Zero Flag
|
||||
SREG_C = 0x1 // Carry Flag
|
||||
|
||||
// SPMCSR: Store Program Memory Control and Status Register
|
||||
SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable
|
||||
SPMCSR_RWWSB = 0x40 // Read-While-Write Section Busy
|
||||
SPMCSR_RWWSRE = 0x10 // Read-While-Write section read enable
|
||||
SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set
|
||||
SPMCSR_PGWRT = 0x4 // Page Write
|
||||
SPMCSR_PGERS = 0x2 // Page Erase
|
||||
SPMCSR_SELFPRGEN = 0x1 // Self Programming Enable
|
||||
|
||||
// MCUCR: MCU Control Register
|
||||
MCUCR_PUD = 0x10 // Pull-up Disable
|
||||
MCUCR_IVSEL = 0x2 // Interrupt Vector Select
|
||||
MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable
|
||||
|
||||
// MCUSR: MCU Status Register
|
||||
MCUSR_WDRF = 0x8 // Watchdog Reset Flag
|
||||
MCUSR_BORF = 0x4 // Brown-out Reset Flag
|
||||
MCUSR_EXTRF = 0x2 // External Reset Flag
|
||||
MCUSR_PORF = 0x1 // Power-on reset flag
|
||||
|
||||
// SMCR: Sleep Mode Control Register
|
||||
SMCR_SM = 0xe // Sleep Mode
|
||||
SMCR_SE = 0x1 // Sleep Enable
|
||||
)
|
||||
|
||||
// Bitfields for WDT: Watchdog Timer
|
||||
const (
|
||||
// WDTCSR: Watchdog Timer Control Register
|
||||
WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag
|
||||
WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable
|
||||
WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits
|
||||
WDTCSR_WDCE = 0x10 // Watchdog Change Enable
|
||||
WDTCSR_WDE = 0x8 // Watch Dog Enable
|
||||
)
|
||||
|
||||
// Bitfields for EEPROM: EEPROM
|
||||
const (
|
||||
// EECR: EEPROM Control Register
|
||||
EECR_EEPM = 0x30 // EEPROM Programming Mode Bits
|
||||
EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable
|
||||
EECR_EEMPE = 0x4 // EEPROM Master Write Enable
|
||||
EECR_EEPE = 0x2 // EEPROM Write Enable
|
||||
EECR_EERE = 0x1 // EEPROM Read Enable
|
||||
)
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from ATmega168.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x4000;
|
||||
__ram_size = 0x400;
|
||||
__num_isrs = 26;
|
||||
|
|
@ -1,641 +0,0 @@
|
|||
// Automatically generated file. DO NOT EDIT.
|
||||
// Generated by gen-device.py from ATmega168A.atdf, see http://packs.download.atmel.com/
|
||||
|
||||
// +build avr,atmega168a
|
||||
|
||||
// Device information for the ATmega168A.
|
||||
//
|
||||
package avr
|
||||
|
||||
// Magic type name for the compiler.
|
||||
type __reg uint8
|
||||
|
||||
// Export this magic type name.
|
||||
type RegValue = __reg
|
||||
|
||||
// Some information about this device.
|
||||
const (
|
||||
DEVICE = "ATmega168A"
|
||||
ARCH = "AVR8"
|
||||
FAMILY = "megaAVR"
|
||||
)
|
||||
|
||||
// Interrupts
|
||||
const (
|
||||
IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset
|
||||
IRQ_INT0 = 1 // External Interrupt Request 0
|
||||
IRQ_INT1 = 2 // External Interrupt Request 1
|
||||
IRQ_PCINT0 = 3 // Pin Change Interrupt Request 0
|
||||
IRQ_PCINT1 = 4 // Pin Change Interrupt Request 0
|
||||
IRQ_PCINT2 = 5 // Pin Change Interrupt Request 1
|
||||
IRQ_WDT = 6 // Watchdog Time-out Interrupt
|
||||
IRQ_TIMER2_COMPA = 7 // Timer/Counter2 Compare Match A
|
||||
IRQ_TIMER2_COMPB = 8 // Timer/Counter2 Compare Match A
|
||||
IRQ_TIMER2_OVF = 9 // Timer/Counter2 Overflow
|
||||
IRQ_TIMER1_CAPT = 10 // Timer/Counter1 Capture Event
|
||||
IRQ_TIMER1_COMPA = 11 // Timer/Counter1 Compare Match A
|
||||
IRQ_TIMER1_COMPB = 12 // Timer/Counter1 Compare Match B
|
||||
IRQ_TIMER1_OVF = 13 // Timer/Counter1 Overflow
|
||||
IRQ_TIMER0_COMPA = 14 // TimerCounter0 Compare Match A
|
||||
IRQ_TIMER0_COMPB = 15 // TimerCounter0 Compare Match B
|
||||
IRQ_TIMER0_OVF = 16 // Timer/Couner0 Overflow
|
||||
IRQ_SPI_STC = 17 // SPI Serial Transfer Complete
|
||||
IRQ_USART_RX = 18 // USART Rx Complete
|
||||
IRQ_USART_UDRE = 19 // USART, Data Register Empty
|
||||
IRQ_USART_TX = 20 // USART Tx Complete
|
||||
IRQ_ADC = 21 // ADC Conversion Complete
|
||||
IRQ_EE_READY = 22 // EEPROM Ready
|
||||
IRQ_ANALOG_COMP = 23 // Analog Comparator
|
||||
IRQ_TWI = 24 // Two-wire Serial Interface
|
||||
IRQ_SPM_Ready = 25 // Store Program Memory Read
|
||||
IRQ_max = 25 // Highest interrupt number on this device.
|
||||
)
|
||||
|
||||
// Peripherals
|
||||
var (
|
||||
// Fuses
|
||||
FUSE = struct {
|
||||
EXTENDED __reg
|
||||
HIGH __reg
|
||||
LOW __reg
|
||||
}{
|
||||
EXTENDED: 0x2,
|
||||
HIGH: 0x1,
|
||||
LOW: 0x0,
|
||||
}
|
||||
|
||||
// Lockbits
|
||||
LOCKBIT = struct {
|
||||
LOCKBIT __reg
|
||||
}{
|
||||
LOCKBIT: 0x0,
|
||||
}
|
||||
|
||||
// USART
|
||||
USART = struct {
|
||||
UDR0 __reg
|
||||
UCSR0A __reg
|
||||
UCSR0B __reg
|
||||
UCSR0C __reg
|
||||
UBRR0L __reg
|
||||
UBRR0H __reg
|
||||
}{
|
||||
UDR0: 0xc6, // USART I/O Data Register
|
||||
UCSR0A: 0xc0, // USART Control and Status Register A
|
||||
UCSR0B: 0xc1, // USART Control and Status Register B
|
||||
UCSR0C: 0xc2, // USART Control and Status Register C
|
||||
UBRR0L: 0xc4, // USART Baud Rate Register Bytes
|
||||
UBRR0H: 0xc4, // USART Baud Rate Register Bytes
|
||||
}
|
||||
|
||||
// Two Wire Serial Interface
|
||||
TWI = struct {
|
||||
TWAMR __reg
|
||||
TWBR __reg
|
||||
TWCR __reg
|
||||
TWSR __reg
|
||||
TWDR __reg
|
||||
TWAR __reg
|
||||
}{
|
||||
TWAMR: 0xbd, // TWI (Slave) Address Mask Register
|
||||
TWBR: 0xb8, // TWI Bit Rate register
|
||||
TWCR: 0xbc, // TWI Control Register
|
||||
TWSR: 0xb9, // TWI Status Register
|
||||
TWDR: 0xbb, // TWI Data register
|
||||
TWAR: 0xba, // TWI (Slave) Address register
|
||||
}
|
||||
|
||||
// Timer/Counter, 16-bit
|
||||
TC16 = struct {
|
||||
TIMSK1 __reg
|
||||
TIFR1 __reg
|
||||
TCCR1A __reg
|
||||
TCCR1B __reg
|
||||
TCCR1C __reg
|
||||
TCNT1L __reg
|
||||
TCNT1H __reg
|
||||
OCR1AL __reg
|
||||
OCR1AH __reg
|
||||
OCR1BL __reg
|
||||
OCR1BH __reg
|
||||
ICR1L __reg
|
||||
ICR1H __reg
|
||||
}{
|
||||
TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register
|
||||
TIFR1: 0x36, // Timer/Counter Interrupt Flag register
|
||||
TCCR1A: 0x80, // Timer/Counter1 Control Register A
|
||||
TCCR1B: 0x81, // Timer/Counter1 Control Register B
|
||||
TCCR1C: 0x82, // Timer/Counter1 Control Register C
|
||||
TCNT1L: 0x84, // Timer/Counter1 Bytes
|
||||
TCNT1H: 0x84, // Timer/Counter1 Bytes
|
||||
OCR1AL: 0x88, // Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1AH: 0x88, // Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register Bytes
|
||||
ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit Async
|
||||
TC8_ASYNC = struct {
|
||||
TIMSK2 __reg
|
||||
TIFR2 __reg
|
||||
TCCR2A __reg
|
||||
TCCR2B __reg
|
||||
TCNT2 __reg
|
||||
OCR2B __reg
|
||||
OCR2A __reg
|
||||
ASSR __reg
|
||||
}{
|
||||
TIMSK2: 0x70, // Timer/Counter Interrupt Mask register
|
||||
TIFR2: 0x37, // Timer/Counter Interrupt Flag Register
|
||||
TCCR2A: 0xb0, // Timer/Counter2 Control Register A
|
||||
TCCR2B: 0xb1, // Timer/Counter2 Control Register B
|
||||
TCNT2: 0xb2, // Timer/Counter2
|
||||
OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B
|
||||
OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A
|
||||
ASSR: 0xb6, // Asynchronous Status Register
|
||||
}
|
||||
|
||||
// Analog-to-Digital Converter
|
||||
ADC = struct {
|
||||
ADMUX __reg
|
||||
ADCL __reg
|
||||
ADCH __reg
|
||||
ADCSRA __reg
|
||||
ADCSRB __reg
|
||||
DIDR0 __reg
|
||||
}{
|
||||
ADMUX: 0x7c, // The ADC multiplexer Selection Register
|
||||
ADCL: 0x78, // ADC Data Register Bytes
|
||||
ADCH: 0x78, // ADC Data Register Bytes
|
||||
ADCSRA: 0x7a, // The ADC Control and Status register A
|
||||
ADCSRB: 0x7b, // The ADC Control and Status register B
|
||||
DIDR0: 0x7e, // Digital Input Disable Register
|
||||
}
|
||||
|
||||
// Analog Comparator
|
||||
AC = struct {
|
||||
ACSR __reg
|
||||
DIDR1 __reg
|
||||
}{
|
||||
ACSR: 0x50, // Analog Comparator Control And Status Register
|
||||
DIDR1: 0x7f, // Digital Input Disable Register 1
|
||||
}
|
||||
|
||||
// I/O Port
|
||||
PORT = struct {
|
||||
PORTB __reg
|
||||
DDRB __reg
|
||||
PINB __reg
|
||||
PORTC __reg
|
||||
DDRC __reg
|
||||
PINC __reg
|
||||
PORTD __reg
|
||||
DDRD __reg
|
||||
PIND __reg
|
||||
}{
|
||||
PORTB: 0x25, // Port B Data Register
|
||||
DDRB: 0x24, // Port B Data Direction Register
|
||||
PINB: 0x23, // Port B Input Pins
|
||||
PORTC: 0x28, // Port C Data Register
|
||||
DDRC: 0x27, // Port C Data Direction Register
|
||||
PINC: 0x26, // Port C Input Pins
|
||||
PORTD: 0x2b, // Port D Data Register
|
||||
DDRD: 0x2a, // Port D Data Direction Register
|
||||
PIND: 0x29, // Port D Input Pins
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit
|
||||
TC8 = struct {
|
||||
OCR0B __reg
|
||||
OCR0A __reg
|
||||
TCNT0 __reg
|
||||
TCCR0B __reg
|
||||
TCCR0A __reg
|
||||
TIMSK0 __reg
|
||||
TIFR0 __reg
|
||||
}{
|
||||
OCR0B: 0x48, // Timer/Counter0 Output Compare Register
|
||||
OCR0A: 0x47, // Timer/Counter0 Output Compare Register
|
||||
TCNT0: 0x46, // Timer/Counter0
|
||||
TCCR0B: 0x45, // Timer/Counter Control Register B
|
||||
TCCR0A: 0x44, // Timer/Counter Control Register A
|
||||
TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register
|
||||
TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register
|
||||
}
|
||||
|
||||
// External Interrupts
|
||||
EXINT = struct {
|
||||
EICRA __reg
|
||||
EIMSK __reg
|
||||
EIFR __reg
|
||||
PCICR __reg
|
||||
PCMSK2 __reg
|
||||
PCMSK1 __reg
|
||||
PCMSK0 __reg
|
||||
PCIFR __reg
|
||||
}{
|
||||
EICRA: 0x69, // External Interrupt Control Register
|
||||
EIMSK: 0x3d, // External Interrupt Mask Register
|
||||
EIFR: 0x3c, // External Interrupt Flag Register
|
||||
PCICR: 0x68, // Pin Change Interrupt Control Register
|
||||
PCMSK2: 0x6d, // Pin Change Mask Register 2
|
||||
PCMSK1: 0x6c, // Pin Change Mask Register 1
|
||||
PCMSK0: 0x6b, // Pin Change Mask Register 0
|
||||
PCIFR: 0x3b, // Pin Change Interrupt Flag Register
|
||||
}
|
||||
|
||||
// Serial Peripheral Interface
|
||||
SPI = struct {
|
||||
SPDR __reg
|
||||
SPSR __reg
|
||||
SPCR __reg
|
||||
}{
|
||||
SPDR: 0x4e, // SPI Data Register
|
||||
SPSR: 0x4d, // SPI Status Register
|
||||
SPCR: 0x4c, // SPI Control Register
|
||||
}
|
||||
|
||||
// Watchdog Timer
|
||||
WDT = struct {
|
||||
WDTCSR __reg
|
||||
}{
|
||||
WDTCSR: 0x60, // Watchdog Timer Control Register
|
||||
}
|
||||
|
||||
// EEPROM
|
||||
EEPROM = struct {
|
||||
EEARL __reg
|
||||
EEARH __reg
|
||||
EEDR __reg
|
||||
EECR __reg
|
||||
}{
|
||||
EEARL: 0x41, // EEPROM Address Register Bytes
|
||||
EEARH: 0x41, // EEPROM Address Register Bytes
|
||||
EEDR: 0x40, // EEPROM Data Register
|
||||
EECR: 0x3f, // EEPROM Control Register
|
||||
}
|
||||
|
||||
// CPU Registers
|
||||
CPU = struct {
|
||||
PRR __reg
|
||||
OSCCAL __reg
|
||||
CLKPR __reg
|
||||
SREG __reg
|
||||
SPL __reg
|
||||
SPH __reg
|
||||
SPMCSR __reg
|
||||
MCUCR __reg
|
||||
MCUSR __reg
|
||||
SMCR __reg
|
||||
GPIOR2 __reg
|
||||
GPIOR1 __reg
|
||||
GPIOR0 __reg
|
||||
}{
|
||||
PRR: 0x64, // Power Reduction Register
|
||||
OSCCAL: 0x66, // Oscillator Calibration Value
|
||||
CLKPR: 0x61, // Clock Prescale Register
|
||||
SREG: 0x5f, // Status Register
|
||||
SPL: 0x5d, // Stack Pointer
|
||||
SPH: 0x5d, // Stack Pointer
|
||||
SPMCSR: 0x57, // Store Program Memory Control and Status Register
|
||||
MCUCR: 0x55, // MCU Control Register
|
||||
MCUSR: 0x54, // MCU Status Register
|
||||
SMCR: 0x53, // Sleep Mode Control Register
|
||||
GPIOR2: 0x4b, // General Purpose I/O Register 2
|
||||
GPIOR1: 0x4a, // General Purpose I/O Register 1
|
||||
GPIOR0: 0x3e, // General Purpose I/O Register 0
|
||||
}
|
||||
)
|
||||
|
||||
// Bitfields for FUSE: Fuses
|
||||
const (
|
||||
// EXTENDED
|
||||
EXTENDED_BOOTSZ = 0x6 // Select boot size
|
||||
EXTENDED_BOOTRST = 0x1 // Boot Reset vector Enabled
|
||||
|
||||
// HIGH
|
||||
HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PC6 as i/o pin)
|
||||
HIGH_DWEN = 0x40 // Debug Wire enable
|
||||
HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled
|
||||
HIGH_WDTON = 0x10 // Watch-dog Timer always on
|
||||
HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle
|
||||
HIGH_BODLEVEL = 0x7 // Brown-out Detector trigger level
|
||||
|
||||
// LOW
|
||||
LOW_CKDIV8 = 0x80 // Divide clock by 8 internally
|
||||
LOW_CKOUT = 0x40 // Clock output on PORTB0
|
||||
LOW_SUT_CKSEL = 0x3f // Select Clock Source
|
||||
)
|
||||
|
||||
// Bitfields for LOCKBIT: Lockbits
|
||||
const (
|
||||
// LOCKBIT
|
||||
LOCKBIT_LB = 0x3 // Memory Lock
|
||||
LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode
|
||||
LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode
|
||||
)
|
||||
|
||||
// Bitfields for USART: USART
|
||||
const (
|
||||
// UCSR0A: USART Control and Status Register A
|
||||
UCSR0A_RXC0 = 0x80 // USART Receive Complete
|
||||
UCSR0A_TXC0 = 0x40 // USART Transmitt Complete
|
||||
UCSR0A_UDRE0 = 0x20 // USART Data Register Empty
|
||||
UCSR0A_FE0 = 0x10 // Framing Error
|
||||
UCSR0A_DOR0 = 0x8 // Data overRun
|
||||
UCSR0A_UPE0 = 0x4 // Parity Error
|
||||
UCSR0A_U2X0 = 0x2 // Double the USART transmission speed
|
||||
UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode
|
||||
|
||||
// UCSR0B: USART Control and Status Register B
|
||||
UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable
|
||||
UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable
|
||||
UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable
|
||||
UCSR0B_RXEN0 = 0x10 // Receiver Enable
|
||||
UCSR0B_TXEN0 = 0x8 // Transmitter Enable
|
||||
UCSR0B_UCSZ02 = 0x4 // Character Size
|
||||
UCSR0B_RXB80 = 0x2 // Receive Data Bit 8
|
||||
UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8
|
||||
|
||||
// UCSR0C: USART Control and Status Register C
|
||||
UCSR0C_UMSEL0 = 0xc0 // USART Mode Select
|
||||
UCSR0C_UPM0 = 0x30 // Parity Mode Bits
|
||||
UCSR0C_USBS0 = 0x8 // Stop Bit Select
|
||||
UCSR0C_UCSZ0 = 0x6 // Character Size
|
||||
UCSR0C_UCPOL0 = 0x1 // Clock Polarity
|
||||
)
|
||||
|
||||
// Bitfields for TWI: Two Wire Serial Interface
|
||||
const (
|
||||
// TWAMR: TWI (Slave) Address Mask Register
|
||||
TWAMR_TWAM = 0xfe
|
||||
|
||||
// TWCR: TWI Control Register
|
||||
TWCR_TWINT = 0x80 // TWI Interrupt Flag
|
||||
TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit
|
||||
TWCR_TWSTA = 0x20 // TWI Start Condition Bit
|
||||
TWCR_TWSTO = 0x10 // TWI Stop Condition Bit
|
||||
TWCR_TWWC = 0x8 // TWI Write Collition Flag
|
||||
TWCR_TWEN = 0x4 // TWI Enable Bit
|
||||
TWCR_TWIE = 0x1 // TWI Interrupt Enable
|
||||
|
||||
// TWSR: TWI Status Register
|
||||
TWSR_TWS = 0xf8 // TWI Status
|
||||
TWSR_TWPS = 0x3 // TWI Prescaler
|
||||
|
||||
// TWAR: TWI (Slave) Address register
|
||||
TWAR_TWA = 0xfe // TWI (Slave) Address register Bits
|
||||
TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit
|
||||
)
|
||||
|
||||
// Bitfields for TC16: Timer/Counter, 16-bit
|
||||
const (
|
||||
// TIMSK1: Timer/Counter Interrupt Mask Register
|
||||
TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable
|
||||
TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output CompareB Match Interrupt Enable
|
||||
TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output CompareA Match Interrupt Enable
|
||||
TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable
|
||||
|
||||
// TIFR1: Timer/Counter Interrupt Flag register
|
||||
TIFR1_ICF1 = 0x20 // Input Capture Flag 1
|
||||
TIFR1_OCF1B = 0x4 // Output Compare Flag 1B
|
||||
TIFR1_OCF1A = 0x2 // Output Compare Flag 1A
|
||||
TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag
|
||||
|
||||
// TCCR1A: Timer/Counter1 Control Register A
|
||||
TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits
|
||||
TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits
|
||||
TCCR1A_WGM1 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TCCR1B: Timer/Counter1 Control Register B
|
||||
TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler
|
||||
TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select
|
||||
TCCR1B_WGM1 = 0x18 // Waveform Generation Mode
|
||||
TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1
|
||||
|
||||
// TCCR1C: Timer/Counter1 Control Register C
|
||||
TCCR1C_FOC1A = 0x80
|
||||
TCCR1C_FOC1B = 0x40
|
||||
)
|
||||
|
||||
// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async
|
||||
const (
|
||||
// TIMSK2: Timer/Counter Interrupt Mask register
|
||||
TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable
|
||||
TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable
|
||||
TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable
|
||||
|
||||
// TIFR2: Timer/Counter Interrupt Flag Register
|
||||
TIFR2_OCF2B = 0x4 // Output Compare Flag 2B
|
||||
TIFR2_OCF2A = 0x2 // Output Compare Flag 2A
|
||||
TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag
|
||||
|
||||
// TCCR2A: Timer/Counter2 Control Register A
|
||||
TCCR2A_COM2A = 0xc0 // Compare Output Mode bits
|
||||
TCCR2A_COM2B = 0x30 // Compare Output Mode bits
|
||||
TCCR2A_WGM2 = 0x3 // Waveform Genration Mode
|
||||
|
||||
// TCCR2B: Timer/Counter2 Control Register B
|
||||
TCCR2B_FOC2A = 0x80 // Force Output Compare A
|
||||
TCCR2B_FOC2B = 0x40 // Force Output Compare B
|
||||
TCCR2B_WGM22 = 0x8 // Waveform Generation Mode
|
||||
TCCR2B_CS2 = 0x7 // Clock Select bits
|
||||
|
||||
// ASSR: Asynchronous Status Register
|
||||
ASSR_EXCLK = 0x40 // Enable External Clock Input
|
||||
ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2
|
||||
ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy
|
||||
ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy
|
||||
ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy
|
||||
ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy
|
||||
ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy
|
||||
)
|
||||
|
||||
// Bitfields for ADC: Analog-to-Digital Converter
|
||||
const (
|
||||
// ADMUX: The ADC multiplexer Selection Register
|
||||
ADMUX_REFS = 0xc0 // Reference Selection Bits
|
||||
ADMUX_ADLAR = 0x20 // Left Adjust Result
|
||||
ADMUX_MUX = 0xf // Analog Channel Selection Bits
|
||||
|
||||
// ADCSRA: The ADC Control and Status register A
|
||||
ADCSRA_ADEN = 0x80 // ADC Enable
|
||||
ADCSRA_ADSC = 0x40 // ADC Start Conversion
|
||||
ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable
|
||||
ADCSRA_ADIF = 0x10 // ADC Interrupt Flag
|
||||
ADCSRA_ADIE = 0x8 // ADC Interrupt Enable
|
||||
ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits
|
||||
|
||||
// ADCSRB: The ADC Control and Status register B
|
||||
ADCSRB_ACME = 0x40
|
||||
ADCSRB_ADTS = 0x7 // ADC Auto Trigger Source bits
|
||||
|
||||
// DIDR0: Digital Input Disable Register
|
||||
DIDR0_ADC5D = 0x20
|
||||
DIDR0_ADC4D = 0x10
|
||||
DIDR0_ADC3D = 0x8
|
||||
DIDR0_ADC2D = 0x4
|
||||
DIDR0_ADC1D = 0x2
|
||||
DIDR0_ADC0D = 0x1
|
||||
)
|
||||
|
||||
// Bitfields for AC: Analog Comparator
|
||||
const (
|
||||
// ACSR: Analog Comparator Control And Status Register
|
||||
ACSR_ACD = 0x80 // Analog Comparator Disable
|
||||
ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select
|
||||
ACSR_ACO = 0x20 // Analog Compare Output
|
||||
ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag
|
||||
ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable
|
||||
ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable
|
||||
ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits
|
||||
|
||||
// DIDR1: Digital Input Disable Register 1
|
||||
DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable
|
||||
DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable
|
||||
)
|
||||
|
||||
// Bitfields for TC8: Timer/Counter, 8-bit
|
||||
const (
|
||||
// TCCR0B: Timer/Counter Control Register B
|
||||
TCCR0B_FOC0A = 0x80 // Force Output Compare A
|
||||
TCCR0B_FOC0B = 0x40 // Force Output Compare B
|
||||
TCCR0B_WGM02 = 0x8
|
||||
TCCR0B_CS0 = 0x7 // Clock Select
|
||||
|
||||
// TCCR0A: Timer/Counter Control Register A
|
||||
TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode
|
||||
TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm
|
||||
TCCR0A_WGM0 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TIMSK0: Timer/Counter0 Interrupt Mask Register
|
||||
TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable
|
||||
TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable
|
||||
TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable
|
||||
|
||||
// TIFR0: Timer/Counter0 Interrupt Flag register
|
||||
TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B
|
||||
TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A
|
||||
TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag
|
||||
)
|
||||
|
||||
// Bitfields for EXINT: External Interrupts
|
||||
const (
|
||||
// EICRA: External Interrupt Control Register
|
||||
EICRA_ISC1 = 0xc // External Interrupt Sense Control 1 Bits
|
||||
EICRA_ISC0 = 0x3 // External Interrupt Sense Control 0 Bits
|
||||
|
||||
// EIMSK: External Interrupt Mask Register
|
||||
EIMSK_INT = 0x3 // External Interrupt Request 1 Enable
|
||||
|
||||
// EIFR: External Interrupt Flag Register
|
||||
EIFR_INTF = 0x3 // External Interrupt Flags
|
||||
|
||||
// PCICR: Pin Change Interrupt Control Register
|
||||
PCICR_PCIE = 0x7 // Pin Change Interrupt Enables
|
||||
|
||||
// PCMSK2: Pin Change Mask Register 2
|
||||
PCMSK2_PCINT = 0xff // Pin Change Enable Masks
|
||||
|
||||
// PCMSK1: Pin Change Mask Register 1
|
||||
PCMSK1_PCINT = 0x7f // Pin Change Enable Masks
|
||||
|
||||
// PCMSK0: Pin Change Mask Register 0
|
||||
PCMSK0_PCINT = 0xff // Pin Change Enable Masks
|
||||
|
||||
// PCIFR: Pin Change Interrupt Flag Register
|
||||
PCIFR_PCIF = 0x7 // Pin Change Interrupt Flags
|
||||
)
|
||||
|
||||
// Bitfields for SPI: Serial Peripheral Interface
|
||||
const (
|
||||
// SPSR: SPI Status Register
|
||||
SPSR_SPIF = 0x80 // SPI Interrupt Flag
|
||||
SPSR_WCOL = 0x40 // Write Collision Flag
|
||||
SPSR_SPI2X = 0x1 // Double SPI Speed Bit
|
||||
|
||||
// SPCR: SPI Control Register
|
||||
SPCR_SPIE = 0x80 // SPI Interrupt Enable
|
||||
SPCR_SPE = 0x40 // SPI Enable
|
||||
SPCR_DORD = 0x20 // Data Order
|
||||
SPCR_MSTR = 0x10 // Master/Slave Select
|
||||
SPCR_CPOL = 0x8 // Clock polarity
|
||||
SPCR_CPHA = 0x4 // Clock Phase
|
||||
SPCR_SPR = 0x3 // SPI Clock Rate Selects
|
||||
)
|
||||
|
||||
// Bitfields for WDT: Watchdog Timer
|
||||
const (
|
||||
// WDTCSR: Watchdog Timer Control Register
|
||||
WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag
|
||||
WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable
|
||||
WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits
|
||||
WDTCSR_WDCE = 0x10 // Watchdog Change Enable
|
||||
WDTCSR_WDE = 0x8 // Watch Dog Enable
|
||||
)
|
||||
|
||||
// Bitfields for EEPROM: EEPROM
|
||||
const (
|
||||
// EECR: EEPROM Control Register
|
||||
EECR_EEPM = 0x30 // EEPROM Programming Mode Bits
|
||||
EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable
|
||||
EECR_EEMPE = 0x4 // EEPROM Master Write Enable
|
||||
EECR_EEPE = 0x2 // EEPROM Write Enable
|
||||
EECR_EERE = 0x1 // EEPROM Read Enable
|
||||
)
|
||||
|
||||
// Bitfields for CPU: CPU Registers
|
||||
const (
|
||||
// PRR: Power Reduction Register
|
||||
PRR_PRTWI = 0x80 // Power Reduction TWI
|
||||
PRR_PRTIM2 = 0x40 // Power Reduction Timer/Counter2
|
||||
PRR_PRTIM0 = 0x20 // Power Reduction Timer/Counter0
|
||||
PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1
|
||||
PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface
|
||||
PRR_PRUSART0 = 0x2 // Power Reduction USART
|
||||
PRR_PRADC = 0x1 // Power Reduction ADC
|
||||
|
||||
// OSCCAL: Oscillator Calibration Value
|
||||
OSCCAL_OSCCAL = 0xff // Oscillator Calibration
|
||||
|
||||
// CLKPR: Clock Prescale Register
|
||||
CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable
|
||||
CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits
|
||||
|
||||
// SREG: Status Register
|
||||
SREG_I = 0x80 // Global Interrupt Enable
|
||||
SREG_T = 0x40 // Bit Copy Storage
|
||||
SREG_H = 0x20 // Half Carry Flag
|
||||
SREG_S = 0x10 // Sign Bit
|
||||
SREG_V = 0x8 // Two's Complement Overflow Flag
|
||||
SREG_N = 0x4 // Negative Flag
|
||||
SREG_Z = 0x2 // Zero Flag
|
||||
SREG_C = 0x1 // Carry Flag
|
||||
|
||||
// SPMCSR: Store Program Memory Control and Status Register
|
||||
SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable
|
||||
SPMCSR_RWWSB = 0x40 // Read-While-Write Section Busy
|
||||
SPMCSR_SIGRD = 0x20 // Signature Row Read
|
||||
SPMCSR_RWWSRE = 0x10 // Read-While-Write section read enable
|
||||
SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set
|
||||
SPMCSR_PGWRT = 0x4 // Page Write
|
||||
SPMCSR_PGERS = 0x2 // Page Erase
|
||||
SPMCSR_SPMEN = 0x1 // Store Program Memory
|
||||
|
||||
// MCUCR: MCU Control Register
|
||||
MCUCR_PUD = 0x10
|
||||
MCUCR_IVSEL = 0x2
|
||||
MCUCR_IVCE = 0x1
|
||||
|
||||
// MCUSR: MCU Status Register
|
||||
MCUSR_WDRF = 0x8 // Watchdog Reset Flag
|
||||
MCUSR_BORF = 0x4 // Brown-out Reset Flag
|
||||
MCUSR_EXTRF = 0x2 // External Reset Flag
|
||||
MCUSR_PORF = 0x1 // Power-on reset flag
|
||||
|
||||
// SMCR: Sleep Mode Control Register
|
||||
SMCR_SM = 0xe // Sleep Mode Select Bits
|
||||
SMCR_SE = 0x1 // Sleep Enable
|
||||
)
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from ATmega168A.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x4000;
|
||||
__ram_size = 0x400;
|
||||
__num_isrs = 26;
|
||||
|
|
@ -1,642 +0,0 @@
|
|||
// Automatically generated file. DO NOT EDIT.
|
||||
// Generated by gen-device.py from ATmega168P.atdf, see http://packs.download.atmel.com/
|
||||
|
||||
// +build avr,atmega168p
|
||||
|
||||
// Device information for the ATmega168P.
|
||||
//
|
||||
package avr
|
||||
|
||||
// Magic type name for the compiler.
|
||||
type __reg uint8
|
||||
|
||||
// Export this magic type name.
|
||||
type RegValue = __reg
|
||||
|
||||
// Some information about this device.
|
||||
const (
|
||||
DEVICE = "ATmega168P"
|
||||
ARCH = "AVR8"
|
||||
FAMILY = "megaAVR"
|
||||
)
|
||||
|
||||
// Interrupts
|
||||
const (
|
||||
IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset
|
||||
IRQ_INT0 = 1 // External Interrupt Request 0
|
||||
IRQ_INT1 = 2 // External Interrupt Request 1
|
||||
IRQ_PCINT0 = 3 // Pin Change Interrupt Request 0
|
||||
IRQ_PCINT1 = 4 // Pin Change Interrupt Request 0
|
||||
IRQ_PCINT2 = 5 // Pin Change Interrupt Request 1
|
||||
IRQ_WDT = 6 // Watchdog Time-out Interrupt
|
||||
IRQ_TIMER2_COMPA = 7 // Timer/Counter2 Compare Match A
|
||||
IRQ_TIMER2_COMPB = 8 // Timer/Counter2 Compare Match A
|
||||
IRQ_TIMER2_OVF = 9 // Timer/Counter2 Overflow
|
||||
IRQ_TIMER1_CAPT = 10 // Timer/Counter1 Capture Event
|
||||
IRQ_TIMER1_COMPA = 11 // Timer/Counter1 Compare Match A
|
||||
IRQ_TIMER1_COMPB = 12 // Timer/Counter1 Compare Match B
|
||||
IRQ_TIMER1_OVF = 13 // Timer/Counter1 Overflow
|
||||
IRQ_TIMER0_COMPA = 14 // TimerCounter0 Compare Match A
|
||||
IRQ_TIMER0_COMPB = 15 // TimerCounter0 Compare Match B
|
||||
IRQ_TIMER0_OVF = 16 // Timer/Couner0 Overflow
|
||||
IRQ_SPI_STC = 17 // SPI Serial Transfer Complete
|
||||
IRQ_USART_RX = 18 // USART Rx Complete
|
||||
IRQ_USART_UDRE = 19 // USART, Data Register Empty
|
||||
IRQ_USART_TX = 20 // USART Tx Complete
|
||||
IRQ_ADC = 21 // ADC Conversion Complete
|
||||
IRQ_EE_READY = 22 // EEPROM Ready
|
||||
IRQ_ANALOG_COMP = 23 // Analog Comparator
|
||||
IRQ_TWI = 24 // Two-wire Serial Interface
|
||||
IRQ_SPM_Ready = 25 // Store Program Memory Read
|
||||
IRQ_max = 25 // Highest interrupt number on this device.
|
||||
)
|
||||
|
||||
// Peripherals
|
||||
var (
|
||||
// Fuses
|
||||
FUSE = struct {
|
||||
EXTENDED __reg
|
||||
HIGH __reg
|
||||
LOW __reg
|
||||
}{
|
||||
EXTENDED: 0x2,
|
||||
HIGH: 0x1,
|
||||
LOW: 0x0,
|
||||
}
|
||||
|
||||
// Lockbits
|
||||
LOCKBIT = struct {
|
||||
LOCKBIT __reg
|
||||
}{
|
||||
LOCKBIT: 0x0,
|
||||
}
|
||||
|
||||
// USART
|
||||
USART = struct {
|
||||
UDR0 __reg
|
||||
UCSR0A __reg
|
||||
UCSR0B __reg
|
||||
UCSR0C __reg
|
||||
UBRR0L __reg
|
||||
UBRR0H __reg
|
||||
}{
|
||||
UDR0: 0xc6, // USART I/O Data Register
|
||||
UCSR0A: 0xc0, // USART Control and Status Register A
|
||||
UCSR0B: 0xc1, // USART Control and Status Register B
|
||||
UCSR0C: 0xc2, // USART Control and Status Register C
|
||||
UBRR0L: 0xc4, // USART Baud Rate Register Bytes
|
||||
UBRR0H: 0xc4, // USART Baud Rate Register Bytes
|
||||
}
|
||||
|
||||
// Two Wire Serial Interface
|
||||
TWI = struct {
|
||||
TWAMR __reg
|
||||
TWBR __reg
|
||||
TWCR __reg
|
||||
TWSR __reg
|
||||
TWDR __reg
|
||||
TWAR __reg
|
||||
}{
|
||||
TWAMR: 0xbd, // TWI (Slave) Address Mask Register
|
||||
TWBR: 0xb8, // TWI Bit Rate register
|
||||
TWCR: 0xbc, // TWI Control Register
|
||||
TWSR: 0xb9, // TWI Status Register
|
||||
TWDR: 0xbb, // TWI Data register
|
||||
TWAR: 0xba, // TWI (Slave) Address register
|
||||
}
|
||||
|
||||
// Timer/Counter, 16-bit
|
||||
TC16 = struct {
|
||||
TIMSK1 __reg
|
||||
TIFR1 __reg
|
||||
TCCR1A __reg
|
||||
TCCR1B __reg
|
||||
TCCR1C __reg
|
||||
TCNT1L __reg
|
||||
TCNT1H __reg
|
||||
OCR1AL __reg
|
||||
OCR1AH __reg
|
||||
OCR1BL __reg
|
||||
OCR1BH __reg
|
||||
ICR1L __reg
|
||||
ICR1H __reg
|
||||
}{
|
||||
TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register
|
||||
TIFR1: 0x36, // Timer/Counter Interrupt Flag register
|
||||
TCCR1A: 0x80, // Timer/Counter1 Control Register A
|
||||
TCCR1B: 0x81, // Timer/Counter1 Control Register B
|
||||
TCCR1C: 0x82, // Timer/Counter1 Control Register C
|
||||
TCNT1L: 0x84, // Timer/Counter1 Bytes
|
||||
TCNT1H: 0x84, // Timer/Counter1 Bytes
|
||||
OCR1AL: 0x88, // Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1AH: 0x88, // Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register Bytes
|
||||
ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit Async
|
||||
TC8_ASYNC = struct {
|
||||
TIMSK2 __reg
|
||||
TIFR2 __reg
|
||||
TCCR2A __reg
|
||||
TCCR2B __reg
|
||||
TCNT2 __reg
|
||||
OCR2B __reg
|
||||
OCR2A __reg
|
||||
ASSR __reg
|
||||
}{
|
||||
TIMSK2: 0x70, // Timer/Counter Interrupt Mask register
|
||||
TIFR2: 0x37, // Timer/Counter Interrupt Flag Register
|
||||
TCCR2A: 0xb0, // Timer/Counter2 Control Register A
|
||||
TCCR2B: 0xb1, // Timer/Counter2 Control Register B
|
||||
TCNT2: 0xb2, // Timer/Counter2
|
||||
OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B
|
||||
OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A
|
||||
ASSR: 0xb6, // Asynchronous Status Register
|
||||
}
|
||||
|
||||
// Analog-to-Digital Converter
|
||||
ADC = struct {
|
||||
ADMUX __reg
|
||||
ADCL __reg
|
||||
ADCH __reg
|
||||
ADCSRA __reg
|
||||
ADCSRB __reg
|
||||
DIDR0 __reg
|
||||
}{
|
||||
ADMUX: 0x7c, // The ADC multiplexer Selection Register
|
||||
ADCL: 0x78, // ADC Data Register Bytes
|
||||
ADCH: 0x78, // ADC Data Register Bytes
|
||||
ADCSRA: 0x7a, // The ADC Control and Status register A
|
||||
ADCSRB: 0x7b, // The ADC Control and Status register B
|
||||
DIDR0: 0x7e, // Digital Input Disable Register
|
||||
}
|
||||
|
||||
// Analog Comparator
|
||||
AC = struct {
|
||||
ACSR __reg
|
||||
DIDR1 __reg
|
||||
}{
|
||||
ACSR: 0x50, // Analog Comparator Control And Status Register
|
||||
DIDR1: 0x7f, // Digital Input Disable Register 1
|
||||
}
|
||||
|
||||
// I/O Port
|
||||
PORT = struct {
|
||||
PORTB __reg
|
||||
DDRB __reg
|
||||
PINB __reg
|
||||
PORTC __reg
|
||||
DDRC __reg
|
||||
PINC __reg
|
||||
PORTD __reg
|
||||
DDRD __reg
|
||||
PIND __reg
|
||||
}{
|
||||
PORTB: 0x25, // Port B Data Register
|
||||
DDRB: 0x24, // Port B Data Direction Register
|
||||
PINB: 0x23, // Port B Input Pins
|
||||
PORTC: 0x28, // Port C Data Register
|
||||
DDRC: 0x27, // Port C Data Direction Register
|
||||
PINC: 0x26, // Port C Input Pins
|
||||
PORTD: 0x2b, // Port D Data Register
|
||||
DDRD: 0x2a, // Port D Data Direction Register
|
||||
PIND: 0x29, // Port D Input Pins
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit
|
||||
TC8 = struct {
|
||||
OCR0B __reg
|
||||
OCR0A __reg
|
||||
TCNT0 __reg
|
||||
TCCR0B __reg
|
||||
TCCR0A __reg
|
||||
TIMSK0 __reg
|
||||
TIFR0 __reg
|
||||
}{
|
||||
OCR0B: 0x48, // Timer/Counter0 Output Compare Register
|
||||
OCR0A: 0x47, // Timer/Counter0 Output Compare Register
|
||||
TCNT0: 0x46, // Timer/Counter0
|
||||
TCCR0B: 0x45, // Timer/Counter Control Register B
|
||||
TCCR0A: 0x44, // Timer/Counter Control Register A
|
||||
TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register
|
||||
TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register
|
||||
}
|
||||
|
||||
// External Interrupts
|
||||
EXINT = struct {
|
||||
EICRA __reg
|
||||
EIMSK __reg
|
||||
EIFR __reg
|
||||
PCICR __reg
|
||||
PCMSK2 __reg
|
||||
PCMSK1 __reg
|
||||
PCMSK0 __reg
|
||||
PCIFR __reg
|
||||
}{
|
||||
EICRA: 0x69, // External Interrupt Control Register
|
||||
EIMSK: 0x3d, // External Interrupt Mask Register
|
||||
EIFR: 0x3c, // External Interrupt Flag Register
|
||||
PCICR: 0x68, // Pin Change Interrupt Control Register
|
||||
PCMSK2: 0x6d, // Pin Change Mask Register 2
|
||||
PCMSK1: 0x6c, // Pin Change Mask Register 1
|
||||
PCMSK0: 0x6b, // Pin Change Mask Register 0
|
||||
PCIFR: 0x3b, // Pin Change Interrupt Flag Register
|
||||
}
|
||||
|
||||
// Serial Peripheral Interface
|
||||
SPI = struct {
|
||||
SPDR __reg
|
||||
SPSR __reg
|
||||
SPCR __reg
|
||||
}{
|
||||
SPDR: 0x4e, // SPI Data Register
|
||||
SPSR: 0x4d, // SPI Status Register
|
||||
SPCR: 0x4c, // SPI Control Register
|
||||
}
|
||||
|
||||
// Watchdog Timer
|
||||
WDT = struct {
|
||||
WDTCSR __reg
|
||||
}{
|
||||
WDTCSR: 0x60, // Watchdog Timer Control Register
|
||||
}
|
||||
|
||||
// EEPROM
|
||||
EEPROM = struct {
|
||||
EEARL __reg
|
||||
EEARH __reg
|
||||
EEDR __reg
|
||||
EECR __reg
|
||||
}{
|
||||
EEARL: 0x41, // EEPROM Address Register Bytes
|
||||
EEARH: 0x41, // EEPROM Address Register Bytes
|
||||
EEDR: 0x40, // EEPROM Data Register
|
||||
EECR: 0x3f, // EEPROM Control Register
|
||||
}
|
||||
|
||||
// CPU Registers
|
||||
CPU = struct {
|
||||
PRR __reg
|
||||
OSCCAL __reg
|
||||
CLKPR __reg
|
||||
SREG __reg
|
||||
SPL __reg
|
||||
SPH __reg
|
||||
SPMCSR __reg
|
||||
MCUCR __reg
|
||||
MCUSR __reg
|
||||
SMCR __reg
|
||||
GPIOR2 __reg
|
||||
GPIOR1 __reg
|
||||
GPIOR0 __reg
|
||||
}{
|
||||
PRR: 0x64, // Power Reduction Register
|
||||
OSCCAL: 0x66, // Oscillator Calibration Value
|
||||
CLKPR: 0x61, // Clock Prescale Register
|
||||
SREG: 0x5f, // Status Register
|
||||
SPL: 0x5d, // Stack Pointer
|
||||
SPH: 0x5d, // Stack Pointer
|
||||
SPMCSR: 0x57, // Store Program Memory Control and Status Register
|
||||
MCUCR: 0x55, // MCU Control Register
|
||||
MCUSR: 0x54, // MCU Status Register
|
||||
SMCR: 0x53, // Sleep Mode Control Register
|
||||
GPIOR2: 0x4b, // General Purpose I/O Register 2
|
||||
GPIOR1: 0x4a, // General Purpose I/O Register 1
|
||||
GPIOR0: 0x3e, // General Purpose I/O Register 0
|
||||
}
|
||||
)
|
||||
|
||||
// Bitfields for FUSE: Fuses
|
||||
const (
|
||||
// EXTENDED
|
||||
EXTENDED_BOOTSZ = 0x6 // Select boot size
|
||||
EXTENDED_BOOTRST = 0x1 // Boot Reset vector Enabled
|
||||
|
||||
// HIGH
|
||||
HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PC6 as i/o pin)
|
||||
HIGH_DWEN = 0x40 // Debug Wire enable
|
||||
HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled
|
||||
HIGH_WDTON = 0x10 // Watch-dog Timer always on
|
||||
HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle
|
||||
HIGH_BODLEVEL = 0x7 // Brown-out Detector trigger level
|
||||
|
||||
// LOW
|
||||
LOW_CKDIV8 = 0x80 // Divide clock by 8 internally
|
||||
LOW_CKOUT = 0x40 // Clock output on PORTB0
|
||||
LOW_SUT_CKSEL = 0x3f // Select Clock Source
|
||||
)
|
||||
|
||||
// Bitfields for LOCKBIT: Lockbits
|
||||
const (
|
||||
// LOCKBIT
|
||||
LOCKBIT_LB = 0x3 // Memory Lock
|
||||
LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode
|
||||
LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode
|
||||
)
|
||||
|
||||
// Bitfields for USART: USART
|
||||
const (
|
||||
// UCSR0A: USART Control and Status Register A
|
||||
UCSR0A_RXC0 = 0x80 // USART Receive Complete
|
||||
UCSR0A_TXC0 = 0x40 // USART Transmitt Complete
|
||||
UCSR0A_UDRE0 = 0x20 // USART Data Register Empty
|
||||
UCSR0A_FE0 = 0x10 // Framing Error
|
||||
UCSR0A_DOR0 = 0x8 // Data overRun
|
||||
UCSR0A_UPE0 = 0x4 // Parity Error
|
||||
UCSR0A_U2X0 = 0x2 // Double the USART transmission speed
|
||||
UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode
|
||||
|
||||
// UCSR0B: USART Control and Status Register B
|
||||
UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable
|
||||
UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable
|
||||
UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable
|
||||
UCSR0B_RXEN0 = 0x10 // Receiver Enable
|
||||
UCSR0B_TXEN0 = 0x8 // Transmitter Enable
|
||||
UCSR0B_UCSZ02 = 0x4 // Character Size
|
||||
UCSR0B_RXB80 = 0x2 // Receive Data Bit 8
|
||||
UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8
|
||||
|
||||
// UCSR0C: USART Control and Status Register C
|
||||
UCSR0C_UMSEL0 = 0xc0 // USART Mode Select
|
||||
UCSR0C_UPM0 = 0x30 // Parity Mode Bits
|
||||
UCSR0C_USBS0 = 0x8 // Stop Bit Select
|
||||
UCSR0C_UCSZ0 = 0x6 // Character Size
|
||||
UCSR0C_UCPOL0 = 0x1 // Clock Polarity
|
||||
)
|
||||
|
||||
// Bitfields for TWI: Two Wire Serial Interface
|
||||
const (
|
||||
// TWAMR: TWI (Slave) Address Mask Register
|
||||
TWAMR_TWAM = 0xfe
|
||||
|
||||
// TWCR: TWI Control Register
|
||||
TWCR_TWINT = 0x80 // TWI Interrupt Flag
|
||||
TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit
|
||||
TWCR_TWSTA = 0x20 // TWI Start Condition Bit
|
||||
TWCR_TWSTO = 0x10 // TWI Stop Condition Bit
|
||||
TWCR_TWWC = 0x8 // TWI Write Collition Flag
|
||||
TWCR_TWEN = 0x4 // TWI Enable Bit
|
||||
TWCR_TWIE = 0x1 // TWI Interrupt Enable
|
||||
|
||||
// TWSR: TWI Status Register
|
||||
TWSR_TWS = 0xf8 // TWI Status
|
||||
TWSR_TWPS = 0x3 // TWI Prescaler
|
||||
|
||||
// TWAR: TWI (Slave) Address register
|
||||
TWAR_TWA = 0xfe // TWI (Slave) Address register Bits
|
||||
TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit
|
||||
)
|
||||
|
||||
// Bitfields for TC16: Timer/Counter, 16-bit
|
||||
const (
|
||||
// TIMSK1: Timer/Counter Interrupt Mask Register
|
||||
TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable
|
||||
TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output CompareB Match Interrupt Enable
|
||||
TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output CompareA Match Interrupt Enable
|
||||
TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable
|
||||
|
||||
// TIFR1: Timer/Counter Interrupt Flag register
|
||||
TIFR1_ICF1 = 0x20 // Input Capture Flag 1
|
||||
TIFR1_OCF1B = 0x4 // Output Compare Flag 1B
|
||||
TIFR1_OCF1A = 0x2 // Output Compare Flag 1A
|
||||
TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag
|
||||
|
||||
// TCCR1A: Timer/Counter1 Control Register A
|
||||
TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits
|
||||
TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits
|
||||
TCCR1A_WGM1 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TCCR1B: Timer/Counter1 Control Register B
|
||||
TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler
|
||||
TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select
|
||||
TCCR1B_WGM1 = 0x18 // Waveform Generation Mode
|
||||
TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1
|
||||
|
||||
// TCCR1C: Timer/Counter1 Control Register C
|
||||
TCCR1C_FOC1A = 0x80
|
||||
TCCR1C_FOC1B = 0x40
|
||||
)
|
||||
|
||||
// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async
|
||||
const (
|
||||
// TIMSK2: Timer/Counter Interrupt Mask register
|
||||
TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable
|
||||
TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable
|
||||
TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable
|
||||
|
||||
// TIFR2: Timer/Counter Interrupt Flag Register
|
||||
TIFR2_OCF2B = 0x4 // Output Compare Flag 2B
|
||||
TIFR2_OCF2A = 0x2 // Output Compare Flag 2A
|
||||
TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag
|
||||
|
||||
// TCCR2A: Timer/Counter2 Control Register A
|
||||
TCCR2A_COM2A = 0xc0 // Compare Output Mode bits
|
||||
TCCR2A_COM2B = 0x30 // Compare Output Mode bits
|
||||
TCCR2A_WGM2 = 0x3 // Waveform Genration Mode
|
||||
|
||||
// TCCR2B: Timer/Counter2 Control Register B
|
||||
TCCR2B_FOC2A = 0x80 // Force Output Compare A
|
||||
TCCR2B_FOC2B = 0x40 // Force Output Compare B
|
||||
TCCR2B_WGM22 = 0x8 // Waveform Generation Mode
|
||||
TCCR2B_CS2 = 0x7 // Clock Select bits
|
||||
|
||||
// ASSR: Asynchronous Status Register
|
||||
ASSR_EXCLK = 0x40 // Enable External Clock Input
|
||||
ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2
|
||||
ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy
|
||||
ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy
|
||||
ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy
|
||||
ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy
|
||||
ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy
|
||||
)
|
||||
|
||||
// Bitfields for ADC: Analog-to-Digital Converter
|
||||
const (
|
||||
// ADMUX: The ADC multiplexer Selection Register
|
||||
ADMUX_REFS = 0xc0 // Reference Selection Bits
|
||||
ADMUX_ADLAR = 0x20 // Left Adjust Result
|
||||
ADMUX_MUX = 0xf // Analog Channel Selection Bits
|
||||
|
||||
// ADCSRA: The ADC Control and Status register A
|
||||
ADCSRA_ADEN = 0x80 // ADC Enable
|
||||
ADCSRA_ADSC = 0x40 // ADC Start Conversion
|
||||
ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable
|
||||
ADCSRA_ADIF = 0x10 // ADC Interrupt Flag
|
||||
ADCSRA_ADIE = 0x8 // ADC Interrupt Enable
|
||||
ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits
|
||||
|
||||
// ADCSRB: The ADC Control and Status register B
|
||||
ADCSRB_ACME = 0x40
|
||||
ADCSRB_ADTS = 0x7 // ADC Auto Trigger Source bits
|
||||
|
||||
// DIDR0: Digital Input Disable Register
|
||||
DIDR0_ADC5D = 0x20
|
||||
DIDR0_ADC4D = 0x10
|
||||
DIDR0_ADC3D = 0x8
|
||||
DIDR0_ADC2D = 0x4
|
||||
DIDR0_ADC1D = 0x2
|
||||
DIDR0_ADC0D = 0x1
|
||||
)
|
||||
|
||||
// Bitfields for AC: Analog Comparator
|
||||
const (
|
||||
// ACSR: Analog Comparator Control And Status Register
|
||||
ACSR_ACD = 0x80 // Analog Comparator Disable
|
||||
ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select
|
||||
ACSR_ACO = 0x20 // Analog Compare Output
|
||||
ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag
|
||||
ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable
|
||||
ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable
|
||||
ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits
|
||||
|
||||
// DIDR1: Digital Input Disable Register 1
|
||||
DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable
|
||||
DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable
|
||||
)
|
||||
|
||||
// Bitfields for TC8: Timer/Counter, 8-bit
|
||||
const (
|
||||
// TCCR0B: Timer/Counter Control Register B
|
||||
TCCR0B_FOC0A = 0x80 // Force Output Compare A
|
||||
TCCR0B_FOC0B = 0x40 // Force Output Compare B
|
||||
TCCR0B_WGM02 = 0x8
|
||||
TCCR0B_CS0 = 0x7 // Clock Select
|
||||
|
||||
// TCCR0A: Timer/Counter Control Register A
|
||||
TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode
|
||||
TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm
|
||||
TCCR0A_WGM0 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TIMSK0: Timer/Counter0 Interrupt Mask Register
|
||||
TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable
|
||||
TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable
|
||||
TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable
|
||||
|
||||
// TIFR0: Timer/Counter0 Interrupt Flag register
|
||||
TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B
|
||||
TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A
|
||||
TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag
|
||||
)
|
||||
|
||||
// Bitfields for EXINT: External Interrupts
|
||||
const (
|
||||
// EICRA: External Interrupt Control Register
|
||||
EICRA_ISC1 = 0xc // External Interrupt Sense Control 1 Bits
|
||||
EICRA_ISC0 = 0x3 // External Interrupt Sense Control 0 Bits
|
||||
|
||||
// EIMSK: External Interrupt Mask Register
|
||||
EIMSK_INT = 0x3 // External Interrupt Request 1 Enable
|
||||
|
||||
// EIFR: External Interrupt Flag Register
|
||||
EIFR_INTF = 0x3 // External Interrupt Flags
|
||||
|
||||
// PCICR: Pin Change Interrupt Control Register
|
||||
PCICR_PCIE = 0x7 // Pin Change Interrupt Enables
|
||||
|
||||
// PCMSK2: Pin Change Mask Register 2
|
||||
PCMSK2_PCINT = 0xff // Pin Change Enable Masks
|
||||
|
||||
// PCMSK1: Pin Change Mask Register 1
|
||||
PCMSK1_PCINT = 0x7f // Pin Change Enable Masks
|
||||
|
||||
// PCMSK0: Pin Change Mask Register 0
|
||||
PCMSK0_PCINT = 0xff // Pin Change Enable Masks
|
||||
|
||||
// PCIFR: Pin Change Interrupt Flag Register
|
||||
PCIFR_PCIF = 0x7 // Pin Change Interrupt Flags
|
||||
)
|
||||
|
||||
// Bitfields for SPI: Serial Peripheral Interface
|
||||
const (
|
||||
// SPSR: SPI Status Register
|
||||
SPSR_SPIF = 0x80 // SPI Interrupt Flag
|
||||
SPSR_WCOL = 0x40 // Write Collision Flag
|
||||
SPSR_SPI2X = 0x1 // Double SPI Speed Bit
|
||||
|
||||
// SPCR: SPI Control Register
|
||||
SPCR_SPIE = 0x80 // SPI Interrupt Enable
|
||||
SPCR_SPE = 0x40 // SPI Enable
|
||||
SPCR_DORD = 0x20 // Data Order
|
||||
SPCR_MSTR = 0x10 // Master/Slave Select
|
||||
SPCR_CPOL = 0x8 // Clock polarity
|
||||
SPCR_CPHA = 0x4 // Clock Phase
|
||||
SPCR_SPR = 0x3 // SPI Clock Rate Selects
|
||||
)
|
||||
|
||||
// Bitfields for WDT: Watchdog Timer
|
||||
const (
|
||||
// WDTCSR: Watchdog Timer Control Register
|
||||
WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag
|
||||
WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable
|
||||
WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits
|
||||
WDTCSR_WDCE = 0x10 // Watchdog Change Enable
|
||||
WDTCSR_WDE = 0x8 // Watch Dog Enable
|
||||
)
|
||||
|
||||
// Bitfields for EEPROM: EEPROM
|
||||
const (
|
||||
// EECR: EEPROM Control Register
|
||||
EECR_EEPM = 0x30 // EEPROM Programming Mode Bits
|
||||
EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable
|
||||
EECR_EEMPE = 0x4 // EEPROM Master Write Enable
|
||||
EECR_EEPE = 0x2 // EEPROM Write Enable
|
||||
EECR_EERE = 0x1 // EEPROM Read Enable
|
||||
)
|
||||
|
||||
// Bitfields for CPU: CPU Registers
|
||||
const (
|
||||
// PRR: Power Reduction Register
|
||||
PRR_PRTWI = 0x80 // Power Reduction TWI
|
||||
PRR_PRTIM2 = 0x40 // Power Reduction Timer/Counter2
|
||||
PRR_PRTIM0 = 0x20 // Power Reduction Timer/Counter0
|
||||
PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1
|
||||
PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface
|
||||
PRR_PRUSART0 = 0x2 // Power Reduction USART
|
||||
PRR_PRADC = 0x1 // Power Reduction ADC
|
||||
|
||||
// OSCCAL: Oscillator Calibration Value
|
||||
OSCCAL_OSCCAL = 0xff // Oscillator Calibration
|
||||
|
||||
// CLKPR: Clock Prescale Register
|
||||
CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable
|
||||
CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits
|
||||
|
||||
// SREG: Status Register
|
||||
SREG_I = 0x80 // Global Interrupt Enable
|
||||
SREG_T = 0x40 // Bit Copy Storage
|
||||
SREG_H = 0x20 // Half Carry Flag
|
||||
SREG_S = 0x10 // Sign Bit
|
||||
SREG_V = 0x8 // Two's Complement Overflow Flag
|
||||
SREG_N = 0x4 // Negative Flag
|
||||
SREG_Z = 0x2 // Zero Flag
|
||||
SREG_C = 0x1 // Carry Flag
|
||||
|
||||
// SPMCSR: Store Program Memory Control and Status Register
|
||||
SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable
|
||||
SPMCSR_RWWSB = 0x40 // Read-While-Write Section Busy
|
||||
SPMCSR_RWWSRE = 0x10 // Read-While-Write section read enable
|
||||
SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set
|
||||
SPMCSR_PGWRT = 0x4 // Page Write
|
||||
SPMCSR_PGERS = 0x2 // Page Erase
|
||||
SPMCSR_SELFPRGEN = 0x1 // Self Programming Enable
|
||||
|
||||
// MCUCR: MCU Control Register
|
||||
MCUCR_BODS = 0x40 // BOD Sleep
|
||||
MCUCR_BODSE = 0x20 // BOD Sleep Enable
|
||||
MCUCR_PUD = 0x10
|
||||
MCUCR_IVSEL = 0x2
|
||||
MCUCR_IVCE = 0x1
|
||||
|
||||
// MCUSR: MCU Status Register
|
||||
MCUSR_WDRF = 0x8 // Watchdog Reset Flag
|
||||
MCUSR_BORF = 0x4 // Brown-out Reset Flag
|
||||
MCUSR_EXTRF = 0x2 // External Reset Flag
|
||||
MCUSR_PORF = 0x1 // Power-on reset flag
|
||||
|
||||
// SMCR: Sleep Mode Control Register
|
||||
SMCR_SM = 0xe // Sleep Mode Select Bits
|
||||
SMCR_SE = 0x1 // Sleep Enable
|
||||
)
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from ATmega168P.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x4000;
|
||||
__ram_size = 0x400;
|
||||
__num_isrs = 26;
|
||||
|
|
@ -1,643 +0,0 @@
|
|||
// Automatically generated file. DO NOT EDIT.
|
||||
// Generated by gen-device.py from ATmega168PA.atdf, see http://packs.download.atmel.com/
|
||||
|
||||
// +build avr,atmega168pa
|
||||
|
||||
// Device information for the ATmega168PA.
|
||||
//
|
||||
package avr
|
||||
|
||||
// Magic type name for the compiler.
|
||||
type __reg uint8
|
||||
|
||||
// Export this magic type name.
|
||||
type RegValue = __reg
|
||||
|
||||
// Some information about this device.
|
||||
const (
|
||||
DEVICE = "ATmega168PA"
|
||||
ARCH = "AVR8"
|
||||
FAMILY = "megaAVR"
|
||||
)
|
||||
|
||||
// Interrupts
|
||||
const (
|
||||
IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset
|
||||
IRQ_INT0 = 1 // External Interrupt Request 0
|
||||
IRQ_INT1 = 2 // External Interrupt Request 1
|
||||
IRQ_PCINT0 = 3 // Pin Change Interrupt Request 0
|
||||
IRQ_PCINT1 = 4 // Pin Change Interrupt Request 0
|
||||
IRQ_PCINT2 = 5 // Pin Change Interrupt Request 1
|
||||
IRQ_WDT = 6 // Watchdog Time-out Interrupt
|
||||
IRQ_TIMER2_COMPA = 7 // Timer/Counter2 Compare Match A
|
||||
IRQ_TIMER2_COMPB = 8 // Timer/Counter2 Compare Match A
|
||||
IRQ_TIMER2_OVF = 9 // Timer/Counter2 Overflow
|
||||
IRQ_TIMER1_CAPT = 10 // Timer/Counter1 Capture Event
|
||||
IRQ_TIMER1_COMPA = 11 // Timer/Counter1 Compare Match A
|
||||
IRQ_TIMER1_COMPB = 12 // Timer/Counter1 Compare Match B
|
||||
IRQ_TIMER1_OVF = 13 // Timer/Counter1 Overflow
|
||||
IRQ_TIMER0_COMPA = 14 // TimerCounter0 Compare Match A
|
||||
IRQ_TIMER0_COMPB = 15 // TimerCounter0 Compare Match B
|
||||
IRQ_TIMER0_OVF = 16 // Timer/Couner0 Overflow
|
||||
IRQ_SPI_STC = 17 // SPI Serial Transfer Complete
|
||||
IRQ_USART_RX = 18 // USART Rx Complete
|
||||
IRQ_USART_UDRE = 19 // USART, Data Register Empty
|
||||
IRQ_USART_TX = 20 // USART Tx Complete
|
||||
IRQ_ADC = 21 // ADC Conversion Complete
|
||||
IRQ_EE_READY = 22 // EEPROM Ready
|
||||
IRQ_ANALOG_COMP = 23 // Analog Comparator
|
||||
IRQ_TWI = 24 // Two-wire Serial Interface
|
||||
IRQ_SPM_Ready = 25 // Store Program Memory Read
|
||||
IRQ_max = 25 // Highest interrupt number on this device.
|
||||
)
|
||||
|
||||
// Peripherals
|
||||
var (
|
||||
// Fuses
|
||||
FUSE = struct {
|
||||
EXTENDED __reg
|
||||
HIGH __reg
|
||||
LOW __reg
|
||||
}{
|
||||
EXTENDED: 0x2,
|
||||
HIGH: 0x1,
|
||||
LOW: 0x0,
|
||||
}
|
||||
|
||||
// Lockbits
|
||||
LOCKBIT = struct {
|
||||
LOCKBIT __reg
|
||||
}{
|
||||
LOCKBIT: 0x0,
|
||||
}
|
||||
|
||||
// USART
|
||||
USART = struct {
|
||||
UDR0 __reg
|
||||
UCSR0A __reg
|
||||
UCSR0B __reg
|
||||
UCSR0C __reg
|
||||
UBRR0L __reg
|
||||
UBRR0H __reg
|
||||
}{
|
||||
UDR0: 0xc6, // USART I/O Data Register
|
||||
UCSR0A: 0xc0, // USART Control and Status Register A
|
||||
UCSR0B: 0xc1, // USART Control and Status Register B
|
||||
UCSR0C: 0xc2, // USART Control and Status Register C
|
||||
UBRR0L: 0xc4, // USART Baud Rate Register Bytes
|
||||
UBRR0H: 0xc4, // USART Baud Rate Register Bytes
|
||||
}
|
||||
|
||||
// Two Wire Serial Interface
|
||||
TWI = struct {
|
||||
TWAMR __reg
|
||||
TWBR __reg
|
||||
TWCR __reg
|
||||
TWSR __reg
|
||||
TWDR __reg
|
||||
TWAR __reg
|
||||
}{
|
||||
TWAMR: 0xbd, // TWI (Slave) Address Mask Register
|
||||
TWBR: 0xb8, // TWI Bit Rate register
|
||||
TWCR: 0xbc, // TWI Control Register
|
||||
TWSR: 0xb9, // TWI Status Register
|
||||
TWDR: 0xbb, // TWI Data register
|
||||
TWAR: 0xba, // TWI (Slave) Address register
|
||||
}
|
||||
|
||||
// Timer/Counter, 16-bit
|
||||
TC16 = struct {
|
||||
TIMSK1 __reg
|
||||
TIFR1 __reg
|
||||
TCCR1A __reg
|
||||
TCCR1B __reg
|
||||
TCCR1C __reg
|
||||
TCNT1L __reg
|
||||
TCNT1H __reg
|
||||
OCR1AL __reg
|
||||
OCR1AH __reg
|
||||
OCR1BL __reg
|
||||
OCR1BH __reg
|
||||
ICR1L __reg
|
||||
ICR1H __reg
|
||||
}{
|
||||
TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register
|
||||
TIFR1: 0x36, // Timer/Counter Interrupt Flag register
|
||||
TCCR1A: 0x80, // Timer/Counter1 Control Register A
|
||||
TCCR1B: 0x81, // Timer/Counter1 Control Register B
|
||||
TCCR1C: 0x82, // Timer/Counter1 Control Register C
|
||||
TCNT1L: 0x84, // Timer/Counter1 Bytes
|
||||
TCNT1H: 0x84, // Timer/Counter1 Bytes
|
||||
OCR1AL: 0x88, // Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1AH: 0x88, // Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register Bytes
|
||||
ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit Async
|
||||
TC8_ASYNC = struct {
|
||||
TIMSK2 __reg
|
||||
TIFR2 __reg
|
||||
TCCR2A __reg
|
||||
TCCR2B __reg
|
||||
TCNT2 __reg
|
||||
OCR2B __reg
|
||||
OCR2A __reg
|
||||
ASSR __reg
|
||||
}{
|
||||
TIMSK2: 0x70, // Timer/Counter Interrupt Mask register
|
||||
TIFR2: 0x37, // Timer/Counter Interrupt Flag Register
|
||||
TCCR2A: 0xb0, // Timer/Counter2 Control Register A
|
||||
TCCR2B: 0xb1, // Timer/Counter2 Control Register B
|
||||
TCNT2: 0xb2, // Timer/Counter2
|
||||
OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B
|
||||
OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A
|
||||
ASSR: 0xb6, // Asynchronous Status Register
|
||||
}
|
||||
|
||||
// Analog-to-Digital Converter
|
||||
ADC = struct {
|
||||
ADMUX __reg
|
||||
ADCL __reg
|
||||
ADCH __reg
|
||||
ADCSRA __reg
|
||||
ADCSRB __reg
|
||||
DIDR0 __reg
|
||||
}{
|
||||
ADMUX: 0x7c, // The ADC multiplexer Selection Register
|
||||
ADCL: 0x78, // ADC Data Register Bytes
|
||||
ADCH: 0x78, // ADC Data Register Bytes
|
||||
ADCSRA: 0x7a, // The ADC Control and Status register A
|
||||
ADCSRB: 0x7b, // The ADC Control and Status register B
|
||||
DIDR0: 0x7e, // Digital Input Disable Register
|
||||
}
|
||||
|
||||
// Analog Comparator
|
||||
AC = struct {
|
||||
ACSR __reg
|
||||
DIDR1 __reg
|
||||
}{
|
||||
ACSR: 0x50, // Analog Comparator Control And Status Register
|
||||
DIDR1: 0x7f, // Digital Input Disable Register 1
|
||||
}
|
||||
|
||||
// I/O Port
|
||||
PORT = struct {
|
||||
PORTB __reg
|
||||
DDRB __reg
|
||||
PINB __reg
|
||||
PORTC __reg
|
||||
DDRC __reg
|
||||
PINC __reg
|
||||
PORTD __reg
|
||||
DDRD __reg
|
||||
PIND __reg
|
||||
}{
|
||||
PORTB: 0x25, // Port B Data Register
|
||||
DDRB: 0x24, // Port B Data Direction Register
|
||||
PINB: 0x23, // Port B Input Pins
|
||||
PORTC: 0x28, // Port C Data Register
|
||||
DDRC: 0x27, // Port C Data Direction Register
|
||||
PINC: 0x26, // Port C Input Pins
|
||||
PORTD: 0x2b, // Port D Data Register
|
||||
DDRD: 0x2a, // Port D Data Direction Register
|
||||
PIND: 0x29, // Port D Input Pins
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit
|
||||
TC8 = struct {
|
||||
OCR0B __reg
|
||||
OCR0A __reg
|
||||
TCNT0 __reg
|
||||
TCCR0B __reg
|
||||
TCCR0A __reg
|
||||
TIMSK0 __reg
|
||||
TIFR0 __reg
|
||||
}{
|
||||
OCR0B: 0x48, // Timer/Counter0 Output Compare Register
|
||||
OCR0A: 0x47, // Timer/Counter0 Output Compare Register
|
||||
TCNT0: 0x46, // Timer/Counter0
|
||||
TCCR0B: 0x45, // Timer/Counter Control Register B
|
||||
TCCR0A: 0x44, // Timer/Counter Control Register A
|
||||
TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register
|
||||
TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register
|
||||
}
|
||||
|
||||
// External Interrupts
|
||||
EXINT = struct {
|
||||
EICRA __reg
|
||||
EIMSK __reg
|
||||
EIFR __reg
|
||||
PCICR __reg
|
||||
PCMSK2 __reg
|
||||
PCMSK1 __reg
|
||||
PCMSK0 __reg
|
||||
PCIFR __reg
|
||||
}{
|
||||
EICRA: 0x69, // External Interrupt Control Register
|
||||
EIMSK: 0x3d, // External Interrupt Mask Register
|
||||
EIFR: 0x3c, // External Interrupt Flag Register
|
||||
PCICR: 0x68, // Pin Change Interrupt Control Register
|
||||
PCMSK2: 0x6d, // Pin Change Mask Register 2
|
||||
PCMSK1: 0x6c, // Pin Change Mask Register 1
|
||||
PCMSK0: 0x6b, // Pin Change Mask Register 0
|
||||
PCIFR: 0x3b, // Pin Change Interrupt Flag Register
|
||||
}
|
||||
|
||||
// Serial Peripheral Interface
|
||||
SPI = struct {
|
||||
SPDR __reg
|
||||
SPSR __reg
|
||||
SPCR __reg
|
||||
}{
|
||||
SPDR: 0x4e, // SPI Data Register
|
||||
SPSR: 0x4d, // SPI Status Register
|
||||
SPCR: 0x4c, // SPI Control Register
|
||||
}
|
||||
|
||||
// Watchdog Timer
|
||||
WDT = struct {
|
||||
WDTCSR __reg
|
||||
}{
|
||||
WDTCSR: 0x60, // Watchdog Timer Control Register
|
||||
}
|
||||
|
||||
// EEPROM
|
||||
EEPROM = struct {
|
||||
EEARL __reg
|
||||
EEARH __reg
|
||||
EEDR __reg
|
||||
EECR __reg
|
||||
}{
|
||||
EEARL: 0x41, // EEPROM Address Register Bytes
|
||||
EEARH: 0x41, // EEPROM Address Register Bytes
|
||||
EEDR: 0x40, // EEPROM Data Register
|
||||
EECR: 0x3f, // EEPROM Control Register
|
||||
}
|
||||
|
||||
// CPU Registers
|
||||
CPU = struct {
|
||||
PRR __reg
|
||||
OSCCAL __reg
|
||||
CLKPR __reg
|
||||
SREG __reg
|
||||
SPL __reg
|
||||
SPH __reg
|
||||
SPMCSR __reg
|
||||
MCUCR __reg
|
||||
MCUSR __reg
|
||||
SMCR __reg
|
||||
GPIOR2 __reg
|
||||
GPIOR1 __reg
|
||||
GPIOR0 __reg
|
||||
}{
|
||||
PRR: 0x64, // Power Reduction Register
|
||||
OSCCAL: 0x66, // Oscillator Calibration Value
|
||||
CLKPR: 0x61, // Clock Prescale Register
|
||||
SREG: 0x5f, // Status Register
|
||||
SPL: 0x5d, // Stack Pointer
|
||||
SPH: 0x5d, // Stack Pointer
|
||||
SPMCSR: 0x57, // Store Program Memory Control and Status Register
|
||||
MCUCR: 0x55, // MCU Control Register
|
||||
MCUSR: 0x54, // MCU Status Register
|
||||
SMCR: 0x53, // Sleep Mode Control Register
|
||||
GPIOR2: 0x4b, // General Purpose I/O Register 2
|
||||
GPIOR1: 0x4a, // General Purpose I/O Register 1
|
||||
GPIOR0: 0x3e, // General Purpose I/O Register 0
|
||||
}
|
||||
)
|
||||
|
||||
// Bitfields for FUSE: Fuses
|
||||
const (
|
||||
// EXTENDED
|
||||
EXTENDED_BOOTSZ = 0x6 // Select boot size
|
||||
EXTENDED_BOOTRST = 0x1 // Boot Reset vector Enabled
|
||||
|
||||
// HIGH
|
||||
HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PC6 as i/o pin)
|
||||
HIGH_DWEN = 0x40 // Debug Wire enable
|
||||
HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled
|
||||
HIGH_WDTON = 0x10 // Watch-dog Timer always on
|
||||
HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle
|
||||
HIGH_BODLEVEL = 0x7 // Brown-out Detector trigger level
|
||||
|
||||
// LOW
|
||||
LOW_CKDIV8 = 0x80 // Divide clock by 8 internally
|
||||
LOW_CKOUT = 0x40 // Clock output on PORTB0
|
||||
LOW_SUT_CKSEL = 0x3f // Select Clock Source
|
||||
)
|
||||
|
||||
// Bitfields for LOCKBIT: Lockbits
|
||||
const (
|
||||
// LOCKBIT
|
||||
LOCKBIT_LB = 0x3 // Memory Lock
|
||||
LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode
|
||||
LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode
|
||||
)
|
||||
|
||||
// Bitfields for USART: USART
|
||||
const (
|
||||
// UCSR0A: USART Control and Status Register A
|
||||
UCSR0A_RXC0 = 0x80 // USART Receive Complete
|
||||
UCSR0A_TXC0 = 0x40 // USART Transmitt Complete
|
||||
UCSR0A_UDRE0 = 0x20 // USART Data Register Empty
|
||||
UCSR0A_FE0 = 0x10 // Framing Error
|
||||
UCSR0A_DOR0 = 0x8 // Data overRun
|
||||
UCSR0A_UPE0 = 0x4 // Parity Error
|
||||
UCSR0A_U2X0 = 0x2 // Double the USART transmission speed
|
||||
UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode
|
||||
|
||||
// UCSR0B: USART Control and Status Register B
|
||||
UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable
|
||||
UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable
|
||||
UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable
|
||||
UCSR0B_RXEN0 = 0x10 // Receiver Enable
|
||||
UCSR0B_TXEN0 = 0x8 // Transmitter Enable
|
||||
UCSR0B_UCSZ02 = 0x4 // Character Size
|
||||
UCSR0B_RXB80 = 0x2 // Receive Data Bit 8
|
||||
UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8
|
||||
|
||||
// UCSR0C: USART Control and Status Register C
|
||||
UCSR0C_UMSEL0 = 0xc0 // USART Mode Select
|
||||
UCSR0C_UPM0 = 0x30 // Parity Mode Bits
|
||||
UCSR0C_USBS0 = 0x8 // Stop Bit Select
|
||||
UCSR0C_UCSZ0 = 0x6 // Character Size
|
||||
UCSR0C_UCPOL0 = 0x1 // Clock Polarity
|
||||
)
|
||||
|
||||
// Bitfields for TWI: Two Wire Serial Interface
|
||||
const (
|
||||
// TWAMR: TWI (Slave) Address Mask Register
|
||||
TWAMR_TWAM = 0xfe
|
||||
|
||||
// TWCR: TWI Control Register
|
||||
TWCR_TWINT = 0x80 // TWI Interrupt Flag
|
||||
TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit
|
||||
TWCR_TWSTA = 0x20 // TWI Start Condition Bit
|
||||
TWCR_TWSTO = 0x10 // TWI Stop Condition Bit
|
||||
TWCR_TWWC = 0x8 // TWI Write Collition Flag
|
||||
TWCR_TWEN = 0x4 // TWI Enable Bit
|
||||
TWCR_TWIE = 0x1 // TWI Interrupt Enable
|
||||
|
||||
// TWSR: TWI Status Register
|
||||
TWSR_TWS = 0xf8 // TWI Status
|
||||
TWSR_TWPS = 0x3 // TWI Prescaler
|
||||
|
||||
// TWAR: TWI (Slave) Address register
|
||||
TWAR_TWA = 0xfe // TWI (Slave) Address register Bits
|
||||
TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit
|
||||
)
|
||||
|
||||
// Bitfields for TC16: Timer/Counter, 16-bit
|
||||
const (
|
||||
// TIMSK1: Timer/Counter Interrupt Mask Register
|
||||
TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable
|
||||
TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output CompareB Match Interrupt Enable
|
||||
TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output CompareA Match Interrupt Enable
|
||||
TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable
|
||||
|
||||
// TIFR1: Timer/Counter Interrupt Flag register
|
||||
TIFR1_ICF1 = 0x20 // Input Capture Flag 1
|
||||
TIFR1_OCF1B = 0x4 // Output Compare Flag 1B
|
||||
TIFR1_OCF1A = 0x2 // Output Compare Flag 1A
|
||||
TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag
|
||||
|
||||
// TCCR1A: Timer/Counter1 Control Register A
|
||||
TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits
|
||||
TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits
|
||||
TCCR1A_WGM1 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TCCR1B: Timer/Counter1 Control Register B
|
||||
TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler
|
||||
TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select
|
||||
TCCR1B_WGM1 = 0x18 // Waveform Generation Mode
|
||||
TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1
|
||||
|
||||
// TCCR1C: Timer/Counter1 Control Register C
|
||||
TCCR1C_FOC1A = 0x80
|
||||
TCCR1C_FOC1B = 0x40
|
||||
)
|
||||
|
||||
// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async
|
||||
const (
|
||||
// TIMSK2: Timer/Counter Interrupt Mask register
|
||||
TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable
|
||||
TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable
|
||||
TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable
|
||||
|
||||
// TIFR2: Timer/Counter Interrupt Flag Register
|
||||
TIFR2_OCF2B = 0x4 // Output Compare Flag 2B
|
||||
TIFR2_OCF2A = 0x2 // Output Compare Flag 2A
|
||||
TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag
|
||||
|
||||
// TCCR2A: Timer/Counter2 Control Register A
|
||||
TCCR2A_COM2A = 0xc0 // Compare Output Mode bits
|
||||
TCCR2A_COM2B = 0x30 // Compare Output Mode bits
|
||||
TCCR2A_WGM2 = 0x3 // Waveform Genration Mode
|
||||
|
||||
// TCCR2B: Timer/Counter2 Control Register B
|
||||
TCCR2B_FOC2A = 0x80 // Force Output Compare A
|
||||
TCCR2B_FOC2B = 0x40 // Force Output Compare B
|
||||
TCCR2B_WGM22 = 0x8 // Waveform Generation Mode
|
||||
TCCR2B_CS2 = 0x7 // Clock Select bits
|
||||
|
||||
// ASSR: Asynchronous Status Register
|
||||
ASSR_EXCLK = 0x40 // Enable External Clock Input
|
||||
ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2
|
||||
ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy
|
||||
ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy
|
||||
ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy
|
||||
ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy
|
||||
ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy
|
||||
)
|
||||
|
||||
// Bitfields for ADC: Analog-to-Digital Converter
|
||||
const (
|
||||
// ADMUX: The ADC multiplexer Selection Register
|
||||
ADMUX_REFS = 0xc0 // Reference Selection Bits
|
||||
ADMUX_ADLAR = 0x20 // Left Adjust Result
|
||||
ADMUX_MUX = 0xf // Analog Channel Selection Bits
|
||||
|
||||
// ADCSRA: The ADC Control and Status register A
|
||||
ADCSRA_ADEN = 0x80 // ADC Enable
|
||||
ADCSRA_ADSC = 0x40 // ADC Start Conversion
|
||||
ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable
|
||||
ADCSRA_ADIF = 0x10 // ADC Interrupt Flag
|
||||
ADCSRA_ADIE = 0x8 // ADC Interrupt Enable
|
||||
ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits
|
||||
|
||||
// ADCSRB: The ADC Control and Status register B
|
||||
ADCSRB_ACME = 0x40
|
||||
ADCSRB_ADTS = 0x7 // ADC Auto Trigger Source bits
|
||||
|
||||
// DIDR0: Digital Input Disable Register
|
||||
DIDR0_ADC5D = 0x20
|
||||
DIDR0_ADC4D = 0x10
|
||||
DIDR0_ADC3D = 0x8
|
||||
DIDR0_ADC2D = 0x4
|
||||
DIDR0_ADC1D = 0x2
|
||||
DIDR0_ADC0D = 0x1
|
||||
)
|
||||
|
||||
// Bitfields for AC: Analog Comparator
|
||||
const (
|
||||
// ACSR: Analog Comparator Control And Status Register
|
||||
ACSR_ACD = 0x80 // Analog Comparator Disable
|
||||
ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select
|
||||
ACSR_ACO = 0x20 // Analog Compare Output
|
||||
ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag
|
||||
ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable
|
||||
ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable
|
||||
ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits
|
||||
|
||||
// DIDR1: Digital Input Disable Register 1
|
||||
DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable
|
||||
DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable
|
||||
)
|
||||
|
||||
// Bitfields for TC8: Timer/Counter, 8-bit
|
||||
const (
|
||||
// TCCR0B: Timer/Counter Control Register B
|
||||
TCCR0B_FOC0A = 0x80 // Force Output Compare A
|
||||
TCCR0B_FOC0B = 0x40 // Force Output Compare B
|
||||
TCCR0B_WGM02 = 0x8
|
||||
TCCR0B_CS0 = 0x7 // Clock Select
|
||||
|
||||
// TCCR0A: Timer/Counter Control Register A
|
||||
TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode
|
||||
TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm
|
||||
TCCR0A_WGM0 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TIMSK0: Timer/Counter0 Interrupt Mask Register
|
||||
TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable
|
||||
TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable
|
||||
TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable
|
||||
|
||||
// TIFR0: Timer/Counter0 Interrupt Flag register
|
||||
TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B
|
||||
TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A
|
||||
TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag
|
||||
)
|
||||
|
||||
// Bitfields for EXINT: External Interrupts
|
||||
const (
|
||||
// EICRA: External Interrupt Control Register
|
||||
EICRA_ISC1 = 0xc // External Interrupt Sense Control 1 Bits
|
||||
EICRA_ISC0 = 0x3 // External Interrupt Sense Control 0 Bits
|
||||
|
||||
// EIMSK: External Interrupt Mask Register
|
||||
EIMSK_INT = 0x3 // External Interrupt Request 1 Enable
|
||||
|
||||
// EIFR: External Interrupt Flag Register
|
||||
EIFR_INTF = 0x3 // External Interrupt Flags
|
||||
|
||||
// PCICR: Pin Change Interrupt Control Register
|
||||
PCICR_PCIE = 0x7 // Pin Change Interrupt Enables
|
||||
|
||||
// PCMSK2: Pin Change Mask Register 2
|
||||
PCMSK2_PCINT = 0xff // Pin Change Enable Masks
|
||||
|
||||
// PCMSK1: Pin Change Mask Register 1
|
||||
PCMSK1_PCINT = 0x7f // Pin Change Enable Masks
|
||||
|
||||
// PCMSK0: Pin Change Mask Register 0
|
||||
PCMSK0_PCINT = 0xff // Pin Change Enable Masks
|
||||
|
||||
// PCIFR: Pin Change Interrupt Flag Register
|
||||
PCIFR_PCIF = 0x7 // Pin Change Interrupt Flags
|
||||
)
|
||||
|
||||
// Bitfields for SPI: Serial Peripheral Interface
|
||||
const (
|
||||
// SPSR: SPI Status Register
|
||||
SPSR_SPIF = 0x80 // SPI Interrupt Flag
|
||||
SPSR_WCOL = 0x40 // Write Collision Flag
|
||||
SPSR_SPI2X = 0x1 // Double SPI Speed Bit
|
||||
|
||||
// SPCR: SPI Control Register
|
||||
SPCR_SPIE = 0x80 // SPI Interrupt Enable
|
||||
SPCR_SPE = 0x40 // SPI Enable
|
||||
SPCR_DORD = 0x20 // Data Order
|
||||
SPCR_MSTR = 0x10 // Master/Slave Select
|
||||
SPCR_CPOL = 0x8 // Clock polarity
|
||||
SPCR_CPHA = 0x4 // Clock Phase
|
||||
SPCR_SPR = 0x3 // SPI Clock Rate Selects
|
||||
)
|
||||
|
||||
// Bitfields for WDT: Watchdog Timer
|
||||
const (
|
||||
// WDTCSR: Watchdog Timer Control Register
|
||||
WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag
|
||||
WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable
|
||||
WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits
|
||||
WDTCSR_WDCE = 0x10 // Watchdog Change Enable
|
||||
WDTCSR_WDE = 0x8 // Watch Dog Enable
|
||||
)
|
||||
|
||||
// Bitfields for EEPROM: EEPROM
|
||||
const (
|
||||
// EECR: EEPROM Control Register
|
||||
EECR_EEPM = 0x30 // EEPROM Programming Mode Bits
|
||||
EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable
|
||||
EECR_EEMPE = 0x4 // EEPROM Master Write Enable
|
||||
EECR_EEPE = 0x2 // EEPROM Write Enable
|
||||
EECR_EERE = 0x1 // EEPROM Read Enable
|
||||
)
|
||||
|
||||
// Bitfields for CPU: CPU Registers
|
||||
const (
|
||||
// PRR: Power Reduction Register
|
||||
PRR_PRTWI = 0x80 // Power Reduction TWI
|
||||
PRR_PRTIM2 = 0x40 // Power Reduction Timer/Counter2
|
||||
PRR_PRTIM0 = 0x20 // Power Reduction Timer/Counter0
|
||||
PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1
|
||||
PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface
|
||||
PRR_PRUSART0 = 0x2 // Power Reduction USART
|
||||
PRR_PRADC = 0x1 // Power Reduction ADC
|
||||
|
||||
// OSCCAL: Oscillator Calibration Value
|
||||
OSCCAL_OSCCAL = 0xff // Oscillator Calibration
|
||||
|
||||
// CLKPR: Clock Prescale Register
|
||||
CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable
|
||||
CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits
|
||||
|
||||
// SREG: Status Register
|
||||
SREG_I = 0x80 // Global Interrupt Enable
|
||||
SREG_T = 0x40 // Bit Copy Storage
|
||||
SREG_H = 0x20 // Half Carry Flag
|
||||
SREG_S = 0x10 // Sign Bit
|
||||
SREG_V = 0x8 // Two's Complement Overflow Flag
|
||||
SREG_N = 0x4 // Negative Flag
|
||||
SREG_Z = 0x2 // Zero Flag
|
||||
SREG_C = 0x1 // Carry Flag
|
||||
|
||||
// SPMCSR: Store Program Memory Control and Status Register
|
||||
SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable
|
||||
SPMCSR_RWWSB = 0x40 // Read-While-Write Section Busy
|
||||
SPMCSR_SIGRD = 0x20 // Signature Row Read
|
||||
SPMCSR_RWWSRE = 0x10 // Read-While-Write section read enable
|
||||
SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set
|
||||
SPMCSR_PGWRT = 0x4 // Page Write
|
||||
SPMCSR_PGERS = 0x2 // Page Erase
|
||||
SPMCSR_SPMEN = 0x1 // Store Program Memory
|
||||
|
||||
// MCUCR: MCU Control Register
|
||||
MCUCR_BODS = 0x40 // BOD Sleep
|
||||
MCUCR_BODSE = 0x20 // BOD Sleep Enable
|
||||
MCUCR_PUD = 0x10
|
||||
MCUCR_IVSEL = 0x2
|
||||
MCUCR_IVCE = 0x1
|
||||
|
||||
// MCUSR: MCU Status Register
|
||||
MCUSR_WDRF = 0x8 // Watchdog Reset Flag
|
||||
MCUSR_BORF = 0x4 // Brown-out Reset Flag
|
||||
MCUSR_EXTRF = 0x2 // External Reset Flag
|
||||
MCUSR_PORF = 0x1 // Power-on reset flag
|
||||
|
||||
// SMCR: Sleep Mode Control Register
|
||||
SMCR_SM = 0xe // Sleep Mode Select Bits
|
||||
SMCR_SE = 0x1 // Sleep Enable
|
||||
)
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from ATmega168PA.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x4000;
|
||||
__ram_size = 0x400;
|
||||
__num_isrs = 26;
|
||||
|
|
@ -1,685 +0,0 @@
|
|||
// Automatically generated file. DO NOT EDIT.
|
||||
// Generated by gen-device.py from ATmega168PB.atdf, see http://packs.download.atmel.com/
|
||||
|
||||
// +build avr,atmega168pb
|
||||
|
||||
// Device information for the ATmega168PB.
|
||||
//
|
||||
package avr
|
||||
|
||||
// Magic type name for the compiler.
|
||||
type __reg uint8
|
||||
|
||||
// Export this magic type name.
|
||||
type RegValue = __reg
|
||||
|
||||
// Some information about this device.
|
||||
const (
|
||||
DEVICE = "ATmega168PB"
|
||||
ARCH = "AVR8"
|
||||
FAMILY = "megaAVR"
|
||||
)
|
||||
|
||||
// Interrupts
|
||||
const (
|
||||
IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset
|
||||
IRQ_INT0 = 1 // External Interrupt Request 0
|
||||
IRQ_INT1 = 2 // External Interrupt Request 1
|
||||
IRQ_PCINT0 = 3 // Pin Change Interrupt Request 0
|
||||
IRQ_PCINT1 = 4 // Pin Change Interrupt Request 0
|
||||
IRQ_PCINT2 = 5 // Pin Change Interrupt Request 1
|
||||
IRQ_WDT = 6 // Watchdog Time-out Interrupt
|
||||
IRQ_TIMER2_COMPA = 7 // Timer/Counter2 Compare Match A
|
||||
IRQ_TIMER2_COMPB = 8 // Timer/Counter2 Compare Match A
|
||||
IRQ_TIMER2_OVF = 9 // Timer/Counter2 Overflow
|
||||
IRQ_TIMER1_CAPT = 10 // Timer/Counter1 Capture Event
|
||||
IRQ_TIMER1_COMPA = 11 // Timer/Counter1 Compare Match A
|
||||
IRQ_TIMER1_COMPB = 12 // Timer/Counter1 Compare Match B
|
||||
IRQ_TIMER1_OVF = 13 // Timer/Counter1 Overflow
|
||||
IRQ_TIMER0_COMPA = 14 // TimerCounter0 Compare Match A
|
||||
IRQ_TIMER0_COMPB = 15 // TimerCounter0 Compare Match B
|
||||
IRQ_TIMER0_OVF = 16 // Timer/Couner0 Overflow
|
||||
IRQ_SPI_STC = 17 // SPI Serial Transfer Complete
|
||||
IRQ_USART_RX = 18 // USART Rx Complete
|
||||
IRQ_USART_UDRE = 19 // USART, Data Register Empty
|
||||
IRQ_USART_TX = 20 // USART Tx Complete
|
||||
IRQ_ADC = 21 // ADC Conversion Complete
|
||||
IRQ_EE_READY = 22 // EEPROM Ready
|
||||
IRQ_ANALOG_COMP = 23 // Analog Comparator
|
||||
IRQ_TWI = 24 // Two-wire Serial Interface
|
||||
IRQ_SPM_Ready = 25 // Store Program Memory Read
|
||||
IRQ_USART_START = 26 // USART Start Edge Interrupt
|
||||
IRQ_max = 26 // Highest interrupt number on this device.
|
||||
)
|
||||
|
||||
// Peripherals
|
||||
var (
|
||||
// Fuses
|
||||
FUSE = struct {
|
||||
EXTENDED __reg
|
||||
HIGH __reg
|
||||
LOW __reg
|
||||
}{
|
||||
EXTENDED: 0x2,
|
||||
HIGH: 0x1,
|
||||
LOW: 0x0,
|
||||
}
|
||||
|
||||
// Lockbits
|
||||
LOCKBIT = struct {
|
||||
LOCKBIT __reg
|
||||
}{
|
||||
LOCKBIT: 0x0,
|
||||
}
|
||||
|
||||
// Device ID
|
||||
DEVICEID = struct {
|
||||
DEVID0 __reg
|
||||
DEVID1 __reg
|
||||
DEVID2 __reg
|
||||
DEVID3 __reg
|
||||
DEVID4 __reg
|
||||
DEVID5 __reg
|
||||
DEVID6 __reg
|
||||
DEVID7 __reg
|
||||
DEVID8 __reg
|
||||
}{
|
||||
DEVID0: 0xf0,
|
||||
DEVID1: 0xf1,
|
||||
DEVID2: 0xf2,
|
||||
DEVID3: 0xf3,
|
||||
DEVID4: 0xf4,
|
||||
DEVID5: 0xf5,
|
||||
DEVID6: 0xf6,
|
||||
DEVID7: 0xf7,
|
||||
DEVID8: 0xf8,
|
||||
}
|
||||
|
||||
// USART
|
||||
USART = struct {
|
||||
UDR0 __reg
|
||||
UCSR0A __reg
|
||||
UCSR0B __reg
|
||||
UCSR0C __reg
|
||||
UCSR0D __reg
|
||||
UBRR0L __reg
|
||||
UBRR0H __reg
|
||||
}{
|
||||
UDR0: 0xc6, // USART I/O Data Register
|
||||
UCSR0A: 0xc0, // USART Control and Status Register A
|
||||
UCSR0B: 0xc1, // USART Control and Status Register B
|
||||
UCSR0C: 0xc2, // USART Control and Status Register C
|
||||
UCSR0D: 0xc3, // USART Control and Status Register D
|
||||
UBRR0L: 0xc4, // USART Baud Rate Register Bytes
|
||||
UBRR0H: 0xc4, // USART Baud Rate Register Bytes
|
||||
}
|
||||
|
||||
// Two Wire Serial Interface
|
||||
TWI = struct {
|
||||
TWAMR __reg
|
||||
TWBR __reg
|
||||
TWCR __reg
|
||||
TWSR __reg
|
||||
TWDR __reg
|
||||
TWAR __reg
|
||||
}{
|
||||
TWAMR: 0xbd, // TWI (Slave) Address Mask Register
|
||||
TWBR: 0xb8, // TWI Bit Rate register
|
||||
TWCR: 0xbc, // TWI Control Register
|
||||
TWSR: 0xb9, // TWI Status Register
|
||||
TWDR: 0xbb, // TWI Data register
|
||||
TWAR: 0xba, // TWI (Slave) Address register
|
||||
}
|
||||
|
||||
// Timer/Counter, 16-bit
|
||||
TC16 = struct {
|
||||
TIMSK1 __reg
|
||||
TIFR1 __reg
|
||||
TCCR1A __reg
|
||||
TCCR1B __reg
|
||||
TCCR1C __reg
|
||||
TCNT1L __reg
|
||||
TCNT1H __reg
|
||||
OCR1AL __reg
|
||||
OCR1AH __reg
|
||||
OCR1BL __reg
|
||||
OCR1BH __reg
|
||||
ICR1L __reg
|
||||
ICR1H __reg
|
||||
}{
|
||||
TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register
|
||||
TIFR1: 0x36, // Timer/Counter Interrupt Flag register
|
||||
TCCR1A: 0x80, // Timer/Counter1 Control Register A
|
||||
TCCR1B: 0x81, // Timer/Counter1 Control Register B
|
||||
TCCR1C: 0x82, // Timer/Counter1 Control Register C
|
||||
TCNT1L: 0x84, // Timer/Counter1 Bytes
|
||||
TCNT1H: 0x84, // Timer/Counter1 Bytes
|
||||
OCR1AL: 0x88, // Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1AH: 0x88, // Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register Bytes
|
||||
ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit Async
|
||||
TC8_ASYNC = struct {
|
||||
TIMSK2 __reg
|
||||
TIFR2 __reg
|
||||
TCCR2A __reg
|
||||
TCCR2B __reg
|
||||
TCNT2 __reg
|
||||
OCR2B __reg
|
||||
OCR2A __reg
|
||||
ASSR __reg
|
||||
}{
|
||||
TIMSK2: 0x70, // Timer/Counter Interrupt Mask register
|
||||
TIFR2: 0x37, // Timer/Counter Interrupt Flag Register
|
||||
TCCR2A: 0xb0, // Timer/Counter2 Control Register A
|
||||
TCCR2B: 0xb1, // Timer/Counter2 Control Register B
|
||||
TCNT2: 0xb2, // Timer/Counter2
|
||||
OCR2B: 0xb4, // Timer/Counter2 Output Compare Register B
|
||||
OCR2A: 0xb3, // Timer/Counter2 Output Compare Register A
|
||||
ASSR: 0xb6, // Asynchronous Status Register
|
||||
}
|
||||
|
||||
// Analog-to-Digital Converter
|
||||
ADC = struct {
|
||||
ADMUX __reg
|
||||
ADCL __reg
|
||||
ADCH __reg
|
||||
ADCSRA __reg
|
||||
ADCSRB __reg
|
||||
DIDR0 __reg
|
||||
}{
|
||||
ADMUX: 0x7c, // The ADC multiplexer Selection Register
|
||||
ADCL: 0x78, // ADC Data Register Bytes
|
||||
ADCH: 0x78, // ADC Data Register Bytes
|
||||
ADCSRA: 0x7a, // The ADC Control and Status register A
|
||||
ADCSRB: 0x7b, // The ADC Control and Status register B
|
||||
DIDR0: 0x7e, // Digital Input Disable Register
|
||||
}
|
||||
|
||||
// Analog Comparator
|
||||
AC = struct {
|
||||
ACSR __reg
|
||||
DIDR1 __reg
|
||||
ACSRB __reg
|
||||
}{
|
||||
ACSR: 0x50, // Analog Comparator Control And Status Register
|
||||
DIDR1: 0x7f, // Digital Input Disable Register 1
|
||||
ACSRB: 0x4f, // Analog Comparator Status Register B
|
||||
}
|
||||
|
||||
// I/O Port
|
||||
PORT = struct {
|
||||
PORTB __reg
|
||||
DDRB __reg
|
||||
PINB __reg
|
||||
PORTC __reg
|
||||
DDRC __reg
|
||||
PINC __reg
|
||||
PORTD __reg
|
||||
DDRD __reg
|
||||
PIND __reg
|
||||
PORTE __reg
|
||||
DDRE __reg
|
||||
PINE __reg
|
||||
}{
|
||||
PORTB: 0x25, // Port B Data Register
|
||||
DDRB: 0x24, // Port B Data Direction Register
|
||||
PINB: 0x23, // Port B Input Pins
|
||||
PORTC: 0x28, // Port C Data Register
|
||||
DDRC: 0x27, // Port C Data Direction Register
|
||||
PINC: 0x26, // Port C Input Pins
|
||||
PORTD: 0x2b, // Port D Data Register
|
||||
DDRD: 0x2a, // Port D Data Direction Register
|
||||
PIND: 0x29, // Port D Input Pins
|
||||
PORTE: 0x2e, // Port E Data Register
|
||||
DDRE: 0x2d, // Port E Data Direction Register
|
||||
PINE: 0x2c, // Port E Input Pins
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit
|
||||
TC8 = struct {
|
||||
OCR0B __reg
|
||||
OCR0A __reg
|
||||
TCNT0 __reg
|
||||
TCCR0B __reg
|
||||
TCCR0A __reg
|
||||
TIMSK0 __reg
|
||||
TIFR0 __reg
|
||||
}{
|
||||
OCR0B: 0x48, // Timer/Counter0 Output Compare Register
|
||||
OCR0A: 0x47, // Timer/Counter0 Output Compare Register
|
||||
TCNT0: 0x46, // Timer/Counter0
|
||||
TCCR0B: 0x45, // Timer/Counter Control Register B
|
||||
TCCR0A: 0x44, // Timer/Counter Control Register A
|
||||
TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register
|
||||
TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register
|
||||
}
|
||||
|
||||
// External Interrupts
|
||||
EXINT = struct {
|
||||
EICRA __reg
|
||||
EIMSK __reg
|
||||
EIFR __reg
|
||||
PCICR __reg
|
||||
PCMSK2 __reg
|
||||
PCMSK1 __reg
|
||||
PCMSK0 __reg
|
||||
PCIFR __reg
|
||||
}{
|
||||
EICRA: 0x69, // External Interrupt Control Register
|
||||
EIMSK: 0x3d, // External Interrupt Mask Register
|
||||
EIFR: 0x3c, // External Interrupt Flag Register
|
||||
PCICR: 0x68, // Pin Change Interrupt Control Register
|
||||
PCMSK2: 0x6d, // Pin Change Mask Register 2
|
||||
PCMSK1: 0x6c, // Pin Change Mask Register 1
|
||||
PCMSK0: 0x6b, // Pin Change Mask Register 0
|
||||
PCIFR: 0x3b, // Pin Change Interrupt Flag Register
|
||||
}
|
||||
|
||||
// Serial Peripheral Interface
|
||||
SPI = struct {
|
||||
SPDR __reg
|
||||
SPSR __reg
|
||||
SPCR __reg
|
||||
}{
|
||||
SPDR: 0x4e, // SPI Data Register
|
||||
SPSR: 0x4d, // SPI Status Register
|
||||
SPCR: 0x4c, // SPI Control Register
|
||||
}
|
||||
|
||||
// Watchdog Timer
|
||||
WDT = struct {
|
||||
WDTCSR __reg
|
||||
}{
|
||||
WDTCSR: 0x60, // Watchdog Timer Control Register
|
||||
}
|
||||
|
||||
// EEPROM
|
||||
EEPROM = struct {
|
||||
EEARL __reg
|
||||
EEARH __reg
|
||||
EEDR __reg
|
||||
EECR __reg
|
||||
}{
|
||||
EEARL: 0x41, // EEPROM Address Register Bytes
|
||||
EEARH: 0x41, // EEPROM Address Register Bytes
|
||||
EEDR: 0x40, // EEPROM Data Register
|
||||
EECR: 0x3f, // EEPROM Control Register
|
||||
}
|
||||
|
||||
// CPU Registers
|
||||
CPU = struct {
|
||||
PRR __reg
|
||||
OSCCAL __reg
|
||||
CLKPR __reg
|
||||
SREG __reg
|
||||
SPL __reg
|
||||
SPH __reg
|
||||
SPMCSR __reg
|
||||
MCUCR __reg
|
||||
MCUSR __reg
|
||||
SMCR __reg
|
||||
GPIOR2 __reg
|
||||
GPIOR1 __reg
|
||||
GPIOR0 __reg
|
||||
}{
|
||||
PRR: 0x64, // Power Reduction Register
|
||||
OSCCAL: 0x66, // Oscillator Calibration Value
|
||||
CLKPR: 0x61, // Clock Prescale Register
|
||||
SREG: 0x5f, // Status Register
|
||||
SPL: 0x5d, // Stack Pointer
|
||||
SPH: 0x5d, // Stack Pointer
|
||||
SPMCSR: 0x57, // Store Program Memory Control and Status Register
|
||||
MCUCR: 0x55, // MCU Control Register
|
||||
MCUSR: 0x54, // MCU Status Register
|
||||
SMCR: 0x53, // Sleep Mode Control Register
|
||||
GPIOR2: 0x4b, // General Purpose I/O Register 2
|
||||
GPIOR1: 0x4a, // General Purpose I/O Register 1
|
||||
GPIOR0: 0x3e, // General Purpose I/O Register 0
|
||||
}
|
||||
)
|
||||
|
||||
// Bitfields for FUSE: Fuses
|
||||
const (
|
||||
// EXTENDED
|
||||
EXTENDED_BOOTSZ = 0x6 // Select boot size
|
||||
EXTENDED_BOOTRST = 0x1 // Boot Reset vector Enabled
|
||||
|
||||
// HIGH
|
||||
HIGH_RSTDISBL = 0x80 // Reset Disabled (Enable PC6 as i/o pin)
|
||||
HIGH_DWEN = 0x40 // Debug Wire enable
|
||||
HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled
|
||||
HIGH_WDTON = 0x10 // Watch-dog Timer always on
|
||||
HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle
|
||||
HIGH_BODLEVEL = 0x7 // Brown-out Detector trigger level
|
||||
|
||||
// LOW
|
||||
LOW_CKDIV8 = 0x80 // Divide clock by 8 internally
|
||||
LOW_CKOUT = 0x40 // Clock output on PORTB0
|
||||
LOW_SUT_CKSEL = 0x3f // Select Clock Source
|
||||
)
|
||||
|
||||
// Bitfields for LOCKBIT: Lockbits
|
||||
const (
|
||||
// LOCKBIT
|
||||
LOCKBIT_LB = 0x3 // Memory Lock
|
||||
LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode
|
||||
LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode
|
||||
)
|
||||
|
||||
// Bitfields for USART: USART
|
||||
const (
|
||||
// UCSR0A: USART Control and Status Register A
|
||||
UCSR0A_RXC0 = 0x80 // USART Receive Complete
|
||||
UCSR0A_TXC0 = 0x40 // USART Transmitt Complete
|
||||
UCSR0A_UDRE0 = 0x20 // USART Data Register Empty
|
||||
UCSR0A_FE0 = 0x10 // Framing Error
|
||||
UCSR0A_DOR0 = 0x8 // Data overRun
|
||||
UCSR0A_UPE0 = 0x4 // Parity Error
|
||||
UCSR0A_U2X0 = 0x2 // Double the USART transmission speed
|
||||
UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode
|
||||
|
||||
// UCSR0B: USART Control and Status Register B
|
||||
UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable
|
||||
UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable
|
||||
UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable
|
||||
UCSR0B_RXEN0 = 0x10 // Receiver Enable
|
||||
UCSR0B_TXEN0 = 0x8 // Transmitter Enable
|
||||
UCSR0B_UCSZ02 = 0x4 // Character Size
|
||||
UCSR0B_RXB80 = 0x2 // Receive Data Bit 8
|
||||
UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8
|
||||
|
||||
// UCSR0C: USART Control and Status Register C
|
||||
UCSR0C_UMSEL0 = 0xc0 // USART Mode Select
|
||||
UCSR0C_UPM0 = 0x30 // Parity Mode Bits
|
||||
UCSR0C_USBS0 = 0x8 // Stop Bit Select
|
||||
UCSR0C_UCSZ0 = 0x6 // Character Size
|
||||
UCSR0C_UCPOL0 = 0x1 // Clock Polarity
|
||||
|
||||
// UCSR0D: USART Control and Status Register D
|
||||
UCSR0D_RXSIE = 0x80 // RX Start Interrupt Enable
|
||||
UCSR0D_RXS = 0x40 // RX Start
|
||||
UCSR0D_SFDE = 0x20 // Start Frame Detection Enable
|
||||
)
|
||||
|
||||
// Bitfields for TWI: Two Wire Serial Interface
|
||||
const (
|
||||
// TWAMR: TWI (Slave) Address Mask Register
|
||||
TWAMR_TWAM = 0xfe
|
||||
|
||||
// TWCR: TWI Control Register
|
||||
TWCR_TWINT = 0x80 // TWI Interrupt Flag
|
||||
TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit
|
||||
TWCR_TWSTA = 0x20 // TWI Start Condition Bit
|
||||
TWCR_TWSTO = 0x10 // TWI Stop Condition Bit
|
||||
TWCR_TWWC = 0x8 // TWI Write Collition Flag
|
||||
TWCR_TWEN = 0x4 // TWI Enable Bit
|
||||
TWCR_TWIE = 0x1 // TWI Interrupt Enable
|
||||
|
||||
// TWSR: TWI Status Register
|
||||
TWSR_TWS = 0xf8 // TWI Status
|
||||
TWSR_TWPS = 0x3 // TWI Prescaler
|
||||
|
||||
// TWAR: TWI (Slave) Address register
|
||||
TWAR_TWA = 0xfe // TWI (Slave) Address register Bits
|
||||
TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit
|
||||
)
|
||||
|
||||
// Bitfields for TC16: Timer/Counter, 16-bit
|
||||
const (
|
||||
// TIMSK1: Timer/Counter Interrupt Mask Register
|
||||
TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable
|
||||
TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output CompareB Match Interrupt Enable
|
||||
TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output CompareA Match Interrupt Enable
|
||||
TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable
|
||||
|
||||
// TIFR1: Timer/Counter Interrupt Flag register
|
||||
TIFR1_ICF1 = 0x20 // Input Capture Flag 1
|
||||
TIFR1_OCF1B = 0x4 // Output Compare Flag 1B
|
||||
TIFR1_OCF1A = 0x2 // Output Compare Flag 1A
|
||||
TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag
|
||||
|
||||
// TCCR1A: Timer/Counter1 Control Register A
|
||||
TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits
|
||||
TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits
|
||||
TCCR1A_WGM1 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TCCR1B: Timer/Counter1 Control Register B
|
||||
TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler
|
||||
TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select
|
||||
TCCR1B_WGM1 = 0x18 // Waveform Generation Mode
|
||||
TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1
|
||||
|
||||
// TCCR1C: Timer/Counter1 Control Register C
|
||||
TCCR1C_FOC1A = 0x80
|
||||
TCCR1C_FOC1B = 0x40
|
||||
)
|
||||
|
||||
// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async
|
||||
const (
|
||||
// TIMSK2: Timer/Counter Interrupt Mask register
|
||||
TIMSK2_OCIE2B = 0x4 // Timer/Counter2 Output Compare Match B Interrupt Enable
|
||||
TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match A Interrupt Enable
|
||||
TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable
|
||||
|
||||
// TIFR2: Timer/Counter Interrupt Flag Register
|
||||
TIFR2_OCF2B = 0x4 // Output Compare Flag 2B
|
||||
TIFR2_OCF2A = 0x2 // Output Compare Flag 2A
|
||||
TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag
|
||||
|
||||
// TCCR2A: Timer/Counter2 Control Register A
|
||||
TCCR2A_COM2A = 0xc0 // Compare Output Mode bits
|
||||
TCCR2A_COM2B = 0x30 // Compare Output Mode bits
|
||||
TCCR2A_WGM2 = 0x3 // Waveform Genration Mode
|
||||
|
||||
// TCCR2B: Timer/Counter2 Control Register B
|
||||
TCCR2B_FOC2A = 0x80 // Force Output Compare A
|
||||
TCCR2B_FOC2B = 0x40 // Force Output Compare B
|
||||
TCCR2B_WGM22 = 0x8 // Waveform Generation Mode
|
||||
TCCR2B_CS2 = 0x7 // Clock Select bits
|
||||
|
||||
// ASSR: Asynchronous Status Register
|
||||
ASSR_EXCLK = 0x40 // Enable External Clock Input
|
||||
ASSR_AS2 = 0x20 // Asynchronous Timer/Counter2
|
||||
ASSR_TCN2UB = 0x10 // Timer/Counter2 Update Busy
|
||||
ASSR_OCR2AUB = 0x8 // Output Compare Register2 Update Busy
|
||||
ASSR_OCR2BUB = 0x4 // Output Compare Register 2 Update Busy
|
||||
ASSR_TCR2AUB = 0x2 // Timer/Counter Control Register2 Update Busy
|
||||
ASSR_TCR2BUB = 0x1 // Timer/Counter Control Register2 Update Busy
|
||||
)
|
||||
|
||||
// Bitfields for ADC: Analog-to-Digital Converter
|
||||
const (
|
||||
// ADMUX: The ADC multiplexer Selection Register
|
||||
ADMUX_REFS = 0xc0 // Reference Selection Bits
|
||||
ADMUX_ADLAR = 0x20 // Left Adjust Result
|
||||
ADMUX_MUX = 0xf // Analog Channel Selection Bits
|
||||
|
||||
// ADCSRA: The ADC Control and Status register A
|
||||
ADCSRA_ADEN = 0x80 // ADC Enable
|
||||
ADCSRA_ADSC = 0x40 // ADC Start Conversion
|
||||
ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable
|
||||
ADCSRA_ADIF = 0x10 // ADC Interrupt Flag
|
||||
ADCSRA_ADIE = 0x8 // ADC Interrupt Enable
|
||||
ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits
|
||||
|
||||
// ADCSRB: The ADC Control and Status register B
|
||||
ADCSRB_ACME = 0x40
|
||||
ADCSRB_ADTS = 0x7 // ADC Auto Trigger Source bits
|
||||
|
||||
// DIDR0: Digital Input Disable Register
|
||||
DIDR0_ADC5D = 0x20
|
||||
DIDR0_ADC4D = 0x10
|
||||
DIDR0_ADC3D = 0x8
|
||||
DIDR0_ADC2D = 0x4
|
||||
DIDR0_ADC1D = 0x2
|
||||
DIDR0_ADC0D = 0x1
|
||||
)
|
||||
|
||||
// Bitfields for AC: Analog Comparator
|
||||
const (
|
||||
// ACSR: Analog Comparator Control And Status Register
|
||||
ACSR_ACD = 0x80 // Analog Comparator Disable
|
||||
ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select
|
||||
ACSR_ACO = 0x20 // Analog Compare Output
|
||||
ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag
|
||||
ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable
|
||||
ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable
|
||||
ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits
|
||||
|
||||
// DIDR1: Digital Input Disable Register 1
|
||||
DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable
|
||||
DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable
|
||||
|
||||
// ACSRB: Analog Comparator Status Register B
|
||||
ACSRB_ACOE = 0x1 // Analog Comparator Output Enable
|
||||
)
|
||||
|
||||
// Bitfields for TC8: Timer/Counter, 8-bit
|
||||
const (
|
||||
// TCCR0B: Timer/Counter Control Register B
|
||||
TCCR0B_FOC0A = 0x80 // Force Output Compare A
|
||||
TCCR0B_FOC0B = 0x40 // Force Output Compare B
|
||||
TCCR0B_WGM02 = 0x8
|
||||
TCCR0B_CS0 = 0x7 // Clock Select
|
||||
|
||||
// TCCR0A: Timer/Counter Control Register A
|
||||
TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode
|
||||
TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm
|
||||
TCCR0A_WGM0 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TIMSK0: Timer/Counter0 Interrupt Mask Register
|
||||
TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable
|
||||
TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable
|
||||
TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable
|
||||
|
||||
// TIFR0: Timer/Counter0 Interrupt Flag register
|
||||
TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B
|
||||
TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A
|
||||
TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag
|
||||
)
|
||||
|
||||
// Bitfields for EXINT: External Interrupts
|
||||
const (
|
||||
// EICRA: External Interrupt Control Register
|
||||
EICRA_ISC1 = 0xc // External Interrupt Sense Control 1 Bits
|
||||
EICRA_ISC0 = 0x3 // External Interrupt Sense Control 0 Bits
|
||||
|
||||
// EIMSK: External Interrupt Mask Register
|
||||
EIMSK_INT = 0x3 // External Interrupt Request 1 Enable
|
||||
|
||||
// EIFR: External Interrupt Flag Register
|
||||
EIFR_INTF = 0x3 // External Interrupt Flags
|
||||
|
||||
// PCICR: Pin Change Interrupt Control Register
|
||||
PCICR_PCIE = 0x7 // Pin Change Interrupt Enables
|
||||
|
||||
// PCMSK2: Pin Change Mask Register 2
|
||||
PCMSK2_PCINT = 0xff // Pin Change Enable Masks
|
||||
|
||||
// PCMSK1: Pin Change Mask Register 1
|
||||
PCMSK1_PCINT = 0x7f // Pin Change Enable Masks
|
||||
|
||||
// PCMSK0: Pin Change Mask Register 0
|
||||
PCMSK0_PCINT = 0xff // Pin Change Enable Masks
|
||||
|
||||
// PCIFR: Pin Change Interrupt Flag Register
|
||||
PCIFR_PCIF = 0x7 // Pin Change Interrupt Flags
|
||||
)
|
||||
|
||||
// Bitfields for SPI: Serial Peripheral Interface
|
||||
const (
|
||||
// SPSR: SPI Status Register
|
||||
SPSR_SPIF = 0x80 // SPI Interrupt Flag
|
||||
SPSR_WCOL = 0x40 // Write Collision Flag
|
||||
SPSR_SPI2X = 0x1 // Double SPI Speed Bit
|
||||
|
||||
// SPCR: SPI Control Register
|
||||
SPCR_SPIE = 0x80 // SPI Interrupt Enable
|
||||
SPCR_SPE = 0x40 // SPI Enable
|
||||
SPCR_DORD = 0x20 // Data Order
|
||||
SPCR_MSTR = 0x10 // Master/Slave Select
|
||||
SPCR_CPOL = 0x8 // Clock polarity
|
||||
SPCR_CPHA = 0x4 // Clock Phase
|
||||
SPCR_SPR = 0x3 // SPI Clock Rate Selects
|
||||
)
|
||||
|
||||
// Bitfields for WDT: Watchdog Timer
|
||||
const (
|
||||
// WDTCSR: Watchdog Timer Control Register
|
||||
WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag
|
||||
WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable
|
||||
WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits
|
||||
WDTCSR_WDCE = 0x10 // Watchdog Change Enable
|
||||
WDTCSR_WDE = 0x8 // Watch Dog Enable
|
||||
)
|
||||
|
||||
// Bitfields for EEPROM: EEPROM
|
||||
const (
|
||||
// EECR: EEPROM Control Register
|
||||
EECR_EEPM = 0x30 // EEPROM Programming Mode Bits
|
||||
EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable
|
||||
EECR_EEMPE = 0x4 // EEPROM Master Write Enable
|
||||
EECR_EEPE = 0x2 // EEPROM Write Enable
|
||||
EECR_EERE = 0x1 // EEPROM Read Enable
|
||||
)
|
||||
|
||||
// Bitfields for CPU: CPU Registers
|
||||
const (
|
||||
// PRR: Power Reduction Register
|
||||
PRR_PRTWI = 0x80 // Power Reduction TWI
|
||||
PRR_PRTIM2 = 0x40 // Power Reduction Timer/Counter2
|
||||
PRR_PRTIM0 = 0x20 // Power Reduction Timer/Counter0
|
||||
PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1
|
||||
PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface
|
||||
PRR_PRUSART0 = 0x2 // Power Reduction USART
|
||||
PRR_PRADC = 0x1 // Power Reduction ADC
|
||||
|
||||
// OSCCAL: Oscillator Calibration Value
|
||||
OSCCAL_OSCCAL = 0xff // Oscillator Calibration
|
||||
|
||||
// CLKPR: Clock Prescale Register
|
||||
CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable
|
||||
CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits
|
||||
|
||||
// SREG: Status Register
|
||||
SREG_I = 0x80 // Global Interrupt Enable
|
||||
SREG_T = 0x40 // Bit Copy Storage
|
||||
SREG_H = 0x20 // Half Carry Flag
|
||||
SREG_S = 0x10 // Sign Bit
|
||||
SREG_V = 0x8 // Two's Complement Overflow Flag
|
||||
SREG_N = 0x4 // Negative Flag
|
||||
SREG_Z = 0x2 // Zero Flag
|
||||
SREG_C = 0x1 // Carry Flag
|
||||
|
||||
// SPMCSR: Store Program Memory Control and Status Register
|
||||
SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable
|
||||
SPMCSR_RWWSB = 0x40 // Read-While-Write Section Busy
|
||||
SPMCSR_SIGRD = 0x20 // Signature Row Read
|
||||
SPMCSR_RWWSRE = 0x10 // Read-While-Write section read enable
|
||||
SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set
|
||||
SPMCSR_PGWRT = 0x4 // Page Write
|
||||
SPMCSR_PGERS = 0x2 // Page Erase
|
||||
SPMCSR_SPMEN = 0x1 // Store Program Memory
|
||||
|
||||
// MCUCR: MCU Control Register
|
||||
MCUCR_BODS = 0x40 // BOD Sleep
|
||||
MCUCR_BODSE = 0x20 // BOD Sleep Enable
|
||||
MCUCR_PUD = 0x10
|
||||
MCUCR_IVSEL = 0x2
|
||||
MCUCR_IVCE = 0x1
|
||||
|
||||
// MCUSR: MCU Status Register
|
||||
MCUSR_WDRF = 0x8 // Watchdog Reset Flag
|
||||
MCUSR_BORF = 0x4 // Brown-out Reset Flag
|
||||
MCUSR_EXTRF = 0x2 // External Reset Flag
|
||||
MCUSR_PORF = 0x1 // Power-on reset flag
|
||||
|
||||
// SMCR: Sleep Mode Control Register
|
||||
SMCR_SM = 0xe // Sleep Mode Select Bits
|
||||
SMCR_SE = 0x1 // Sleep Enable
|
||||
)
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from ATmega168PB.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x4000;
|
||||
__ram_size = 0x400;
|
||||
__num_isrs = 27;
|
||||
|
|
@ -1,679 +0,0 @@
|
|||
// Automatically generated file. DO NOT EDIT.
|
||||
// Generated by gen-device.py from ATmega169A.atdf, see http://packs.download.atmel.com/
|
||||
|
||||
// +build avr,atmega169a
|
||||
|
||||
// Device information for the ATmega169A.
|
||||
//
|
||||
package avr
|
||||
|
||||
// Magic type name for the compiler.
|
||||
type __reg uint8
|
||||
|
||||
// Export this magic type name.
|
||||
type RegValue = __reg
|
||||
|
||||
// Some information about this device.
|
||||
const (
|
||||
DEVICE = "ATmega169A"
|
||||
ARCH = "AVR8"
|
||||
FAMILY = "megaAVR"
|
||||
)
|
||||
|
||||
// Interrupts
|
||||
const (
|
||||
IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet.
|
||||
IRQ_INT0 = 1 // External Interrupt Request 0
|
||||
IRQ_PCINT0 = 2 // Pin Change Interrupt Request 0
|
||||
IRQ_PCINT1 = 3 // Pin Change Interrupt Request 1
|
||||
IRQ_TIMER2_COMP = 4 // Timer/Counter2 Compare Match
|
||||
IRQ_TIMER2_OVF = 5 // Timer/Counter2 Overflow
|
||||
IRQ_TIMER1_CAPT = 6 // Timer/Counter1 Capture Event
|
||||
IRQ_TIMER1_COMPA = 7 // Timer/Counter1 Compare Match A
|
||||
IRQ_TIMER1_COMPB = 8 // Timer/Counter Compare Match B
|
||||
IRQ_TIMER1_OVF = 9 // Timer/Counter1 Overflow
|
||||
IRQ_TIMER0_COMP = 10 // Timer/Counter0 Compare Match
|
||||
IRQ_TIMER0_OVF = 11 // Timer/Counter0 Overflow
|
||||
IRQ_SPI_STC = 12 // SPI Serial Transfer Complete
|
||||
IRQ_USART0_RX = 13 // USART0, Rx Complete
|
||||
IRQ_USART0_UDRE = 14 // USART0 Data register Empty
|
||||
IRQ_USART0_TX = 15 // USART0, Tx Complete
|
||||
IRQ_USI_START = 16 // USI Start Condition
|
||||
IRQ_USI_OVERFLOW = 17 // USI Overflow
|
||||
IRQ_ANALOG_COMP = 18 // Analog Comparator
|
||||
IRQ_ADC = 19 // ADC Conversion Complete
|
||||
IRQ_EE_READY = 20 // EEPROM Ready
|
||||
IRQ_SPM_READY = 21 // Store Program Memory Read
|
||||
IRQ_LCD = 22 // LCD Start of Frame
|
||||
IRQ_max = 22 // Highest interrupt number on this device.
|
||||
)
|
||||
|
||||
// Peripherals
|
||||
var (
|
||||
// Fuses
|
||||
FUSE = struct {
|
||||
EXTENDED __reg
|
||||
HIGH __reg
|
||||
LOW __reg
|
||||
}{
|
||||
EXTENDED: 0x2,
|
||||
HIGH: 0x1,
|
||||
LOW: 0x0,
|
||||
}
|
||||
|
||||
// Lockbits
|
||||
LOCKBIT = struct {
|
||||
LOCKBIT __reg
|
||||
}{
|
||||
LOCKBIT: 0x0,
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit
|
||||
TC8 = struct {
|
||||
TCCR0A __reg
|
||||
TCNT0 __reg
|
||||
OCR0A __reg
|
||||
TIMSK0 __reg
|
||||
TIFR0 __reg
|
||||
}{
|
||||
TCCR0A: 0x44, // Timer/Counter0 Control Register
|
||||
TCNT0: 0x46, // Timer/Counter0
|
||||
OCR0A: 0x47, // Timer/Counter0 Output Compare Register
|
||||
TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register
|
||||
TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register
|
||||
}
|
||||
|
||||
// Timer/Counter, 16-bit
|
||||
TC16 = struct {
|
||||
TCCR1A __reg
|
||||
TCCR1B __reg
|
||||
TCCR1C __reg
|
||||
TCNT1L __reg
|
||||
TCNT1H __reg
|
||||
OCR1AL __reg
|
||||
OCR1AH __reg
|
||||
OCR1BL __reg
|
||||
OCR1BH __reg
|
||||
ICR1L __reg
|
||||
ICR1H __reg
|
||||
TIMSK1 __reg
|
||||
TIFR1 __reg
|
||||
}{
|
||||
TCCR1A: 0x80, // Timer/Counter1 Control Register A
|
||||
TCCR1B: 0x81, // Timer/Counter1 Control Register B
|
||||
TCCR1C: 0x82, // Timer/Counter 1 Control Register C
|
||||
TCNT1L: 0x84, // Timer/Counter1 Bytes
|
||||
TCNT1H: 0x84, // Timer/Counter1 Bytes
|
||||
OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes
|
||||
OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes
|
||||
OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes
|
||||
OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes
|
||||
ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register
|
||||
TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit Async
|
||||
TC8_ASYNC = struct {
|
||||
TCCR2A __reg
|
||||
TCNT2 __reg
|
||||
OCR2A __reg
|
||||
TIMSK2 __reg
|
||||
TIFR2 __reg
|
||||
ASSR __reg
|
||||
}{
|
||||
TCCR2A: 0xb0, // Timer/Counter2 Control Register
|
||||
TCNT2: 0xb2, // Timer/Counter2
|
||||
OCR2A: 0xb3, // Timer/Counter2 Output Compare Register
|
||||
TIMSK2: 0x70, // Timer/Counter2 Interrupt Mask register
|
||||
TIFR2: 0x37, // Timer/Counter2 Interrupt Flag Register
|
||||
ASSR: 0xb6, // Asynchronous Status Register
|
||||
}
|
||||
|
||||
// Watchdog Timer
|
||||
WDT = struct {
|
||||
WDTCR __reg
|
||||
}{
|
||||
WDTCR: 0x60, // Watchdog Timer Control Register
|
||||
}
|
||||
|
||||
// EEPROM
|
||||
EEPROM = struct {
|
||||
EEARL __reg
|
||||
EEARH __reg
|
||||
EEDR __reg
|
||||
EECR __reg
|
||||
}{
|
||||
EEARL: 0x41, // EEPROM Address Register Bytes
|
||||
EEARH: 0x41, // EEPROM Address Register Bytes
|
||||
EEDR: 0x40, // EEPROM Data Register
|
||||
EECR: 0x3f, // EEPROM Control Register
|
||||
}
|
||||
|
||||
// Serial Peripheral Interface
|
||||
SPI = struct {
|
||||
SPCR __reg
|
||||
SPSR __reg
|
||||
SPDR __reg
|
||||
}{
|
||||
SPCR: 0x4c, // SPI Control Register
|
||||
SPSR: 0x4d, // SPI Status Register
|
||||
SPDR: 0x4e, // SPI Data Register
|
||||
}
|
||||
|
||||
// I/O Port
|
||||
PORT = struct {
|
||||
PORTA __reg
|
||||
DDRA __reg
|
||||
PINA __reg
|
||||
PORTB __reg
|
||||
DDRB __reg
|
||||
PINB __reg
|
||||
PORTC __reg
|
||||
DDRC __reg
|
||||
PINC __reg
|
||||
PORTD __reg
|
||||
DDRD __reg
|
||||
PIND __reg
|
||||
PORTE __reg
|
||||
DDRE __reg
|
||||
PINE __reg
|
||||
PORTF __reg
|
||||
DDRF __reg
|
||||
PINF __reg
|
||||
PORTG __reg
|
||||
DDRG __reg
|
||||
PING __reg
|
||||
}{
|
||||
PORTA: 0x22, // Port A Data Register
|
||||
DDRA: 0x21, // Port A Data Direction Register
|
||||
PINA: 0x20, // Port A Input Pins
|
||||
PORTB: 0x25, // Port B Data Register
|
||||
DDRB: 0x24, // Port B Data Direction Register
|
||||
PINB: 0x23, // Port B Input Pins
|
||||
PORTC: 0x28, // Port C Data Register
|
||||
DDRC: 0x27, // Port C Data Direction Register
|
||||
PINC: 0x26, // Port C Input Pins
|
||||
PORTD: 0x2b, // Port D Data Register
|
||||
DDRD: 0x2a, // Port D Data Direction Register
|
||||
PIND: 0x29, // Port D Input Pins
|
||||
PORTE: 0x2e, // Data Register, Port E
|
||||
DDRE: 0x2d, // Data Direction Register, Port E
|
||||
PINE: 0x2c, // Input Pins, Port E
|
||||
PORTF: 0x31, // Data Register, Port F
|
||||
DDRF: 0x30, // Data Direction Register, Port F
|
||||
PINF: 0x2f, // Input Pins, Port F
|
||||
PORTG: 0x34, // Port G Data Register
|
||||
DDRG: 0x33, // Port G Data Direction Register
|
||||
PING: 0x32, // Port G Input Pins
|
||||
}
|
||||
|
||||
// Analog Comparator
|
||||
AC = struct {
|
||||
ACSR __reg
|
||||
DIDR1 __reg
|
||||
}{
|
||||
ACSR: 0x50, // Analog Comparator Control And Status Register
|
||||
DIDR1: 0x7f, // Digital Input Disable Register 1
|
||||
}
|
||||
|
||||
// JTAG Interface
|
||||
JTAG = struct {
|
||||
OCDR __reg
|
||||
}{
|
||||
OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory
|
||||
}
|
||||
|
||||
// Liquid Crystal Display
|
||||
LCD = struct {
|
||||
LCDCRA __reg
|
||||
LCDCRB __reg
|
||||
LCDFRR __reg
|
||||
LCDCCR __reg
|
||||
LCDDR18 __reg
|
||||
LCDDR17 __reg
|
||||
LCDDR16 __reg
|
||||
LCDDR15 __reg
|
||||
LCDDR13 __reg
|
||||
LCDDR12 __reg
|
||||
LCDDR11 __reg
|
||||
LCDDR10 __reg
|
||||
LCDDR8 __reg
|
||||
LCDDR7 __reg
|
||||
LCDDR6 __reg
|
||||
LCDDR5 __reg
|
||||
LCDDR3 __reg
|
||||
LCDDR2 __reg
|
||||
LCDDR1 __reg
|
||||
LCDDR0 __reg
|
||||
}{
|
||||
LCDCRA: 0xe4, // LCD Control Register A
|
||||
LCDCRB: 0xe5, // LCD Control and Status Register B
|
||||
LCDFRR: 0xe6, // LCD Frame Rate Register
|
||||
LCDCCR: 0xe7, // LCD Contrast Control Register
|
||||
LCDDR18: 0xfe, // LCD Data Register 18
|
||||
LCDDR17: 0xfd, // LCD Data Register 17
|
||||
LCDDR16: 0xfc, // LCD Data Register 16
|
||||
LCDDR15: 0xfb, // LCD Data Register 15
|
||||
LCDDR13: 0xf9, // LCD Data Register 13
|
||||
LCDDR12: 0xf8, // LCD Data Register 12
|
||||
LCDDR11: 0xf7, // LCD Data Register 11
|
||||
LCDDR10: 0xf6, // LCD Data Register 10
|
||||
LCDDR8: 0xf4, // LCD Data Register 8
|
||||
LCDDR7: 0xf3, // LCD Data Register 7
|
||||
LCDDR6: 0xf2, // LCD Data Register 6
|
||||
LCDDR5: 0xf1, // LCD Data Register 5
|
||||
LCDDR3: 0xef, // LCD Data Register 3
|
||||
LCDDR2: 0xee, // LCD Data Register 2
|
||||
LCDDR1: 0xed, // LCD Data Register 1
|
||||
LCDDR0: 0xec, // LCD Data Register 0
|
||||
}
|
||||
|
||||
// Universal Serial Interface
|
||||
USI = struct {
|
||||
USIDR __reg
|
||||
USISR __reg
|
||||
USICR __reg
|
||||
}{
|
||||
USIDR: 0xba, // USI Data Register
|
||||
USISR: 0xb9, // USI Status Register
|
||||
USICR: 0xb8, // USI Control Register
|
||||
}
|
||||
|
||||
// Analog-to-Digital Converter
|
||||
ADC = struct {
|
||||
ADMUX __reg
|
||||
ADCSRA __reg
|
||||
ADCL __reg
|
||||
ADCH __reg
|
||||
DIDR0 __reg
|
||||
}{
|
||||
ADMUX: 0x7c, // The ADC multiplexer Selection Register
|
||||
ADCSRA: 0x7a, // The ADC Control and Status register
|
||||
ADCL: 0x78, // ADC Data Register Bytes
|
||||
ADCH: 0x78, // ADC Data Register Bytes
|
||||
DIDR0: 0x7e, // Digital Input Disable Register 0
|
||||
}
|
||||
|
||||
// Bootloader
|
||||
BOOT_LOAD = struct {
|
||||
SPMCSR __reg
|
||||
}{
|
||||
SPMCSR: 0x57, // Store Program Memory Control Register
|
||||
}
|
||||
|
||||
// USART
|
||||
USART = struct {
|
||||
UDR0 __reg
|
||||
UCSR0A __reg
|
||||
UCSR0B __reg
|
||||
UCSR0C __reg
|
||||
UBRR0L __reg
|
||||
UBRR0H __reg
|
||||
}{
|
||||
UDR0: 0xc6, // USART I/O Data Register
|
||||
UCSR0A: 0xc0, // USART Control and Status Register A
|
||||
UCSR0B: 0xc1, // USART Control and Status Register B
|
||||
UCSR0C: 0xc2, // USART Control and Status Register C
|
||||
UBRR0L: 0xc4, // USART Baud Rate Register Bytes
|
||||
UBRR0H: 0xc4, // USART Baud Rate Register Bytes
|
||||
}
|
||||
|
||||
// External Interrupts
|
||||
EXINT = struct {
|
||||
EICRA __reg
|
||||
EIMSK __reg
|
||||
EIFR __reg
|
||||
PCMSK1 __reg
|
||||
PCMSK0 __reg
|
||||
}{
|
||||
EICRA: 0x69, // External Interrupt Control Register
|
||||
EIMSK: 0x3d, // External Interrupt Mask Register
|
||||
EIFR: 0x3c, // External Interrupt Flag Register
|
||||
PCMSK1: 0x6c, // Pin Change Mask Register 1
|
||||
PCMSK0: 0x6b, // Pin Change Mask Register 0
|
||||
}
|
||||
|
||||
// CPU Registers
|
||||
CPU = struct {
|
||||
SREG __reg
|
||||
SPL __reg
|
||||
SPH __reg
|
||||
OSCCAL __reg
|
||||
CLKPR __reg
|
||||
PRR __reg
|
||||
SMCR __reg
|
||||
GPIOR2 __reg
|
||||
GPIOR1 __reg
|
||||
GPIOR0 __reg
|
||||
}{
|
||||
SREG: 0x5f, // Status Register
|
||||
SPL: 0x5d, // Stack Pointer
|
||||
SPH: 0x5d, // Stack Pointer
|
||||
OSCCAL: 0x66, // Oscillator Calibration Value
|
||||
CLKPR: 0x61, // Clock Prescale Register
|
||||
PRR: 0x64, // Power Reduction Register
|
||||
SMCR: 0x53, // Sleep Mode Control Register
|
||||
GPIOR2: 0x4b, // General Purpose IO Register 2
|
||||
GPIOR1: 0x4a, // General Purpose IO Register 1
|
||||
GPIOR0: 0x3e, // General Purpose IO Register 0
|
||||
}
|
||||
)
|
||||
|
||||
// Bitfields for FUSE: Fuses
|
||||
const (
|
||||
// EXTENDED
|
||||
EXTENDED_BODLEVEL = 0xe // Brown-out Detector trigger level
|
||||
EXTENDED_RSTDISBL = 0x1 // Disable external reset
|
||||
|
||||
// HIGH
|
||||
HIGH_OCDEN = 0x80 // On-Chip Debug Enabled
|
||||
HIGH_JTAGEN = 0x40 // JTAG Interface Enabled
|
||||
HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled
|
||||
HIGH_WDTON = 0x10 // Watchdog timer always on
|
||||
HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle
|
||||
HIGH_BOOTSZ = 0x6 // Select Boot Size
|
||||
HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled
|
||||
|
||||
// LOW
|
||||
LOW_CKDIV8 = 0x80 // Divide clock by 8 internally
|
||||
LOW_CKOUT = 0x40 // Clock output on PORTE7
|
||||
LOW_SUT_CKSEL = 0x3f // Select Clock Source
|
||||
)
|
||||
|
||||
// Bitfields for LOCKBIT: Lockbits
|
||||
const (
|
||||
// LOCKBIT
|
||||
LOCKBIT_LB = 0x3 // Memory Lock
|
||||
LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode
|
||||
LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode
|
||||
)
|
||||
|
||||
// Bitfields for TC8: Timer/Counter, 8-bit
|
||||
const (
|
||||
// TCCR0A: Timer/Counter0 Control Register
|
||||
TCCR0A_FOC0A = 0x80 // Force Output Compare
|
||||
TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0
|
||||
TCCR0A_COM0A = 0x30 // Compare Match Output Modes
|
||||
TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1
|
||||
TCCR0A_CS0 = 0x7 // Clock Selects
|
||||
|
||||
// TIMSK0: Timer/Counter0 Interrupt Mask Register
|
||||
TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable
|
||||
TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable
|
||||
|
||||
// TIFR0: Timer/Counter0 Interrupt Flag register
|
||||
TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0
|
||||
TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag
|
||||
)
|
||||
|
||||
// Bitfields for TC16: Timer/Counter, 16-bit
|
||||
const (
|
||||
// TCCR1A: Timer/Counter1 Control Register A
|
||||
TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits
|
||||
TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits
|
||||
TCCR1A_WGM1 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TCCR1B: Timer/Counter1 Control Register B
|
||||
TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler
|
||||
TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select
|
||||
TCCR1B_WGM1 = 0x18 // Waveform Generation Mode
|
||||
TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1
|
||||
|
||||
// TCCR1C: Timer/Counter 1 Control Register C
|
||||
TCCR1C_FOC1A = 0x80 // Force Output Compare 1A
|
||||
TCCR1C_FOC1B = 0x40 // Force Output Compare 1B
|
||||
|
||||
// TIMSK1: Timer/Counter1 Interrupt Mask Register
|
||||
TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable
|
||||
TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable
|
||||
TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable
|
||||
TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable
|
||||
|
||||
// TIFR1: Timer/Counter1 Interrupt Flag register
|
||||
TIFR1_ICF1 = 0x20 // Input Capture Flag 1
|
||||
TIFR1_OCF1B = 0x4 // Output Compare Flag 1B
|
||||
TIFR1_OCF1A = 0x2 // Output Compare Flag 1A
|
||||
TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag
|
||||
)
|
||||
|
||||
// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async
|
||||
const (
|
||||
// TCCR2A: Timer/Counter2 Control Register
|
||||
TCCR2A_FOC2A = 0x80 // Force Output Compare A
|
||||
TCCR2A_WGM20 = 0x40 // Waveform Generation Mode
|
||||
TCCR2A_COM2A = 0x30 // Compare Output Mode bits
|
||||
TCCR2A_WGM21 = 0x8 // Waveform Generation Mode
|
||||
TCCR2A_CS2 = 0x7 // Clock Select bits
|
||||
|
||||
// TIMSK2: Timer/Counter2 Interrupt Mask register
|
||||
TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable
|
||||
TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable
|
||||
|
||||
// TIFR2: Timer/Counter2 Interrupt Flag Register
|
||||
TIFR2_OCF2A = 0x2 // Timer/Counter2 Output Compare Flag 2
|
||||
TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag
|
||||
|
||||
// ASSR: Asynchronous Status Register
|
||||
ASSR_EXCLK = 0x10 // Enable External Clock Interrupt
|
||||
ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2
|
||||
ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy
|
||||
ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy
|
||||
ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy
|
||||
)
|
||||
|
||||
// Bitfields for WDT: Watchdog Timer
|
||||
const (
|
||||
// WDTCR: Watchdog Timer Control Register
|
||||
WDTCR_WDCE = 0x10 // Watchdog Change Enable
|
||||
WDTCR_WDE = 0x8 // Watch Dog Enable
|
||||
WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits
|
||||
)
|
||||
|
||||
// Bitfields for EEPROM: EEPROM
|
||||
const (
|
||||
// EECR: EEPROM Control Register
|
||||
EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable
|
||||
EECR_EEMWE = 0x4 // EEPROM Master Write Enable
|
||||
EECR_EEWE = 0x2 // EEPROM Write Enable
|
||||
EECR_EERE = 0x1 // EEPROM Read Enable
|
||||
)
|
||||
|
||||
// Bitfields for SPI: Serial Peripheral Interface
|
||||
const (
|
||||
// SPCR: SPI Control Register
|
||||
SPCR_SPIE = 0x80 // SPI Interrupt Enable
|
||||
SPCR_SPE = 0x40 // SPI Enable
|
||||
SPCR_DORD = 0x20 // Data Order
|
||||
SPCR_MSTR = 0x10 // Master/Slave Select
|
||||
SPCR_CPOL = 0x8 // Clock polarity
|
||||
SPCR_CPHA = 0x4 // Clock Phase
|
||||
SPCR_SPR = 0x3 // SPI Clock Rate Selects
|
||||
|
||||
// SPSR: SPI Status Register
|
||||
SPSR_SPIF = 0x80 // SPI Interrupt Flag
|
||||
SPSR_WCOL = 0x40 // Write Collision Flag
|
||||
SPSR_SPI2X = 0x1 // Double SPI Speed Bit
|
||||
)
|
||||
|
||||
// Bitfields for AC: Analog Comparator
|
||||
const (
|
||||
// ACSR: Analog Comparator Control And Status Register
|
||||
ACSR_ACD = 0x80 // Analog Comparator Disable
|
||||
ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select
|
||||
ACSR_ACO = 0x20 // Analog Compare Output
|
||||
ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag
|
||||
ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable
|
||||
ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable
|
||||
ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits
|
||||
|
||||
// DIDR1: Digital Input Disable Register 1
|
||||
DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable
|
||||
DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable
|
||||
)
|
||||
|
||||
// Bitfields for LCD: Liquid Crystal Display
|
||||
const (
|
||||
// LCDCRA: LCD Control Register A
|
||||
LCDCRA_LCDEN = 0x80 // LCD Enable
|
||||
LCDCRA_LCDAB = 0x40 // LCD A or B waveform
|
||||
LCDCRA_LCDIF = 0x10 // LCD Interrupt Flag
|
||||
LCDCRA_LCDIE = 0x8 // LCD Interrupt Enable
|
||||
LCDCRA_LCDBD = 0x4 // LCD Buffer Disable
|
||||
LCDCRA_LCDCCD = 0x2 // LCD Contrast Control Disable
|
||||
LCDCRA_LCDBL = 0x1 // LCD Blanking
|
||||
|
||||
// LCDCRB: LCD Control and Status Register B
|
||||
LCDCRB_LCDCS = 0x80 // LCD CLock Select
|
||||
LCDCRB_LCD2B = 0x40 // LCD 1/2 Bias Select
|
||||
LCDCRB_LCDMUX = 0x30 // LCD Mux Selects
|
||||
LCDCRB_LCDPM = 0x7 // LCD Port Masks
|
||||
|
||||
// LCDFRR: LCD Frame Rate Register
|
||||
LCDFRR_LCDPS = 0x70 // LCD Prescaler Selects
|
||||
LCDFRR_LCDCD = 0x7 // LCD Clock Dividers
|
||||
|
||||
// LCDCCR: LCD Contrast Control Register
|
||||
LCDCCR_LCDDC = 0xe0 // LCD Display Configuration Bits
|
||||
LCDCCR_LCDMDT = 0x10 // LCD Maximum Drive Time
|
||||
LCDCCR_LCDCC = 0xf // LCD Contrast Controls
|
||||
)
|
||||
|
||||
// Bitfields for USI: Universal Serial Interface
|
||||
const (
|
||||
// USISR: USI Status Register
|
||||
USISR_USISIF = 0x80 // Start Condition Interrupt Flag
|
||||
USISR_USIOIF = 0x40 // Counter Overflow Interrupt Flag
|
||||
USISR_USIPF = 0x20 // Stop Condition Flag
|
||||
USISR_USIDC = 0x10 // Data Output Collision
|
||||
USISR_USICNT = 0xf // USI Counter Value Bits
|
||||
|
||||
// USICR: USI Control Register
|
||||
USICR_USISIE = 0x80 // Start Condition Interrupt Enable
|
||||
USICR_USIOIE = 0x40 // Counter Overflow Interrupt Enable
|
||||
USICR_USIWM = 0x30 // USI Wire Mode Bits
|
||||
USICR_USICS = 0xc // USI Clock Source Select Bits
|
||||
USICR_USICLK = 0x2 // Clock Strobe
|
||||
USICR_USITC = 0x1 // Toggle Clock Port Pin
|
||||
)
|
||||
|
||||
// Bitfields for ADC: Analog-to-Digital Converter
|
||||
const (
|
||||
// ADMUX: The ADC multiplexer Selection Register
|
||||
ADMUX_REFS = 0xc0 // Reference Selection Bits
|
||||
ADMUX_ADLAR = 0x20 // Left Adjust Result
|
||||
ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits
|
||||
|
||||
// ADCSRA: The ADC Control and Status register
|
||||
ADCSRA_ADEN = 0x80 // ADC Enable
|
||||
ADCSRA_ADSC = 0x40 // ADC Start Conversion
|
||||
ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable
|
||||
ADCSRA_ADIF = 0x10 // ADC Interrupt Flag
|
||||
ADCSRA_ADIE = 0x8 // ADC Interrupt Enable
|
||||
ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits
|
||||
|
||||
// DIDR0: Digital Input Disable Register 0
|
||||
DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable
|
||||
DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable
|
||||
DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable
|
||||
DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable
|
||||
DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable
|
||||
DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable
|
||||
DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable
|
||||
DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable
|
||||
)
|
||||
|
||||
// Bitfields for BOOT_LOAD: Bootloader
|
||||
const (
|
||||
// SPMCSR: Store Program Memory Control Register
|
||||
SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable
|
||||
SPMCSR_RWWSB = 0x40 // Read While Write Section Busy
|
||||
SPMCSR_RWWSRE = 0x10 // Read While Write section read enable
|
||||
SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set
|
||||
SPMCSR_PGWRT = 0x4 // Page Write
|
||||
SPMCSR_PGERS = 0x2 // Page Erase
|
||||
SPMCSR_SPMEN = 0x1 // Store Program Memory Enable
|
||||
)
|
||||
|
||||
// Bitfields for USART: USART
|
||||
const (
|
||||
// UCSR0A: USART Control and Status Register A
|
||||
UCSR0A_RXC0 = 0x80 // USART Receive Complete
|
||||
UCSR0A_TXC0 = 0x40 // USART Transmit Complete
|
||||
UCSR0A_UDRE0 = 0x20 // USART Data Register Empty
|
||||
UCSR0A_FE0 = 0x10 // Framing Error
|
||||
UCSR0A_DOR0 = 0x8 // Data OverRun
|
||||
UCSR0A_UPE0 = 0x4 // USART Parity Error
|
||||
UCSR0A_U2X0 = 0x2 // Double the USART Transmission Speed
|
||||
UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode
|
||||
|
||||
// UCSR0B: USART Control and Status Register B
|
||||
UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable
|
||||
UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable
|
||||
UCSR0B_UDRIE0 = 0x20 // USART Data Register Empty Interrupt Enable
|
||||
UCSR0B_RXEN0 = 0x10 // Receiver Enable
|
||||
UCSR0B_TXEN0 = 0x8 // Transmitter Enable
|
||||
UCSR0B_UCSZ02 = 0x4 // Character Size
|
||||
UCSR0B_RXB80 = 0x2 // Receive Data Bit 8
|
||||
UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8
|
||||
|
||||
// UCSR0C: USART Control and Status Register C
|
||||
UCSR0C_UMSEL0 = 0x40 // USART Mode Select
|
||||
UCSR0C_UPM0 = 0x30 // Parity Mode Bits
|
||||
UCSR0C_USBS0 = 0x8 // Stop Bit Select
|
||||
UCSR0C_UCSZ0 = 0x6 // Character Size
|
||||
UCSR0C_UCPOL0 = 0x1 // Clock Polarity
|
||||
)
|
||||
|
||||
// Bitfields for EXINT: External Interrupts
|
||||
const (
|
||||
// EICRA: External Interrupt Control Register
|
||||
EICRA_ISC01 = 0x2 // External Interrupt Sense Control 0 Bit 1
|
||||
EICRA_ISC00 = 0x1 // External Interrupt Sense Control 0 Bit 0
|
||||
|
||||
// EIMSK: External Interrupt Mask Register
|
||||
EIMSK_PCIE = 0x30 // Pin Change Interrupt Enables
|
||||
EIMSK_INT0 = 0x1 // External Interrupt Request 0 Enable
|
||||
|
||||
// EIFR: External Interrupt Flag Register
|
||||
EIFR_PCIF = 0x30 // Pin Change Interrupt Flags
|
||||
EIFR_INTF0 = 0x1 // External Interrupt Flag 0
|
||||
|
||||
// PCMSK1: Pin Change Mask Register 1
|
||||
PCMSK1_PCINT = 0xff // Pin Change Enable Masks
|
||||
|
||||
// PCMSK0: Pin Change Mask Register 0
|
||||
PCMSK0_PCINT = 0xff // Pin Change Enable Masks
|
||||
)
|
||||
|
||||
// Bitfields for CPU: CPU Registers
|
||||
const (
|
||||
// SREG: Status Register
|
||||
SREG_I = 0x80 // Global Interrupt Enable
|
||||
SREG_T = 0x40 // Bit Copy Storage
|
||||
SREG_H = 0x20 // Half Carry Flag
|
||||
SREG_S = 0x10 // Sign Bit
|
||||
SREG_V = 0x8 // Two's Complement Overflow Flag
|
||||
SREG_N = 0x4 // Negative Flag
|
||||
SREG_Z = 0x2 // Zero Flag
|
||||
SREG_C = 0x1 // Carry Flag
|
||||
|
||||
// OSCCAL: Oscillator Calibration Value
|
||||
OSCCAL_OSCCAL = 0xff // Oscillator Calibration
|
||||
|
||||
// CLKPR: Clock Prescale Register
|
||||
CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable
|
||||
CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits
|
||||
|
||||
// PRR: Power Reduction Register
|
||||
PRR_PRLCD = 0x10 // Power Reduction LCD
|
||||
PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1
|
||||
PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface
|
||||
PRR_PRUSART0 = 0x2 // Power Reduction USART
|
||||
PRR_PRADC = 0x1 // Power Reduction ADC
|
||||
|
||||
// SMCR: Sleep Mode Control Register
|
||||
SMCR_SM = 0xe // Sleep Mode Select bits
|
||||
SMCR_SE = 0x1 // Sleep Enable
|
||||
)
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from ATmega169A.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x4000;
|
||||
__ram_size = 0x400;
|
||||
__num_isrs = 23;
|
||||
|
|
@ -1,679 +0,0 @@
|
|||
// Automatically generated file. DO NOT EDIT.
|
||||
// Generated by gen-device.py from ATmega169P.atdf, see http://packs.download.atmel.com/
|
||||
|
||||
// +build avr,atmega169p
|
||||
|
||||
// Device information for the ATmega169P.
|
||||
//
|
||||
package avr
|
||||
|
||||
// Magic type name for the compiler.
|
||||
type __reg uint8
|
||||
|
||||
// Export this magic type name.
|
||||
type RegValue = __reg
|
||||
|
||||
// Some information about this device.
|
||||
const (
|
||||
DEVICE = "ATmega169P"
|
||||
ARCH = "AVR8"
|
||||
FAMILY = "megaAVR"
|
||||
)
|
||||
|
||||
// Interrupts
|
||||
const (
|
||||
IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet.
|
||||
IRQ_INT0 = 1 // External Interrupt Request 0
|
||||
IRQ_PCINT0 = 2 // Pin Change Interrupt Request 0
|
||||
IRQ_PCINT1 = 3 // Pin Change Interrupt Request 1
|
||||
IRQ_TIMER2_COMP = 4 // Timer/Counter2 Compare Match
|
||||
IRQ_TIMER2_OVF = 5 // Timer/Counter2 Overflow
|
||||
IRQ_TIMER1_CAPT = 6 // Timer/Counter1 Capture Event
|
||||
IRQ_TIMER1_COMPA = 7 // Timer/Counter1 Compare Match A
|
||||
IRQ_TIMER1_COMPB = 8 // Timer/Counter Compare Match B
|
||||
IRQ_TIMER1_OVF = 9 // Timer/Counter1 Overflow
|
||||
IRQ_TIMER0_COMP = 10 // Timer/Counter0 Compare Match
|
||||
IRQ_TIMER0_OVF = 11 // Timer/Counter0 Overflow
|
||||
IRQ_SPI_STC = 12 // SPI Serial Transfer Complete
|
||||
IRQ_USART0_RX = 13 // USART0, Rx Complete
|
||||
IRQ_USART0_UDRE = 14 // USART0 Data register Empty
|
||||
IRQ_USART0_TX = 15 // USART0, Tx Complete
|
||||
IRQ_USI_START = 16 // USI Start Condition
|
||||
IRQ_USI_OVERFLOW = 17 // USI Overflow
|
||||
IRQ_ANALOG_COMP = 18 // Analog Comparator
|
||||
IRQ_ADC = 19 // ADC Conversion Complete
|
||||
IRQ_EE_READY = 20 // EEPROM Ready
|
||||
IRQ_SPM_READY = 21 // Store Program Memory Read
|
||||
IRQ_LCD = 22 // LCD Start of Frame
|
||||
IRQ_max = 22 // Highest interrupt number on this device.
|
||||
)
|
||||
|
||||
// Peripherals
|
||||
var (
|
||||
// Fuses
|
||||
FUSE = struct {
|
||||
EXTENDED __reg
|
||||
HIGH __reg
|
||||
LOW __reg
|
||||
}{
|
||||
EXTENDED: 0x2,
|
||||
HIGH: 0x1,
|
||||
LOW: 0x0,
|
||||
}
|
||||
|
||||
// Lockbits
|
||||
LOCKBIT = struct {
|
||||
LOCKBIT __reg
|
||||
}{
|
||||
LOCKBIT: 0x0,
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit
|
||||
TC8 = struct {
|
||||
TCCR0A __reg
|
||||
TCNT0 __reg
|
||||
OCR0A __reg
|
||||
TIMSK0 __reg
|
||||
TIFR0 __reg
|
||||
}{
|
||||
TCCR0A: 0x44, // Timer/Counter0 Control Register
|
||||
TCNT0: 0x46, // Timer/Counter0
|
||||
OCR0A: 0x47, // Timer/Counter0 Output Compare Register
|
||||
TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register
|
||||
TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register
|
||||
}
|
||||
|
||||
// Timer/Counter, 16-bit
|
||||
TC16 = struct {
|
||||
TCCR1A __reg
|
||||
TCCR1B __reg
|
||||
TCCR1C __reg
|
||||
TCNT1L __reg
|
||||
TCNT1H __reg
|
||||
OCR1AL __reg
|
||||
OCR1AH __reg
|
||||
OCR1BL __reg
|
||||
OCR1BH __reg
|
||||
ICR1L __reg
|
||||
ICR1H __reg
|
||||
TIMSK1 __reg
|
||||
TIFR1 __reg
|
||||
}{
|
||||
TCCR1A: 0x80, // Timer/Counter1 Control Register A
|
||||
TCCR1B: 0x81, // Timer/Counter1 Control Register B
|
||||
TCCR1C: 0x82, // Timer/Counter 1 Control Register C
|
||||
TCNT1L: 0x84, // Timer/Counter1 Bytes
|
||||
TCNT1H: 0x84, // Timer/Counter1 Bytes
|
||||
OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes
|
||||
OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes
|
||||
OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes
|
||||
OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes
|
||||
ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register
|
||||
TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit Async
|
||||
TC8_ASYNC = struct {
|
||||
TCCR2A __reg
|
||||
TCNT2 __reg
|
||||
OCR2A __reg
|
||||
TIMSK2 __reg
|
||||
TIFR2 __reg
|
||||
ASSR __reg
|
||||
}{
|
||||
TCCR2A: 0xb0, // Timer/Counter2 Control Register
|
||||
TCNT2: 0xb2, // Timer/Counter2
|
||||
OCR2A: 0xb3, // Timer/Counter2 Output Compare Register
|
||||
TIMSK2: 0x70, // Timer/Counter2 Interrupt Mask register
|
||||
TIFR2: 0x37, // Timer/Counter2 Interrupt Flag Register
|
||||
ASSR: 0xb6, // Asynchronous Status Register
|
||||
}
|
||||
|
||||
// Watchdog Timer
|
||||
WDT = struct {
|
||||
WDTCR __reg
|
||||
}{
|
||||
WDTCR: 0x60, // Watchdog Timer Control Register
|
||||
}
|
||||
|
||||
// EEPROM
|
||||
EEPROM = struct {
|
||||
EEARL __reg
|
||||
EEARH __reg
|
||||
EEDR __reg
|
||||
EECR __reg
|
||||
}{
|
||||
EEARL: 0x41, // EEPROM Address Register Bytes
|
||||
EEARH: 0x41, // EEPROM Address Register Bytes
|
||||
EEDR: 0x40, // EEPROM Data Register
|
||||
EECR: 0x3f, // EEPROM Control Register
|
||||
}
|
||||
|
||||
// Serial Peripheral Interface
|
||||
SPI = struct {
|
||||
SPCR __reg
|
||||
SPSR __reg
|
||||
SPDR __reg
|
||||
}{
|
||||
SPCR: 0x4c, // SPI Control Register
|
||||
SPSR: 0x4d, // SPI Status Register
|
||||
SPDR: 0x4e, // SPI Data Register
|
||||
}
|
||||
|
||||
// I/O Port
|
||||
PORT = struct {
|
||||
PORTA __reg
|
||||
DDRA __reg
|
||||
PINA __reg
|
||||
PORTB __reg
|
||||
DDRB __reg
|
||||
PINB __reg
|
||||
PORTC __reg
|
||||
DDRC __reg
|
||||
PINC __reg
|
||||
PORTD __reg
|
||||
DDRD __reg
|
||||
PIND __reg
|
||||
PORTE __reg
|
||||
DDRE __reg
|
||||
PINE __reg
|
||||
PORTF __reg
|
||||
DDRF __reg
|
||||
PINF __reg
|
||||
PORTG __reg
|
||||
DDRG __reg
|
||||
PING __reg
|
||||
}{
|
||||
PORTA: 0x22, // Port A Data Register
|
||||
DDRA: 0x21, // Port A Data Direction Register
|
||||
PINA: 0x20, // Port A Input Pins
|
||||
PORTB: 0x25, // Port B Data Register
|
||||
DDRB: 0x24, // Port B Data Direction Register
|
||||
PINB: 0x23, // Port B Input Pins
|
||||
PORTC: 0x28, // Port C Data Register
|
||||
DDRC: 0x27, // Port C Data Direction Register
|
||||
PINC: 0x26, // Port C Input Pins
|
||||
PORTD: 0x2b, // Port D Data Register
|
||||
DDRD: 0x2a, // Port D Data Direction Register
|
||||
PIND: 0x29, // Port D Input Pins
|
||||
PORTE: 0x2e, // Data Register, Port E
|
||||
DDRE: 0x2d, // Data Direction Register, Port E
|
||||
PINE: 0x2c, // Input Pins, Port E
|
||||
PORTF: 0x31, // Data Register, Port F
|
||||
DDRF: 0x30, // Data Direction Register, Port F
|
||||
PINF: 0x2f, // Input Pins, Port F
|
||||
PORTG: 0x34, // Port G Data Register
|
||||
DDRG: 0x33, // Port G Data Direction Register
|
||||
PING: 0x32, // Port G Input Pins
|
||||
}
|
||||
|
||||
// Analog Comparator
|
||||
AC = struct {
|
||||
ACSR __reg
|
||||
DIDR1 __reg
|
||||
}{
|
||||
ACSR: 0x50, // Analog Comparator Control And Status Register
|
||||
DIDR1: 0x7f, // Digital Input Disable Register 1
|
||||
}
|
||||
|
||||
// JTAG Interface
|
||||
JTAG = struct {
|
||||
OCDR __reg
|
||||
}{
|
||||
OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory
|
||||
}
|
||||
|
||||
// Liquid Crystal Display
|
||||
LCD = struct {
|
||||
LCDCRA __reg
|
||||
LCDCRB __reg
|
||||
LCDFRR __reg
|
||||
LCDCCR __reg
|
||||
LCDDR18 __reg
|
||||
LCDDR17 __reg
|
||||
LCDDR16 __reg
|
||||
LCDDR15 __reg
|
||||
LCDDR13 __reg
|
||||
LCDDR12 __reg
|
||||
LCDDR11 __reg
|
||||
LCDDR10 __reg
|
||||
LCDDR8 __reg
|
||||
LCDDR7 __reg
|
||||
LCDDR6 __reg
|
||||
LCDDR5 __reg
|
||||
LCDDR3 __reg
|
||||
LCDDR2 __reg
|
||||
LCDDR1 __reg
|
||||
LCDDR0 __reg
|
||||
}{
|
||||
LCDCRA: 0xe4, // LCD Control Register A
|
||||
LCDCRB: 0xe5, // LCD Control and Status Register B
|
||||
LCDFRR: 0xe6, // LCD Frame Rate Register
|
||||
LCDCCR: 0xe7, // LCD Contrast Control Register
|
||||
LCDDR18: 0xfe, // LCD Data Register 18
|
||||
LCDDR17: 0xfd, // LCD Data Register 17
|
||||
LCDDR16: 0xfc, // LCD Data Register 16
|
||||
LCDDR15: 0xfb, // LCD Data Register 15
|
||||
LCDDR13: 0xf9, // LCD Data Register 13
|
||||
LCDDR12: 0xf8, // LCD Data Register 12
|
||||
LCDDR11: 0xf7, // LCD Data Register 11
|
||||
LCDDR10: 0xf6, // LCD Data Register 10
|
||||
LCDDR8: 0xf4, // LCD Data Register 8
|
||||
LCDDR7: 0xf3, // LCD Data Register 7
|
||||
LCDDR6: 0xf2, // LCD Data Register 6
|
||||
LCDDR5: 0xf1, // LCD Data Register 5
|
||||
LCDDR3: 0xef, // LCD Data Register 3
|
||||
LCDDR2: 0xee, // LCD Data Register 2
|
||||
LCDDR1: 0xed, // LCD Data Register 1
|
||||
LCDDR0: 0xec, // LCD Data Register 0
|
||||
}
|
||||
|
||||
// External Interrupts
|
||||
EXINT = struct {
|
||||
EICRA __reg
|
||||
EIMSK __reg
|
||||
EIFR __reg
|
||||
PCMSK1 __reg
|
||||
PCMSK0 __reg
|
||||
}{
|
||||
EICRA: 0x69, // External Interrupt Control Register
|
||||
EIMSK: 0x3d, // External Interrupt Mask Register
|
||||
EIFR: 0x3c, // External Interrupt Flag Register
|
||||
PCMSK1: 0x6c, // Pin Change Mask Register 1
|
||||
PCMSK0: 0x6b, // Pin Change Mask Register 0
|
||||
}
|
||||
|
||||
// Universal Serial Interface
|
||||
USI = struct {
|
||||
USIDR __reg
|
||||
USISR __reg
|
||||
USICR __reg
|
||||
}{
|
||||
USIDR: 0xba, // USI Data Register
|
||||
USISR: 0xb9, // USI Status Register
|
||||
USICR: 0xb8, // USI Control Register
|
||||
}
|
||||
|
||||
// Analog-to-Digital Converter
|
||||
ADC = struct {
|
||||
ADMUX __reg
|
||||
ADCSRA __reg
|
||||
ADCL __reg
|
||||
ADCH __reg
|
||||
DIDR0 __reg
|
||||
}{
|
||||
ADMUX: 0x7c, // The ADC multiplexer Selection Register
|
||||
ADCSRA: 0x7a, // The ADC Control and Status register
|
||||
ADCL: 0x78, // ADC Data Register Bytes
|
||||
ADCH: 0x78, // ADC Data Register Bytes
|
||||
DIDR0: 0x7e, // Digital Input Disable Register 0
|
||||
}
|
||||
|
||||
// Bootloader
|
||||
BOOT_LOAD = struct {
|
||||
SPMCSR __reg
|
||||
}{
|
||||
SPMCSR: 0x57, // Store Program Memory Control Register
|
||||
}
|
||||
|
||||
// USART
|
||||
USART = struct {
|
||||
UDR0 __reg
|
||||
UCSR0A __reg
|
||||
UCSR0B __reg
|
||||
UCSR0C __reg
|
||||
UBRR0L __reg
|
||||
UBRR0H __reg
|
||||
}{
|
||||
UDR0: 0xc6, // USART I/O Data Register
|
||||
UCSR0A: 0xc0, // USART Control and Status Register A
|
||||
UCSR0B: 0xc1, // USART Control and Status Register B
|
||||
UCSR0C: 0xc2, // USART Control and Status Register C
|
||||
UBRR0L: 0xc4, // USART Baud Rate Register Bytes
|
||||
UBRR0H: 0xc4, // USART Baud Rate Register Bytes
|
||||
}
|
||||
|
||||
// CPU Registers
|
||||
CPU = struct {
|
||||
SREG __reg
|
||||
SPL __reg
|
||||
SPH __reg
|
||||
OSCCAL __reg
|
||||
CLKPR __reg
|
||||
PRR __reg
|
||||
SMCR __reg
|
||||
GPIOR2 __reg
|
||||
GPIOR1 __reg
|
||||
GPIOR0 __reg
|
||||
}{
|
||||
SREG: 0x5f, // Status Register
|
||||
SPL: 0x5d, // Stack Pointer
|
||||
SPH: 0x5d, // Stack Pointer
|
||||
OSCCAL: 0x66, // Oscillator Calibration Value
|
||||
CLKPR: 0x61, // Clock Prescale Register
|
||||
PRR: 0x64, // Power Reduction Register
|
||||
SMCR: 0x53, // Sleep Mode Control Register
|
||||
GPIOR2: 0x4b, // General Purpose IO Register 2
|
||||
GPIOR1: 0x4a, // General Purpose IO Register 1
|
||||
GPIOR0: 0x3e, // General Purpose IO Register 0
|
||||
}
|
||||
)
|
||||
|
||||
// Bitfields for FUSE: Fuses
|
||||
const (
|
||||
// EXTENDED
|
||||
EXTENDED_BODLEVEL = 0xe // Brown-out Detector trigger level
|
||||
EXTENDED_RSTDISBL = 0x1 // Disable external reset
|
||||
|
||||
// HIGH
|
||||
HIGH_OCDEN = 0x80 // On-Chip Debug Enabled
|
||||
HIGH_JTAGEN = 0x40 // JTAG Interface Enabled
|
||||
HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled
|
||||
HIGH_WDTON = 0x10 // Watchdog timer always on
|
||||
HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle
|
||||
HIGH_BOOTSZ = 0x6 // Select Boot Size
|
||||
HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled
|
||||
|
||||
// LOW
|
||||
LOW_CKDIV8 = 0x80 // Divide clock by 8 internally
|
||||
LOW_CKOUT = 0x40 // Clock output on PORTE7
|
||||
LOW_SUT_CKSEL = 0x3f // Select Clock Source
|
||||
)
|
||||
|
||||
// Bitfields for LOCKBIT: Lockbits
|
||||
const (
|
||||
// LOCKBIT
|
||||
LOCKBIT_LB = 0x3 // Memory Lock
|
||||
LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode
|
||||
LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode
|
||||
)
|
||||
|
||||
// Bitfields for TC8: Timer/Counter, 8-bit
|
||||
const (
|
||||
// TCCR0A: Timer/Counter0 Control Register
|
||||
TCCR0A_FOC0A = 0x80 // Force Output Compare
|
||||
TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0
|
||||
TCCR0A_COM0A = 0x30 // Compare Match Output Modes
|
||||
TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1
|
||||
TCCR0A_CS0 = 0x7 // Clock Selects
|
||||
|
||||
// TIMSK0: Timer/Counter0 Interrupt Mask Register
|
||||
TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable
|
||||
TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable
|
||||
|
||||
// TIFR0: Timer/Counter0 Interrupt Flag register
|
||||
TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0
|
||||
TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag
|
||||
)
|
||||
|
||||
// Bitfields for TC16: Timer/Counter, 16-bit
|
||||
const (
|
||||
// TCCR1A: Timer/Counter1 Control Register A
|
||||
TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits
|
||||
TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits
|
||||
TCCR1A_WGM1 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TCCR1B: Timer/Counter1 Control Register B
|
||||
TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler
|
||||
TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select
|
||||
TCCR1B_WGM1 = 0x18 // Waveform Generation Mode
|
||||
TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1
|
||||
|
||||
// TCCR1C: Timer/Counter 1 Control Register C
|
||||
TCCR1C_FOC1A = 0x80 // Force Output Compare 1A
|
||||
TCCR1C_FOC1B = 0x40 // Force Output Compare 1B
|
||||
|
||||
// TIMSK1: Timer/Counter1 Interrupt Mask Register
|
||||
TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable
|
||||
TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable
|
||||
TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable
|
||||
TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable
|
||||
|
||||
// TIFR1: Timer/Counter1 Interrupt Flag register
|
||||
TIFR1_ICF1 = 0x20 // Input Capture Flag 1
|
||||
TIFR1_OCF1B = 0x4 // Output Compare Flag 1B
|
||||
TIFR1_OCF1A = 0x2 // Output Compare Flag 1A
|
||||
TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag
|
||||
)
|
||||
|
||||
// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async
|
||||
const (
|
||||
// TCCR2A: Timer/Counter2 Control Register
|
||||
TCCR2A_FOC2A = 0x80 // Force Output Compare A
|
||||
TCCR2A_WGM20 = 0x40 // Waveform Generation Mode
|
||||
TCCR2A_COM2A = 0x30 // Compare Output Mode bits
|
||||
TCCR2A_WGM21 = 0x8 // Waveform Generation Mode
|
||||
TCCR2A_CS2 = 0x7 // Clock Select bits
|
||||
|
||||
// TIMSK2: Timer/Counter2 Interrupt Mask register
|
||||
TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable
|
||||
TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable
|
||||
|
||||
// TIFR2: Timer/Counter2 Interrupt Flag Register
|
||||
TIFR2_OCF2A = 0x2 // Timer/Counter2 Output Compare Flag 2
|
||||
TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag
|
||||
|
||||
// ASSR: Asynchronous Status Register
|
||||
ASSR_EXCLK = 0x10 // Enable External Clock Interrupt
|
||||
ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2
|
||||
ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy
|
||||
ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy
|
||||
ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy
|
||||
)
|
||||
|
||||
// Bitfields for WDT: Watchdog Timer
|
||||
const (
|
||||
// WDTCR: Watchdog Timer Control Register
|
||||
WDTCR_WDCE = 0x10 // Watchdog Change Enable
|
||||
WDTCR_WDE = 0x8 // Watch Dog Enable
|
||||
WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits
|
||||
)
|
||||
|
||||
// Bitfields for EEPROM: EEPROM
|
||||
const (
|
||||
// EECR: EEPROM Control Register
|
||||
EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable
|
||||
EECR_EEMWE = 0x4 // EEPROM Master Write Enable
|
||||
EECR_EEWE = 0x2 // EEPROM Write Enable
|
||||
EECR_EERE = 0x1 // EEPROM Read Enable
|
||||
)
|
||||
|
||||
// Bitfields for SPI: Serial Peripheral Interface
|
||||
const (
|
||||
// SPCR: SPI Control Register
|
||||
SPCR_SPIE = 0x80 // SPI Interrupt Enable
|
||||
SPCR_SPE = 0x40 // SPI Enable
|
||||
SPCR_DORD = 0x20 // Data Order
|
||||
SPCR_MSTR = 0x10 // Master/Slave Select
|
||||
SPCR_CPOL = 0x8 // Clock polarity
|
||||
SPCR_CPHA = 0x4 // Clock Phase
|
||||
SPCR_SPR = 0x3 // SPI Clock Rate Selects
|
||||
|
||||
// SPSR: SPI Status Register
|
||||
SPSR_SPIF = 0x80 // SPI Interrupt Flag
|
||||
SPSR_WCOL = 0x40 // Write Collision Flag
|
||||
SPSR_SPI2X = 0x1 // Double SPI Speed Bit
|
||||
)
|
||||
|
||||
// Bitfields for AC: Analog Comparator
|
||||
const (
|
||||
// ACSR: Analog Comparator Control And Status Register
|
||||
ACSR_ACD = 0x80 // Analog Comparator Disable
|
||||
ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select
|
||||
ACSR_ACO = 0x20 // Analog Compare Output
|
||||
ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag
|
||||
ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable
|
||||
ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable
|
||||
ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits
|
||||
|
||||
// DIDR1: Digital Input Disable Register 1
|
||||
DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable
|
||||
DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable
|
||||
)
|
||||
|
||||
// Bitfields for LCD: Liquid Crystal Display
|
||||
const (
|
||||
// LCDCRA: LCD Control Register A
|
||||
LCDCRA_LCDEN = 0x80 // LCD Enable
|
||||
LCDCRA_LCDAB = 0x40 // LCD A or B waveform
|
||||
LCDCRA_LCDIF = 0x10 // LCD Interrupt Flag
|
||||
LCDCRA_LCDIE = 0x8 // LCD Interrupt Enable
|
||||
LCDCRA_LCDBD = 0x4 // LCD Buffer Disable
|
||||
LCDCRA_LCDCCD = 0x2 // LCD Contrast Control Disable
|
||||
LCDCRA_LCDBL = 0x1 // LCD Blanking
|
||||
|
||||
// LCDCRB: LCD Control and Status Register B
|
||||
LCDCRB_LCDCS = 0x80 // LCD CLock Select
|
||||
LCDCRB_LCD2B = 0x40 // LCD 1/2 Bias Select
|
||||
LCDCRB_LCDMUX = 0x30 // LCD Mux Selects
|
||||
LCDCRB_LCDPM = 0x7 // LCD Port Masks
|
||||
|
||||
// LCDFRR: LCD Frame Rate Register
|
||||
LCDFRR_LCDPS = 0x70 // LCD Prescaler Selects
|
||||
LCDFRR_LCDCD = 0x7 // LCD Clock Dividers
|
||||
|
||||
// LCDCCR: LCD Contrast Control Register
|
||||
LCDCCR_LCDDC = 0xe0 // LCD Display Configuration Bits
|
||||
LCDCCR_LCDMDT = 0x10 // LCD Maximum Drive Time
|
||||
LCDCCR_LCDCC = 0xf // LCD Contrast Controls
|
||||
)
|
||||
|
||||
// Bitfields for EXINT: External Interrupts
|
||||
const (
|
||||
// EICRA: External Interrupt Control Register
|
||||
EICRA_ISC01 = 0x2 // External Interrupt Sense Control 0 Bit 1
|
||||
EICRA_ISC00 = 0x1 // External Interrupt Sense Control 0 Bit 0
|
||||
|
||||
// EIMSK: External Interrupt Mask Register
|
||||
EIMSK_PCIE = 0xc0 // Pin Change Interrupt Enables
|
||||
EIMSK_INT0 = 0x1 // External Interrupt Request 0 Enable
|
||||
|
||||
// EIFR: External Interrupt Flag Register
|
||||
EIFR_PCIF = 0xc0 // Pin Change Interrupt Flags
|
||||
EIFR_INTF0 = 0x1 // External Interrupt Flag 0
|
||||
|
||||
// PCMSK1: Pin Change Mask Register 1
|
||||
PCMSK1_PCINT = 0xff // Pin Change Enable Masks
|
||||
|
||||
// PCMSK0: Pin Change Mask Register 0
|
||||
PCMSK0_PCINT = 0xff // Pin Change Enable Masks
|
||||
)
|
||||
|
||||
// Bitfields for USI: Universal Serial Interface
|
||||
const (
|
||||
// USISR: USI Status Register
|
||||
USISR_USISIF = 0x80 // Start Condition Interrupt Flag
|
||||
USISR_USIOIF = 0x40 // Counter Overflow Interrupt Flag
|
||||
USISR_USIPF = 0x20 // Stop Condition Flag
|
||||
USISR_USIDC = 0x10 // Data Output Collision
|
||||
USISR_USICNT = 0xf // USI Counter Value Bits
|
||||
|
||||
// USICR: USI Control Register
|
||||
USICR_USISIE = 0x80 // Start Condition Interrupt Enable
|
||||
USICR_USIOIE = 0x40 // Counter Overflow Interrupt Enable
|
||||
USICR_USIWM = 0x30 // USI Wire Mode Bits
|
||||
USICR_USICS = 0xc // USI Clock Source Select Bits
|
||||
USICR_USICLK = 0x2 // Clock Strobe
|
||||
USICR_USITC = 0x1 // Toggle Clock Port Pin
|
||||
)
|
||||
|
||||
// Bitfields for ADC: Analog-to-Digital Converter
|
||||
const (
|
||||
// ADMUX: The ADC multiplexer Selection Register
|
||||
ADMUX_REFS = 0xc0 // Reference Selection Bits
|
||||
ADMUX_ADLAR = 0x20 // Left Adjust Result
|
||||
ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits
|
||||
|
||||
// ADCSRA: The ADC Control and Status register
|
||||
ADCSRA_ADEN = 0x80 // ADC Enable
|
||||
ADCSRA_ADSC = 0x40 // ADC Start Conversion
|
||||
ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable
|
||||
ADCSRA_ADIF = 0x10 // ADC Interrupt Flag
|
||||
ADCSRA_ADIE = 0x8 // ADC Interrupt Enable
|
||||
ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits
|
||||
|
||||
// DIDR0: Digital Input Disable Register 0
|
||||
DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable
|
||||
DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable
|
||||
DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable
|
||||
DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable
|
||||
DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable
|
||||
DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable
|
||||
DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable
|
||||
DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable
|
||||
)
|
||||
|
||||
// Bitfields for BOOT_LOAD: Bootloader
|
||||
const (
|
||||
// SPMCSR: Store Program Memory Control Register
|
||||
SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable
|
||||
SPMCSR_RWWSB = 0x40 // Read While Write Section Busy
|
||||
SPMCSR_RWWSRE = 0x10 // Read While Write section read enable
|
||||
SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set
|
||||
SPMCSR_PGWRT = 0x4 // Page Write
|
||||
SPMCSR_PGERS = 0x2 // Page Erase
|
||||
SPMCSR_SPMEN = 0x1 // Store Program Memory Enable
|
||||
)
|
||||
|
||||
// Bitfields for USART: USART
|
||||
const (
|
||||
// UCSR0A: USART Control and Status Register A
|
||||
UCSR0A_RXC0 = 0x80 // USART Receive Complete
|
||||
UCSR0A_TXC0 = 0x40 // USART Transmit Complete
|
||||
UCSR0A_UDRE0 = 0x20 // USART Data Register Empty
|
||||
UCSR0A_FE0 = 0x10 // Framing Error
|
||||
UCSR0A_DOR0 = 0x8 // Data OverRun
|
||||
UCSR0A_UPE0 = 0x4 // USART Parity Error
|
||||
UCSR0A_U2X0 = 0x2 // Double the USART Transmission Speed
|
||||
UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode
|
||||
|
||||
// UCSR0B: USART Control and Status Register B
|
||||
UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable
|
||||
UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable
|
||||
UCSR0B_UDRIE0 = 0x20 // USART Data Register Empty Interrupt Enable
|
||||
UCSR0B_RXEN0 = 0x10 // Receiver Enable
|
||||
UCSR0B_TXEN0 = 0x8 // Transmitter Enable
|
||||
UCSR0B_UCSZ02 = 0x4 // Character Size
|
||||
UCSR0B_RXB80 = 0x2 // Receive Data Bit 8
|
||||
UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8
|
||||
|
||||
// UCSR0C: USART Control and Status Register C
|
||||
UCSR0C_UMSEL0 = 0x40 // USART Mode Select
|
||||
UCSR0C_UPM0 = 0x30 // Parity Mode Bits
|
||||
UCSR0C_USBS0 = 0x8 // Stop Bit Select
|
||||
UCSR0C_UCSZ0 = 0x6 // Character Size
|
||||
UCSR0C_UCPOL0 = 0x1 // Clock Polarity
|
||||
)
|
||||
|
||||
// Bitfields for CPU: CPU Registers
|
||||
const (
|
||||
// SREG: Status Register
|
||||
SREG_I = 0x80 // Global Interrupt Enable
|
||||
SREG_T = 0x40 // Bit Copy Storage
|
||||
SREG_H = 0x20 // Half Carry Flag
|
||||
SREG_S = 0x10 // Sign Bit
|
||||
SREG_V = 0x8 // Two's Complement Overflow Flag
|
||||
SREG_N = 0x4 // Negative Flag
|
||||
SREG_Z = 0x2 // Zero Flag
|
||||
SREG_C = 0x1 // Carry Flag
|
||||
|
||||
// OSCCAL: Oscillator Calibration Value
|
||||
OSCCAL_OSCCAL = 0xff // Oscillator Calibration
|
||||
|
||||
// CLKPR: Clock Prescale Register
|
||||
CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable
|
||||
CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits
|
||||
|
||||
// PRR: Power Reduction Register
|
||||
PRR_PRLCD = 0x10 // Power Reduction LCD
|
||||
PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1
|
||||
PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface
|
||||
PRR_PRUSART0 = 0x2 // Power Reduction USART
|
||||
PRR_PRADC = 0x1 // Power Reduction ADC
|
||||
|
||||
// SMCR: Sleep Mode Control Register
|
||||
SMCR_SM = 0xe // Sleep Mode Select bits
|
||||
SMCR_SE = 0x1 // Sleep Enable
|
||||
)
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from ATmega169P.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x4000;
|
||||
__ram_size = 0x400;
|
||||
__num_isrs = 23;
|
||||
|
|
@ -1,747 +0,0 @@
|
|||
// Automatically generated file. DO NOT EDIT.
|
||||
// Generated by gen-device.py from ATmega169PA.atdf, see http://packs.download.atmel.com/
|
||||
|
||||
// +build avr,atmega169pa
|
||||
|
||||
// Device information for the ATmega169PA.
|
||||
//
|
||||
package avr
|
||||
|
||||
// Magic type name for the compiler.
|
||||
type __reg uint8
|
||||
|
||||
// Export this magic type name.
|
||||
type RegValue = __reg
|
||||
|
||||
// Some information about this device.
|
||||
const (
|
||||
DEVICE = "ATmega169PA"
|
||||
ARCH = "AVR8"
|
||||
FAMILY = "megaAVR"
|
||||
)
|
||||
|
||||
// Interrupts
|
||||
const (
|
||||
IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet.
|
||||
IRQ_INT0 = 1 // External Interrupt Request 0
|
||||
IRQ_PCINT0 = 2 // Pin Change Interrupt Request 0
|
||||
IRQ_PCINT1 = 3 // Pin Change Interrupt Request 1
|
||||
IRQ_TIMER2_COMP = 4 // Timer/Counter2 Compare Match
|
||||
IRQ_TIMER2_OVF = 5 // Timer/Counter2 Overflow
|
||||
IRQ_TIMER1_CAPT = 6 // Timer/Counter1 Capture Event
|
||||
IRQ_TIMER1_COMPA = 7 // Timer/Counter1 Compare Match A
|
||||
IRQ_TIMER1_COMPB = 8 // Timer/Counter Compare Match B
|
||||
IRQ_TIMER1_OVF = 9 // Timer/Counter1 Overflow
|
||||
IRQ_TIMER0_COMP = 10 // Timer/Counter0 Compare Match
|
||||
IRQ_TIMER0_OVF = 11 // Timer/Counter0 Overflow
|
||||
IRQ_SPI_STC = 12 // SPI Serial Transfer Complete
|
||||
IRQ_USART0_RX = 13 // USART0, Rx Complete
|
||||
IRQ_USART0_UDRE = 14 // USART0 Data register Empty
|
||||
IRQ_USART0_TX = 15 // USART0, Tx Complete
|
||||
IRQ_USI_START = 16 // USI Start Condition
|
||||
IRQ_USI_OVERFLOW = 17 // USI Overflow
|
||||
IRQ_ANALOG_COMP = 18 // Analog Comparator
|
||||
IRQ_ADC = 19 // ADC Conversion Complete
|
||||
IRQ_EE_READY = 20 // EEPROM Ready
|
||||
IRQ_SPM_READY = 21 // Store Program Memory Read
|
||||
IRQ_LCD = 22 // LCD Start of Frame
|
||||
IRQ_max = 22 // Highest interrupt number on this device.
|
||||
)
|
||||
|
||||
// Peripherals
|
||||
var (
|
||||
// Fuses
|
||||
FUSE = struct {
|
||||
EXTENDED __reg
|
||||
HIGH __reg
|
||||
LOW __reg
|
||||
}{
|
||||
EXTENDED: 0x2,
|
||||
HIGH: 0x1,
|
||||
LOW: 0x0,
|
||||
}
|
||||
|
||||
// Lockbits
|
||||
LOCKBIT = struct {
|
||||
LOCKBIT __reg
|
||||
}{
|
||||
LOCKBIT: 0x0,
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit
|
||||
TC8 = struct {
|
||||
TCCR0A __reg
|
||||
TCNT0 __reg
|
||||
OCR0A __reg
|
||||
TIMSK0 __reg
|
||||
TIFR0 __reg
|
||||
}{
|
||||
TCCR0A: 0x44, // Timer/Counter0 Control Register
|
||||
TCNT0: 0x46, // Timer/Counter0
|
||||
OCR0A: 0x47, // Timer/Counter0 Output Compare Register
|
||||
TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register
|
||||
TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register
|
||||
}
|
||||
|
||||
// Timer/Counter, 16-bit
|
||||
TC16 = struct {
|
||||
TCCR1A __reg
|
||||
TCCR1B __reg
|
||||
TCCR1C __reg
|
||||
TCNT1L __reg
|
||||
TCNT1H __reg
|
||||
OCR1AL __reg
|
||||
OCR1AH __reg
|
||||
OCR1BL __reg
|
||||
OCR1BH __reg
|
||||
ICR1L __reg
|
||||
ICR1H __reg
|
||||
TIMSK1 __reg
|
||||
TIFR1 __reg
|
||||
}{
|
||||
TCCR1A: 0x80, // Timer/Counter1 Control Register A
|
||||
TCCR1B: 0x81, // Timer/Counter1 Control Register B
|
||||
TCCR1C: 0x82, // Timer/Counter 1 Control Register C
|
||||
TCNT1L: 0x84, // Timer/Counter1 Bytes
|
||||
TCNT1H: 0x84, // Timer/Counter1 Bytes
|
||||
OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes
|
||||
OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes
|
||||
OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes
|
||||
OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes
|
||||
ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register
|
||||
TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit Async
|
||||
TC8_ASYNC = struct {
|
||||
TCCR2A __reg
|
||||
TCNT2 __reg
|
||||
OCR2A __reg
|
||||
TIMSK2 __reg
|
||||
TIFR2 __reg
|
||||
ASSR __reg
|
||||
}{
|
||||
TCCR2A: 0xb0, // Timer/Counter2 Control Register
|
||||
TCNT2: 0xb2, // Timer/Counter2
|
||||
OCR2A: 0xb3, // Timer/Counter2 Output Compare Register
|
||||
TIMSK2: 0x70, // Timer/Counter2 Interrupt Mask register
|
||||
TIFR2: 0x37, // Timer/Counter2 Interrupt Flag Register
|
||||
ASSR: 0xb6, // Asynchronous Status Register
|
||||
}
|
||||
|
||||
// Watchdog Timer
|
||||
WDT = struct {
|
||||
WDTCR __reg
|
||||
}{
|
||||
WDTCR: 0x60, // Watchdog Timer Control Register
|
||||
}
|
||||
|
||||
// EEPROM
|
||||
EEPROM = struct {
|
||||
EEARL __reg
|
||||
EEARH __reg
|
||||
EEDR __reg
|
||||
EECR __reg
|
||||
}{
|
||||
EEARL: 0x41, // EEPROM Address Register Bytes
|
||||
EEARH: 0x41, // EEPROM Address Register Bytes
|
||||
EEDR: 0x40, // EEPROM Data Register
|
||||
EECR: 0x3f, // EEPROM Control Register
|
||||
}
|
||||
|
||||
// Serial Peripheral Interface
|
||||
SPI = struct {
|
||||
SPCR __reg
|
||||
SPSR __reg
|
||||
SPDR __reg
|
||||
}{
|
||||
SPCR: 0x4c, // SPI Control Register
|
||||
SPSR: 0x4d, // SPI Status Register
|
||||
SPDR: 0x4e, // SPI Data Register
|
||||
}
|
||||
|
||||
// I/O Port
|
||||
PORT = struct {
|
||||
PORTA __reg
|
||||
DDRA __reg
|
||||
PINA __reg
|
||||
PORTB __reg
|
||||
DDRB __reg
|
||||
PINB __reg
|
||||
PORTC __reg
|
||||
DDRC __reg
|
||||
PINC __reg
|
||||
PORTD __reg
|
||||
DDRD __reg
|
||||
PIND __reg
|
||||
PORTE __reg
|
||||
DDRE __reg
|
||||
PINE __reg
|
||||
PORTF __reg
|
||||
DDRF __reg
|
||||
PINF __reg
|
||||
PORTG __reg
|
||||
DDRG __reg
|
||||
PING __reg
|
||||
}{
|
||||
PORTA: 0x22, // Port A Data Register
|
||||
DDRA: 0x21, // Port A Data Direction Register
|
||||
PINA: 0x20, // Port A Input Pins
|
||||
PORTB: 0x25, // Port B Data Register
|
||||
DDRB: 0x24, // Port B Data Direction Register
|
||||
PINB: 0x23, // Port B Input Pins
|
||||
PORTC: 0x28, // Port C Data Register
|
||||
DDRC: 0x27, // Port C Data Direction Register
|
||||
PINC: 0x26, // Port C Input Pins
|
||||
PORTD: 0x2b, // Port D Data Register
|
||||
DDRD: 0x2a, // Port D Data Direction Register
|
||||
PIND: 0x29, // Port D Input Pins
|
||||
PORTE: 0x2e, // Data Register, Port E
|
||||
DDRE: 0x2d, // Data Direction Register, Port E
|
||||
PINE: 0x2c, // Input Pins, Port E
|
||||
PORTF: 0x31, // Data Register, Port F
|
||||
DDRF: 0x30, // Data Direction Register, Port F
|
||||
PINF: 0x2f, // Input Pins, Port F
|
||||
PORTG: 0x34, // Port G Data Register
|
||||
DDRG: 0x33, // Port G Data Direction Register
|
||||
PING: 0x32, // Port G Input Pins
|
||||
}
|
||||
|
||||
// Analog Comparator
|
||||
AC = struct {
|
||||
ACSR __reg
|
||||
DIDR1 __reg
|
||||
}{
|
||||
ACSR: 0x50, // Analog Comparator Control And Status Register
|
||||
DIDR1: 0x7f, // Digital Input Disable Register 1
|
||||
}
|
||||
|
||||
// JTAG Interface
|
||||
JTAG = struct {
|
||||
OCDR __reg
|
||||
}{
|
||||
OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory
|
||||
}
|
||||
|
||||
// Liquid Crystal Display
|
||||
LCD = struct {
|
||||
LCDCRA __reg
|
||||
LCDCRB __reg
|
||||
LCDFRR __reg
|
||||
LCDCCR __reg
|
||||
LCDDR18 __reg
|
||||
LCDDR17 __reg
|
||||
LCDDR16 __reg
|
||||
LCDDR15 __reg
|
||||
LCDDR13 __reg
|
||||
LCDDR12 __reg
|
||||
LCDDR11 __reg
|
||||
LCDDR10 __reg
|
||||
LCDDR8 __reg
|
||||
LCDDR7 __reg
|
||||
LCDDR6 __reg
|
||||
LCDDR5 __reg
|
||||
LCDDR3 __reg
|
||||
LCDDR2 __reg
|
||||
LCDDR1 __reg
|
||||
LCDDR0 __reg
|
||||
}{
|
||||
LCDCRA: 0xe4, // LCD Control Register A
|
||||
LCDCRB: 0xe5, // LCD Control and Status Register B
|
||||
LCDFRR: 0xe6, // LCD Frame Rate Register
|
||||
LCDCCR: 0xe7, // LCD Contrast Control Register
|
||||
LCDDR18: 0xfe, // LCD Data Register 18
|
||||
LCDDR17: 0xfd, // LCD Data Register 17
|
||||
LCDDR16: 0xfc, // LCD Data Register 16
|
||||
LCDDR15: 0xfb, // LCD Data Register 15
|
||||
LCDDR13: 0xf9, // LCD Data Register 13
|
||||
LCDDR12: 0xf8, // LCD Data Register 12
|
||||
LCDDR11: 0xf7, // LCD Data Register 11
|
||||
LCDDR10: 0xf6, // LCD Data Register 10
|
||||
LCDDR8: 0xf4, // LCD Data Register 8
|
||||
LCDDR7: 0xf3, // LCD Data Register 7
|
||||
LCDDR6: 0xf2, // LCD Data Register 6
|
||||
LCDDR5: 0xf1, // LCD Data Register 5
|
||||
LCDDR3: 0xef, // LCD Data Register 3
|
||||
LCDDR2: 0xee, // LCD Data Register 2
|
||||
LCDDR1: 0xed, // LCD Data Register 1
|
||||
LCDDR0: 0xec, // LCD Data Register 0
|
||||
}
|
||||
|
||||
// Universal Serial Interface
|
||||
USI = struct {
|
||||
USIDR __reg
|
||||
USISR __reg
|
||||
USICR __reg
|
||||
}{
|
||||
USIDR: 0xba, // USI Data Register
|
||||
USISR: 0xb9, // USI Status Register
|
||||
USICR: 0xb8, // USI Control Register
|
||||
}
|
||||
|
||||
// Analog-to-Digital Converter
|
||||
ADC = struct {
|
||||
ADMUX __reg
|
||||
ADCSRA __reg
|
||||
ADCL __reg
|
||||
ADCH __reg
|
||||
DIDR0 __reg
|
||||
}{
|
||||
ADMUX: 0x7c, // The ADC multiplexer Selection Register
|
||||
ADCSRA: 0x7a, // The ADC Control and Status register
|
||||
ADCL: 0x78, // ADC Data Register Bytes
|
||||
ADCH: 0x78, // ADC Data Register Bytes
|
||||
DIDR0: 0x7e, // Digital Input Disable Register 0
|
||||
}
|
||||
|
||||
// Bootloader
|
||||
BOOT_LOAD = struct {
|
||||
SPMCSR __reg
|
||||
}{
|
||||
SPMCSR: 0x57, // Store Program Memory Control Register
|
||||
}
|
||||
|
||||
// USART
|
||||
USART = struct {
|
||||
UDR0 __reg
|
||||
UCSR0A __reg
|
||||
UCSR0B __reg
|
||||
UCSR0C __reg
|
||||
UBRR0L __reg
|
||||
UBRR0H __reg
|
||||
}{
|
||||
UDR0: 0xc6, // USART I/O Data Register
|
||||
UCSR0A: 0xc0, // USART Control and Status Register A
|
||||
UCSR0B: 0xc1, // USART Control and Status Register B
|
||||
UCSR0C: 0xc2, // USART Control and Status Register C
|
||||
UBRR0L: 0xc4, // USART Baud Rate Register Bytes
|
||||
UBRR0H: 0xc4, // USART Baud Rate Register Bytes
|
||||
}
|
||||
|
||||
// External Interrupts
|
||||
EXINT = struct {
|
||||
EICRA __reg
|
||||
EIMSK __reg
|
||||
EIFR __reg
|
||||
PCMSK1 __reg
|
||||
PCMSK0 __reg
|
||||
}{
|
||||
EICRA: 0x69, // External Interrupt Control Register
|
||||
EIMSK: 0x3d, // External Interrupt Mask Register
|
||||
EIFR: 0x3c, // External Interrupt Flag Register
|
||||
PCMSK1: 0x6c, // Pin Change Mask Register 1
|
||||
PCMSK0: 0x6b, // Pin Change Mask Register 0
|
||||
}
|
||||
|
||||
// CPU Registers
|
||||
CPU = struct {
|
||||
SREG __reg
|
||||
SPL __reg
|
||||
SPH __reg
|
||||
OSCCAL __reg
|
||||
CLKPR __reg
|
||||
PRR __reg
|
||||
SMCR __reg
|
||||
GPIOR2 __reg
|
||||
GPIOR1 __reg
|
||||
GPIOR0 __reg
|
||||
}{
|
||||
SREG: 0x5f, // Status Register
|
||||
SPL: 0x5d, // Stack Pointer
|
||||
SPH: 0x5d, // Stack Pointer
|
||||
OSCCAL: 0x66, // Oscillator Calibration Value
|
||||
CLKPR: 0x61, // Clock Prescale Register
|
||||
PRR: 0x64, // Power Reduction Register
|
||||
SMCR: 0x53, // Sleep Mode Control Register
|
||||
GPIOR2: 0x4b, // General Purpose IO Register 2
|
||||
GPIOR1: 0x4a, // General Purpose IO Register 1
|
||||
GPIOR0: 0x3e, // General Purpose IO Register 0
|
||||
}
|
||||
)
|
||||
|
||||
// Bitfields for FUSE: Fuses
|
||||
const (
|
||||
// EXTENDED
|
||||
EXTENDED_BODLEVEL = 0xe // Brown-out Detector trigger level
|
||||
EXTENDED_RSTDISBL = 0x1 // Disable external reset
|
||||
|
||||
// HIGH
|
||||
HIGH_OCDEN = 0x80 // On-Chip Debug Enabled
|
||||
HIGH_JTAGEN = 0x40 // JTAG Interface Enabled
|
||||
HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled
|
||||
HIGH_WDTON = 0x10 // Watchdog timer always on
|
||||
HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle
|
||||
HIGH_BOOTSZ = 0x6 // Select Boot Size
|
||||
HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled
|
||||
|
||||
// LOW
|
||||
LOW_CKDIV8 = 0x80 // Divide clock by 8 internally
|
||||
LOW_CKOUT = 0x40 // Clock output on PORTE7
|
||||
LOW_SUT_CKSEL = 0x3f // Select Clock Source
|
||||
)
|
||||
|
||||
// Bitfields for LOCKBIT: Lockbits
|
||||
const (
|
||||
// LOCKBIT
|
||||
LOCKBIT_LB = 0x3 // Memory Lock
|
||||
LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode
|
||||
LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode
|
||||
)
|
||||
|
||||
// Bitfields for TC8: Timer/Counter, 8-bit
|
||||
const (
|
||||
// TCCR0A: Timer/Counter0 Control Register
|
||||
TCCR0A_FOC0A = 0x80 // Force Output Compare
|
||||
TCCR0A_WGM00 = 0x40 // Waveform Generation Mode 0
|
||||
TCCR0A_COM0A = 0x30 // Compare Match Output Modes
|
||||
TCCR0A_WGM01 = 0x8 // Waveform Generation Mode 1
|
||||
TCCR0A_CS0 = 0x7 // Clock Selects
|
||||
|
||||
// TCNT0: Timer/Counter0
|
||||
TCNT0_TCNT0 = 0xff // Timer/Counter0 bits
|
||||
|
||||
// OCR0A: Timer/Counter0 Output Compare Register
|
||||
OCR0A_OCR0A = 0xff // Timer/Counter0 Output Compare A
|
||||
|
||||
// TIMSK0: Timer/Counter0 Interrupt Mask Register
|
||||
TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable
|
||||
TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable
|
||||
|
||||
// TIFR0: Timer/Counter0 Interrupt Flag register
|
||||
TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0
|
||||
TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag
|
||||
)
|
||||
|
||||
// Bitfields for TC16: Timer/Counter, 16-bit
|
||||
const (
|
||||
// TCCR1A: Timer/Counter1 Control Register A
|
||||
TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits
|
||||
TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits
|
||||
TCCR1A_WGM1 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TCCR1B: Timer/Counter1 Control Register B
|
||||
TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler
|
||||
TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select
|
||||
TCCR1B_WGM1 = 0x18 // Waveform Generation Mode
|
||||
TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1
|
||||
|
||||
// TCCR1C: Timer/Counter 1 Control Register C
|
||||
TCCR1C_FOC1A = 0x80 // Force Output Compare 1A
|
||||
TCCR1C_FOC1B = 0x40 // Force Output Compare 1B
|
||||
|
||||
// TCNT1L: Timer/Counter1 Bytes
|
||||
|
||||
// TCNT1H: Timer/Counter1 Bytes
|
||||
TCNT1_TCNT1 = 0xffff // Timer/Counter1 bits
|
||||
|
||||
// OCR1AL: Timer/Counter1 Output Compare Register A Bytes
|
||||
|
||||
// OCR1AH: Timer/Counter1 Output Compare Register A Bytes
|
||||
OCR1A_OCR1A = 0xffff // Timer/Counter1 Output Compare A
|
||||
|
||||
// OCR1BL: Timer/Counter1 Output Compare Register B Bytes
|
||||
|
||||
// OCR1BH: Timer/Counter1 Output Compare Register B Bytes
|
||||
OCR1B_OCR1B = 0xffff // Timer/Counter1 Output Compare B
|
||||
|
||||
// ICR1L: Timer/Counter1 Input Capture Register Bytes
|
||||
|
||||
// ICR1H: Timer/Counter1 Input Capture Register Bytes
|
||||
ICR1_ICR1 = 0xffff // Timer/Counter1 Input Capture
|
||||
|
||||
// TIMSK1: Timer/Counter1 Interrupt Mask Register
|
||||
TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable
|
||||
TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable
|
||||
TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable
|
||||
TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable
|
||||
|
||||
// TIFR1: Timer/Counter1 Interrupt Flag register
|
||||
TIFR1_ICF1 = 0x20 // Input Capture Flag 1
|
||||
TIFR1_OCF1B = 0x4 // Output Compare Flag 1B
|
||||
TIFR1_OCF1A = 0x2 // Output Compare Flag 1A
|
||||
TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag
|
||||
)
|
||||
|
||||
// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async
|
||||
const (
|
||||
// TCCR2A: Timer/Counter2 Control Register
|
||||
TCCR2A_FOC2A = 0x80 // Force Output Compare A
|
||||
TCCR2A_WGM20 = 0x40 // Waveform Generation Mode
|
||||
TCCR2A_COM2A = 0x30 // Compare Output Mode bits
|
||||
TCCR2A_WGM21 = 0x8 // Waveform Generation Mode
|
||||
TCCR2A_CS2 = 0x7 // Clock Select bits
|
||||
|
||||
// TCNT2: Timer/Counter2
|
||||
TCNT2_TCNT2 = 0xff // Timer/Counter2 bits
|
||||
|
||||
// OCR2A: Timer/Counter2 Output Compare Register
|
||||
OCR2A_OCR2A = 0xff // Timer/Counter2 Output Compare A
|
||||
|
||||
// TIMSK2: Timer/Counter2 Interrupt Mask register
|
||||
TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable
|
||||
TIMSK2_TOIE2 = 0x1 // Timer/Counter2 Overflow Interrupt Enable
|
||||
|
||||
// TIFR2: Timer/Counter2 Interrupt Flag Register
|
||||
TIFR2_OCF2A = 0x2 // Timer/Counter2 Output Compare Flag 2
|
||||
TIFR2_TOV2 = 0x1 // Timer/Counter2 Overflow Flag
|
||||
|
||||
// ASSR: Asynchronous Status Register
|
||||
ASSR_EXCLK = 0x10 // Enable External Clock Interrupt
|
||||
ASSR_AS2 = 0x8 // AS2: Asynchronous Timer/Counter2
|
||||
ASSR_TCN2UB = 0x4 // TCN2UB: Timer/Counter2 Update Busy
|
||||
ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy
|
||||
ASSR_TCR2UB = 0x1 // TCR2UB: Timer/Counter Control Register2 Update Busy
|
||||
)
|
||||
|
||||
// Bitfields for WDT: Watchdog Timer
|
||||
const (
|
||||
// WDTCR: Watchdog Timer Control Register
|
||||
WDTCR_WDCE = 0x10 // Watchdog Change Enable
|
||||
WDTCR_WDE = 0x8 // Watch Dog Enable
|
||||
WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits
|
||||
)
|
||||
|
||||
// Bitfields for EEPROM: EEPROM
|
||||
const (
|
||||
// EEARL: EEPROM Address Register Bytes
|
||||
|
||||
// EEARH: EEPROM Address Register Bytes
|
||||
EEAR_EEAR = 0x1ff // EEPROM Address Bits
|
||||
|
||||
// EEDR: EEPROM Data Register
|
||||
EEDR_EEDR = 0xff // EEPROM Data Bits
|
||||
|
||||
// EECR: EEPROM Control Register
|
||||
EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable
|
||||
EECR_EEMWE = 0x4 // EEPROM Master Write Enable
|
||||
EECR_EEWE = 0x2 // EEPROM Write Enable
|
||||
EECR_EERE = 0x1 // EEPROM Read Enable
|
||||
)
|
||||
|
||||
// Bitfields for SPI: Serial Peripheral Interface
|
||||
const (
|
||||
// SPCR: SPI Control Register
|
||||
SPCR_SPIE = 0x80 // SPI Interrupt Enable
|
||||
SPCR_SPE = 0x40 // SPI Enable
|
||||
SPCR_DORD = 0x20 // Data Order
|
||||
SPCR_MSTR = 0x10 // Master/Slave Select
|
||||
SPCR_CPOL = 0x8 // Clock polarity
|
||||
SPCR_CPHA = 0x4 // Clock Phase
|
||||
SPCR_SPR = 0x3 // SPI Clock Rate Selects
|
||||
|
||||
// SPSR: SPI Status Register
|
||||
SPSR_SPIF = 0x80 // SPI Interrupt Flag
|
||||
SPSR_WCOL = 0x40 // Write Collision Flag
|
||||
SPSR_SPI2X = 0x1 // Double SPI Speed Bit
|
||||
|
||||
// SPDR: SPI Data Register
|
||||
SPDR_SPDR = 0xff // SPI Data bits
|
||||
)
|
||||
|
||||
// Bitfields for AC: Analog Comparator
|
||||
const (
|
||||
// ACSR: Analog Comparator Control And Status Register
|
||||
ACSR_ACD = 0x80 // Analog Comparator Disable
|
||||
ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select
|
||||
ACSR_ACO = 0x20 // Analog Compare Output
|
||||
ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag
|
||||
ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable
|
||||
ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable
|
||||
ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits
|
||||
|
||||
// DIDR1: Digital Input Disable Register 1
|
||||
DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable
|
||||
DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable
|
||||
)
|
||||
|
||||
// Bitfields for LCD: Liquid Crystal Display
|
||||
const (
|
||||
// LCDCRA: LCD Control Register A
|
||||
LCDCRA_LCDEN = 0x80 // LCD Enable
|
||||
LCDCRA_LCDAB = 0x40 // LCD A or B waveform
|
||||
LCDCRA_LCDIF = 0x10 // LCD Interrupt Flag
|
||||
LCDCRA_LCDIE = 0x8 // LCD Interrupt Enable
|
||||
LCDCRA_LCDBD = 0x4 // LCD Buffer Disable
|
||||
LCDCRA_LCDCCD = 0x2 // LCD Contrast Control Disable
|
||||
LCDCRA_LCDBL = 0x1 // LCD Blanking
|
||||
|
||||
// LCDCRB: LCD Control and Status Register B
|
||||
LCDCRB_LCDCS = 0x80 // LCD CLock Select
|
||||
LCDCRB_LCD2B = 0x40 // LCD 1/2 Bias Select
|
||||
LCDCRB_LCDMUX = 0x30 // LCD Mux Selects
|
||||
LCDCRB_LCDPM = 0x7 // LCD Port Masks
|
||||
|
||||
// LCDFRR: LCD Frame Rate Register
|
||||
LCDFRR_LCDPS = 0x70 // LCD Prescaler Selects
|
||||
LCDFRR_LCDCD = 0x7 // LCD Clock Dividers
|
||||
|
||||
// LCDCCR: LCD Contrast Control Register
|
||||
LCDCCR_LCDDC = 0xe0 // LCD Display Configuration Bits
|
||||
LCDCCR_LCDMDT = 0x10 // LCD Maximum Drive Time
|
||||
LCDCCR_LCDCC = 0xf // LCD Contrast Controls
|
||||
)
|
||||
|
||||
// Bitfields for USI: Universal Serial Interface
|
||||
const (
|
||||
// USIDR: USI Data Register
|
||||
USIDR_USIDR = 0xff // USI Data bits
|
||||
|
||||
// USISR: USI Status Register
|
||||
USISR_USISIF = 0x80 // Start Condition Interrupt Flag
|
||||
USISR_USIOIF = 0x40 // Counter Overflow Interrupt Flag
|
||||
USISR_USIPF = 0x20 // Stop Condition Flag
|
||||
USISR_USIDC = 0x10 // Data Output Collision
|
||||
USISR_USICNT = 0xf // USI Counter Value Bits
|
||||
|
||||
// USICR: USI Control Register
|
||||
USICR_USISIE = 0x80 // Start Condition Interrupt Enable
|
||||
USICR_USIOIE = 0x40 // Counter Overflow Interrupt Enable
|
||||
USICR_USIWM = 0x30 // USI Wire Mode Bits
|
||||
USICR_USICS = 0xc // USI Clock Source Select Bits
|
||||
USICR_USICLK = 0x2 // Clock Strobe
|
||||
USICR_USITC = 0x1 // Toggle Clock Port Pin
|
||||
)
|
||||
|
||||
// Bitfields for ADC: Analog-to-Digital Converter
|
||||
const (
|
||||
// ADMUX: The ADC multiplexer Selection Register
|
||||
ADMUX_REFS = 0xc0 // Reference Selection Bits
|
||||
ADMUX_ADLAR = 0x20 // Left Adjust Result
|
||||
ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits
|
||||
|
||||
// ADCSRA: The ADC Control and Status register
|
||||
ADCSRA_ADEN = 0x80 // ADC Enable
|
||||
ADCSRA_ADSC = 0x40 // ADC Start Conversion
|
||||
ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable
|
||||
ADCSRA_ADIF = 0x10 // ADC Interrupt Flag
|
||||
ADCSRA_ADIE = 0x8 // ADC Interrupt Enable
|
||||
ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits
|
||||
|
||||
// ADCL: ADC Data Register Bytes
|
||||
|
||||
// ADCH: ADC Data Register Bytes
|
||||
ADC_ADC = 0x3ff // ADC Data Bits
|
||||
|
||||
// DIDR0: Digital Input Disable Register 0
|
||||
DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable
|
||||
DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable
|
||||
DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable
|
||||
DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable
|
||||
DIDR0_ADC3D = 0x8 // ADC3 Digital input Disable
|
||||
DIDR0_ADC2D = 0x4 // ADC2 Digital input Disable
|
||||
DIDR0_ADC1D = 0x2 // ADC1 Digital input Disable
|
||||
DIDR0_ADC0D = 0x1 // ADC0 Digital input Disable
|
||||
)
|
||||
|
||||
// Bitfields for BOOT_LOAD: Bootloader
|
||||
const (
|
||||
// SPMCSR: Store Program Memory Control Register
|
||||
SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable
|
||||
SPMCSR_RWWSB = 0x40 // Read While Write Section Busy
|
||||
SPMCSR_RWWSRE = 0x10 // Read While Write section read enable
|
||||
SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set
|
||||
SPMCSR_PGWRT = 0x4 // Page Write
|
||||
SPMCSR_PGERS = 0x2 // Page Erase
|
||||
SPMCSR_SPMEN = 0x1 // Store Program Memory Enable
|
||||
)
|
||||
|
||||
// Bitfields for USART: USART
|
||||
const (
|
||||
// UDR0: USART I/O Data Register
|
||||
UDR0_UDR0 = 0xff // USART I/O Data bits
|
||||
|
||||
// UCSR0A: USART Control and Status Register A
|
||||
UCSR0A_RXC0 = 0x80 // USART Receive Complete
|
||||
UCSR0A_TXC0 = 0x40 // USART Transmit Complete
|
||||
UCSR0A_UDRE0 = 0x20 // USART Data Register Empty
|
||||
UCSR0A_FE0 = 0x10 // Framing Error
|
||||
UCSR0A_DOR0 = 0x8 // Data OverRun
|
||||
UCSR0A_UPE0 = 0x4 // USART Parity Error
|
||||
UCSR0A_U2X0 = 0x2 // Double the USART Transmission Speed
|
||||
UCSR0A_MPCM0 = 0x1 // Multi-processor Communication Mode
|
||||
|
||||
// UCSR0B: USART Control and Status Register B
|
||||
UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable
|
||||
UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable
|
||||
UCSR0B_UDRIE0 = 0x20 // USART Data Register Empty Interrupt Enable
|
||||
UCSR0B_RXEN0 = 0x10 // Receiver Enable
|
||||
UCSR0B_TXEN0 = 0x8 // Transmitter Enable
|
||||
UCSR0B_UCSZ02 = 0x4 // Character Size
|
||||
UCSR0B_RXB80 = 0x2 // Receive Data Bit 8
|
||||
UCSR0B_TXB80 = 0x1 // Transmit Data Bit 8
|
||||
|
||||
// UCSR0C: USART Control and Status Register C
|
||||
UCSR0C_UMSEL0 = 0x40 // USART Mode Select
|
||||
UCSR0C_UPM0 = 0x30 // Parity Mode Bits
|
||||
UCSR0C_USBS0 = 0x8 // Stop Bit Select
|
||||
UCSR0C_UCSZ0 = 0x6 // Character Size
|
||||
UCSR0C_UCPOL0 = 0x1 // Clock Polarity
|
||||
|
||||
// UBRR0L: USART Baud Rate Register Bytes
|
||||
|
||||
// UBRR0H: USART Baud Rate Register Bytes
|
||||
UBRR0_UBRR0 = 0xfff // USART Baud Rate bits
|
||||
)
|
||||
|
||||
// Bitfields for EXINT: External Interrupts
|
||||
const (
|
||||
// EICRA: External Interrupt Control Register
|
||||
EICRA_ISC01 = 0x2 // External Interrupt Sense Control 0 Bit 1
|
||||
EICRA_ISC00 = 0x1 // External Interrupt Sense Control 0 Bit 0
|
||||
|
||||
// EIMSK: External Interrupt Mask Register
|
||||
EIMSK_PCIE = 0x30 // Pin Change Interrupt Enables
|
||||
EIMSK_INT0 = 0x1 // External Interrupt Request 0 Enable
|
||||
|
||||
// EIFR: External Interrupt Flag Register
|
||||
EIFR_PCIF = 0x30 // Pin Change Interrupt Flags
|
||||
EIFR_INTF0 = 0x1 // External Interrupt Flag 0
|
||||
|
||||
// PCMSK1: Pin Change Mask Register 1
|
||||
PCMSK1_PCINT = 0xff // Pin Change Enable Masks
|
||||
|
||||
// PCMSK0: Pin Change Mask Register 0
|
||||
PCMSK0_PCINT = 0xff // Pin Change Enable Masks
|
||||
)
|
||||
|
||||
// Bitfields for CPU: CPU Registers
|
||||
const (
|
||||
// SREG: Status Register
|
||||
SREG_I = 0x80 // Global Interrupt Enable
|
||||
SREG_T = 0x40 // Bit Copy Storage
|
||||
SREG_H = 0x20 // Half Carry Flag
|
||||
SREG_S = 0x10 // Sign Bit
|
||||
SREG_V = 0x8 // Two's Complement Overflow Flag
|
||||
SREG_N = 0x4 // Negative Flag
|
||||
SREG_Z = 0x2 // Zero Flag
|
||||
SREG_C = 0x1 // Carry Flag
|
||||
|
||||
// OSCCAL: Oscillator Calibration Value
|
||||
OSCCAL_OSCCAL = 0xff // Oscillator Calibration
|
||||
|
||||
// CLKPR: Clock Prescale Register
|
||||
CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable
|
||||
CLKPR_CLKPS = 0xf // Clock Prescaler Select Bits
|
||||
|
||||
// PRR: Power Reduction Register
|
||||
PRR_PRLCD = 0x10 // Power Reduction LCD
|
||||
PRR_PRTIM1 = 0x8 // Power Reduction Timer/Counter1
|
||||
PRR_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface
|
||||
PRR_PRUSART0 = 0x2 // Power Reduction USART
|
||||
PRR_PRADC = 0x1 // Power Reduction ADC
|
||||
|
||||
// SMCR: Sleep Mode Control Register
|
||||
SMCR_SM = 0xe // Sleep Mode Select bits
|
||||
SMCR_SE = 0x1 // Sleep Enable
|
||||
|
||||
// GPIOR2: General Purpose IO Register 2
|
||||
GPIOR2_GPIOR2 = 0xff // General Purpose Bits
|
||||
|
||||
// GPIOR1: General Purpose IO Register 1
|
||||
GPIOR1_GPIOR1 = 0xff // General Purpose Bits
|
||||
|
||||
// GPIOR0: General Purpose IO Register 0
|
||||
GPIOR0_GPIOR0 = 0xff // General Purpose Bits
|
||||
)
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from ATmega169PA.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x4000;
|
||||
__ram_size = 0x400;
|
||||
__num_isrs = 23;
|
||||
|
|
@ -1,553 +0,0 @@
|
|||
// Automatically generated file. DO NOT EDIT.
|
||||
// Generated by gen-device.py from ATmega16A.atdf, see http://packs.download.atmel.com/
|
||||
|
||||
// +build avr,atmega16a
|
||||
|
||||
// Device information for the ATmega16A.
|
||||
//
|
||||
package avr
|
||||
|
||||
// Magic type name for the compiler.
|
||||
type __reg uint8
|
||||
|
||||
// Export this magic type name.
|
||||
type RegValue = __reg
|
||||
|
||||
// Some information about this device.
|
||||
const (
|
||||
DEVICE = "ATmega16A"
|
||||
ARCH = "AVR8"
|
||||
FAMILY = "megaAVR"
|
||||
)
|
||||
|
||||
// Interrupts
|
||||
const (
|
||||
IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset
|
||||
IRQ_INT0 = 1 // External Interrupt Request 0
|
||||
IRQ_INT1 = 2 // External Interrupt Request 1
|
||||
IRQ_TIMER2_COMP = 3 // Timer/Counter2 Compare Match
|
||||
IRQ_TIMER2_OVF = 4 // Timer/Counter2 Overflow
|
||||
IRQ_TIMER1_CAPT = 5 // Timer/Counter1 Capture Event
|
||||
IRQ_TIMER1_COMPA = 6 // Timer/Counter1 Compare Match A
|
||||
IRQ_TIMER1_COMPB = 7 // Timer/Counter1 Compare Match B
|
||||
IRQ_TIMER1_OVF = 8 // Timer/Counter1 Overflow
|
||||
IRQ_TIMER0_OVF = 9 // Timer/Counter0 Overflow
|
||||
IRQ_SPI_STC = 10 // Serial Transfer Complete
|
||||
IRQ_USART_RXC = 11 // USART, Rx Complete
|
||||
IRQ_USART_UDRE = 12 // USART Data Register Empty
|
||||
IRQ_USART_TXC = 13 // USART, Tx Complete
|
||||
IRQ_ADC = 14 // ADC Conversion Complete
|
||||
IRQ_EE_RDY = 15 // EEPROM Ready
|
||||
IRQ_ANA_COMP = 16 // Analog Comparator
|
||||
IRQ_TWI = 17 // 2-wire Serial Interface
|
||||
IRQ_INT2 = 18 // External Interrupt Request 2
|
||||
IRQ_TIMER0_COMP = 19 // Timer/Counter0 Compare Match
|
||||
IRQ_SPM_RDY = 20 // Store Program Memory Ready
|
||||
IRQ_max = 20 // Highest interrupt number on this device.
|
||||
)
|
||||
|
||||
// Peripherals
|
||||
var (
|
||||
// Fuses
|
||||
FUSE = struct {
|
||||
HIGH __reg
|
||||
LOW __reg
|
||||
}{
|
||||
HIGH: 0x1,
|
||||
LOW: 0x0,
|
||||
}
|
||||
|
||||
// Lockbits
|
||||
LOCKBIT = struct {
|
||||
LOCKBIT __reg
|
||||
}{
|
||||
LOCKBIT: 0x0,
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit
|
||||
TC8 = struct {
|
||||
TCCR0 __reg
|
||||
TCNT0 __reg
|
||||
OCR0 __reg
|
||||
}{
|
||||
TCCR0: 0x53, // Timer/Counter Control Register
|
||||
TCNT0: 0x52, // Timer/Counter 0 Register
|
||||
OCR0: 0x5c, // Output Compare 0 Register
|
||||
}
|
||||
|
||||
// Timer/Counter, 16-bit
|
||||
TC16 = struct {
|
||||
TCCR1A __reg
|
||||
TCCR1B __reg
|
||||
TCNT1L __reg
|
||||
TCNT1H __reg
|
||||
OCR1AL __reg
|
||||
OCR1AH __reg
|
||||
OCR1BL __reg
|
||||
OCR1BH __reg
|
||||
ICR1L __reg
|
||||
ICR1H __reg
|
||||
}{
|
||||
TCCR1A: 0x4f, // Timer/Counter1 Control Register A
|
||||
TCCR1B: 0x4e, // Timer/Counter1 Control Register B
|
||||
TCNT1L: 0x4c, // Timer/Counter1 Bytes
|
||||
TCNT1H: 0x4c, // Timer/Counter1 Bytes
|
||||
OCR1AL: 0x4a, // Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1AH: 0x4a, // Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1BL: 0x48, // Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1BH: 0x48, // Timer/Counter1 Output Compare Register Bytes
|
||||
ICR1L: 0x46, // Timer/Counter1 Input Capture Register Bytes
|
||||
ICR1H: 0x46, // Timer/Counter1 Input Capture Register Bytes
|
||||
}
|
||||
|
||||
// External Interrupts
|
||||
EXINT = struct {
|
||||
GICR __reg
|
||||
GIFR __reg
|
||||
}{
|
||||
GICR: 0x5b, // General Interrupt Control Register
|
||||
GIFR: 0x5a, // General Interrupt Flag Register
|
||||
}
|
||||
|
||||
// EEPROM
|
||||
EEPROM = struct {
|
||||
EEARL __reg
|
||||
EEARH __reg
|
||||
EEDR __reg
|
||||
EECR __reg
|
||||
}{
|
||||
EEARL: 0x3e, // EEPROM Address Register Bytes
|
||||
EEARH: 0x3e, // EEPROM Address Register Bytes
|
||||
EEDR: 0x3d, // EEPROM Data Register
|
||||
EECR: 0x3c, // EEPROM Control Register
|
||||
}
|
||||
|
||||
// CPU Registers
|
||||
CPU = struct {
|
||||
SREG __reg
|
||||
SPL __reg
|
||||
SPH __reg
|
||||
OSCCAL __reg
|
||||
}{
|
||||
SREG: 0x5f, // Status Register
|
||||
SPL: 0x5d, // Stack Pointer
|
||||
SPH: 0x5d, // Stack Pointer
|
||||
OSCCAL: 0x51, // Oscillator Calibration Value
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit Async
|
||||
TC8_ASYNC = struct {
|
||||
TCCR2 __reg
|
||||
TCNT2 __reg
|
||||
OCR2 __reg
|
||||
ASSR __reg
|
||||
}{
|
||||
TCCR2: 0x45, // Timer/Counter2 Control Register
|
||||
TCNT2: 0x44, // Timer/Counter2
|
||||
OCR2: 0x43, // Timer/Counter2 Output Compare Register
|
||||
ASSR: 0x42, // Asynchronous Status Register
|
||||
}
|
||||
|
||||
// Serial Peripheral Interface
|
||||
SPI = struct {
|
||||
SPDR __reg
|
||||
SPSR __reg
|
||||
SPCR __reg
|
||||
}{
|
||||
SPDR: 0x2f, // SPI Data Register
|
||||
SPSR: 0x2e, // SPI Status Register
|
||||
SPCR: 0x2d, // SPI Control Register
|
||||
}
|
||||
|
||||
// USART
|
||||
USART = struct {
|
||||
UDR __reg
|
||||
UCSRA __reg
|
||||
UCSRB __reg
|
||||
UCSRC __reg
|
||||
UBRRL __reg
|
||||
UBRRH __reg
|
||||
}{
|
||||
UDR: 0x2c, // USART I/O Data Register
|
||||
UCSRA: 0x2b, // USART Control and Status Register A
|
||||
UCSRB: 0x2a, // USART Control and Status Register B
|
||||
UCSRC: 0x40, // USART Control and Status Register C
|
||||
UBRRL: 0x3f, // USART Baud Rate Register
|
||||
UBRRH: 0x3f, // USART Baud Rate Register
|
||||
}
|
||||
|
||||
// Two Wire Serial Interface
|
||||
TWI = struct {
|
||||
TWBR __reg
|
||||
TWCR __reg
|
||||
TWSR __reg
|
||||
TWDR __reg
|
||||
TWAR __reg
|
||||
}{
|
||||
TWBR: 0x20, // TWI Bit Rate register
|
||||
TWCR: 0x56, // TWI Control Register
|
||||
TWSR: 0x21, // TWI Status Register
|
||||
TWDR: 0x23, // TWI Data register
|
||||
TWAR: 0x22, // TWI (Slave) Address register
|
||||
}
|
||||
|
||||
// Analog Comparator
|
||||
AC = struct {
|
||||
ACSR __reg
|
||||
}{
|
||||
ACSR: 0x28, // Analog Comparator Control And Status Register
|
||||
}
|
||||
|
||||
// Analog-to-Digital Converter
|
||||
ADC = struct {
|
||||
ADMUX __reg
|
||||
ADCSRA __reg
|
||||
ADCL __reg
|
||||
ADCH __reg
|
||||
}{
|
||||
ADMUX: 0x27, // The ADC multiplexer Selection Register
|
||||
ADCSRA: 0x26, // The ADC Control and Status register
|
||||
ADCL: 0x24, // ADC Data Register Bytes
|
||||
ADCH: 0x24, // ADC Data Register Bytes
|
||||
}
|
||||
|
||||
// JTAG Interface
|
||||
JTAG = struct {
|
||||
OCDR __reg
|
||||
}{
|
||||
OCDR: 0x51, // On-Chip Debug Related Register in I/O Memory
|
||||
}
|
||||
|
||||
// Bootloader
|
||||
BOOT_LOAD = struct {
|
||||
SPMCSR __reg
|
||||
}{
|
||||
SPMCSR: 0x57, // Store Program Memory Control Register
|
||||
}
|
||||
|
||||
// I/O Port
|
||||
PORT = struct {
|
||||
PORTA __reg
|
||||
DDRA __reg
|
||||
PINA __reg
|
||||
PORTB __reg
|
||||
DDRB __reg
|
||||
PINB __reg
|
||||
PORTC __reg
|
||||
DDRC __reg
|
||||
PINC __reg
|
||||
PORTD __reg
|
||||
DDRD __reg
|
||||
PIND __reg
|
||||
}{
|
||||
PORTA: 0x3b, // Port A Data Register
|
||||
DDRA: 0x3a, // Port A Data Direction Register
|
||||
PINA: 0x39, // Port A Input Pins
|
||||
PORTB: 0x38, // Port B Data Register
|
||||
DDRB: 0x37, // Port B Data Direction Register
|
||||
PINB: 0x36, // Port B Input Pins
|
||||
PORTC: 0x35, // Port C Data Register
|
||||
DDRC: 0x34, // Port C Data Direction Register
|
||||
PINC: 0x33, // Port C Input Pins
|
||||
PORTD: 0x32, // Port D Data Register
|
||||
DDRD: 0x31, // Port D Data Direction Register
|
||||
PIND: 0x30, // Port D Input Pins
|
||||
}
|
||||
|
||||
// Watchdog Timer
|
||||
WDT = struct {
|
||||
WDTCR __reg
|
||||
}{
|
||||
WDTCR: 0x41, // Watchdog Timer Control Register
|
||||
}
|
||||
)
|
||||
|
||||
// Bitfields for FUSE: Fuses
|
||||
const (
|
||||
// HIGH
|
||||
HIGH_OCDEN = 0x80 // On-Chip Debug Enabled
|
||||
HIGH_JTAGEN = 0x40 // JTAG Interface Enabled
|
||||
HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled
|
||||
HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle
|
||||
HIGH_BOOTSZ = 0x6 // Select Boot Size
|
||||
HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled
|
||||
HIGH_CKOPT = 0x10 // CKOPT fuse (operation dependent of CKSEL fuses)
|
||||
|
||||
// LOW
|
||||
LOW_BODLEVEL = 0x80 // Brownout detector trigger level
|
||||
LOW_BODEN = 0x40 // Brown-out detection enabled
|
||||
LOW_SUT_CKSEL = 0x3f // Select Clock Source
|
||||
)
|
||||
|
||||
// Bitfields for LOCKBIT: Lockbits
|
||||
const (
|
||||
// LOCKBIT
|
||||
LOCKBIT_LB = 0x3 // Memory Lock
|
||||
LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode
|
||||
LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode
|
||||
)
|
||||
|
||||
// Bitfields for TC8: Timer/Counter, 8-bit
|
||||
const (
|
||||
// TCCR0: Timer/Counter Control Register
|
||||
TCCR0_FOC0 = 0x80 // Force Output Compare
|
||||
TCCR0_WGM00 = 0x40 // Waveform Generation Mode 0
|
||||
TCCR0_COM0 = 0x30 // Compare Match Output Modes
|
||||
TCCR0_WGM01 = 0x8 // Waveform Generation Mode 1
|
||||
TCCR0_CS0 = 0x7 // Clock Selects
|
||||
|
||||
// TCNT0: Timer/Counter 0 Register
|
||||
TCNT0_TCNT0 = 0xff // Timer/Counter 0 bits
|
||||
|
||||
// OCR0: Output Compare 0 Register
|
||||
OCR0_OCR0 = 0xff // Output Compare bits
|
||||
)
|
||||
|
||||
// Bitfields for TC16: Timer/Counter, 16-bit
|
||||
const (
|
||||
// TCCR1A: Timer/Counter1 Control Register A
|
||||
TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits
|
||||
TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits
|
||||
TCCR1A_FOC1A = 0x8 // Force Output Compare 1A
|
||||
TCCR1A_FOC1B = 0x4 // Force Output Compare 1B
|
||||
TCCR1A_WGM1 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TCCR1B: Timer/Counter1 Control Register B
|
||||
TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler
|
||||
TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select
|
||||
TCCR1B_WGM1 = 0x18 // Waveform Generation Mode
|
||||
TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1
|
||||
|
||||
// TCNT1L: Timer/Counter1 Bytes
|
||||
|
||||
// TCNT1H: Timer/Counter1 Bytes
|
||||
TCNT1_TCNT1 = 0xffff // Timer/Counter1 bits
|
||||
|
||||
// OCR1AL: Timer/Counter1 Output Compare Register Bytes
|
||||
|
||||
// OCR1AH: Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1A_OCR1A = 0xffff // Timer/Counter1 Output Compare A bits
|
||||
|
||||
// OCR1BL: Timer/Counter1 Output Compare Register Bytes
|
||||
|
||||
// OCR1BH: Timer/Counter1 Output Compare Register Bytes
|
||||
OCR1B_OCR1B = 0xffff // Timer/Counter1 Output Compare B bits
|
||||
|
||||
// ICR1L: Timer/Counter1 Input Capture Register Bytes
|
||||
|
||||
// ICR1H: Timer/Counter1 Input Capture Register Bytes
|
||||
ICR1_ICR1 = 0xffff // Timer/Counter1 Input Capture bits
|
||||
)
|
||||
|
||||
// Bitfields for EXINT: External Interrupts
|
||||
const (
|
||||
// GICR: General Interrupt Control Register
|
||||
GICR_INT0 = 0x40 // External Interrupt Request 0 Enable
|
||||
GICR_INT1 = 0x80 // External Interrupt Request 1 Enable
|
||||
GICR_INT2 = 0x20 // External Interrupt Request 2 Enable
|
||||
GICR_IVSEL = 0x2 // Interrupt Vector Select
|
||||
GICR_IVCE = 0x1 // Interrupt Vector Change Enable
|
||||
|
||||
// GIFR: General Interrupt Flag Register
|
||||
GIFR_INTF = 0xc0 // External Interrupt Flags
|
||||
GIFR_INTF2 = 0x20 // External Interrupt Flag 2
|
||||
)
|
||||
|
||||
// Bitfields for EEPROM: EEPROM
|
||||
const (
|
||||
// EEARL: EEPROM Address Register Bytes
|
||||
|
||||
// EEARH: EEPROM Address Register Bytes
|
||||
EEAR_EEAR = 0x1ff // EEPROM Address bits
|
||||
|
||||
// EEDR: EEPROM Data Register
|
||||
EEDR_EEDR = 0xff // EEPROM Data bits
|
||||
|
||||
// EECR: EEPROM Control Register
|
||||
EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable
|
||||
EECR_EEMWE = 0x4 // EEPROM Master Write Enable
|
||||
EECR_EEWE = 0x2 // EEPROM Write Enable
|
||||
EECR_EERE = 0x1 // EEPROM Read Enable
|
||||
)
|
||||
|
||||
// Bitfields for CPU: CPU Registers
|
||||
const (
|
||||
// SREG: Status Register
|
||||
SREG_I = 0x80 // Global Interrupt Enable
|
||||
SREG_T = 0x40 // Bit Copy Storage
|
||||
SREG_H = 0x20 // Half Carry Flag
|
||||
SREG_S = 0x10 // Sign Bit
|
||||
SREG_V = 0x8 // Two's Complement Overflow Flag
|
||||
SREG_N = 0x4 // Negative Flag
|
||||
SREG_Z = 0x2 // Zero Flag
|
||||
SREG_C = 0x1 // Carry Flag
|
||||
|
||||
// OSCCAL: Oscillator Calibration Value
|
||||
OSCCAL_OSCCAL = 0xff // Oscillator Calibration
|
||||
)
|
||||
|
||||
// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async
|
||||
const (
|
||||
// TCCR2: Timer/Counter2 Control Register
|
||||
TCCR2_FOC2 = 0x80 // Force Output Compare
|
||||
TCCR2_WGM20 = 0x40 // Waveform Genration Mode
|
||||
TCCR2_COM2 = 0x30 // Compare Output Mode bits
|
||||
TCCR2_WGM21 = 0x8 // Waveform Generation Mode
|
||||
TCCR2_CS2 = 0x7 // Clock Select bits
|
||||
|
||||
// TCNT2: Timer/Counter2
|
||||
TCNT2_TCNT2 = 0xff // Timer/Counter2
|
||||
|
||||
// OCR2: Timer/Counter2 Output Compare Register
|
||||
OCR2_OCR2 = 0xff // Timer/Counter2 Output Compare bits
|
||||
|
||||
// ASSR: Asynchronous Status Register
|
||||
ASSR_AS2 = 0x8 // Asynchronous Timer/counter2
|
||||
ASSR_TCN2UB = 0x4 // Timer/Counter2 Update Busy
|
||||
ASSR_OCR2UB = 0x2 // Output Compare Register2 Update Busy
|
||||
ASSR_TCR2UB = 0x1 // Timer/counter Control Register2 Update Busy
|
||||
)
|
||||
|
||||
// Bitfields for SPI: Serial Peripheral Interface
|
||||
const (
|
||||
// SPDR: SPI Data Register
|
||||
SPDR_SPDR = 0xff // SPI Data bits
|
||||
|
||||
// SPSR: SPI Status Register
|
||||
SPSR_SPIF = 0x80 // SPI Interrupt Flag
|
||||
SPSR_WCOL = 0x40 // Write Collision Flag
|
||||
SPSR_SPI2X = 0x1 // Double SPI Speed Bit
|
||||
|
||||
// SPCR: SPI Control Register
|
||||
SPCR_SPIE = 0x80 // SPI Interrupt Enable
|
||||
SPCR_SPE = 0x40 // SPI Enable
|
||||
SPCR_DORD = 0x20 // Data Order
|
||||
SPCR_MSTR = 0x10 // Master/Slave Select
|
||||
SPCR_CPOL = 0x8 // Clock polarity
|
||||
SPCR_CPHA = 0x4 // Clock Phase
|
||||
SPCR_SPR = 0x3 // SPI Clock Rate Selects
|
||||
)
|
||||
|
||||
// Bitfields for USART: USART
|
||||
const (
|
||||
// UDR: USART I/O Data Register
|
||||
UDR_UDR = 0xff // USART I/O Data bits
|
||||
|
||||
// UCSRA: USART Control and Status Register A
|
||||
UCSRA_RXC = 0x80 // USART Receive Complete
|
||||
UCSRA_TXC = 0x40 // USART Transmitt Complete
|
||||
UCSRA_UDRE = 0x20 // USART Data Register Empty
|
||||
UCSRA_FE = 0x10 // Framing Error
|
||||
UCSRA_DOR = 0x8 // Data overRun
|
||||
UCSRA_UPE = 0x4 // Parity Error
|
||||
UCSRA_U2X = 0x2 // Double the USART transmission speed
|
||||
UCSRA_MPCM = 0x1 // Multi-processor Communication Mode
|
||||
|
||||
// UCSRB: USART Control and Status Register B
|
||||
UCSRB_RXCIE = 0x80 // RX Complete Interrupt Enable
|
||||
UCSRB_TXCIE = 0x40 // TX Complete Interrupt Enable
|
||||
UCSRB_UDRIE = 0x20 // USART Data register Empty Interrupt Enable
|
||||
UCSRB_RXEN = 0x10 // Receiver Enable
|
||||
UCSRB_TXEN = 0x8 // Transmitter Enable
|
||||
UCSRB_UCSZ2 = 0x4 // Character Size
|
||||
UCSRB_RXB8 = 0x2 // Receive Data Bit 8
|
||||
UCSRB_TXB8 = 0x1 // Transmit Data Bit 8
|
||||
|
||||
// UCSRC: USART Control and Status Register C
|
||||
UCSRC_URSEL = 0x80 // Register Select
|
||||
UCSRC_UMSEL = 0x40 // USART Mode Select
|
||||
UCSRC_UPM = 0x30 // Parity Mode Bits
|
||||
UCSRC_USBS = 0x8 // Stop Bit Select
|
||||
UCSRC_UCSZ = 0x6 // Character Size
|
||||
UCSRC_UCPOL = 0x1 // Clock Polarity
|
||||
|
||||
// UBRRL: USART Baud Rate Register
|
||||
|
||||
// UBRRH: USART Baud Rate Register
|
||||
UBRR_UBRR = 0xfff // USART Baud Rate bits
|
||||
)
|
||||
|
||||
// Bitfields for TWI: Two Wire Serial Interface
|
||||
const (
|
||||
// TWBR: TWI Bit Rate register
|
||||
TWBR_TWBR = 0xff // TWI Bit Rate bits
|
||||
|
||||
// TWCR: TWI Control Register
|
||||
TWCR_TWINT = 0x80 // TWI Interrupt Flag
|
||||
TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit
|
||||
TWCR_TWSTA = 0x20 // TWI Start Condition Bit
|
||||
TWCR_TWSTO = 0x10 // TWI Stop Condition Bit
|
||||
TWCR_TWWC = 0x8 // TWI Write Collition Flag
|
||||
TWCR_TWEN = 0x4 // TWI Enable Bit
|
||||
TWCR_TWIE = 0x1 // TWI Interrupt Enable
|
||||
|
||||
// TWSR: TWI Status Register
|
||||
TWSR_TWS = 0xf8 // TWI Status
|
||||
TWSR_TWPS = 0x3 // TWI Prescaler
|
||||
|
||||
// TWDR: TWI Data register
|
||||
TWDR_TWD = 0xff // TWI Data bits
|
||||
|
||||
// TWAR: TWI (Slave) Address register
|
||||
TWAR_TWA = 0xfe // TWI (Slave) Address register Bits
|
||||
TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit
|
||||
)
|
||||
|
||||
// Bitfields for AC: Analog Comparator
|
||||
const (
|
||||
// ACSR: Analog Comparator Control And Status Register
|
||||
ACSR_ACD = 0x80 // Analog Comparator Disable
|
||||
ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select
|
||||
ACSR_ACO = 0x20 // Analog Compare Output
|
||||
ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag
|
||||
ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable
|
||||
ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable
|
||||
ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits
|
||||
)
|
||||
|
||||
// Bitfields for ADC: Analog-to-Digital Converter
|
||||
const (
|
||||
// ADMUX: The ADC multiplexer Selection Register
|
||||
ADMUX_REFS = 0xc0 // Reference Selection Bits
|
||||
ADMUX_ADLAR = 0x20 // Left Adjust Result
|
||||
ADMUX_MUX = 0x1f // Analog Channel and Gain Selection Bits
|
||||
|
||||
// ADCSRA: The ADC Control and Status register
|
||||
ADCSRA_ADEN = 0x80 // ADC Enable
|
||||
ADCSRA_ADSC = 0x40 // ADC Start Conversion
|
||||
ADCSRA_ADATE = 0x20 // ADC Auto Trigger
|
||||
ADCSRA_ADIF = 0x10 // ADC Interrupt Flag
|
||||
ADCSRA_ADIE = 0x8 // ADC Interrupt Enable
|
||||
ADCSRA_ADPS = 0x7 // ADC Prescaler Select Bits
|
||||
|
||||
// ADCL: ADC Data Register Bytes
|
||||
|
||||
// ADCH: ADC Data Register Bytes
|
||||
ADC_ADC = 0x3ff // ADC Data Bits
|
||||
)
|
||||
|
||||
// Bitfields for JTAG: JTAG Interface
|
||||
const (
|
||||
// OCDR: On-Chip Debug Related Register in I/O Memory
|
||||
OCDR_OCDR = 0xff // On-Chip Debug Register Bits
|
||||
)
|
||||
|
||||
// Bitfields for BOOT_LOAD: Bootloader
|
||||
const (
|
||||
// SPMCSR: Store Program Memory Control Register
|
||||
SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable
|
||||
SPMCSR_RWWSB = 0x40 // Read While Write Section Busy
|
||||
SPMCSR_RWWSRE = 0x10 // Read While Write section read enable
|
||||
SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set
|
||||
SPMCSR_PGWRT = 0x4 // Page Write
|
||||
SPMCSR_PGERS = 0x2 // Page Erase
|
||||
SPMCSR_SPMEN = 0x1 // Store Program Memory Enable
|
||||
)
|
||||
|
||||
// Bitfields for WDT: Watchdog Timer
|
||||
const (
|
||||
// WDTCR: Watchdog Timer Control Register
|
||||
WDTCR_WDTOE = 0x10 // RW
|
||||
WDTCR_WDE = 0x8 // Watch Dog Enable
|
||||
WDTCR_WDP = 0x7 // Watch Dog Timer Prescaler bits
|
||||
)
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from ATmega16A.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x4000;
|
||||
__ram_size = 0x400;
|
||||
__num_isrs = 21;
|
||||
|
|
@ -1,560 +0,0 @@
|
|||
// Automatically generated file. DO NOT EDIT.
|
||||
// Generated by gen-device.py from ATmega16HVA.atdf, see http://packs.download.atmel.com/
|
||||
|
||||
// +build avr,atmega16hva
|
||||
|
||||
// Device information for the ATmega16HVA.
|
||||
//
|
||||
package avr
|
||||
|
||||
// Magic type name for the compiler.
|
||||
type __reg uint8
|
||||
|
||||
// Export this magic type name.
|
||||
type RegValue = __reg
|
||||
|
||||
// Some information about this device.
|
||||
const (
|
||||
DEVICE = "ATmega16HVA"
|
||||
ARCH = "AVR8"
|
||||
FAMILY = "megaAVR"
|
||||
)
|
||||
|
||||
// Interrupts
|
||||
const (
|
||||
IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset
|
||||
IRQ_BPINT = 1 // Battery Protection Interrupt
|
||||
IRQ_VREGMON = 2 // Voltage regulator monitor interrupt
|
||||
IRQ_INT0 = 3 // External Interrupt Request 0
|
||||
IRQ_INT1 = 4 // External Interrupt Request 1
|
||||
IRQ_INT2 = 5 // External Interrupt Request 2
|
||||
IRQ_WDT = 6 // Watchdog Timeout Interrupt
|
||||
IRQ_TIMER1_IC = 7 // Timer 1 Input capture
|
||||
IRQ_TIMER1_COMPA = 8 // Timer 1 Compare Match A
|
||||
IRQ_TIMER1_COMPB = 9 // Timer 1 Compare Match B
|
||||
IRQ_TIMER1_OVF = 10 // Timer 1 overflow
|
||||
IRQ_TIMER0_IC = 11 // Timer 0 Input Capture
|
||||
IRQ_TIMER0_COMPA = 12 // Timer 0 Comapre Match A
|
||||
IRQ_TIMER0_COMPB = 13 // Timer 0 Compare Match B
|
||||
IRQ_TIMER0_OVF = 14 // Timer 0 Overflow
|
||||
IRQ_SPI_STC = 15 // SPI Serial transfer complete
|
||||
IRQ_VADC = 16 // Voltage ADC Conversion Complete
|
||||
IRQ_CCADC_CONV = 17 // Coulomb Counter ADC Conversion Complete
|
||||
IRQ_CCADC_REG_CUR = 18 // Coloumb Counter ADC Regular Current
|
||||
IRQ_CCADC_ACC = 19 // Coloumb Counter ADC Accumulator
|
||||
IRQ_EE_READY = 20 // EEPROM Ready
|
||||
IRQ_max = 20 // Highest interrupt number on this device.
|
||||
)
|
||||
|
||||
// Peripherals
|
||||
var (
|
||||
// Fuses
|
||||
FUSE = struct {
|
||||
LOW __reg
|
||||
}{
|
||||
LOW: 0x0,
|
||||
}
|
||||
|
||||
// Lockbits
|
||||
LOCKBIT = struct {
|
||||
LOCKBIT __reg
|
||||
}{
|
||||
LOCKBIT: 0x0,
|
||||
}
|
||||
|
||||
// Analog-to-Digital Converter
|
||||
ADC = struct {
|
||||
VADMUX __reg
|
||||
VADCL __reg
|
||||
VADCH __reg
|
||||
VADCSR __reg
|
||||
}{
|
||||
VADMUX: 0x7c, // The VADC multiplexer Selection Register
|
||||
VADCL: 0x78, // VADC Data Register Bytes
|
||||
VADCH: 0x78, // VADC Data Register Bytes
|
||||
VADCSR: 0x7a, // The VADC Control and Status register
|
||||
}
|
||||
|
||||
// Watchdog Timer
|
||||
WDT = struct {
|
||||
WDTCSR __reg
|
||||
}{
|
||||
WDTCSR: 0x60, // Watchdog Timer Control Register
|
||||
}
|
||||
|
||||
// Bandgap
|
||||
BANDGAP = struct {
|
||||
BGCRR __reg
|
||||
BGCCR __reg
|
||||
}{
|
||||
BGCRR: 0xd1, // Bandgap Calibration of Resistor Ladder
|
||||
BGCCR: 0xd0, // Bandgap Calibration Register
|
||||
}
|
||||
|
||||
// External Interrupts
|
||||
EXINT = struct {
|
||||
EICRA __reg
|
||||
EIMSK __reg
|
||||
EIFR __reg
|
||||
}{
|
||||
EICRA: 0x69, // External Interrupt Control Register
|
||||
EIMSK: 0x3d, // External Interrupt Mask Register
|
||||
EIFR: 0x3c, // External Interrupt Flag Register
|
||||
}
|
||||
|
||||
// I/O Port
|
||||
PORT = struct {
|
||||
PORTC __reg
|
||||
PINC __reg
|
||||
PORTA __reg
|
||||
DDRA __reg
|
||||
PINA __reg
|
||||
PORTB __reg
|
||||
DDRB __reg
|
||||
PINB __reg
|
||||
}{
|
||||
PORTC: 0x28, // Port C Data Register
|
||||
PINC: 0x26, // Port C Input Pins
|
||||
PORTA: 0x22, // Port A Data Register
|
||||
DDRA: 0x21, // Port A Data Direction Register
|
||||
PINA: 0x20, // Port A Input Pins
|
||||
PORTB: 0x25, // Data Register, Port B
|
||||
DDRB: 0x24, // Data Direction Register, Port B
|
||||
PINB: 0x23, // Input Pins, Port B
|
||||
}
|
||||
|
||||
// FET Control
|
||||
FET = struct {
|
||||
FCSR __reg
|
||||
}{
|
||||
FCSR: 0xf0, // FET Control and Status Register
|
||||
}
|
||||
|
||||
// Serial Peripheral Interface
|
||||
SPI = struct {
|
||||
SPCR __reg
|
||||
SPSR __reg
|
||||
SPDR __reg
|
||||
}{
|
||||
SPCR: 0x4c, // SPI Control Register
|
||||
SPSR: 0x4d, // SPI Status Register
|
||||
SPDR: 0x4e, // SPI Data Register
|
||||
}
|
||||
|
||||
// Bootloader
|
||||
BOOT_LOAD = struct {
|
||||
SPMCSR __reg
|
||||
}{
|
||||
SPMCSR: 0x57, // Store Program Memory Control and Status Register
|
||||
}
|
||||
|
||||
// CPU Registers
|
||||
CPU = struct {
|
||||
SREG __reg
|
||||
SPL __reg
|
||||
SPH __reg
|
||||
MCUCR __reg
|
||||
MCUSR __reg
|
||||
FOSCCAL __reg
|
||||
OSICSR __reg
|
||||
SMCR __reg
|
||||
GPIOR2 __reg
|
||||
GPIOR1 __reg
|
||||
GPIOR0 __reg
|
||||
DIDR0 __reg
|
||||
PRR0 __reg
|
||||
CLKPR __reg
|
||||
}{
|
||||
SREG: 0x5f, // Status Register
|
||||
SPL: 0x5d, // Stack Pointer
|
||||
SPH: 0x5d, // Stack Pointer
|
||||
MCUCR: 0x55, // MCU Control Register
|
||||
MCUSR: 0x54, // MCU Status Register
|
||||
FOSCCAL: 0x66, // Fast Oscillator Calibration Value
|
||||
OSICSR: 0x37, // Oscillator Sampling Interface Control and Status Register
|
||||
SMCR: 0x53, // Sleep Mode Control Register
|
||||
GPIOR2: 0x4b, // General Purpose IO Register 2
|
||||
GPIOR1: 0x4a, // General Purpose IO Register 1
|
||||
GPIOR0: 0x3e, // General Purpose IO Register 0
|
||||
DIDR0: 0x7e, // Digital Input Disable Register
|
||||
PRR0: 0x64, // Power Reduction Register 0
|
||||
CLKPR: 0x61, // Clock Prescale Register
|
||||
}
|
||||
|
||||
// Battery Protection
|
||||
BATTERY_PROTECTION = struct {
|
||||
BPPLR __reg
|
||||
BPCR __reg
|
||||
BPHCTR __reg
|
||||
BPOCTR __reg
|
||||
BPSCTR __reg
|
||||
BPCHCD __reg
|
||||
BPDHCD __reg
|
||||
BPCOCD __reg
|
||||
BPDOCD __reg
|
||||
BPSCD __reg
|
||||
BPIFR __reg
|
||||
BPIMSK __reg
|
||||
}{
|
||||
BPPLR: 0xfe, // Battery Protection Parameter Lock Register
|
||||
BPCR: 0xfd, // Battery Protection Control Register
|
||||
BPHCTR: 0xfc, // Battery Protection Short-current Timing Register
|
||||
BPOCTR: 0xfb, // Battery Protection Over-current Timing Register
|
||||
BPSCTR: 0xfa, // Battery Protection Short-current Timing Register
|
||||
BPCHCD: 0xf9, // Battery Protection Charge-High-current Detection Level Register
|
||||
BPDHCD: 0xf8, // Battery Protection Discharge-High-current Detection Level Register
|
||||
BPCOCD: 0xf7, // Battery Protection Charge-Over-current Detection Level Register
|
||||
BPDOCD: 0xf6, // Battery Protection Discharge-Over-current Detection Level Register
|
||||
BPSCD: 0xf5, // Battery Protection Short-Circuit Detection Level Register
|
||||
BPIFR: 0xf3, // Battery Protection Interrupt Flag Register
|
||||
BPIMSK: 0xf2, // Battery Protection Interrupt Mask Register
|
||||
}
|
||||
|
||||
// EEPROM
|
||||
EEPROM = struct {
|
||||
EEAR __reg
|
||||
EEDR __reg
|
||||
EECR __reg
|
||||
}{
|
||||
EEAR: 0x41, // EEPROM Read/Write Access
|
||||
EEDR: 0x40, // EEPROM Data Register
|
||||
EECR: 0x3f, // EEPROM Control Register
|
||||
}
|
||||
|
||||
// Timer/Counter, 16-bit
|
||||
TC16 = struct {
|
||||
TCCR1B __reg
|
||||
TCCR1A __reg
|
||||
TCNT1L __reg
|
||||
TCNT1H __reg
|
||||
OCR1A __reg
|
||||
OCR1B __reg
|
||||
TIMSK1 __reg
|
||||
TIFR1 __reg
|
||||
GTCCR __reg
|
||||
TCCR0A __reg
|
||||
TCCR0B __reg
|
||||
TCNT0L __reg
|
||||
TCNT0H __reg
|
||||
OCR0A __reg
|
||||
OCR0B __reg
|
||||
TIMSK0 __reg
|
||||
TIFR0 __reg
|
||||
}{
|
||||
TCCR1B: 0x81, // Timer/Counter1 Control Register B
|
||||
TCCR1A: 0x80, // Timer/Counter 1 Control Register A
|
||||
TCNT1L: 0x84, // Timer Counter 1 Bytes
|
||||
TCNT1H: 0x84, // Timer Counter 1 Bytes
|
||||
OCR1A: 0x88, // Output Compare Register 1A
|
||||
OCR1B: 0x89, // Output Compare Register B
|
||||
TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register
|
||||
TIFR1: 0x36, // Timer/Counter Interrupt Flag register
|
||||
GTCCR: 0x43, // General Timer/Counter Control Register
|
||||
TCCR0A: 0x44, // Timer/Counter0 Control Register
|
||||
TCCR0B: 0x45, // Timer/Counter0 Control Register
|
||||
TCNT0L: 0x46, // Timer Counter 0 Bytes
|
||||
TCNT0H: 0x46, // Timer Counter 0 Bytes
|
||||
OCR0A: 0x48, // Output compare Register A
|
||||
OCR0B: 0x49, // Output compare Register B
|
||||
TIMSK0: 0x6e, // Timer/Counter Interrupt Mask Register
|
||||
TIFR0: 0x35, // Timer/Counter Interrupt Flag register
|
||||
}
|
||||
|
||||
// Coulomb Counter
|
||||
COULOMB_COUNTER = struct {
|
||||
CADCSRA __reg
|
||||
CADCSRB __reg
|
||||
CADICL __reg
|
||||
CADICH __reg
|
||||
CADAC3 __reg
|
||||
CADAC2 __reg
|
||||
CADAC1 __reg
|
||||
CADAC0 __reg
|
||||
CADRC __reg
|
||||
}{
|
||||
CADCSRA: 0xe4, // CC-ADC Control and Status Register A
|
||||
CADCSRB: 0xe5, // CC-ADC Control and Status Register B
|
||||
CADICL: 0xe8, // CC-ADC Instantaneous Current
|
||||
CADICH: 0xe8, // CC-ADC Instantaneous Current
|
||||
CADAC3: 0xe3, // ADC Accumulate Current
|
||||
CADAC2: 0xe2, // ADC Accumulate Current
|
||||
CADAC1: 0xe1, // ADC Accumulate Current
|
||||
CADAC0: 0xe0, // ADC Accumulate Current
|
||||
CADRC: 0xe6, // CC-ADC Regular Current
|
||||
}
|
||||
|
||||
// Voltage Regulator
|
||||
VOLTAGE_REGULATOR = struct {
|
||||
ROCR __reg
|
||||
}{
|
||||
ROCR: 0xc8, // Regulator Operating Condition Register
|
||||
}
|
||||
)
|
||||
|
||||
// Bitfields for FUSE: Fuses
|
||||
const (
|
||||
// LOW
|
||||
LOW_WDTON = 0x80 // Watch-dog Timer always on
|
||||
LOW_EESAVE = 0x40 // Preserve EEPROM through the Chip Erase cycle
|
||||
LOW_SPIEN = 0x20 // Serial program downloading (SPI) enabled
|
||||
LOW_DWEN = 0x10 // Debug Wire enable
|
||||
LOW_SELFPRGEN = 0x8 // Self Programming enable
|
||||
LOW_SUT = 0x7 // Select start-up time
|
||||
)
|
||||
|
||||
// Bitfields for LOCKBIT: Lockbits
|
||||
const (
|
||||
// LOCKBIT
|
||||
LOCKBIT_LB = 0x3 // Memory Lock
|
||||
)
|
||||
|
||||
// Bitfields for ADC: Analog-to-Digital Converter
|
||||
const (
|
||||
// VADMUX: The VADC multiplexer Selection Register
|
||||
VADMUX_VADMUX = 0xf // Analog Channel and Gain Selection Bits
|
||||
|
||||
// VADCSR: The VADC Control and Status register
|
||||
VADCSR_VADEN = 0x8 // VADC Enable
|
||||
VADCSR_VADSC = 0x4 // VADC Satrt Conversion
|
||||
VADCSR_VADCCIF = 0x2 // VADC Conversion Complete Interrupt Flag
|
||||
VADCSR_VADCCIE = 0x1 // VADC Conversion Complete Interrupt Enable
|
||||
)
|
||||
|
||||
// Bitfields for WDT: Watchdog Timer
|
||||
const (
|
||||
// WDTCSR: Watchdog Timer Control Register
|
||||
WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag
|
||||
WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable
|
||||
WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits
|
||||
WDTCSR_WDCE = 0x10 // Watchdog Change Enable
|
||||
WDTCSR_WDE = 0x8 // Watch Dog Enable
|
||||
)
|
||||
|
||||
// Bitfields for BANDGAP: Bandgap
|
||||
const (
|
||||
// BGCRR: Bandgap Calibration of Resistor Ladder
|
||||
BGCRR_BGCR = 0xff // Bandgap calibration bits
|
||||
|
||||
// BGCCR: Bandgap Calibration Register
|
||||
BGCCR_BGD = 0x80 // Setting the BGD bit to one will disable the bandgap voltage reference. This bit must be cleared before enabling CC-ADC or V-ADC, and must remain unset while either ADC is enabled.
|
||||
BGCCR_BGCC = 0x3f // BG Calibration of PTAT Current Bits
|
||||
)
|
||||
|
||||
// Bitfields for EXINT: External Interrupts
|
||||
const (
|
||||
// EICRA: External Interrupt Control Register
|
||||
EICRA_ISC2 = 0x30 // External Interrupt Sense Control 2 Bits
|
||||
EICRA_ISC1 = 0xc // External Interrupt Sense Control 1 Bits
|
||||
EICRA_ISC0 = 0x3 // External Interrupt Sense Control 0 Bits
|
||||
|
||||
// EIMSK: External Interrupt Mask Register
|
||||
EIMSK_INT = 0x7 // External Interrupt Request 2 Enable
|
||||
|
||||
// EIFR: External Interrupt Flag Register
|
||||
EIFR_INTF = 0x7 // External Interrupt Flags
|
||||
)
|
||||
|
||||
// Bitfields for FET: FET Control
|
||||
const (
|
||||
// FCSR: FET Control and Status Register
|
||||
FCSR_DUVRD = 0x8 // Deep Under-Voltage Recovery Disable
|
||||
FCSR_CPS = 0x4 // Current Protection Status
|
||||
FCSR_DFE = 0x2 // Discharge FET Enable
|
||||
FCSR_CFE = 0x1 // Charge FET Enable
|
||||
)
|
||||
|
||||
// Bitfields for SPI: Serial Peripheral Interface
|
||||
const (
|
||||
// SPCR: SPI Control Register
|
||||
SPCR_SPIE = 0x80 // SPI Interrupt Enable
|
||||
SPCR_SPE = 0x40 // SPI Enable
|
||||
SPCR_DORD = 0x20 // Data Order
|
||||
SPCR_MSTR = 0x10 // Master/Slave Select
|
||||
SPCR_CPOL = 0x8 // Clock polarity
|
||||
SPCR_CPHA = 0x4 // Clock Phase
|
||||
SPCR_SPR = 0x3 // SPI Clock Rate Selects
|
||||
|
||||
// SPSR: SPI Status Register
|
||||
SPSR_SPIF = 0x80 // SPI Interrupt Flag
|
||||
SPSR_WCOL = 0x40 // Write Collision Flag
|
||||
SPSR_SPI2X = 0x1 // Double SPI Speed Bit
|
||||
)
|
||||
|
||||
// Bitfields for BOOT_LOAD: Bootloader
|
||||
const (
|
||||
// SPMCSR: Store Program Memory Control and Status Register
|
||||
SPMCSR_SIGRD = 0x20 // Signature Row Read
|
||||
SPMCSR_CTPB = 0x10 // Clear Temporary Page Buffer
|
||||
SPMCSR_RFLB = 0x8 // Read Fuse and Lock Bits
|
||||
SPMCSR_PGWRT = 0x4 // Page Write
|
||||
SPMCSR_PGERS = 0x2 // Page Erase
|
||||
SPMCSR_SPMEN = 0x1 // Store Program Memory Enable
|
||||
)
|
||||
|
||||
// Bitfields for CPU: CPU Registers
|
||||
const (
|
||||
// SREG: Status Register
|
||||
SREG_I = 0x80 // Global Interrupt Enable
|
||||
SREG_T = 0x40 // Bit Copy Storage
|
||||
SREG_H = 0x20 // Half Carry Flag
|
||||
SREG_S = 0x10 // Sign Bit
|
||||
SREG_V = 0x8 // Two's Complement Overflow Flag
|
||||
SREG_N = 0x4 // Negative Flag
|
||||
SREG_Z = 0x2 // Zero Flag
|
||||
SREG_C = 0x1 // Carry Flag
|
||||
|
||||
// MCUCR: MCU Control Register
|
||||
MCUCR_CKOE = 0x20 // Clock Output Enable
|
||||
MCUCR_PUD = 0x10 // Pull-up disable
|
||||
|
||||
// MCUSR: MCU Status Register
|
||||
MCUSR_OCDRF = 0x10 // OCD Reset Flag
|
||||
MCUSR_WDRF = 0x8 // Watchdog Reset Flag
|
||||
MCUSR_BODRF = 0x4 // Brown-out Reset Flag
|
||||
MCUSR_EXTRF = 0x2 // External Reset Flag
|
||||
MCUSR_PORF = 0x1 // Power-on reset flag
|
||||
|
||||
// OSICSR: Oscillator Sampling Interface Control and Status Register
|
||||
OSICSR_OSISEL0 = 0x10 // Oscillator Sampling Interface Select 0
|
||||
OSICSR_OSIST = 0x2 // Oscillator Sampling Interface Status
|
||||
OSICSR_OSIEN = 0x1 // Oscillator Sampling Interface Enable
|
||||
|
||||
// SMCR: Sleep Mode Control Register
|
||||
SMCR_SM = 0xe // Sleep Mode Select bits
|
||||
SMCR_SE = 0x1 // Sleep Enable
|
||||
|
||||
// DIDR0: Digital Input Disable Register
|
||||
DIDR0_PA1DID = 0x2 // When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.
|
||||
DIDR0_PA0DID = 0x1 // When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.
|
||||
|
||||
// PRR0: Power Reduction Register 0
|
||||
PRR0_PRVRM = 0x20 // Power Reduction Voltage Regulator Monitor
|
||||
PRR0_PRSPI = 0x8 // Power reduction SPI
|
||||
PRR0_PRTIM1 = 0x4 // Power Reduction Timer/Counter1
|
||||
PRR0_PRTIM0 = 0x2 // Power Reduction Timer/Counter0
|
||||
PRR0_PRVADC = 0x1 // Power Reduction V-ADC
|
||||
|
||||
// CLKPR: Clock Prescale Register
|
||||
CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable
|
||||
CLKPR_CLKPS = 0x3 // Clock Prescaler Select Bits
|
||||
)
|
||||
|
||||
// Bitfields for BATTERY_PROTECTION: Battery Protection
|
||||
const (
|
||||
// BPPLR: Battery Protection Parameter Lock Register
|
||||
BPPLR_BPPLE = 0x2 // Battery Protection Parameter Lock Enable
|
||||
BPPLR_BPPL = 0x1 // Battery Protection Parameter Lock
|
||||
|
||||
// BPCR: Battery Protection Control Register
|
||||
BPCR_SCD = 0x10 // Short Circuit Protection Disabled
|
||||
BPCR_DOCD = 0x8 // Discharge Over-current Protection Disabled
|
||||
BPCR_COCD = 0x4 // Charge Over-current Protection Disabled
|
||||
BPCR_DHCD = 0x2 // Discharge High-current Protection Disable
|
||||
BPCR_CHCD = 0x1 // Charge High-current Protection Disable
|
||||
|
||||
// BPIFR: Battery Protection Interrupt Flag Register
|
||||
BPIFR_SCIF = 0x10 // Short-circuit Protection Activated Interrupt Flag
|
||||
BPIFR_DOCIF = 0x8 // Discharge Over-current Protection Activated Interrupt Flag
|
||||
BPIFR_COCIF = 0x4 // Charge Over-current Protection Activated Interrupt Flag
|
||||
BPIFR_DHCIF = 0x2 // Disharge High-current Protection Activated Interrupt
|
||||
BPIFR_CHCIF = 0x1 // Charge High-current Protection Activated Interrupt
|
||||
|
||||
// BPIMSK: Battery Protection Interrupt Mask Register
|
||||
BPIMSK_SCIE = 0x10 // Short-circuit Protection Activated Interrupt Enable
|
||||
BPIMSK_DOCIE = 0x8 // Discharge Over-current Protection Activated Interrupt Enable
|
||||
BPIMSK_COCIE = 0x4 // Charge Over-current Protection Activated Interrupt Enable
|
||||
BPIMSK_DHCIE = 0x2 // Discharger High-current Protection Activated Interrupt
|
||||
BPIMSK_CHCIE = 0x1 // Charger High-current Protection Activated Interrupt
|
||||
)
|
||||
|
||||
// Bitfields for EEPROM: EEPROM
|
||||
const (
|
||||
// EECR: EEPROM Control Register
|
||||
EECR_EEPM = 0x30
|
||||
EECR_EERIE = 0x8 // EEProm Ready Interrupt Enable
|
||||
EECR_EEMPE = 0x4 // EEPROM Master Write Enable
|
||||
EECR_EEPE = 0x2 // EEPROM Write Enable
|
||||
EECR_EERE = 0x1 // EEPROM Read Enable
|
||||
)
|
||||
|
||||
// Bitfields for TC16: Timer/Counter, 16-bit
|
||||
const (
|
||||
// TCCR1B: Timer/Counter1 Control Register B
|
||||
TCCR1B_CS = 0x7 // Clock Select1 bis
|
||||
|
||||
// TCCR1A: Timer/Counter 1 Control Register A
|
||||
TCCR1A_TCW1 = 0x80 // Timer/Counter Width
|
||||
TCCR1A_ICEN1 = 0x40 // Input Capture Mode Enable
|
||||
TCCR1A_ICNC1 = 0x20 // Input Capture Noise Canceler
|
||||
TCCR1A_ICES1 = 0x10 // Input Capture Edge Select
|
||||
TCCR1A_ICS1 = 0x8 // Input Capture Select
|
||||
TCCR1A_WGM10 = 0x1 // Waveform Generation Mode
|
||||
|
||||
// TIMSK1: Timer/Counter Interrupt Mask Register
|
||||
TIMSK1_ICIE1 = 0x8 // Timer/Counter n Input Capture Interrupt Enable
|
||||
TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Interrupt Enable
|
||||
TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Interrupt Enable
|
||||
TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable
|
||||
|
||||
// TIFR1: Timer/Counter Interrupt Flag register
|
||||
TIFR1_ICF1 = 0x8 // Timer/Counter 1 Input Capture Flag
|
||||
TIFR1_OCF1B = 0x4 // Timer/Counter1 Output Compare Flag B
|
||||
TIFR1_OCF1A = 0x2 // Timer/Counter1 Output Compare Flag A
|
||||
TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag
|
||||
|
||||
// GTCCR: General Timer/Counter Control Register
|
||||
GTCCR_TSM = 0x80 // Timer/Counter Synchronization Mode
|
||||
GTCCR_PSRSYNC = 0x1 // Prescaler Reset
|
||||
|
||||
// TCCR0A: Timer/Counter0 Control Register
|
||||
TCCR0A_TCW0 = 0x80 // Timer/Counter Width
|
||||
TCCR0A_ICEN0 = 0x40 // Input Capture Mode Enable
|
||||
TCCR0A_ICNC0 = 0x20 // Input Capture Noise Canceler
|
||||
TCCR0A_ICES0 = 0x10 // Input Capture Edge Select
|
||||
TCCR0A_ICS0 = 0x8 // Input Capture Select
|
||||
TCCR0A_WGM00 = 0x1 // Clock Select0 bit 0
|
||||
|
||||
// TCCR0B: Timer/Counter0 Control Register
|
||||
TCCR0B_CS02 = 0x4 // Clock Select0 bit 2
|
||||
TCCR0B_CS01 = 0x2 // Clock Select0 bit 1
|
||||
TCCR0B_CS00 = 0x1 // Clock Select0 bit 0
|
||||
|
||||
// TIMSK0: Timer/Counter Interrupt Mask Register
|
||||
TIMSK0_ICIE0 = 0x8 // Timer/Counter n Input Capture Interrupt Enable
|
||||
TIMSK0_OCIE0B = 0x4 // Output Compare Interrupt Enable
|
||||
TIMSK0_OCIE0A = 0x2 // Output Compare Interrupt Enable
|
||||
TIMSK0_TOIE0 = 0x1 // Overflow Interrupt Enable
|
||||
|
||||
// TIFR0: Timer/Counter Interrupt Flag register
|
||||
TIFR0_ICF0 = 0x8 // Timer/Counter Interrupt Flag Register
|
||||
TIFR0_OCF0B = 0x4 // Output Compare Flag
|
||||
TIFR0_OCF0A = 0x2 // Output Compare Flag
|
||||
TIFR0_TOV0 = 0x1 // Overflow Flag
|
||||
)
|
||||
|
||||
// Bitfields for COULOMB_COUNTER: Coulomb Counter
|
||||
const (
|
||||
// CADCSRA: CC-ADC Control and Status Register A
|
||||
CADCSRA_CADEN = 0x80 // When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled.
|
||||
CADCSRA_CADPOL = 0x40
|
||||
CADCSRA_CADUB = 0x20 // CC_ADC Update Busy
|
||||
CADCSRA_CADAS = 0x18 // CC_ADC Accumulate Current Select Bits
|
||||
CADCSRA_CADSI = 0x6 // The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.
|
||||
CADCSRA_CADSE = 0x1 // When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode.
|
||||
|
||||
// CADCSRB: CC-ADC Control and Status Register B
|
||||
CADCSRB_CADACIE = 0x40
|
||||
CADCSRB_CADRCIE = 0x20 // Regular Current Interrupt Enable
|
||||
CADCSRB_CADICIE = 0x10 // CAD Instantenous Current Interrupt Enable
|
||||
CADCSRB_CADACIF = 0x4 // CC-ADC Accumulate Current Interrupt Flag
|
||||
CADCSRB_CADRCIF = 0x2 // CC-ADC Accumulate Current Interrupt Flag
|
||||
CADCSRB_CADICIF = 0x1 // CC-ADC Instantaneous Current Interrupt Flag
|
||||
)
|
||||
|
||||
// Bitfields for VOLTAGE_REGULATOR: Voltage Regulator
|
||||
const (
|
||||
// ROCR: Regulator Operating Condition Register
|
||||
ROCR_ROCS = 0x80 // ROC Status
|
||||
ROCR_ROCWIF = 0x2 // ROC Warning Interrupt Flag
|
||||
ROCR_ROCWIE = 0x1 // ROC Warning Interrupt Enable
|
||||
)
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from ATmega16HVA.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x4000;
|
||||
__ram_size = 0x200;
|
||||
__num_isrs = 21;
|
||||
|
|
@ -1,796 +0,0 @@
|
|||
// Automatically generated file. DO NOT EDIT.
|
||||
// Generated by gen-device.py from ATmega16HVB.atdf, see http://packs.download.atmel.com/
|
||||
|
||||
// +build avr,atmega16hvb
|
||||
|
||||
// Device information for the ATmega16HVB.
|
||||
//
|
||||
package avr
|
||||
|
||||
// Magic type name for the compiler.
|
||||
type __reg uint8
|
||||
|
||||
// Export this magic type name.
|
||||
type RegValue = __reg
|
||||
|
||||
// Some information about this device.
|
||||
const (
|
||||
DEVICE = "ATmega16HVB"
|
||||
ARCH = "AVR8"
|
||||
FAMILY = "megaAVR"
|
||||
)
|
||||
|
||||
// Interrupts
|
||||
const (
|
||||
IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset
|
||||
IRQ_BPINT = 1 // Battery Protection Interrupt
|
||||
IRQ_VREGMON = 2 // Voltage regulator monitor interrupt
|
||||
IRQ_INT0 = 3 // External Interrupt Request 0
|
||||
IRQ_INT1 = 4 // External Interrupt Request 1
|
||||
IRQ_INT2 = 5 // External Interrupt Request 2
|
||||
IRQ_INT3 = 6 // External Interrupt Request 3
|
||||
IRQ_PCINT0 = 7 // Pin Change Interrupt 0
|
||||
IRQ_PCINT1 = 8 // Pin Change Interrupt 1
|
||||
IRQ_WDT = 9 // Watchdog Timeout Interrupt
|
||||
IRQ_BGSCD = 10 // Bandgap Buffer Short Circuit Detected
|
||||
IRQ_CHDET = 11 // Charger Detect
|
||||
IRQ_TIMER1_IC = 12 // Timer 1 Input capture
|
||||
IRQ_TIMER1_COMPA = 13 // Timer 1 Compare Match A
|
||||
IRQ_TIMER1_COMPB = 14 // Timer 1 Compare Match B
|
||||
IRQ_TIMER1_OVF = 15 // Timer 1 overflow
|
||||
IRQ_TIMER0_IC = 16 // Timer 0 Input Capture
|
||||
IRQ_TIMER0_COMPA = 17 // Timer 0 Comapre Match A
|
||||
IRQ_TIMER0_COMPB = 18 // Timer 0 Compare Match B
|
||||
IRQ_TIMER0_OVF = 19 // Timer 0 Overflow
|
||||
IRQ_TWIBUSCD = 20 // Two-Wire Bus Connect/Disconnect
|
||||
IRQ_TWI = 21 // Two-Wire Serial Interface
|
||||
IRQ_SPI_STC = 22 // SPI Serial transfer complete
|
||||
IRQ_VADC = 23 // Voltage ADC Conversion Complete
|
||||
IRQ_CCADC_CONV = 24 // Coulomb Counter ADC Conversion Complete
|
||||
IRQ_CCADC_REG_CUR = 25 // Coloumb Counter ADC Regular Current
|
||||
IRQ_CCADC_ACC = 26 // Coloumb Counter ADC Accumulator
|
||||
IRQ_EE_READY = 27 // EEPROM Ready
|
||||
IRQ_SPM = 28 // SPM Ready
|
||||
IRQ_max = 28 // Highest interrupt number on this device.
|
||||
)
|
||||
|
||||
// Peripherals
|
||||
var (
|
||||
// Fuses
|
||||
FUSE = struct {
|
||||
LOW __reg
|
||||
HIGH __reg
|
||||
}{
|
||||
LOW: 0x0,
|
||||
HIGH: 0x1,
|
||||
}
|
||||
|
||||
// Lockbits
|
||||
LOCKBIT = struct {
|
||||
LOCKBIT __reg
|
||||
}{
|
||||
LOCKBIT: 0x0,
|
||||
}
|
||||
|
||||
// Analog-to-Digital Converter
|
||||
ADC = struct {
|
||||
VADMUX __reg
|
||||
VADCL __reg
|
||||
VADCH __reg
|
||||
VADCSR __reg
|
||||
}{
|
||||
VADMUX: 0x7c, // The VADC multiplexer Selection Register
|
||||
VADCL: 0x78, // VADC Data Register Bytes
|
||||
VADCH: 0x78, // VADC Data Register Bytes
|
||||
VADCSR: 0x7a, // The VADC Control and Status register
|
||||
}
|
||||
|
||||
// Watchdog Timer
|
||||
WDT = struct {
|
||||
WDTCSR __reg
|
||||
}{
|
||||
WDTCSR: 0x60, // Watchdog Timer Control Register
|
||||
}
|
||||
|
||||
// FET Control
|
||||
FET = struct {
|
||||
FCSR __reg
|
||||
}{
|
||||
FCSR: 0xf0, // FET Control and Status Register
|
||||
}
|
||||
|
||||
// Serial Peripheral Interface
|
||||
SPI = struct {
|
||||
SPCR __reg
|
||||
SPSR __reg
|
||||
SPDR __reg
|
||||
}{
|
||||
SPCR: 0x4c, // SPI Control Register
|
||||
SPSR: 0x4d, // SPI Status Register
|
||||
SPDR: 0x4e, // SPI Data Register
|
||||
}
|
||||
|
||||
// EEPROM
|
||||
EEPROM = struct {
|
||||
EEARL __reg
|
||||
EEARH __reg
|
||||
EEDR __reg
|
||||
EECR __reg
|
||||
}{
|
||||
EEARL: 0x41, // EEPROM Read/Write Access
|
||||
EEARH: 0x41, // EEPROM Read/Write Access
|
||||
EEDR: 0x40, // EEPROM Data Register
|
||||
EECR: 0x3f, // EEPROM Control Register
|
||||
}
|
||||
|
||||
// Coulomb Counter
|
||||
COULOMB_COUNTER = struct {
|
||||
CADCSRA __reg
|
||||
CADCSRB __reg
|
||||
CADCSRC __reg
|
||||
CADICL __reg
|
||||
CADICH __reg
|
||||
CADAC3 __reg
|
||||
CADAC2 __reg
|
||||
CADAC1 __reg
|
||||
CADAC0 __reg
|
||||
CADRCC __reg
|
||||
CADRDC __reg
|
||||
}{
|
||||
CADCSRA: 0xe6, // CC-ADC Control and Status Register A
|
||||
CADCSRB: 0xe7, // CC-ADC Control and Status Register B
|
||||
CADCSRC: 0xe8, // CC-ADC Control and Status Register C
|
||||
CADICL: 0xe4, // CC-ADC Instantaneous Current
|
||||
CADICH: 0xe4, // CC-ADC Instantaneous Current
|
||||
CADAC3: 0xe3, // ADC Accumulate Current
|
||||
CADAC2: 0xe2, // ADC Accumulate Current
|
||||
CADAC1: 0xe1, // ADC Accumulate Current
|
||||
CADAC0: 0xe0, // ADC Accumulate Current
|
||||
CADRCC: 0xe9, // CC-ADC Regular Charge Current
|
||||
CADRDC: 0xea, // CC-ADC Regular Discharge Current
|
||||
}
|
||||
|
||||
// Two Wire Serial Interface
|
||||
TWI = struct {
|
||||
TWBCSR __reg
|
||||
TWAMR __reg
|
||||
TWBR __reg
|
||||
TWCR __reg
|
||||
TWSR __reg
|
||||
TWDR __reg
|
||||
TWAR __reg
|
||||
}{
|
||||
TWBCSR: 0xbe, // TWI Bus Control and Status Register
|
||||
TWAMR: 0xbd, // TWI (Slave) Address Mask Register
|
||||
TWBR: 0xb8, // TWI Bit Rate register
|
||||
TWCR: 0xbc, // TWI Control Register
|
||||
TWSR: 0xb9, // TWI Status Register
|
||||
TWDR: 0xbb, // TWI Data register
|
||||
TWAR: 0xba, // TWI (Slave) Address register
|
||||
}
|
||||
|
||||
// External Interrupts
|
||||
EXINT = struct {
|
||||
EICRA __reg
|
||||
EIMSK __reg
|
||||
EIFR __reg
|
||||
PCICR __reg
|
||||
PCIFR __reg
|
||||
PCMSK1 __reg
|
||||
PCMSK0 __reg
|
||||
}{
|
||||
EICRA: 0x69, // External Interrupt Control Register
|
||||
EIMSK: 0x3d, // External Interrupt Mask Register
|
||||
EIFR: 0x3c, // External Interrupt Flag Register
|
||||
PCICR: 0x68, // Pin Change Interrupt Control Register
|
||||
PCIFR: 0x3b, // Pin Change Interrupt Flag Register
|
||||
PCMSK1: 0x6c, // Pin Change Enable Mask Register 1
|
||||
PCMSK0: 0x6b, // Pin Change Enable Mask Register 0
|
||||
}
|
||||
|
||||
// Timer/Counter, 16-bit
|
||||
TC16 = struct {
|
||||
TCCR1B __reg
|
||||
TCCR1A __reg
|
||||
TCNT1L __reg
|
||||
TCNT1H __reg
|
||||
OCR1A __reg
|
||||
OCR1B __reg
|
||||
TIMSK1 __reg
|
||||
TIFR1 __reg
|
||||
TCCR0B __reg
|
||||
TCCR0A __reg
|
||||
TCNT0L __reg
|
||||
TCNT0H __reg
|
||||
OCR0A __reg
|
||||
OCR0B __reg
|
||||
TIMSK0 __reg
|
||||
TIFR0 __reg
|
||||
}{
|
||||
TCCR1B: 0x81, // Timer/Counter1 Control Register B
|
||||
TCCR1A: 0x80, // Timer/Counter 1 Control Register A
|
||||
TCNT1L: 0x84, // Timer Counter 1 Bytes
|
||||
TCNT1H: 0x84, // Timer Counter 1 Bytes
|
||||
OCR1A: 0x88, // Output Compare Register 1A
|
||||
OCR1B: 0x89, // Output Compare Register B
|
||||
TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register
|
||||
TIFR1: 0x36, // Timer/Counter Interrupt Flag register
|
||||
TCCR0B: 0x45, // Timer/Counter0 Control Register B
|
||||
TCCR0A: 0x44, // Timer/Counter 0 Control Register A
|
||||
TCNT0L: 0x46, // Timer Counter 0 Bytes
|
||||
TCNT0H: 0x46, // Timer Counter 0 Bytes
|
||||
OCR0A: 0x48, // Output Compare Register A
|
||||
OCR0B: 0x49, // Output Compare Register B
|
||||
TIMSK0: 0x6e, // Timer/Counter Interrupt Mask Register
|
||||
TIFR0: 0x35, // Timer/Counter Interrupt Flag register
|
||||
}
|
||||
|
||||
// Cell Balancing
|
||||
CELL_BALANCING = struct {
|
||||
CBCR __reg
|
||||
}{
|
||||
CBCR: 0xf1, // Cell Balancing Control Register
|
||||
}
|
||||
|
||||
// Battery Protection
|
||||
BATTERY_PROTECTION = struct {
|
||||
BPPLR __reg
|
||||
BPCR __reg
|
||||
BPHCTR __reg
|
||||
BPOCTR __reg
|
||||
BPSCTR __reg
|
||||
BPCHCD __reg
|
||||
BPDHCD __reg
|
||||
BPCOCD __reg
|
||||
BPDOCD __reg
|
||||
BPSCD __reg
|
||||
BPIFR __reg
|
||||
BPIMSK __reg
|
||||
}{
|
||||
BPPLR: 0xfe, // Battery Protection Parameter Lock Register
|
||||
BPCR: 0xfd, // Battery Protection Control Register
|
||||
BPHCTR: 0xfc, // Battery Protection Short-current Timing Register
|
||||
BPOCTR: 0xfb, // Battery Protection Over-current Timing Register
|
||||
BPSCTR: 0xfa, // Battery Protection Short-current Timing Register
|
||||
BPCHCD: 0xf9, // Battery Protection Charge-High-current Detection Level Register
|
||||
BPDHCD: 0xf8, // Battery Protection Discharge-High-current Detection Level Register
|
||||
BPCOCD: 0xf7, // Battery Protection Charge-Over-current Detection Level Register
|
||||
BPDOCD: 0xf6, // Battery Protection Discharge-Over-current Detection Level Register
|
||||
BPSCD: 0xf5, // Battery Protection Short-Circuit Detection Level Register
|
||||
BPIFR: 0xf3, // Battery Protection Interrupt Flag Register
|
||||
BPIMSK: 0xf2, // Battery Protection Interrupt Mask Register
|
||||
}
|
||||
|
||||
// Charger Detect
|
||||
CHARGER_DETECT = struct {
|
||||
CHGDCSR __reg
|
||||
}{
|
||||
CHGDCSR: 0xd4, // Charger Detect Control and Status Register
|
||||
}
|
||||
|
||||
// Voltage Regulator
|
||||
VOLTAGE_REGULATOR = struct {
|
||||
ROCR __reg
|
||||
}{
|
||||
ROCR: 0xc8, // Regulator Operating Condition Register
|
||||
}
|
||||
|
||||
// Bandgap
|
||||
BANDGAP = struct {
|
||||
BGCSR __reg
|
||||
BGCRR __reg
|
||||
BGCCR __reg
|
||||
}{
|
||||
BGCSR: 0xd2, // Bandgap Control and Status Register
|
||||
BGCRR: 0xd1, // Bandgap Calibration of Resistor Ladder
|
||||
BGCCR: 0xd0, // Bandgap Calibration Register
|
||||
}
|
||||
|
||||
// CPU Registers
|
||||
CPU = struct {
|
||||
SREG __reg
|
||||
SPL __reg
|
||||
SPH __reg
|
||||
MCUCR __reg
|
||||
MCUSR __reg
|
||||
FOSCCAL __reg
|
||||
OSICSR __reg
|
||||
SMCR __reg
|
||||
GPIOR2 __reg
|
||||
GPIOR1 __reg
|
||||
GPIOR0 __reg
|
||||
DIDR0 __reg
|
||||
PRR0 __reg
|
||||
CLKPR __reg
|
||||
}{
|
||||
SREG: 0x5f, // Status Register
|
||||
SPL: 0x5d, // Stack Pointer
|
||||
SPH: 0x5d, // Stack Pointer
|
||||
MCUCR: 0x55, // MCU Control Register
|
||||
MCUSR: 0x54, // MCU Status Register
|
||||
FOSCCAL: 0x66, // Fast Oscillator Calibration Value
|
||||
OSICSR: 0x37, // Oscillator Sampling Interface Control and Status Register
|
||||
SMCR: 0x53, // Sleep Mode Control Register
|
||||
GPIOR2: 0x4b, // General Purpose IO Register 2
|
||||
GPIOR1: 0x4a, // General Purpose IO Register 1
|
||||
GPIOR0: 0x3e, // General Purpose IO Register 0
|
||||
DIDR0: 0x7e, // Digital Input Disable Register
|
||||
PRR0: 0x64, // Power Reduction Register 0
|
||||
CLKPR: 0x61, // Clock Prescale Register
|
||||
}
|
||||
|
||||
// I/O Port
|
||||
PORT = struct {
|
||||
PORTA __reg
|
||||
DDRA __reg
|
||||
PINA __reg
|
||||
PORTB __reg
|
||||
DDRB __reg
|
||||
PINB __reg
|
||||
PORTC __reg
|
||||
PINC __reg
|
||||
}{
|
||||
PORTA: 0x22, // Port A Data Register
|
||||
DDRA: 0x21, // Port A Data Direction Register
|
||||
PINA: 0x20, // Port A Input Pins
|
||||
PORTB: 0x25, // Port B Data Register
|
||||
DDRB: 0x24, // Port B Data Direction Register
|
||||
PINB: 0x23, // Port B Input Pins
|
||||
PORTC: 0x28, // Port C Data Register
|
||||
PINC: 0x26, // Port C Input Pins
|
||||
}
|
||||
|
||||
// Bootloader
|
||||
BOOT_LOAD = struct {
|
||||
SPMCSR __reg
|
||||
}{
|
||||
SPMCSR: 0x57, // Store Program Memory Control and Status Register
|
||||
}
|
||||
)
|
||||
|
||||
// Bitfields for FUSE: Fuses
|
||||
const (
|
||||
// LOW
|
||||
LOW_WDTON = 0x80 // Watch-dog Timer always on
|
||||
LOW_EESAVE = 0x40 // Preserve EEPROM through the Chip Erase cycle
|
||||
LOW_SPIEN = 0x20 // Serial program downloading (SPI) enabled
|
||||
LOW_SUT = 0x1c // Select start-up time
|
||||
LOW_OSCSEL = 0x3 // Oscillator select
|
||||
|
||||
// HIGH
|
||||
HIGH_CKDIV8 = 0x10 // Clock Divide mode
|
||||
HIGH_DWEN = 0x8 // Debug Wire enable
|
||||
HIGH_BOOTSZ = 0x6 // Select Boot Size
|
||||
HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled
|
||||
)
|
||||
|
||||
// Bitfields for LOCKBIT: Lockbits
|
||||
const (
|
||||
// LOCKBIT
|
||||
LOCKBIT_LB = 0x3 // Memory Lock
|
||||
LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode
|
||||
LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode
|
||||
)
|
||||
|
||||
// Bitfields for ADC: Analog-to-Digital Converter
|
||||
const (
|
||||
// VADMUX: The VADC multiplexer Selection Register
|
||||
VADMUX_VADMUX = 0xf // Analog Channel and Gain Selection Bits
|
||||
|
||||
// VADCL: VADC Data Register Bytes
|
||||
|
||||
// VADCH: VADC Data Register Bytes
|
||||
VADC_VADC = 0xfff // VADC Data bits
|
||||
|
||||
// VADCSR: The VADC Control and Status register
|
||||
VADCSR_VADEN = 0x8 // VADC Enable
|
||||
VADCSR_VADSC = 0x4 // VADC Satrt Conversion
|
||||
VADCSR_VADCCIF = 0x2 // VADC Conversion Complete Interrupt Flag
|
||||
VADCSR_VADCCIE = 0x1 // VADC Conversion Complete Interrupt Enable
|
||||
)
|
||||
|
||||
// Bitfields for WDT: Watchdog Timer
|
||||
const (
|
||||
// WDTCSR: Watchdog Timer Control Register
|
||||
WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag
|
||||
WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable
|
||||
WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits
|
||||
WDTCSR_WDCE = 0x10 // Watchdog Change Enable
|
||||
WDTCSR_WDE = 0x8 // Watch Dog Enable
|
||||
)
|
||||
|
||||
// Bitfields for FET: FET Control
|
||||
const (
|
||||
// FCSR: FET Control and Status Register
|
||||
FCSR_DUVRD = 0x8 // Deep Under-Voltage Recovery Disable
|
||||
FCSR_CPS = 0x4 // Current Protection Status
|
||||
FCSR_DFE = 0x2 // Discharge FET Enable
|
||||
FCSR_CFE = 0x1 // Charge FET Enable
|
||||
)
|
||||
|
||||
// Bitfields for SPI: Serial Peripheral Interface
|
||||
const (
|
||||
// SPCR: SPI Control Register
|
||||
SPCR_SPIE = 0x80 // SPI Interrupt Enable
|
||||
SPCR_SPE = 0x40 // SPI Enable
|
||||
SPCR_DORD = 0x20 // Data Order
|
||||
SPCR_MSTR = 0x10 // Master/Slave Select
|
||||
SPCR_CPOL = 0x8 // Clock polarity
|
||||
SPCR_CPHA = 0x4 // Clock Phase
|
||||
SPCR_SPR = 0x3 // SPI Clock Rate Selects
|
||||
|
||||
// SPSR: SPI Status Register
|
||||
SPSR_SPIF = 0x80 // SPI Interrupt Flag
|
||||
SPSR_WCOL = 0x40 // Write Collision Flag
|
||||
SPSR_SPI2X = 0x1 // Double SPI Speed Bit
|
||||
|
||||
// SPDR: SPI Data Register
|
||||
SPDR_SPDR = 0xff // SPI Data bits
|
||||
)
|
||||
|
||||
// Bitfields for EEPROM: EEPROM
|
||||
const (
|
||||
// EEARL: EEPROM Read/Write Access
|
||||
|
||||
// EEARH: EEPROM Read/Write Access
|
||||
EEAR_EEAR = 0x3ff // EEPROM Address bits
|
||||
|
||||
// EEDR: EEPROM Data Register
|
||||
EEDR_EEDR = 0xff // EEPROM Data bits
|
||||
|
||||
// EECR: EEPROM Control Register
|
||||
EECR_EEPM = 0x30
|
||||
EECR_EERIE = 0x8 // EEProm Ready Interrupt Enable
|
||||
EECR_EEMPE = 0x4 // EEPROM Master Write Enable
|
||||
EECR_EEPE = 0x2 // EEPROM Write Enable
|
||||
EECR_EERE = 0x1 // EEPROM Read Enable
|
||||
)
|
||||
|
||||
// Bitfields for COULOMB_COUNTER: Coulomb Counter
|
||||
const (
|
||||
// CADCSRA: CC-ADC Control and Status Register A
|
||||
CADCSRA_CADEN = 0x80 // When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled.
|
||||
CADCSRA_CADPOL = 0x40
|
||||
CADCSRA_CADUB = 0x20 // CC_ADC Update Busy
|
||||
CADCSRA_CADAS = 0x18 // CC_ADC Accumulate Current Select Bits
|
||||
CADCSRA_CADSI = 0x6 // The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.
|
||||
CADCSRA_CADSE = 0x1 // When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode.
|
||||
|
||||
// CADCSRB: CC-ADC Control and Status Register B
|
||||
CADCSRB_CADACIE = 0x40
|
||||
CADCSRB_CADRCIE = 0x20 // Regular Current Interrupt Enable
|
||||
CADCSRB_CADICIE = 0x10 // CAD Instantenous Current Interrupt Enable
|
||||
CADCSRB_CADACIF = 0x4 // CC-ADC Accumulate Current Interrupt Flag
|
||||
CADCSRB_CADRCIF = 0x2 // CC-ADC Accumulate Current Interrupt Flag
|
||||
CADCSRB_CADICIF = 0x1 // CC-ADC Instantaneous Current Interrupt Flag
|
||||
|
||||
// CADCSRC: CC-ADC Control and Status Register C
|
||||
CADCSRC_CADVSE = 0x1 // CC-ADC Voltage Scaling Enable
|
||||
|
||||
// CADICL: CC-ADC Instantaneous Current
|
||||
|
||||
// CADICH: CC-ADC Instantaneous Current
|
||||
CADIC_CADIC = 0xffff // CC-ADC Instantaneous Current
|
||||
|
||||
// CADAC3: ADC Accumulate Current
|
||||
CADAC3_CADAC = 0xff // ADC accumulate current bits
|
||||
|
||||
// CADAC2: ADC Accumulate Current
|
||||
CADAC2_CADAC = 0xff // ADC accumulate current bits
|
||||
|
||||
// CADAC1: ADC Accumulate Current
|
||||
CADAC1_CADAC = 0xfc // ADC accumulate current bits
|
||||
CADAC1_CADAC0 = 0x3 // ADC accumulate current bits
|
||||
|
||||
// CADAC0: ADC Accumulate Current
|
||||
CADAC0_CADAC0 = 0xff // ADC accumulate current bits
|
||||
|
||||
// CADRCC: CC-ADC Regular Charge Current
|
||||
CADRCC_CADRCC = 0xff // CC-ADC Regular Charge Current
|
||||
|
||||
// CADRDC: CC-ADC Regular Discharge Current
|
||||
CADRDC_CADRDC = 0xff // CC-ADC Regular Discharge Current
|
||||
)
|
||||
|
||||
// Bitfields for TWI: Two Wire Serial Interface
|
||||
const (
|
||||
// TWBCSR: TWI Bus Control and Status Register
|
||||
TWBCSR_TWBCIF = 0x80 // TWI Bus Connect/Disconnect Interrupt Flag
|
||||
TWBCSR_TWBCIE = 0x40 // TWI Bus Connect/Disconnect Interrupt Enable
|
||||
TWBCSR_TWBDT = 0x6 // TWI Bus Disconnect Time-out Period
|
||||
TWBCSR_TWBCIP = 0x1 // TWI Bus Connect/Disconnect Interrupt Polarity
|
||||
|
||||
// TWAMR: TWI (Slave) Address Mask Register
|
||||
TWAMR_TWAM = 0xfe
|
||||
|
||||
// TWBR: TWI Bit Rate register
|
||||
TWBR_TWBR = 0xff // TWI Bit Rate bits
|
||||
|
||||
// TWCR: TWI Control Register
|
||||
TWCR_TWINT = 0x80 // TWI Interrupt Flag
|
||||
TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit
|
||||
TWCR_TWSTA = 0x20 // TWI Start Condition Bit
|
||||
TWCR_TWSTO = 0x10 // TWI Stop Condition Bit
|
||||
TWCR_TWWC = 0x8 // TWI Write Collition Flag
|
||||
TWCR_TWEN = 0x4 // TWI Enable Bit
|
||||
TWCR_TWIE = 0x1 // TWI Interrupt Enable
|
||||
|
||||
// TWSR: TWI Status Register
|
||||
TWSR_TWS = 0xf8 // TWI Status
|
||||
TWSR_TWPS = 0x3 // TWI Prescaler
|
||||
|
||||
// TWDR: TWI Data register
|
||||
TWDR_TWD = 0xff // TWI Data Bits
|
||||
|
||||
// TWAR: TWI (Slave) Address register
|
||||
TWAR_TWA = 0xfe // TWI (Slave) Address register Bits
|
||||
TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit
|
||||
)
|
||||
|
||||
// Bitfields for EXINT: External Interrupts
|
||||
const (
|
||||
// EICRA: External Interrupt Control Register
|
||||
EICRA_ISC3 = 0xc0 // External Interrupt Sense Control 3 Bits
|
||||
EICRA_ISC2 = 0x30 // External Interrupt Sense Control 2 Bits
|
||||
EICRA_ISC1 = 0xc // External Interrupt Sense Control 1 Bits
|
||||
EICRA_ISC0 = 0x3 // External Interrupt Sense Control 0 Bits
|
||||
|
||||
// EIMSK: External Interrupt Mask Register
|
||||
EIMSK_INT = 0xf // External Interrupt Request 3 Enable
|
||||
|
||||
// EIFR: External Interrupt Flag Register
|
||||
EIFR_INTF = 0xf // External Interrupt Flags
|
||||
|
||||
// PCICR: Pin Change Interrupt Control Register
|
||||
PCICR_PCIE = 0x3 // Pin Change Interrupt Enables
|
||||
|
||||
// PCIFR: Pin Change Interrupt Flag Register
|
||||
PCIFR_PCIF = 0x3 // Pin Change Interrupt Flags
|
||||
|
||||
// PCMSK1: Pin Change Enable Mask Register 1
|
||||
PCMSK1_PCINT = 0xff // Pin Change Enable Mask
|
||||
|
||||
// PCMSK0: Pin Change Enable Mask Register 0
|
||||
PCMSK0_PCINT = 0xf // Pin Change Enable Mask
|
||||
)
|
||||
|
||||
// Bitfields for TC16: Timer/Counter, 16-bit
|
||||
const (
|
||||
// TCCR1B: Timer/Counter1 Control Register B
|
||||
TCCR1B_CS = 0x7 // Clock Select1 bis
|
||||
|
||||
// TCCR1A: Timer/Counter 1 Control Register A
|
||||
TCCR1A_TCW1 = 0x80 // Timer/Counter Width
|
||||
TCCR1A_ICEN1 = 0x40 // Input Capture Mode Enable
|
||||
TCCR1A_ICNC1 = 0x20 // Input Capture Noise Canceler
|
||||
TCCR1A_ICES1 = 0x10 // Input Capture Edge Select
|
||||
TCCR1A_ICS1 = 0x8 // Input Capture Select
|
||||
TCCR1A_WGM10 = 0x1 // Waveform Generation Mode
|
||||
|
||||
// TCNT1L: Timer Counter 1 Bytes
|
||||
|
||||
// TCNT1H: Timer Counter 1 Bytes
|
||||
TCNT1_TCNT1 = 0xffff // Timer Counter 1 bits
|
||||
|
||||
// OCR1A: Output Compare Register 1A
|
||||
OCR1A_OCR1A = 0xff // Output Compare 1 A bits
|
||||
|
||||
// OCR1B: Output Compare Register B
|
||||
OCR1B_OCR1B = 0xff // Output Compare 1 B bits
|
||||
|
||||
// TIMSK1: Timer/Counter Interrupt Mask Register
|
||||
TIMSK1_ICIE1 = 0x8 // Timer/Counter n Input Capture Interrupt Enable
|
||||
TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Interrupt Enable
|
||||
TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Interrupt Enable
|
||||
TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable
|
||||
|
||||
// TIFR1: Timer/Counter Interrupt Flag register
|
||||
TIFR1_ICF1 = 0x8 // Timer/Counter 1 Input Capture Flag
|
||||
TIFR1_OCF1B = 0x4 // Timer/Counter1 Output Compare Flag B
|
||||
TIFR1_OCF1A = 0x2 // Timer/Counter1 Output Compare Flag A
|
||||
TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag
|
||||
|
||||
// TCCR0B: Timer/Counter0 Control Register B
|
||||
TCCR0B_CS02 = 0x4 // Clock Select0 bit 2
|
||||
TCCR0B_CS01 = 0x2 // Clock Select0 bit 1
|
||||
TCCR0B_CS00 = 0x1 // Clock Select0 bit 0
|
||||
|
||||
// TCCR0A: Timer/Counter 0 Control Register A
|
||||
TCCR0A_TCW0 = 0x80 // Timer/Counter Width
|
||||
TCCR0A_ICEN0 = 0x40 // Input Capture Mode Enable
|
||||
TCCR0A_ICNC0 = 0x20 // Input Capture Noise Canceler
|
||||
TCCR0A_ICES0 = 0x10 // Input Capture Edge Select
|
||||
TCCR0A_ICS0 = 0x8 // Input Capture Select
|
||||
TCCR0A_WGM00 = 0x1 // Waveform Generation Mode
|
||||
|
||||
// TCNT0L: Timer Counter 0 Bytes
|
||||
|
||||
// TCNT0H: Timer Counter 0 Bytes
|
||||
TCNT0_TCNT0 = 0xffff // Timer Counter 0 bits
|
||||
|
||||
// OCR0A: Output Compare Register A
|
||||
OCR0A_OCR0A = 0xff // Output Compare 0 A bits
|
||||
|
||||
// OCR0B: Output Compare Register B
|
||||
OCR0B_OCR0B = 0xff // Output Compare 0 B bits
|
||||
|
||||
// TIMSK0: Timer/Counter Interrupt Mask Register
|
||||
TIMSK0_ICIE0 = 0x8 // Timer/Counter n Input Capture Interrupt Enable
|
||||
TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare B Interrupt Enable
|
||||
TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare A Interrupt Enable
|
||||
TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable
|
||||
|
||||
// TIFR0: Timer/Counter Interrupt Flag register
|
||||
TIFR0_ICF0 = 0x8 // Timer/Counter 0 Input Capture Flag
|
||||
TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag B
|
||||
TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag A
|
||||
TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag
|
||||
)
|
||||
|
||||
// Bitfields for CELL_BALANCING: Cell Balancing
|
||||
const (
|
||||
// CBCR: Cell Balancing Control Register
|
||||
CBCR_CBE = 0xf // Cell Balancing Enables
|
||||
)
|
||||
|
||||
// Bitfields for BATTERY_PROTECTION: Battery Protection
|
||||
const (
|
||||
// BPPLR: Battery Protection Parameter Lock Register
|
||||
BPPLR_BPPLE = 0x2 // Battery Protection Parameter Lock Enable
|
||||
BPPLR_BPPL = 0x1 // Battery Protection Parameter Lock
|
||||
|
||||
// BPCR: Battery Protection Control Register
|
||||
BPCR_EPID = 0x20 // External Protection Input Disable
|
||||
BPCR_SCD = 0x10 // Short Circuit Protection Disabled
|
||||
BPCR_DOCD = 0x8 // Discharge Over-current Protection Disabled
|
||||
BPCR_COCD = 0x4 // Charge Over-current Protection Disabled
|
||||
BPCR_DHCD = 0x2 // Discharge High-current Protection Disable
|
||||
BPCR_CHCD = 0x1 // Charge High-current Protection Disable
|
||||
|
||||
// BPHCTR: Battery Protection Short-current Timing Register
|
||||
BPHCTR_HCPT = 0x3f // Battery Protection Short-current Timing bits
|
||||
|
||||
// BPOCTR: Battery Protection Over-current Timing Register
|
||||
BPOCTR_OCPT = 0x3f // Battery Protection Over-current Timing bits
|
||||
|
||||
// BPSCTR: Battery Protection Short-current Timing Register
|
||||
BPSCTR_SCPT = 0x7f // Battery Protection Short-current Timing bits
|
||||
|
||||
// BPCHCD: Battery Protection Charge-High-current Detection Level Register
|
||||
BPCHCD_CHCDL = 0xff // Battery Protection Charge-High-current Detection Level bits
|
||||
|
||||
// BPDHCD: Battery Protection Discharge-High-current Detection Level Register
|
||||
BPDHCD_DHCDL = 0xff // Battery Protection Discharge-High-current Detection Level bits
|
||||
|
||||
// BPCOCD: Battery Protection Charge-Over-current Detection Level Register
|
||||
BPCOCD_COCDL = 0xff // Battery Protection Charge-Over-current Detection Level bits
|
||||
|
||||
// BPDOCD: Battery Protection Discharge-Over-current Detection Level Register
|
||||
BPDOCD_DOCDL = 0xff // Battery Protection Discharge-Over-current Detection Level bits
|
||||
|
||||
// BPSCD: Battery Protection Short-Circuit Detection Level Register
|
||||
BPSCD_SCDL = 0xff // Battery Protection Short-Circuit Detection Level Register bits
|
||||
|
||||
// BPIFR: Battery Protection Interrupt Flag Register
|
||||
BPIFR_SCIF = 0x10 // Short-circuit Protection Activated Interrupt Flag
|
||||
BPIFR_DOCIF = 0x8 // Discharge Over-current Protection Activated Interrupt Flag
|
||||
BPIFR_COCIF = 0x4 // Charge Over-current Protection Activated Interrupt Flag
|
||||
BPIFR_DHCIF = 0x2 // Disharge High-current Protection Activated Interrupt
|
||||
BPIFR_CHCIF = 0x1 // Charge High-current Protection Activated Interrupt
|
||||
|
||||
// BPIMSK: Battery Protection Interrupt Mask Register
|
||||
BPIMSK_SCIE = 0x10 // Short-circuit Protection Activated Interrupt Enable
|
||||
BPIMSK_DOCIE = 0x8 // Discharge Over-current Protection Activated Interrupt Enable
|
||||
BPIMSK_COCIE = 0x4 // Charge Over-current Protection Activated Interrupt Enable
|
||||
BPIMSK_DHCIE = 0x2 // Discharger High-current Protection Activated Interrupt
|
||||
BPIMSK_CHCIE = 0x1 // Charger High-current Protection Activated Interrupt
|
||||
)
|
||||
|
||||
// Bitfields for CHARGER_DETECT: Charger Detect
|
||||
const (
|
||||
// CHGDCSR: Charger Detect Control and Status Register
|
||||
CHGDCSR_BATTPVL = 0x10 // BATT Pin Voltage Level
|
||||
CHGDCSR_CHGDISC = 0xc // Charger Detect Interrupt Sense Control
|
||||
CHGDCSR_CHGDIF = 0x2 // Charger Detect Interrupt Flag
|
||||
CHGDCSR_CHGDIE = 0x1 // Charger Detect Interrupt Enable
|
||||
)
|
||||
|
||||
// Bitfields for VOLTAGE_REGULATOR: Voltage Regulator
|
||||
const (
|
||||
// ROCR: Regulator Operating Condition Register
|
||||
ROCR_ROCS = 0x80 // ROC Status
|
||||
ROCR_ROCD = 0x10 // ROC Disable
|
||||
ROCR_ROCWIF = 0x2 // ROC Warning Interrupt Flag
|
||||
ROCR_ROCWIE = 0x1 // ROC Warning Interrupt Enable
|
||||
)
|
||||
|
||||
// Bitfields for BANDGAP: Bandgap
|
||||
const (
|
||||
// BGCSR: Bandgap Control and Status Register
|
||||
BGCSR_BGD = 0x20 // Bandgap Disable
|
||||
BGCSR_BGSCDE = 0x10 // Bandgap Short Circuit Detection Enabled
|
||||
BGCSR_BGSCDIF = 0x2 // Bandgap Short Circuit Detection Interrupt Flag
|
||||
BGCSR_BGSCDIE = 0x1 // Bandgap Short Circuit Detection Interrupt Enable
|
||||
|
||||
// BGCRR: Bandgap Calibration of Resistor Ladder
|
||||
BGCRR_BGCR = 0xff // Bandgap Calibration of Resistor Ladder Bits
|
||||
|
||||
// BGCCR: Bandgap Calibration Register
|
||||
BGCCR_BGCC = 0x3f // BG Calibration of PTAT Current Bits
|
||||
)
|
||||
|
||||
// Bitfields for CPU: CPU Registers
|
||||
const (
|
||||
// SREG: Status Register
|
||||
SREG_I = 0x80 // Global Interrupt Enable
|
||||
SREG_T = 0x40 // Bit Copy Storage
|
||||
SREG_H = 0x20 // Half Carry Flag
|
||||
SREG_S = 0x10 // Sign Bit
|
||||
SREG_V = 0x8 // Two's Complement Overflow Flag
|
||||
SREG_N = 0x4 // Negative Flag
|
||||
SREG_Z = 0x2 // Zero Flag
|
||||
SREG_C = 0x1 // Carry Flag
|
||||
|
||||
// MCUCR: MCU Control Register
|
||||
MCUCR_CKOE = 0x20 // Clock Output Enable
|
||||
MCUCR_PUD = 0x10 // Pull-up disable
|
||||
MCUCR_IVSEL = 0x2 // Interrupt Vector Select
|
||||
MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable
|
||||
|
||||
// MCUSR: MCU Status Register
|
||||
MCUSR_OCDRF = 0x10 // OCD Reset Flag
|
||||
MCUSR_WDRF = 0x8 // Watchdog Reset Flag
|
||||
MCUSR_BODRF = 0x4 // Brown-out Reset Flag
|
||||
MCUSR_EXTRF = 0x2 // External Reset Flag
|
||||
MCUSR_PORF = 0x1 // Power-on reset flag
|
||||
|
||||
// FOSCCAL: Fast Oscillator Calibration Value
|
||||
FOSCCAL_FCAL = 0xff // Fast Oscillator Calibration Value
|
||||
|
||||
// OSICSR: Oscillator Sampling Interface Control and Status Register
|
||||
OSICSR_OSISEL0 = 0x10 // Oscillator Sampling Interface Select 0
|
||||
OSICSR_OSIST = 0x2 // Oscillator Sampling Interface Status
|
||||
OSICSR_OSIEN = 0x1 // Oscillator Sampling Interface Enable
|
||||
|
||||
// SMCR: Sleep Mode Control Register
|
||||
SMCR_SM = 0xe // Sleep Mode Select bits
|
||||
SMCR_SE = 0x1 // Sleep Enable
|
||||
|
||||
// GPIOR2: General Purpose IO Register 2
|
||||
GPIOR2_GPIOR2 = 0xff // General Purpose IO bits
|
||||
|
||||
// GPIOR1: General Purpose IO Register 1
|
||||
GPIOR1_GPIOR1 = 0xff // General Purpose IO bits
|
||||
|
||||
// GPIOR0: General Purpose IO Register 0
|
||||
GPIOR0_GPIOR0 = 0xff // General Purpose IO bits
|
||||
|
||||
// DIDR0: Digital Input Disable Register
|
||||
DIDR0_PA1DID = 0x2 // When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.
|
||||
DIDR0_PA0DID = 0x1 // When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.
|
||||
|
||||
// PRR0: Power Reduction Register 0
|
||||
PRR0_PRTWI = 0x40 // Power Reduction TWI
|
||||
PRR0_PRVRM = 0x20 // Power Reduction Voltage Regulator Monitor
|
||||
PRR0_PRSPI = 0x8 // Power reduction SPI
|
||||
PRR0_PRTIM1 = 0x4 // Power Reduction Timer/Counter1
|
||||
PRR0_PRTIM0 = 0x2 // Power Reduction Timer/Counter0
|
||||
PRR0_PRVADC = 0x1 // Power Reduction V-ADC
|
||||
|
||||
// CLKPR: Clock Prescale Register
|
||||
CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable
|
||||
CLKPR_CLKPS = 0x3 // Clock Prescaler Select Bits
|
||||
)
|
||||
|
||||
// Bitfields for BOOT_LOAD: Bootloader
|
||||
const (
|
||||
// SPMCSR: Store Program Memory Control and Status Register
|
||||
SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable
|
||||
SPMCSR_RWWSB = 0x40 // Read-While-Write Section Busy
|
||||
SPMCSR_SIGRD = 0x20 // Signature Row Read
|
||||
SPMCSR_RWWSRE = 0x10 // Read-While-Write Section Read Enable
|
||||
SPMCSR_LBSET = 0x8 // Lock Bit Set
|
||||
SPMCSR_PGWRT = 0x4 // Page Write
|
||||
SPMCSR_PGERS = 0x2 // Page Erase
|
||||
SPMCSR_SPMEN = 0x1 // Store Program Memory Enable
|
||||
)
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from ATmega16HVB.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x4000;
|
||||
__ram_size = 0x400;
|
||||
__num_isrs = 29;
|
||||
|
|
@ -1,796 +0,0 @@
|
|||
// Automatically generated file. DO NOT EDIT.
|
||||
// Generated by gen-device.py from ATmega16HVBrevB.atdf, see http://packs.download.atmel.com/
|
||||
|
||||
// +build avr,atmega16hvbrevb
|
||||
|
||||
// Device information for the ATmega16HVBrevB.
|
||||
//
|
||||
package avr
|
||||
|
||||
// Magic type name for the compiler.
|
||||
type __reg uint8
|
||||
|
||||
// Export this magic type name.
|
||||
type RegValue = __reg
|
||||
|
||||
// Some information about this device.
|
||||
const (
|
||||
DEVICE = "ATmega16HVBrevB"
|
||||
ARCH = "AVR8"
|
||||
FAMILY = "megaAVR"
|
||||
)
|
||||
|
||||
// Interrupts
|
||||
const (
|
||||
IRQ_RESET = 0 // External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset
|
||||
IRQ_BPINT = 1 // Battery Protection Interrupt
|
||||
IRQ_VREGMON = 2 // Voltage regulator monitor interrupt
|
||||
IRQ_INT0 = 3 // External Interrupt Request 0
|
||||
IRQ_INT1 = 4 // External Interrupt Request 1
|
||||
IRQ_INT2 = 5 // External Interrupt Request 2
|
||||
IRQ_INT3 = 6 // External Interrupt Request 3
|
||||
IRQ_PCINT0 = 7 // Pin Change Interrupt 0
|
||||
IRQ_PCINT1 = 8 // Pin Change Interrupt 1
|
||||
IRQ_WDT = 9 // Watchdog Timeout Interrupt
|
||||
IRQ_BGSCD = 10 // Bandgap Buffer Short Circuit Detected
|
||||
IRQ_CHDET = 11 // Charger Detect
|
||||
IRQ_TIMER1_IC = 12 // Timer 1 Input capture
|
||||
IRQ_TIMER1_COMPA = 13 // Timer 1 Compare Match A
|
||||
IRQ_TIMER1_COMPB = 14 // Timer 1 Compare Match B
|
||||
IRQ_TIMER1_OVF = 15 // Timer 1 overflow
|
||||
IRQ_TIMER0_IC = 16 // Timer 0 Input Capture
|
||||
IRQ_TIMER0_COMPA = 17 // Timer 0 Comapre Match A
|
||||
IRQ_TIMER0_COMPB = 18 // Timer 0 Compare Match B
|
||||
IRQ_TIMER0_OVF = 19 // Timer 0 Overflow
|
||||
IRQ_TWIBUSCD = 20 // Two-Wire Bus Connect/Disconnect
|
||||
IRQ_TWI = 21 // Two-Wire Serial Interface
|
||||
IRQ_SPI_STC = 22 // SPI Serial transfer complete
|
||||
IRQ_VADC = 23 // Voltage ADC Conversion Complete
|
||||
IRQ_CCADC_CONV = 24 // Coulomb Counter ADC Conversion Complete
|
||||
IRQ_CCADC_REG_CUR = 25 // Coloumb Counter ADC Regular Current
|
||||
IRQ_CCADC_ACC = 26 // Coloumb Counter ADC Accumulator
|
||||
IRQ_EE_READY = 27 // EEPROM Ready
|
||||
IRQ_SPM = 28 // SPM Ready
|
||||
IRQ_max = 28 // Highest interrupt number on this device.
|
||||
)
|
||||
|
||||
// Peripherals
|
||||
var (
|
||||
// Fuses
|
||||
FUSE = struct {
|
||||
LOW __reg
|
||||
HIGH __reg
|
||||
}{
|
||||
LOW: 0x0,
|
||||
HIGH: 0x1,
|
||||
}
|
||||
|
||||
// Lockbits
|
||||
LOCKBIT = struct {
|
||||
LOCKBIT __reg
|
||||
}{
|
||||
LOCKBIT: 0x0,
|
||||
}
|
||||
|
||||
// Analog-to-Digital Converter
|
||||
ADC = struct {
|
||||
VADMUX __reg
|
||||
VADCL __reg
|
||||
VADCH __reg
|
||||
VADCSR __reg
|
||||
}{
|
||||
VADMUX: 0x7c, // The VADC multiplexer Selection Register
|
||||
VADCL: 0x78, // VADC Data Register Bytes
|
||||
VADCH: 0x78, // VADC Data Register Bytes
|
||||
VADCSR: 0x7a, // The VADC Control and Status register
|
||||
}
|
||||
|
||||
// Watchdog Timer
|
||||
WDT = struct {
|
||||
WDTCSR __reg
|
||||
}{
|
||||
WDTCSR: 0x60, // Watchdog Timer Control Register
|
||||
}
|
||||
|
||||
// FET Control
|
||||
FET = struct {
|
||||
FCSR __reg
|
||||
}{
|
||||
FCSR: 0xf0, // FET Control and Status Register
|
||||
}
|
||||
|
||||
// Serial Peripheral Interface
|
||||
SPI = struct {
|
||||
SPCR __reg
|
||||
SPSR __reg
|
||||
SPDR __reg
|
||||
}{
|
||||
SPCR: 0x4c, // SPI Control Register
|
||||
SPSR: 0x4d, // SPI Status Register
|
||||
SPDR: 0x4e, // SPI Data Register
|
||||
}
|
||||
|
||||
// EEPROM
|
||||
EEPROM = struct {
|
||||
EEARL __reg
|
||||
EEARH __reg
|
||||
EEDR __reg
|
||||
EECR __reg
|
||||
}{
|
||||
EEARL: 0x41, // EEPROM Read/Write Access
|
||||
EEARH: 0x41, // EEPROM Read/Write Access
|
||||
EEDR: 0x40, // EEPROM Data Register
|
||||
EECR: 0x3f, // EEPROM Control Register
|
||||
}
|
||||
|
||||
// Coulomb Counter
|
||||
COULOMB_COUNTER = struct {
|
||||
CADCSRA __reg
|
||||
CADCSRB __reg
|
||||
CADCSRC __reg
|
||||
CADICL __reg
|
||||
CADICH __reg
|
||||
CADAC3 __reg
|
||||
CADAC2 __reg
|
||||
CADAC1 __reg
|
||||
CADAC0 __reg
|
||||
CADRCC __reg
|
||||
CADRDC __reg
|
||||
}{
|
||||
CADCSRA: 0xe6, // CC-ADC Control and Status Register A
|
||||
CADCSRB: 0xe7, // CC-ADC Control and Status Register B
|
||||
CADCSRC: 0xe8, // CC-ADC Control and Status Register C
|
||||
CADICL: 0xe4, // CC-ADC Instantaneous Current
|
||||
CADICH: 0xe4, // CC-ADC Instantaneous Current
|
||||
CADAC3: 0xe3, // ADC Accumulate Current
|
||||
CADAC2: 0xe2, // ADC Accumulate Current
|
||||
CADAC1: 0xe1, // ADC Accumulate Current
|
||||
CADAC0: 0xe0, // ADC Accumulate Current
|
||||
CADRCC: 0xe9, // CC-ADC Regular Charge Current
|
||||
CADRDC: 0xea, // CC-ADC Regular Discharge Current
|
||||
}
|
||||
|
||||
// Two Wire Serial Interface
|
||||
TWI = struct {
|
||||
TWBCSR __reg
|
||||
TWAMR __reg
|
||||
TWBR __reg
|
||||
TWCR __reg
|
||||
TWSR __reg
|
||||
TWDR __reg
|
||||
TWAR __reg
|
||||
}{
|
||||
TWBCSR: 0xbe, // TWI Bus Control and Status Register
|
||||
TWAMR: 0xbd, // TWI (Slave) Address Mask Register
|
||||
TWBR: 0xb8, // TWI Bit Rate register
|
||||
TWCR: 0xbc, // TWI Control Register
|
||||
TWSR: 0xb9, // TWI Status Register
|
||||
TWDR: 0xbb, // TWI Data register
|
||||
TWAR: 0xba, // TWI (Slave) Address register
|
||||
}
|
||||
|
||||
// External Interrupts
|
||||
EXINT = struct {
|
||||
EICRA __reg
|
||||
EIMSK __reg
|
||||
EIFR __reg
|
||||
PCICR __reg
|
||||
PCIFR __reg
|
||||
PCMSK1 __reg
|
||||
PCMSK0 __reg
|
||||
}{
|
||||
EICRA: 0x69, // External Interrupt Control Register
|
||||
EIMSK: 0x3d, // External Interrupt Mask Register
|
||||
EIFR: 0x3c, // External Interrupt Flag Register
|
||||
PCICR: 0x68, // Pin Change Interrupt Control Register
|
||||
PCIFR: 0x3b, // Pin Change Interrupt Flag Register
|
||||
PCMSK1: 0x6c, // Pin Change Enable Mask Register 1
|
||||
PCMSK0: 0x6b, // Pin Change Enable Mask Register 0
|
||||
}
|
||||
|
||||
// Timer/Counter, 16-bit
|
||||
TC16 = struct {
|
||||
TCCR1B __reg
|
||||
TCCR1A __reg
|
||||
TCNT1L __reg
|
||||
TCNT1H __reg
|
||||
OCR1A __reg
|
||||
OCR1B __reg
|
||||
TIMSK1 __reg
|
||||
TIFR1 __reg
|
||||
TCCR0B __reg
|
||||
TCCR0A __reg
|
||||
TCNT0L __reg
|
||||
TCNT0H __reg
|
||||
OCR0A __reg
|
||||
OCR0B __reg
|
||||
TIMSK0 __reg
|
||||
TIFR0 __reg
|
||||
}{
|
||||
TCCR1B: 0x81, // Timer/Counter1 Control Register B
|
||||
TCCR1A: 0x80, // Timer/Counter 1 Control Register A
|
||||
TCNT1L: 0x84, // Timer Counter 1 Bytes
|
||||
TCNT1H: 0x84, // Timer Counter 1 Bytes
|
||||
OCR1A: 0x88, // Output Compare Register 1A
|
||||
OCR1B: 0x89, // Output Compare Register B
|
||||
TIMSK1: 0x6f, // Timer/Counter Interrupt Mask Register
|
||||
TIFR1: 0x36, // Timer/Counter Interrupt Flag register
|
||||
TCCR0B: 0x45, // Timer/Counter0 Control Register B
|
||||
TCCR0A: 0x44, // Timer/Counter 0 Control Register A
|
||||
TCNT0L: 0x46, // Timer Counter 0 Bytes
|
||||
TCNT0H: 0x46, // Timer Counter 0 Bytes
|
||||
OCR0A: 0x48, // Output Compare Register 0A
|
||||
OCR0B: 0x49, // Output Compare Register B
|
||||
TIMSK0: 0x6e, // Timer/Counter Interrupt Mask Register
|
||||
TIFR0: 0x35, // Timer/Counter Interrupt Flag register
|
||||
}
|
||||
|
||||
// Cell Balancing
|
||||
CELL_BALANCING = struct {
|
||||
CBCR __reg
|
||||
}{
|
||||
CBCR: 0xf1, // Cell Balancing Control Register
|
||||
}
|
||||
|
||||
// Battery Protection
|
||||
BATTERY_PROTECTION = struct {
|
||||
BPPLR __reg
|
||||
BPCR __reg
|
||||
BPHCTR __reg
|
||||
BPOCTR __reg
|
||||
BPSCTR __reg
|
||||
BPCHCD __reg
|
||||
BPDHCD __reg
|
||||
BPCOCD __reg
|
||||
BPDOCD __reg
|
||||
BPSCD __reg
|
||||
BPIFR __reg
|
||||
BPIMSK __reg
|
||||
}{
|
||||
BPPLR: 0xfe, // Battery Protection Parameter Lock Register
|
||||
BPCR: 0xfd, // Battery Protection Control Register
|
||||
BPHCTR: 0xfc, // Battery Protection Short-current Timing Register
|
||||
BPOCTR: 0xfb, // Battery Protection Over-current Timing Register
|
||||
BPSCTR: 0xfa, // Battery Protection Short-current Timing Register
|
||||
BPCHCD: 0xf9, // Battery Protection Charge-High-current Detection Level Register
|
||||
BPDHCD: 0xf8, // Battery Protection Discharge-High-current Detection Level Register
|
||||
BPCOCD: 0xf7, // Battery Protection Charge-Over-current Detection Level Register
|
||||
BPDOCD: 0xf6, // Battery Protection Discharge-Over-current Detection Level Register
|
||||
BPSCD: 0xf5, // Battery Protection Short-Circuit Detection Level Register
|
||||
BPIFR: 0xf3, // Battery Protection Interrupt Flag Register
|
||||
BPIMSK: 0xf2, // Battery Protection Interrupt Mask Register
|
||||
}
|
||||
|
||||
// Charger Detect
|
||||
CHARGER_DETECT = struct {
|
||||
CHGDCSR __reg
|
||||
}{
|
||||
CHGDCSR: 0xd4, // Charger Detect Control and Status Register
|
||||
}
|
||||
|
||||
// Voltage Regulator
|
||||
VOLTAGE_REGULATOR = struct {
|
||||
ROCR __reg
|
||||
}{
|
||||
ROCR: 0xc8, // Regulator Operating Condition Register
|
||||
}
|
||||
|
||||
// Bandgap
|
||||
BANDGAP = struct {
|
||||
BGCSR __reg
|
||||
BGCRR __reg
|
||||
BGCCR __reg
|
||||
}{
|
||||
BGCSR: 0xd2, // Bandgap Control and Status Register
|
||||
BGCRR: 0xd1, // Bandgap Calibration of Resistor Ladder
|
||||
BGCCR: 0xd0, // Bandgap Calibration Register
|
||||
}
|
||||
|
||||
// CPU Registers
|
||||
CPU = struct {
|
||||
SREG __reg
|
||||
SPL __reg
|
||||
SPH __reg
|
||||
MCUCR __reg
|
||||
MCUSR __reg
|
||||
FOSCCAL __reg
|
||||
OSICSR __reg
|
||||
SMCR __reg
|
||||
GPIOR2 __reg
|
||||
GPIOR1 __reg
|
||||
GPIOR0 __reg
|
||||
DIDR0 __reg
|
||||
PRR0 __reg
|
||||
CLKPR __reg
|
||||
}{
|
||||
SREG: 0x5f, // Status Register
|
||||
SPL: 0x5d, // Stack Pointer
|
||||
SPH: 0x5d, // Stack Pointer
|
||||
MCUCR: 0x55, // MCU Control Register
|
||||
MCUSR: 0x54, // MCU Status Register
|
||||
FOSCCAL: 0x66, // Fast Oscillator Calibration Value
|
||||
OSICSR: 0x37, // Oscillator Sampling Interface Control and Status Register
|
||||
SMCR: 0x53, // Sleep Mode Control Register
|
||||
GPIOR2: 0x4b, // General Purpose IO Register 2
|
||||
GPIOR1: 0x4a, // General Purpose IO Register 1
|
||||
GPIOR0: 0x3e, // General Purpose IO Register 0
|
||||
DIDR0: 0x7e, // Digital Input Disable Register
|
||||
PRR0: 0x64, // Power Reduction Register 0
|
||||
CLKPR: 0x61, // Clock Prescale Register
|
||||
}
|
||||
|
||||
// I/O Port
|
||||
PORT = struct {
|
||||
PORTA __reg
|
||||
DDRA __reg
|
||||
PINA __reg
|
||||
PORTB __reg
|
||||
DDRB __reg
|
||||
PINB __reg
|
||||
PORTC __reg
|
||||
PINC __reg
|
||||
}{
|
||||
PORTA: 0x22, // Port A Data Register
|
||||
DDRA: 0x21, // Port A Data Direction Register
|
||||
PINA: 0x20, // Port A Input Pins
|
||||
PORTB: 0x25, // Port B Data Register
|
||||
DDRB: 0x24, // Port B Data Direction Register
|
||||
PINB: 0x23, // Port B Input Pins
|
||||
PORTC: 0x28, // Port C Data Register
|
||||
PINC: 0x26, // Port C Input Pins
|
||||
}
|
||||
|
||||
// Bootloader
|
||||
BOOT_LOAD = struct {
|
||||
SPMCSR __reg
|
||||
}{
|
||||
SPMCSR: 0x57, // Store Program Memory Control and Status Register
|
||||
}
|
||||
)
|
||||
|
||||
// Bitfields for FUSE: Fuses
|
||||
const (
|
||||
// LOW
|
||||
LOW_WDTON = 0x80 // Watch-dog Timer always on
|
||||
LOW_EESAVE = 0x40 // Preserve EEPROM through the Chip Erase cycle
|
||||
LOW_SPIEN = 0x20 // Serial program downloading (SPI) enabled
|
||||
LOW_SUT = 0x1c // Select start-up time
|
||||
LOW_OSCSEL = 0x3 // Oscillator select
|
||||
|
||||
// HIGH
|
||||
HIGH_DUVRDINIT = 0x10 // DUVR mode on
|
||||
HIGH_DWEN = 0x8 // Debug Wire enable
|
||||
HIGH_BOOTSZ = 0x6 // Select Boot Size
|
||||
HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled
|
||||
)
|
||||
|
||||
// Bitfields for LOCKBIT: Lockbits
|
||||
const (
|
||||
// LOCKBIT
|
||||
LOCKBIT_LB = 0x3 // Memory Lock
|
||||
LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode
|
||||
LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode
|
||||
)
|
||||
|
||||
// Bitfields for ADC: Analog-to-Digital Converter
|
||||
const (
|
||||
// VADMUX: The VADC multiplexer Selection Register
|
||||
VADMUX_VADMUX = 0xf // Analog Channel and Gain Selection Bits
|
||||
|
||||
// VADCL: VADC Data Register Bytes
|
||||
|
||||
// VADCH: VADC Data Register Bytes
|
||||
VADC_VADC = 0xfff // VADC Data bits
|
||||
|
||||
// VADCSR: The VADC Control and Status register
|
||||
VADCSR_VADEN = 0x8 // VADC Enable
|
||||
VADCSR_VADSC = 0x4 // VADC Satrt Conversion
|
||||
VADCSR_VADCCIF = 0x2 // VADC Conversion Complete Interrupt Flag
|
||||
VADCSR_VADCCIE = 0x1 // VADC Conversion Complete Interrupt Enable
|
||||
)
|
||||
|
||||
// Bitfields for WDT: Watchdog Timer
|
||||
const (
|
||||
// WDTCSR: Watchdog Timer Control Register
|
||||
WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag
|
||||
WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable
|
||||
WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits
|
||||
WDTCSR_WDCE = 0x10 // Watchdog Change Enable
|
||||
WDTCSR_WDE = 0x8 // Watch Dog Enable
|
||||
)
|
||||
|
||||
// Bitfields for FET: FET Control
|
||||
const (
|
||||
// FCSR: FET Control and Status Register
|
||||
FCSR_DUVRD = 0x8 // Deep Under-Voltage Recovery Disable
|
||||
FCSR_CPS = 0x4 // Current Protection Status
|
||||
FCSR_DFE = 0x2 // Discharge FET Enable
|
||||
FCSR_CFE = 0x1 // Charge FET Enable
|
||||
)
|
||||
|
||||
// Bitfields for SPI: Serial Peripheral Interface
|
||||
const (
|
||||
// SPCR: SPI Control Register
|
||||
SPCR_SPIE = 0x80 // SPI Interrupt Enable
|
||||
SPCR_SPE = 0x40 // SPI Enable
|
||||
SPCR_DORD = 0x20 // Data Order
|
||||
SPCR_MSTR = 0x10 // Master/Slave Select
|
||||
SPCR_CPOL = 0x8 // Clock polarity
|
||||
SPCR_CPHA = 0x4 // Clock Phase
|
||||
SPCR_SPR = 0x3 // SPI Clock Rate Selects
|
||||
|
||||
// SPSR: SPI Status Register
|
||||
SPSR_SPIF = 0x80 // SPI Interrupt Flag
|
||||
SPSR_WCOL = 0x40 // Write Collision Flag
|
||||
SPSR_SPI2X = 0x1 // Double SPI Speed Bit
|
||||
|
||||
// SPDR: SPI Data Register
|
||||
SPDR_SPDR = 0xff // SPI Data bits
|
||||
)
|
||||
|
||||
// Bitfields for EEPROM: EEPROM
|
||||
const (
|
||||
// EEARL: EEPROM Read/Write Access
|
||||
|
||||
// EEARH: EEPROM Read/Write Access
|
||||
EEAR_EEAR = 0x3ff // EEPROM Address bits
|
||||
|
||||
// EEDR: EEPROM Data Register
|
||||
EEDR_EEDR = 0xff // EEPROM Data bits
|
||||
|
||||
// EECR: EEPROM Control Register
|
||||
EECR_EEPM = 0x30
|
||||
EECR_EERIE = 0x8 // EEProm Ready Interrupt Enable
|
||||
EECR_EEMPE = 0x4 // EEPROM Master Write Enable
|
||||
EECR_EEPE = 0x2 // EEPROM Write Enable
|
||||
EECR_EERE = 0x1 // EEPROM Read Enable
|
||||
)
|
||||
|
||||
// Bitfields for COULOMB_COUNTER: Coulomb Counter
|
||||
const (
|
||||
// CADCSRA: CC-ADC Control and Status Register A
|
||||
CADCSRA_CADEN = 0x80 // When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled.
|
||||
CADCSRA_CADPOL = 0x40
|
||||
CADCSRA_CADUB = 0x20 // CC_ADC Update Busy
|
||||
CADCSRA_CADAS = 0x18 // CC_ADC Accumulate Current Select Bits
|
||||
CADCSRA_CADSI = 0x6 // The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.
|
||||
CADCSRA_CADSE = 0x1 // When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode.
|
||||
|
||||
// CADCSRB: CC-ADC Control and Status Register B
|
||||
CADCSRB_CADACIE = 0x40
|
||||
CADCSRB_CADRCIE = 0x20 // Regular Current Interrupt Enable
|
||||
CADCSRB_CADICIE = 0x10 // CAD Instantenous Current Interrupt Enable
|
||||
CADCSRB_CADACIF = 0x4 // CC-ADC Accumulate Current Interrupt Flag
|
||||
CADCSRB_CADRCIF = 0x2 // CC-ADC Accumulate Current Interrupt Flag
|
||||
CADCSRB_CADICIF = 0x1 // CC-ADC Instantaneous Current Interrupt Flag
|
||||
|
||||
// CADCSRC: CC-ADC Control and Status Register C
|
||||
CADCSRC_CADVSE = 0x1 // CC-ADC Voltage Scaling Enable
|
||||
|
||||
// CADICL: CC-ADC Instantaneous Current
|
||||
|
||||
// CADICH: CC-ADC Instantaneous Current
|
||||
CADIC_CADIC = 0xffff // CC-ADC Instantaneous Current
|
||||
|
||||
// CADAC3: ADC Accumulate Current
|
||||
CADAC3_CADAC = 0xff // ADC accumulate current bits
|
||||
|
||||
// CADAC2: ADC Accumulate Current
|
||||
CADAC2_CADAC = 0xff // ADC accumulate current bits
|
||||
|
||||
// CADAC1: ADC Accumulate Current
|
||||
CADAC1_CADAC = 0xfc // ADC accumulate current bits
|
||||
CADAC1_CADAC0 = 0x3 // ADC accumulate current bits
|
||||
|
||||
// CADAC0: ADC Accumulate Current
|
||||
CADAC0_CADAC0 = 0xff // ADC accumulate current bits
|
||||
|
||||
// CADRCC: CC-ADC Regular Charge Current
|
||||
CADRCC_CADRCC = 0xff // CC-ADC Regular Charge Current
|
||||
|
||||
// CADRDC: CC-ADC Regular Discharge Current
|
||||
CADRDC_CADRDC = 0xff // CC-ADC Regular Discharge Current
|
||||
)
|
||||
|
||||
// Bitfields for TWI: Two Wire Serial Interface
|
||||
const (
|
||||
// TWBCSR: TWI Bus Control and Status Register
|
||||
TWBCSR_TWBCIF = 0x80 // TWI Bus Connect/Disconnect Interrupt Flag
|
||||
TWBCSR_TWBCIE = 0x40 // TWI Bus Connect/Disconnect Interrupt Enable
|
||||
TWBCSR_TWBDT = 0x6 // TWI Bus Disconnect Time-out Period
|
||||
TWBCSR_TWBCIP = 0x1 // TWI Bus Connect/Disconnect Interrupt Polarity
|
||||
|
||||
// TWAMR: TWI (Slave) Address Mask Register
|
||||
TWAMR_TWAM = 0xfe
|
||||
|
||||
// TWBR: TWI Bit Rate register
|
||||
TWBR_TWBR = 0xff // TWI Bit Rate bits
|
||||
|
||||
// TWCR: TWI Control Register
|
||||
TWCR_TWINT = 0x80 // TWI Interrupt Flag
|
||||
TWCR_TWEA = 0x40 // TWI Enable Acknowledge Bit
|
||||
TWCR_TWSTA = 0x20 // TWI Start Condition Bit
|
||||
TWCR_TWSTO = 0x10 // TWI Stop Condition Bit
|
||||
TWCR_TWWC = 0x8 // TWI Write Collition Flag
|
||||
TWCR_TWEN = 0x4 // TWI Enable Bit
|
||||
TWCR_TWIE = 0x1 // TWI Interrupt Enable
|
||||
|
||||
// TWSR: TWI Status Register
|
||||
TWSR_TWS = 0xf8 // TWI Status
|
||||
TWSR_TWPS = 0x3 // TWI Prescaler
|
||||
|
||||
// TWDR: TWI Data register
|
||||
TWDR_TWD = 0xff // TWI Data Bits
|
||||
|
||||
// TWAR: TWI (Slave) Address register
|
||||
TWAR_TWA = 0xfe // TWI (Slave) Address register Bits
|
||||
TWAR_TWGCE = 0x1 // TWI General Call Recognition Enable Bit
|
||||
)
|
||||
|
||||
// Bitfields for EXINT: External Interrupts
|
||||
const (
|
||||
// EICRA: External Interrupt Control Register
|
||||
EICRA_ISC3 = 0xc0 // External Interrupt Sense Control 3 Bits
|
||||
EICRA_ISC2 = 0x30 // External Interrupt Sense Control 2 Bits
|
||||
EICRA_ISC1 = 0xc // External Interrupt Sense Control 1 Bits
|
||||
EICRA_ISC0 = 0x3 // External Interrupt Sense Control 0 Bits
|
||||
|
||||
// EIMSK: External Interrupt Mask Register
|
||||
EIMSK_INT = 0xf // External Interrupt Request 3 Enable
|
||||
|
||||
// EIFR: External Interrupt Flag Register
|
||||
EIFR_INTF = 0xf // External Interrupt Flags
|
||||
|
||||
// PCICR: Pin Change Interrupt Control Register
|
||||
PCICR_PCIE = 0x3 // Pin Change Interrupt Enables
|
||||
|
||||
// PCIFR: Pin Change Interrupt Flag Register
|
||||
PCIFR_PCIF = 0x3 // Pin Change Interrupt Flags
|
||||
|
||||
// PCMSK1: Pin Change Enable Mask Register 1
|
||||
PCMSK1_PCINT = 0xff // Pin Change Enable Mask
|
||||
|
||||
// PCMSK0: Pin Change Enable Mask Register 0
|
||||
PCMSK0_PCINT = 0xf // Pin Change Enable Mask
|
||||
)
|
||||
|
||||
// Bitfields for TC16: Timer/Counter, 16-bit
|
||||
const (
|
||||
// TCCR1B: Timer/Counter1 Control Register B
|
||||
TCCR1B_CS = 0x7 // Clock Select1 bis
|
||||
|
||||
// TCCR1A: Timer/Counter 1 Control Register A
|
||||
TCCR1A_TCW1 = 0x80 // Timer/Counter Width
|
||||
TCCR1A_ICEN1 = 0x40 // Input Capture Mode Enable
|
||||
TCCR1A_ICNC1 = 0x20 // Input Capture Noise Canceler
|
||||
TCCR1A_ICES1 = 0x10 // Input Capture Edge Select
|
||||
TCCR1A_ICS1 = 0x8 // Input Capture Select
|
||||
TCCR1A_WGM10 = 0x1 // Waveform Generation Mode
|
||||
|
||||
// TCNT1L: Timer Counter 1 Bytes
|
||||
|
||||
// TCNT1H: Timer Counter 1 Bytes
|
||||
TCNT1_TCNT1 = 0xffff // Timer Counter 1 bits
|
||||
|
||||
// OCR1A: Output Compare Register 1A
|
||||
OCR1A_OCR1A = 0xff // Output Compare 1 A bits
|
||||
|
||||
// OCR1B: Output Compare Register B
|
||||
OCR1B_OCR1B = 0xff // Output Compare 1 B bits
|
||||
|
||||
// TIMSK1: Timer/Counter Interrupt Mask Register
|
||||
TIMSK1_ICIE1 = 0x8 // Timer/Counter n Input Capture Interrupt Enable
|
||||
TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Interrupt Enable
|
||||
TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Interrupt Enable
|
||||
TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable
|
||||
|
||||
// TIFR1: Timer/Counter Interrupt Flag register
|
||||
TIFR1_ICF1 = 0x8 // Timer/Counter 1 Input Capture Flag
|
||||
TIFR1_OCF1B = 0x4 // Timer/Counter1 Output Compare Flag B
|
||||
TIFR1_OCF1A = 0x2 // Timer/Counter1 Output Compare Flag A
|
||||
TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag
|
||||
|
||||
// TCCR0B: Timer/Counter0 Control Register B
|
||||
TCCR0B_CS02 = 0x4 // Clock Select0 bit 2
|
||||
TCCR0B_CS01 = 0x2 // Clock Select0 bit 1
|
||||
TCCR0B_CS00 = 0x1 // Clock Select0 bit 0
|
||||
|
||||
// TCCR0A: Timer/Counter 0 Control Register A
|
||||
TCCR0A_TCW0 = 0x80 // Timer/Counter Width
|
||||
TCCR0A_ICEN0 = 0x40 // Input Capture Mode Enable
|
||||
TCCR0A_ICNC0 = 0x20 // Input Capture Noise Canceler
|
||||
TCCR0A_ICES0 = 0x10 // Input Capture Edge Select
|
||||
TCCR0A_ICS0 = 0x8 // Input Capture Select
|
||||
TCCR0A_WGM00 = 0x1 // Waveform Generation Mode
|
||||
|
||||
// TCNT0L: Timer Counter 0 Bytes
|
||||
|
||||
// TCNT0H: Timer Counter 0 Bytes
|
||||
TCNT0_TCNT0 = 0xffff // Timer Counter 0 bits
|
||||
|
||||
// OCR0A: Output Compare Register 0A
|
||||
OCR0A_OCR0A = 0xff // Output Compare 0 A bits
|
||||
|
||||
// OCR0B: Output Compare Register B
|
||||
OCR0B_OCR0B = 0xff // Output Compare 0 B bits
|
||||
|
||||
// TIMSK0: Timer/Counter Interrupt Mask Register
|
||||
TIMSK0_ICIE0 = 0x8 // Timer/Counter n Input Capture Interrupt Enable
|
||||
TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare B Interrupt Enable
|
||||
TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare A Interrupt Enable
|
||||
TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable
|
||||
|
||||
// TIFR0: Timer/Counter Interrupt Flag register
|
||||
TIFR0_ICF0 = 0x8 // Timer/Counter 0 Input Capture Flag
|
||||
TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag B
|
||||
TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag A
|
||||
TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag
|
||||
)
|
||||
|
||||
// Bitfields for CELL_BALANCING: Cell Balancing
|
||||
const (
|
||||
// CBCR: Cell Balancing Control Register
|
||||
CBCR_CBE = 0xf // Cell Balancing Enables
|
||||
)
|
||||
|
||||
// Bitfields for BATTERY_PROTECTION: Battery Protection
|
||||
const (
|
||||
// BPPLR: Battery Protection Parameter Lock Register
|
||||
BPPLR_BPPLE = 0x2 // Battery Protection Parameter Lock Enable
|
||||
BPPLR_BPPL = 0x1 // Battery Protection Parameter Lock
|
||||
|
||||
// BPCR: Battery Protection Control Register
|
||||
BPCR_EPID = 0x20 // External Protection Input Disable
|
||||
BPCR_SCD = 0x10 // Short Circuit Protection Disabled
|
||||
BPCR_DOCD = 0x8 // Discharge Over-current Protection Disabled
|
||||
BPCR_COCD = 0x4 // Charge Over-current Protection Disabled
|
||||
BPCR_DHCD = 0x2 // Discharge High-current Protection Disable
|
||||
BPCR_CHCD = 0x1 // Charge High-current Protection Disable
|
||||
|
||||
// BPHCTR: Battery Protection Short-current Timing Register
|
||||
BPHCTR_HCPT = 0x3f // Battery Protection Short-current Timing bits
|
||||
|
||||
// BPOCTR: Battery Protection Over-current Timing Register
|
||||
BPOCTR_OCPT = 0x3f // Battery Protection Over-current Timing bits
|
||||
|
||||
// BPSCTR: Battery Protection Short-current Timing Register
|
||||
BPSCTR_SCPT = 0x7f // Battery Protection Short-current Timing bits
|
||||
|
||||
// BPCHCD: Battery Protection Charge-High-current Detection Level Register
|
||||
BPCHCD_CHCDL = 0xff // Battery Protection Charge-High-current Detection Level bits
|
||||
|
||||
// BPDHCD: Battery Protection Discharge-High-current Detection Level Register
|
||||
BPDHCD_DHCDL = 0xff // Battery Protection Discharge-High-current Detection Level bits
|
||||
|
||||
// BPCOCD: Battery Protection Charge-Over-current Detection Level Register
|
||||
BPCOCD_COCDL = 0xff // Battery Protection Charge-Over-current Detection Level bits
|
||||
|
||||
// BPDOCD: Battery Protection Discharge-Over-current Detection Level Register
|
||||
BPDOCD_DOCDL = 0xff // Battery Protection Discharge-Over-current Detection Level bits
|
||||
|
||||
// BPSCD: Battery Protection Short-Circuit Detection Level Register
|
||||
BPSCD_SCDL = 0xff // Battery Protection Short-Circuit Detection Level Register bits
|
||||
|
||||
// BPIFR: Battery Protection Interrupt Flag Register
|
||||
BPIFR_SCIF = 0x10 // Short-circuit Protection Activated Interrupt Flag
|
||||
BPIFR_DOCIF = 0x8 // Discharge Over-current Protection Activated Interrupt Flag
|
||||
BPIFR_COCIF = 0x4 // Charge Over-current Protection Activated Interrupt Flag
|
||||
BPIFR_DHCIF = 0x2 // Disharge High-current Protection Activated Interrupt
|
||||
BPIFR_CHCIF = 0x1 // Charge High-current Protection Activated Interrupt
|
||||
|
||||
// BPIMSK: Battery Protection Interrupt Mask Register
|
||||
BPIMSK_SCIE = 0x10 // Short-circuit Protection Activated Interrupt Enable
|
||||
BPIMSK_DOCIE = 0x8 // Discharge Over-current Protection Activated Interrupt Enable
|
||||
BPIMSK_COCIE = 0x4 // Charge Over-current Protection Activated Interrupt Enable
|
||||
BPIMSK_DHCIE = 0x2 // Discharger High-current Protection Activated Interrupt
|
||||
BPIMSK_CHCIE = 0x1 // Charger High-current Protection Activated Interrupt
|
||||
)
|
||||
|
||||
// Bitfields for CHARGER_DETECT: Charger Detect
|
||||
const (
|
||||
// CHGDCSR: Charger Detect Control and Status Register
|
||||
CHGDCSR_BATTPVL = 0x10 // BATT Pin Voltage Level
|
||||
CHGDCSR_CHGDISC = 0xc // Charger Detect Interrupt Sense Control
|
||||
CHGDCSR_CHGDIF = 0x2 // Charger Detect Interrupt Flag
|
||||
CHGDCSR_CHGDIE = 0x1 // Charger Detect Interrupt Enable
|
||||
)
|
||||
|
||||
// Bitfields for VOLTAGE_REGULATOR: Voltage Regulator
|
||||
const (
|
||||
// ROCR: Regulator Operating Condition Register
|
||||
ROCR_ROCS = 0x80 // ROC Status
|
||||
ROCR_ROCD = 0x10 // ROC Disable
|
||||
ROCR_ROCWIF = 0x2 // ROC Warning Interrupt Flag
|
||||
ROCR_ROCWIE = 0x1 // ROC Warning Interrupt Enable
|
||||
)
|
||||
|
||||
// Bitfields for BANDGAP: Bandgap
|
||||
const (
|
||||
// BGCSR: Bandgap Control and Status Register
|
||||
BGCSR_BGD = 0x20 // Bandgap Disable
|
||||
BGCSR_BGSCDE = 0x10 // Bandgap Short Circuit Detection Enabled
|
||||
BGCSR_BGSCDIF = 0x2 // Bandgap Short Circuit Detection Interrupt Flag
|
||||
BGCSR_BGSCDIE = 0x1 // Bandgap Short Circuit Detection Interrupt Enable
|
||||
|
||||
// BGCRR: Bandgap Calibration of Resistor Ladder
|
||||
BGCRR_BGCR = 0xff // Bandgap Calibration of Resistor Ladder Bits
|
||||
|
||||
// BGCCR: Bandgap Calibration Register
|
||||
BGCCR_BGCC = 0x3f // BG Calibration of PTAT Current Bits
|
||||
)
|
||||
|
||||
// Bitfields for CPU: CPU Registers
|
||||
const (
|
||||
// SREG: Status Register
|
||||
SREG_I = 0x80 // Global Interrupt Enable
|
||||
SREG_T = 0x40 // Bit Copy Storage
|
||||
SREG_H = 0x20 // Half Carry Flag
|
||||
SREG_S = 0x10 // Sign Bit
|
||||
SREG_V = 0x8 // Two's Complement Overflow Flag
|
||||
SREG_N = 0x4 // Negative Flag
|
||||
SREG_Z = 0x2 // Zero Flag
|
||||
SREG_C = 0x1 // Carry Flag
|
||||
|
||||
// MCUCR: MCU Control Register
|
||||
MCUCR_CKOE = 0x20 // Clock Output Enable
|
||||
MCUCR_PUD = 0x10 // Pull-up disable
|
||||
MCUCR_IVSEL = 0x2 // Interrupt Vector Select
|
||||
MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable
|
||||
|
||||
// MCUSR: MCU Status Register
|
||||
MCUSR_OCDRF = 0x10 // OCD Reset Flag
|
||||
MCUSR_WDRF = 0x8 // Watchdog Reset Flag
|
||||
MCUSR_BODRF = 0x4 // Brown-out Reset Flag
|
||||
MCUSR_EXTRF = 0x2 // External Reset Flag
|
||||
MCUSR_PORF = 0x1 // Power-on reset flag
|
||||
|
||||
// FOSCCAL: Fast Oscillator Calibration Value
|
||||
FOSCCAL_FCAL = 0xff // Fast Oscillator Calibration Value
|
||||
|
||||
// OSICSR: Oscillator Sampling Interface Control and Status Register
|
||||
OSICSR_OSISEL0 = 0x10 // Oscillator Sampling Interface Select 0
|
||||
OSICSR_OSIST = 0x2 // Oscillator Sampling Interface Status
|
||||
OSICSR_OSIEN = 0x1 // Oscillator Sampling Interface Enable
|
||||
|
||||
// SMCR: Sleep Mode Control Register
|
||||
SMCR_SM = 0xe // Sleep Mode Select bits
|
||||
SMCR_SE = 0x1 // Sleep Enable
|
||||
|
||||
// GPIOR2: General Purpose IO Register 2
|
||||
GPIOR2_GPIOR2 = 0xff // General Purpose IO bits
|
||||
|
||||
// GPIOR1: General Purpose IO Register 1
|
||||
GPIOR1_GPIOR1 = 0xff // General Purpose IO bits
|
||||
|
||||
// GPIOR0: General Purpose IO Register 0
|
||||
GPIOR0_GPIOR0 = 0xff // General Purpose IO bits
|
||||
|
||||
// DIDR0: Digital Input Disable Register
|
||||
DIDR0_PA1DID = 0x2 // When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.
|
||||
DIDR0_PA0DID = 0x1 // When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.
|
||||
|
||||
// PRR0: Power Reduction Register 0
|
||||
PRR0_PRTWI = 0x40 // Power Reduction TWI
|
||||
PRR0_PRVRM = 0x20 // Power Reduction Voltage Regulator Monitor
|
||||
PRR0_PRSPI = 0x8 // Power reduction SPI
|
||||
PRR0_PRTIM1 = 0x4 // Power Reduction Timer/Counter1
|
||||
PRR0_PRTIM0 = 0x2 // Power Reduction Timer/Counter0
|
||||
PRR0_PRVADC = 0x1 // Power Reduction V-ADC
|
||||
|
||||
// CLKPR: Clock Prescale Register
|
||||
CLKPR_CLKPCE = 0x80 // Clock Prescaler Change Enable
|
||||
CLKPR_CLKPS = 0x3 // Clock Prescaler Select Bits
|
||||
)
|
||||
|
||||
// Bitfields for BOOT_LOAD: Bootloader
|
||||
const (
|
||||
// SPMCSR: Store Program Memory Control and Status Register
|
||||
SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable
|
||||
SPMCSR_RWWSB = 0x40 // Read-While-Write Section Busy
|
||||
SPMCSR_SIGRD = 0x20 // Signature Row Read
|
||||
SPMCSR_RWWSRE = 0x10 // Read-While-Write Section Read Enable
|
||||
SPMCSR_LBSET = 0x8 // Lock Bit Set
|
||||
SPMCSR_PGWRT = 0x4 // Page Write
|
||||
SPMCSR_PGERS = 0x2 // Page Erase
|
||||
SPMCSR_SPMEN = 0x1 // Store Program Memory Enable
|
||||
)
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from ATmega16HVBrevB.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x4000;
|
||||
__ram_size = 0x400;
|
||||
__num_isrs = 29;
|
||||
Различия файлов не показаны, т.к. их слишком много
Показать различия
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from ATmega16M1.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x4000;
|
||||
__ram_size = 0x400;
|
||||
__num_isrs = 31;
|
||||
|
|
@ -1,842 +0,0 @@
|
|||
// Automatically generated file. DO NOT EDIT.
|
||||
// Generated by gen-device.py from ATmega16U2.atdf, see http://packs.download.atmel.com/
|
||||
|
||||
// +build avr,atmega16u2
|
||||
|
||||
// Device information for the ATmega16U2.
|
||||
//
|
||||
package avr
|
||||
|
||||
// Magic type name for the compiler.
|
||||
type __reg uint8
|
||||
|
||||
// Export this magic type name.
|
||||
type RegValue = __reg
|
||||
|
||||
// Some information about this device.
|
||||
const (
|
||||
DEVICE = "ATmega16U2"
|
||||
ARCH = "AVR8"
|
||||
FAMILY = "megaAVR"
|
||||
)
|
||||
|
||||
// Interrupts
|
||||
const (
|
||||
IRQ_RESET = 0 // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet.
|
||||
IRQ_INT0 = 1 // External Interrupt Request 0
|
||||
IRQ_INT1 = 2 // External Interrupt Request 1
|
||||
IRQ_INT2 = 3 // External Interrupt Request 2
|
||||
IRQ_INT3 = 4 // External Interrupt Request 3
|
||||
IRQ_INT4 = 5 // External Interrupt Request 4
|
||||
IRQ_INT5 = 6 // External Interrupt Request 5
|
||||
IRQ_INT6 = 7 // External Interrupt Request 6
|
||||
IRQ_INT7 = 8 // External Interrupt Request 7
|
||||
IRQ_PCINT0 = 9 // Pin Change Interrupt Request 0
|
||||
IRQ_PCINT1 = 10 // Pin Change Interrupt Request 1
|
||||
IRQ_USB_GEN = 11 // USB General Interrupt Request
|
||||
IRQ_USB_COM = 12 // USB Endpoint/Pipe Interrupt Communication Request
|
||||
IRQ_WDT = 13 // Watchdog Time-out Interrupt
|
||||
IRQ_TIMER1_CAPT = 14 // Timer/Counter2 Capture Event
|
||||
IRQ_TIMER1_COMPA = 15 // Timer/Counter2 Compare Match B
|
||||
IRQ_TIMER1_COMPB = 16 // Timer/Counter2 Compare Match B
|
||||
IRQ_TIMER1_COMPC = 17 // Timer/Counter2 Compare Match C
|
||||
IRQ_TIMER1_OVF = 18 // Timer/Counter1 Overflow
|
||||
IRQ_TIMER0_COMPA = 19 // Timer/Counter0 Compare Match A
|
||||
IRQ_TIMER0_COMPB = 20 // Timer/Counter0 Compare Match B
|
||||
IRQ_TIMER0_OVF = 21 // Timer/Counter0 Overflow
|
||||
IRQ_SPI_STC = 22 // SPI Serial Transfer Complete
|
||||
IRQ_USART1_RX = 23 // USART1, Rx Complete
|
||||
IRQ_USART1_UDRE = 24 // USART1 Data register Empty
|
||||
IRQ_USART1_TX = 25 // USART1, Tx Complete
|
||||
IRQ_ANALOG_COMP = 26 // Analog Comparator
|
||||
IRQ_EE_READY = 27 // EEPROM Ready
|
||||
IRQ_SPM_READY = 28 // Store Program Memory Read
|
||||
IRQ_max = 28 // Highest interrupt number on this device.
|
||||
)
|
||||
|
||||
// Peripherals
|
||||
var (
|
||||
// Fuses
|
||||
FUSE = struct {
|
||||
EXTENDED __reg
|
||||
HIGH __reg
|
||||
LOW __reg
|
||||
}{
|
||||
EXTENDED: 0x2,
|
||||
HIGH: 0x1,
|
||||
LOW: 0x0,
|
||||
}
|
||||
|
||||
// Lockbits
|
||||
LOCKBIT = struct {
|
||||
LOCKBIT __reg
|
||||
}{
|
||||
LOCKBIT: 0x0,
|
||||
}
|
||||
|
||||
// I/O Port
|
||||
PORT = struct {
|
||||
PORTB __reg
|
||||
DDRB __reg
|
||||
PINB __reg
|
||||
PORTD __reg
|
||||
DDRD __reg
|
||||
PIND __reg
|
||||
PORTC __reg
|
||||
DDRC __reg
|
||||
PINC __reg
|
||||
}{
|
||||
PORTB: 0x25, // Port B Data Register
|
||||
DDRB: 0x24, // Port B Data Direction Register
|
||||
PINB: 0x23, // Port B Input Pins
|
||||
PORTD: 0x2b, // Port D Data Register
|
||||
DDRD: 0x2a, // Port D Data Direction Register
|
||||
PIND: 0x29, // Port D Input Pins
|
||||
PORTC: 0x28, // Port C Data Register
|
||||
DDRC: 0x27, // Port C Data Direction Register
|
||||
PINC: 0x26, // Port C Input Pins
|
||||
}
|
||||
|
||||
// Serial Peripheral Interface
|
||||
SPI = struct {
|
||||
SPCR __reg
|
||||
SPSR __reg
|
||||
SPDR __reg
|
||||
}{
|
||||
SPCR: 0x4c, // SPI Control Register
|
||||
SPSR: 0x4d, // SPI Status Register
|
||||
SPDR: 0x4e, // SPI Data Register
|
||||
}
|
||||
|
||||
// Bootloader
|
||||
BOOT_LOAD = struct {
|
||||
SPMCSR __reg
|
||||
}{
|
||||
SPMCSR: 0x57, // Store Program Memory Control Register
|
||||
}
|
||||
|
||||
// EEPROM
|
||||
EEPROM = struct {
|
||||
EEARL __reg
|
||||
EEARH __reg
|
||||
EEDR __reg
|
||||
EECR __reg
|
||||
}{
|
||||
EEARL: 0x41, // EEPROM Address Register Low Bytes
|
||||
EEARH: 0x41, // EEPROM Address Register Low Bytes
|
||||
EEDR: 0x40, // EEPROM Data Register
|
||||
EECR: 0x3f, // EEPROM Control Register
|
||||
}
|
||||
|
||||
// Timer/Counter, 8-bit
|
||||
TC8 = struct {
|
||||
OCR0B __reg
|
||||
OCR0A __reg
|
||||
TCNT0 __reg
|
||||
TCCR0B __reg
|
||||
TCCR0A __reg
|
||||
TIMSK0 __reg
|
||||
TIFR0 __reg
|
||||
GTCCR __reg
|
||||
}{
|
||||
OCR0B: 0x48, // Timer/Counter0 Output Compare Register
|
||||
OCR0A: 0x47, // Timer/Counter0 Output Compare Register
|
||||
TCNT0: 0x46, // Timer/Counter0
|
||||
TCCR0B: 0x45, // Timer/Counter Control Register B
|
||||
TCCR0A: 0x44, // Timer/Counter Control Register A
|
||||
TIMSK0: 0x6e, // Timer/Counter0 Interrupt Mask Register
|
||||
TIFR0: 0x35, // Timer/Counter0 Interrupt Flag register
|
||||
GTCCR: 0x43, // General Timer/Counter Control Register
|
||||
}
|
||||
|
||||
// Timer/Counter, 16-bit
|
||||
TC16 = struct {
|
||||
TCCR1A __reg
|
||||
TCCR1B __reg
|
||||
TCCR1C __reg
|
||||
TCNT1L __reg
|
||||
TCNT1H __reg
|
||||
OCR1AL __reg
|
||||
OCR1AH __reg
|
||||
OCR1BL __reg
|
||||
OCR1BH __reg
|
||||
OCR1CL __reg
|
||||
OCR1CH __reg
|
||||
ICR1L __reg
|
||||
ICR1H __reg
|
||||
TIMSK1 __reg
|
||||
TIFR1 __reg
|
||||
}{
|
||||
TCCR1A: 0x80, // Timer/Counter1 Control Register A
|
||||
TCCR1B: 0x81, // Timer/Counter1 Control Register B
|
||||
TCCR1C: 0x82, // Timer/Counter 1 Control Register C
|
||||
TCNT1L: 0x84, // Timer/Counter1 Bytes
|
||||
TCNT1H: 0x84, // Timer/Counter1 Bytes
|
||||
OCR1AL: 0x88, // Timer/Counter1 Output Compare Register A Bytes
|
||||
OCR1AH: 0x88, // Timer/Counter1 Output Compare Register A Bytes
|
||||
OCR1BL: 0x8a, // Timer/Counter1 Output Compare Register B Bytes
|
||||
OCR1BH: 0x8a, // Timer/Counter1 Output Compare Register B Bytes
|
||||
OCR1CL: 0x8c, // Timer/Counter1 Output Compare Register C Bytes
|
||||
OCR1CH: 0x8c, // Timer/Counter1 Output Compare Register C Bytes
|
||||
ICR1L: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
ICR1H: 0x86, // Timer/Counter1 Input Capture Register Bytes
|
||||
TIMSK1: 0x6f, // Timer/Counter1 Interrupt Mask Register
|
||||
TIFR1: 0x36, // Timer/Counter1 Interrupt Flag register
|
||||
}
|
||||
|
||||
// Phase Locked Loop
|
||||
PLL = struct {
|
||||
PLLCSR __reg
|
||||
}{
|
||||
PLLCSR: 0x49, // PLL Status and Control register
|
||||
}
|
||||
|
||||
// USB Device Registers
|
||||
USB_DEVICE = struct {
|
||||
UPOE __reg
|
||||
UEINT __reg
|
||||
UEBCLX __reg
|
||||
UEDATX __reg
|
||||
UEIENX __reg
|
||||
UESTA1X __reg
|
||||
UESTA0X __reg
|
||||
UECFG1X __reg
|
||||
UECFG0X __reg
|
||||
UECONX __reg
|
||||
UERST __reg
|
||||
UENUM __reg
|
||||
UEINTX __reg
|
||||
UDMFN __reg
|
||||
UDFNUML __reg
|
||||
UDFNUMH __reg
|
||||
UDADDR __reg
|
||||
UDIEN __reg
|
||||
UDINT __reg
|
||||
UDCON __reg
|
||||
USBCON __reg
|
||||
REGCR __reg
|
||||
}{
|
||||
UPOE: 0xfb, // USB Software Output Enable register
|
||||
UEINT: 0xf4, // USB Endpoint Number Interrupt Register
|
||||
UEBCLX: 0xf2, // USB Endpoint Byte Count Register
|
||||
UEDATX: 0xf1, // USB Data Endpoint
|
||||
UEIENX: 0xf0, // USB Endpoint Interrupt Enable Register
|
||||
UESTA1X: 0xef, // USB Endpoint Status 1 Register
|
||||
UESTA0X: 0xee, // USB Endpoint Status 0 Register
|
||||
UECFG1X: 0xed, // USB Endpoint Configuration 1 Register
|
||||
UECFG0X: 0xec, // USB Endpoint Configuration 0 Register
|
||||
UECONX: 0xeb, // USB Endpoint Control Register
|
||||
UERST: 0xea, // USB Endpoint Reset Register
|
||||
UENUM: 0xe9, // USB Endpoint Number
|
||||
UEINTX: 0xe8, // USB Endpoint Interrupt Register
|
||||
UDMFN: 0xe6, // USB Device Micro Frame Number
|
||||
UDFNUML: 0xe4, // USB Device Frame Number High Register
|
||||
UDFNUMH: 0xe4, // USB Device Frame Number High Register
|
||||
UDADDR: 0xe3, // USB Device Address Register
|
||||
UDIEN: 0xe2, // USB Device Interrupt Enable Register
|
||||
UDINT: 0xe1, // USB Device Interrupt Register
|
||||
UDCON: 0xe0, // USB Device Control Registers
|
||||
USBCON: 0xd8, // USB General Control Register
|
||||
REGCR: 0x63, // Regulator Control Register
|
||||
}
|
||||
|
||||
// CPU Registers
|
||||
CPU = struct {
|
||||
SREG __reg
|
||||
SPL __reg
|
||||
SPH __reg
|
||||
MCUCR __reg
|
||||
MCUSR __reg
|
||||
OSCCAL __reg
|
||||
CLKPR __reg
|
||||
SMCR __reg
|
||||
EIND __reg
|
||||
GPIOR2 __reg
|
||||
GPIOR1 __reg
|
||||
GPIOR0 __reg
|
||||
PRR1 __reg
|
||||
PRR0 __reg
|
||||
CLKSTA __reg
|
||||
CLKSEL1 __reg
|
||||
CLKSEL0 __reg
|
||||
DWDR __reg
|
||||
}{
|
||||
SREG: 0x5f, // Status Register
|
||||
SPL: 0x5d, // Stack Pointer
|
||||
SPH: 0x5d, // Stack Pointer
|
||||
MCUCR: 0x55, // MCU Control Register
|
||||
MCUSR: 0x54, // MCU Status Register
|
||||
OSCCAL: 0x66, // Oscillator Calibration Value
|
||||
CLKPR: 0x61,
|
||||
SMCR: 0x53, // Sleep Mode Control Register
|
||||
EIND: 0x5c, // Extended Indirect Register
|
||||
GPIOR2: 0x4b, // General Purpose IO Register 2
|
||||
GPIOR1: 0x4a, // General Purpose IO Register 1
|
||||
GPIOR0: 0x3e, // General Purpose IO Register 0
|
||||
PRR1: 0x65, // Power Reduction Register1
|
||||
PRR0: 0x64, // Power Reduction Register0
|
||||
CLKSTA: 0xd2,
|
||||
CLKSEL1: 0xd1,
|
||||
CLKSEL0: 0xd0,
|
||||
DWDR: 0x51, // debugWire communication register
|
||||
}
|
||||
|
||||
// External Interrupts
|
||||
EXINT = struct {
|
||||
EICRA __reg
|
||||
EICRB __reg
|
||||
EIMSK __reg
|
||||
EIFR __reg
|
||||
PCMSK0 __reg
|
||||
PCMSK1 __reg
|
||||
PCIFR __reg
|
||||
PCICR __reg
|
||||
}{
|
||||
EICRA: 0x69, // External Interrupt Control Register A
|
||||
EICRB: 0x6a, // External Interrupt Control Register B
|
||||
EIMSK: 0x3d, // External Interrupt Mask Register
|
||||
EIFR: 0x3c, // External Interrupt Flag Register
|
||||
PCMSK0: 0x6b, // Pin Change Mask Register 0
|
||||
PCMSK1: 0x6c, // Pin Change Mask Register 1
|
||||
PCIFR: 0x3b, // Pin Change Interrupt Flag Register
|
||||
PCICR: 0x68, // Pin Change Interrupt Control Register
|
||||
}
|
||||
|
||||
// USART
|
||||
USART = struct {
|
||||
UDR1 __reg
|
||||
UCSR1A __reg
|
||||
UCSR1B __reg
|
||||
UCSR1C __reg
|
||||
UCSR1D __reg
|
||||
UBRR1L __reg
|
||||
UBRR1H __reg
|
||||
}{
|
||||
UDR1: 0xce, // USART I/O Data Register
|
||||
UCSR1A: 0xc8, // USART Control and Status Register A
|
||||
UCSR1B: 0xc9, // USART Control and Status Register B
|
||||
UCSR1C: 0xca, // USART Control and Status Register C
|
||||
UCSR1D: 0xcb, // USART Control and Status Register D
|
||||
UBRR1L: 0xcc, // USART Baud Rate Register Bytes
|
||||
UBRR1H: 0xcc, // USART Baud Rate Register Bytes
|
||||
}
|
||||
|
||||
// Watchdog Timer
|
||||
WDT = struct {
|
||||
WDTCSR __reg
|
||||
WDTCKD __reg
|
||||
}{
|
||||
WDTCSR: 0x60, // Watchdog Timer Control Register
|
||||
WDTCKD: 0x62, // Watchdog Timer Clock Divider
|
||||
}
|
||||
|
||||
// Analog Comparator
|
||||
AC = struct {
|
||||
ACSR __reg
|
||||
ACMUX __reg
|
||||
DIDR1 __reg
|
||||
}{
|
||||
ACSR: 0x50, // Analog Comparator Control And Status Register
|
||||
ACMUX: 0x7d, // Analog Comparator Input Multiplexer
|
||||
DIDR1: 0x7f,
|
||||
}
|
||||
)
|
||||
|
||||
// Bitfields for FUSE: Fuses
|
||||
const (
|
||||
// EXTENDED
|
||||
EXTENDED_BODLEVEL = 0x7 // Brown-out Detector trigger level
|
||||
EXTENDED_HWBE = 0x8 // Hardware Boot Enable
|
||||
|
||||
// HIGH
|
||||
HIGH_DWEN = 0x80 // Debug Wire enable
|
||||
HIGH_RSTDISBL = 0x40 // Reset Disabled (Enable PC6 as i/o pin)
|
||||
HIGH_SPIEN = 0x20 // Serial program downloading (SPI) enabled
|
||||
HIGH_WDTON = 0x10 // Watchdog timer always on
|
||||
HIGH_EESAVE = 0x8 // Preserve EEPROM through the Chip Erase cycle
|
||||
HIGH_BOOTSZ = 0x6 // Select Boot Size
|
||||
HIGH_BOOTRST = 0x1 // Boot Reset vector Enabled
|
||||
|
||||
// LOW
|
||||
LOW_CKDIV8 = 0x80 // Divide clock by 8 internally
|
||||
LOW_CKOUT = 0x40 // Clock output on PORTC7
|
||||
LOW_SUT_CKSEL = 0x3f // Select Clock Source
|
||||
)
|
||||
|
||||
// Bitfields for LOCKBIT: Lockbits
|
||||
const (
|
||||
// LOCKBIT
|
||||
LOCKBIT_LB = 0x3 // Memory Lock
|
||||
LOCKBIT_BLB0 = 0xc // Boot Loader Protection Mode
|
||||
LOCKBIT_BLB1 = 0x30 // Boot Loader Protection Mode
|
||||
)
|
||||
|
||||
// Bitfields for PORT: I/O Port
|
||||
const (
|
||||
// PORTC: Port C Data Register
|
||||
PORTC_PORTC = 0xf0 // Port C Data Register bits
|
||||
PORTC_PORTC = 0x7 // Port C Data Register bits
|
||||
|
||||
// DDRC: Port C Data Direction Register
|
||||
DDRC_DDC = 0xf0 // Port C Data Direction Register bits
|
||||
DDRC_DDC = 0x7 // Port C Data Direction Register bits
|
||||
|
||||
// PINC: Port C Input Pins
|
||||
PINC_PINC = 0xf0 // Port C Input Pins bits
|
||||
PINC_PINC = 0x7 // Port C Input Pins bits
|
||||
)
|
||||
|
||||
// Bitfields for SPI: Serial Peripheral Interface
|
||||
const (
|
||||
// SPCR: SPI Control Register
|
||||
SPCR_SPIE = 0x80 // SPI Interrupt Enable
|
||||
SPCR_SPE = 0x40 // SPI Enable
|
||||
SPCR_DORD = 0x20 // Data Order
|
||||
SPCR_MSTR = 0x10 // Master/Slave Select
|
||||
SPCR_CPOL = 0x8 // Clock polarity
|
||||
SPCR_CPHA = 0x4 // Clock Phase
|
||||
SPCR_SPR = 0x3 // SPI Clock Rate Selects
|
||||
|
||||
// SPSR: SPI Status Register
|
||||
SPSR_SPIF = 0x80 // SPI Interrupt Flag
|
||||
SPSR_WCOL = 0x40 // Write Collision Flag
|
||||
SPSR_SPI2X = 0x1 // Double SPI Speed Bit
|
||||
|
||||
// SPDR: SPI Data Register
|
||||
SPDR_SPDR = 0xff // SPI Data bits
|
||||
)
|
||||
|
||||
// Bitfields for BOOT_LOAD: Bootloader
|
||||
const (
|
||||
// SPMCSR: Store Program Memory Control Register
|
||||
SPMCSR_SPMIE = 0x80 // SPM Interrupt Enable
|
||||
SPMCSR_RWWSB = 0x40 // Read While Write Section Busy
|
||||
SPMCSR_SIGRD = 0x20 // Signature Row Read
|
||||
SPMCSR_RWWSRE = 0x10 // Read While Write section read enable
|
||||
SPMCSR_BLBSET = 0x8 // Boot Lock Bit Set
|
||||
SPMCSR_PGWRT = 0x4 // Page Write
|
||||
SPMCSR_PGERS = 0x2 // Page Erase
|
||||
SPMCSR_SPMEN = 0x1 // Store Program Memory Enable
|
||||
)
|
||||
|
||||
// Bitfields for EEPROM: EEPROM
|
||||
const (
|
||||
// EEARL: EEPROM Address Register Low Bytes
|
||||
|
||||
// EEARH: EEPROM Address Register Low Bytes
|
||||
EEAR_EEAR = 0xfff // EEPROM Address bits
|
||||
|
||||
// EEDR: EEPROM Data Register
|
||||
EEDR_EEDR = 0xff // EEPROM Data bits
|
||||
|
||||
// EECR: EEPROM Control Register
|
||||
EECR_EEPM = 0x30 // EEPROM Programming Mode Bits
|
||||
EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable
|
||||
EECR_EEMPE = 0x4 // EEPROM Master Write Enable
|
||||
EECR_EEPE = 0x2 // EEPROM Write Enable
|
||||
EECR_EERE = 0x1 // EEPROM Read Enable
|
||||
)
|
||||
|
||||
// Bitfields for TC8: Timer/Counter, 8-bit
|
||||
const (
|
||||
// OCR0B: Timer/Counter0 Output Compare Register
|
||||
OCR0B_OCR0B = 0xff // Timer/Counter0 Output Compare B bits
|
||||
|
||||
// OCR0A: Timer/Counter0 Output Compare Register
|
||||
OCR0A_OCR0A = 0xff // Timer/Counter0 Output Compare A bits
|
||||
|
||||
// TCNT0: Timer/Counter0
|
||||
TCNT0_TCNT0 = 0xff // Timer/Counter0 bits
|
||||
|
||||
// TCCR0B: Timer/Counter Control Register B
|
||||
TCCR0B_FOC0A = 0x80 // Force Output Compare A
|
||||
TCCR0B_FOC0B = 0x40 // Force Output Compare B
|
||||
TCCR0B_WGM02 = 0x8
|
||||
TCCR0B_CS0 = 0x7 // Clock Select
|
||||
|
||||
// TCCR0A: Timer/Counter Control Register A
|
||||
TCCR0A_COM0A = 0xc0 // Compare Output Mode, Phase Correct PWM Mode
|
||||
TCCR0A_COM0B = 0x30 // Compare Output Mode, Fast PWm
|
||||
TCCR0A_WGM0 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TIMSK0: Timer/Counter0 Interrupt Mask Register
|
||||
TIMSK0_OCIE0B = 0x4 // Timer/Counter0 Output Compare Match B Interrupt Enable
|
||||
TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match A Interrupt Enable
|
||||
TIMSK0_TOIE0 = 0x1 // Timer/Counter0 Overflow Interrupt Enable
|
||||
|
||||
// TIFR0: Timer/Counter0 Interrupt Flag register
|
||||
TIFR0_OCF0B = 0x4 // Timer/Counter0 Output Compare Flag 0B
|
||||
TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0A
|
||||
TIFR0_TOV0 = 0x1 // Timer/Counter0 Overflow Flag
|
||||
|
||||
// GTCCR: General Timer/Counter Control Register
|
||||
GTCCR_TSM = 0x80 // Timer/Counter Synchronization Mode
|
||||
GTCCR_PSRSYNC = 0x1 // Prescaler Reset Timer/Counter1 and Timer/Counter0
|
||||
)
|
||||
|
||||
// Bitfields for TC16: Timer/Counter, 16-bit
|
||||
const (
|
||||
// TCCR1A: Timer/Counter1 Control Register A
|
||||
TCCR1A_COM1A = 0xc0 // Compare Output Mode 1A, bits
|
||||
TCCR1A_COM1B = 0x30 // Compare Output Mode 1B, bits
|
||||
TCCR1A_COM1C = 0xc // Compare Output Mode 1C, bits
|
||||
TCCR1A_WGM1 = 0x3 // Waveform Generation Mode
|
||||
|
||||
// TCCR1B: Timer/Counter1 Control Register B
|
||||
TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler
|
||||
TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select
|
||||
TCCR1B_WGM1 = 0x18 // Waveform Generation Mode
|
||||
TCCR1B_CS1 = 0x7 // Prescaler source of Timer/Counter 1
|
||||
|
||||
// TCCR1C: Timer/Counter 1 Control Register C
|
||||
TCCR1C_FOC1A = 0x80 // Force Output Compare 1A
|
||||
TCCR1C_FOC1B = 0x40 // Force Output Compare 1B
|
||||
TCCR1C_FOC1C = 0x20 // Force Output Compare 1C
|
||||
|
||||
// TCNT1L: Timer/Counter1 Bytes
|
||||
|
||||
// TCNT1H: Timer/Counter1 Bytes
|
||||
TCNT1_TCNT1 = 0xffff // Timer/Counter1 bits
|
||||
|
||||
// OCR1AL: Timer/Counter1 Output Compare Register A Bytes
|
||||
|
||||
// OCR1AH: Timer/Counter1 Output Compare Register A Bytes
|
||||
OCR1A_OCR1A = 0xffff // Timer/Counter1 Output Compare A bits
|
||||
|
||||
// OCR1BL: Timer/Counter1 Output Compare Register B Bytes
|
||||
|
||||
// OCR1BH: Timer/Counter1 Output Compare Register B Bytes
|
||||
OCR1B_OCR1B = 0xffff // Timer/Counter1 Output Compare B bits
|
||||
|
||||
// OCR1CL: Timer/Counter1 Output Compare Register C Bytes
|
||||
|
||||
// OCR1CH: Timer/Counter1 Output Compare Register C Bytes
|
||||
OCR1C_OCR1C = 0xffff // Timer/Counter1 Output Compare C bits
|
||||
|
||||
// ICR1L: Timer/Counter1 Input Capture Register Bytes
|
||||
|
||||
// ICR1H: Timer/Counter1 Input Capture Register Bytes
|
||||
ICR1_ICR1 = 0xffff // Timer/Counter1 Input Capture bits
|
||||
|
||||
// TIMSK1: Timer/Counter1 Interrupt Mask Register
|
||||
TIMSK1_ICIE1 = 0x20 // Timer/Counter1 Input Capture Interrupt Enable
|
||||
TIMSK1_OCIE1C = 0x8 // Timer/Counter1 Output Compare C Match Interrupt Enable
|
||||
TIMSK1_OCIE1B = 0x4 // Timer/Counter1 Output Compare B Match Interrupt Enable
|
||||
TIMSK1_OCIE1A = 0x2 // Timer/Counter1 Output Compare A Match Interrupt Enable
|
||||
TIMSK1_TOIE1 = 0x1 // Timer/Counter1 Overflow Interrupt Enable
|
||||
|
||||
// TIFR1: Timer/Counter1 Interrupt Flag register
|
||||
TIFR1_ICF1 = 0x20 // Input Capture Flag 1
|
||||
TIFR1_OCF1C = 0x8 // Output Compare Flag 1C
|
||||
TIFR1_OCF1B = 0x4 // Output Compare Flag 1B
|
||||
TIFR1_OCF1A = 0x2 // Output Compare Flag 1A
|
||||
TIFR1_TOV1 = 0x1 // Timer/Counter1 Overflow Flag
|
||||
)
|
||||
|
||||
// Bitfields for PLL: Phase Locked Loop
|
||||
const (
|
||||
// PLLCSR: PLL Status and Control register
|
||||
PLLCSR_PLLP = 0x1c // PLL prescaler Bits
|
||||
PLLCSR_PLLE = 0x2 // PLL Enable Bit
|
||||
PLLCSR_PLOCK = 0x1 // PLL Lock Status Bit
|
||||
)
|
||||
|
||||
// Bitfields for USB_DEVICE: USB Device Registers
|
||||
const (
|
||||
// UPOE: USB Software Output Enable register
|
||||
UPOE_UPWE = 0xc0 // USB Buffers Direct Drive enable configuration
|
||||
UPOE_UPDRV = 0x30 // USB direct drive values
|
||||
UPOE_DPI = 0x2 // D+ Input value
|
||||
UPOE_DMI = 0x1 // D- Input value
|
||||
|
||||
// UEINT: USB Endpoint Number Interrupt Register
|
||||
UEINT_EPINT = 0x1f // Byte Count bits
|
||||
|
||||
// UEBCLX: USB Endpoint Byte Count Register
|
||||
UEBCLX_BYCT = 0xff // Byte Count bits
|
||||
|
||||
// UEDATX: USB Data Endpoint
|
||||
UEDATX_DAT = 0xff // Data bits
|
||||
|
||||
// UEIENX: USB Endpoint Interrupt Enable Register
|
||||
UEIENX_FLERRE = 0x80 // Flow Error Interrupt Enable Flag
|
||||
UEIENX_NAKINE = 0x40 // NAK IN Interrupt Enable Bit
|
||||
UEIENX_NAKOUTE = 0x10 // NAK OUT Interrupt Enable Bit
|
||||
UEIENX_RXSTPE = 0x8 // Received SETUP Interrupt Enable Flag
|
||||
UEIENX_RXOUTE = 0x4 // Received OUT Data Interrupt Enable Flag
|
||||
UEIENX_STALLEDE = 0x2 // Stalled Interrupt Enable Flag
|
||||
UEIENX_TXINE = 0x1 // Transmitter Ready Interrupt Enable Flag
|
||||
|
||||
// UESTA1X: USB Endpoint Status 1 Register
|
||||
UESTA1X_CTRLDIR = 0x4 // Control Direction
|
||||
UESTA1X_CURRBK = 0x3 // Current Bank
|
||||
|
||||
// UESTA0X: USB Endpoint Status 0 Register
|
||||
UESTA0X_CFGOK = 0x80 // Configuration Status Flag
|
||||
UESTA0X_OVERFI = 0x40 // Overflow Error Interrupt Flag
|
||||
UESTA0X_UNDERFI = 0x20 // Underflow Error Interrupt Flag
|
||||
UESTA0X_DTSEQ = 0xc // Data Toggle Sequencing Flag
|
||||
UESTA0X_NBUSYBK = 0x3 // Busy Bank Flag
|
||||
|
||||
// UECFG1X: USB Endpoint Configuration 1 Register
|
||||
UECFG1X_EPSIZE = 0x70 // Endpoint Size Bits
|
||||
UECFG1X_EPBK = 0xc // Endpoint Bank Bits
|
||||
UECFG1X_ALLOC = 0x2 // Endpoint Allocation Bit
|
||||
|
||||
// UECFG0X: USB Endpoint Configuration 0 Register
|
||||
UECFG0X_EPTYPE = 0xc0 // Endpoint Type Bits
|
||||
UECFG0X_EPDIR = 0x1 // Endpoint Direction Bit
|
||||
|
||||
// UECONX: USB Endpoint Control Register
|
||||
UECONX_STALLRQ = 0x20 // STALL Request Handshake Bit
|
||||
UECONX_STALLRQC = 0x10 // STALL Request Clear Handshake Bit
|
||||
UECONX_RSTDT = 0x8 // Reset Data Toggle Bit
|
||||
UECONX_EPEN = 0x1 // Endpoint Enable Bit
|
||||
|
||||
// UERST: USB Endpoint Reset Register
|
||||
UERST_EPRST = 0x1f // Endpoint FIFO Reset Bits
|
||||
|
||||
// UENUM: USB Endpoint Number
|
||||
UENUM_EPNUM = 0x7 // Endpoint Number bits
|
||||
|
||||
// UEINTX: USB Endpoint Interrupt Register
|
||||
UEINTX_FIFOCON = 0x80 // FIFO Control Bit
|
||||
UEINTX_NAKINI = 0x40 // NAK IN Received Interrupt Flag
|
||||
UEINTX_RWAL = 0x20 // Read/Write Allowed Flag
|
||||
UEINTX_NAKOUTI = 0x10 // NAK OUT Received Interrupt Flag
|
||||
UEINTX_RXSTPI = 0x8 // Received SETUP Interrupt Flag
|
||||
UEINTX_RXOUTI = 0x4 // Received OUT Data Interrupt Flag
|
||||
UEINTX_STALLEDI = 0x2 // STALLEDI Interrupt Flag
|
||||
UEINTX_TXINI = 0x1 // Transmitter Ready Interrupt Flag
|
||||
|
||||
// UDMFN: USB Device Micro Frame Number
|
||||
UDMFN_FNCERR = 0x10 // Frame Number CRC Error Flag
|
||||
|
||||
// UDFNUML: USB Device Frame Number High Register
|
||||
|
||||
// UDFNUMH: USB Device Frame Number High Register
|
||||
UDFNUM_FNUM = 0x7ff // Frame Number Upper Flag
|
||||
|
||||
// UDADDR: USB Device Address Register
|
||||
UDADDR_ADDEN = 0x80 // Address Enable Bit
|
||||
UDADDR_UADD = 0x7f // USB Address Bits
|
||||
|
||||
// UDIEN: USB Device Interrupt Enable Register
|
||||
UDIEN_UPRSME = 0x40 // Upstream Resume Interrupt Enable Bit
|
||||
UDIEN_EORSME = 0x20 // End Of Resume Interrupt Enable Bit
|
||||
UDIEN_WAKEUPE = 0x10 // Wake-up CPU Interrupt Enable Bit
|
||||
UDIEN_EORSTE = 0x8 // End Of Reset Interrupt Enable Bit
|
||||
UDIEN_SOFE = 0x4 // Start Of Frame Interrupt Enable Bit
|
||||
UDIEN_SUSPE = 0x1 // Suspend Interrupt Enable Bit
|
||||
|
||||
// UDINT: USB Device Interrupt Register
|
||||
UDINT_UPRSMI = 0x40 // Upstream Resume Interrupt Flag
|
||||
UDINT_EORSMI = 0x20 // End Of Resume Interrupt Flag
|
||||
UDINT_WAKEUPI = 0x10 // Wake-up CPU Interrupt Flag
|
||||
UDINT_EORSTI = 0x8 // End Of Reset Interrupt Flag
|
||||
UDINT_SOFI = 0x4 // Start Of Frame Interrupt Flag
|
||||
UDINT_SUSPI = 0x1 // Suspend Interrupt Flag
|
||||
|
||||
// UDCON: USB Device Control Registers
|
||||
UDCON_RSTCPU = 0x4 // USB Reset CPU Bit
|
||||
UDCON_RMWKUP = 0x2 // Remote Wake-up Bit
|
||||
UDCON_DETACH = 0x1 // Detach Bit
|
||||
|
||||
// USBCON: USB General Control Register
|
||||
USBCON_USBE = 0x80 // USB macro Enable Bit
|
||||
USBCON_FRZCLK = 0x20 // Freeze USB Clock Bit
|
||||
|
||||
// REGCR: Regulator Control Register
|
||||
REGCR_REGDIS = 0x1 // Regulator Disable
|
||||
)
|
||||
|
||||
// Bitfields for CPU: CPU Registers
|
||||
const (
|
||||
// SREG: Status Register
|
||||
SREG_I = 0x80 // Global Interrupt Enable
|
||||
SREG_T = 0x40 // Bit Copy Storage
|
||||
SREG_H = 0x20 // Half Carry Flag
|
||||
SREG_S = 0x10 // Sign Bit
|
||||
SREG_V = 0x8 // Two's Complement Overflow Flag
|
||||
SREG_N = 0x4 // Negative Flag
|
||||
SREG_Z = 0x2 // Zero Flag
|
||||
SREG_C = 0x1 // Carry Flag
|
||||
|
||||
// MCUCR: MCU Control Register
|
||||
MCUCR_PUD = 0x10 // Pull-up disable
|
||||
MCUCR_IVSEL = 0x2 // Interrupt Vector Select
|
||||
MCUCR_IVCE = 0x1 // Interrupt Vector Change Enable
|
||||
|
||||
// MCUSR: MCU Status Register
|
||||
MCUSR_USBRF = 0x20 // USB reset flag
|
||||
MCUSR_WDRF = 0x8 // Watchdog Reset Flag
|
||||
MCUSR_BORF = 0x4 // Brown-out Reset Flag
|
||||
MCUSR_EXTRF = 0x2 // External Reset Flag
|
||||
MCUSR_PORF = 0x1 // Power-on reset flag
|
||||
|
||||
// OSCCAL: Oscillator Calibration Value
|
||||
OSCCAL_OSCCAL = 0xff // Oscillator Calibration
|
||||
|
||||
// CLKPR
|
||||
CLKPR_CLKPCE = 0x80
|
||||
CLKPR_CLKPS = 0xf
|
||||
|
||||
// SMCR: Sleep Mode Control Register
|
||||
SMCR_SM = 0xe // Sleep Mode Select bits
|
||||
SMCR_SE = 0x1 // Sleep Enable
|
||||
|
||||
// GPIOR2: General Purpose IO Register 2
|
||||
GPIOR2_GPIOR = 0xff // General Purpose IO Register 2 bis
|
||||
|
||||
// GPIOR1: General Purpose IO Register 1
|
||||
GPIOR1_GPIOR = 0xff // General Purpose IO Register 1 bis
|
||||
|
||||
// GPIOR0: General Purpose IO Register 0
|
||||
GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7
|
||||
GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6
|
||||
GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5
|
||||
GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4
|
||||
GPIOR0_GPIOR03 = 0x8 // General Purpose IO Register 0 bit 3
|
||||
GPIOR0_GPIOR02 = 0x4 // General Purpose IO Register 0 bit 2
|
||||
GPIOR0_GPIOR01 = 0x2 // General Purpose IO Register 0 bit 1
|
||||
GPIOR0_GPIOR00 = 0x1 // General Purpose IO Register 0 bit 0
|
||||
|
||||
// PRR1: Power Reduction Register1
|
||||
PRR1_PRUSB = 0x80 // Power Reduction USB
|
||||
PRR1_PRUSART1 = 0x1 // Power Reduction USART1
|
||||
|
||||
// PRR0: Power Reduction Register0
|
||||
PRR0_PRTIM0 = 0x20 // Power Reduction Timer/Counter0
|
||||
PRR0_PRTIM1 = 0x8 // Power Reduction Timer/Counter1
|
||||
PRR0_PRSPI = 0x4 // Power Reduction Serial Peripheral Interface
|
||||
|
||||
// CLKSTA
|
||||
CLKSTA_RCON = 0x2
|
||||
CLKSTA_EXTON = 0x1
|
||||
|
||||
// CLKSEL1
|
||||
CLKSEL1_RCCKSEL = 0xf0
|
||||
CLKSEL1_EXCKSEL = 0xf
|
||||
|
||||
// CLKSEL0
|
||||
CLKSEL0_RCSUT = 0xc0
|
||||
CLKSEL0_EXSUT = 0x30
|
||||
CLKSEL0_RCE = 0x8
|
||||
CLKSEL0_EXTE = 0x4
|
||||
CLKSEL0_CLKS = 0x1
|
||||
)
|
||||
|
||||
// Bitfields for EXINT: External Interrupts
|
||||
const (
|
||||
// EICRA: External Interrupt Control Register A
|
||||
EICRA_ISC3 = 0xc0 // External Interrupt Sense Control Bit
|
||||
EICRA_ISC2 = 0x30 // External Interrupt Sense Control Bit
|
||||
EICRA_ISC1 = 0xc // External Interrupt Sense Control Bit
|
||||
EICRA_ISC0 = 0x3 // External Interrupt Sense Control Bit
|
||||
|
||||
// EICRB: External Interrupt Control Register B
|
||||
EICRB_ISC7 = 0xc0 // External Interrupt 7-4 Sense Control Bit
|
||||
EICRB_ISC6 = 0x30 // External Interrupt 7-4 Sense Control Bit
|
||||
EICRB_ISC5 = 0xc // External Interrupt 7-4 Sense Control Bit
|
||||
EICRB_ISC4 = 0x3 // External Interrupt 7-4 Sense Control Bit
|
||||
|
||||
// EIMSK: External Interrupt Mask Register
|
||||
EIMSK_INT = 0xff // External Interrupt Request 7 Enable
|
||||
|
||||
// EIFR: External Interrupt Flag Register
|
||||
EIFR_INTF = 0xff // External Interrupt Flags
|
||||
|
||||
// PCMSK0: Pin Change Mask Register 0
|
||||
PCMSK0_PCINT = 0xff // Pin Change Enable Masks
|
||||
|
||||
// PCMSK1: Pin Change Mask Register 1
|
||||
PCMSK1_PCINT = 0x1f
|
||||
|
||||
// PCIFR: Pin Change Interrupt Flag Register
|
||||
PCIFR_PCIF = 0x3 // Pin Change Interrupt Flags
|
||||
|
||||
// PCICR: Pin Change Interrupt Control Register
|
||||
PCICR_PCIE = 0x3 // Pin Change Interrupt Enables
|
||||
)
|
||||
|
||||
// Bitfields for USART: USART
|
||||
const (
|
||||
// UDR1: USART I/O Data Register
|
||||
UDR1_UDR1 = 0xff // USART I/O Data bits
|
||||
|
||||
// UCSR1A: USART Control and Status Register A
|
||||
UCSR1A_RXC1 = 0x80 // USART Receive Complete
|
||||
UCSR1A_TXC1 = 0x40 // USART Transmitt Complete
|
||||
UCSR1A_UDRE1 = 0x20 // USART Data Register Empty
|
||||
UCSR1A_FE1 = 0x10 // Framing Error
|
||||
UCSR1A_DOR1 = 0x8 // Data overRun
|
||||
UCSR1A_UPE1 = 0x4 // Parity Error
|
||||
UCSR1A_U2X1 = 0x2 // Double the USART transmission speed
|
||||
UCSR1A_MPCM1 = 0x1 // Multi-processor Communication Mode
|
||||
|
||||
// UCSR1B: USART Control and Status Register B
|
||||
UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable
|
||||
UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable
|
||||
UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable
|
||||
UCSR1B_RXEN1 = 0x10 // Receiver Enable
|
||||
UCSR1B_TXEN1 = 0x8 // Transmitter Enable
|
||||
UCSR1B_UCSZ12 = 0x4 // Character Size
|
||||
UCSR1B_RXB81 = 0x2 // Receive Data Bit 8
|
||||
UCSR1B_TXB81 = 0x1 // Transmit Data Bit 8
|
||||
|
||||
// UCSR1C: USART Control and Status Register C
|
||||
UCSR1C_UMSEL1 = 0xc0 // USART Mode Select
|
||||
UCSR1C_UPM1 = 0x30 // Parity Mode Bits
|
||||
UCSR1C_USBS1 = 0x8 // Stop Bit Select
|
||||
UCSR1C_UCSZ1 = 0x6 // Character Size
|
||||
UCSR1C_UCPOL1 = 0x1 // Clock Polarity
|
||||
|
||||
// UCSR1D: USART Control and Status Register D
|
||||
UCSR1D_CTSEN = 0x2 // CTS Enable
|
||||
UCSR1D_RTSEN = 0x1 // RTS Enable
|
||||
|
||||
// UBRR1L: USART Baud Rate Register Bytes
|
||||
|
||||
// UBRR1H: USART Baud Rate Register Bytes
|
||||
UBRR1_UBRR1 = 0xfff // USART Baud Rate bits
|
||||
)
|
||||
|
||||
// Bitfields for WDT: Watchdog Timer
|
||||
const (
|
||||
// WDTCSR: Watchdog Timer Control Register
|
||||
WDTCSR_WDIF = 0x80 // Watchdog Timeout Interrupt Flag
|
||||
WDTCSR_WDIE = 0x40 // Watchdog Timeout Interrupt Enable
|
||||
WDTCSR_WDP = 0x27 // Watchdog Timer Prescaler Bits
|
||||
WDTCSR_WDCE = 0x10 // Watchdog Change Enable
|
||||
WDTCSR_WDE = 0x8 // Watch Dog Enable
|
||||
|
||||
// WDTCKD: Watchdog Timer Clock Divider
|
||||
WDTCKD_WDEWIF = 0x8 // Watchdog Early Warning Interrupt Flag
|
||||
WDTCKD_WDEWIE = 0x4 // Watchdog Early Warning Interrupt Enable
|
||||
WDTCKD_WCLKD = 0x3 // Watchdog Timer Clock Dividers
|
||||
)
|
||||
|
||||
// Bitfields for AC: Analog Comparator
|
||||
const (
|
||||
// ACSR: Analog Comparator Control And Status Register
|
||||
ACSR_ACD = 0x80 // Analog Comparator Disable
|
||||
ACSR_ACBG = 0x40 // Analog Comparator Bandgap Select
|
||||
ACSR_ACO = 0x20 // Analog Compare Output
|
||||
ACSR_ACI = 0x10 // Analog Comparator Interrupt Flag
|
||||
ACSR_ACIE = 0x8 // Analog Comparator Interrupt Enable
|
||||
ACSR_ACIC = 0x4 // Analog Comparator Input Capture Enable
|
||||
ACSR_ACIS = 0x3 // Analog Comparator Interrupt Mode Select bits
|
||||
|
||||
// ACMUX: Analog Comparator Input Multiplexer
|
||||
ACMUX_CMUX = 0x7 // Analog Comparator Selection Bits
|
||||
|
||||
// DIDR1
|
||||
DIDR1_AIN7D = 0x80 // AIN7 Digital Input Disable
|
||||
DIDR1_AIN6D = 0x40 // AIN6 Digital Input Disable
|
||||
DIDR1_AIN5D = 0x20 // AIN5 Digital Input Disable
|
||||
DIDR1_AIN4D = 0x10 // AIN4 Digital Input Disable
|
||||
DIDR1_AIN3D = 0x8 // AIN3 Digital Input Disable
|
||||
DIDR1_AIN2D = 0x4 // AIN2 Digital Input Disable
|
||||
DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable
|
||||
DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable
|
||||
)
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from ATmega16U2.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x4000;
|
||||
__ram_size = 0x200;
|
||||
__num_isrs = 29;
|
||||
Различия файлов не показаны, т.к. их слишком много
Показать различия
|
|
@ -1,6 +0,0 @@
|
|||
/* Automatically generated file. DO NOT EDIT. */
|
||||
/* Generated by gen-device.py from ATmega16U4.atdf, see http://packs.download.atmel.com/ */
|
||||
|
||||
__flash_size = 0x4000;
|
||||
__ram_size = 0x500;
|
||||
__num_isrs = 43;
|
||||
Показаны не все изменённые файлы, т.к. их слишком много Показать больше
Загрузка…
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