af00e218a8
This is necessary to support the ESP32-C3, which lacks the A (atomic) extension and thus requires these 32-bit atomic operations. With this commit, flashing ./testdata/atomic.go to the ESP32-C3 works correctly and produces the expected output on the serial console.
137 строки
3,5 КиБ
Go
137 строки
3,5 КиБ
Go
// +build tinygo.riscv
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package runtime
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import "device/riscv"
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func getCurrentStackPointer() uintptr {
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return riscv.AsmFull("mv {}, sp", nil)
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}
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// Documentation:
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// * https://llvm.org/docs/Atomics.html
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// * https://gcc.gnu.org/onlinedocs/gcc/_005f_005fsync-Builtins.html
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//
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// In the case of RISC-V, some operations may be implemented with libcalls if
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// the operation is too big to be handled by assembly. Officially, these calls
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// should be implemented with a lock-free algorithm but as (as of this time) all
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// supported RISC-V chips have a single hart, we can simply disable interrupts
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// to get the same behavior.
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//export __atomic_load_4
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func __atomic_load_4(ptr *uint32, ordering int32) uint32 {
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mask := riscv.DisableInterrupts()
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value := *ptr
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riscv.EnableInterrupts(mask)
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return value
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}
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//export __atomic_store_4
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func __atomic_store_4(ptr *uint32, value uint32, ordering int32) {
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mask := riscv.DisableInterrupts()
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*ptr = value
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riscv.EnableInterrupts(mask)
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}
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//export __atomic_exchange_4
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func __atomic_exchange_4(ptr *uint32, value uint32, ordering int32) uint32 {
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mask := riscv.DisableInterrupts()
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oldValue := *ptr
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*ptr = value
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riscv.EnableInterrupts(mask)
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return oldValue
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}
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//export __atomic_compare_exchange_4
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func __atomic_compare_exchange_4(ptr, expected *uint32, desired uint32, success_ordering, failure_ordering int32) bool {
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mask := riscv.DisableInterrupts()
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oldValue := *ptr
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success := oldValue == *expected
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if success {
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*ptr = desired
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} else {
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*expected = oldValue
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}
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riscv.EnableInterrupts(mask)
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return success
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}
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//export __atomic_fetch_add_4
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func __atomic_fetch_add_4(ptr *uint32, value uint32, ordering int32) uint32 {
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mask := riscv.DisableInterrupts()
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oldValue := *ptr
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*ptr = oldValue + value
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riscv.EnableInterrupts(mask)
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return oldValue
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}
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//export __atomic_load_8
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func __atomic_load_8(ptr *uint64, ordering int32) uint64 {
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mask := riscv.DisableInterrupts()
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value := *ptr
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riscv.EnableInterrupts(mask)
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return value
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}
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//export __atomic_store_8
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func __atomic_store_8(ptr *uint64, value uint64, ordering int32) {
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mask := riscv.DisableInterrupts()
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*ptr = value
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riscv.EnableInterrupts(mask)
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}
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//export __atomic_exchange_8
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func __atomic_exchange_8(ptr *uint64, value uint64, ordering int32) uint64 {
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mask := riscv.DisableInterrupts()
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oldValue := *ptr
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*ptr = value
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riscv.EnableInterrupts(mask)
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return oldValue
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}
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//export __atomic_compare_exchange_8
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func __atomic_compare_exchange_8(ptr, expected *uint64, desired uint64, success_ordering, failure_ordering int32) bool {
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mask := riscv.DisableInterrupts()
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oldValue := *ptr
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success := oldValue == *expected
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if success {
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*ptr = desired
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} else {
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*expected = oldValue
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}
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riscv.EnableInterrupts(mask)
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return success
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}
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//export __atomic_fetch_add_8
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func __atomic_fetch_add_8(ptr *uint64, value uint64, ordering int32) uint64 {
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mask := riscv.DisableInterrupts()
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oldValue := *ptr
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*ptr = oldValue + value
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riscv.EnableInterrupts(mask)
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return oldValue
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}
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// The safest thing to do here would just be to disable interrupts for
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// procPin/procUnpin. Note that a global variable is safe in this case, as any
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// access to procPinnedMask will happen with interrupts disabled.
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var procPinnedMask uintptr
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//go:linkname procPin sync/atomic.runtime_procPin
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func procPin() {
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procPinnedMask = riscv.DisableInterrupts()
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}
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//go:linkname procUnpin sync/atomic.runtime_procUnpin
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func procUnpin() {
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riscv.EnableInterrupts(procPinnedMask)
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}
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func waitForEvents() {
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mask := riscv.DisableInterrupts()
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if !runqueue.Empty() {
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riscv.Asm("wfi")
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}
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riscv.EnableInterrupts(mask)
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}
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