677 строки
18 КиБ
Go
677 строки
18 КиБ
Go
// +build stm32f7
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package machine
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// Peripheral abstraction layer for the stm32f4
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import (
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"device/stm32"
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"runtime/interrupt"
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"runtime/volatile"
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"unsafe"
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)
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// Alternative peripheral pin functions
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const (
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AF0_SYSTEM = 0
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AF1_TIM1_2 = 1
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AF2_TIM3_4_5 = 2
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AF3_TIM8_9_10_11_LPTIM1 = 3
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AF4_I2C1_2_3_USART1 = 4
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AF5_SPI1_2_3_4_5_I2S1_2_3 = 5
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AF6_SPI2_3_I2S2_3_SAI1_UART4 = 6
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AF7_SPI2_3_I2S2_3_USART1_2_3_UART5 = 7
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AF8_SAI2_USART6_UART4_5_7_8_OTG1_FS = 8
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AF9_CAN1_TIM12_13_14_QUADSPI_FMC_OTG2_HS = 9
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AF10_SAI2_QUADSPI_SDMMC2_OTG2_HS_OTG1_FS = 10
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AF11_SDMMC2 = 11
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AF12_UART7_FMC_SDMMC1_OTG2_FS = 12
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AF15_EVENTOUT = 15
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)
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const (
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PA0 = portA + 0
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PA1 = portA + 1
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PA2 = portA + 2
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PA3 = portA + 3
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PA4 = portA + 4
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PA5 = portA + 5
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PA6 = portA + 6
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PA7 = portA + 7
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PA8 = portA + 8
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PA9 = portA + 9
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PA10 = portA + 10
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PA11 = portA + 11
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PA12 = portA + 12
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PA13 = portA + 13
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PA14 = portA + 14
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PA15 = portA + 15
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PB0 = portB + 0
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PB1 = portB + 1
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PB2 = portB + 2
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PB3 = portB + 3
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PB4 = portB + 4
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PB5 = portB + 5
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PB6 = portB + 6
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PB7 = portB + 7
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PB8 = portB + 8
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PB9 = portB + 9
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PB10 = portB + 10
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PB11 = portB + 11
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PB12 = portB + 12
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PB13 = portB + 13
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PB14 = portB + 14
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PB15 = portB + 15
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PC0 = portC + 0
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PC1 = portC + 1
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PC2 = portC + 2
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PC3 = portC + 3
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PC4 = portC + 4
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PC5 = portC + 5
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PC6 = portC + 6
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PC7 = portC + 7
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PC8 = portC + 8
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PC9 = portC + 9
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PC10 = portC + 10
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PC11 = portC + 11
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PC12 = portC + 12
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PC13 = portC + 13
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PC14 = portC + 14
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PC15 = portC + 15
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PD0 = portD + 0
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PD1 = portD + 1
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PD2 = portD + 2
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PD3 = portD + 3
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PD4 = portD + 4
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PD5 = portD + 5
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PD6 = portD + 6
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PD7 = portD + 7
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PD8 = portD + 8
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PD9 = portD + 9
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PD10 = portD + 10
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PD11 = portD + 11
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PD12 = portD + 12
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PD13 = portD + 13
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PD14 = portD + 14
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PD15 = portD + 15
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PE0 = portE + 0
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PE1 = portE + 1
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PE2 = portE + 2
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PE3 = portE + 3
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PE4 = portE + 4
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PE5 = portE + 5
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PE6 = portE + 6
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PE7 = portE + 7
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PE8 = portE + 8
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PE9 = portE + 9
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PE10 = portE + 10
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PE11 = portE + 11
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PE12 = portE + 12
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PE13 = portE + 13
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PE14 = portE + 14
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PE15 = portE + 15
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PF0 = portF + 0
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PF1 = portF + 1
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PF2 = portF + 2
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PF3 = portF + 3
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PF4 = portF + 4
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PF5 = portF + 5
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PF6 = portF + 6
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PF7 = portF + 7
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PF8 = portF + 8
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PF9 = portF + 9
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PF10 = portF + 10
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PF11 = portF + 11
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PF12 = portF + 12
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PF13 = portF + 13
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PF14 = portF + 14
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PF15 = portF + 15
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PG0 = portG + 0
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PG1 = portG + 1
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PG2 = portG + 2
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PG3 = portG + 3
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PG4 = portG + 4
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PG5 = portG + 5
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PG6 = portG + 6
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PG7 = portG + 7
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PG8 = portG + 8
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PG9 = portG + 9
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PG10 = portG + 10
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PG11 = portG + 11
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PG12 = portG + 12
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PG13 = portG + 13
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PG14 = portG + 14
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PG15 = portG + 15
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PH0 = portH + 0
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PH1 = portH + 1
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PH2 = portH + 2
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PH3 = portH + 3
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PH4 = portH + 4
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PH5 = portH + 5
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PH6 = portH + 6
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PH7 = portH + 7
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PH8 = portH + 8
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PH9 = portH + 9
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PH10 = portH + 10
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PH11 = portH + 11
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PH12 = portH + 12
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PH13 = portH + 13
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PH14 = portH + 14
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PH15 = portH + 15
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PI0 = portI + 0
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PI1 = portI + 1
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PI2 = portI + 2
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PI3 = portI + 3
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PI4 = portI + 4
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PI5 = portI + 5
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PI6 = portI + 6
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PI7 = portI + 7
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PI8 = portI + 8
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PI9 = portI + 9
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PI10 = portI + 10
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PI11 = portI + 11
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PI12 = portI + 12
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PI13 = portI + 13
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PI14 = portI + 14
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PI15 = portI + 15
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)
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func (p Pin) getPort() *stm32.GPIO_Type {
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switch p / 16 {
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case 0:
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return stm32.GPIOA
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case 1:
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return stm32.GPIOB
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case 2:
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return stm32.GPIOC
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case 3:
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return stm32.GPIOD
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case 4:
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return stm32.GPIOE
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case 5:
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return stm32.GPIOF
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case 6:
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return stm32.GPIOG
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case 7:
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return stm32.GPIOH
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case 8:
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return stm32.GPIOI
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default:
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panic("machine: unknown port")
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}
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}
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// enableClock enables the clock for this desired GPIO port.
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func (p Pin) enableClock() {
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switch p / 16 {
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case 0:
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stm32.RCC.AHB1ENR.SetBits(stm32.RCC_AHB1ENR_GPIOAEN)
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case 1:
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stm32.RCC.AHB1ENR.SetBits(stm32.RCC_AHB1ENR_GPIOBEN)
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case 2:
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stm32.RCC.AHB1ENR.SetBits(stm32.RCC_AHB1ENR_GPIOCEN)
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case 3:
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stm32.RCC.AHB1ENR.SetBits(stm32.RCC_AHB1ENR_GPIODEN)
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case 4:
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stm32.RCC.AHB1ENR.SetBits(stm32.RCC_AHB1ENR_GPIOEEN)
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case 5:
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stm32.RCC.AHB1ENR.SetBits(stm32.RCC_AHB1ENR_GPIOFEN)
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case 6:
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stm32.RCC.AHB1ENR.SetBits(stm32.RCC_AHB1ENR_GPIOGEN)
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case 7:
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stm32.RCC.AHB1ENR.SetBits(stm32.RCC_AHB1ENR_GPIOHEN)
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case 8:
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stm32.RCC.AHB1ENR.SetBits(stm32.RCC_AHB1ENR_GPIOIEN)
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default:
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panic("machine: unknown port")
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}
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}
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// Enable peripheral clock
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func enableAltFuncClock(bus unsafe.Pointer) {
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switch bus {
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case unsafe.Pointer(stm32.DAC): // DAC interface clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_DACEN)
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case unsafe.Pointer(stm32.PWR): // Power interface clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_PWREN)
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case unsafe.Pointer(stm32.CAN1): // CAN 1 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_CAN1EN)
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case unsafe.Pointer(stm32.I2C3): // I2C3 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_I2C3EN)
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case unsafe.Pointer(stm32.I2C2): // I2C2 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_I2C2EN)
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case unsafe.Pointer(stm32.I2C1): // I2C1 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_I2C1EN)
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case unsafe.Pointer(stm32.UART5): // UART5 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_UART5EN)
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case unsafe.Pointer(stm32.UART4): // UART4 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_UART4EN)
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case unsafe.Pointer(stm32.USART3): // USART3 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_USART3EN)
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case unsafe.Pointer(stm32.USART2): // USART2 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_USART2EN)
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case unsafe.Pointer(stm32.SPI3): // SPI3 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_SPI3EN)
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case unsafe.Pointer(stm32.SPI2): // SPI2 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_SPI2EN)
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case unsafe.Pointer(stm32.WWDG): // Window watchdog clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_WWDGEN)
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case unsafe.Pointer(stm32.TIM14): // TIM14 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM14EN)
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case unsafe.Pointer(stm32.TIM13): // TIM13 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM13EN)
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case unsafe.Pointer(stm32.TIM12): // TIM12 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM12EN)
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case unsafe.Pointer(stm32.TIM7): // TIM7 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM7EN)
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case unsafe.Pointer(stm32.TIM6): // TIM6 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM6EN)
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case unsafe.Pointer(stm32.TIM5): // TIM5 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM5EN)
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case unsafe.Pointer(stm32.TIM4): // TIM4 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM4EN)
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case unsafe.Pointer(stm32.TIM3): // TIM3 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM3EN)
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case unsafe.Pointer(stm32.TIM2): // TIM2 clock enable
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stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_TIM2EN)
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case unsafe.Pointer(stm32.TIM11): // TIM11 clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM11EN)
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case unsafe.Pointer(stm32.TIM10): // TIM10 clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM10EN)
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case unsafe.Pointer(stm32.TIM9): // TIM9 clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM9EN)
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case unsafe.Pointer(stm32.SYSCFG): // System configuration controller clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SYSCFGEN)
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case unsafe.Pointer(stm32.SPI1): // SPI1 clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SPI1EN)
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case unsafe.Pointer(stm32.ADC3): // ADC3 clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_ADC3EN)
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case unsafe.Pointer(stm32.ADC2): // ADC2 clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_ADC2EN)
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case unsafe.Pointer(stm32.ADC1): // ADC1 clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_ADC1EN)
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case unsafe.Pointer(stm32.USART6): // USART6 clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_USART6EN)
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case unsafe.Pointer(stm32.USART1): // USART1 clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_USART1EN)
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case unsafe.Pointer(stm32.TIM8): // TIM8 clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM8EN)
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case unsafe.Pointer(stm32.TIM1): // TIM1 clock enable
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stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_TIM1EN)
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}
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}
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//---------- Timer related code
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var (
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TIM1 = TIM{
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EnableRegister: &stm32.RCC.APB2ENR,
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EnableFlag: stm32.RCC_APB2ENR_TIM1EN,
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Device: stm32.TIM1,
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Channels: [4]TimerChannel{
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TimerChannel{Pins: []PinFunction{
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{PA8, AF1_TIM1_2},
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{PE9, AF1_TIM1_2},
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}},
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TimerChannel{Pins: []PinFunction{
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{PA9, AF1_TIM1_2},
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{PE11, AF1_TIM1_2},
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}},
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TimerChannel{Pins: []PinFunction{
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{PA10, AF1_TIM1_2},
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{PE13, AF1_TIM1_2},
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}},
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TimerChannel{Pins: []PinFunction{
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{PA11, AF1_TIM1_2},
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{PE14, AF1_TIM1_2},
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}},
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},
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busFreq: APB2_TIM_FREQ,
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}
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TIM2 = TIM{
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EnableRegister: &stm32.RCC.APB1ENR,
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EnableFlag: stm32.RCC_APB1ENR_TIM2EN,
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Device: stm32.TIM2,
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Channels: [4]TimerChannel{
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TimerChannel{Pins: []PinFunction{
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{PA0, AF1_TIM1_2},
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{PA5, AF1_TIM1_2},
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{PA15, AF1_TIM1_2},
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}},
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TimerChannel{Pins: []PinFunction{
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{PA1, AF1_TIM1_2},
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{PB3, AF1_TIM1_2},
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}},
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TimerChannel{Pins: []PinFunction{
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{PA2, AF1_TIM1_2},
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{PB10, AF1_TIM1_2},
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}},
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TimerChannel{Pins: []PinFunction{
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{PA3, AF1_TIM1_2},
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{PB11, AF1_TIM1_2},
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}},
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},
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busFreq: APB1_TIM_FREQ,
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}
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TIM3 = TIM{
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EnableRegister: &stm32.RCC.APB1ENR,
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EnableFlag: stm32.RCC_APB1ENR_TIM3EN,
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Device: stm32.TIM3,
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Channels: [4]TimerChannel{
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TimerChannel{Pins: []PinFunction{
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{PA6, AF2_TIM3_4_5},
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{PB4, AF2_TIM3_4_5},
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{PC6, AF2_TIM3_4_5},
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}},
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TimerChannel{Pins: []PinFunction{
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{PA7, AF2_TIM3_4_5},
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{PB5, AF2_TIM3_4_5},
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{PC7, AF2_TIM3_4_5},
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}},
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TimerChannel{Pins: []PinFunction{
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{PB0, AF2_TIM3_4_5},
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{PC8, AF2_TIM3_4_5},
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}},
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TimerChannel{Pins: []PinFunction{
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{PB1, AF2_TIM3_4_5},
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{PC9, AF2_TIM3_4_5},
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}},
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},
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busFreq: APB1_TIM_FREQ,
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}
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TIM4 = TIM{
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EnableRegister: &stm32.RCC.APB1ENR,
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EnableFlag: stm32.RCC_APB1ENR_TIM4EN,
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Device: stm32.TIM4,
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Channels: [4]TimerChannel{
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TimerChannel{Pins: []PinFunction{
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{PB6, AF2_TIM3_4_5},
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{PD12, AF2_TIM3_4_5},
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}},
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TimerChannel{Pins: []PinFunction{
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{PB7, AF2_TIM3_4_5},
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{PD13, AF2_TIM3_4_5},
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}},
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TimerChannel{Pins: []PinFunction{
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{PB8, AF2_TIM3_4_5},
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{PD14, AF2_TIM3_4_5},
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}},
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TimerChannel{Pins: []PinFunction{
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{PB9, AF2_TIM3_4_5},
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{PD15, AF2_TIM3_4_5},
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}},
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},
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busFreq: APB1_TIM_FREQ,
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}
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TIM5 = TIM{
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EnableRegister: &stm32.RCC.APB1ENR,
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EnableFlag: stm32.RCC_APB1ENR_TIM5EN,
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Device: stm32.TIM5,
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Channels: [4]TimerChannel{
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TimerChannel{Pins: []PinFunction{
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{PA0, AF2_TIM3_4_5},
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{PH10, AF2_TIM3_4_5},
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}},
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TimerChannel{Pins: []PinFunction{
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{PA1, AF2_TIM3_4_5},
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{PH11, AF2_TIM3_4_5},
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}},
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TimerChannel{Pins: []PinFunction{
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{PA2, AF2_TIM3_4_5},
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{PH12, AF2_TIM3_4_5},
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}},
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TimerChannel{Pins: []PinFunction{
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{PA3, AF2_TIM3_4_5},
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{PI0, AF2_TIM3_4_5},
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}},
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},
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busFreq: APB1_TIM_FREQ,
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}
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TIM6 = TIM{
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EnableRegister: &stm32.RCC.APB1ENR,
|
|
EnableFlag: stm32.RCC_APB1ENR_TIM6EN,
|
|
Device: stm32.TIM6,
|
|
Channels: [4]TimerChannel{
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
},
|
|
busFreq: APB1_TIM_FREQ,
|
|
}
|
|
|
|
TIM7 = TIM{
|
|
EnableRegister: &stm32.RCC.APB1ENR,
|
|
EnableFlag: stm32.RCC_APB1ENR_TIM7EN,
|
|
Device: stm32.TIM7,
|
|
Channels: [4]TimerChannel{
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
},
|
|
busFreq: APB1_TIM_FREQ,
|
|
}
|
|
|
|
TIM8 = TIM{
|
|
EnableRegister: &stm32.RCC.APB2ENR,
|
|
EnableFlag: stm32.RCC_APB2ENR_TIM8EN,
|
|
Device: stm32.TIM8,
|
|
Channels: [4]TimerChannel{
|
|
TimerChannel{Pins: []PinFunction{
|
|
{PC6, AF3_TIM8_9_10_11_LPTIM1},
|
|
{PI5, AF3_TIM8_9_10_11_LPTIM1},
|
|
}},
|
|
TimerChannel{Pins: []PinFunction{
|
|
{PC7, AF3_TIM8_9_10_11_LPTIM1},
|
|
{PI6, AF3_TIM8_9_10_11_LPTIM1},
|
|
}},
|
|
TimerChannel{Pins: []PinFunction{
|
|
{PC8, AF3_TIM8_9_10_11_LPTIM1},
|
|
{PI7, AF3_TIM8_9_10_11_LPTIM1},
|
|
}},
|
|
TimerChannel{Pins: []PinFunction{
|
|
{PC9, AF3_TIM8_9_10_11_LPTIM1},
|
|
{PI2, AF3_TIM8_9_10_11_LPTIM1},
|
|
}},
|
|
},
|
|
busFreq: APB2_TIM_FREQ,
|
|
}
|
|
|
|
TIM9 = TIM{
|
|
EnableRegister: &stm32.RCC.APB2ENR,
|
|
EnableFlag: stm32.RCC_APB2ENR_TIM9EN,
|
|
Device: stm32.TIM9,
|
|
Channels: [4]TimerChannel{
|
|
TimerChannel{Pins: []PinFunction{
|
|
{PA2, AF3_TIM8_9_10_11_LPTIM1},
|
|
{PE5, AF3_TIM8_9_10_11_LPTIM1},
|
|
}},
|
|
TimerChannel{Pins: []PinFunction{
|
|
{PA3, AF3_TIM8_9_10_11_LPTIM1},
|
|
{PE6, AF3_TIM8_9_10_11_LPTIM1},
|
|
}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
},
|
|
busFreq: APB2_TIM_FREQ,
|
|
}
|
|
|
|
TIM10 = TIM{
|
|
EnableRegister: &stm32.RCC.APB2ENR,
|
|
EnableFlag: stm32.RCC_APB2ENR_TIM10EN,
|
|
Device: stm32.TIM10,
|
|
Channels: [4]TimerChannel{
|
|
TimerChannel{Pins: []PinFunction{
|
|
{PB8, AF3_TIM8_9_10_11_LPTIM1},
|
|
{PF6, AF3_TIM8_9_10_11_LPTIM1},
|
|
}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
},
|
|
busFreq: APB2_TIM_FREQ,
|
|
}
|
|
|
|
TIM11 = TIM{
|
|
EnableRegister: &stm32.RCC.APB2ENR,
|
|
EnableFlag: stm32.RCC_APB2ENR_TIM11EN,
|
|
Device: stm32.TIM11,
|
|
Channels: [4]TimerChannel{
|
|
TimerChannel{Pins: []PinFunction{
|
|
{PB9, AF3_TIM8_9_10_11_LPTIM1},
|
|
{PF7, AF3_TIM8_9_10_11_LPTIM1},
|
|
}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
},
|
|
busFreq: APB2_TIM_FREQ,
|
|
}
|
|
|
|
TIM12 = TIM{
|
|
EnableRegister: &stm32.RCC.APB1ENR,
|
|
EnableFlag: stm32.RCC_APB1ENR_TIM12EN,
|
|
Device: stm32.TIM12,
|
|
Channels: [4]TimerChannel{
|
|
TimerChannel{Pins: []PinFunction{
|
|
{PB14, AF9_CAN1_TIM12_13_14_QUADSPI_FMC_OTG2_HS},
|
|
{PH6, AF9_CAN1_TIM12_13_14_QUADSPI_FMC_OTG2_HS},
|
|
}},
|
|
TimerChannel{Pins: []PinFunction{
|
|
{PB15, AF9_CAN1_TIM12_13_14_QUADSPI_FMC_OTG2_HS},
|
|
{PH9, AF9_CAN1_TIM12_13_14_QUADSPI_FMC_OTG2_HS},
|
|
}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
},
|
|
busFreq: APB1_TIM_FREQ,
|
|
}
|
|
|
|
TIM13 = TIM{
|
|
EnableRegister: &stm32.RCC.APB1ENR,
|
|
EnableFlag: stm32.RCC_APB1ENR_TIM13EN,
|
|
Device: stm32.TIM13,
|
|
Channels: [4]TimerChannel{
|
|
TimerChannel{Pins: []PinFunction{
|
|
{PA6, AF9_CAN1_TIM12_13_14_QUADSPI_FMC_OTG2_HS},
|
|
{PF8, AF9_CAN1_TIM12_13_14_QUADSPI_FMC_OTG2_HS},
|
|
}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
},
|
|
busFreq: APB1_TIM_FREQ,
|
|
}
|
|
|
|
TIM14 = TIM{
|
|
EnableRegister: &stm32.RCC.APB1ENR,
|
|
EnableFlag: stm32.RCC_APB1ENR_TIM14EN,
|
|
Device: stm32.TIM14,
|
|
Channels: [4]TimerChannel{
|
|
TimerChannel{Pins: []PinFunction{
|
|
{PA7, AF9_CAN1_TIM12_13_14_QUADSPI_FMC_OTG2_HS},
|
|
{PF9, AF9_CAN1_TIM12_13_14_QUADSPI_FMC_OTG2_HS},
|
|
}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
TimerChannel{Pins: []PinFunction{}},
|
|
},
|
|
busFreq: APB1_TIM_FREQ,
|
|
}
|
|
)
|
|
|
|
func (t *TIM) registerUPInterrupt() interrupt.Interrupt {
|
|
switch t {
|
|
case &TIM1:
|
|
return interrupt.New(stm32.IRQ_TIM1_UP_TIM10, TIM1.handleUPInterrupt)
|
|
case &TIM2:
|
|
return interrupt.New(stm32.IRQ_TIM2, TIM2.handleUPInterrupt)
|
|
case &TIM3:
|
|
return interrupt.New(stm32.IRQ_TIM3, TIM3.handleUPInterrupt)
|
|
case &TIM4:
|
|
return interrupt.New(stm32.IRQ_TIM4, TIM4.handleUPInterrupt)
|
|
case &TIM5:
|
|
return interrupt.New(stm32.IRQ_TIM5, TIM5.handleUPInterrupt)
|
|
case &TIM6:
|
|
return interrupt.New(stm32.IRQ_TIM6_DAC, TIM6.handleUPInterrupt)
|
|
case &TIM7:
|
|
return interrupt.New(stm32.IRQ_TIM7, TIM7.handleUPInterrupt)
|
|
case &TIM8:
|
|
return interrupt.New(stm32.IRQ_TIM8_UP_TIM13, TIM8.handleUPInterrupt)
|
|
case &TIM9:
|
|
return interrupt.New(stm32.IRQ_TIM1_BRK_TIM9, TIM9.handleUPInterrupt)
|
|
case &TIM10:
|
|
return interrupt.New(stm32.IRQ_TIM1_UP_TIM10, TIM10.handleUPInterrupt)
|
|
case &TIM11:
|
|
return interrupt.New(stm32.IRQ_TIM1_TRG_COM_TIM11, TIM11.handleUPInterrupt)
|
|
case &TIM12:
|
|
return interrupt.New(stm32.IRQ_TIM8_BRK_TIM12, TIM12.handleUPInterrupt)
|
|
case &TIM13:
|
|
return interrupt.New(stm32.IRQ_TIM8_UP_TIM13, TIM13.handleUPInterrupt)
|
|
case &TIM14:
|
|
return interrupt.New(stm32.IRQ_TIM8_TRG_COM_TIM14, TIM14.handleUPInterrupt)
|
|
}
|
|
|
|
return interrupt.Interrupt{}
|
|
}
|
|
|
|
func (t *TIM) registerOCInterrupt() interrupt.Interrupt {
|
|
switch t {
|
|
case &TIM1:
|
|
return interrupt.New(stm32.IRQ_TIM1_CC, TIM1.handleUPInterrupt)
|
|
case &TIM2:
|
|
return interrupt.New(stm32.IRQ_TIM2, TIM2.handleOCInterrupt)
|
|
case &TIM3:
|
|
return interrupt.New(stm32.IRQ_TIM3, TIM3.handleOCInterrupt)
|
|
case &TIM4:
|
|
return interrupt.New(stm32.IRQ_TIM4, TIM4.handleOCInterrupt)
|
|
case &TIM5:
|
|
return interrupt.New(stm32.IRQ_TIM5, TIM5.handleOCInterrupt)
|
|
case &TIM6:
|
|
return interrupt.New(stm32.IRQ_TIM6_DAC, TIM6.handleOCInterrupt)
|
|
case &TIM7:
|
|
return interrupt.New(stm32.IRQ_TIM7, TIM7.handleOCInterrupt)
|
|
case &TIM8:
|
|
return interrupt.New(stm32.IRQ_TIM8_CC, TIM8.handleOCInterrupt)
|
|
case &TIM9:
|
|
return interrupt.New(stm32.IRQ_TIM1_BRK_TIM9, TIM9.handleOCInterrupt)
|
|
case &TIM10:
|
|
return interrupt.New(stm32.IRQ_TIM1_UP_TIM10, TIM10.handleOCInterrupt)
|
|
case &TIM11:
|
|
return interrupt.New(stm32.IRQ_TIM1_TRG_COM_TIM11, TIM11.handleOCInterrupt)
|
|
case &TIM12:
|
|
return interrupt.New(stm32.IRQ_TIM8_BRK_TIM12, TIM12.handleOCInterrupt)
|
|
case &TIM13:
|
|
return interrupt.New(stm32.IRQ_TIM8_UP_TIM13, TIM13.handleOCInterrupt)
|
|
case &TIM14:
|
|
return interrupt.New(stm32.IRQ_TIM8_TRG_COM_TIM14, TIM14.handleOCInterrupt)
|
|
}
|
|
|
|
return interrupt.Interrupt{}
|
|
}
|
|
|
|
func (t *TIM) enableMainOutput() {
|
|
t.Device.BDTR.SetBits(stm32.TIM_BDTR_MOE)
|
|
}
|
|
|
|
type arrtype = uint32
|
|
type arrRegType = volatile.Register32
|
|
|
|
const (
|
|
ARR_MAX = 0x10000
|
|
PSC_MAX = 0x10000
|
|
)
|